Initial upload: Catalyst N1 open source neuromorphic processor RTL

.gitignore

@@ -0,0 +1,65 @@
+# Compiled Verilog
+*.vvp
+*.out
+
+# Waveform dumps
+*.vcd
+
+# Simulation directories and binaries
+sim/
+sim_async
+sim_stress
+
+# Synthesis outputs
+synth/
+
+# Windows artifacts
+nul
+
+# Python
+__pycache__/
+*.pyc
+*.pyo
+*.egg-info/
+.pytest_cache/
+
+# Datasets (large, download separately)
+sdk/benchmarks/data/
+sdk/data/
+
+# Model checkpoints
+*.pt
+
+# Build archives
+upload.zip
+
+# Generated images (keep architecture.png)
+spike_visualization.png
+sdk/neurocore_dashboard.png
+sdk/async_dashboard.png
+sdk/p13_dashboard.png
+sdk/raster_demo.png
+sdk/results/
+
+# FPGA build artifacts
+fpga/f2/*.tar
+
+# Editor/IDE
+.vscode/
+*.swp
+*.swo
+*~
+
+# Vivado
+*.jou
+*.log
+*.str
+.Xil/
+
+# LaTeX build artifacts
+paper/*.aux
+paper/*.bbl
+paper/*.blg
+paper/*.fdb_latexmk
+paper/*.fls
+paper/*.synctex.gz

LICENSE

@@ -0,0 +1,190 @@
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+   Copyright 2026 Henry Arthur Shulayev Barnes / Catalyst Neuromorphic Ltd
+
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+   limitations under the License.

Makefile

@@ -0,0 +1,35 @@
+# Neuromorphic Chip - Build & Simulation Makefile
+# Usage:
+#   make sim      - Compile and run simulation
+#   make waves    - Open waveform viewer
+#   make synth    - Synthesize with Yosys (gate-level)
+#   make clean    - Clean build artifacts
+
+# Source files
+RTL_DIR = rtl
+TB_DIR  = tb
+SIM_DIR = sim
+
+RTL_SRC = $(RTL_DIR)/lif_neuron.v $(RTL_DIR)/synapse.v $(RTL_DIR)/neuron_core.v
+TB_SRC  = $(TB_DIR)/tb_neuron_core.v
+
+# Simulation
+SIM_OUT = $(SIM_DIR)/neuron_core_sim
+VCD_OUT = $(SIM_DIR)/neuron_core.vcd
+
+.PHONY: sim waves synth clean
+
+sim: $(RTL_SRC) $(TB_SRC)
+	@mkdir -p $(SIM_DIR)
+	iverilog -o $(SIM_OUT) -I $(RTL_DIR) $(RTL_SRC) $(TB_SRC)
+	cd $(SIM_DIR) && vvp ../$(SIM_OUT)
+
+waves: $(VCD_OUT)
+	gtkwave $(VCD_OUT) &
+
+synth:
+	@mkdir -p synth
+	yosys -p "read_verilog $(RTL_SRC); synth -top neuron_core; stat; write_json synth/neuron_core.json" 2>&1 | tail -30
+
+clean:
+	rm -rf $(SIM_DIR)/*.vcd $(SIM_DIR)/neuron_core_sim synth/*.json

NOTICE

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+Catalyst N1 Neuromorphic Processor
+Copyright 2026 Henry Arthur Shulayev Barnes / Catalyst Neuromorphic Ltd
+Company No. 17054540
+
+This product includes hardware description language (HDL) designs
+originally developed by Henry Arthur Shulayev Barnes.
+
+UK Patent Application No. 2602902.6 (filed 13 February 2026)

README.md

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+---
+license: apache-2.0
+tags:
+  - neuromorphic
+  - spiking-neural-networks
+  - fpga
+  - verilog
+  - hardware
+  - edge-ai
+  - loihi
+  - rtl
+  - noc
+  - stdp
+language:
+  - en
+library_name: neurocore
+pipeline_tag: other
+---
+
+# Catalyst N1
+
+Open source 128-core neuromorphic processor with full mesh NoC, STDP learning, and RISC-V management. Verilog RTL, validated on FPGA.
+
+## Specifications
+
+| Parameter | Value |
+|-----------|-------|
+| Cores | 128 |
+| Neurons per core | 1,024 |
+| Total neurons | 131,072 |
+| Neuron model | Leaky Integrate-and-Fire (16-bit fixed-point) |
+| Synapse pool | 131,072 entries per core |
+| Learning | STDP, 14-opcode programmable learning ISA |
+| Network-on-Chip | Configurable XY mesh with multicast |
+| Host interface | UART (FPGA) / AXI-Lite (F2) / PCIe MMIO |
+| Management | RV32IM RISC-V cluster |
+| Multi-chip | Chip link with routing table |
+| Clock | 100 MHz (simulation default) |
+
+## Directory Structure
+
+```
+catalyst-n1/
+  rtl/           25 Verilog modules (core, NoC, memory, host, RISC-V)
+  tb/            46 testbenches (unit, integration, regression)
+  sdk/           Python SDK with CPU, GPU, and FPGA backends
+  fpga/          FPGA build files (Arty A7, AWS F2, Kria K26)
+  sim/           Simulation scripts and visualization
+  Makefile       Compile and run simulation
+```
+
+## Simulation
+
+Requires [Icarus Verilog](https://github.com/steveicarus/iverilog) (v12+).
+
+```bash
+# Compile and run basic simulation
+make sim
+
+# Run full regression (25 testbenches)
+bash run_regression.sh
+
+# Run a single testbench
+iverilog -g2012 -DSIMULATION -o out.vvp \
+  rtl/sram.v rtl/spike_fifo.v rtl/uart_tx.v rtl/uart_rx.v \
+  rtl/scalable_core_v2.v rtl/neuromorphic_mesh.v \
+  rtl/host_interface.v rtl/neuromorphic_top.v rtl/sync_tree.v \
+  rtl/rv32i_core.v rtl/mmio_bridge.v rtl/rv32im_cluster.v \
+  tb/tb_p24_final.v
+vvp out.vvp
+
+# View waveforms (requires GTKWave)
+make waves
+```
+
+## SDK
+
+Python SDK for building, simulating, and deploying spiking neural networks. See [`sdk/README.md`](sdk/README.md) for full documentation.
+
+```bash
+cd sdk
+pip install -e .
+```
+
+```python
+import neurocore as nc
+
+net = nc.Network()
+inp = net.population(100, params={'threshold': 1000, 'leak': 10}, label='input')
+hid = net.population(50, params={'threshold': 1000, 'leak': 5}, label='hidden')
+out = net.population(10, params={'threshold': 1000, 'leak': 5}, label='output')
+
+net.connect(inp, hid, weight=500, probability=0.3)
+net.connect(hid, out, weight=400, probability=0.5)
+
+sim = nc.Simulator()
+sim.deploy(net)
+
+for t in range(100):
+    sim.inject(inp, neuron_ids=[0, 5, 10], current=1500)
+    sim.step()
+
+result = sim.get_result()
+result.raster_plot(show=True)
+```
+
+Four backends: CPU simulator, GPU simulator (PyTorch CUDA), FPGA via UART (Arty A7), AWS F2 via PCIe. All share the same API.
+
+## FPGA
+
+### Arty A7
+
+```bash
+# Vivado batch build
+vivado -mode batch -source fpga/build_vivado.tcl
+```
+
+Constraints: `fpga/arty_a7.xdc`. Top module: `fpga/fpga_top.v`.
+
+### AWS F2
+
+```bash
+# Build on F2 build instance
+cd fpga/f2
+bash run_build.sh
+```
+
+CL wrapper: `fpga/f2/cl_neuromorphic.sv`. Host driver: `fpga/f2_host.py`.
+
+### Kria K26
+
+```bash
+vivado -mode batch -source fpga/kria/build_kria.tcl
+```
+
+Wrapper: `fpga/kria/kria_neuromorphic.v`.
+
+## Benchmarks
+
+SHD (Spiking Heidelberg Digits) spoken digit classification:
+
+```bash
+cd sdk
+python benchmarks/shd_train.py --data-dir benchmarks/data/shd --epochs 200
+python benchmarks/shd_deploy.py --checkpoint benchmarks/shd_model.pt --data-dir benchmarks/data/shd
+```
+
+Additional benchmarks in `sdk/benchmarks/`: DVS gesture recognition, XOR classification, temporal patterns, scaling, stress tests.
+
+## Links
+
+- [GitHub Repository](https://github.com/catalyst-neuromorphic/catalyst-n1)
+- [catalyst-neuromorphic.com](https://catalyst-neuromorphic.com)
+- [Cloud API](https://github.com/catalyst-neuromorphic/catalyst-cloud-python)
+- [Catalyst-Neurocore](https://github.com/catalyst-neuromorphic/catalyst-neurocore)
+
+## License
+
+Apache 2.0. See [LICENSE](LICENSE).

fpga/arty_a7.xdc

@@ -0,0 +1,33 @@
+## ============================================================================
+## Arty A7-100T Pin Constraints
+## ============================================================================
+
+## System Clock (100 MHz)
+set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports {clk}]
+create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk}]
+
+## Reset (BTN0, active-high)
+set_property -dict { PACKAGE_PIN D9    IOSTANDARD LVCMOS33 } [get_ports {btn_rst}]
+
+## UART
+set_property -dict { PACKAGE_PIN A9    IOSTANDARD LVCMOS33 } [get_ports {uart_rxd}]
+set_property -dict { PACKAGE_PIN D10   IOSTANDARD LVCMOS33 } [get_ports {uart_txd}]
+
+## Status LEDs
+set_property -dict { PACKAGE_PIN H5    IOSTANDARD LVCMOS33 } [get_ports {led[0]}]
+set_property -dict { PACKAGE_PIN J5    IOSTANDARD LVCMOS33 } [get_ports {led[1]}]
+set_property -dict { PACKAGE_PIN T9    IOSTANDARD LVCMOS33 } [get_ports {led[2]}]
+set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS33 } [get_ports {led[3]}]
+
+## RGB LEDs (unused)
+#set_property -dict { PACKAGE_PIN F6    IOSTANDARD LVCMOS33 } [get_ports {led_r[0]}]
+#set_property -dict { PACKAGE_PIN J4    IOSTANDARD LVCMOS33 } [get_ports {led_g[0]}]
+#set_property -dict { PACKAGE_PIN J2    IOSTANDARD LVCMOS33 } [get_ports {led_b[0]}]
+
+## Configuration
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property CFGBVS VCCO [current_design]
+
+## Bitstream
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]

fpga/build_vivado.tcl

@@ -0,0 +1,107 @@
+# ============================================================================
+# Vivado Non-Project Mode Build Script
+# ============================================================================
+# Target: Arty A7-100T (xc7a100tcsg324-1)
+# Usage:  vivado -mode batch -source fpga/build_vivado.tcl
+# ============================================================================
+
+# ---- Configuration ----
+set part        "xc7a100tcsg324-1"
+set top         "fpga_top"
+set build_dir   "fpga/build"
+set bit_file    "${build_dir}/neuromorphic.bit"
+
+# ---- Create build directory ----
+file mkdir $build_dir
+
+# ---- Read RTL sources ----
+read_verilog {
+    rtl/sram.v
+    rtl/spike_fifo.v
+    rtl/uart_tx.v
+    rtl/uart_rx.v
+    rtl/scalable_core_v2.v
+    rtl/neuromorphic_mesh.v
+    rtl/async_noc_mesh.v
+    rtl/async_router.v
+    rtl/sync_tree.v
+    rtl/chip_link.v
+    rtl/host_interface.v
+    rtl/neuromorphic_top.v
+    fpga/fpga_top.v
+}
+
+# ---- Read constraints ----
+read_xdc fpga/arty_a7.xdc
+
+# ---- Synthesis ----
+puts "========================================"
+puts "  SYNTHESIS"
+puts "========================================"
+synth_design -top $top -part $part \
+    -flatten_hierarchy rebuilt \
+    -directive Default
+
+# Report utilization after synthesis
+report_utilization -file ${build_dir}/synth_utilization.rpt
+report_timing_summary -file ${build_dir}/synth_timing.rpt
+
+# ---- Optimization ----
+puts "========================================"
+puts "  OPTIMIZATION"
+puts "========================================"
+opt_design
+
+# ---- Placement ----
+puts "========================================"
+puts "  PLACEMENT"
+puts "========================================"
+place_design -directive Explore
+
+# Report utilization after placement
+report_utilization -file ${build_dir}/place_utilization.rpt
+
+# ---- Routing ----
+puts "========================================"
+puts "  ROUTING"
+puts "========================================"
+route_design -directive Explore
+
+# ---- Reports ----
+puts "========================================"
+puts "  REPORTS"
+puts "========================================"
+report_utilization -file ${build_dir}/route_utilization.rpt
+report_timing_summary -file ${build_dir}/route_timing.rpt -max_paths 10
+report_power -file ${build_dir}/power.rpt
+report_drc -file ${build_dir}/drc.rpt
+report_methodology -file ${build_dir}/methodology.rpt
+
+# Check timing
+set timing_slack [get_property SLACK [get_timing_paths -max_paths 1]]
+puts "Worst slack: ${timing_slack} ns"
+if {$timing_slack < 0} {
+    puts "WARNING: Timing not met! Worst negative slack: ${timing_slack} ns"
+}
+
+# ---- Generate Bitstream ----
+puts "========================================"
+puts "  BITSTREAM"
+puts "========================================"
+write_bitstream -force $bit_file
+
+# ---- Summary ----
+puts ""
+puts "========================================"
+puts "  BUILD COMPLETE"
+puts "========================================"
+puts "  Bitstream: $bit_file"
+puts "  Reports:   ${build_dir}/"
+puts ""
+puts "  To program the FPGA:"
+puts "    open_hw_manager"
+puts "    connect_hw_server"
+puts "    open_hw_target"
+puts "    set_property PROGRAM.FILE {${bit_file}} [current_hw_device]"
+puts "    program_hw_devices"
+puts "========================================"

fpga/extract_power.py

@@ -0,0 +1,171 @@
+"""Extract power and utilization numbers from Vivado reports.
+
+Parses post-implementation reports and outputs structured data
+for the paper's resource and power tables.
+
+Usage (on build instance):
+    # After opening DCP in Vivado and generating reports:
+    python extract_power.py power_report.rpt utilization_report.rpt
+
+Usage (manual entry from existing numbers):
+    python extract_power.py --manual
+"""
+
+import argparse
+import re
+import sys
+
+
+def parse_power_report(path):
+    """Parse Vivado report_power output."""
+    data = {}
+    with open(path, 'r') as f:
+        for line in f:
+            # Total On-Chip Power (W)  : X.XXX
+            m = re.search(r'Total On-Chip Power.*?:\s+([\d.]+)', line)
+            if m:
+                data['total_power_w'] = float(m.group(1))
+
+            # Dynamic (W)  : X.XXX
+            m = re.search(r'Dynamic.*?:\s+([\d.]+)', line)
+            if m and 'dynamic_power_w' not in data:
+                data['dynamic_power_w'] = float(m.group(1))
+
+            # Device Static (W) : X.XXX
+            m = re.search(r'Device Static.*?:\s+([\d.]+)', line)
+            if m:
+                data['static_power_w'] = float(m.group(1))
+
+            # Block RAM : X.XXX
+            m = re.search(r'Block RAM\s*:\s+([\d.]+)', line)
+            if m:
+                data['bram_power_w'] = float(m.group(1))
+
+            # Clocks : X.XXX
+            m = re.search(r'Clocks\s*:\s+([\d.]+)', line)
+            if m:
+                data['clock_power_w'] = float(m.group(1))
+
+            # Logic : X.XXX
+            m = re.search(r'Logic\s*:\s+([\d.]+)', line)
+            if m and 'logic_power_w' not in data:
+                data['logic_power_w'] = float(m.group(1))
+
+    return data
+
+
+def parse_utilization_report(path):
+    """Parse Vivado report_utilization output."""
+    data = {}
+    with open(path, 'r') as f:
+        content = f.read()
+
+    # Look for: | Slice LUTs | XXXXX | XXXXX | XX.XX |
+    m = re.search(r'Slice LUTs\*?\s*\|\s*([\d,]+)\s*\|\s*([\d,]+)', content)
+    if m:
+        data['luts_used'] = int(m.group(1).replace(',', ''))
+        data['luts_total'] = int(m.group(2).replace(',', ''))
+
+    # Slice Registers / FFs
+    m = re.search(r'(?:Slice Registers|Register as Flip Flop)\s*\|\s*([\d,]+)\s*\|\s*([\d,]+)', content)
+    if m:
+        data['ffs_used'] = int(m.group(1).replace(',', ''))
+        data['ffs_total'] = int(m.group(2).replace(',', ''))
+
+    # Block RAM Tile
+    m = re.search(r'Block RAM Tile\s*\|\s*([\d.]+)\s*\|\s*([\d.]+)', content)
+    if m:
+        data['bram_used'] = float(m.group(1))
+        data['bram_total'] = float(m.group(2))
+
+    # DSPs
+    m = re.search(r'DSPs?\s*\|\s*([\d]+)\s*\|\s*([\d]+)', content)
+    if m:
+        data['dsps_used'] = int(m.group(1))
+        data['dsps_total'] = int(m.group(2))
+
+    return data
+
+
+def manual_entry():
+    """Known numbers from the F2 build (16 cores, 62.5MHz)."""
+    return {
+        # From f2_deployment.md and build logs
+        'target': 'Xilinx VU47P (xcvu47p, AWS F2)',
+        'cores': 16,
+        'neurons_per_core': 1024,
+        'total_neurons': 16384,
+        'clock_mhz': 62.5,
+        'bram36k_used': 1999,
+        'bram36k_total': 3576,
+        'bram_pct': 55.9,
+        'wns_ns': 0.003,
+        'throughput_ts_per_sec': 8690,
+        # ASIC estimate: FPGA dynamic / 15x (typical FPGA-to-ASIC ratio)
+        'asic_estimate_note': 'FPGA power / 10-20x for ASIC estimate',
+    }
+
+
+def print_paper_table(power, util, manual):
+    """Print formatted table for paper.tex."""
+    print("\n" + "=" * 60)
+    print("RESOURCE UTILIZATION (for paper Table)")
+    print("=" * 60)
+    print(f"Target:          {manual['target']}")
+    print(f"Cores:           {manual['cores']}")
+    print(f"Neurons:         {manual['total_neurons']:,}")
+    print(f"Clock:           {manual['clock_mhz']} MHz")
+    print(f"WNS:             +{manual['wns_ns']} ns (timing MET)")
+    print(f"BRAM36K:         {manual['bram36k_used']} / {manual['bram36k_total']} "
+          f"({manual['bram_pct']:.1f}%)")
+
+    if util:
+        if 'luts_used' in util:
+            lut_pct = 100 * util['luts_used'] / util['luts_total']
+            print(f"LUTs:            {util['luts_used']:,} / {util['luts_total']:,} "
+                  f"({lut_pct:.1f}%)")
+        if 'ffs_used' in util:
+            ff_pct = 100 * util['ffs_used'] / util['ffs_total']
+            print(f"Flip-Flops:      {util['ffs_used']:,} / {util['ffs_total']:,} "
+                  f"({ff_pct:.1f}%)")
+        if 'dsps_used' in util:
+            print(f"DSPs:            {util['dsps_used']} / {util['dsps_total']}")
+
+    print(f"\nThroughput:      {manual['throughput_ts_per_sec']:,} timesteps/sec")
+
+    if power:
+        print(f"\n{'='*60}")
+        print("POWER (from Vivado report_power)")
+        print(f"{'='*60}")
+        for k, v in sorted(power.items()):
+            print(f"  {k}: {v:.3f} W")
+
+        if 'dynamic_power_w' in power:
+            asic_lo = power['dynamic_power_w'] / 20
+            asic_hi = power['dynamic_power_w'] / 10
+            print(f"\nASIC estimate: {asic_lo*1000:.0f} - {asic_hi*1000:.0f} mW "
+                  f"(FPGA dynamic / 10-20x)")
+
+
+def main():
+    parser = argparse.ArgumentParser(description="Extract Vivado power/utilization")
+    parser.add_argument("power_report", nargs='?', help="Vivado power report file")
+    parser.add_argument("util_report", nargs='?', help="Vivado utilization report file")
+    parser.add_argument("--manual", action="store_true",
+                        help="Use known F2 build numbers")
+    args = parser.parse_args()
+
+    manual = manual_entry()
+    power = {}
+    util = {}
+
+    if args.power_report:
+        power = parse_power_report(args.power_report)
+    if args.util_report:
+        util = parse_utilization_report(args.util_report)
+
+    print_paper_table(power, util, manual)
+
+
+if __name__ == "__main__":
+    main()

fpga/f2/build_f2.tcl

@@ -0,0 +1,55 @@
+# ============================================================================
+# F2 Build Script — Source File List
+# ============================================================================
+#
+# This script is sourced by the AWS HDK build flow.
+# It adds our CL design sources to the Vivado project.
+#
+# Usage (within HDK environment):
+#   source $CL_DIR/build/scripts/aws_build_dcp_from_cl.tcl
+#
+# The HDK flow expects CL sources in $CL_DIR/design/
+# Copy all .v files there before running the build.
+# ============================================================================
+
+# ---- CL wrapper + bridge ----
+set cl_design_files [list \
+    $CL_DIR/design/cl_neuromorphic_defines.vh \
+    $CL_DIR/design/cl_neuromorphic.v \
+    $CL_DIR/design/axi_uart_bridge.v \
+]
+
+# ---- Neuromorphic RTL ----
+set neuro_rtl_files [list \
+    $CL_DIR/design/sram.v \
+    $CL_DIR/design/spike_fifo.v \
+    $CL_DIR/design/scalable_core_v2.v \
+    $CL_DIR/design/neuromorphic_mesh.v \
+    $CL_DIR/design/async_noc_mesh.v \
+    $CL_DIR/design/async_router.v \
+    $CL_DIR/design/sync_tree.v \
+    $CL_DIR/design/chip_link.v \
+    $CL_DIR/design/host_interface.v \
+    $CL_DIR/design/neuromorphic_top.v \
+    $CL_DIR/design/rv32i_core.v \
+    $CL_DIR/design/rv32im_cluster.v \
+    $CL_DIR/design/mmio_bridge.v \
+    $CL_DIR/design/multi_chip_router.v \
+]
+
+# Note: uart_rx.v and uart_tx.v are NOT needed (BYPASS_UART=1).
+# They would be optimized away anyway, but omitting them prevents
+# Vivado lint warnings about unconnected modules.
+
+# ---- Add all sources ----
+foreach f [concat $cl_design_files $neuro_rtl_files] {
+    if {[file exists $f]} {
+        read_verilog $f
+    } else {
+        puts "WARNING: File not found: $f"
+    }
+}
+
+# ---- Include path for defines ----
+set_property verilog_define {} [current_fileset]
+set_property include_dirs [list $CL_DIR/design] [current_fileset]

fpga/f2/cl_id_defines.vh

@@ -0,0 +1,25 @@
+// ============================================================================
+// Copyright 2026 Henry Arthur Shulayev Barnes / Catalyst Neuromorphic Ltd
+// Company No. 17054540 — UK Patent Application No. 2602902.6
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// ============================================================================
+
+// CL Neuromorphic — PCIe ID defines
+`ifndef CL_NEUROMORPHIC_DEFINES_VH
+`define CL_NEUROMORPHIC_DEFINES_VH
+
+`define CL_SH_ID0 32'hF230_1D0F  // F230=neuromorphic, 1D0F=Amazon
+`define CL_SH_ID1 32'h0010_1D0F  // 0010=16-core
+
+`endif

fpga/f2/cl_neuromorphic.sv

@@ -0,0 +1,249 @@
+// ============================================================================
+// CL Neuromorphic — AWS F2 FPGA Top-Level Custom Logic Wrapper
+// Neuromorphic Chip v2.3 (16 cores x 1024 neurons) via PCIe MMIO
+// MMCME4 generates 62.5 MHz for neuromorphic logic (CDC via async FIFOs)
+// ============================================================================
+//
+// Copyright 2026 Henry Arthur Shulayev Barnes / Catalyst Neuromorphic Ltd
+// Company No. 17054540 — UK Patent Application No. 2602902.6
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// ============================================================================
+
+module cl_neuromorphic
+    #(
+      parameter EN_DDR = 0,
+      parameter EN_HBM = 0
+    )
+    (
+      `include "cl_ports.vh"
+    );
+
+`include "cl_neuromorphic_defines.vh"
+
+//=============================================================================
+// Reset synchronizer (AXI clock domain)
+//=============================================================================
+  logic rst_main_n_sync;
+  always_ff @(negedge rst_main_n or posedge clk_main_a0)
+    if (!rst_main_n) rst_main_n_sync <= 1'b0;
+    else             rst_main_n_sync <= 1'b1;
+
+//=============================================================================
+// MMCME4: Generate 62.5 MHz neuromorphic clock from 250 MHz
+//=============================================================================
+// VCO = 250 MHz * 4.0 = 1000 MHz
+// CLKOUT0 = 1000 MHz / 16.0 = 62.5 MHz
+  wire clk_neuro_unbuf;
+  wire clk_neuro;
+  wire mmcm_fb;
+  wire mmcm_locked;
+
+  MMCME4_BASE #(
+      .CLKIN1_PERIOD   (4.000),   // 250 MHz input
+      .CLKFBOUT_MULT_F (4.000),   // VCO = 1000 MHz
+      .CLKOUT0_DIVIDE_F(16.000),  // 62.5 MHz output
+      .CLKOUT0_PHASE   (0.000),
+      .DIVCLK_DIVIDE   (1)
+  ) u_mmcm (
+      .CLKIN1   (clk_main_a0),
+      .CLKFBOUT (mmcm_fb),
+      .CLKFBIN  (mmcm_fb),
+      .CLKOUT0  (clk_neuro_unbuf),
+      .CLKOUT0B (),
+      .CLKOUT1  (),
+      .CLKOUT1B (),
+      .CLKOUT2  (),
+      .CLKOUT2B (),
+      .CLKOUT3  (),
+      .CLKOUT3B (),
+      .CLKOUT4  (),
+      .CLKOUT5  (),
+      .CLKOUT6  (),
+      .LOCKED   (mmcm_locked),
+      .PWRDWN   (1'b0),
+      .RST      (~rst_main_n)
+  );
+
+  BUFG u_bufg_neuro (.I(clk_neuro_unbuf), .O(clk_neuro));
+
+//=============================================================================
+// Reset synchronizer (neuro clock domain)
+//=============================================================================
+  logic rst_neuro_n_sync;
+  logic rst_neuro_n_pipe;
+  always_ff @(negedge mmcm_locked or posedge clk_neuro)
+    if (!mmcm_locked) begin
+      rst_neuro_n_pipe <= 1'b0;
+      rst_neuro_n_sync <= 1'b0;
+    end else begin
+      rst_neuro_n_pipe <= rst_main_n;
+      rst_neuro_n_sync <= rst_neuro_n_pipe;
+    end
+
+//=============================================================================
+// GLOBALS
+//=============================================================================
+  assign cl_sh_flr_done    = 1'b1;
+  assign cl_sh_status0     = {31'b0, mmcm_locked};
+  assign cl_sh_status1     = 32'b0;
+  assign cl_sh_status2     = 32'b0;
+  assign cl_sh_id0         = `CL_SH_ID0;
+  assign cl_sh_id1         = `CL_SH_ID1;
+  assign cl_sh_status_vled = {15'b0, mmcm_locked};
+
+//=============================================================================
+// Unused interfaces — tie off with standard AWS templates
+//=============================================================================
+
+  // PCIM (CL-initiated DMA master) — unused
+  `include "unused_pcim_template.inc"
+
+  // PCIS (Host DMA slave) — unused
+  `include "unused_dma_pcis_template.inc"
+
+  // SDA (Management AXI-Lite BAR) — unused
+  `include "unused_cl_sda_template.inc"
+
+  // DDR4 — unused but sh_ddr required for pin connections
+  `include "unused_ddr_template.inc"
+
+  // Interrupts — unused
+  `include "unused_apppf_irq_template.inc"
+
+//=============================================================================
+// JTAG — unused
+//=============================================================================
+  assign tdo = 1'b0;
+
+//=============================================================================
+// HBM Monitor — unused
+//=============================================================================
+  assign hbm_apb_paddr_1   = 22'b0;
+  assign hbm_apb_pprot_1   = 3'b0;
+  assign hbm_apb_psel_1    = 1'b0;
+  assign hbm_apb_penable_1 = 1'b0;
+  assign hbm_apb_pwrite_1  = 1'b0;
+  assign hbm_apb_pwdata_1  = 32'b0;
+  assign hbm_apb_pstrb_1   = 4'b0;
+  assign hbm_apb_pready_1  = 1'b0;
+  assign hbm_apb_prdata_1  = 32'b0;
+  assign hbm_apb_pslverr_1 = 1'b0;
+
+  assign hbm_apb_paddr_0   = 22'b0;
+  assign hbm_apb_pprot_0   = 3'b0;
+  assign hbm_apb_psel_0    = 1'b0;
+  assign hbm_apb_penable_0 = 1'b0;
+  assign hbm_apb_pwrite_0  = 1'b0;
+  assign hbm_apb_pwdata_0  = 32'b0;
+  assign hbm_apb_pstrb_0   = 4'b0;
+  assign hbm_apb_pready_0  = 1'b0;
+  assign hbm_apb_prdata_0  = 32'b0;
+  assign hbm_apb_pslverr_0 = 1'b0;
+
+//=============================================================================
+// PCIe EP/RP — unused
+//=============================================================================
+  assign PCIE_EP_TXP    = 8'b0;
+  assign PCIE_EP_TXN    = 8'b0;
+  assign PCIE_RP_PERSTN = 1'b0;
+  assign PCIE_RP_TXP    = 8'b0;
+  assign PCIE_RP_TXN    = 8'b0;
+
+//=============================================================================
+// OCL AXI-Lite -> AXI-UART Bridge -> Neuromorphic Top
+//=============================================================================
+
+  // Bridge <-> neuromorphic_top byte-stream wires
+  wire [7:0]  bridge_rx_data;
+  wire        bridge_rx_valid;
+  wire [7:0]  bridge_tx_data;
+  wire        bridge_tx_valid;
+  wire        bridge_tx_ready;
+
+  axi_uart_bridge #(
+      .VERSION_ID (32'hF2_02_03_10),  // F2, v2.3, 16-core
+      .NUM_CORES  (16)
+  ) u_bridge (
+      .clk          (clk_main_a0),
+      .rst_n        (rst_main_n_sync),
+      .clk_neuro    (clk_neuro),
+      .rst_neuro_n  (rst_neuro_n_sync),
+
+      // AXI-Lite slave (OCL BAR0)
+      .s_axi_awaddr (ocl_cl_awaddr),
+      .s_axi_awvalid(ocl_cl_awvalid),
+      .s_axi_awready(cl_ocl_awready),
+      .s_axi_wdata  (ocl_cl_wdata),
+      .s_axi_wstrb  (ocl_cl_wstrb),
+      .s_axi_wvalid (ocl_cl_wvalid),
+      .s_axi_wready (cl_ocl_wready),
+      .s_axi_bresp  (cl_ocl_bresp),
+      .s_axi_bvalid (cl_ocl_bvalid),
+      .s_axi_bready (ocl_cl_bready),
+      .s_axi_araddr (ocl_cl_araddr),
+      .s_axi_arvalid(ocl_cl_arvalid),
+      .s_axi_arready(cl_ocl_arready),
+      .s_axi_rdata  (cl_ocl_rdata),
+      .s_axi_rresp  (cl_ocl_rresp),
+      .s_axi_rvalid (cl_ocl_rvalid),
+      .s_axi_rready (ocl_cl_rready),
+
+      // Byte-stream to neuromorphic_top (clk_neuro domain)
+      .hi_rx_data   (bridge_rx_data),
+      .hi_rx_valid  (bridge_rx_valid),
+      .hi_tx_data   (bridge_tx_data),
+      .hi_tx_valid  (bridge_tx_valid),
+      .hi_tx_ready  (bridge_tx_ready)
+  );
+
+  neuromorphic_top #(
+      .CLK_FREQ       (62_500_000),
+      .BAUD           (115200),
+      .BYPASS_UART    (1),
+      .NUM_CORES      (16),
+      .CORE_ID_BITS   (4),
+      .NUM_NEURONS    (1024),
+      .NEURON_BITS    (10),
+      .POOL_DEPTH     (4096),
+      .POOL_ADDR_BITS (12),
+      .COUNT_BITS     (12),
+      .CHIP_LINK_EN   (0),
+      .NOC_MODE       (0),
+      .MESH_X         (4),
+      .MESH_Y         (4)
+  ) u_neuromorphic (
+      .clk            (clk_neuro),
+      .rst_n          (rst_neuro_n_sync),
+
+      // UART unused (BYPASS_UART=1)
+      .uart_rxd       (1'b1),
+      .uart_txd       (),
+
+      // Byte-stream from AXI bridge (clk_neuro domain)
+      .rx_data_ext    (bridge_rx_data),
+      .rx_valid_ext   (bridge_rx_valid),
+      .tx_data_ext    (bridge_tx_data),
+      .tx_valid_ext   (bridge_tx_valid),
+      .tx_ready_ext   (bridge_tx_ready),
+
+      // Multi-chip link disabled
+      .link_tx_data   (),
+      .link_tx_valid  (),
+      .link_tx_ready  (1'b0),
+      .link_rx_data   (8'b0),
+      .link_rx_valid  (1'b0),
+      .link_rx_ready  ()
+  );
+
+endmodule

fpga/f2/cl_neuromorphic.v

@@ -0,0 +1,298 @@
+// ============================================================================
+// CL Top-Level — AWS F2 Shell ↔ Neuromorphic Chip
+// ============================================================================
+//
+// Wraps the 128-core neuromorphic system for the AWS F2 FPGA (VU47P).
+//
+// Active interfaces:
+//   - OCL AXI-Lite (BAR0): Host MMIO → axi_uart_bridge → host_interface
+//
+// All other Shell interfaces (PCIM, PCIS/DMA, SDA, DDR, HBM, interrupts)
+// are tied off as unused.
+//
+// ============================================================================
+//
+// Copyright 2026 Henry Arthur Shulayev Barnes / Catalyst Neuromorphic Ltd
+// Company No. 17054540 — UK Patent Application No. 2602902.6
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// ============================================================================
+
+`include "cl_neuromorphic_defines.vh"
+
+module cl_neuromorphic (
+    input  wire        clk_main_a0,
+    input  wire        rst_main_n,
+
+    output wire [31:0] cl_sh_id0,
+    output wire [31:0] cl_sh_id1,
+
+    input  wire [31:0] sh_ocl_awaddr,
+    input  wire        sh_ocl_awvalid,
+    output wire        ocl_sh_awready,
+    input  wire [31:0] sh_ocl_wdata,
+    input  wire [3:0]  sh_ocl_wstrb,
+    input  wire        sh_ocl_wvalid,
+    output wire        ocl_sh_wready,
+    output wire [1:0]  ocl_sh_bresp,
+    output wire        ocl_sh_bvalid,
+    input  wire        sh_ocl_bready,
+    input  wire [31:0] sh_ocl_araddr,
+    input  wire        sh_ocl_arvalid,
+    output wire        ocl_sh_arready,
+    output wire [31:0] ocl_sh_rdata,
+    output wire [1:0]  ocl_sh_rresp,
+    output wire        ocl_sh_rvalid,
+    input  wire        sh_ocl_rready,
+
+    input  wire [31:0] sh_sda_awaddr,
+    input  wire        sh_sda_awvalid,
+    output wire        sda_sh_awready,
+    input  wire [31:0] sh_sda_wdata,
+    input  wire [3:0]  sh_sda_wstrb,
+    input  wire        sh_sda_wvalid,
+    output wire        sda_sh_wready,
+    output wire [1:0]  sda_sh_bresp,
+    output wire        sda_sh_bvalid,
+    input  wire        sh_sda_bready,
+    input  wire [31:0] sh_sda_araddr,
+    input  wire        sh_sda_arvalid,
+    output wire        sda_sh_arready,
+    output wire [31:0] sda_sh_rdata,
+    output wire [1:0]  sda_sh_rresp,
+    output wire        sda_sh_rvalid,
+    input  wire        sh_sda_rready,
+
+    output wire [63:0] cl_sh_pcim_awaddr,
+    output wire [15:0] cl_sh_pcim_awid,
+    output wire [7:0]  cl_sh_pcim_awlen,
+    output wire [2:0]  cl_sh_pcim_awsize,
+    output wire        cl_sh_pcim_awvalid,
+    input  wire        sh_cl_pcim_awready,
+    output wire [511:0] cl_sh_pcim_wdata,
+    output wire [63:0] cl_sh_pcim_wstrb,
+    output wire        cl_sh_pcim_wlast,
+    output wire        cl_sh_pcim_wvalid,
+    input  wire        sh_cl_pcim_wready,
+    input  wire [1:0]  sh_cl_pcim_bresp,
+    input  wire [15:0] sh_cl_pcim_bid,
+    input  wire        sh_cl_pcim_bvalid,
+    output wire        cl_sh_pcim_bready,
+    output wire [63:0] cl_sh_pcim_araddr,
+    output wire [15:0] cl_sh_pcim_arid,
+    output wire [7:0]  cl_sh_pcim_arlen,
+    output wire [2:0]  cl_sh_pcim_arsize,
+    output wire        cl_sh_pcim_arvalid,
+    input  wire        sh_cl_pcim_arready,
+    input  wire [511:0] sh_cl_pcim_rdata,
+    input  wire [15:0] sh_cl_pcim_rid,
+    input  wire [1:0]  sh_cl_pcim_rresp,
+    input  wire        sh_cl_pcim_rlast,
+    input  wire        sh_cl_pcim_rvalid,
+    output wire        cl_sh_pcim_rready,
+
+    input  wire [63:0] sh_cl_dma_pcis_awaddr,
+    input  wire [15:0] sh_cl_dma_pcis_awid,
+    input  wire [7:0]  sh_cl_dma_pcis_awlen,
+    input  wire [2:0]  sh_cl_dma_pcis_awsize,
+    input  wire        sh_cl_dma_pcis_awvalid,
+    output wire        cl_sh_dma_pcis_awready,
+    input  wire [511:0] sh_cl_dma_pcis_wdata,
+    input  wire [63:0] sh_cl_dma_pcis_wstrb,
+    input  wire        sh_cl_dma_pcis_wlast,
+    input  wire        sh_cl_dma_pcis_wvalid,
+    output wire        cl_sh_dma_pcis_wready,
+    output wire [1:0]  cl_sh_dma_pcis_bresp,
+    output wire [15:0] cl_sh_dma_pcis_bid,
+    output wire        cl_sh_dma_pcis_bvalid,
+    input  wire        sh_cl_dma_pcis_bready,
+    input  wire [63:0] sh_cl_dma_pcis_araddr,
+    input  wire [15:0] sh_cl_dma_pcis_arid,
+    input  wire [7:0]  sh_cl_dma_pcis_arlen,
+    input  wire [2:0]  sh_cl_dma_pcis_arsize,
+    input  wire        sh_cl_dma_pcis_arvalid,
+    output wire        cl_sh_dma_pcis_arready,
+    output wire [511:0] cl_sh_dma_pcis_rdata,
+    output wire [15:0] cl_sh_dma_pcis_rid,
+    output wire [1:0]  cl_sh_dma_pcis_rresp,
+    output wire        cl_sh_dma_pcis_rlast,
+    output wire        cl_sh_dma_pcis_rvalid,
+    input  wire        sh_cl_dma_pcis_rready,
+
+    input  wire        sh_cl_ddr_stat_wr,
+    input  wire        sh_cl_ddr_stat_rd,
+    input  wire [7:0]  sh_cl_ddr_stat_addr,
+    input  wire [31:0] sh_cl_ddr_stat_wdata,
+    output wire        cl_sh_ddr_stat_ack,
+    output wire [31:0] cl_sh_ddr_stat_rdata,
+    output wire [7:0]  cl_sh_ddr_stat_int,
+
+    output wire [15:0] cl_sh_apppf_irq_req,
+    input  wire [15:0] sh_cl_apppf_irq_ack,
+
+    input  wire        sh_cl_flr_assert,
+    output wire        cl_sh_flr_done,
+
+    output wire [31:0] cl_sh_status0,
+    output wire [31:0] cl_sh_status1
+);
+
+    assign cl_sh_id0 = `CL_SH_ID0;
+    assign cl_sh_id1 = `CL_SH_ID1;
+
+    assign cl_sh_status0 = 32'h0000_0001;  // bit 0 = CL alive
+    assign cl_sh_status1 = 32'd128;         // core count
+
+    // SDA — not used (management register space)
+    assign sda_sh_awready  = 1'b0;
+    assign sda_sh_wready   = 1'b0;
+    assign sda_sh_bresp    = 2'b00;
+    assign sda_sh_bvalid   = 1'b0;
+    assign sda_sh_arready  = 1'b0;
+    assign sda_sh_rdata    = 32'd0;
+    assign sda_sh_rresp    = 2'b00;
+    assign sda_sh_rvalid   = 1'b0;
+
+    // PCIM — not used (no CL-initiated DMA)
+    assign cl_sh_pcim_awaddr  = 64'd0;
+    assign cl_sh_pcim_awid    = 16'd0;
+    assign cl_sh_pcim_awlen   = 8'd0;
+    assign cl_sh_pcim_awsize  = 3'd0;
+    assign cl_sh_pcim_awvalid = 1'b0;
+    assign cl_sh_pcim_wdata   = 512'd0;
+    assign cl_sh_pcim_wstrb   = 64'd0;
+    assign cl_sh_pcim_wlast   = 1'b0;
+    assign cl_sh_pcim_wvalid  = 1'b0;
+    assign cl_sh_pcim_bready  = 1'b1;  // Accept any write response
+    assign cl_sh_pcim_araddr  = 64'd0;
+    assign cl_sh_pcim_arid    = 16'd0;
+    assign cl_sh_pcim_arlen   = 8'd0;
+    assign cl_sh_pcim_arsize  = 3'd0;
+    assign cl_sh_pcim_arvalid = 1'b0;
+    assign cl_sh_pcim_rready  = 1'b1;  // Accept any read data
+
+    // PCIS (DMA) — not used (no host DMA writes to CL)
+    assign cl_sh_dma_pcis_awready = 1'b0;
+    assign cl_sh_dma_pcis_wready  = 1'b0;
+    assign cl_sh_dma_pcis_bresp   = 2'b00;
+    assign cl_sh_dma_pcis_bid     = 16'd0;
+    assign cl_sh_dma_pcis_bvalid  = 1'b0;
+    assign cl_sh_dma_pcis_arready = 1'b0;
+    assign cl_sh_dma_pcis_rdata   = 512'd0;
+    assign cl_sh_dma_pcis_rid     = 16'd0;
+    assign cl_sh_dma_pcis_rresp   = 2'b00;
+    assign cl_sh_dma_pcis_rlast   = 1'b0;
+    assign cl_sh_dma_pcis_rvalid  = 1'b0;
+
+    // DDR stat — ack any request, return 0
+    assign cl_sh_ddr_stat_ack   = sh_cl_ddr_stat_wr | sh_cl_ddr_stat_rd;
+    assign cl_sh_ddr_stat_rdata = 32'd0;
+    assign cl_sh_ddr_stat_int   = 8'd0;
+
+    // Interrupts — none
+    assign cl_sh_apppf_irq_req = 16'd0;
+
+    // FLR — immediate acknowledge
+    assign cl_sh_flr_done = sh_cl_flr_assert;
+
+    wire [7:0] bridge_rx_data;
+    wire       bridge_rx_valid;
+    wire [7:0] bridge_tx_data;
+    wire       bridge_tx_valid;
+    wire       bridge_tx_ready;
+
+    axi_uart_bridge #(
+        .FIFO_DEPTH   (32),
+        .VERSION_ID   (32'hF2_02_03_80),  // F2, v2.3, 128-core
+        .NUM_CORES    (128)
+    ) u_bridge (
+        .clk           (clk_main_a0),
+        .rst_n         (rst_main_n),
+
+        // AXI-Lite slave ← Shell OCL master
+        .s_axi_awaddr  (sh_ocl_awaddr),
+        .s_axi_awvalid (sh_ocl_awvalid),
+        .s_axi_awready (ocl_sh_awready),
+        .s_axi_wdata   (sh_ocl_wdata),
+        .s_axi_wstrb   (sh_ocl_wstrb),
+        .s_axi_wvalid  (sh_ocl_wvalid),
+        .s_axi_wready  (ocl_sh_wready),
+        .s_axi_bresp   (ocl_sh_bresp),
+        .s_axi_bvalid  (ocl_sh_bvalid),
+        .s_axi_bready  (sh_ocl_bready),
+        .s_axi_araddr  (sh_ocl_araddr),
+        .s_axi_arvalid (sh_ocl_arvalid),
+        .s_axi_arready (ocl_sh_arready),
+        .s_axi_rdata   (ocl_sh_rdata),
+        .s_axi_rresp   (ocl_sh_rresp),
+        .s_axi_rvalid  (ocl_sh_rvalid),
+        .s_axi_rready  (sh_ocl_rready),
+
+        // Byte-stream to neuromorphic_top
+        .hi_rx_data    (bridge_rx_data),
+        .hi_rx_valid   (bridge_rx_valid),
+        .hi_tx_data    (bridge_tx_data),
+        .hi_tx_valid   (bridge_tx_valid),
+        .hi_tx_ready   (bridge_tx_ready)
+    );
+
+    neuromorphic_top #(
+        .CLK_FREQ       (250_000_000),  // F2 clk_main_a0 = 250 MHz
+        .BAUD           (115200),       // Unused (BYPASS_UART=1)
+        .BYPASS_UART    (1),
+        .NUM_CORES      (128),
+        .CORE_ID_BITS   (12),
+        .NUM_NEURONS    (1024),
+        .NEURON_BITS    (10),
+        .DATA_WIDTH     (16),
+        .POOL_DEPTH     (8192),         // 8K/core × 128 cores = 1M total
+        .POOL_ADDR_BITS (13),
+        .COUNT_BITS     (12),
+        .REV_FANIN      (32),
+        .REV_SLOT_BITS  (5),
+        .THRESHOLD      (16'sd1000),
+        .LEAK_RATE      (16'sd3),
+        .REFRAC_CYCLES  (3),
+        .ROUTE_FANOUT           (8),
+        .ROUTE_SLOT_BITS        (3),
+        .GLOBAL_ROUTE_SLOTS     (4),
+        .GLOBAL_ROUTE_SLOT_BITS (2),
+        .CHIP_LINK_EN   (0),
+        .NOC_MODE       (0),           // Barrier mesh (deterministic)
+        .MESH_X         (16),          // 16×8 = 128 cores
+        .MESH_Y         (8)
+    ) u_neuromorphic (
+        .clk            (clk_main_a0),
+        .rst_n          (rst_main_n),
+
+        // UART — unused (BYPASS_UART=1)
+        .uart_rxd       (1'b1),
+        .uart_txd       (),
+
+        // Byte-stream from AXI bridge
+        .rx_data_ext    (bridge_rx_data),
+        .rx_valid_ext   (bridge_rx_valid),
+        .tx_data_ext    (bridge_tx_data),
+        .tx_valid_ext   (bridge_tx_valid),
+        .tx_ready_ext   (bridge_tx_ready),
+
+        // Chip link — disabled
+        .link_tx_data   (),
+        .link_tx_valid  (),
+        .link_tx_ready  (1'b0),
+        .link_rx_data   (8'd0),
+        .link_rx_valid  (1'b0),
+        .link_rx_ready  ()
+    );
+
+endmodule

fpga/f2/cl_neuromorphic_defines.vh

@@ -0,0 +1,25 @@
+// ============================================================================
+// Copyright 2026 Henry Arthur Shulayev Barnes / Catalyst Neuromorphic Ltd
+// Company No. 17054540 — UK Patent Application No. 2602902.6
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// ============================================================================
+
+// CL Neuromorphic — PCIe ID defines
+`ifndef CL_NEUROMORPHIC_DEFINES_VH
+`define CL_NEUROMORPHIC_DEFINES_VH
+
+`define CL_SH_ID0 32'hF230_1D0F  // F230=neuromorphic, 1D0F=Amazon
+`define CL_SH_ID1 32'h0010_1D0F  // 0010=16-core
+
+`endif

fpga/f2/cl_synth_user.xdc

@@ -0,0 +1,8 @@
+# ============================================================================
+# CL Synthesis Constraints — Neuromorphic Chip on AWS F2
+# ============================================================================
+# These are applied during synthesis only (not implementation).
+
+# No false paths or multicycle needed — single clock domain design.
+# The Shell provides clk_main_a0 at 250 MHz (4.0 ns period).
+# All neuromorphic logic is synchronous to this single clock.

fpga/f2/cl_timing_user.xdc

@@ -0,0 +1,14 @@
+# ===========================================================================
+# CL Neuromorphic — User Timing Constraints
+# ===========================================================================
+
+# Generated clock from MMCME4 (62.5 MHz)
+# The MMCM auto-generates clock constraints from its parameters,
+# but we add explicit false paths between clock domains for CDC.
+
+# Async FIFO CDC: false paths between AXI clock and neuro clock
+# The Gray-code synchronizers in async_fifo handle the CDC safely.
+set_false_path -from [get_clocks -of_objects [get_pins WRAPPER/CL/u_mmcm/CLKIN1]] \
+               -to   [get_clocks -of_objects [get_pins WRAPPER/CL/u_mmcm/CLKOUT0]]
+set_false_path -from [get_clocks -of_objects [get_pins WRAPPER/CL/u_mmcm/CLKOUT0]] \
+               -to   [get_clocks -of_objects [get_pins WRAPPER/CL/u_mmcm/CLKIN1]]

fpga/f2/deploy_f2.sh

@@ -0,0 +1,181 @@
+#!/bin/bash
+# ============================================================================
+# F2 Deploy Script — Build + Deploy Neuromorphic Chip to AWS F2
+# ============================================================================
+#
+# Prerequisites:
+#   1. AWS FPGA HDK cloned and set up:
+#      git clone https://github.com/aws/aws-fpga
+#      cd aws-fpga && source hdk_setup.sh
+#
+#   2. This repository cloned at $NEURO_DIR:
+#      export NEURO_DIR=/path/to/neuromorphic-chip
+#
+#   3. S3 bucket for AFI artifacts:
+#      export AFI_BUCKET=my-fpga-bucket
+#      export AFI_PREFIX=neuromorphic-v2.3
+#
+# Usage:
+#   ./deploy_f2.sh [--build-only | --load-only | --test]
+# ============================================================================
+
+set -euo pipefail
+
+NEURO_DIR="${NEURO_DIR:-$(cd "$(dirname "$0")/../.." && pwd)}"
+AFI_BUCKET="${AFI_BUCKET:-}"
+AFI_PREFIX="${AFI_PREFIX:-neuromorphic-v2.3}"
+CL_DIR="${CL_DIR:-$HDK_DIR/cl/developer_designs/cl_neuromorphic}"
+MODE="${1:---full}"
+
+echo "============================================"
+echo "  Neuromorphic Chip v2.3 — F2 Deployment"
+echo "============================================"
+echo "  NEURO_DIR: $NEURO_DIR"
+echo "  CL_DIR:    $CL_DIR"
+echo "  Mode:      $MODE"
+echo ""
+
+# ---- Step 1: Copy design files into HDK CL tree ----
+copy_design() {
+    echo "--- Copying design files ---"
+    mkdir -p "$CL_DIR/design"
+    mkdir -p "$CL_DIR/build/constraints"
+
+    # CL wrapper + bridge
+    cp "$NEURO_DIR/fpga/f2/cl_neuromorphic.v"          "$CL_DIR/design/"
+    cp "$NEURO_DIR/fpga/f2/cl_neuromorphic_defines.vh"  "$CL_DIR/design/"
+    cp "$NEURO_DIR/rtl/axi_uart_bridge.v"               "$CL_DIR/design/"
+
+    # Neuromorphic RTL (excluding UART modules — BYPASS_UART=1)
+    for f in sram.v spike_fifo.v scalable_core_v2.v neuromorphic_mesh.v \
+             async_noc_mesh.v async_router.v sync_tree.v chip_link.v \
+             host_interface.v neuromorphic_top.v rv32i_core.v \
+             rv32im_cluster.v mmio_bridge.v multi_chip_router.v; do
+        cp "$NEURO_DIR/rtl/$f" "$CL_DIR/design/"
+    done
+
+    # Constraints
+    cp "$NEURO_DIR/fpga/f2/cl_synth_user.xdc"   "$CL_DIR/build/constraints/"
+    cp "$NEURO_DIR/fpga/f2/cl_timing_user.xdc"   "$CL_DIR/build/constraints/"
+
+    # Build source list
+    cp "$NEURO_DIR/fpga/f2/build_f2.tcl" "$CL_DIR/build/scripts/cl_build_user.tcl"
+
+    echo "  Copied $(ls "$CL_DIR/design/"*.v 2>/dev/null | wc -l) Verilog files"
+}
+
+# ---- Step 2: Build DCP (synthesis + implementation) ----
+build_dcp() {
+    echo ""
+    echo "--- Building DCP (this takes 4-8 hours) ---"
+    cd "$CL_DIR/build/scripts"
+    ./aws_build_dcp_from_cl.sh -clock_recipe_a A1  # A1 = 250 MHz
+    echo "  DCP build complete"
+
+    # Check for timing failures
+    local timing_rpt="$CL_DIR/build/checkpoints/to_aws/*.SH_CL_routed.rpt"
+    if grep -q "VIOLATED" $timing_rpt 2>/dev/null; then
+        echo "  WARNING: Timing violations detected! Check reports."
+    else
+        echo "  Timing met at 250 MHz"
+    fi
+}
+
+# ---- Step 3: Create AFI ----
+create_afi() {
+    if [ -z "$AFI_BUCKET" ]; then
+        echo "  ERROR: Set AFI_BUCKET environment variable"
+        exit 1
+    fi
+
+    echo ""
+    echo "--- Creating AFI ---"
+    local tar_file=$(ls "$CL_DIR/build/checkpoints/to_aws/"*.tar 2>/dev/null | head -1)
+    if [ -z "$tar_file" ]; then
+        echo "  ERROR: No .tar file found in checkpoints/to_aws/"
+        exit 1
+    fi
+
+    aws s3 cp "$tar_file" "s3://$AFI_BUCKET/$AFI_PREFIX/"
+
+    local tar_name=$(basename "$tar_file")
+    aws ec2 create-fpga-image \
+        --name "neuromorphic-v2.3-16core" \
+        --description "Neuromorphic chip v2.3, 16 cores x 1024 neurons, F2 VU47P" \
+        --input-storage-location "Bucket=$AFI_BUCKET,Key=$AFI_PREFIX/$tar_name" \
+        --logs-storage-location "Bucket=$AFI_BUCKET,Key=$AFI_PREFIX/logs/" \
+        | tee /tmp/afi_create_output.json
+
+    echo ""
+    echo "  AFI creation submitted. Monitor with:"
+    echo "    aws ec2 describe-fpga-images --fpga-image-ids <afi-id>"
+}
+
+# ---- Step 4: Load AFI ----
+load_afi() {
+    local afi_id="${AFI_ID:-}"
+    if [ -z "$afi_id" ]; then
+        echo "  ERROR: Set AFI_ID environment variable (e.g., afi-XXXXXXXX)"
+        exit 1
+    fi
+
+    local agfi_id="${AGFI_ID:-}"
+    if [ -z "$agfi_id" ]; then
+        echo "  ERROR: Set AGFI_ID environment variable (e.g., agfi-XXXXXXXX)"
+        exit 1
+    fi
+
+    echo ""
+    echo "--- Loading AFI onto slot 0 ---"
+    sudo fpga-load-local-image -S 0 -I "$agfi_id"
+    sleep 2
+    sudo fpga-describe-local-image -S 0 -H
+    echo "  AFI loaded"
+}
+
+# ---- Step 5: Run test ----
+run_test() {
+    echo ""
+    echo "--- Running connectivity test ---"
+    python3 "$NEURO_DIR/fpga/f2_host.py" --test-loopback
+    echo ""
+    echo "--- Running spike test ---"
+    python3 "$NEURO_DIR/fpga/f2_host.py" --test-spike
+}
+
+# ---- Main ----
+case "$MODE" in
+    --build-only)
+        copy_design
+        build_dcp
+        ;;
+    --afi-only)
+        create_afi
+        ;;
+    --load-only)
+        load_afi
+        ;;
+    --test)
+        run_test
+        ;;
+    --full)
+        copy_design
+        build_dcp
+        create_afi
+        echo ""
+        echo "============================================"
+        echo "  BUILD COMPLETE"
+        echo "============================================"
+        echo "  Next steps:"
+        echo "    1. Wait for AFI to become available"
+        echo "    2. export AFI_ID=afi-XXXXXXXX"
+        echo "    3. export AGFI_ID=agfi-XXXXXXXX"
+        echo "    4. ./deploy_f2.sh --load-only"
+        echo "    5. ./deploy_f2.sh --test"
+        echo "============================================"
+        ;;
+    *)
+        echo "Usage: $0 [--build-only | --afi-only | --load-only | --test | --full]"
+        exit 1
+        ;;
+esac

fpga/f2/run_build.sh

@@ -0,0 +1,10 @@
+#!/bin/bash
+set -e
+source /opt/Xilinx/2025.2/Vivado/settings64.sh
+cd /home/ubuntu/aws-fpga
+source hdk_setup.sh
+export CL_DIR=/home/ubuntu/aws-fpga/hdk/cl/developer_designs/cl_neuromorphic
+echo "=== Starting build at $(date) ==="
+cd /home/ubuntu/aws-fpga/hdk/cl/developer_designs/cl_neuromorphic/build/scripts
+python3 aws_build_dcp_from_cl.py -c cl_neuromorphic --no-encrypt
+echo "=== Build finished at $(date) ==="

fpga/f2/synth_cl_neuromorphic.tcl

@@ -0,0 +1,48 @@
+source ${HDK_SHELL_DIR}/build/scripts/synth_cl_header.tcl
+
+print "Reading neuromorphic design sources"
+
+# CL wrapper is SystemVerilog (uses cl_ports.vh with 'logic' types)
+read_verilog -sv [ list \
+  ${src_post_enc_dir}/cl_neuromorphic.sv \
+]
+
+# RTL modules are plain Verilog
+read_verilog [ list \
+  ${src_post_enc_dir}/cl_neuromorphic_defines.vh \
+  ${src_post_enc_dir}/async_fifo.v \
+  ${src_post_enc_dir}/axi_uart_bridge.v \
+  ${src_post_enc_dir}/sram.v \
+  ${src_post_enc_dir}/spike_fifo.v \
+  ${src_post_enc_dir}/scalable_core_v2.v \
+  ${src_post_enc_dir}/neuromorphic_mesh.v \
+  ${src_post_enc_dir}/async_noc_mesh.v \
+  ${src_post_enc_dir}/async_router.v \
+  ${src_post_enc_dir}/sync_tree.v \
+  ${src_post_enc_dir}/chip_link.v \
+  ${src_post_enc_dir}/host_interface.v \
+  ${src_post_enc_dir}/neuromorphic_top.v \
+  ${src_post_enc_dir}/rv32i_core.v \
+  ${src_post_enc_dir}/rv32im_cluster.v \
+  ${src_post_enc_dir}/mmio_bridge.v \
+  ${src_post_enc_dir}/multi_chip_router.v \
+]
+
+print "Reading user constraints"
+read_xdc [ list \
+  ${constraints_dir}/cl_synth_user.xdc \
+  ${constraints_dir}/cl_timing_user.xdc \
+]
+set_property PROCESSING_ORDER LATE [get_files cl_synth_user.xdc]
+set_property PROCESSING_ORDER LATE [get_files cl_timing_user.xdc]
+
+print "Starting synthesizing customer design ${CL}"
+update_compile_order -fileset sources_1
+
+synth_design -mode out_of_context \
+             -top ${CL} \
+             -verilog_define XSDB_SLV_DIS \
+             -part ${DEVICE_TYPE} \
+             -keep_equivalent_registers
+
+source ${HDK_SHELL_DIR}/build/scripts/synth_cl_footer.tcl

fpga/f2_host.py

@@ -0,0 +1,580 @@
+"""
+Neuromorphic Chip F2 Host Controller
+=====================================
+Python driver for the neuromorphic FPGA on AWS F2, communicating via
+PCIe MMIO (AXI-Lite registers) instead of UART.
+
+Same byte-level protocol as host.py, different transport layer.
+
+Usage:
+    python fpga/f2_host.py --demo                   # Run demo (fpga_mgmt transport)
+    python fpga/f2_host.py --status                  # Query chip status
+    python fpga/f2_host.py --test-loopback           # Connectivity test
+    python fpga/f2_host.py --test-spike              # Spike chain test
+    python fpga/f2_host.py --transport mmap           # Use mmap transport
+
+Register map (BAR0 offsets, via fpga_mgmt BAR0):
+    0x000 [W]   TX_DATA    - write byte to host_interface
+    0x004 [R]   TX_STATUS  - bit[0] = ready (TX FIFO not full)
+    0x008 [R]   RX_DATA    - read response byte (auto-pops)
+    0x00C [R]   RX_STATUS  - bit[0] = not empty
+    0x010 [R/W] CONTROL    - bit[0] = soft reset (self-clearing)
+    0x014 [R]   VERSION    - firmware version (0xF2020310 = 16-core)
+    0x018 [R/W] SCRATCH    - loopback register
+    0x01C [R]   CORE_COUNT - number of cores
+
+FPGA BRAM init workaround:
+    On FPGA, all SRAMs init to 0. For compartment system correctness,
+    each used neuron must have is_root=1 (param_id=24) and
+    parent_ptr=1023 (param_id=22) set explicitly. Use setup_neuron().
+"""
+
+import struct
+import time
+import argparse
+import sys
+
+
+class MmapTransport:
+    """MMIO via mmap of /dev/fpga0_ocl BAR0."""
+
+    def __init__(self, device="/dev/fpga0_ocl", bar_size=0x10000):
+        import mmap
+        import os
+        fd = os.open(device, os.O_RDWR | os.O_SYNC)
+        self._mm = mmap.mmap(fd, bar_size, access=mmap.ACCESS_WRITE)
+        os.close(fd)  # mmap keeps its own reference
+
+    def write32(self, offset, value):
+        struct.pack_into('<I', self._mm, offset, value & 0xFFFFFFFF)
+
+    def read32(self, offset):
+        return struct.unpack_from('<I', self._mm, offset)[0]
+
+    def close(self):
+        self._mm.close()
+
+
+class FpgaMgmtTransport:
+    """MMIO via AWS FPGA Management Library (libfpga_mgmt.so)."""
+
+    def __init__(self, slot=0, bar=0):
+        import ctypes
+        self._lib = ctypes.CDLL("libfpga_mgmt.so")
+
+        # fpga_mgmt_init()
+        rc = self._lib.fpga_mgmt_init()
+        if rc != 0:
+            raise RuntimeError(f"fpga_mgmt_init failed: {rc}")
+
+        # fpga_pci_attach(slot, pf_id=0, bar, flags=0, &handle)
+        self._handle = ctypes.c_int()
+        rc = self._lib.fpga_pci_attach(slot, 0, bar, 0,
+                                        ctypes.byref(self._handle))
+        if rc != 0:
+            raise RuntimeError(f"fpga_pci_attach failed: {rc}")
+
+        self._poke = self._lib.fpga_pci_poke
+        self._peek = self._lib.fpga_pci_peek
+        self._ctypes = ctypes
+
+    def write32(self, offset, value):
+        rc = self._poke(self._handle, offset, value & 0xFFFFFFFF)
+        if rc != 0:
+            raise RuntimeError(f"fpga_pci_poke(0x{offset:X}, 0x{value:X}) failed: {rc}")
+
+    def read32(self, offset):
+        val = self._ctypes.c_uint32()
+        rc = self._peek(self._handle, offset, self._ctypes.byref(val))
+        if rc != 0:
+            raise RuntimeError(f"fpga_pci_peek(0x{offset:X}) failed: {rc}")
+        return val.value
+
+    def close(self):
+        self._lib.fpga_pci_detach(self._handle)
+
+
+class F2NeuromorphicChip:
+    """Interface to the neuromorphic FPGA via PCIe MMIO."""
+
+    # Register offsets
+    REG_TX_DATA    = 0x000
+    REG_TX_STATUS  = 0x004
+    REG_RX_DATA    = 0x008
+    REG_RX_STATUS  = 0x00C
+    REG_CONTROL    = 0x010
+    REG_VERSION    = 0x014
+    REG_SCRATCH    = 0x018
+    REG_CORE_COUNT = 0x01C
+
+    # Command opcodes (same as host.py)
+    CMD_PROG_POOL   = 0x01
+    CMD_PROG_ROUTE  = 0x02
+    CMD_STIMULUS    = 0x03
+    CMD_RUN         = 0x04
+    CMD_STATUS      = 0x05
+    CMD_LEARN_CFG   = 0x06
+    CMD_PROG_NEURON = 0x07
+    CMD_PROG_INDEX  = 0x08
+    CMD_REWARD      = 0x09
+    CMD_PROG_DELAY  = 0x0A
+    CMD_PROG_LEARN  = 0x0C
+    CMD_PROG_GLOBAL_ROUTE = 0x10
+
+    # Parameter IDs
+    PARAM_THRESHOLD      = 0
+    PARAM_LEAK           = 1
+    PARAM_RESTING        = 2
+    PARAM_REFRAC         = 3
+    PARAM_DEND_THRESHOLD = 4
+    PARAM_DECAY_V        = 16
+    PARAM_DECAY_U        = 17
+    PARAM_BIAS_CFG       = 18
+    PARAM_PARENT_PTR     = 22
+    PARAM_JOINOP         = 23
+    PARAM_IS_ROOT        = 24
+
+    # Response codes
+    RESP_ACK  = 0xAA
+    RESP_DONE = 0xDD
+
+    def __init__(self, transport='fpga_mgmt', slot=0, timeout=5.0):
+        if transport == 'mmap':
+            self._t = MmapTransport()
+        elif transport == 'fpga_mgmt':
+            self._t = FpgaMgmtTransport(slot=slot)
+        else:
+            raise ValueError(f"Unknown transport: {transport}")
+
+        self._timeout = timeout
+        self._pool_alloc = {}
+
+        # Verify connectivity
+        ver = self._t.read32(self.REG_VERSION)
+        cores = self._t.read32(self.REG_CORE_COUNT)
+        self._num_cores = cores
+        print(f"Connected via {transport}: version=0x{ver:08X}, cores={cores}")
+
+    def close(self):
+        self._t.close()
+
+    def _send(self, data):
+        """Send bytes to host_interface via TX FIFO."""
+        for b in data:
+            deadline = time.monotonic() + self._timeout
+            while True:
+                status = self._t.read32(self.REG_TX_STATUS)
+                if status & 1:
+                    break
+                if time.monotonic() > deadline:
+                    raise TimeoutError("TX FIFO full timeout")
+            self._t.write32(self.REG_TX_DATA, b & 0xFF)
+
+    def _recv(self, n):
+        """Receive n bytes from host_interface via RX FIFO."""
+        result = bytearray()
+        deadline = time.monotonic() + self._timeout
+        while len(result) < n:
+            status = self._t.read32(self.REG_RX_STATUS)
+            if status & 1:  # not empty
+                val = self._t.read32(self.REG_RX_DATA)
+                result.append(val & 0xFF)
+                deadline = time.monotonic() + self._timeout  # Reset per byte
+            elif time.monotonic() > deadline:
+                raise TimeoutError(
+                    f"RX timeout: got {len(result)}/{n} bytes")
+        return bytes(result)
+
+    def _wait_ack(self):
+        """Wait for ACK (0xAA) response."""
+        resp = self._recv(1)
+        if resp[0] != self.RESP_ACK:
+            raise ValueError(f"Expected ACK (0xAA), got 0x{resp[0]:02X}")
+
+    def _alloc_pool(self, core, count=1):
+        """Allocate pool entries (bump allocator)."""
+        if core not in self._pool_alloc:
+            self._pool_alloc[core] = 0
+        addr = self._pool_alloc[core]
+        self._pool_alloc[core] += count
+        return addr
+
+    def soft_reset(self):
+        """Issue a soft reset (clears FIFOs)."""
+        self._t.write32(self.REG_CONTROL, 1)
+        time.sleep(0.001)
+
+    def read_version(self):
+        return self._t.read32(self.REG_VERSION)
+
+    def read_core_count(self):
+        return self._t.read32(self.REG_CORE_COUNT)
+
+    def test_scratch(self, value=0xDEADBEEF):
+        """Write/read SCRATCH register for loopback test."""
+        self._t.write32(self.REG_SCRATCH, value)
+        readback = self._t.read32(self.REG_SCRATCH)
+        return readback == value, readback
+
+    def prog_pool(self, core, pool_addr, src, target, weight, comp=0):
+        w = weight & 0xFFFF
+        flags = ((comp & 0x3) << 6) | (((src >> 8) & 0x3) << 4) | (((target >> 8) & 0x3) << 2)
+        self._send([
+            self.CMD_PROG_POOL,
+            core & 0xFF,
+            (pool_addr >> 8) & 0xFF, pool_addr & 0xFF,
+            flags,
+            src & 0xFF,
+            target & 0xFF,
+            (w >> 8) & 0xFF, w & 0xFF
+        ])
+        self._wait_ack()
+
+    def prog_index(self, core, neuron, base_addr, count, format=0, base_target=0):
+        self._send([
+            self.CMD_PROG_INDEX,
+            core & 0xFF,
+            (neuron >> 8) & 0xFF, neuron & 0xFF,
+            (base_addr >> 8) & 0xFF, base_addr & 0xFF,
+            ((format & 0x3) << 6) | ((count >> 8) & 0x3F), count & 0xFF,
+        ])
+        self._wait_ack()
+
+    def prog_conn(self, core, src, targets_weights, comp=0):
+        if not targets_weights:
+            return
+        base = self._alloc_pool(core, len(targets_weights))
+        for i, (target, weight) in enumerate(targets_weights):
+            self.prog_pool(core, base + i, src, target, weight, comp)
+        self.prog_index(core, src, base, len(targets_weights))
+
+    def prog_route(self, src_core, src_neuron, dest_core, dest_neuron, weight, slot=0):
+        w = weight & 0xFFFF
+        self._send([
+            self.CMD_PROG_ROUTE,
+            src_core & 0xFF,
+            (src_neuron >> 8) & 0xFF, src_neuron & 0xFF,
+            slot & 0xFF,
+            dest_core & 0xFF,
+            (dest_neuron >> 8) & 0xFF, dest_neuron & 0xFF,
+            (w >> 8) & 0xFF, w & 0xFF
+        ])
+        self._wait_ack()
+
+    def stimulus(self, core, neuron, current):
+        c = current & 0xFFFF
+        self._send([
+            self.CMD_STIMULUS,
+            core & 0xFF,
+            (neuron >> 8) & 0xFF, neuron & 0xFF,
+            (c >> 8) & 0xFF, c & 0xFF
+        ])
+        self._wait_ack()
+
+    def run(self, timesteps):
+        ts = timesteps & 0xFFFF
+        self._send([
+            self.CMD_RUN,
+            (ts >> 8) & 0xFF, ts & 0xFF
+        ])
+        resp = self._recv(5)
+        if resp[0] != self.RESP_DONE:
+            raise ValueError(f"Expected DONE (0xDD), got 0x{resp[0]:02X}")
+        spikes = struct.unpack('>I', resp[1:5])[0]
+        return spikes
+
+    def status(self):
+        self._send([self.CMD_STATUS])
+        resp = self._recv(5)
+        state = resp[0]
+        ts_count = struct.unpack('>I', resp[1:5])[0]
+        return state, ts_count
+
+    def reward(self, value):
+        v = value & 0xFFFF
+        self._send([
+            self.CMD_REWARD,
+            (v >> 8) & 0xFF, v & 0xFF
+        ])
+        self._wait_ack()
+
+    def set_learning(self, learn_enable, graded_enable=False, dendritic_enable=False,
+                      async_enable=False, threefactor_enable=False, noise_enable=False):
+        flags = ((int(learn_enable) & 1)
+                 | ((int(graded_enable) & 1) << 1)
+                 | ((int(dendritic_enable) & 1) << 2)
+                 | ((int(async_enable) & 1) << 3)
+                 | ((int(threefactor_enable) & 1) << 4)
+                 | ((int(noise_enable) & 1) << 5))
+        self._send([self.CMD_LEARN_CFG, flags])
+        self._wait_ack()
+
+    def prog_neuron(self, core, neuron, param_id, value):
+        v = value & 0xFFFF
+        self._send([
+            self.CMD_PROG_NEURON,
+            core & 0xFF,
+            (neuron >> 8) & 0xFF, neuron & 0xFF,
+            param_id & 0xFF,
+            (v >> 8) & 0xFF, v & 0xFF
+        ])
+        self._wait_ack()
+
+    def setup_neuron(self, core, neuron, threshold=1000):
+        """Configure a neuron for standalone operation on FPGA.
+
+        FPGA BRAMs init to 0, which breaks the compartment system:
+        - is_root=0 means spikes never counted externally
+        - parent_ptr=0 means all neurons cascade to neuron 0
+
+        This sets threshold + is_root=1 + parent_ptr=sentinel for
+        correct standalone operation.
+        """
+        self.prog_neuron(core, neuron, self.PARAM_THRESHOLD, threshold)
+        self.prog_neuron(core, neuron, self.PARAM_PARENT_PTR, 1023)  # no-parent sentinel
+        self.prog_neuron(core, neuron, self.PARAM_IS_ROOT, 1)
+
+    def setup_neurons(self, neuron_list):
+        """Setup multiple neurons. neuron_list: [(core, neuron, threshold), ...]"""
+        for core, neuron, threshold in neuron_list:
+            self.setup_neuron(core, neuron, threshold)
+
+    def prog_delay(self, core, pool_addr, delay):
+        self._send([
+            self.CMD_PROG_DELAY,
+            core & 0xFF,
+            (pool_addr >> 8) & 0xFF, pool_addr & 0xFF,
+            delay & 0x3F,
+        ])
+        self._wait_ack()
+
+    def prog_learn(self, core, addr, instr):
+        self._send([
+            self.CMD_PROG_LEARN,
+            core & 0xFF,
+            addr & 0x3F,
+            (instr >> 24) & 0xFF,
+            (instr >> 16) & 0xFF,
+            (instr >> 8) & 0xFF,
+            instr & 0xFF,
+        ])
+        self._wait_ack()
+
+    def prog_global_route(self, src_core, src_neuron, dest_core, dest_neuron,
+                           weight, slot=0):
+        w = weight & 0xFFFF
+        self._send([
+            self.CMD_PROG_GLOBAL_ROUTE,
+            src_core & 0xFF,
+            (src_neuron >> 8) & 0xFF, src_neuron & 0xFF,
+            slot & 0xFF,
+            dest_core & 0xFF,
+            (dest_neuron >> 8) & 0xFF, dest_neuron & 0xFF,
+            (w >> 8) & 0xFF, w & 0xFF,
+        ])
+        self._wait_ack()
+
+
+def test_loopback(chip):
+    """Basic connectivity test: registers only, no mesh interaction."""
+    print("\n" + "=" * 60)
+    print("  F2 Loopback Test")
+    print("=" * 60)
+    passed = 0
+    total = 0
+
+    # VERSION
+    total += 1
+    ver = chip.read_version()
+    if ver == 0xF2020310:
+        print(f"  [PASS] VERSION = 0x{ver:08X}")
+        passed += 1
+    else:
+        print(f"  [FAIL] VERSION = 0x{ver:08X} (expected 0xF2020310)")
+
+    # CORE_COUNT
+    total += 1
+    cores = chip.read_core_count()
+    if cores == 16:
+        print(f"  [PASS] CORE_COUNT = {cores}")
+        passed += 1
+    else:
+        print(f"  [FAIL] CORE_COUNT = {cores} (expected 16)")
+
+    # SCRATCH
+    total += 1
+    ok, val = chip.test_scratch(0xDEADBEEF)
+    if ok:
+        print(f"  [PASS] SCRATCH loopback = 0x{val:08X}")
+        passed += 1
+    else:
+        print(f"  [FAIL] SCRATCH = 0x{val:08X} (expected 0xDEADBEEF)")
+
+    total += 1
+    ok, val = chip.test_scratch(0x12345678)
+    if ok:
+        print(f"  [PASS] SCRATCH loopback = 0x{val:08X}")
+        passed += 1
+    else:
+        print(f"  [FAIL] SCRATCH = 0x{val:08X} (expected 0x12345678)")
+
+    # STATUS command
+    total += 1
+    try:
+        state, ts = chip.status()
+        print(f"  [PASS] STATUS: state={state}, ts_count={ts}")
+        passed += 1
+    except Exception as e:
+        print(f"  [FAIL] STATUS: {e}")
+
+    print(f"\n  Result: {passed}/{total} passed")
+    print("=" * 60)
+    return passed == total
+
+
+def test_spike(chip):
+    """Program a 2-neuron chain, inject spike, verify propagation."""
+    print("\n" + "=" * 60)
+    print("  F2 Spike Test")
+    print("=" * 60)
+
+    # Soft reset to clear any previous state
+    chip.soft_reset()
+    chip._pool_alloc = {}
+
+    state, ts = chip.status()
+    print(f"  Initial: state={state}, ts={ts}")
+
+    # Setup neurons (FPGA BRAM init workaround)
+    print("  Setting up neurons (is_root=1, parent_ptr=1023)...")
+    chip.setup_neuron(0, 0, threshold=1000)
+    chip.setup_neuron(0, 1, threshold=1000)
+
+    # Program: Core 0, N0→N1 (w=1200 > threshold=1000)
+    print("  Programming: N0 -> N1 (w=1200)")
+    chip.prog_conn(0, 0, [(1, 1200)])
+
+    # Stimulate N0
+    print("  Stimulating: Core 0, N0, current=1200")
+    chip.stimulus(core=0, neuron=0, current=1200)
+
+    # Run 5 timesteps
+    print("  Running 5 timesteps...")
+    t0 = time.monotonic()
+    spikes = chip.run(5)
+    dt = time.monotonic() - t0
+    print(f"  Result: {spikes} spikes in {dt*1000:.1f} ms")
+
+    if spikes > 0:
+        print("  [PASS] Spike propagation detected")
+    else:
+        print("  [FAIL] No spikes (expected > 0)")
+
+    print("=" * 60)
+    return spikes > 0
+
+
+def demo(chip):
+    """Run full demo: program cross-core spike chain, run, observe."""
+    print("\n" + "=" * 60)
+    print("  Neuromorphic Chip F2 Demo (16-core, PCIe MMIO)")
+    print("=" * 60)
+
+    chip.soft_reset()
+    chip._pool_alloc = {}
+
+    state, ts = chip.status()
+    print(f"\nInitial status: state={state}, timesteps={ts}")
+
+    # Setup neurons (FPGA BRAM init workaround)
+    print("\nSetting up neurons (is_root=1, parent_ptr=1023)...")
+    neurons = [(0, i, 1000) for i in range(4)] + [(1, i, 1000) for i in range(3)]
+    chip.setup_neurons(neurons)
+    print(f"  {len(neurons)} neurons configured")
+
+    # Program a spike chain: Core 0, N0→N1→N2→N3
+    print("\nProgramming spike chain: Core 0, N0 -> N1 -> N2 -> N3")
+    chip.prog_conn(0, 0, [(1, 1200)])
+    print("  N0 -> N1 (w=1200) OK")
+    chip.prog_conn(0, 1, [(2, 1200)])
+    print("  N1 -> N2 (w=1200) OK")
+    chip.prog_conn(0, 2, [(3, 1200)])
+    print("  N2 -> N3 (w=1200) OK")
+
+    # Cross-core route: Core 0 N3 → Core 1 N0
+    print("\nProgramming cross-core route: C0:N3 -> C1:N0")
+    chip.prog_route(src_core=0, src_neuron=3,
+                    dest_core=1, dest_neuron=0, weight=1200)
+    print("  Route OK")
+
+    # Core 1 chain
+    print("Programming Core 1 chain: N0 -> N1 -> N2")
+    chip.prog_conn(1, 0, [(1, 1200)])
+    chip.prog_conn(1, 1, [(2, 1200)])
+    print("  Core 1 chain OK")
+
+    # Stimulate and run
+    print("\nApplying stimulus: Core 0, N0, current=1200")
+    chip.stimulus(core=0, neuron=0, current=1200)
+
+    print("Running 20 timesteps...")
+    t0 = time.monotonic()
+    spikes = chip.run(20)
+    dt = time.monotonic() - t0
+    print(f"  Done! {spikes} spikes in {dt*1000:.1f} ms")
+    print(f"  Throughput: {20/dt:.0f} timesteps/sec")
+
+    # Run more without stimulus
+    print("\nRunning 10 more timesteps (no stimulus)...")
+    spikes2 = chip.run(10)
+    print(f"  {spikes2} spikes (should be 0 - no input)")
+
+    # Final status
+    state, ts = chip.status()
+    print(f"\nFinal status: state={state}, timesteps={ts}")
+
+    print("\n" + "=" * 60)
+    print("  Demo complete! The chip is alive on F2.")
+    print("=" * 60)
+
+
+def main():
+    parser = argparse.ArgumentParser(
+        description="Neuromorphic Chip F2 Host Controller (PCIe MMIO)")
+    parser.add_argument("--transport", choices=["mmap", "fpga_mgmt"],
+                        default="fpga_mgmt", help="MMIO transport (default: fpga_mgmt)")
+    parser.add_argument("--slot", type=int, default=0,
+                        help="FPGA slot (default: 0)")
+    parser.add_argument("--demo", action="store_true",
+                        help="Run full demo")
+    parser.add_argument("--status", action="store_true",
+                        help="Query chip status")
+    parser.add_argument("--test-loopback", action="store_true",
+                        help="Run loopback connectivity test")
+    parser.add_argument("--test-spike", action="store_true",
+                        help="Run spike propagation test")
+    args = parser.parse_args()
+
+    chip = F2NeuromorphicChip(transport=args.transport, slot=args.slot)
+
+    try:
+        if args.test_loopback:
+            ok = test_loopback(chip)
+            sys.exit(0 if ok else 1)
+        elif args.test_spike:
+            ok = test_spike(chip)
+            sys.exit(0 if ok else 1)
+        elif args.status:
+            state, ts = chip.status()
+            print(f"State: {state} ({'idle' if state == 0 else 'busy'})")
+            print(f"Timestep count: {ts}")
+        elif args.demo:
+            demo(chip)
+        else:
+            print("No command specified. Use --demo, --status, --test-loopback, or --test-spike")
+    finally:
+        chip.close()
+
+
+if __name__ == "__main__":
+    main()

fpga/fpga_top.v

@@ -0,0 +1,174 @@
+// ============================================================================
+// FPGA Top
+// ============================================================================
+//
+// Copyright 2026 Henry Arthur Shulayev Barnes / Catalyst Neuromorphic Ltd
+// Company No. 17054540 — UK Patent Application No. 2602902.6
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// ============================================================================
+
+module fpga_top #(
+    parameter CLK_FREQ  = 100_000_000,
+    parameter BAUD      = 115200,
+    parameter POR_BITS  = 20
+)(
+    input  wire       clk,
+    input  wire       btn_rst,    // Active-high
+    input  wire       uart_rxd,
+    output wire       uart_txd,
+    output reg  [3:0] led
+);
+
+    reg [POR_BITS-1:0] debounce_cnt;
+    reg        btn_sync1, btn_sync2;
+    reg        btn_stable;
+    wire       rst_n;
+
+    always @(posedge clk) begin
+        btn_sync1 <= btn_rst;
+        btn_sync2 <= btn_sync1;
+    end
+
+    always @(posedge clk) begin
+        if (btn_sync2 != btn_stable) begin
+            debounce_cnt <= debounce_cnt + 1;
+            if (debounce_cnt == {POR_BITS{1'b1}}) begin
+                btn_stable   <= btn_sync2;
+                debounce_cnt <= 0;
+            end
+        end else begin
+            debounce_cnt <= 0;
+        end
+    end
+
+    reg [POR_BITS-1:0] por_cnt;
+    reg                por_done;
+
+    always @(posedge clk) begin
+        if (!por_done) begin
+            por_cnt <= por_cnt + 1;
+            if (por_cnt == {POR_BITS{1'b1}})
+                por_done <= 1;
+        end
+    end
+
+    initial begin
+        por_cnt    = 0;
+        por_done   = 0;
+        btn_stable = 0;
+        debounce_cnt = 0;
+    end
+
+    assign rst_n = por_done & ~btn_stable;
+
+    neuromorphic_top #(
+        .CLK_FREQ       (CLK_FREQ),
+        .BAUD           (BAUD),
+        .NUM_CORES      (4),
+        .CORE_ID_BITS   (2),
+        .NUM_NEURONS    (256),
+        .NEURON_BITS    (8),
+        .DATA_WIDTH     (16),
+        .POOL_DEPTH     (8192),
+        .POOL_ADDR_BITS (13),
+        .COUNT_BITS     (6),
+        .REV_FANIN      (16),
+        .REV_SLOT_BITS  (4),
+        .THRESHOLD      (16'sd1000),
+        .LEAK_RATE      (16'sd3),
+        .REFRAC_CYCLES  (3),
+        .ROUTE_FANOUT           (8),
+        .ROUTE_SLOT_BITS        (3),
+        .GLOBAL_ROUTE_SLOTS     (4),
+        .GLOBAL_ROUTE_SLOT_BITS (2),
+        .CHIP_LINK_EN   (0),
+        .NOC_MODE       (0),
+        .MESH_X         (2),
+        .MESH_Y         (2)
+    ) u_neuromorphic (
+        .clk            (clk),
+        .rst_n          (rst_n),
+        .uart_rxd       (uart_rxd),
+        .uart_txd       (uart_txd),
+        .link_tx_data   (),
+        .link_tx_valid  (),
+        .link_tx_ready  (1'b0),
+        .link_rx_data   (8'd0),
+        .link_rx_valid  (1'b0),
+        .link_rx_ready  (),
+        .rx_data_ext    (8'd0),
+        .rx_valid_ext   (1'b0),
+        .tx_data_ext    (),
+        .tx_valid_ext   (),
+        .tx_ready_ext   (1'b0)
+    );
+
+    reg [25:0] heartbeat_cnt;
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n)
+            heartbeat_cnt <= 0;
+        else
+            heartbeat_cnt <= heartbeat_cnt + 1;
+    end
+
+    reg [22:0] rx_blink_cnt;
+    wire       rx_activity;
+    reg        rxd_prev;
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n) begin
+            rxd_prev     <= 1;
+            rx_blink_cnt <= 0;
+        end else begin
+            rxd_prev <= uart_rxd;
+            if (rxd_prev && !uart_rxd)
+                rx_blink_cnt <= {23{1'b1}};
+            else if (rx_blink_cnt != 0)
+                rx_blink_cnt <= rx_blink_cnt - 1;
+        end
+    end
+    assign rx_activity = (rx_blink_cnt != 0);
+
+    reg        txd_prev;
+    reg [22:0] tx_blink_cnt;
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n) begin
+            txd_prev     <= 1;
+            tx_blink_cnt <= 0;
+        end else begin
+            txd_prev <= uart_txd;
+            if (txd_prev && !uart_txd)
+                tx_blink_cnt <= {23{1'b1}};
+            else if (tx_blink_cnt != 0)
+                tx_blink_cnt <= tx_blink_cnt - 1;
+        end
+    end
+
+    reg [22:0] activity_cnt;
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n)
+            activity_cnt <= 0;
+        else if (rx_activity || tx_blink_cnt != 0)
+            activity_cnt <= {23{1'b1}};
+        else if (activity_cnt != 0)
+            activity_cnt <= activity_cnt - 1;
+    end
+
+    always @(*) begin
+        led[0] = heartbeat_cnt[25];
+        led[1] = rx_activity;
+        led[2] = (tx_blink_cnt != 0);
+        led[3] = (activity_cnt != 0);
+    end
+
+endmodule

fpga/host.py

@@ -0,0 +1,418 @@
+"""
+Neuromorphic Chip Host Controller
+==================================
+Python script to communicate with the neuromorphic FPGA over UART.
+
+v1.0 Loihi parity: CSR pool, multicast routing, noise, dual traces,
+axon delays, synapse formats, microcode learning, hierarchical routing.
+
+Usage:
+    python fpga/host.py --port COM3          # Windows
+    python fpga/host.py --port /dev/ttyUSB1  # Linux
+
+Commands:
+    python fpga/host.py --port COM3 --demo   # Run demo (program chain, stimulate, run)
+    python fpga/host.py --port COM3 --status # Query chip status
+"""
+
+import serial
+import struct
+import time
+import argparse
+import sys
+
+
+class NeuromorphicChip:
+    """Interface to the neuromorphic FPGA over UART."""
+
+    # Command opcodes (Phase 13a protocol)
+    CMD_PROG_POOL   = 0x01
+    CMD_PROG_ROUTE  = 0x02
+    CMD_STIMULUS    = 0x03
+    CMD_RUN         = 0x04
+    CMD_STATUS      = 0x05
+    CMD_LEARN_CFG   = 0x06
+    CMD_PROG_NEURON = 0x07
+    CMD_PROG_INDEX  = 0x08
+    CMD_REWARD      = 0x09
+    CMD_PROG_DELAY  = 0x0A
+    CMD_PROG_LEARN  = 0x0C
+    CMD_PROG_GLOBAL_ROUTE = 0x10
+
+    # Parameter IDs for CMD_PROG_NEURON
+    PARAM_THRESHOLD      = 0
+    PARAM_LEAK           = 1
+    PARAM_RESTING        = 2
+    PARAM_REFRAC         = 3
+    PARAM_DEND_THRESHOLD = 4
+
+    # Response codes
+    RESP_ACK  = 0xAA
+    RESP_DONE = 0xDD
+
+    def __init__(self, port, baud=115200, timeout=10):
+        self.ser = serial.Serial(port, baud, timeout=timeout)
+        time.sleep(0.1)
+        self.ser.reset_input_buffer()
+        self._pool_alloc = {}  # per-core pool bump allocator: core -> next_addr
+        print(f"Connected to {port} @ {baud} baud")
+
+    def close(self):
+        self.ser.close()
+
+    def _send(self, data):
+        """Send raw bytes."""
+        self.ser.write(bytes(data))
+
+    def _recv(self, n):
+        """Receive exactly n bytes."""
+        data = self.ser.read(n)
+        if len(data) != n:
+            raise TimeoutError(f"Expected {n} bytes, got {len(data)}")
+        return data
+
+    def _wait_ack(self):
+        """Wait for ACK (0xAA) response."""
+        resp = self._recv(1)
+        if resp[0] != self.RESP_ACK:
+            raise ValueError(f"Expected ACK (0xAA), got 0x{resp[0]:02X}")
+
+    def _alloc_pool(self, core, count=1):
+        """Allocate pool entries for a core (bump allocator)."""
+        if core not in self._pool_alloc:
+            self._pool_alloc[core] = 0
+        addr = self._pool_alloc[core]
+        self._pool_alloc[core] += count
+        return addr
+
+    def prog_pool(self, core, pool_addr, src, target, weight, comp=0):
+        """Program a connection pool entry.
+
+        Args:
+            core: Core ID
+            pool_addr: Pool address (0 to POOL_DEPTH-1)
+            src: Source neuron (for reverse table, 0-1023)
+            target: Target neuron (0-1023)
+            weight: Signed 16-bit weight
+            comp: Compartment ID (0=soma, 1-3=dendrites)
+        """
+        w = weight & 0xFFFF
+        # Pack flags: {comp[1:0], src[9:8], target[9:8], 2'b00}
+        flags = ((comp & 0x3) << 6) | (((src >> 8) & 0x3) << 4) | (((target >> 8) & 0x3) << 2)
+        self._send([
+            self.CMD_PROG_POOL,
+            core & 0xFF,
+            (pool_addr >> 8) & 0xFF, pool_addr & 0xFF,
+            flags,
+            src & 0xFF,
+            target & 0xFF,
+            (w >> 8) & 0xFF, w & 0xFF
+        ])
+        self._wait_ack()
+
+    def prog_index(self, core, neuron, base_addr, count, format=0, base_target=0):
+        """Program a CSR index entry (base_addr + count for a neuron).
+
+        Args:
+            core: Core ID
+            neuron: Neuron ID (0-1023)
+            base_addr: Pool base address
+            count: Number of connections
+            format: Synapse format (0=sparse, 1=dense, 2=pop)
+            base_target: Base target neuron for dense/pop formats
+        """
+        self._send([
+            self.CMD_PROG_INDEX,
+            core & 0xFF,
+            (neuron >> 8) & 0xFF, neuron & 0xFF,
+            (base_addr >> 8) & 0xFF, base_addr & 0xFF,
+            (count >> 8) & 0xFF, count & 0xFF,
+            ((format & 0x3) << 6) | ((base_target >> 8) & 0x3),
+            base_target & 0xFF,
+        ])
+        self._wait_ack()
+
+    def prog_conn(self, core, src, targets_weights, comp=0):
+        """High-level: program connections for a source neuron using pool allocator.
+
+        Args:
+            core: Core ID
+            src: Source neuron
+            targets_weights: List of (target, weight) tuples
+            comp: Compartment ID (default 0=soma)
+        """
+        if not targets_weights:
+            return
+        base = self._alloc_pool(core, len(targets_weights))
+        for i, (target, weight) in enumerate(targets_weights):
+            self.prog_pool(core, base + i, src, target, weight, comp)
+        self.prog_index(core, src, base, len(targets_weights))
+
+    def prog_route(self, src_core, src_neuron, dest_core, dest_neuron, weight, slot=0):
+        """Program an inter-core route (multicast slot).
+
+        Args:
+            src_core: Source core ID
+            src_neuron: Source neuron (0-1023)
+            dest_core: Destination core ID
+            dest_neuron: Destination neuron (0-1023)
+            weight: Signed 16-bit weight
+            slot: Route slot (0-7) for multicast fanout
+        """
+        w = weight & 0xFFFF
+        self._send([
+            self.CMD_PROG_ROUTE,
+            src_core & 0xFF,
+            (src_neuron >> 8) & 0xFF, src_neuron & 0xFF,
+            slot & 0xFF,
+            dest_core & 0xFF,
+            (dest_neuron >> 8) & 0xFF, dest_neuron & 0xFF,
+            (w >> 8) & 0xFF, w & 0xFF
+        ])
+        self._wait_ack()
+
+    def stimulus(self, core, neuron, current):
+        """Set external stimulus current for next RUN.
+
+        Args:
+            core: Target core ID
+            neuron: Target neuron (0-1023)
+            current: Signed 16-bit current value
+        """
+        c = current & 0xFFFF
+        self._send([
+            self.CMD_STIMULUS,
+            core & 0xFF,
+            (neuron >> 8) & 0xFF, neuron & 0xFF,
+            (c >> 8) & 0xFF, c & 0xFF
+        ])
+        self._wait_ack()
+
+    def run(self, timesteps):
+        """Run the mesh for N timesteps.
+
+        Args:
+            timesteps: Number of timesteps (1-65535)
+
+        Returns:
+            Number of spikes that occurred during the run.
+        """
+        ts = timesteps & 0xFFFF
+        self._send([
+            self.CMD_RUN,
+            (ts >> 8) & 0xFF, ts & 0xFF
+        ])
+        resp = self._recv(5)
+        if resp[0] != self.RESP_DONE:
+            raise ValueError(f"Expected DONE (0xDD), got 0x{resp[0]:02X}")
+        spikes = struct.unpack('>I', resp[1:5])[0]
+        return spikes
+
+    def reward(self, value):
+        """Set reward value for 3-factor learning.
+
+        Args:
+            value: Signed 16-bit reward (0 = no reward)
+        """
+        v = value & 0xFFFF
+        self._send([
+            self.CMD_REWARD,
+            (v >> 8) & 0xFF, v & 0xFF
+        ])
+        self._wait_ack()
+
+    def set_learning(self, learn_enable, graded_enable=False, dendritic_enable=False,
+                      async_enable=False, threefactor_enable=False, noise_enable=False):
+        """Configure learning mode flags."""
+        flags = ((int(learn_enable) & 1)
+                 | ((int(graded_enable) & 1) << 1)
+                 | ((int(dendritic_enable) & 1) << 2)
+                 | ((int(async_enable) & 1) << 3)
+                 | ((int(threefactor_enable) & 1) << 4)
+                 | ((int(noise_enable) & 1) << 5))
+        self._send([self.CMD_LEARN_CFG, flags])
+        self._wait_ack()
+
+    def prog_delay(self, core, pool_addr, delay):
+        """Program an axon delay for a pool entry (P17).
+
+        Args:
+            core: Core ID
+            pool_addr: Pool address of the connection
+            delay: Delay in timesteps (0-63)
+        """
+        self._send([
+            self.CMD_PROG_DELAY,
+            core & 0xFF,
+            (pool_addr >> 8) & 0xFF, pool_addr & 0xFF,
+            delay & 0x3F,
+        ])
+        self._wait_ack()
+
+    def prog_learn(self, core, addr, instr):
+        """Program a microcode learning instruction (P19).
+
+        Args:
+            core: Core ID
+            addr: Instruction address (0-63)
+            instr: 32-bit instruction word
+        """
+        self._send([
+            self.CMD_PROG_LEARN,
+            core & 0xFF,
+            addr & 0x3F,
+            (instr >> 24) & 0xFF,
+            (instr >> 16) & 0xFF,
+            (instr >> 8) & 0xFF,
+            instr & 0xFF,
+        ])
+        self._wait_ack()
+
+    def prog_global_route(self, src_core, src_neuron, dest_core, dest_neuron,
+                           weight, slot=0):
+        """Program an inter-cluster global route (P20).
+
+        Args:
+            src_core: Source core ID
+            src_neuron: Source neuron (0-1023)
+            dest_core: Destination core ID
+            dest_neuron: Destination neuron (0-1023)
+            weight: Signed 16-bit weight
+            slot: Route slot (0-3)
+        """
+        w = weight & 0xFFFF
+        self._send([
+            self.CMD_PROG_GLOBAL_ROUTE,
+            src_core & 0xFF,
+            (src_neuron >> 8) & 0xFF, src_neuron & 0xFF,
+            slot & 0xFF,
+            dest_core & 0xFF,
+            (dest_neuron >> 8) & 0xFF, dest_neuron & 0xFF,
+            (w >> 8) & 0xFF, w & 0xFF,
+        ])
+        self._wait_ack()
+
+    def async_mode(self, enable=True):
+        """Enable or disable async event-driven mode."""
+        self.set_learning(False, False, False, async_enable=enable)
+
+    def prog_neuron(self, core, neuron, param_id, value):
+        """Program a per-neuron parameter.
+
+        Args:
+            core: Core ID
+            neuron: Neuron ID (0-1023)
+            param_id: Parameter (PARAM_THRESHOLD=0, PARAM_LEAK=1, etc.)
+            value: Signed 16-bit value
+        """
+        v = value & 0xFFFF
+        self._send([
+            self.CMD_PROG_NEURON,
+            core & 0xFF,
+            (neuron >> 8) & 0xFF, neuron & 0xFF,
+            param_id & 0xFF,
+            (v >> 8) & 0xFF, v & 0xFF
+        ])
+        self._wait_ack()
+
+    def status(self):
+        """Query chip status.
+
+        Returns:
+            Tuple of (state, timestep_count)
+        """
+        self._send([self.CMD_STATUS])
+        resp = self._recv(5)
+        state = resp[0]
+        ts_count = struct.unpack('>I', resp[1:5])[0]
+        return state, ts_count
+
+
+def demo(chip):
+    """Run a demonstration: program a spike chain and observe propagation."""
+
+    print("\n" + "=" * 60)
+    print("  Neuromorphic Chip Demo (Phase 13b: CSR + Multicast)")
+    print("=" * 60)
+
+    state, ts = chip.status()
+    print(f"\nInitial status: state={state}, timesteps={ts}")
+
+    # Program a spike chain: Core 0, N0→N1→N2→N3
+    print("\nProgramming spike chain: Core 0, N0 -> N1 -> N2 -> N3")
+    chip.prog_conn(0, 0, [(1, 1200)])
+    print("  N0 -> N1 (w=1200) OK")
+    chip.prog_conn(0, 1, [(2, 1200)])
+    print("  N1 -> N2 (w=1200) OK")
+    chip.prog_conn(0, 2, [(3, 1200)])
+    print("  N2 -> N3 (w=1200) OK")
+
+    # Program cross-core route: Core 0 N3 → Core 1 N0
+    print("\nProgramming cross-core route: C0:N3 -> C1:N0")
+    chip.prog_route(src_core=0, src_neuron=3,
+                    dest_core=1, dest_neuron=0, weight=1200)
+    print("  Route OK")
+
+    # Core 1 chain
+    print("Programming Core 1 chain: N0 -> N1 -> N2")
+    chip.prog_conn(1, 0, [(1, 1200)])
+    chip.prog_conn(1, 1, [(2, 1200)])
+    print("  Core 1 chain OK")
+
+    # Stimulate and run
+    print("\nApplying stimulus: Core 0, N0, current=1200")
+    chip.stimulus(core=0, neuron=0, current=1200)
+
+    print("Running 20 timesteps...")
+    t_start = time.time()
+    spikes = chip.run(20)
+    elapsed = time.time() - t_start
+    print(f"  Done! {spikes} spikes in {elapsed:.3f}s")
+
+    # Run more without stimulus
+    print("\nRunning 10 more timesteps (no stimulus)...")
+    spikes2 = chip.run(10)
+    print(f"  {spikes2} spikes (should be 0 - no input)")
+
+    # Final status
+    state, ts = chip.status()
+    print(f"\nFinal status: state={state}, timesteps={ts}")
+
+    print("\n" + "=" * 60)
+    print("  Demo complete! The chip is alive.")
+    print("=" * 60)
+
+
+def main():
+    parser = argparse.ArgumentParser(description="Neuromorphic Chip Host Controller")
+    parser.add_argument("--port", required=True, help="Serial port (e.g., COM3 or /dev/ttyUSB1)")
+    parser.add_argument("--baud", type=int, default=115200, help="Baud rate (default: 115200)")
+    parser.add_argument("--demo", action="store_true", help="Run demo program")
+    parser.add_argument("--status", action="store_true", help="Query chip status")
+    args = parser.parse_args()
+
+    chip = NeuromorphicChip(args.port, args.baud)
+
+    try:
+        if args.status:
+            state, ts = chip.status()
+            print(f"State: {state} ({'idle' if state == 0 else 'busy'})")
+            print(f"Timestep count: {ts}")
+        elif args.demo:
+            demo(chip)
+        else:
+            print("No command specified. Use --demo or --status")
+            print("Or import NeuromorphicChip in Python for programmatic access:")
+            print("")
+            print("  from host import NeuromorphicChip")
+            print("  chip = NeuromorphicChip('COM3')")
+            print("  chip.prog_conn(0, 0, [(1, 1200), (2, 800)])  # N0 -> N1(w=1200), N2(w=800)")
+            print("  chip.prog_index(0, 0, 0, 2)  # Or use prog_conn() which handles this")
+            print("  chip.stimulus(core=0, neuron=0, current=1200)")
+            print("  spikes = chip.run(100)")
+    finally:
+        chip.close()
+
+
+if __name__ == "__main__":
+    main()

fpga/kria/build_kria.tcl

@@ -0,0 +1,73 @@
+# ============================================================================
+# Vivado Build Script — Kria KV260 Target — Catalyst N1 (Loihi 1 Parity)
+# ============================================================================
+# Usage: vivado -mode batch -source fpga/kria/build_kria.tcl -tclargs synth_only
+# ============================================================================
+
+set script_dir  [file dirname [file normalize [info script]]]
+set project_dir "${script_dir}/build"
+set part        "xczu5ev-sfvc784-2-i"
+set rtl_dir     "[file normalize ${script_dir}/../../rtl]"
+set kria_dir    $script_dir
+
+set mode "full"
+if {[llength $argv] > 0} {
+    set mode [lindex $argv 0]
+}
+
+puts "============================================"
+puts "  Catalyst N1 — Kria KV260 Build"
+puts "  Mode: $mode"
+puts "  Part: $part"
+puts "============================================"
+
+file mkdir $project_dir
+create_project catalyst_kria_n1 $project_dir -part $part -force
+
+set rtl_files [list \
+    ${rtl_dir}/sram.v \
+    ${rtl_dir}/spike_fifo.v \
+    ${rtl_dir}/async_fifo.v \
+    ${rtl_dir}/uart_tx.v \
+    ${rtl_dir}/uart_rx.v \
+    ${rtl_dir}/scalable_core_v2.v \
+    ${rtl_dir}/neuromorphic_mesh.v \
+    ${rtl_dir}/async_noc_mesh.v \
+    ${rtl_dir}/async_router.v \
+    ${rtl_dir}/sync_tree.v \
+    ${rtl_dir}/chip_link.v \
+    ${rtl_dir}/host_interface.v \
+    ${rtl_dir}/axi_uart_bridge.v \
+    ${rtl_dir}/neuromorphic_top.v \
+    ${kria_dir}/kria_neuromorphic.v \
+]
+add_files -norecurse $rtl_files
+update_compile_order -fileset sources_1
+
+if {$mode eq "synth_only"} {
+    puts "============================================"
+    puts "  SYNTHESIS-ONLY MODE"
+    puts "============================================"
+
+    set_property top kria_neuromorphic [current_fileset]
+    update_compile_order -fileset sources_1
+
+    launch_runs synth_1 -jobs 4
+    wait_on_run synth_1
+    open_run synth_1
+
+    report_utilization -file ${project_dir}/synth_utilization.rpt
+    report_utilization -hierarchical -file ${project_dir}/synth_utilization_hier.rpt
+    report_timing_summary -file ${project_dir}/synth_timing.rpt
+
+    puts ""
+    puts "============================================"
+    puts "  N1 SYNTHESIS COMPLETE"
+    puts "============================================"
+    report_utilization -return_string
+
+    close_project
+    exit
+}
+
+close_project

fpga/kria/kria_neuromorphic.v

@@ -0,0 +1,143 @@
+// ============================================================================
+// Kria KV260 Neuromorphic PL Wrapper — Catalyst N1 (Loihi 1 Parity)
+// ============================================================================
+//
+// Catalyst N1 v2.3 — Zynq UltraScale+ ZU5EV target (2 cores x 256 neurons)
+// 2-core variant for Kria K26 resource characterization.
+//
+// VERSION_ID: 0xA0_23_02_01
+//   A0 = Kria platform, 23 = N1 v2.3, 02 = 2-core, 01 = N1 generation
+// ============================================================================
+// ============================================================================
+// Copyright 2026 Henry Arthur Shulayev Barnes / Catalyst Neuromorphic Ltd
+// Company No. 17054540 — UK Patent Application No. 2602902.6
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// ============================================================================
+
+module kria_neuromorphic #(
+    parameter NUM_CORES      = 2,
+    parameter CORE_ID_BITS   = 1,
+    parameter NUM_NEURONS    = 256,
+    parameter NEURON_BITS    = 8,
+    parameter POOL_DEPTH     = 4096,
+    parameter POOL_ADDR_BITS = 12,
+    parameter COUNT_BITS     = 8,
+    parameter VERSION_ID     = 32'hA0_23_02_01
+)(
+    input  wire        s_axi_aclk,
+    input  wire        s_axi_aresetn,
+    input  wire [31:0] s_axi_awaddr,
+    input  wire        s_axi_awvalid,
+    output wire        s_axi_awready,
+    input  wire [31:0] s_axi_wdata,
+    input  wire [3:0]  s_axi_wstrb,
+    input  wire        s_axi_wvalid,
+    output wire        s_axi_wready,
+    output wire [1:0]  s_axi_bresp,
+    output wire        s_axi_bvalid,
+    input  wire        s_axi_bready,
+    input  wire [31:0] s_axi_araddr,
+    input  wire        s_axi_arvalid,
+    output wire        s_axi_arready,
+    output wire [31:0] s_axi_rdata,
+    output wire [1:0]  s_axi_rresp,
+    output wire        s_axi_rvalid,
+    input  wire        s_axi_rready
+);
+
+    wire clk   = s_axi_aclk;
+    wire rst_n = s_axi_aresetn;
+
+    wire [7:0] bridge_rx_data;
+    wire       bridge_rx_valid;
+    wire [7:0] bridge_tx_data;
+    wire       bridge_tx_valid;
+    wire       bridge_tx_ready;
+
+    axi_uart_bridge #(
+        .VERSION_ID (VERSION_ID),
+        .NUM_CORES  (NUM_CORES)
+    ) u_bridge (
+        .clk          (clk),
+        .rst_n        (rst_n),
+        .clk_neuro    (clk),
+        .rst_neuro_n  (rst_n),
+        .s_axi_awaddr (s_axi_awaddr),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_awready(s_axi_awready),
+        .s_axi_wdata  (s_axi_wdata),
+        .s_axi_wstrb  (s_axi_wstrb),
+        .s_axi_wvalid (s_axi_wvalid),
+        .s_axi_wready (s_axi_wready),
+        .s_axi_bresp  (s_axi_bresp),
+        .s_axi_bvalid (s_axi_bvalid),
+        .s_axi_bready (s_axi_bready),
+        .s_axi_araddr (s_axi_araddr),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_rdata  (s_axi_rdata),
+        .s_axi_rresp  (s_axi_rresp),
+        .s_axi_rvalid (s_axi_rvalid),
+        .s_axi_rready (s_axi_rready),
+        .hi_rx_data   (bridge_rx_data),
+        .hi_rx_valid  (bridge_rx_valid),
+        .hi_tx_data   (bridge_tx_data),
+        .hi_tx_valid  (bridge_tx_valid),
+        .hi_tx_ready  (bridge_tx_ready)
+    );
+
+    neuromorphic_top #(
+        .CLK_FREQ       (100_000_000),
+        .BAUD           (115200),
+        .BYPASS_UART    (1),
+        .NUM_CORES      (NUM_CORES),
+        .CORE_ID_BITS   (CORE_ID_BITS),
+        .NUM_NEURONS    (NUM_NEURONS),
+        .NEURON_BITS    (NEURON_BITS),
+        .DATA_WIDTH     (16),
+        .POOL_DEPTH     (POOL_DEPTH),
+        .POOL_ADDR_BITS (POOL_ADDR_BITS),
+        .COUNT_BITS     (COUNT_BITS),
+        .REV_FANIN      (16),
+        .REV_SLOT_BITS  (4),
+        .THRESHOLD      (16'sd1000),
+        .LEAK_RATE      (16'sd3),
+        .REFRAC_CYCLES  (3),
+        .ROUTE_FANOUT           (8),
+        .ROUTE_SLOT_BITS        (3),
+        .GLOBAL_ROUTE_SLOTS     (4),
+        .GLOBAL_ROUTE_SLOT_BITS (2),
+        .CHIP_LINK_EN   (0),
+        .NOC_MODE       (0),
+        .MESH_X         (2),
+        .MESH_Y         (1)
+    ) u_neuromorphic (
+        .clk            (clk),
+        .rst_n          (rst_n),
+        .uart_rxd       (1'b1),
+        .uart_txd       (),
+        .rx_data_ext    (bridge_rx_data),
+        .rx_valid_ext   (bridge_rx_valid),
+        .tx_data_ext    (bridge_tx_data),
+        .tx_valid_ext   (bridge_tx_valid),
+        .tx_ready_ext   (bridge_tx_ready),
+        .link_tx_data   (),
+        .link_tx_valid  (),
+        .link_tx_ready  (1'b0),
+        .link_rx_data   (8'b0),
+        .link_rx_valid  (1'b0),
+        .link_rx_ready  ()
+    );
+
+endmodule

fpga/kria/kria_neuromorphic_8core_backup.v

@@ -0,0 +1,143 @@
+// ============================================================================
+// Kria KV260 Neuromorphic PL Wrapper — Catalyst N1 (Loihi 1 Parity)
+// ============================================================================
+//
+// Catalyst N1 v2.3 — Zynq UltraScale+ ZU5EV target (8 cores x 256 neurons)
+// Same architecture as N2 wrapper but with N1 RTL (simpler, less resource usage).
+//
+// VERSION_ID: 0xA0_23_08_01
+//   A0 = Kria platform, 23 = N1 v2.3, 08 = 8-core, 01 = N1 generation
+// ============================================================================
+// ============================================================================
+// Copyright 2026 Henry Arthur Shulayev Barnes / Catalyst Neuromorphic Ltd
+// Company No. 17054540 — UK Patent Application No. 2602902.6
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// ============================================================================
+
+module kria_neuromorphic #(
+    parameter NUM_CORES      = 8,
+    parameter CORE_ID_BITS   = 3,
+    parameter NUM_NEURONS    = 256,
+    parameter NEURON_BITS    = 8,
+    parameter POOL_DEPTH     = 4096,
+    parameter POOL_ADDR_BITS = 12,
+    parameter COUNT_BITS     = 8,
+    parameter VERSION_ID     = 32'hA0_23_08_01
+)(
+    input  wire        s_axi_aclk,
+    input  wire        s_axi_aresetn,
+    input  wire [31:0] s_axi_awaddr,
+    input  wire        s_axi_awvalid,
+    output wire        s_axi_awready,
+    input  wire [31:0] s_axi_wdata,
+    input  wire [3:0]  s_axi_wstrb,
+    input  wire        s_axi_wvalid,
+    output wire        s_axi_wready,
+    output wire [1:0]  s_axi_bresp,
+    output wire        s_axi_bvalid,
+    input  wire        s_axi_bready,
+    input  wire [31:0] s_axi_araddr,
+    input  wire        s_axi_arvalid,
+    output wire        s_axi_arready,
+    output wire [31:0] s_axi_rdata,
+    output wire [1:0]  s_axi_rresp,
+    output wire        s_axi_rvalid,
+    input  wire        s_axi_rready
+);
+
+    wire clk   = s_axi_aclk;
+    wire rst_n = s_axi_aresetn;
+
+    wire [7:0] bridge_rx_data;
+    wire       bridge_rx_valid;
+    wire [7:0] bridge_tx_data;
+    wire       bridge_tx_valid;
+    wire       bridge_tx_ready;
+
+    axi_uart_bridge #(
+        .VERSION_ID (VERSION_ID),
+        .NUM_CORES  (NUM_CORES)
+    ) u_bridge (
+        .clk          (clk),
+        .rst_n        (rst_n),
+        .clk_neuro    (clk),
+        .rst_neuro_n  (rst_n),
+        .s_axi_awaddr (s_axi_awaddr),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_awready(s_axi_awready),
+        .s_axi_wdata  (s_axi_wdata),
+        .s_axi_wstrb  (s_axi_wstrb),
+        .s_axi_wvalid (s_axi_wvalid),
+        .s_axi_wready (s_axi_wready),
+        .s_axi_bresp  (s_axi_bresp),
+        .s_axi_bvalid (s_axi_bvalid),
+        .s_axi_bready (s_axi_bready),
+        .s_axi_araddr (s_axi_araddr),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_rdata  (s_axi_rdata),
+        .s_axi_rresp  (s_axi_rresp),
+        .s_axi_rvalid (s_axi_rvalid),
+        .s_axi_rready (s_axi_rready),
+        .hi_rx_data   (bridge_rx_data),
+        .hi_rx_valid  (bridge_rx_valid),
+        .hi_tx_data   (bridge_tx_data),
+        .hi_tx_valid  (bridge_tx_valid),
+        .hi_tx_ready  (bridge_tx_ready)
+    );
+
+    neuromorphic_top #(
+        .CLK_FREQ       (100_000_000),
+        .BAUD           (115200),
+        .BYPASS_UART    (1),
+        .NUM_CORES      (NUM_CORES),
+        .CORE_ID_BITS   (CORE_ID_BITS),
+        .NUM_NEURONS    (NUM_NEURONS),
+        .NEURON_BITS    (NEURON_BITS),
+        .DATA_WIDTH     (16),
+        .POOL_DEPTH     (POOL_DEPTH),
+        .POOL_ADDR_BITS (POOL_ADDR_BITS),
+        .COUNT_BITS     (COUNT_BITS),
+        .REV_FANIN      (16),
+        .REV_SLOT_BITS  (4),
+        .THRESHOLD      (16'sd1000),
+        .LEAK_RATE      (16'sd3),
+        .REFRAC_CYCLES  (3),
+        .ROUTE_FANOUT           (8),
+        .ROUTE_SLOT_BITS        (3),
+        .GLOBAL_ROUTE_SLOTS     (4),
+        .GLOBAL_ROUTE_SLOT_BITS (2),
+        .CHIP_LINK_EN   (0),
+        .NOC_MODE       (0),
+        .MESH_X         (2),
+        .MESH_Y         (4)
+    ) u_neuromorphic (
+        .clk            (clk),
+        .rst_n          (rst_n),
+        .uart_rxd       (1'b1),
+        .uart_txd       (),
+        .rx_data_ext    (bridge_rx_data),
+        .rx_valid_ext   (bridge_rx_valid),
+        .tx_data_ext    (bridge_tx_data),
+        .tx_valid_ext   (bridge_tx_valid),
+        .tx_ready_ext   (bridge_tx_ready),
+        .link_tx_data   (),
+        .link_tx_valid  (),
+        .link_tx_ready  (1'b0),
+        .link_rx_data   (8'b0),
+        .link_rx_valid  (1'b0),
+        .link_rx_ready  ()
+    );
+
+endmodule

fpga/kria/run_impl.tcl

@@ -0,0 +1,68 @@
+# ============================================================================
+# Vivado Implementation Script — Kria K26 — Catalyst N1 (Loihi 1 Parity)
+# ============================================================================
+# Opens existing synthesis checkpoint and runs Place & Route + reports
+# Usage: vivado -mode batch -source fpga/kria/run_impl.tcl
+# ============================================================================
+
+set script_dir  [file dirname [file normalize [info script]]]
+set project_dir "${script_dir}/build"
+set synth_dcp   "${project_dir}/catalyst_kria_n1.runs/synth_1/kria_neuromorphic.dcp"
+set out_dir     "${project_dir}/impl_results"
+
+file mkdir $out_dir
+
+puts "============================================"
+puts "  Catalyst N1 — Kria K26 Implementation"
+puts "  Loading: $synth_dcp"
+puts "============================================"
+
+# Open synthesis checkpoint
+open_checkpoint $synth_dcp
+
+# Add clock constraint — Kria K26 PS provides 100 MHz PL clock
+create_clock -period 10.000 -name sys_clk [get_ports s_axi_aclk]
+
+# Set IO delay constraints (generic, for timing closure)
+set_input_delay -clock sys_clk -max 2.0 [get_ports -filter {DIRECTION == IN && NAME != "s_axi_aclk"}]
+set_output_delay -clock sys_clk -max 2.0 [get_ports -filter {DIRECTION == OUT}]
+
+# Run implementation
+puts "Running opt_design..."
+opt_design
+
+puts "Running place_design..."
+place_design
+
+puts "Running phys_opt_design..."
+phys_opt_design
+
+puts "Running route_design..."
+route_design
+
+# Save implemented checkpoint
+write_checkpoint -force ${out_dir}/kria_n1_impl.dcp
+
+# Generate reports
+puts "Generating reports..."
+report_timing_summary -file ${out_dir}/timing_summary.rpt
+report_timing -max_paths 20 -file ${out_dir}/timing_paths.rpt
+report_utilization -file ${out_dir}/utilization.rpt
+report_utilization -hierarchical -file ${out_dir}/utilization_hier.rpt
+report_power -file ${out_dir}/power.rpt
+report_clock_utilization -file ${out_dir}/clock_utilization.rpt
+report_design_analysis -file ${out_dir}/design_analysis.rpt
+
+puts ""
+puts "============================================"
+puts "  N1 IMPLEMENTATION COMPLETE"
+puts "============================================"
+puts "Reports in: $out_dir"
+
+# Print summary to console
+report_timing_summary -return_string
+report_utilization -return_string
+report_power -return_string
+
+close_design
+exit

rtl/async_fifo.v

@@ -0,0 +1,96 @@
+// ============================================================================
+// Async FIFO
+// ============================================================================
+//
+// Copyright 2026 Henry Arthur Shulayev Barnes / Catalyst Neuromorphic Ltd
+// Company No. 17054540 — UK Patent Application No. 2602902.6
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// ============================================================================
+module async_fifo #(
+    parameter DATA_WIDTH = 8,
+    parameter ADDR_BITS  = 4
+)(
+    input  wire                  wr_clk,
+    input  wire                  wr_rst_n,
+    input  wire [DATA_WIDTH-1:0] wr_data,
+    input  wire                  wr_en,
+    output wire                  wr_full,
+
+    input  wire                  rd_clk,
+    input  wire                  rd_rst_n,
+    input  wire                  rd_en,
+    output wire [DATA_WIDTH-1:0] rd_data,
+    output wire                  rd_empty
+);
+
+    localparam DEPTH = 1 << ADDR_BITS;
+
+    reg [DATA_WIDTH-1:0] mem [0:DEPTH-1];
+
+    reg [ADDR_BITS:0] wr_bin, wr_gray;
+    wire [ADDR_BITS:0] wr_bin_next  = wr_bin + 1;
+    wire [ADDR_BITS:0] wr_gray_next = wr_bin_next ^ (wr_bin_next >> 1);
+
+    reg [ADDR_BITS:0] rd_bin, rd_gray;
+    wire [ADDR_BITS:0] rd_bin_next  = rd_bin + 1;
+    wire [ADDR_BITS:0] rd_gray_next = rd_bin_next ^ (rd_bin_next >> 1);
+
+    reg [ADDR_BITS:0] wr_gray_rd_s1, wr_gray_rd_s2;
+    reg [ADDR_BITS:0] rd_gray_wr_s1, rd_gray_wr_s2;
+
+    always @(posedge wr_clk or negedge wr_rst_n)
+        if (!wr_rst_n) begin
+            wr_bin  <= 0;
+            wr_gray <= 0;
+        end else if (wr_en && !wr_full) begin
+            mem[wr_bin[ADDR_BITS-1:0]] <= wr_data;
+            wr_bin  <= wr_bin_next;
+            wr_gray <= wr_gray_next;
+        end
+
+    always @(posedge rd_clk or negedge rd_rst_n)
+        if (!rd_rst_n) begin
+            rd_bin  <= 0;
+            rd_gray <= 0;
+        end else if (rd_en && !rd_empty) begin
+            rd_bin  <= rd_bin_next;
+            rd_gray <= rd_gray_next;
+        end
+
+    always @(posedge rd_clk or negedge rd_rst_n)
+        if (!rd_rst_n) begin
+            wr_gray_rd_s1 <= 0;
+            wr_gray_rd_s2 <= 0;
+        end else begin
+            wr_gray_rd_s1 <= wr_gray;
+            wr_gray_rd_s2 <= wr_gray_rd_s1;
+        end
+
+    always @(posedge wr_clk or negedge wr_rst_n)
+        if (!wr_rst_n) begin
+            rd_gray_wr_s1 <= 0;
+            rd_gray_wr_s2 <= 0;
+        end else begin
+            rd_gray_wr_s1 <= rd_gray;
+            rd_gray_wr_s2 <= rd_gray_wr_s1;
+        end
+
+    assign wr_full  = (wr_gray == {~rd_gray_wr_s2[ADDR_BITS:ADDR_BITS-1],
+                                     rd_gray_wr_s2[ADDR_BITS-2:0]});
+
+    assign rd_empty = (rd_gray == wr_gray_rd_s2);
+
+    assign rd_data  = mem[rd_bin[ADDR_BITS-1:0]];
+
+endmodule

rtl/async_noc_mesh.v

@@ -0,0 +1,701 @@
+// ============================================================================
+// Async NoC Mesh
+// ============================================================================
+//
+// Copyright 2026 Henry Arthur Shulayev Barnes / Catalyst Neuromorphic Ltd
+// Company No. 17054540 — UK Patent Application No. 2602902.6
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// ============================================================================
+
+`timescale 1ns/1ps
+
+module async_noc_mesh #(
+    parameter NUM_CORES      = 4,
+    parameter CORE_ID_BITS   = 2,
+    parameter NUM_NEURONS    = 1024,
+    parameter NEURON_BITS    = 10,
+    parameter DATA_WIDTH     = 16,
+    parameter POOL_DEPTH     = 32768,
+    parameter POOL_ADDR_BITS = 15,
+    parameter COUNT_BITS     = 12,
+    parameter REV_FANIN      = 32,
+    parameter REV_SLOT_BITS  = 5,
+    parameter THRESHOLD      = 16'sd1000,
+    parameter LEAK_RATE      = 16'sd3,
+    parameter REFRAC_CYCLES  = 3,
+    parameter GRADE_SHIFT    = 7,
+    parameter ROUTE_FANOUT     = 8,
+    parameter ROUTE_SLOT_BITS  = 3,
+    parameter ROUTE_ADDR_W   = CORE_ID_BITS + NEURON_BITS + ROUTE_SLOT_BITS,
+    parameter ROUTE_DATA_W   = 1 + CORE_ID_BITS + NEURON_BITS + DATA_WIDTH,
+    parameter CLUSTER_SIZE          = 4,
+    parameter GLOBAL_ROUTE_SLOTS    = 4,
+    parameter GLOBAL_ROUTE_SLOT_BITS = 2,
+    parameter GLOBAL_ROUTE_ADDR_W   = CORE_ID_BITS + NEURON_BITS + GLOBAL_ROUTE_SLOT_BITS,
+    parameter CHIP_LINK_EN = 0,
+    parameter DUAL_NOC = 0,
+    parameter MESH_X = 2,
+    parameter MESH_Y = 2
+)(
+    input  wire                    clk,
+    input  wire                    rst_n,
+    input  wire                    start,
+    input  wire                         prog_pool_we,
+    input  wire [CORE_ID_BITS-1:0]      prog_pool_core,
+    input  wire [POOL_ADDR_BITS-1:0]    prog_pool_addr,
+    input  wire [NEURON_BITS-1:0]       prog_pool_src,
+    input  wire [NEURON_BITS-1:0]       prog_pool_target,
+    input  wire signed [DATA_WIDTH-1:0] prog_pool_weight,
+    input  wire [1:0]                   prog_pool_comp,
+    input  wire                         prog_index_we,
+    input  wire [CORE_ID_BITS-1:0]      prog_index_core,
+    input  wire [NEURON_BITS-1:0]       prog_index_neuron,
+    input  wire [POOL_ADDR_BITS-1:0]    prog_index_base,
+    input  wire [COUNT_BITS-1:0]        prog_index_count,
+    input  wire [1:0]                   prog_index_format,
+    input  wire                        prog_route_we,
+    input  wire [CORE_ID_BITS-1:0]     prog_route_src_core,
+    input  wire [NEURON_BITS-1:0]      prog_route_src_neuron,
+    input  wire [ROUTE_SLOT_BITS-1:0]  prog_route_slot,
+    input  wire [CORE_ID_BITS-1:0]     prog_route_dest_core,
+    input  wire [NEURON_BITS-1:0]      prog_route_dest_neuron,
+    input  wire signed [DATA_WIDTH-1:0] prog_route_weight,
+    input  wire                        prog_global_route_we,
+    input  wire [CORE_ID_BITS-1:0]     prog_global_route_src_core,
+    input  wire [NEURON_BITS-1:0]      prog_global_route_src_neuron,
+    input  wire [GLOBAL_ROUTE_SLOT_BITS-1:0] prog_global_route_slot,
+    input  wire [CORE_ID_BITS-1:0]     prog_global_route_dest_core,
+    input  wire [NEURON_BITS-1:0]      prog_global_route_dest_neuron,
+    input  wire signed [DATA_WIDTH-1:0] prog_global_route_weight,
+    input  wire                        learn_enable,
+    input  wire                        graded_enable,
+    input  wire                        dendritic_enable,
+    input  wire                        async_enable,
+    input  wire                        threefactor_enable,
+    input  wire                        noise_enable,
+    input  wire                        skip_idle_enable,
+    input  wire                        scale_u_enable,
+    input  wire signed [DATA_WIDTH-1:0] reward_value,
+    input  wire                        prog_delay_we,
+    input  wire [CORE_ID_BITS-1:0]     prog_delay_core,
+    input  wire [POOL_ADDR_BITS-1:0]   prog_delay_addr,
+    input  wire [5:0]                  prog_delay_value,
+    input  wire                        prog_ucode_we,
+    input  wire [CORE_ID_BITS-1:0]     prog_ucode_core,
+    input  wire [7:0]                  prog_ucode_addr,
+    input  wire [31:0]                 prog_ucode_data,
+    input  wire                        prog_param_we,
+    input  wire [CORE_ID_BITS-1:0]     prog_param_core,
+    input  wire [NEURON_BITS-1:0]      prog_param_neuron,
+    input  wire [4:0]                  prog_param_id,
+    input  wire signed [DATA_WIDTH-1:0] prog_param_value,
+    input  wire                        ext_valid,
+    input  wire [CORE_ID_BITS-1:0]     ext_core,
+    input  wire [NEURON_BITS-1:0]      ext_neuron_id,
+    input  wire signed [DATA_WIDTH-1:0] ext_current,
+    input  wire                        probe_read,
+    input  wire [CORE_ID_BITS-1:0]     probe_core,
+    input  wire [NEURON_BITS-1:0]      probe_neuron,
+    input  wire [4:0]                  probe_state_id,
+    input  wire [POOL_ADDR_BITS-1:0]   probe_pool_addr,
+    output wire signed [DATA_WIDTH-1:0] probe_data,
+    output wire                         probe_valid,
+    output reg                         timestep_done,
+    output wire [NUM_CORES-1:0]        spike_valid_bus,
+    output wire [NUM_CORES*NEURON_BITS-1:0] spike_id_bus,
+    output wire [5:0]                  mesh_state_out,
+    output reg  [31:0]                 total_spikes,
+    output reg  [31:0]                 timestep_count,
+    output wire [NUM_CORES-1:0]        core_idle_bus,
+    output wire                        link_tx_push,
+    output wire [CORE_ID_BITS-1:0]     link_tx_core,
+    output wire [NEURON_BITS-1:0]      link_tx_neuron,
+    output wire [7:0]                  link_tx_payload,
+    input  wire                        link_tx_full,
+    input  wire [CORE_ID_BITS-1:0]     link_rx_core,
+    input  wire [NEURON_BITS-1:0]      link_rx_neuron,
+    input  wire signed [DATA_WIDTH-1:0] link_rx_current,
+    output wire                        link_rx_pop,
+    input  wire                        link_rx_empty
+);
+
+    assign link_tx_push = 0;
+    assign link_tx_core = 0;
+    assign link_tx_neuron = 0;
+    assign link_tx_payload = 0;
+    assign link_rx_pop = 0;
+
+    localparam COORD_BITS = 4;
+    localparam PACKET_W   = 2*COORD_BITS + NEURON_BITS + DATA_WIDTH;
+
+    function [COORD_BITS-1:0] core_to_x;
+        input [CORE_ID_BITS-1:0] cid;
+        core_to_x = cid % MESH_X;
+    endfunction
+
+    function [COORD_BITS-1:0] core_to_y;
+        input [CORE_ID_BITS-1:0] cid;
+        core_to_y = cid / MESH_X;
+    endfunction
+
+    localparam SM_IDLE       = 4'd0;
+    localparam SM_PKT_DRAIN  = 4'd1;
+    localparam SM_START      = 4'd2;
+    localparam SM_RUN_WAIT   = 4'd3;
+    localparam SM_ROUTE_POP  = 4'd4;
+    localparam SM_ROUTE_ADDR = 4'd5;
+    localparam SM_ROUTE_WAIT = 4'd6;
+    localparam SM_ROUTE_READ = 4'd7;
+    localparam SM_GRT_ADDR   = 4'd8;
+    localparam SM_GRT_WAIT   = 4'd9;
+    localparam SM_GRT_READ   = 4'd10;
+    localparam SM_DONE       = 4'd11;
+
+    reg [3:0] mesh_state;
+    assign mesh_state_out = {2'b0, mesh_state};
+
+    reg                      rt_we;
+    reg  [ROUTE_ADDR_W-1:0]  rt_addr;
+    wire [ROUTE_DATA_W-1:0]  rt_rdata;
+
+    wire                     rt_we_mux   = (mesh_state == SM_IDLE) ? prog_route_we : rt_we;
+    wire [ROUTE_ADDR_W-1:0]  rt_addr_mux = (mesh_state == SM_IDLE) ?
+        {prog_route_src_core, prog_route_src_neuron, prog_route_slot} : rt_addr;
+    wire [ROUTE_DATA_W-1:0]  rt_wdata_mux = (mesh_state == SM_IDLE) ?
+        {1'b1, prog_route_dest_core, prog_route_dest_neuron, prog_route_weight} : {ROUTE_DATA_W{1'b0}};
+
+    sram #(.DATA_WIDTH(ROUTE_DATA_W), .ADDR_WIDTH(ROUTE_ADDR_W)) route_table (
+        .clk(clk), .we_a(rt_we_mux), .addr_a(rt_addr_mux),
+        .wdata_a(rt_wdata_mux), .rdata_a(rt_rdata),
+        .addr_b({ROUTE_ADDR_W{1'b0}}), .rdata_b()
+    );
+
+    wire                       rt_valid     = rt_rdata[ROUTE_DATA_W-1];
+    wire [CORE_ID_BITS-1:0]    rt_dest_core = rt_rdata[NEURON_BITS+DATA_WIDTH +: CORE_ID_BITS];
+    wire [NEURON_BITS-1:0]     rt_dest_nrn  = rt_rdata[DATA_WIDTH +: NEURON_BITS];
+    wire signed [DATA_WIDTH-1:0] rt_weight  = rt_rdata[DATA_WIDTH-1:0];
+
+    reg                               grt_we;
+    reg  [GLOBAL_ROUTE_ADDR_W-1:0]   grt_addr;
+    wire [ROUTE_DATA_W-1:0]          grt_rdata;
+
+    wire grt_we_mux = (mesh_state == SM_IDLE) ? prog_global_route_we : grt_we;
+    wire [GLOBAL_ROUTE_ADDR_W-1:0] grt_addr_mux = (mesh_state == SM_IDLE) ?
+        {prog_global_route_src_core, prog_global_route_src_neuron, prog_global_route_slot} : grt_addr;
+    wire [ROUTE_DATA_W-1:0] grt_wdata_mux = (mesh_state == SM_IDLE) ?
+        {1'b1, prog_global_route_dest_core, prog_global_route_dest_neuron, prog_global_route_weight} : {ROUTE_DATA_W{1'b0}};
+
+    sram #(.DATA_WIDTH(ROUTE_DATA_W), .ADDR_WIDTH(GLOBAL_ROUTE_ADDR_W)) global_route_table (
+        .clk(clk), .we_a(grt_we_mux), .addr_a(grt_addr_mux),
+        .wdata_a(grt_wdata_mux), .rdata_a(grt_rdata),
+        .addr_b({GLOBAL_ROUTE_ADDR_W{1'b0}}), .rdata_b()
+    );
+
+    wire                       grt_valid     = grt_rdata[ROUTE_DATA_W-1];
+    wire [CORE_ID_BITS-1:0]    grt_dest_core = grt_rdata[NEURON_BITS+DATA_WIDTH +: CORE_ID_BITS];
+    wire [NEURON_BITS-1:0]     grt_dest_nrn  = grt_rdata[DATA_WIDTH +: NEURON_BITS];
+    wire signed [DATA_WIDTH-1:0] grt_weight  = grt_rdata[DATA_WIDTH-1:0];
+
+    wire [NUM_CORES-1:0]                core_done;
+    wire [NUM_CORES-1:0]                core_spike_valid;
+    wire [NUM_CORES*NEURON_BITS-1:0]    core_spike_id;
+    wire [NUM_CORES*8-1:0]              core_spike_payload;
+    reg  [NUM_CORES-1:0]                core_start_r;
+
+    reg  [NUM_CORES-1:0] core_done_latch;
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n)
+            core_done_latch <= 0;
+        else if (mesh_state == SM_START)
+            core_done_latch <= 0;
+        else
+            core_done_latch <= core_done_latch | core_done;
+    end
+
+    assign spike_valid_bus = core_spike_valid;
+    assign spike_id_bus    = core_spike_id;
+
+    wire sync_all_done;
+    sync_tree #(.NUM_LEAVES(NUM_CORES)) u_sync (
+        .clk(clk), .rst_n(rst_n),
+        .leaf_done(core_done_latch),
+        .all_done(sync_all_done),
+        .root_start(1'b0), .leaf_start()
+    );
+
+    localparam CAP_WIDTH = NEURON_BITS + 8;
+    reg  [NUM_CORES-1:0] cap_pop;
+    reg  [NUM_CORES-1:0] cap_clear;
+    wire [NUM_CORES-1:0] cap_empty;
+    wire [NUM_CORES*CAP_WIDTH-1:0] cap_data;
+
+    wire [NUM_CORES-1:0] core_probe_valid;
+    wire [NUM_CORES*DATA_WIDTH-1:0] core_probe_data;
+    assign probe_data  = core_probe_data[probe_core*DATA_WIDTH +: DATA_WIDTH];
+    assign probe_valid = core_probe_valid[probe_core];
+
+    function [31:0] popcount;
+        input [NUM_CORES-1:0] bits;
+        integer k;
+    begin
+        popcount = 0;
+        for (k = 0; k < NUM_CORES; k = k + 1)
+            popcount = popcount + bits[k];
+    end
+    endfunction
+
+    wire [NUM_CORES-1:0] rtr_idle;
+    wire [NUM_CORES-1:0] rtr_local_out_valid;
+    wire [NUM_CORES*PACKET_W-1:0] rtr_local_out_data;
+    wire [NUM_CORES-1:0] rtr_local_in_ready;
+
+    reg  [NUM_CORES-1:0] rtr_local_in_valid;
+    reg  [NUM_CORES*PACKET_W-1:0] rtr_local_in_data;
+
+    wire [NUM_CORES-1:0] rtr_local_out_ready =
+        (mesh_state == SM_PKT_DRAIN) ? {NUM_CORES{1'b1}} : {NUM_CORES{1'b0}};
+
+    wire [NUM_CORES-1:0] rtr_n_out_v, rtr_s_out_v, rtr_e_out_v, rtr_w_out_v;
+    wire [NUM_CORES*PACKET_W-1:0] rtr_n_out_d, rtr_s_out_d, rtr_e_out_d, rtr_w_out_d;
+    wire [NUM_CORES-1:0] rtr_n_in_r, rtr_s_in_r, rtr_e_in_r, rtr_w_in_r;
+
+    wire [NUM_CORES-1:0] rtr_b_idle;
+    wire [NUM_CORES-1:0] rtr_b_local_out_valid;
+    wire [NUM_CORES*PACKET_W-1:0] rtr_b_local_out_data;
+    wire [NUM_CORES-1:0] rtr_b_local_in_ready;
+
+    reg  [NUM_CORES-1:0] rtr_b_local_in_valid;
+    reg  [NUM_CORES*PACKET_W-1:0] rtr_b_local_in_data;
+
+    wire [NUM_CORES-1:0] rtr_b_local_out_ready =
+        (mesh_state == SM_PKT_DRAIN) ? ~rtr_local_out_valid : {NUM_CORES{1'b0}};
+
+    wire [NUM_CORES-1:0] rtr_b_n_out_v, rtr_b_s_out_v, rtr_b_e_out_v, rtr_b_w_out_v;
+    wire [NUM_CORES*PACKET_W-1:0] rtr_b_n_out_d, rtr_b_s_out_d, rtr_b_e_out_d, rtr_b_w_out_d;
+    wire [NUM_CORES-1:0] rtr_b_n_in_r, rtr_b_s_in_r, rtr_b_e_in_r, rtr_b_w_in_r;
+
+    genvar gi;
+    generate
+        for (gi = 0; gi < NUM_CORES; gi = gi + 1) begin : gen_core
+
+            wire this_ext_valid =
+                (mesh_state == SM_IDLE && ext_valid && ext_core == gi[CORE_ID_BITS-1:0]) ||
+                (mesh_state == SM_PKT_DRAIN && (rtr_local_out_valid[gi] || rtr_b_local_out_valid[gi]));
+
+            wire [PACKET_W-1:0] drain_pkt = rtr_local_out_valid[gi] ?
+                rtr_local_out_data[gi*PACKET_W +: PACKET_W] :
+                rtr_b_local_out_data[gi*PACKET_W +: PACKET_W];
+            wire [NEURON_BITS-1:0] this_ext_nid =
+                (mesh_state == SM_PKT_DRAIN) ? drain_pkt[DATA_WIDTH +: NEURON_BITS] : ext_neuron_id;
+            wire signed [DATA_WIDTH-1:0] this_ext_cur =
+                (mesh_state == SM_PKT_DRAIN) ? drain_pkt[DATA_WIDTH-1:0] : ext_current;
+
+            wire this_pool_we = prog_pool_we && (prog_pool_core == gi[CORE_ID_BITS-1:0]) &&
+                                (mesh_state == SM_IDLE);
+            wire this_index_we = prog_index_we && (prog_index_core == gi[CORE_ID_BITS-1:0]) &&
+                                 (mesh_state == SM_IDLE);
+            wire this_param_we = prog_param_we && (prog_param_core == gi[CORE_ID_BITS-1:0]) &&
+                                 (mesh_state == SM_IDLE);
+            wire this_delay_we = prog_delay_we && (prog_delay_core == gi[CORE_ID_BITS-1:0]) &&
+                                 (mesh_state == SM_IDLE);
+            wire this_ucode_we = prog_ucode_we && (prog_ucode_core == gi[CORE_ID_BITS-1:0]) &&
+                                 (mesh_state == SM_IDLE);
+
+            scalable_core_v2 #(
+                .NUM_NEURONS(NUM_NEURONS), .NEURON_BITS(NEURON_BITS),
+                .DATA_WIDTH(DATA_WIDTH), .POOL_DEPTH(POOL_DEPTH),
+                .POOL_ADDR_BITS(POOL_ADDR_BITS), .COUNT_BITS(COUNT_BITS),
+                .REV_FANIN(REV_FANIN), .REV_SLOT_BITS(REV_SLOT_BITS),
+                .THRESHOLD(THRESHOLD), .LEAK_RATE(LEAK_RATE),
+                .REFRAC_CYCLES(REFRAC_CYCLES), .GRADE_SHIFT(GRADE_SHIFT)
+            ) core (
+                .clk(clk), .rst_n(rst_n),
+                .start(core_start_r[gi]),
+                .learn_enable(learn_enable), .graded_enable(graded_enable),
+                .dendritic_enable(dendritic_enable),
+                .threefactor_enable(threefactor_enable),
+                .noise_enable(noise_enable), .skip_idle_enable(skip_idle_enable),
+                .scale_u_enable(scale_u_enable),
+                .reward_value(reward_value),
+                .ext_valid(this_ext_valid),
+                .ext_neuron_id(this_ext_nid),
+                .ext_current(this_ext_cur),
+                .pool_we(this_pool_we), .pool_addr_in(prog_pool_addr),
+                .pool_src_in(prog_pool_src), .pool_target_in(prog_pool_target),
+                .pool_weight_in(prog_pool_weight), .pool_comp_in(prog_pool_comp),
+                .index_we(this_index_we), .index_neuron_in(prog_index_neuron),
+                .index_base_in(prog_index_base), .index_count_in(prog_index_count),
+                .index_format_in(prog_index_format),
+                .delay_we(this_delay_we), .delay_addr_in(prog_delay_addr),
+                .delay_value_in(prog_delay_value),
+                .ucode_prog_we(this_ucode_we), .ucode_prog_addr(prog_ucode_addr),
+                .ucode_prog_data(prog_ucode_data),
+                .prog_param_we(this_param_we), .prog_param_neuron(prog_param_neuron),
+                .prog_param_id(prog_param_id), .prog_param_value(prog_param_value),
+                .probe_read(probe_read && (probe_core == gi[CORE_ID_BITS-1:0])),
+                .probe_neuron(probe_neuron), .probe_state_id(probe_state_id),
+                .probe_pool_addr(probe_pool_addr),
+                .probe_data(core_probe_data[gi*DATA_WIDTH +: DATA_WIDTH]),
+                .probe_valid(core_probe_valid[gi]),
+                .timestep_done(core_done[gi]),
+                .spike_out_valid(core_spike_valid[gi]),
+                .spike_out_id(core_spike_id[gi*NEURON_BITS +: NEURON_BITS]),
+                .spike_out_payload(core_spike_payload[gi*8 +: 8]),
+                .state_out(), .total_spikes(), .timestep_count(),
+                .core_idle(core_idle_bus[gi])
+            );
+
+            spike_fifo #(.ID_WIDTH(CAP_WIDTH), .DEPTH(64), .PTR_BITS(6)) capture_fifo (
+                .clk(clk), .rst_n(rst_n), .clear(cap_clear[gi]),
+                .push(core_spike_valid[gi] && (mesh_state == SM_RUN_WAIT)),
+                .push_data({core_spike_id[gi*NEURON_BITS +: NEURON_BITS],
+                            core_spike_payload[gi*8 +: 8]}),
+                .pop(cap_pop[gi]),
+                .pop_data(cap_data[gi*CAP_WIDTH +: CAP_WIDTH]),
+                .empty(cap_empty[gi]), .full(), .count()
+            );
+
+            localparam RX = gi % MESH_X;
+            localparam RY = gi / MESH_X;
+            localparam HAS_N = (RY < MESH_Y - 1) ? 1 : 0;
+            localparam HAS_S = (RY > 0) ? 1 : 0;
+            localparam HAS_E = (RX < MESH_X - 1) ? 1 : 0;
+            localparam HAS_W = (RX > 0) ? 1 : 0;
+            localparam N_ID = HAS_N ? ((RY+1)*MESH_X + RX) : 0;
+            localparam S_ID = HAS_S ? ((RY-1)*MESH_X + RX) : 0;
+            localparam E_ID = HAS_E ? (RY*MESH_X + (RX+1)) : 0;
+            localparam W_ID = HAS_W ? (RY*MESH_X + (RX-1)) : 0;
+
+            wire n_in_v = HAS_N ? rtr_s_out_v[N_ID] : 1'b0;
+            wire [PACKET_W-1:0] n_in_d = HAS_N ? rtr_s_out_d[N_ID*PACKET_W +: PACKET_W] : {PACKET_W{1'b0}};
+            wire n_out_r = HAS_N ? rtr_s_in_r[N_ID] : 1'b1;
+
+            wire s_in_v = HAS_S ? rtr_n_out_v[S_ID] : 1'b0;
+            wire [PACKET_W-1:0] s_in_d = HAS_S ? rtr_n_out_d[S_ID*PACKET_W +: PACKET_W] : {PACKET_W{1'b0}};
+            wire s_out_r = HAS_S ? rtr_n_in_r[S_ID] : 1'b1;
+
+            wire e_in_v = HAS_E ? rtr_w_out_v[E_ID] : 1'b0;
+            wire [PACKET_W-1:0] e_in_d = HAS_E ? rtr_w_out_d[E_ID*PACKET_W +: PACKET_W] : {PACKET_W{1'b0}};
+            wire e_out_r = HAS_E ? rtr_w_in_r[E_ID] : 1'b1;
+
+            wire w_in_v = HAS_W ? rtr_e_out_v[W_ID] : 1'b0;
+            wire [PACKET_W-1:0] w_in_d = HAS_W ? rtr_e_out_d[W_ID*PACKET_W +: PACKET_W] : {PACKET_W{1'b0}};
+            wire w_out_r = HAS_W ? rtr_e_in_r[W_ID] : 1'b1;
+
+            async_router #(
+                .PACKET_W(PACKET_W), .COORD_BITS(COORD_BITS),
+                .FIFO_DEPTH(16), .FIFO_PTR_BITS(4)
+            ) router (
+                .clk(clk), .rst_n(rst_n),
+                .my_x(core_to_x(gi[CORE_ID_BITS-1:0])),
+                .my_y(core_to_y(gi[CORE_ID_BITS-1:0])),
+                .local_in_valid (rtr_local_in_valid[gi]),
+                .local_in_ready (rtr_local_in_ready[gi]),
+                .local_in_data  (rtr_local_in_data[gi*PACKET_W +: PACKET_W]),
+                .local_out_valid(rtr_local_out_valid[gi]),
+                .local_out_ready(rtr_local_out_ready[gi]),
+                .local_out_data (rtr_local_out_data[gi*PACKET_W +: PACKET_W]),
+                .north_in_valid (n_in_v),
+                .north_in_ready (rtr_n_in_r[gi]),
+                .north_in_data  (n_in_d),
+                .north_out_valid(rtr_n_out_v[gi]),
+                .north_out_ready(n_out_r),
+                .north_out_data (rtr_n_out_d[gi*PACKET_W +: PACKET_W]),
+                .south_in_valid (s_in_v),
+                .south_in_ready (rtr_s_in_r[gi]),
+                .south_in_data  (s_in_d),
+                .south_out_valid(rtr_s_out_v[gi]),
+                .south_out_ready(s_out_r),
+                .south_out_data (rtr_s_out_d[gi*PACKET_W +: PACKET_W]),
+                .east_in_valid  (e_in_v),
+                .east_in_ready  (rtr_e_in_r[gi]),
+                .east_in_data   (e_in_d),
+                .east_out_valid (rtr_e_out_v[gi]),
+                .east_out_ready (e_out_r),
+                .east_out_data  (rtr_e_out_d[gi*PACKET_W +: PACKET_W]),
+                .west_in_valid  (w_in_v),
+                .west_in_ready  (rtr_w_in_r[gi]),
+                .west_in_data   (w_in_d),
+                .west_out_valid (rtr_w_out_v[gi]),
+                .west_out_ready (w_out_r),
+                .west_out_data  (rtr_w_out_d[gi*PACKET_W +: PACKET_W]),
+                .idle           (rtr_idle[gi])
+            );
+        end
+    endgenerate
+
+    generate if (DUAL_NOC) begin : gen_net_b
+        genvar bi;
+        for (bi = 0; bi < NUM_CORES; bi = bi + 1) begin : gen_rtr_b
+            localparam BRX = bi % MESH_X;
+            localparam BRY = bi / MESH_X;
+            localparam B_HAS_N = (BRY < MESH_Y - 1) ? 1 : 0;
+            localparam B_HAS_S = (BRY > 0) ? 1 : 0;
+            localparam B_HAS_E = (BRX < MESH_X - 1) ? 1 : 0;
+            localparam B_HAS_W = (BRX > 0) ? 1 : 0;
+            localparam BN_ID = B_HAS_N ? ((BRY+1)*MESH_X + BRX) : 0;
+            localparam BS_ID = B_HAS_S ? ((BRY-1)*MESH_X + BRX) : 0;
+            localparam BE_ID = B_HAS_E ? (BRY*MESH_X + (BRX+1)) : 0;
+            localparam BW_ID = B_HAS_W ? (BRY*MESH_X + (BRX-1)) : 0;
+
+            wire bn_in_v = B_HAS_N ? rtr_b_s_out_v[BN_ID] : 1'b0;
+            wire [PACKET_W-1:0] bn_in_d = B_HAS_N ?
+                rtr_b_s_out_d[BN_ID*PACKET_W +: PACKET_W] : {PACKET_W{1'b0}};
+            wire bn_out_r = B_HAS_N ? rtr_b_s_in_r[BN_ID] : 1'b1;
+
+            wire bs_in_v = B_HAS_S ? rtr_b_n_out_v[BS_ID] : 1'b0;
+            wire [PACKET_W-1:0] bs_in_d = B_HAS_S ?
+                rtr_b_n_out_d[BS_ID*PACKET_W +: PACKET_W] : {PACKET_W{1'b0}};
+            wire bs_out_r = B_HAS_S ? rtr_b_n_in_r[BS_ID] : 1'b1;
+
+            wire be_in_v = B_HAS_E ? rtr_b_w_out_v[BE_ID] : 1'b0;
+            wire [PACKET_W-1:0] be_in_d = B_HAS_E ?
+                rtr_b_w_out_d[BE_ID*PACKET_W +: PACKET_W] : {PACKET_W{1'b0}};
+            wire be_out_r = B_HAS_E ? rtr_b_w_in_r[BE_ID] : 1'b1;
+
+            wire bw_in_v = B_HAS_W ? rtr_b_e_out_v[BW_ID] : 1'b0;
+            wire [PACKET_W-1:0] bw_in_d = B_HAS_W ?
+                rtr_b_e_out_d[BW_ID*PACKET_W +: PACKET_W] : {PACKET_W{1'b0}};
+            wire bw_out_r = B_HAS_W ? rtr_b_e_in_r[BW_ID] : 1'b1;
+
+            async_router #(
+                .PACKET_W(PACKET_W), .COORD_BITS(COORD_BITS),
+                .FIFO_DEPTH(16), .FIFO_PTR_BITS(4)
+            ) router_b (
+                .clk(clk), .rst_n(rst_n),
+                .my_x(core_to_x(bi[CORE_ID_BITS-1:0])),
+                .my_y(core_to_y(bi[CORE_ID_BITS-1:0])),
+                .local_in_valid (rtr_b_local_in_valid[bi]),
+                .local_in_ready (rtr_b_local_in_ready[bi]),
+                .local_in_data  (rtr_b_local_in_data[bi*PACKET_W +: PACKET_W]),
+                .local_out_valid(rtr_b_local_out_valid[bi]),
+                .local_out_ready(rtr_b_local_out_ready[bi]),
+                .local_out_data (rtr_b_local_out_data[bi*PACKET_W +: PACKET_W]),
+                .north_in_valid (bn_in_v),
+                .north_in_ready (rtr_b_n_in_r[bi]),
+                .north_in_data  (bn_in_d),
+                .north_out_valid(rtr_b_n_out_v[bi]),
+                .north_out_ready(bn_out_r),
+                .north_out_data (rtr_b_n_out_d[bi*PACKET_W +: PACKET_W]),
+                .south_in_valid (bs_in_v),
+                .south_in_ready (rtr_b_s_in_r[bi]),
+                .south_in_data  (bs_in_d),
+                .south_out_valid(rtr_b_s_out_v[bi]),
+                .south_out_ready(bs_out_r),
+                .south_out_data (rtr_b_s_out_d[bi*PACKET_W +: PACKET_W]),
+                .east_in_valid  (be_in_v),
+                .east_in_ready  (rtr_b_e_in_r[bi]),
+                .east_in_data   (be_in_d),
+                .east_out_valid (rtr_b_e_out_v[bi]),
+                .east_out_ready (be_out_r),
+                .east_out_data  (rtr_b_e_out_d[bi*PACKET_W +: PACKET_W]),
+                .west_in_valid  (bw_in_v),
+                .west_in_ready  (rtr_b_w_in_r[bi]),
+                .west_in_data   (bw_in_d),
+                .west_out_valid (rtr_b_w_out_v[bi]),
+                .west_out_ready (bw_out_r),
+                .west_out_data  (rtr_b_w_out_d[bi*PACKET_W +: PACKET_W]),
+                .idle           (rtr_b_idle[bi])
+            );
+        end
+    end else begin : gen_no_net_b
+        assign rtr_b_idle = {NUM_CORES{1'b1}};
+        assign rtr_b_local_out_valid = {NUM_CORES{1'b0}};
+        assign rtr_b_local_out_data = {NUM_CORES*PACKET_W{1'b0}};
+        assign rtr_b_local_in_ready = {NUM_CORES{1'b1}};
+    end endgenerate
+
+    reg [CORE_ID_BITS-1:0]     route_core_idx;
+    reg [NEURON_BITS-1:0]      route_neuron;
+    reg [7:0]                  route_payload;
+    reg [ROUTE_SLOT_BITS-1:0]  route_slot;
+    reg [GLOBAL_ROUTE_SLOT_BITS-1:0] global_slot;
+    reg [3:0]                  drain_wait;
+
+    wire signed [31:0] route_weight_ext = rt_weight;
+    wire signed [31:0] route_payload_ext = {24'd0, route_payload};
+    wire signed [31:0] route_graded_product = route_weight_ext * route_payload_ext;
+    wire signed [DATA_WIDTH-1:0] route_graded_current = route_graded_product >>> GRADE_SHIFT;
+
+    wire signed [31:0] grt_weight_ext = grt_weight;
+    wire signed [31:0] grt_graded_product = grt_weight_ext * route_payload_ext;
+    wire signed [DATA_WIDTH-1:0] grt_graded_current = grt_graded_product >>> GRADE_SHIFT;
+
+    wire signed [DATA_WIDTH-1:0] rt_eff_weight = graded_enable ? route_graded_current : rt_weight;
+    wire signed [DATA_WIDTH-1:0] grt_eff_weight = graded_enable ? grt_graded_current : grt_weight;
+
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n) begin
+            mesh_state     <= SM_IDLE;
+            timestep_done  <= 0;
+            total_spikes   <= 0;
+            timestep_count <= 0;
+            core_start_r   <= 0;
+            route_core_idx <= 0;
+            route_neuron   <= 0;
+            route_payload  <= 0;
+            route_slot     <= 0;
+            global_slot    <= 0;
+            drain_wait     <= 0;
+            rt_we          <= 0;
+            rt_addr        <= 0;
+            grt_we         <= 0;
+            grt_addr       <= 0;
+            cap_pop        <= 0;
+            cap_clear      <= 0;
+            rtr_local_in_valid <= 0;
+            rtr_local_in_data  <= 0;
+            rtr_b_local_in_valid <= 0;
+            rtr_b_local_in_data  <= 0;
+        end else begin
+            timestep_done      <= 0;
+            core_start_r       <= 0;
+            rt_we              <= 0;
+            grt_we             <= 0;
+            cap_pop            <= 0;
+            cap_clear          <= 0;
+            rtr_local_in_valid <= 0;
+            rtr_b_local_in_valid <= 0;
+
+            total_spikes <= total_spikes + popcount(core_spike_valid);
+
+            case (mesh_state)
+                SM_IDLE: begin
+                    if (start) begin
+                        drain_wait <= 0;
+                        mesh_state <= SM_PKT_DRAIN;
+                    end
+                end
+
+                SM_PKT_DRAIN: begin
+                    if ((&rtr_idle) && (&rtr_b_idle) && !(|rtr_local_out_valid) && !(|rtr_b_local_out_valid)) begin
+                        drain_wait <= drain_wait + 1;
+                        if (drain_wait >= 4'd3)
+                            mesh_state <= SM_START;
+                    end else begin
+                        drain_wait <= 0;
+                    end
+                end
+
+                SM_START: begin
+                    core_start_r <= {NUM_CORES{1'b1}};
+                    mesh_state   <= SM_RUN_WAIT;
+                end
+
+                SM_RUN_WAIT: begin
+                    if (sync_all_done) begin
+                        route_core_idx <= 0;
+                        mesh_state     <= SM_ROUTE_POP;
+                    end
+                end
+
+                SM_ROUTE_POP: begin
+                    if (cap_empty[route_core_idx]) begin
+                        if (route_core_idx == NUM_CORES - 1)
+                            mesh_state <= SM_DONE;
+                        else
+                            route_core_idx <= route_core_idx + 1;
+                    end else begin
+                        cap_pop[route_core_idx] <= 1;
+                        route_neuron  <= cap_data[route_core_idx * CAP_WIDTH + 8 +: NEURON_BITS];
+                        route_payload <= cap_data[route_core_idx * CAP_WIDTH +: 8];
+                        route_slot    <= 0;
+                        mesh_state    <= SM_ROUTE_ADDR;
+                    end
+                end
+
+                SM_ROUTE_ADDR: begin
+                    rt_addr    <= {route_core_idx, route_neuron, route_slot};
+                    mesh_state <= SM_ROUTE_WAIT;
+                end
+
+                SM_ROUTE_WAIT: begin
+                    mesh_state <= SM_ROUTE_READ;
+                end
+
+                SM_ROUTE_READ: begin
+                    if (rt_valid) begin
+                        if (route_core_idx[0] == 1'b0 || !DUAL_NOC) begin
+                            if (rtr_local_in_ready[route_core_idx]) begin
+                                rtr_local_in_valid[route_core_idx] <= 1;
+                                rtr_local_in_data[route_core_idx*PACKET_W +: PACKET_W] <=
+                                    {core_to_x(rt_dest_core), core_to_y(rt_dest_core),
+                                     rt_dest_nrn, rt_eff_weight};
+                            end
+                        end else begin
+                            if (rtr_b_local_in_ready[route_core_idx]) begin
+                                rtr_b_local_in_valid[route_core_idx] <= 1;
+                                rtr_b_local_in_data[route_core_idx*PACKET_W +: PACKET_W] <=
+                                    {core_to_x(rt_dest_core), core_to_y(rt_dest_core),
+                                     rt_dest_nrn, rt_eff_weight};
+                            end
+                        end
+                    end
+                    if (route_slot < ROUTE_FANOUT - 1) begin
+                        route_slot <= route_slot + 1;
+                        mesh_state <= SM_ROUTE_ADDR;
+                    end else begin
+                        global_slot <= 0;
+                        mesh_state  <= SM_GRT_ADDR;
+                    end
+                end
+
+                SM_GRT_ADDR: begin
+                    grt_addr   <= {route_core_idx, route_neuron, global_slot};
+                    mesh_state <= SM_GRT_WAIT;
+                end
+
+                SM_GRT_WAIT: begin
+                    mesh_state <= SM_GRT_READ;
+                end
+
+                SM_GRT_READ: begin
+                    if (grt_valid) begin
+                        if (route_core_idx[0] == 1'b0 || !DUAL_NOC) begin
+                            if (rtr_local_in_ready[route_core_idx]) begin
+                                rtr_local_in_valid[route_core_idx] <= 1;
+                                rtr_local_in_data[route_core_idx*PACKET_W +: PACKET_W] <=
+                                    {core_to_x(grt_dest_core), core_to_y(grt_dest_core),
+                                     grt_dest_nrn, grt_eff_weight};
+                            end
+                        end else begin
+                            if (rtr_b_local_in_ready[route_core_idx]) begin
+                                rtr_b_local_in_valid[route_core_idx] <= 1;
+                                rtr_b_local_in_data[route_core_idx*PACKET_W +: PACKET_W] <=
+                                    {core_to_x(grt_dest_core), core_to_y(grt_dest_core),
+                                     grt_dest_nrn, grt_eff_weight};
+                            end
+                        end
+                    end
+                    if (global_slot < GLOBAL_ROUTE_SLOTS - 1) begin
+                        global_slot <= global_slot + 1;
+                        mesh_state  <= SM_GRT_ADDR;
+                    end else begin
+                        mesh_state <= SM_ROUTE_POP;
+                    end
+                end
+
+                SM_DONE: begin
+                    cap_clear      <= {NUM_CORES{1'b1}};
+                    timestep_done  <= 1;
+                    timestep_count <= timestep_count + 1;
+                    mesh_state     <= SM_IDLE;
+                end
+
+                default: mesh_state <= SM_IDLE;
+            endcase
+        end
+    end
+
+endmodule

rtl/async_router.v

@@ -0,0 +1,217 @@
+// ============================================================================
+// Async Router
+// ============================================================================
+//
+// Copyright 2026 Henry Arthur Shulayev Barnes / Catalyst Neuromorphic Ltd
+// Company No. 17054540 — UK Patent Application No. 2602902.6
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// ============================================================================
+
+`timescale 1ns/1ps
+
+module async_router #(
+    parameter PACKET_W      = 34,
+    parameter COORD_BITS    = 4,
+    parameter FIFO_DEPTH    = 16,
+    parameter FIFO_PTR_BITS = 4
+)(
+    input  wire                    clk,
+    input  wire                    rst_n,
+    input  wire [COORD_BITS-1:0]   my_x,
+    input  wire [COORD_BITS-1:0]   my_y,
+
+    input  wire                    local_in_valid,
+    output wire                    local_in_ready,
+    input  wire [PACKET_W-1:0]     local_in_data,
+    output wire                    local_out_valid,
+    input  wire                    local_out_ready,
+    output wire [PACKET_W-1:0]     local_out_data,
+
+    input  wire                    north_in_valid,
+    output wire                    north_in_ready,
+    input  wire [PACKET_W-1:0]     north_in_data,
+    output wire                    north_out_valid,
+    input  wire                    north_out_ready,
+    output wire [PACKET_W-1:0]     north_out_data,
+
+    input  wire                    south_in_valid,
+    output wire                    south_in_ready,
+    input  wire [PACKET_W-1:0]     south_in_data,
+    output wire                    south_out_valid,
+    input  wire                    south_out_ready,
+    output wire [PACKET_W-1:0]     south_out_data,
+
+    input  wire                    east_in_valid,
+    output wire                    east_in_ready,
+    input  wire [PACKET_W-1:0]     east_in_data,
+    output wire                    east_out_valid,
+    input  wire                    east_out_ready,
+    output wire [PACKET_W-1:0]     east_out_data,
+
+    input  wire                    west_in_valid,
+    output wire                    west_in_ready,
+    input  wire [PACKET_W-1:0]     west_in_data,
+    output wire                    west_out_valid,
+    input  wire                    west_out_ready,
+    output wire [PACKET_W-1:0]     west_out_data,
+
+    output wire                    idle
+);
+
+    localparam P_LOCAL = 0, P_NORTH = 1, P_SOUTH = 2, P_EAST = 3, P_WEST = 4;
+
+    localparam DX_MSB = PACKET_W - 1;
+    localparam DX_LSB = PACKET_W - COORD_BITS;
+    localparam DY_MSB = DX_LSB - 1;
+    localparam DY_LSB = DX_LSB - COORD_BITS;
+
+    wire [4:0] fifo_empty, fifo_full;
+    wire [PACKET_W-1:0] fifo_head [0:4];
+    wire [4:0] fifo_push;
+    reg  [4:0] fifo_pop;
+
+    assign fifo_push[P_LOCAL] = local_in_valid && !fifo_full[P_LOCAL];
+    assign fifo_push[P_NORTH] = north_in_valid && !fifo_full[P_NORTH];
+    assign fifo_push[P_SOUTH] = south_in_valid && !fifo_full[P_SOUTH];
+    assign fifo_push[P_EAST]  = east_in_valid  && !fifo_full[P_EAST];
+    assign fifo_push[P_WEST]  = west_in_valid  && !fifo_full[P_WEST];
+
+    assign local_in_ready = !fifo_full[P_LOCAL];
+    assign north_in_ready = !fifo_full[P_NORTH];
+    assign south_in_ready = !fifo_full[P_SOUTH];
+    assign east_in_ready  = !fifo_full[P_EAST];
+    assign west_in_ready  = !fifo_full[P_WEST];
+
+    wire [PACKET_W-1:0] in_data [0:4];
+    assign in_data[P_LOCAL] = local_in_data;
+    assign in_data[P_NORTH] = north_in_data;
+    assign in_data[P_SOUTH] = south_in_data;
+    assign in_data[P_EAST]  = east_in_data;
+    assign in_data[P_WEST]  = west_in_data;
+
+    genvar gi;
+    generate
+        for (gi = 0; gi < 5; gi = gi + 1) begin : gen_fifo
+            spike_fifo #(
+                .ID_WIDTH  (PACKET_W),
+                .DEPTH     (FIFO_DEPTH),
+                .PTR_BITS  (FIFO_PTR_BITS)
+            ) input_fifo (
+                .clk       (clk),
+                .rst_n     (rst_n),
+                .push      (fifo_push[gi]),
+                .pop       (fifo_pop[gi]),
+                .clear     (1'b0),
+                .push_data (in_data[gi]),
+                .pop_data  (fifo_head[gi]),
+                .empty     (fifo_empty[gi]),
+                .full      (fifo_full[gi])
+            );
+        end
+    endgenerate
+
+    function [2:0] xy_route;
+        input [COORD_BITS-1:0] dx, dy, cx, cy;
+        begin
+            if      (dx > cx) xy_route = P_EAST;
+            else if (dx < cx) xy_route = P_WEST;
+            else if (dy > cy) xy_route = P_NORTH;
+            else if (dy < cy) xy_route = P_SOUTH;
+            else              xy_route = P_LOCAL;
+        end
+    endfunction
+
+    wire [2:0] head_route [0:4];
+    generate
+        for (gi = 0; gi < 5; gi = gi + 1) begin : gen_route
+            assign head_route[gi] = xy_route(
+                fifo_head[gi][DX_MSB:DX_LSB],
+                fifo_head[gi][DY_MSB:DY_LSB],
+                my_x, my_y
+            );
+        end
+    endgenerate
+
+    reg  [4:0] out_valid_r;
+    reg  [PACKET_W-1:0] out_data_r [0:4];
+
+    wire [4:0] out_ready;
+    assign out_ready[P_LOCAL] = local_out_ready;
+    assign out_ready[P_NORTH] = north_out_ready;
+    assign out_ready[P_SOUTH] = south_out_ready;
+    assign out_ready[P_EAST]  = east_out_ready;
+    assign out_ready[P_WEST]  = west_out_ready;
+
+    assign local_out_valid = out_valid_r[P_LOCAL];
+    assign local_out_data  = out_data_r[P_LOCAL];
+    assign north_out_valid = out_valid_r[P_NORTH];
+    assign north_out_data  = out_data_r[P_NORTH];
+    assign south_out_valid = out_valid_r[P_SOUTH];
+    assign south_out_data  = out_data_r[P_SOUTH];
+    assign east_out_valid  = out_valid_r[P_EAST];
+    assign east_out_data   = out_data_r[P_EAST];
+    assign west_out_valid  = out_valid_r[P_WEST];
+    assign west_out_data   = out_data_r[P_WEST];
+
+    reg [2:0] arb_ptr;
+
+    reg [4:0] comb_grant;
+    reg [4:0] comb_out_claim;
+
+    always @(*) begin : grant_logic
+        integer p, idx;
+        comb_grant = 5'b0;
+        comb_out_claim = 5'b0;
+        for (p = 0; p < 5; p = p + 1) begin
+            idx = arb_ptr + p;
+            if (idx >= 5) idx = idx - 5;
+            if (!fifo_empty[idx] && !comb_grant[idx]) begin
+                if (!out_valid_r[head_route[idx]] && !comb_out_claim[head_route[idx]]) begin
+                    comb_grant[idx] = 1'b1;
+                    comb_out_claim[head_route[idx]] = 1'b1;
+                end
+            end
+        end
+    end
+
+    always @(posedge clk or negedge rst_n) begin : seq_logic
+        integer i;
+        if (!rst_n) begin
+            out_valid_r <= 5'b0;
+            arb_ptr <= 3'd0;
+            for (i = 0; i < 5; i = i + 1)
+                out_data_r[i] <= {PACKET_W{1'b0}};
+        end else begin
+            for (i = 0; i < 5; i = i + 1)
+                if (out_valid_r[i] && out_ready[i])
+                    out_valid_r[i] <= 1'b0;
+
+            for (i = 0; i < 5; i = i + 1) begin
+                if (comb_grant[i]) begin
+                    out_valid_r[head_route[i]] <= 1'b1;
+                    out_data_r[head_route[i]] <= fifo_head[i];
+                end
+            end
+
+            arb_ptr <= (arb_ptr == 3'd4) ? 3'd0 : arb_ptr + 3'd1;
+        end
+    end
+
+    always @(*) fifo_pop = comb_grant;
+
+    assign idle = (&fifo_empty) &&
+                  !out_valid_r[P_NORTH] && !out_valid_r[P_SOUTH] &&
+                  !out_valid_r[P_EAST]  && !out_valid_r[P_WEST];
+
+endmodule

rtl/axi_uart_bridge.v

@@ -0,0 +1,258 @@
+// ============================================================================
+// AXI-UART Bridge
+// ============================================================================
+//
+// Copyright 2026 Henry Arthur Shulayev Barnes / Catalyst Neuromorphic Ltd
+// Company No. 17054540 — UK Patent Application No. 2602902.6
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// ============================================================================
+
+module axi_uart_bridge #(
+    parameter VERSION_ID = 32'hF2_02_03_10,
+    parameter NUM_CORES  = 16
+)(
+    input  wire        clk,
+    input  wire        rst_n,
+    input  wire        clk_neuro,
+    input  wire        rst_neuro_n,
+
+    input  wire [31:0] s_axi_awaddr,
+    input  wire        s_axi_awvalid,
+    output reg         s_axi_awready,
+    input  wire [31:0] s_axi_wdata,
+    input  wire [3:0]  s_axi_wstrb,
+    input  wire        s_axi_wvalid,
+    output reg         s_axi_wready,
+    output reg  [1:0]  s_axi_bresp,
+    output reg         s_axi_bvalid,
+    input  wire        s_axi_bready,
+    input  wire [31:0] s_axi_araddr,
+    input  wire        s_axi_arvalid,
+    output reg         s_axi_arready,
+    output reg  [31:0] s_axi_rdata,
+    output reg  [1:0]  s_axi_rresp,
+    output reg         s_axi_rvalid,
+    input  wire        s_axi_rready,
+
+    output reg  [7:0]  hi_rx_data,
+    output reg         hi_rx_valid,
+    input  wire [7:0]  hi_tx_data,
+    input  wire        hi_tx_valid,
+    output wire        hi_tx_ready
+);
+
+    localparam REG_TX_DATA    = 3'd0;
+    localparam REG_TX_STATUS  = 3'd1;
+    localparam REG_RX_DATA    = 3'd2;
+    localparam REG_RX_STATUS  = 3'd3;
+    localparam REG_CONTROL    = 3'd4;
+    localparam REG_VERSION    = 3'd5;
+    localparam REG_SCRATCH    = 3'd6;
+    localparam REG_CORE_COUNT = 3'd7;
+
+    wire       tx_wr_full;
+    wire       tx_rd_empty;
+    wire [7:0] tx_rd_data;
+    reg        tx_rd_en;
+    reg        tx_wr_en;
+    reg  [7:0] tx_wr_data;
+
+    async_fifo #(.DATA_WIDTH(8), .ADDR_BITS(5)) u_tx_fifo (
+        .wr_clk   (clk),
+        .wr_rst_n (rst_n),
+        .wr_data  (tx_wr_data),
+        .wr_en    (tx_wr_en),
+        .wr_full  (tx_wr_full),
+        .rd_clk   (clk_neuro),
+        .rd_rst_n (rst_neuro_n),
+        .rd_en    (tx_rd_en),
+        .rd_data  (tx_rd_data),
+        .rd_empty (tx_rd_empty)
+    );
+
+    wire       rx_wr_full;
+    wire       rx_rd_empty;
+    wire [7:0] rx_rd_data;
+    reg        rx_rd_en;
+    reg        rx_wr_en;
+    reg  [7:0] rx_wr_data;
+
+    async_fifo #(.DATA_WIDTH(8), .ADDR_BITS(5)) u_rx_fifo (
+        .wr_clk   (clk_neuro),
+        .wr_rst_n (rst_neuro_n),
+        .wr_data  (rx_wr_data),
+        .wr_en    (rx_wr_en),
+        .wr_full  (rx_wr_full),
+        .rd_clk   (clk),
+        .rd_rst_n (rst_n),
+        .rd_en    (rx_rd_en),
+        .rd_data  (rx_rd_data),
+        .rd_empty (rx_rd_empty)
+    );
+
+    always @(posedge clk_neuro or negedge rst_neuro_n) begin
+        if (!rst_neuro_n) begin
+            hi_rx_data  <= 8'd0;
+            hi_rx_valid <= 1'b0;
+            tx_rd_en    <= 1'b0;
+        end else begin
+            hi_rx_valid <= 1'b0;
+            tx_rd_en    <= 1'b0;
+            if (!tx_rd_empty && !hi_rx_valid) begin
+                hi_rx_data  <= tx_rd_data;
+                hi_rx_valid <= 1'b1;
+                tx_rd_en    <= 1'b1;
+            end
+        end
+    end
+
+    reg [1:0] rx_holdoff;
+    reg       tx_ready_prev;
+
+    wire internal_tx_ready = ~rx_wr_full & (rx_holdoff == 0);
+    wire tx_ready_rising   = internal_tx_ready & ~tx_ready_prev;
+    wire do_rx_capture     = hi_tx_valid & internal_tx_ready & ~tx_ready_rising;
+
+    assign hi_tx_ready = internal_tx_ready;
+
+    always @(posedge clk_neuro or negedge rst_neuro_n) begin
+        if (!rst_neuro_n) begin
+            rx_holdoff    <= 2'd0;
+            tx_ready_prev <= 1'b1;
+            rx_wr_en      <= 1'b0;
+            rx_wr_data    <= 8'd0;
+        end else begin
+            tx_ready_prev <= internal_tx_ready;
+            rx_wr_en      <= 1'b0;
+
+            if (rx_holdoff != 0)
+                rx_holdoff <= rx_holdoff - 1;
+
+            if (do_rx_capture) begin
+                rx_wr_data <= hi_tx_data;
+                rx_wr_en   <= 1'b1;
+                rx_holdoff <= 2'd2;
+            end
+        end
+    end
+
+    reg [31:0] scratch_reg;
+
+    localparam S_IDLE       = 2'd0;
+    localparam S_WRITE_RESP = 2'd1;
+    localparam S_READ_RESP  = 2'd2;
+
+    reg [1:0]  axi_state;
+    reg [2:0]  wr_reg_addr;
+    reg [31:0] wr_data_reg;
+    reg [2:0]  rd_reg_addr;
+
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n) begin
+            axi_state     <= S_IDLE;
+            s_axi_awready <= 1'b0;
+            s_axi_wready  <= 1'b0;
+            s_axi_bvalid  <= 1'b0;
+            s_axi_bresp   <= 2'b00;
+            s_axi_arready <= 1'b0;
+            s_axi_rvalid  <= 1'b0;
+            s_axi_rdata   <= 32'd0;
+            s_axi_rresp   <= 2'b00;
+            scratch_reg   <= 32'd0;
+            wr_reg_addr   <= 3'd0;
+            wr_data_reg   <= 32'd0;
+            rd_reg_addr   <= 3'd0;
+            tx_wr_en      <= 1'b0;
+            tx_wr_data    <= 8'd0;
+            rx_rd_en      <= 1'b0;
+        end else begin
+            tx_wr_en <= 1'b0;
+            rx_rd_en <= 1'b0;
+
+            case (axi_state)
+                S_IDLE: begin
+                    s_axi_bvalid <= 1'b0;
+                    s_axi_rvalid <= 1'b0;
+
+                    if (s_axi_awvalid && s_axi_wvalid) begin
+                        s_axi_awready <= 1'b1;
+                        s_axi_wready  <= 1'b1;
+                        wr_reg_addr   <= s_axi_awaddr[4:2];
+                        wr_data_reg   <= s_axi_wdata;
+                        axi_state     <= S_WRITE_RESP;
+                    end else if (s_axi_arvalid) begin
+                        s_axi_arready <= 1'b1;
+                        rd_reg_addr   <= s_axi_araddr[4:2];
+                        axi_state     <= S_READ_RESP;
+                    end
+                end
+
+                S_WRITE_RESP: begin
+                    s_axi_awready <= 1'b0;
+                    s_axi_wready  <= 1'b0;
+
+                    if (!s_axi_bvalid) begin
+                        case (wr_reg_addr)
+                            REG_TX_DATA: begin
+                                if (!tx_wr_full) begin
+                                    tx_wr_data <= wr_data_reg[7:0];
+                                    tx_wr_en   <= 1'b1;
+                                end
+                            end
+                            REG_SCRATCH: scratch_reg <= wr_data_reg;
+                            default: ;
+                        endcase
+                        s_axi_bvalid <= 1'b1;
+                        s_axi_bresp  <= 2'b00;
+                    end
+
+                    if (s_axi_bvalid && s_axi_bready)
+                        axi_state <= S_IDLE;
+                end
+
+                S_READ_RESP: begin
+                    s_axi_arready <= 1'b0;
+
+                    if (!s_axi_rvalid) begin
+                        case (rd_reg_addr)
+                            REG_TX_DATA:    s_axi_rdata <= 32'd0;
+                            REG_TX_STATUS:  s_axi_rdata <= {31'd0, ~tx_wr_full};
+                            REG_RX_DATA: begin
+                                if (!rx_rd_empty) begin
+                                    s_axi_rdata <= {24'd0, rx_rd_data};
+                                    rx_rd_en    <= 1'b1;
+                                end else begin
+                                    s_axi_rdata <= 32'd0;
+                                end
+                            end
+                            REG_RX_STATUS:  s_axi_rdata <= {31'd0, ~rx_rd_empty};
+                            REG_CONTROL:    s_axi_rdata <= 32'd0;
+                            REG_VERSION:    s_axi_rdata <= VERSION_ID;
+                            REG_SCRATCH:    s_axi_rdata <= scratch_reg;
+                            REG_CORE_COUNT: s_axi_rdata <= NUM_CORES;
+                        endcase
+                        s_axi_rvalid <= 1'b1;
+                        s_axi_rresp  <= 2'b00;
+                    end
+
+                    if (s_axi_rvalid && s_axi_rready)
+                        axi_state <= S_IDLE;
+                end
+
+                default: axi_state <= S_IDLE;
+            endcase
+        end
+    end
+
+endmodule

rtl/chip_link.v

@@ -0,0 +1,199 @@
+// ============================================================================
+// Chip Link
+// ============================================================================
+//
+// Copyright 2026 Henry Arthur Shulayev Barnes / Catalyst Neuromorphic Ltd
+// Company No. 17054540 — UK Patent Application No. 2602902.6
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// ============================================================================
+
+module chip_link #(
+    parameter CORE_ID_BITS = 7,
+    parameter NEURON_BITS  = 10,
+    parameter DATA_WIDTH   = 16,
+    parameter TX_DEPTH     = 256,
+    parameter RX_DEPTH     = 256
+)(
+    input  wire clk,
+    input  wire rst_n,
+
+    input  wire                        tx_push,
+    input  wire [CORE_ID_BITS-1:0]     tx_core,
+    input  wire [NEURON_BITS-1:0]      tx_neuron,
+    input  wire [7:0]                  tx_payload,
+    output wire                        tx_full,
+
+    output wire [CORE_ID_BITS-1:0]     rx_core,
+    output wire [NEURON_BITS-1:0]      rx_neuron,
+    output wire signed [DATA_WIDTH-1:0] rx_current,
+    input  wire                        rx_pop,
+    output wire                        rx_empty,
+
+    output reg  [7:0]                  link_tx_data,
+    output reg                         link_tx_valid,
+    input  wire                        link_tx_ready,
+
+    input  wire [7:0]                  link_rx_data,
+    input  wire                        link_rx_valid,
+    output wire                        link_rx_ready
+);
+
+    localparam TX_PKT_W = CORE_ID_BITS + NEURON_BITS + 8;
+
+    reg  [TX_PKT_W-1:0] tx_fifo [0:TX_DEPTH-1];
+    reg  [8:0] tx_wr_ptr, tx_rd_ptr;
+    wire [8:0] tx_count = tx_wr_ptr - tx_rd_ptr;
+    wire        tx_empty_i = (tx_wr_ptr == tx_rd_ptr);
+    assign      tx_full    = (tx_count >= TX_DEPTH);
+
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n)
+            tx_wr_ptr <= 0;
+        else if (tx_push && !tx_full) begin
+            tx_fifo[tx_wr_ptr[7:0]] <= {tx_core, tx_neuron, tx_payload};
+            tx_wr_ptr <= tx_wr_ptr + 1;
+        end
+    end
+
+    localparam TX_IDLE = 2'd0, TX_BYTE1 = 2'd1, TX_BYTE2 = 2'd2, TX_BYTE3 = 2'd3;
+    reg [1:0] tx_state;
+    reg [TX_PKT_W-1:0] tx_pkt;
+
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n) begin
+            tx_state     <= TX_IDLE;
+            tx_rd_ptr    <= 0;
+            link_tx_valid <= 0;
+            link_tx_data  <= 0;
+        end else begin
+            link_tx_valid <= 0;
+
+            case (tx_state)
+                TX_IDLE: begin
+                    if (!tx_empty_i && link_tx_ready) begin
+                        tx_pkt    <= tx_fifo[tx_rd_ptr[7:0]];
+                        tx_rd_ptr <= tx_rd_ptr + 1;
+                        link_tx_data  <= 8'h80 | tx_fifo[tx_rd_ptr[7:0]][TX_PKT_W-1 -: CORE_ID_BITS];
+                        link_tx_valid <= 1;
+                        tx_state      <= TX_BYTE1;
+                    end
+                end
+
+                TX_BYTE1: begin
+                    if (link_tx_ready) begin
+                        link_tx_data  <= tx_pkt[NEURON_BITS+7:10];
+                        link_tx_valid <= 1;
+                        tx_state      <= TX_BYTE2;
+                    end
+                end
+
+                TX_BYTE2: begin
+                    if (link_tx_ready) begin
+                        link_tx_data  <= {tx_pkt[9:8], tx_pkt[7:2]};
+                        link_tx_valid <= 1;
+                        tx_state      <= TX_BYTE3;
+                    end
+                end
+
+                TX_BYTE3: begin
+                    if (link_tx_ready) begin
+                        link_tx_data  <= {tx_pkt[1:0], 6'd0};
+                        link_tx_valid <= 1;
+                        tx_state      <= TX_IDLE;
+                    end
+                end
+            endcase
+        end
+    end
+
+    localparam RX_PKT_W = CORE_ID_BITS + NEURON_BITS + DATA_WIDTH;
+
+    localparam RX_IDLE = 2'd0, RX_BYTE1 = 2'd1, RX_BYTE2 = 2'd2, RX_BYTE3 = 2'd3;
+    reg [1:0] rx_state;
+    reg [CORE_ID_BITS-1:0]  rx_pkt_core;
+    reg [NEURON_BITS-1:0]   rx_pkt_neuron;
+    reg [7:0]               rx_pkt_payload;
+    reg                     rx_push;
+
+    assign link_rx_ready = (rx_count < RX_DEPTH - 4);
+
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n) begin
+            rx_state <= RX_IDLE;
+            rx_push  <= 0;
+        end else begin
+            rx_push <= 0;
+
+            case (rx_state)
+                RX_IDLE: begin
+                    if (link_rx_valid && link_rx_data[7]) begin
+                        rx_pkt_core <= link_rx_data[CORE_ID_BITS-1:0];
+                        rx_state    <= RX_BYTE1;
+                    end
+                end
+
+                RX_BYTE1: begin
+                    if (link_rx_valid) begin
+                        rx_pkt_neuron[NEURON_BITS-1:2] <= link_rx_data;
+                        rx_state <= RX_BYTE2;
+                    end
+                end
+
+                RX_BYTE2: begin
+                    if (link_rx_valid) begin
+                        rx_pkt_neuron[1:0]   <= link_rx_data[7:6];
+                        rx_pkt_payload[7:2]  <= link_rx_data[5:0];
+                        rx_state <= RX_BYTE3;
+                    end
+                end
+
+                RX_BYTE3: begin
+                    if (link_rx_valid) begin
+                        rx_pkt_payload[1:0] <= link_rx_data[7:6];
+                        rx_push <= 1;
+                        rx_state <= RX_IDLE;
+                    end
+                end
+            endcase
+        end
+    end
+
+    reg  [RX_PKT_W-1:0] rx_fifo [0:RX_DEPTH-1];
+    reg  [8:0] rx_wr_ptr, rx_rd_ptr;
+    wire [8:0] rx_count = rx_wr_ptr - rx_rd_ptr;
+    assign rx_empty = (rx_wr_ptr == rx_rd_ptr);
+
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n)
+            rx_wr_ptr <= 0;
+        else if (rx_push && rx_count < RX_DEPTH) begin
+            rx_fifo[rx_wr_ptr[7:0]] <= {rx_pkt_core, rx_pkt_neuron,
+                                         {{(DATA_WIDTH-8){1'b0}}, rx_pkt_payload}};
+            rx_wr_ptr <= rx_wr_ptr + 1;
+        end
+    end
+
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n)
+            rx_rd_ptr <= 0;
+        else if (rx_pop && !rx_empty)
+            rx_rd_ptr <= rx_rd_ptr + 1;
+    end
+
+    wire [RX_PKT_W-1:0] rx_top = rx_fifo[rx_rd_ptr[7:0]];
+    assign rx_core    = rx_top[RX_PKT_W-1 -: CORE_ID_BITS];
+    assign rx_neuron  = rx_top[DATA_WIDTH +: NEURON_BITS];
+    assign rx_current = rx_top[DATA_WIDTH-1:0];
+
+endmodule

rtl/host_interface.v

@@ -0,0 +1,550 @@
+// ============================================================================
+// Host Interface
+// ============================================================================
+//
+// Copyright 2026 Henry Arthur Shulayev Barnes / Catalyst Neuromorphic Ltd
+// Company No. 17054540 — UK Patent Application No. 2602902.6
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// ============================================================================
+
+module host_interface #(
+    parameter NUM_CORES      = 4,
+    parameter CORE_ID_BITS   = 2,
+    parameter NUM_NEURONS    = 1024,
+    parameter NEURON_BITS    = 10,
+    parameter DATA_WIDTH     = 16,
+    parameter POOL_ADDR_BITS = 15,
+    parameter COUNT_BITS     = 12,
+    parameter ROUTE_SLOT_BITS = 3,
+    parameter GLOBAL_ROUTE_SLOT_BITS = 2
+)(
+    input  wire       clk,
+    input  wire       rst_n,
+
+    input  wire [7:0] rx_data,
+    input  wire       rx_valid,
+    output reg  [7:0] tx_data,
+    output reg        tx_valid,
+    input  wire       tx_ready,
+
+    output reg                         mesh_start,
+
+    output reg                              mesh_prog_pool_we,
+    output reg  [CORE_ID_BITS-1:0]         mesh_prog_pool_core,
+    output reg  [POOL_ADDR_BITS-1:0]       mesh_prog_pool_addr,
+    output reg  [NEURON_BITS-1:0]          mesh_prog_pool_src,
+    output reg  [NEURON_BITS-1:0]          mesh_prog_pool_target,
+    output reg  signed [DATA_WIDTH-1:0]    mesh_prog_pool_weight,
+    output reg  [1:0]                      mesh_prog_pool_comp,
+
+    output reg                              mesh_prog_index_we,
+    output reg  [CORE_ID_BITS-1:0]         mesh_prog_index_core,
+    output reg  [NEURON_BITS-1:0]          mesh_prog_index_neuron,
+    output reg  [POOL_ADDR_BITS-1:0]       mesh_prog_index_base,
+    output reg  [COUNT_BITS-1:0]           mesh_prog_index_count,
+    output reg  [1:0]                      mesh_prog_index_format,
+
+    output reg                              mesh_prog_route_we,
+    output reg  [CORE_ID_BITS-1:0]         mesh_prog_route_src_core,
+    output reg  [NEURON_BITS-1:0]          mesh_prog_route_src_neuron,
+    output reg  [ROUTE_SLOT_BITS-1:0]      mesh_prog_route_slot,
+    output reg  [CORE_ID_BITS-1:0]         mesh_prog_route_dest_core,
+    output reg  [NEURON_BITS-1:0]          mesh_prog_route_dest_neuron,
+    output reg  signed [DATA_WIDTH-1:0]    mesh_prog_route_weight,
+
+    output reg                              mesh_prog_global_route_we,
+    output reg  [CORE_ID_BITS-1:0]         mesh_prog_global_route_src_core,
+    output reg  [NEURON_BITS-1:0]          mesh_prog_global_route_src_neuron,
+    output reg  [GLOBAL_ROUTE_SLOT_BITS-1:0] mesh_prog_global_route_slot,
+    output reg  [CORE_ID_BITS-1:0]         mesh_prog_global_route_dest_core,
+    output reg  [NEURON_BITS-1:0]          mesh_prog_global_route_dest_neuron,
+    output reg  signed [DATA_WIDTH-1:0]    mesh_prog_global_route_weight,
+
+    output reg                         mesh_ext_valid,
+    output reg  [CORE_ID_BITS-1:0]    mesh_ext_core,
+    output reg  [NEURON_BITS-1:0]     mesh_ext_neuron_id,
+    output reg  signed [DATA_WIDTH-1:0] mesh_ext_current,
+
+    output reg        mesh_learn_enable,
+    output reg        mesh_graded_enable,
+    output reg        mesh_dendritic_enable,
+    output reg        mesh_async_enable,
+    output reg        mesh_threefactor_enable,
+    output reg signed [DATA_WIDTH-1:0] mesh_reward_value,
+    output reg        mesh_noise_enable,
+    output reg        mesh_skip_idle_enable,
+    output reg        mesh_scale_u_enable,
+
+    output reg                              mesh_prog_delay_we,
+    output reg  [CORE_ID_BITS-1:0]         mesh_prog_delay_core,
+    output reg  [POOL_ADDR_BITS-1:0]       mesh_prog_delay_addr,
+    output reg  [5:0]                      mesh_prog_delay_value,
+
+    output reg                              mesh_prog_ucode_we,
+    output reg  [CORE_ID_BITS-1:0]         mesh_prog_ucode_core,
+    output reg  [7:0]                      mesh_prog_ucode_addr,
+    output reg  [31:0]                     mesh_prog_ucode_data,
+
+    output reg                         mesh_prog_param_we,
+    output reg  [CORE_ID_BITS-1:0]    mesh_prog_param_core,
+    output reg  [NEURON_BITS-1:0]     mesh_prog_param_neuron,
+    output reg  [4:0]                 mesh_prog_param_id,
+    output reg  signed [DATA_WIDTH-1:0] mesh_prog_param_value,
+
+    output reg                              mesh_probe_read,
+    output reg  [CORE_ID_BITS-1:0]         mesh_probe_core,
+    output reg  [NEURON_BITS-1:0]          mesh_probe_neuron,
+    output reg  [4:0]                      mesh_probe_state_id,
+    output reg  [POOL_ADDR_BITS-1:0]       mesh_probe_pool_addr,
+    input  wire signed [DATA_WIDTH-1:0]    mesh_probe_data,
+    input  wire                            mesh_probe_valid,
+
+    output reg  [7:0]  mesh_dvfs_stall,
+
+    input  wire       mesh_timestep_done,
+    input  wire [5:0] mesh_state,
+    input  wire [31:0] mesh_total_spikes,
+    input  wire [31:0] mesh_timestep_count
+);
+
+    localparam CMD_PROG_POOL   = 8'h01;
+    localparam CMD_PROG_ROUTE  = 8'h02;
+    localparam CMD_STIMULUS    = 8'h03;
+    localparam CMD_RUN         = 8'h04;
+    localparam CMD_STATUS      = 8'h05;
+    localparam CMD_LEARN_CFG   = 8'h06;
+    localparam CMD_PROG_NEURON = 8'h07;
+    localparam CMD_PROG_INDEX  = 8'h08;
+    localparam CMD_REWARD      = 8'h09;
+    localparam CMD_PROG_DELAY  = 8'h0A;
+    localparam CMD_PROG_FORMAT = 8'h0B;
+    localparam CMD_PROG_LEARN  = 8'h0C;
+    localparam CMD_NOISE_SEED  = 8'h0D;
+    localparam CMD_READ_WEIGHT = 8'h0E;
+    localparam CMD_PROG_DEND_TREE = 8'h0F;
+    localparam CMD_PROG_GLOBAL_ROUTE = 8'h10;
+    localparam CMD_DVFS_CFG    = 8'h1C;
+    localparam CMD_RESET_PERF  = 8'h1D;
+
+    localparam RESP_ACK  = 8'hAA;
+    localparam RESP_DONE = 8'hDD;
+
+    localparam HI_IDLE        = 6'd0;
+    localparam HI_RECV        = 6'd1;
+    localparam HI_EXEC_POOL   = 6'd2;
+    localparam HI_EXEC_ROUTE  = 6'd3;
+    localparam HI_EXEC_STIM   = 6'd4;
+    localparam HI_SEND_ACK    = 6'd5;
+    localparam HI_RUN_START   = 6'd6;
+    localparam HI_RUN_WAIT    = 6'd7;
+    localparam HI_RUN_LOOP    = 6'd8;
+    localparam HI_SEND_RESP   = 6'd9;
+    localparam HI_EXEC_STATUS = 6'd10;
+    localparam HI_SEND_WAIT   = 6'd11;
+    localparam HI_EXEC_LEARN  = 6'd12;
+    localparam HI_EXEC_PARAM  = 6'd13;
+    localparam HI_EXEC_INDEX  = 6'd14;
+    localparam HI_EXEC_REWARD = 6'd15;
+    localparam HI_EXEC_DELAY     = 6'd16;
+    localparam HI_EXEC_FORMAT    = 6'd17;
+    localparam HI_EXEC_LEARN_MC  = 6'd18;
+    localparam HI_EXEC_SEED      = 6'd19;
+    localparam HI_EXEC_READ_WT   = 6'd20;
+    localparam HI_EXEC_GLOBAL_ROUTE = 6'd21;
+    localparam HI_PROBE_WAIT    = 6'd22;
+    localparam HI_PROBE_RESP    = 6'd23;
+    localparam HI_EXEC_DEND_TREE = 6'd24;
+    localparam HI_EXEC_DVFS      = 6'd25;
+    localparam HI_EXEC_RESET_PERF = 6'd26;
+
+    reg [5:0]  state;
+    reg [7:0]  cmd;
+    reg [4:0]  byte_cnt;
+    reg [4:0]  payload_len;
+    reg [7:0]  payload [0:15];
+
+    reg [15:0] run_remaining;
+    reg [31:0] run_spike_base;
+
+    reg [7:0]  resp_buf [0:4];
+    reg [2:0]  resp_len;
+    reg [2:0]  resp_idx;
+
+    function [4:0] cmd_payload_len;
+        input [7:0] opcode;
+        case (opcode)
+            CMD_PROG_POOL:   cmd_payload_len = 5'd8;
+            CMD_PROG_ROUTE:  cmd_payload_len = 5'd9;
+            CMD_STIMULUS:    cmd_payload_len = 5'd5;
+            CMD_RUN:         cmd_payload_len = 5'd2;
+            CMD_STATUS:      cmd_payload_len = 5'd0;
+            CMD_LEARN_CFG:   cmd_payload_len = 5'd1;
+            CMD_PROG_NEURON: cmd_payload_len = 5'd6;
+            CMD_PROG_INDEX:  cmd_payload_len = 5'd7;
+            CMD_REWARD:      cmd_payload_len = 5'd2;
+            CMD_PROG_DELAY:  cmd_payload_len = 5'd4;
+            CMD_PROG_FORMAT: cmd_payload_len = 5'd4;
+            CMD_PROG_LEARN:  cmd_payload_len = 5'd6;
+            CMD_NOISE_SEED:  cmd_payload_len = 5'd3;
+            CMD_READ_WEIGHT: cmd_payload_len = 5'd4;
+            CMD_PROG_DEND_TREE: cmd_payload_len = 5'd4;
+            CMD_PROG_GLOBAL_ROUTE: cmd_payload_len = 5'd9;
+            CMD_DVFS_CFG:    cmd_payload_len = 5'd1;
+            CMD_RESET_PERF:  cmd_payload_len = 5'd1;
+            default:         cmd_payload_len = 5'd0;
+        endcase
+    endfunction
+
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n) begin
+            state              <= HI_IDLE;
+            cmd                <= 0;
+            byte_cnt           <= 0;
+            payload_len        <= 0;
+            tx_data            <= 0;
+            tx_valid           <= 0;
+            mesh_start         <= 0;
+            mesh_prog_pool_we  <= 0;
+            mesh_prog_pool_core   <= 0;
+            mesh_prog_pool_addr   <= 0;
+            mesh_prog_pool_src    <= 0;
+            mesh_prog_pool_target <= 0;
+            mesh_prog_pool_weight <= 0;
+            mesh_prog_pool_comp   <= 0;
+            mesh_prog_index_we     <= 0;
+            mesh_prog_index_core   <= 0;
+            mesh_prog_index_neuron <= 0;
+            mesh_prog_index_base   <= 0;
+            mesh_prog_index_count  <= 0;
+            mesh_prog_index_format <= 0;
+            mesh_prog_route_we <= 0;
+            mesh_prog_route_src_core   <= 0;
+            mesh_prog_route_src_neuron <= 0;
+            mesh_prog_route_slot       <= 0;
+            mesh_prog_route_dest_core  <= 0;
+            mesh_prog_route_dest_neuron<= 0;
+            mesh_prog_route_weight     <= 0;
+            mesh_prog_global_route_we          <= 0;
+            mesh_prog_global_route_src_core    <= 0;
+            mesh_prog_global_route_src_neuron  <= 0;
+            mesh_prog_global_route_slot        <= 0;
+            mesh_prog_global_route_dest_core   <= 0;
+            mesh_prog_global_route_dest_neuron <= 0;
+            mesh_prog_global_route_weight      <= 0;
+            mesh_ext_valid     <= 0;
+            mesh_ext_core      <= 0;
+            mesh_ext_neuron_id <= 0;
+            mesh_ext_current   <= 0;
+            mesh_learn_enable     <= 0;
+            mesh_graded_enable    <= 0;
+            mesh_dendritic_enable <= 0;
+            mesh_async_enable     <= 0;
+            mesh_threefactor_enable <= 0;
+            mesh_noise_enable     <= 0;
+            mesh_skip_idle_enable <= 0;
+            mesh_scale_u_enable   <= 0;
+            mesh_reward_value     <= 0;
+            mesh_prog_delay_we     <= 0;
+            mesh_prog_delay_core   <= 0;
+            mesh_prog_delay_addr   <= 0;
+            mesh_prog_delay_value  <= 0;
+            mesh_prog_ucode_we     <= 0;
+            mesh_prog_ucode_core   <= 0;
+            mesh_prog_ucode_addr   <= 0;
+            mesh_prog_ucode_data   <= 0;
+            mesh_prog_param_we <= 0;
+            mesh_prog_param_core   <= 0;
+            mesh_prog_param_neuron <= 0;
+            mesh_prog_param_id     <= 0;
+            mesh_prog_param_value  <= 0;
+            mesh_probe_read    <= 0;
+            mesh_probe_core    <= 0;
+            mesh_probe_neuron  <= 0;
+            mesh_probe_state_id <= 0;
+            mesh_probe_pool_addr <= 0;
+            mesh_dvfs_stall    <= 0;
+            run_remaining      <= 0;
+            run_spike_base     <= 0;
+            resp_len           <= 0;
+            resp_idx           <= 0;
+        end else begin
+            mesh_prog_pool_we  <= 0;
+            mesh_prog_index_we <= 0;
+            mesh_prog_route_we <= 0;
+            mesh_prog_global_route_we <= 0;
+            mesh_prog_delay_we <= 0;
+            mesh_prog_ucode_we <= 0;
+            mesh_prog_param_we <= 0;
+            mesh_probe_read    <= 0;
+            mesh_ext_valid     <= 0;
+            mesh_start         <= 0;
+            tx_valid           <= 0;
+
+            case (state)
+
+                HI_IDLE: begin
+                    if (rx_valid) begin
+                        cmd         <= rx_data;
+                        payload_len <= cmd_payload_len(rx_data);
+                        byte_cnt    <= 0;
+                        if (cmd_payload_len(rx_data) == 0) begin
+                            case (rx_data)
+                                CMD_STATUS: state <= HI_EXEC_STATUS;
+                                default:    state <= HI_IDLE;
+                            endcase
+                        end else begin
+                            state <= HI_RECV;
+                        end
+                    end
+                end
+
+                HI_RECV: begin
+                    if (rx_valid) begin
+                        payload[byte_cnt] <= rx_data;
+                        if (byte_cnt == payload_len - 1) begin
+                            case (cmd)
+                                CMD_PROG_POOL:   state <= HI_EXEC_POOL;
+                                CMD_PROG_ROUTE:  state <= HI_EXEC_ROUTE;
+                                CMD_STIMULUS:    state <= HI_EXEC_STIM;
+                                CMD_RUN:         state <= HI_RUN_START;
+                                CMD_LEARN_CFG:   state <= HI_EXEC_LEARN;
+                                CMD_PROG_NEURON: state <= HI_EXEC_PARAM;
+                                CMD_PROG_INDEX:  state <= HI_EXEC_INDEX;
+                                CMD_REWARD:      state <= HI_EXEC_REWARD;
+                                CMD_PROG_DELAY:  state <= HI_EXEC_DELAY;
+                                CMD_PROG_FORMAT: state <= HI_EXEC_FORMAT;
+                                CMD_PROG_LEARN:  state <= HI_EXEC_LEARN_MC;
+                                CMD_NOISE_SEED:  state <= HI_EXEC_SEED;
+                                CMD_READ_WEIGHT: state <= HI_EXEC_READ_WT;
+                                CMD_PROG_DEND_TREE: state <= HI_EXEC_DEND_TREE;
+                                CMD_PROG_GLOBAL_ROUTE: state <= HI_EXEC_GLOBAL_ROUTE;
+                                CMD_DVFS_CFG:    state <= HI_EXEC_DVFS;
+                                CMD_RESET_PERF:  state <= HI_EXEC_RESET_PERF;
+                                default:         state <= HI_IDLE;
+                            endcase
+                        end else begin
+                            byte_cnt <= byte_cnt + 1;
+                        end
+                    end
+                end
+
+                HI_EXEC_POOL: begin
+                    mesh_prog_pool_we     <= 1;
+                    mesh_prog_pool_core   <= payload[0][CORE_ID_BITS-1:0];
+                    mesh_prog_pool_addr   <= {payload[1], payload[2]};
+                    mesh_prog_pool_comp   <= payload[3][7:6];
+                    mesh_prog_pool_src    <= {payload[3][5:4], payload[4]};
+                    mesh_prog_pool_target <= {payload[3][3:2], payload[5]};
+                    mesh_prog_pool_weight <= {payload[6], payload[7]};
+                    state <= HI_SEND_ACK;
+                end
+
+                HI_EXEC_INDEX: begin
+                    mesh_prog_index_we     <= 1;
+                    mesh_prog_index_core   <= payload[0][CORE_ID_BITS-1:0];
+                    mesh_prog_index_neuron <= {payload[1], payload[2]};
+                    mesh_prog_index_base   <= {payload[3], payload[4]};
+                    mesh_prog_index_count  <= {payload[5], payload[6]};
+                    mesh_prog_index_format <= payload[5][7:6];
+                    state <= HI_SEND_ACK;
+                end
+
+                HI_EXEC_REWARD: begin
+                    mesh_reward_value <= {payload[0], payload[1]};
+                    state <= HI_SEND_ACK;
+                end
+
+                HI_EXEC_ROUTE: begin
+                    mesh_prog_route_we         <= 1;
+                    mesh_prog_route_src_core   <= payload[0][CORE_ID_BITS-1:0];
+                    mesh_prog_route_src_neuron <= {payload[1], payload[2]};
+                    mesh_prog_route_slot       <= payload[3][ROUTE_SLOT_BITS-1:0];
+                    mesh_prog_route_dest_core  <= payload[4][CORE_ID_BITS-1:0];
+                    mesh_prog_route_dest_neuron<= {payload[5], payload[6]};
+                    mesh_prog_route_weight     <= {payload[7], payload[8]};
+                    state <= HI_SEND_ACK;
+                end
+
+                HI_EXEC_STIM: begin
+                    mesh_ext_valid     <= 1;
+                    mesh_ext_core      <= payload[0][CORE_ID_BITS-1:0];
+                    mesh_ext_neuron_id <= {payload[1], payload[2]};
+                    mesh_ext_current   <= {payload[3], payload[4]};
+                    state <= HI_SEND_ACK;
+                end
+
+                HI_EXEC_LEARN: begin
+                    mesh_learn_enable     <= payload[0][0];
+                    mesh_graded_enable    <= payload[0][1];
+                    mesh_dendritic_enable <= payload[0][2];
+                    mesh_async_enable     <= payload[0][3];
+                    mesh_threefactor_enable <= payload[0][4];
+                    mesh_noise_enable      <= payload[0][5];
+                    mesh_skip_idle_enable  <= payload[0][6];
+                    mesh_scale_u_enable    <= payload[0][7];
+                    state <= HI_SEND_ACK;
+                end
+
+                HI_EXEC_PARAM: begin
+                    mesh_prog_param_we     <= 1;
+                    mesh_prog_param_core   <= payload[0][CORE_ID_BITS-1:0];
+                    mesh_prog_param_neuron <= {payload[1], payload[2]};
+                    mesh_prog_param_id     <= payload[3][4:0];
+                    mesh_prog_param_value  <= {payload[4], payload[5]};
+                    state <= HI_SEND_ACK;
+                end
+
+                HI_SEND_ACK: begin
+                    if (tx_ready) begin
+                        tx_data  <= RESP_ACK;
+                        tx_valid <= 1;
+                        state    <= HI_IDLE;
+                    end
+                end
+
+                HI_RUN_START: begin
+                    run_remaining  <= {payload[0], payload[1]};
+                    run_spike_base <= mesh_total_spikes;
+                    mesh_start     <= 1;
+                    state          <= HI_RUN_WAIT;
+                end
+
+                HI_RUN_WAIT: begin
+                    if (mesh_timestep_done) begin
+                        state <= HI_RUN_LOOP;
+                    end
+                end
+
+                HI_RUN_LOOP: begin
+                    if (run_remaining <= 1) begin
+                        resp_buf[0] <= RESP_DONE;
+                        resp_buf[1] <= (mesh_total_spikes - run_spike_base) >> 24;
+                        resp_buf[2] <= (mesh_total_spikes - run_spike_base) >> 16;
+                        resp_buf[3] <= (mesh_total_spikes - run_spike_base) >> 8;
+                        resp_buf[4] <= (mesh_total_spikes - run_spike_base);
+                        resp_len    <= 5;
+                        resp_idx    <= 0;
+                        state       <= HI_SEND_RESP;
+                    end else begin
+                        run_remaining <= run_remaining - 1;
+                        mesh_start    <= 1;
+                        state         <= HI_RUN_WAIT;
+                    end
+                end
+
+                HI_EXEC_STATUS: begin
+                    resp_buf[0] <= {3'b0, mesh_state};
+                    resp_buf[1] <= mesh_timestep_count >> 24;
+                    resp_buf[2] <= mesh_timestep_count >> 16;
+                    resp_buf[3] <= mesh_timestep_count >> 8;
+                    resp_buf[4] <= mesh_timestep_count;
+                    resp_len    <= 5;
+                    resp_idx    <= 0;
+                    state       <= HI_SEND_RESP;
+                end
+
+                HI_SEND_RESP: begin
+                    if (tx_ready) begin
+                        tx_data  <= resp_buf[resp_idx];
+                        tx_valid <= 1;
+                        state    <= HI_SEND_WAIT;
+                    end
+                end
+
+                HI_SEND_WAIT: begin
+                    if (resp_idx == resp_len - 1) begin
+                        state <= HI_IDLE;
+                    end else begin
+                        resp_idx <= resp_idx + 1;
+                        state    <= HI_SEND_RESP;
+                    end
+                end
+
+                HI_EXEC_DELAY: begin
+                    mesh_prog_delay_we    <= 1;
+                    mesh_prog_delay_core  <= payload[0][CORE_ID_BITS-1:0];
+                    mesh_prog_delay_addr  <= {payload[1], payload[2]};
+                    mesh_prog_delay_value <= payload[3][5:0];
+                    state <= HI_SEND_ACK;
+                end
+                HI_EXEC_FORMAT:   state <= HI_SEND_ACK;
+
+                HI_EXEC_LEARN_MC: begin
+                    mesh_prog_ucode_we   <= 1;
+                    mesh_prog_ucode_core <= payload[0][CORE_ID_BITS-1:0];
+                    mesh_prog_ucode_addr <= payload[1][7:0];
+                    mesh_prog_ucode_data <= {payload[2], payload[3], payload[4], payload[5]};
+                    state <= HI_SEND_ACK;
+                end
+                HI_EXEC_SEED:     state <= HI_SEND_ACK;
+
+                HI_EXEC_READ_WT: begin
+                    mesh_probe_read     <= 1;
+                    mesh_probe_core     <= payload[0][CORE_ID_BITS-1:0];
+                    mesh_probe_neuron   <= {payload[1], payload[2]};
+                    mesh_probe_state_id <= payload[3][4:0];
+                    mesh_probe_pool_addr <= {payload[1], payload[2]};
+                    state <= HI_PROBE_WAIT;
+                end
+
+                HI_PROBE_WAIT: begin
+                    if (mesh_probe_valid) begin
+                        resp_buf[0] <= mesh_probe_data[15:8];
+                        resp_buf[1] <= mesh_probe_data[7:0];
+                        resp_len    <= 2;
+                        resp_idx    <= 0;
+                        state       <= HI_SEND_RESP;
+                    end
+                end
+
+                HI_EXEC_GLOBAL_ROUTE: begin
+                    mesh_prog_global_route_we          <= 1;
+                    mesh_prog_global_route_src_core    <= payload[0][CORE_ID_BITS-1:0];
+                    mesh_prog_global_route_src_neuron  <= {payload[1], payload[2]};
+                    mesh_prog_global_route_slot        <= payload[3][GLOBAL_ROUTE_SLOT_BITS-1:0];
+                    mesh_prog_global_route_dest_core   <= payload[4][CORE_ID_BITS-1:0];
+                    mesh_prog_global_route_dest_neuron <= {payload[5], payload[6]};
+                    mesh_prog_global_route_weight      <= {payload[7], payload[8]};
+                    state <= HI_SEND_ACK;
+                end
+
+                HI_EXEC_DEND_TREE: begin
+                    mesh_prog_param_we     <= 1;
+                    mesh_prog_param_core   <= payload[0][CORE_ID_BITS-1:0];
+                    mesh_prog_param_neuron <= {payload[1], payload[2]};
+                    mesh_prog_param_id     <= 5'd15;
+                    mesh_prog_param_value  <= {{(DATA_WIDTH-6){1'b0}}, payload[3][5:0]};
+                    state <= HI_SEND_ACK;
+                end
+
+                HI_EXEC_DVFS: begin
+                    mesh_dvfs_stall <= payload[0];
+                    state <= HI_SEND_ACK;
+                end
+
+                HI_EXEC_RESET_PERF: begin
+                    mesh_prog_param_we     <= 1;
+                    mesh_prog_param_core   <= payload[0][CORE_ID_BITS-1:0];
+                    mesh_prog_param_neuron <= 0;
+                    mesh_prog_param_id     <= 5'd28;
+                    mesh_prog_param_value  <= 0;
+                    state <= HI_SEND_ACK;
+                end
+
+                default: state <= HI_IDLE;
+            endcase
+        end
+    end
+
+endmodule

rtl/lif_neuron.v

@@ -0,0 +1,71 @@
+// ============================================================================
+// Leaky Integrate-and-Fire (LIF) Neuron
+// ============================================================================
+//
+// Copyright 2026 Henry Arthur Shulayev Barnes / Catalyst Neuromorphic Ltd
+// Company No. 17054540 — UK Patent Application No. 2602902.6
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// ============================================================================
+
+module lif_neuron #(
+    parameter DATA_WIDTH    = 16,
+    parameter THRESHOLD     = 16'd1000,
+    parameter LEAK_RATE     = 16'd2,
+    parameter RESTING_POT   = 16'd0,
+    parameter REFRAC_CYCLES = 4
+)(
+    input  wire                    clk,
+    input  wire                    rst_n,
+    input  wire                    enable,
+    input  wire signed [DATA_WIDTH-1:0] synaptic_input,
+    output reg                     spike,
+    output reg  [DATA_WIDTH-1:0]   membrane_pot
+);
+
+    reg [DATA_WIDTH-1:0] potential;
+    reg [3:0]            refrac_counter;
+
+    wire in_refractory = (refrac_counter > 0);
+
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n) begin
+            potential      <= RESTING_POT;
+            spike          <= 1'b0;
+            refrac_counter <= 4'd0;
+            membrane_pot   <= RESTING_POT;
+
+        end else if (enable) begin
+            spike <= 1'b0;
+
+            if (in_refractory) begin
+                refrac_counter <= refrac_counter - 1;
+                potential      <= RESTING_POT;
+
+            end else begin
+                if (potential + synaptic_input > THRESHOLD) begin
+                    spike          <= 1'b1;
+                    potential      <= RESTING_POT;
+                    refrac_counter <= REFRAC_CYCLES[3:0];
+                end else if (potential + synaptic_input < RESTING_POT + LEAK_RATE) begin
+                    potential <= RESTING_POT;
+                end else begin
+                    potential <= potential + synaptic_input - LEAK_RATE;
+                end
+            end
+
+            membrane_pot <= potential;
+        end
+    end
+
+endmodule

rtl/mmio_bridge.v

@@ -0,0 +1,447 @@
+// ============================================================================
+// MMIO Bridge
+// ============================================================================
+//
+// Copyright 2026 Henry Arthur Shulayev Barnes / Catalyst Neuromorphic Ltd
+// Company No. 17054540 — UK Patent Application No. 2602902.6
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// ============================================================================
+
+`timescale 1ns/1ps
+
+module mmio_bridge #(
+    parameter CORE_ID_BITS   = 7,
+    parameter NEURON_BITS    = 10,
+    parameter DATA_WIDTH     = 16,
+    parameter POOL_ADDR_BITS = 15,
+    parameter ROUTE_SLOT_BITS = 3,
+    parameter GLOBAL_ROUTE_SLOT_BITS = 2,
+    parameter COUNT_BITS     = 12
+)(
+    input  wire        clk,
+    input  wire        rst_n,
+
+    input  wire        mgmt_phase,
+
+    input  wire        mmio_valid,
+    input  wire        mmio_we,
+    input  wire [15:0] mmio_addr,
+    input  wire [31:0] mmio_wdata,
+    output reg  [31:0] mmio_rdata,
+    output reg         mmio_ready,
+
+    output reg                          mesh_start,
+    output reg                          ext_valid,
+    output reg  [CORE_ID_BITS-1:0]     ext_core,
+    output reg  [NEURON_BITS-1:0]      ext_neuron_id,
+    output reg  signed [DATA_WIDTH-1:0] ext_current,
+
+    output reg                          prog_param_we,
+    output reg  [CORE_ID_BITS-1:0]     prog_param_core,
+    output reg  [NEURON_BITS-1:0]      prog_param_neuron,
+    output reg  [4:0]                   prog_param_id,
+    output reg  signed [DATA_WIDTH-1:0] prog_param_value,
+
+    output reg                          probe_read,
+    output reg  [CORE_ID_BITS-1:0]     probe_core,
+    output reg  [NEURON_BITS-1:0]      probe_neuron,
+    output reg  [3:0]                   probe_state_id,
+    input  wire signed [DATA_WIDTH-1:0] probe_data,
+    input  wire                         probe_valid,
+
+    output reg  [7:0]  uart_tx_data,
+    output reg         uart_tx_valid,
+    input  wire        uart_tx_ready,
+    input  wire [7:0]  uart_rx_data,
+    input  wire        uart_rx_valid,
+
+    input  wire        rv_halted,
+    input  wire        rv_running,
+    input  wire [31:0] timestep_count,
+
+    output reg         learn_enable,
+    output reg         graded_enable,
+    output reg         dendritic_enable,
+    output reg         async_enable,
+    output reg         threefactor_enable,
+    output reg         noise_enable,
+    output reg         skip_idle_enable,
+
+    output reg  signed [DATA_WIDTH-1:0] reward_value,
+
+    output reg                              prog_route_we,
+    output reg  [CORE_ID_BITS-1:0]         prog_route_src_core,
+    output reg  [NEURON_BITS-1:0]          prog_route_src_neuron,
+    output reg  [ROUTE_SLOT_BITS-1:0]      prog_route_slot,
+    output reg  [CORE_ID_BITS-1:0]         prog_route_dest_core,
+    output reg  [NEURON_BITS-1:0]          prog_route_dest_neuron,
+    output reg  signed [DATA_WIDTH-1:0]    prog_route_weight,
+
+    output reg                              prog_delay_we,
+    output reg  [CORE_ID_BITS-1:0]         prog_delay_core,
+    output reg  [POOL_ADDR_BITS-1:0]       prog_delay_addr,
+    output reg  [5:0]                      prog_delay_value,
+
+    output reg                              prog_ucode_we,
+    output reg  [CORE_ID_BITS-1:0]         prog_ucode_core,
+    output reg  [7:0]                      prog_ucode_addr,
+    output reg  [31:0]                     prog_ucode_data,
+
+    output reg  [7:0]                      dvfs_stall,
+
+    output reg                              prog_index_we,
+    output reg  [CORE_ID_BITS-1:0]         prog_index_core,
+    output reg  [NEURON_BITS-1:0]          prog_index_neuron,
+    output reg  [POOL_ADDR_BITS-1:0]       prog_index_base,
+    output reg  [COUNT_BITS-1:0]           prog_index_count,
+
+    output reg                              prog_noise_seed_we,
+    output reg  [CORE_ID_BITS-1:0]         prog_noise_seed_core,
+    output reg  [31:0]                     prog_noise_seed_value,
+
+    output reg                              prog_dend_parent_we,
+    output reg  [CORE_ID_BITS-1:0]         prog_dend_parent_core,
+    output reg  [NEURON_BITS-1:0]          prog_dend_parent_neuron,
+    output reg  [7:0]                      prog_dend_parent_data,
+
+    output reg                              prog_global_route_we,
+    output reg  [CORE_ID_BITS-1:0]         prog_global_route_src_core,
+    output reg  [NEURON_BITS-1:0]          prog_global_route_src_neuron,
+    output reg  [GLOBAL_ROUTE_SLOT_BITS-1:0] prog_global_route_slot,
+    output reg  [CORE_ID_BITS-1:0]         prog_global_route_dest_core,
+    output reg  [NEURON_BITS-1:0]          prog_global_route_dest_neuron,
+    output reg  signed [DATA_WIDTH-1:0]    prog_global_route_weight,
+
+    input  wire [31:0] perf_spike_count,
+    input  wire [31:0] perf_synop_count,
+    input  wire [31:0] perf_active_cycles,
+    input  wire [31:0] perf_power_estimate,
+
+    output reg                             perf_reset_we,
+    output reg  [CORE_ID_BITS-1:0]        perf_reset_core,
+
+    output reg  [31:0] debug_bp_addr_0,
+    output reg  [31:0] debug_bp_addr_1,
+    output reg  [31:0] debug_bp_addr_2,
+    output reg  [31:0] debug_bp_addr_3,
+    output reg  [3:0]  debug_bp_enable,
+    output reg         debug_resume,
+    output reg         debug_halt_req,
+    output reg         debug_single_step
+);
+
+    reg [CORE_ID_BITS-1:0]  sel_core;
+    reg [NEURON_BITS-1:0]   sel_neuron;
+    reg [POOL_ADDR_BITS-1:0] sel_pool_addr;
+
+    reg [CORE_ID_BITS-1:0]         route_dest_core;
+    reg [NEURON_BITS-1:0]          route_dest_neuron;
+    reg signed [DATA_WIDTH-1:0]    route_weight;
+
+    reg [POOL_ADDR_BITS-1:0]       index_base;
+
+    reg [7:0]                      ucode_addr;
+
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n) begin
+            mmio_rdata     <= 32'd0;
+            mmio_ready     <= 1'b0;
+            mesh_start     <= 1'b0;
+            ext_valid      <= 1'b0;
+            ext_core       <= 0;
+            ext_neuron_id  <= 0;
+            ext_current    <= 0;
+            prog_param_we  <= 1'b0;
+            prog_param_core   <= 0;
+            prog_param_neuron <= 0;
+            prog_param_id     <= 0;
+            prog_param_value  <= 0;
+            probe_read     <= 1'b0;
+            probe_core     <= 0;
+            probe_neuron   <= 0;
+            probe_state_id <= 0;
+            uart_tx_data   <= 8'd0;
+            uart_tx_valid  <= 1'b0;
+            sel_core       <= 0;
+            sel_neuron     <= 0;
+            sel_pool_addr  <= 0;
+            learn_enable       <= 1'b0;
+            graded_enable      <= 1'b0;
+            dendritic_enable   <= 1'b0;
+            async_enable       <= 1'b0;
+            threefactor_enable <= 1'b0;
+            noise_enable       <= 1'b0;
+            skip_idle_enable   <= 1'b0;
+            reward_value       <= 0;
+            prog_route_we          <= 1'b0;
+            prog_route_src_core    <= 0;
+            prog_route_src_neuron  <= 0;
+            prog_route_slot        <= 0;
+            prog_route_dest_core   <= 0;
+            prog_route_dest_neuron <= 0;
+            prog_route_weight      <= 0;
+            route_dest_core        <= 0;
+            route_dest_neuron      <= 0;
+            route_weight           <= 0;
+            prog_delay_we    <= 1'b0;
+            prog_delay_core  <= 0;
+            prog_delay_addr  <= 0;
+            prog_delay_value <= 0;
+            prog_ucode_we   <= 1'b0;
+            prog_ucode_core <= 0;
+            prog_ucode_addr <= 0;
+            prog_ucode_data <= 0;
+            ucode_addr      <= 0;
+            dvfs_stall       <= 8'd0;
+            prog_index_we     <= 1'b0;
+            prog_index_core   <= 0;
+            prog_index_neuron <= 0;
+            prog_index_base   <= 0;
+            prog_index_count  <= 0;
+            index_base        <= 0;
+            prog_noise_seed_we    <= 1'b0;
+            prog_noise_seed_core  <= 0;
+            prog_noise_seed_value <= 0;
+            prog_dend_parent_we     <= 1'b0;
+            prog_dend_parent_core   <= 0;
+            prog_dend_parent_neuron <= 0;
+            prog_dend_parent_data   <= 0;
+            prog_global_route_we          <= 1'b0;
+            prog_global_route_src_core    <= 0;
+            prog_global_route_src_neuron  <= 0;
+            prog_global_route_slot        <= 0;
+            prog_global_route_dest_core   <= 0;
+            prog_global_route_dest_neuron <= 0;
+            prog_global_route_weight      <= 0;
+            perf_reset_we   <= 1'b0;
+            perf_reset_core <= 0;
+            debug_bp_addr_0    <= 32'd0;
+            debug_bp_addr_1    <= 32'd0;
+            debug_bp_addr_2    <= 32'd0;
+            debug_bp_addr_3    <= 32'd0;
+            debug_bp_enable    <= 4'd0;
+            debug_resume       <= 1'b0;
+            debug_halt_req     <= 1'b0;
+            debug_single_step  <= 1'b0;
+        end else begin
+            mmio_ready     <= 1'b0;
+            mesh_start     <= 1'b0;
+            ext_valid      <= 1'b0;
+            prog_param_we  <= 1'b0;
+            probe_read     <= 1'b0;
+            uart_tx_valid  <= 1'b0;
+            prog_route_we        <= 1'b0;
+            prog_delay_we        <= 1'b0;
+            prog_ucode_we        <= 1'b0;
+            prog_index_we        <= 1'b0;
+            prog_noise_seed_we   <= 1'b0;
+            prog_dend_parent_we  <= 1'b0;
+            prog_global_route_we <= 1'b0;
+            perf_reset_we        <= 1'b0;
+            debug_resume         <= 1'b0;
+            debug_halt_req       <= 1'b0;
+            debug_single_step    <= 1'b0;
+
+            if (mmio_valid && !mmio_ready) begin
+                mmio_ready <= 1'b1;
+
+                if (mmio_we) begin
+                    case (mmio_addr)
+                        16'h0000: begin
+                            if (mmio_wdata[0]) mesh_start <= 1'b1;
+                        end
+                        16'h0004: sel_core   <= mmio_wdata[CORE_ID_BITS-1:0];
+                        16'h0008: sel_neuron <= mmio_wdata[NEURON_BITS-1:0];
+                        16'h000C: begin
+                            prog_param_we     <= mgmt_phase;
+                            prog_param_core   <= sel_core;
+                            prog_param_neuron <= sel_neuron;
+                            prog_param_id     <= mmio_wdata[20:16];
+                            prog_param_value  <= mmio_wdata[DATA_WIDTH-1:0];
+                        end
+                        16'h0010: sel_pool_addr <= mmio_wdata[POOL_ADDR_BITS-1:0];
+                        16'h0018: begin
+                            ext_valid     <= 1'b1;
+                            ext_core      <= sel_core;
+                            ext_neuron_id <= mmio_wdata[NEURON_BITS-1:0];
+                            ext_current   <= mmio_wdata[DATA_WIDTH+NEURON_BITS-1:NEURON_BITS];
+                        end
+                        16'h0020: begin
+                            uart_tx_data  <= mmio_wdata[7:0];
+                            uart_tx_valid <= 1'b1;
+                        end
+
+
+                        16'h0030: begin
+                            if (mgmt_phase) begin
+                                learn_enable       <= mmio_wdata[0];
+                                graded_enable      <= mmio_wdata[1];
+                                dendritic_enable   <= mmio_wdata[2];
+                                async_enable       <= mmio_wdata[3];
+                                threefactor_enable <= mmio_wdata[4];
+                                noise_enable       <= mmio_wdata[5];
+                                skip_idle_enable   <= mmio_wdata[6];
+                            end
+                        end
+
+                        16'h0034: begin
+                            if (mgmt_phase)
+                                reward_value <= mmio_wdata[DATA_WIDTH-1:0];
+                        end
+
+                        16'h0038: begin
+                            route_dest_core <= mmio_wdata[CORE_ID_BITS-1:0];
+                        end
+
+                        16'h003C: begin
+                            route_dest_neuron <= mmio_wdata[NEURON_BITS-1:0];
+                        end
+
+                        16'h0040: begin
+                            route_weight <= mmio_wdata[DATA_WIDTH-1:0];
+                        end
+
+                        16'h0044: begin
+                            if (mgmt_phase) begin
+                                prog_route_we          <= 1'b1;
+                                prog_route_src_core    <= sel_core;
+                                prog_route_src_neuron  <= sel_neuron;
+                                prog_route_slot        <= mmio_wdata[ROUTE_SLOT_BITS-1:0];
+                                prog_route_dest_core   <= route_dest_core;
+                                prog_route_dest_neuron <= route_dest_neuron;
+                                prog_route_weight      <= route_weight;
+                            end
+                        end
+
+                        16'h0048: begin
+                            if (mgmt_phase) begin
+                                prog_delay_we    <= 1'b1;
+                                prog_delay_core  <= sel_core;
+                                prog_delay_addr  <= sel_pool_addr;
+                                prog_delay_value <= mmio_wdata[5:0];
+                            end
+                        end
+
+                        16'h004C: begin
+                            ucode_addr <= mmio_wdata[7:0];
+                        end
+
+                        16'h0050: begin
+                            if (mgmt_phase) begin
+                                prog_ucode_we   <= 1'b1;
+                                prog_ucode_core <= sel_core;
+                                prog_ucode_addr <= ucode_addr;
+                                prog_ucode_data <= mmio_wdata;
+                            end
+                        end
+
+                        16'h0054: begin
+                            if (mgmt_phase)
+                                dvfs_stall <= mmio_wdata[7:0];
+                        end
+
+                        16'h0058: begin
+                            if (mgmt_phase) begin
+                                perf_reset_we   <= 1'b1;
+                                perf_reset_core <= sel_core;
+                            end
+                        end
+
+                        16'h005C: begin
+                            index_base <= mmio_wdata[POOL_ADDR_BITS-1:0];
+                        end
+
+                        16'h0060: begin
+                            if (mgmt_phase) begin
+                                prog_index_we     <= 1'b1;
+                                prog_index_core   <= sel_core;
+                                prog_index_neuron <= sel_neuron;
+                                prog_index_base   <= index_base;
+                                prog_index_count  <= mmio_wdata[COUNT_BITS-1:0];
+                            end
+                        end
+
+                        16'h0064: begin
+                            if (mgmt_phase) begin
+                                prog_noise_seed_we    <= 1'b1;
+                                prog_noise_seed_core  <= sel_core;
+                                prog_noise_seed_value <= mmio_wdata;
+                            end
+                        end
+
+                        16'h0068: begin
+                            if (mgmt_phase) begin
+                                prog_dend_parent_we     <= 1'b1;
+                                prog_dend_parent_core   <= sel_core;
+                                prog_dend_parent_neuron <= sel_neuron;
+                                prog_dend_parent_data   <= mmio_wdata[7:0];
+                            end
+                        end
+
+                        16'h006C: begin
+                            if (mgmt_phase) begin
+                                prog_global_route_we          <= 1'b1;
+                                prog_global_route_src_core    <= sel_core;
+                                prog_global_route_src_neuron  <= sel_neuron;
+                                prog_global_route_slot        <= mmio_wdata[GLOBAL_ROUTE_SLOT_BITS-1:0];
+                                prog_global_route_dest_core   <= route_dest_core;
+                                prog_global_route_dest_neuron <= route_dest_neuron;
+                                prog_global_route_weight      <= route_weight;
+                            end
+                        end
+
+
+                        16'h0090: begin
+                            debug_resume      <= mmio_wdata[0];
+                            debug_halt_req    <= mmio_wdata[1];
+                            debug_single_step <= mmio_wdata[2];
+                        end
+
+                        16'h0094: debug_bp_addr_0 <= mmio_wdata;
+                        16'h0098: debug_bp_addr_1 <= mmio_wdata;
+                        16'h009C: debug_bp_addr_2 <= mmio_wdata;
+                        16'h00A0: debug_bp_addr_3 <= mmio_wdata;
+                        16'h00A4: debug_bp_enable <= mmio_wdata[3:0];
+
+                        default: ;
+                    endcase
+                end else begin
+                    case (mmio_addr)
+                        16'h0000: mmio_rdata <= {30'd0, rv_running, rv_halted};
+                        16'h0004: mmio_rdata <= {{(32-CORE_ID_BITS){1'b0}}, sel_core};
+                        16'h0008: mmio_rdata <= {{(32-NEURON_BITS){1'b0}}, sel_neuron};
+                        16'h000C: begin
+                            probe_read     <= 1'b1;
+                            probe_core     <= sel_core;
+                            probe_neuron   <= sel_neuron;
+                            probe_state_id <= mmio_wdata[3:0];
+                            mmio_rdata     <= {{(32-DATA_WIDTH){probe_data[DATA_WIDTH-1]}}, probe_data};
+                        end
+                        16'h0024: mmio_rdata <= {24'd0, uart_rx_data};
+                        16'h0028: mmio_rdata <= {30'd0, uart_rx_valid, uart_tx_ready};
+                        16'h002C: mmio_rdata <= timestep_count;
+
+                        16'h0070: mmio_rdata <= perf_spike_count;
+                        16'h0074: mmio_rdata <= perf_synop_count;
+                        16'h0078: mmio_rdata <= perf_active_cycles;
+                        16'h007C: mmio_rdata <= perf_power_estimate;
+
+                        default:  mmio_rdata <= 32'd0;
+                    endcase
+                end
+            end
+        end
+    end
+
+endmodule

rtl/multi_chip_router.v

@@ -0,0 +1,346 @@
+// ============================================================================
+// Multi-Chip Router
+// ============================================================================
+//
+// Copyright 2026 Henry Arthur Shulayev Barnes / Catalyst Neuromorphic Ltd
+// Company No. 17054540 — UK Patent Application No. 2602902.6
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// ============================================================================
+
+`timescale 1ns/1ps
+
+module multi_chip_router #(
+    parameter NUM_LINKS    = 1,
+    parameter CHIP_ID_BITS = 14,
+    parameter CORE_ID_BITS = 7,
+    parameter NEURON_BITS  = 10,
+    parameter DATA_WIDTH   = 16,
+    parameter TX_DEPTH     = 256,
+    parameter RX_DEPTH     = 256
+)(
+    input  wire        clk,
+    input  wire        rst_n,
+
+    input  wire [CHIP_ID_BITS-1:0] my_chip_id,
+
+    input  wire                        tx_push,
+    input  wire [CHIP_ID_BITS-1:0]     tx_dest_chip,
+    input  wire [CORE_ID_BITS-1:0]     tx_core,
+    input  wire [NEURON_BITS-1:0]      tx_neuron,
+    input  wire [7:0]                  tx_payload,
+    output wire                        tx_full,
+
+    output wire [CHIP_ID_BITS-1:0]     rx_src_chip,
+    output wire [CORE_ID_BITS-1:0]     rx_core,
+    output wire [NEURON_BITS-1:0]      rx_neuron,
+    output wire signed [DATA_WIDTH-1:0] rx_current,
+    input  wire                        rx_pop,
+    output wire                        rx_empty,
+
+    input  wire                        barrier_tx_send,
+    output reg                         barrier_rx,
+
+    input  wire                        mgmt_tx_push,
+    input  wire [CORE_ID_BITS-1:0]     mgmt_tx_core,
+    input  wire [NEURON_BITS-1:0]      mgmt_tx_neuron,
+    input  wire [7:0]                  mgmt_tx_data,
+    input  wire                        mgmt_tx_is_write,
+    input  wire [CHIP_ID_BITS-1:0]     mgmt_tx_dest_chip,
+    output reg                         mgmt_rx_valid,
+    output reg  [CHIP_ID_BITS-1:0]     mgmt_rx_src_chip,
+    output reg  [CORE_ID_BITS-1:0]     mgmt_rx_core,
+    output reg  [NEURON_BITS-1:0]      mgmt_rx_neuron,
+    output reg  [7:0]                  mgmt_rx_data,
+    output reg                         mgmt_rx_is_write,
+
+    input  wire                        preempt_request,
+    output reg                         preempt_rx,
+
+    output wire [NUM_LINKS*8-1:0]      link_tx_data,
+    output wire [NUM_LINKS-1:0]        link_tx_valid,
+    input  wire [NUM_LINKS-1:0]        link_tx_ready,
+    input  wire [NUM_LINKS*8-1:0]      link_rx_data,
+    input  wire [NUM_LINKS-1:0]        link_rx_valid,
+    output wire [NUM_LINKS-1:0]        link_rx_ready
+);
+
+    localparam MSG_SPIKE   = 2'b00;
+    localparam MSG_BARRIER = 2'b01;
+    localparam MSG_MGMT    = 2'b10;
+    localparam MSG_PREEMPT = 2'b11;
+
+    localparam TX_FLAT_W    = 1 + 2 + 2*CHIP_ID_BITS + CORE_ID_BITS + NEURON_BITS + 8;
+    localparam TX_NUM_BYTES = (TX_FLAT_W + 7) / 8;
+    localparam TX_PAD_W     = TX_NUM_BYTES * 8;
+
+    localparam MSGTYPE_OFFSET = TX_PAD_W - 1 - 1;
+    localparam DEST_OFFSET = MSGTYPE_OFFSET - 2;
+    localparam SRC_OFFSET  = DEST_OFFSET - CHIP_ID_BITS;
+    localparam CORE_OFFSET = SRC_OFFSET - CHIP_ID_BITS;
+    localparam NRN_OFFSET  = CORE_OFFSET - CORE_ID_BITS;
+    localparam PAY_OFFSET  = NRN_OFFSET - NEURON_BITS;
+
+    localparam PKT_W = 2 + CHIP_ID_BITS + CORE_ID_BITS + NEURON_BITS + 8;
+
+    reg [PKT_W-1:0] tx_fifo [0:TX_DEPTH-1];
+    reg [8:0] tx_wr_ptr, tx_rd_ptr;
+    wire [8:0] tx_count = tx_wr_ptr - tx_rd_ptr;
+    wire        tx_fifo_empty = (tx_wr_ptr == tx_rd_ptr);
+    assign      tx_full = (tx_count >= TX_DEPTH);
+
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n)
+            tx_wr_ptr <= 0;
+        else if (tx_push && !tx_full) begin
+            tx_fifo[tx_wr_ptr[7:0]] <= {MSG_SPIKE, tx_dest_chip, tx_core, tx_neuron, tx_payload};
+            tx_wr_ptr <= tx_wr_ptr + 1;
+        end else if (mgmt_tx_push && !tx_full) begin
+            tx_fifo[tx_wr_ptr[7:0]] <= {MSG_MGMT, mgmt_tx_dest_chip, mgmt_tx_core, mgmt_tx_neuron,
+                                         mgmt_tx_is_write, mgmt_tx_data[6:0]};
+            tx_wr_ptr <= tx_wr_ptr + 1;
+        end
+    end
+
+    wire [PKT_W-1:0] tx_head = tx_fifo[tx_rd_ptr[7:0]];
+    wire [1:0] tx_head_msgtype = tx_head[PKT_W-1 -: 2];
+    wire [CHIP_ID_BITS-1:0] tx_head_chip = tx_head[PKT_W-3 -: CHIP_ID_BITS];
+
+    wire [CHIP_ID_BITS-1:0] tx_link_sel = tx_head_chip % NUM_LINKS;
+
+    reg [TX_PAD_W-1:0] txs_shift;
+    reg [$clog2(TX_NUM_BYTES+1)-1:0] txs_cnt;
+    reg txs_active;
+    reg [CHIP_ID_BITS-1:0] txs_link;
+
+    reg [NUM_LINKS*8-1:0] ltx_data;
+    reg [NUM_LINKS-1:0]   ltx_valid;
+    assign link_tx_data  = ltx_data;
+    assign link_tx_valid = ltx_valid;
+
+    wire [TX_PAD_W-1:0] tx_flat = {1'b1, tx_head_msgtype, tx_head_chip, my_chip_id,
+        tx_head[CORE_ID_BITS+NEURON_BITS+7 : 0],
+        {(TX_PAD_W - TX_FLAT_W){1'b0}}};
+
+    wire [TX_PAD_W-1:0] barrier_flat = {1'b1, MSG_BARRIER, {CHIP_ID_BITS{1'b1}}, my_chip_id,
+        {(CORE_ID_BITS+NEURON_BITS+8){1'b0}},
+        {(TX_PAD_W - TX_FLAT_W){1'b0}}};
+    wire [TX_PAD_W-1:0] preempt_flat = {1'b1, MSG_PREEMPT, {CHIP_ID_BITS{1'b1}}, my_chip_id,
+        {(CORE_ID_BITS+NEURON_BITS+8){1'b0}},
+        {(TX_PAD_W - TX_FLAT_W){1'b0}}};
+
+    reg                     bcast_active;
+    reg [TX_PAD_W-1:0]      bcast_shift;
+    reg [$clog2(TX_NUM_BYTES+1)-1:0] bcast_cnt;
+    reg [CHIP_ID_BITS-1:0]  bcast_link;
+    reg [CHIP_ID_BITS-1:0]  bcast_link_max;
+    reg [1:0]               bcast_msg_type;
+    reg                     bcast_pending;
+    reg [TX_PAD_W-1:0]      bcast_flat_save;
+
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n) begin
+            txs_active     <= 0;
+            txs_cnt        <= 0;
+            txs_shift      <= 0;
+            txs_link       <= 0;
+            tx_rd_ptr      <= 0;
+            ltx_data       <= 0;
+            ltx_valid      <= 0;
+            bcast_active   <= 0;
+            bcast_shift    <= 0;
+            bcast_cnt      <= 0;
+            bcast_link     <= 0;
+            bcast_link_max <= 0;
+            bcast_msg_type <= 0;
+            bcast_pending  <= 0;
+            bcast_flat_save <= 0;
+        end else begin
+            ltx_valid <= 0;
+
+            if (bcast_active) begin
+                ltx_data[bcast_link*8 +: 8] <= bcast_shift[TX_PAD_W-1 -: 8];
+                ltx_valid[bcast_link] <= 1;
+
+                if (link_tx_ready[bcast_link]) begin
+                    bcast_shift <= bcast_shift << 8;
+                    if (bcast_cnt == TX_NUM_BYTES - 1) begin
+                        if (bcast_link < NUM_LINKS - 1) begin
+                            bcast_link  <= bcast_link + 1;
+                            bcast_shift <= bcast_flat_save;
+                            bcast_cnt   <= 0;
+                        end else begin
+                            bcast_active <= 0;
+                        end
+                    end else begin
+                        bcast_cnt <= bcast_cnt + 1;
+                    end
+                end
+            end else if (!txs_active) begin
+                if (barrier_tx_send) begin
+                    bcast_active    <= 1;
+                    bcast_flat_save <= barrier_flat;
+                    bcast_shift     <= barrier_flat;
+                    bcast_cnt       <= 0;
+                    bcast_link      <= 0;
+                    bcast_msg_type  <= MSG_BARRIER;
+                end else if (preempt_request) begin
+                    bcast_active    <= 1;
+                    bcast_flat_save <= preempt_flat;
+                    bcast_shift     <= preempt_flat;
+                    bcast_cnt       <= 0;
+                    bcast_link      <= 0;
+                    bcast_msg_type  <= MSG_PREEMPT;
+                end else if (!tx_fifo_empty) begin
+                    ltx_data[tx_link_sel*8 +: 8] <= tx_flat[TX_PAD_W-1 -: 8];
+                    ltx_valid[tx_link_sel] <= 1;
+                    txs_shift  <= tx_flat << 8;
+                    txs_link   <= tx_link_sel;
+                    txs_cnt    <= 1;
+                    txs_active <= 1;
+                    tx_rd_ptr  <= tx_rd_ptr + 1;
+                end
+            end else begin
+                ltx_data[txs_link*8 +: 8] <= txs_shift[TX_PAD_W-1 -: 8];
+                ltx_valid[txs_link] <= 1;
+
+                if (link_tx_ready[txs_link]) begin
+                    txs_shift <= txs_shift << 8;
+                    if (txs_cnt == TX_NUM_BYTES - 1)
+                        txs_active <= 0;
+                    else
+                        txs_cnt <= txs_cnt + 1;
+                end
+            end
+        end
+    end
+
+    localparam RX_PKT_W = CHIP_ID_BITS + CORE_ID_BITS + NEURON_BITS + DATA_WIDTH;
+
+    reg [TX_PAD_W-1:0] rxs_accum [0:NUM_LINKS-1];
+    reg [$clog2(TX_NUM_BYTES+1)-1:0] rxs_cnt [0:NUM_LINKS-1];
+    reg [NUM_LINKS-1:0] rxs_push;
+
+    assign link_rx_ready = (rx_count < RX_DEPTH - 4) ? {NUM_LINKS{1'b1}} : {NUM_LINKS{1'b0}};
+
+    genvar li;
+    generate
+        for (li = 0; li < NUM_LINKS; li = li + 1) begin : gen_rx
+            always @(posedge clk or negedge rst_n) begin
+                if (!rst_n) begin
+                    rxs_cnt[li]  <= 0;
+                    rxs_push[li] <= 0;
+                    rxs_accum[li] <= 0;
+                end else begin
+                    rxs_push[li] <= 0;
+
+                    if (link_rx_valid[li]) begin
+                        rxs_accum[li] <= {rxs_accum[li][TX_PAD_W-9:0], link_rx_data[li*8 +: 8]};
+
+                        if (rxs_cnt[li] == 0) begin
+                            if (link_rx_data[li*8 + 7]) begin
+                                rxs_accum[li] <= {{(TX_PAD_W-8){1'b0}}, link_rx_data[li*8 +: 8]};
+                                rxs_cnt[li] <= 1;
+                            end
+                        end else begin
+                            if (rxs_cnt[li] == TX_NUM_BYTES - 1) begin
+                                rxs_push[li] <= 1;
+                                rxs_cnt[li]  <= 0;
+                            end else begin
+                                rxs_cnt[li] <= rxs_cnt[li] + 1;
+                            end
+                        end
+                    end
+                end
+            end
+        end
+    endgenerate
+
+
+    reg [RX_PKT_W-1:0] rx_fifo [0:RX_DEPTH-1];
+    reg [8:0] rx_wr_ptr, rx_rd_ptr;
+    wire [8:0] rx_count = rx_wr_ptr - rx_rd_ptr;
+    assign rx_empty = (rx_wr_ptr == rx_rd_ptr);
+
+    always @(posedge clk or negedge rst_n) begin : rx_fifo_wr
+        integer k;
+        reg [1:0] rx_msg_type;
+        if (!rst_n) begin
+            rx_wr_ptr    <= 0;
+            barrier_rx   <= 0;
+            preempt_rx   <= 0;
+            mgmt_rx_valid <= 0;
+            mgmt_rx_src_chip <= 0;
+            mgmt_rx_core     <= 0;
+            mgmt_rx_neuron   <= 0;
+            mgmt_rx_data     <= 0;
+            mgmt_rx_is_write <= 0;
+        end else begin
+            barrier_rx    <= 0;
+            preempt_rx    <= 0;
+            mgmt_rx_valid <= 0;
+
+            for (k = 0; k < NUM_LINKS; k = k + 1) begin
+                if (rxs_push[k]) begin
+                    rx_msg_type = rxs_accum[k][MSGTYPE_OFFSET -: 2];
+
+                    case (rx_msg_type)
+                        MSG_SPIKE: begin
+                            if (rx_count < RX_DEPTH) begin
+                                rx_fifo[rx_wr_ptr[7:0]] <= {
+                                    rxs_accum[k][SRC_OFFSET -: CHIP_ID_BITS],
+                                    rxs_accum[k][CORE_OFFSET -: CORE_ID_BITS],
+                                    rxs_accum[k][NRN_OFFSET -: NEURON_BITS],
+                                    {{(DATA_WIDTH-8){1'b0}},
+                                     rxs_accum[k][PAY_OFFSET -: 8]}
+                                };
+                                rx_wr_ptr <= rx_wr_ptr + 1;
+                            end
+                        end
+
+                        MSG_BARRIER: begin
+                            barrier_rx <= 1;
+                        end
+
+                        MSG_MGMT: begin
+                            mgmt_rx_valid    <= 1;
+                            mgmt_rx_src_chip <= rxs_accum[k][SRC_OFFSET -: CHIP_ID_BITS];
+                            mgmt_rx_core     <= rxs_accum[k][CORE_OFFSET -: CORE_ID_BITS];
+                            mgmt_rx_neuron   <= rxs_accum[k][NRN_OFFSET -: NEURON_BITS];
+                            mgmt_rx_is_write <= rxs_accum[k][PAY_OFFSET];
+                            mgmt_rx_data     <= {1'b0, rxs_accum[k][PAY_OFFSET-1 -: 7]};
+                        end
+
+                        MSG_PREEMPT: begin
+                            preempt_rx <= 1;
+                        end
+                    endcase
+                end
+            end
+        end
+    end
+
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n)
+            rx_rd_ptr <= 0;
+        else if (rx_pop && !rx_empty)
+            rx_rd_ptr <= rx_rd_ptr + 1;
+    end
+
+    wire [RX_PKT_W-1:0] rx_top = rx_fifo[rx_rd_ptr[7:0]];
+    assign rx_src_chip = rx_top[RX_PKT_W-1 -: CHIP_ID_BITS];
+    assign rx_core     = rx_top[NEURON_BITS+DATA_WIDTH +: CORE_ID_BITS];
+    assign rx_neuron   = rx_top[DATA_WIDTH +: NEURON_BITS];
+    assign rx_current  = rx_top[DATA_WIDTH-1:0];
+
+endmodule

rtl/neuromorphic_mesh.v

@@ -0,0 +1,859 @@
+// ============================================================================
+// Neuromorphic Mesh
+// ============================================================================
+//
+// Copyright 2026 Henry Arthur Shulayev Barnes / Catalyst Neuromorphic Ltd
+// Company No. 17054540 — UK Patent Application No. 2602902.6
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// ============================================================================
+
+module neuromorphic_mesh #(
+    parameter NUM_CORES      = 4,
+    parameter CORE_ID_BITS   = 2,
+    parameter NUM_NEURONS    = 1024,
+    parameter NEURON_BITS    = 10,
+    parameter DATA_WIDTH     = 16,
+    parameter POOL_DEPTH     = 32768,
+    parameter POOL_ADDR_BITS = 15,
+    parameter COUNT_BITS     = 12,
+    parameter REV_FANIN      = 32,
+    parameter REV_SLOT_BITS  = 5,
+    parameter THRESHOLD      = 16'sd1000,
+    parameter LEAK_RATE      = 16'sd3,
+    parameter REFRAC_CYCLES  = 3,
+    parameter GRADE_SHIFT    = 7,
+
+    parameter ROUTE_FANOUT     = 8,
+    parameter ROUTE_SLOT_BITS  = 3,
+
+    parameter ROUTE_ADDR_W   = CORE_ID_BITS + NEURON_BITS + ROUTE_SLOT_BITS,
+    parameter ROUTE_DATA_W   = 1 + CORE_ID_BITS + NEURON_BITS + DATA_WIDTH,
+
+    parameter CLUSTER_SIZE          = 4,
+    parameter GLOBAL_ROUTE_SLOTS    = 4,
+    parameter GLOBAL_ROUTE_SLOT_BITS = 2,
+    parameter GLOBAL_ROUTE_ADDR_W   = CORE_ID_BITS + NEURON_BITS + GLOBAL_ROUTE_SLOT_BITS,
+
+    parameter CHIP_LINK_EN = 0
+)(
+    input  wire                    clk,
+    input  wire                    rst_n,
+    input  wire                    start,
+
+    input  wire                         prog_pool_we,
+    input  wire [CORE_ID_BITS-1:0]      prog_pool_core,
+    input  wire [POOL_ADDR_BITS-1:0]    prog_pool_addr,
+    input  wire [NEURON_BITS-1:0]       prog_pool_src,
+    input  wire [NEURON_BITS-1:0]       prog_pool_target,
+    input  wire signed [DATA_WIDTH-1:0] prog_pool_weight,
+    input  wire [1:0]                   prog_pool_comp,
+
+    input  wire                         prog_index_we,
+    input  wire [CORE_ID_BITS-1:0]      prog_index_core,
+    input  wire [NEURON_BITS-1:0]       prog_index_neuron,
+    input  wire [POOL_ADDR_BITS-1:0]    prog_index_base,
+    input  wire [COUNT_BITS-1:0]        prog_index_count,
+    input  wire [1:0]                   prog_index_format,
+
+    input  wire                        prog_route_we,
+    input  wire [CORE_ID_BITS-1:0]     prog_route_src_core,
+    input  wire [NEURON_BITS-1:0]      prog_route_src_neuron,
+    input  wire [ROUTE_SLOT_BITS-1:0]  prog_route_slot,
+    input  wire [CORE_ID_BITS-1:0]     prog_route_dest_core,
+    input  wire [NEURON_BITS-1:0]      prog_route_dest_neuron,
+    input  wire signed [DATA_WIDTH-1:0] prog_route_weight,
+
+    input  wire                        prog_global_route_we,
+    input  wire [CORE_ID_BITS-1:0]     prog_global_route_src_core,
+    input  wire [NEURON_BITS-1:0]      prog_global_route_src_neuron,
+    input  wire [GLOBAL_ROUTE_SLOT_BITS-1:0] prog_global_route_slot,
+    input  wire [CORE_ID_BITS-1:0]     prog_global_route_dest_core,
+    input  wire [NEURON_BITS-1:0]      prog_global_route_dest_neuron,
+    input  wire signed [DATA_WIDTH-1:0] prog_global_route_weight,
+
+    input  wire                        learn_enable,
+
+    input  wire                        graded_enable,
+
+    input  wire                        dendritic_enable,
+
+    input  wire                        async_enable,
+
+    input  wire                        threefactor_enable,
+    input  wire signed [DATA_WIDTH-1:0] reward_value,
+
+    input  wire                        noise_enable,
+
+    input  wire                        skip_idle_enable,
+
+    input  wire                        scale_u_enable,
+
+    input  wire                        prog_delay_we,
+    input  wire [CORE_ID_BITS-1:0]     prog_delay_core,
+    input  wire [POOL_ADDR_BITS-1:0]   prog_delay_addr,
+    input  wire [5:0]                  prog_delay_value,
+
+    input  wire                        prog_ucode_we,
+    input  wire [CORE_ID_BITS-1:0]     prog_ucode_core,
+    input  wire [7:0]                  prog_ucode_addr,
+    input  wire [31:0]                 prog_ucode_data,
+
+    input  wire                        prog_param_we,
+    input  wire [CORE_ID_BITS-1:0]     prog_param_core,
+    input  wire [NEURON_BITS-1:0]      prog_param_neuron,
+    input  wire [4:0]                  prog_param_id,
+    input  wire signed [DATA_WIDTH-1:0] prog_param_value,
+
+    input  wire                        ext_valid,
+    input  wire [CORE_ID_BITS-1:0]     ext_core,
+    input  wire [NEURON_BITS-1:0]      ext_neuron_id,
+    input  wire signed [DATA_WIDTH-1:0] ext_current,
+
+    input  wire                        probe_read,
+    input  wire [CORE_ID_BITS-1:0]     probe_core,
+    input  wire [NEURON_BITS-1:0]      probe_neuron,
+    input  wire [4:0]                  probe_state_id,
+    input  wire [POOL_ADDR_BITS-1:0]   probe_pool_addr,
+    output reg  signed [DATA_WIDTH-1:0] probe_data,
+    output reg                          probe_valid,
+
+    output reg                         timestep_done,
+    output wire [NUM_CORES-1:0]        spike_valid_bus,
+    output wire [NUM_CORES*NEURON_BITS-1:0] spike_id_bus,
+    output wire [5:0]                  mesh_state_out,
+    output reg  [31:0]                 total_spikes,
+    output reg  [31:0]                 timestep_count,
+
+    output wire [NUM_CORES-1:0]        core_idle_bus,
+
+    input  wire [7:0]                  dvfs_stall,
+
+    output wire [NUM_CORES-1:0]        core_clock_en,
+    output reg  [31:0]                 energy_counter,
+    output wire                        power_idle_hint,
+
+    output reg                         link_tx_push,
+    output reg  [CORE_ID_BITS-1:0]     link_tx_core,
+    output reg  [NEURON_BITS-1:0]      link_tx_neuron,
+    output reg  [7:0]                  link_tx_payload,
+    input  wire                        link_tx_full,
+    input  wire [CORE_ID_BITS-1:0]     link_rx_core,
+    input  wire [NEURON_BITS-1:0]      link_rx_neuron,
+    input  wire signed [DATA_WIDTH-1:0] link_rx_current,
+    output reg                         link_rx_pop,
+    input  wire                        link_rx_empty
+);
+
+    localparam SM_IDLE       = 6'd0;
+    localparam SM_INJECT     = 6'd1;
+    localparam SM_START      = 6'd2;
+    localparam SM_RUN_WAIT   = 6'd3;
+    localparam SM_ROUTE_POP  = 6'd4;
+    localparam SM_ROUTE_ADDR = 6'd5;
+    localparam SM_ROUTE_WAIT = 6'd6;
+    localparam SM_ROUTE_READ = 6'd7;
+    localparam SM_DONE       = 6'd8;
+
+    localparam SM_ASYNC_ACTIVE     = 6'd9;
+    localparam SM_ASYNC_INJECT     = 6'd10;
+    localparam SM_ASYNC_ROUTE_POP  = 6'd11;
+    localparam SM_ASYNC_ROUTE_ADDR = 6'd12;
+    localparam SM_ASYNC_ROUTE_WAIT = 6'd13;
+    localparam SM_ASYNC_ROUTE_READ = 6'd14;
+    localparam SM_ASYNC_DONE       = 6'd15;
+
+    localparam SM_GLOBAL_ROUTE_ADDR = 6'd16;
+    localparam SM_GLOBAL_ROUTE_WAIT = 6'd17;
+    localparam SM_GLOBAL_ROUTE_READ = 6'd18;
+
+    localparam SM_LINK_RX_DRAIN = 6'd19;
+    localparam SM_LINK_RX_WAIT  = 6'd20;
+
+    localparam SM_DVFS_WAIT     = 6'd21;
+
+    reg [5:0] mesh_state;
+    assign mesh_state_out = mesh_state;
+    reg [7:0] dvfs_wait_cnt;
+
+    reg                      rt_we;
+    reg  [ROUTE_ADDR_W-1:0]  rt_addr;
+    reg  [ROUTE_DATA_W-1:0]  rt_wdata;
+    wire [ROUTE_DATA_W-1:0]  rt_rdata;
+
+    wire                     rt_we_mux   = (mesh_state == SM_IDLE) ? prog_route_we : rt_we;
+    wire [ROUTE_ADDR_W-1:0]  rt_addr_mux = (mesh_state == SM_IDLE) ?
+        {prog_route_src_core, prog_route_src_neuron, prog_route_slot} : rt_addr;
+    wire [ROUTE_DATA_W-1:0]  rt_wdata_mux = (mesh_state == SM_IDLE) ?
+        {1'b1, prog_route_dest_core, prog_route_dest_neuron, prog_route_weight} : rt_wdata;
+
+    sram #(.DATA_WIDTH(ROUTE_DATA_W), .ADDR_WIDTH(ROUTE_ADDR_W)) route_table (
+        .clk(clk),
+        .we_a(rt_we_mux), .addr_a(rt_addr_mux),
+        .wdata_a(rt_wdata_mux), .rdata_a(rt_rdata),
+        .addr_b({ROUTE_ADDR_W{1'b0}}), .rdata_b()
+    );
+
+    wire                       rt_valid      = rt_rdata[ROUTE_DATA_W-1];
+    localparam RT_DEST_CORE_LO = NEURON_BITS + DATA_WIDTH;
+    localparam RT_DEST_CORE_HI = NEURON_BITS + DATA_WIDTH + CORE_ID_BITS - 1;
+    wire [CORE_ID_BITS-1:0]    rt_dest_core  = rt_rdata[RT_DEST_CORE_HI:RT_DEST_CORE_LO];
+    localparam RT_DEST_NRN_LO = DATA_WIDTH;
+    localparam RT_DEST_NRN_HI = DATA_WIDTH + NEURON_BITS - 1;
+    wire [NEURON_BITS-1:0]     rt_dest_nrn   = rt_rdata[RT_DEST_NRN_HI:RT_DEST_NRN_LO];
+    wire signed [DATA_WIDTH-1:0] rt_weight   = rt_rdata[DATA_WIDTH-1:0];
+
+    reg                               grt_we;
+    reg  [GLOBAL_ROUTE_ADDR_W-1:0]   grt_addr;
+    wire [ROUTE_DATA_W-1:0]          grt_rdata;
+
+    wire                              grt_we_mux   = (mesh_state == SM_IDLE) ? prog_global_route_we : grt_we;
+    wire [GLOBAL_ROUTE_ADDR_W-1:0]   grt_addr_mux = (mesh_state == SM_IDLE) ?
+        {prog_global_route_src_core, prog_global_route_src_neuron, prog_global_route_slot} : grt_addr;
+    wire [ROUTE_DATA_W-1:0]          grt_wdata_mux = (mesh_state == SM_IDLE) ?
+        {1'b1, prog_global_route_dest_core, prog_global_route_dest_neuron, prog_global_route_weight} : {ROUTE_DATA_W{1'b0}};
+
+    sram #(.DATA_WIDTH(ROUTE_DATA_W), .ADDR_WIDTH(GLOBAL_ROUTE_ADDR_W)) global_route_table (
+        .clk(clk),
+        .we_a(grt_we_mux), .addr_a(grt_addr_mux),
+        .wdata_a(grt_wdata_mux), .rdata_a(grt_rdata),
+        .addr_b({GLOBAL_ROUTE_ADDR_W{1'b0}}), .rdata_b()
+    );
+
+    wire                       grt_valid      = grt_rdata[ROUTE_DATA_W-1];
+    localparam GRT_DEST_CORE_LO = NEURON_BITS + DATA_WIDTH;
+    localparam GRT_DEST_CORE_HI = NEURON_BITS + DATA_WIDTH + CORE_ID_BITS - 1;
+    wire [CORE_ID_BITS-1:0]    grt_dest_core  = grt_rdata[GRT_DEST_CORE_HI:GRT_DEST_CORE_LO];
+    localparam GRT_DEST_NRN_LO = DATA_WIDTH;
+    localparam GRT_DEST_NRN_HI = DATA_WIDTH + NEURON_BITS - 1;
+    wire [NEURON_BITS-1:0]     grt_dest_nrn   = grt_rdata[GRT_DEST_NRN_HI:GRT_DEST_NRN_LO];
+    wire signed [DATA_WIDTH-1:0] grt_weight   = grt_rdata[DATA_WIDTH-1:0];
+
+    wire signed [31:0] grt_weight_ext      = grt_weight;
+    wire signed [31:0] grt_graded_product  = grt_weight_ext * route_payload_ext;
+    wire signed [DATA_WIDTH-1:0] grt_graded_current = grt_graded_product >>> GRADE_SHIFT;
+
+    localparam INJECT_WIDTH = CORE_ID_BITS + NEURON_BITS + DATA_WIDTH;
+
+    reg                        inj_push, inj_pop, inj_clear;
+    reg  [INJECT_WIDTH-1:0]    inj_push_data;
+    wire [INJECT_WIDTH-1:0]    inj_pop_data;
+    wire                       inj_empty, inj_full;
+
+    spike_fifo #(.ID_WIDTH(INJECT_WIDTH), .DEPTH(512), .PTR_BITS(9)) inject_fifo (
+        .clk(clk), .rst_n(rst_n), .clear(inj_clear),
+        .push(inj_push), .push_data(inj_push_data),
+        .pop(inj_pop), .pop_data(inj_pop_data),
+        .empty(inj_empty), .full(inj_full), .count()
+    );
+
+    localparam INJ_DEST_CORE_HI = INJECT_WIDTH - 1;
+    localparam INJ_DEST_CORE_LO = INJECT_WIDTH - CORE_ID_BITS;
+    wire [CORE_ID_BITS-1:0]      inj_dest_core = inj_pop_data[INJ_DEST_CORE_HI:INJ_DEST_CORE_LO];
+    localparam INJ_DEST_NRN_LO = DATA_WIDTH;
+    localparam INJ_DEST_NRN_HI = DATA_WIDTH + NEURON_BITS - 1;
+    wire [NEURON_BITS-1:0]       inj_dest_nrn  = inj_pop_data[INJ_DEST_NRN_HI:INJ_DEST_NRN_LO];
+    wire signed [DATA_WIDTH-1:0] inj_weight    = inj_pop_data[DATA_WIDTH-1:0];
+
+    wire [NUM_CORES-1:0]                    core_done;
+    wire [NUM_CORES-1:0]                    core_spike_valid;
+    wire [NUM_CORES*NEURON_BITS-1:0]        core_spike_id;
+    wire [NUM_CORES*8-1:0]                  core_spike_payload;
+
+    reg  [NUM_CORES-1:0]                    core_start_r;
+
+    reg  [NUM_CORES-1:0] core_done_latch;
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n)
+            core_done_latch <= 0;
+        else if (mesh_state == SM_START)
+            core_done_latch <= 0;
+        else
+            core_done_latch <= core_done_latch | core_done;
+    end
+
+    reg [NUM_CORES-1:0] core_running;
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n)
+            core_running <= 0;
+        else
+            core_running <= (core_running | core_start_r) & ~core_done;
+    end
+
+    reg [NUM_CORES-1:0] core_produced_spike;
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n)
+            core_produced_spike <= 0;
+        else
+            core_produced_spike <= (core_produced_spike & ~core_start_r)
+                                   | (core_spike_valid & core_running);
+    end
+
+    reg [NUM_CORES-1:0] core_needs_restart;
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n)
+            core_needs_restart <= 0;
+        else if (mesh_state == SM_ASYNC_DONE)
+            core_needs_restart <= 0;
+        else
+            core_needs_restart <= (core_needs_restart
+                                   | (core_done & (core_produced_spike | core_spike_valid)))
+                                  & ~core_start_r;
+    end
+
+    assign spike_valid_bus = core_spike_valid;
+    assign spike_id_bus    = core_spike_id;
+
+    localparam PCF_WIDTH = NEURON_BITS + DATA_WIDTH;
+
+    reg  [NUM_CORES-1:0]           pcif_push;
+    reg  [NUM_CORES-1:0]           pcif_pop;
+    reg  [NUM_CORES-1:0]           pcif_clear;
+    reg  [PCF_WIDTH-1:0]           pcif_push_data;
+    wire [NUM_CORES-1:0]           pcif_empty;
+    wire [NUM_CORES-1:0]           pcif_full;
+    wire [NUM_CORES*PCF_WIDTH-1:0] pcif_data;
+
+    reg [CORE_ID_BITS-1:0] inject_core_idx;
+
+    reg [PCF_WIDTH-1:0] active_pcif_entry;
+    always @(*) begin
+        active_pcif_entry = pcif_data >> (inject_core_idx * PCF_WIDTH);
+    end
+    localparam PCIF_NID_LO = DATA_WIDTH;
+    localparam PCIF_NID_HI = DATA_WIDTH + NEURON_BITS - 1;
+    wire [NEURON_BITS-1:0]         pcif_nid = active_pcif_entry[PCIF_NID_HI:PCIF_NID_LO];
+    wire signed [DATA_WIDTH-1:0]   pcif_cur = active_pcif_entry[DATA_WIDTH-1:0];
+
+    wire [NEURON_BITS-1:0] mesh_ext_nid =
+        (mesh_state == SM_INJECT)       ? inj_dest_nrn :
+        (mesh_state == SM_ASYNC_INJECT) ? pcif_nid :
+                                          ext_neuron_id;
+
+    wire signed [DATA_WIDTH-1:0] mesh_ext_cur =
+        (mesh_state == SM_INJECT)       ? inj_weight :
+        (mesh_state == SM_ASYNC_INJECT) ? pcif_cur :
+                                          ext_current;
+
+    localparam CAP_WIDTH = NEURON_BITS + 8;
+
+    reg  [NUM_CORES-1:0] cap_pop;
+    reg  [NUM_CORES-1:0] cap_clear;
+    wire [NUM_CORES-1:0] cap_empty;
+    wire [NUM_CORES*CAP_WIDTH-1:0] cap_data;
+
+    wire [NUM_CORES-1:0] core_probe_valid;
+    wire [NUM_CORES*DATA_WIDTH-1:0] core_probe_data;
+
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n) begin
+            probe_data  <= {DATA_WIDTH{1'b0}};
+            probe_valid <= 1'b0;
+        end else begin
+            probe_data  <= core_probe_data >> (probe_core * DATA_WIDTH);
+            probe_valid <= core_probe_valid[probe_core];
+        end
+    end
+
+    genvar gi;
+    generate
+        for (gi = 0; gi < NUM_CORES; gi = gi + 1) begin : gen_core
+
+            localparam [CORE_ID_BITS-1:0] GI_CORE_ID = gi;
+
+            wire this_ext_valid =
+                (mesh_state == SM_IDLE && ext_valid && ext_core == GI_CORE_ID && !async_enable) ||
+                (mesh_state == SM_INJECT && !inj_empty && inj_dest_core == GI_CORE_ID) ||
+                (mesh_state == SM_ASYNC_INJECT && inject_core_idx == GI_CORE_ID && !pcif_empty[gi]);
+
+            wire this_pool_we = prog_pool_we && (prog_pool_core == GI_CORE_ID) &&
+                                (mesh_state == SM_IDLE);
+
+            wire this_index_we = prog_index_we && (prog_index_core == GI_CORE_ID) &&
+                                 (mesh_state == SM_IDLE);
+
+            wire this_param_we = prog_param_we && (prog_param_core == GI_CORE_ID) &&
+                                 (mesh_state == SM_IDLE);
+
+            wire this_delay_we = prog_delay_we && (prog_delay_core == GI_CORE_ID) &&
+                                 (mesh_state == SM_IDLE);
+
+            wire this_ucode_we = prog_ucode_we && (prog_ucode_core == GI_CORE_ID) &&
+                                 (mesh_state == SM_IDLE);
+
+            scalable_core_v2 #(
+                .NUM_NEURONS   (NUM_NEURONS),
+                .NEURON_BITS   (NEURON_BITS),
+                .DATA_WIDTH    (DATA_WIDTH),
+                .POOL_DEPTH    (POOL_DEPTH),
+                .POOL_ADDR_BITS(POOL_ADDR_BITS),
+                .COUNT_BITS    (COUNT_BITS),
+                .REV_FANIN     (REV_FANIN),
+                .REV_SLOT_BITS (REV_SLOT_BITS),
+                .THRESHOLD     (THRESHOLD),
+                .LEAK_RATE     (LEAK_RATE),
+                .REFRAC_CYCLES (REFRAC_CYCLES),
+                .TRACE_MAX     (8'd100),
+                .TRACE_DECAY   (8'd3),
+                .LEARN_SHIFT   (3),
+                .GRADE_SHIFT   (GRADE_SHIFT)
+            ) core (
+                .clk            (clk),
+                .rst_n          (rst_n),
+                .start          (core_start_r[gi]),
+                .learn_enable   (learn_enable),
+                .graded_enable  (graded_enable),
+                .dendritic_enable(dendritic_enable),
+                .threefactor_enable(threefactor_enable),
+                .noise_enable   (noise_enable),
+                .skip_idle_enable(skip_idle_enable),
+                .scale_u_enable (scale_u_enable),
+                .reward_value   (reward_value),
+                .ext_valid      (this_ext_valid),
+                .ext_neuron_id  (mesh_ext_nid),
+                .ext_current    (mesh_ext_cur),
+                .pool_we        (this_pool_we),
+                .pool_addr_in   (prog_pool_addr),
+                .pool_src_in    (prog_pool_src),
+                .pool_target_in (prog_pool_target),
+                .pool_weight_in (prog_pool_weight),
+                .pool_comp_in   (prog_pool_comp),
+                .index_we       (this_index_we),
+                .index_neuron_in(prog_index_neuron),
+                .index_base_in  (prog_index_base),
+                .index_count_in (prog_index_count),
+                .index_format_in(prog_index_format),
+                .delay_we        (this_delay_we),
+                .delay_addr_in   (prog_delay_addr),
+                .delay_value_in  (prog_delay_value),
+                .ucode_prog_we   (this_ucode_we),
+                .ucode_prog_addr (prog_ucode_addr),
+                .ucode_prog_data (prog_ucode_data),
+                .prog_param_we    (this_param_we),
+                .prog_param_neuron(prog_param_neuron),
+                .prog_param_id    (prog_param_id),
+                .prog_param_value (prog_param_value),
+
+                .probe_read     (probe_read && (probe_core == GI_CORE_ID)),
+                .probe_neuron   (probe_neuron),
+                .probe_state_id (probe_state_id),
+                .probe_pool_addr(probe_pool_addr),
+                .probe_data     (core_probe_data[gi*DATA_WIDTH +: DATA_WIDTH]),
+                .probe_valid    (core_probe_valid[gi]),
+                .timestep_done  (core_done[gi]),
+                .spike_out_valid(core_spike_valid[gi]),
+                .spike_out_id   (core_spike_id[gi*NEURON_BITS +: NEURON_BITS]),
+                .spike_out_payload(core_spike_payload[gi*8 +: 8]),
+                .state_out      (),
+                .total_spikes   (),
+                .timestep_count (),
+                .core_idle      (core_idle_bus[gi])
+            );
+
+            spike_fifo #(.ID_WIDTH(CAP_WIDTH), .DEPTH(64), .PTR_BITS(6)) capture_fifo (
+                .clk(clk), .rst_n(rst_n),
+                .clear(cap_clear[gi]),
+                .push(core_spike_valid[gi] && (mesh_state == SM_RUN_WAIT || core_running[gi])),
+                .push_data({core_spike_id[gi*NEURON_BITS +: NEURON_BITS],
+                            core_spike_payload[gi*8 +: 8]}),
+                .pop(cap_pop[gi]),
+                .pop_data(cap_data[gi*CAP_WIDTH +: CAP_WIDTH]),
+                .empty(cap_empty[gi]),
+                .full(), .count()
+            );
+
+            spike_fifo #(.ID_WIDTH(PCF_WIDTH), .DEPTH(8), .PTR_BITS(3)) pcif (
+                .clk(clk), .rst_n(rst_n),
+                .clear(pcif_clear[gi]),
+                .push(pcif_push[gi]),
+                .push_data(pcif_push_data),
+                .pop(pcif_pop[gi]),
+                .pop_data(pcif_data[gi*PCF_WIDTH +: PCF_WIDTH]),
+                .empty(pcif_empty[gi]),
+                .full(pcif_full[gi]),
+                .count()
+            );
+        end
+    endgenerate
+
+    wire mesh_active = (mesh_state != SM_IDLE && mesh_state != SM_DVFS_WAIT);
+    assign core_clock_en = mesh_active ? {NUM_CORES{1'b1}} : ~core_idle_bus;
+    assign power_idle_hint = (mesh_state == SM_IDLE) && (&core_idle_bus);
+
+    reg [7:0] e_spike_coeff;
+    reg [7:0] e_synop_coeff;
+    reg [7:0] e_cycle_coeff;
+    wire [31:0] total_spike_count_this_ts = popcount(core_spike_valid_sync);
+    reg [NUM_CORES-1:0] core_spike_valid_sync;
+    always @(posedge clk) core_spike_valid_sync <= {NUM_CORES{1'b0}};
+
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n) begin
+            energy_counter  <= 32'd0;
+            e_spike_coeff   <= 8'd10;
+            e_synop_coeff   <= 8'd1;
+            e_cycle_coeff   <= 8'd1;
+        end else begin
+            if (mesh_active)
+                energy_counter <= energy_counter + {24'd0, e_cycle_coeff};
+            if (mesh_state == SM_DONE)
+                energy_counter <= energy_counter + total_spikes * {24'd0, e_spike_coeff};
+        end
+    end
+
+    function [31:0] popcount;
+        input [NUM_CORES-1:0] bits;
+        integer k;
+    begin
+        popcount = 0;
+        for (k = 0; k < NUM_CORES; k = k + 1)
+            popcount = popcount + bits[k];
+    end
+    endfunction
+
+    reg                      first_inject_found;
+    reg  [CORE_ID_BITS-1:0]  first_inject_core;
+    integer pe_i;
+    always @(*) begin
+        first_inject_found = 0;
+        first_inject_core  = 0;
+        for (pe_i = 0; pe_i < NUM_CORES; pe_i = pe_i + 1) begin
+            if (!first_inject_found && !core_running[pe_i] && !pcif_empty[pe_i]) begin
+                first_inject_found = 1;
+                first_inject_core  = pe_i[CORE_ID_BITS-1:0];
+            end
+        end
+    end
+
+    reg                      first_route_found;
+    reg  [CORE_ID_BITS-1:0]  first_route_core;
+    integer pe_j;
+    always @(*) begin
+        first_route_found = 0;
+        first_route_core  = 0;
+        for (pe_j = 0; pe_j < NUM_CORES; pe_j = pe_j + 1) begin
+            if (!first_route_found && !cap_empty[pe_j]) begin
+                first_route_found = 1;
+                first_route_core  = pe_j[CORE_ID_BITS-1:0];
+            end
+        end
+    end
+
+    reg                      first_restart_found;
+    reg  [CORE_ID_BITS-1:0]  first_restart_core;
+    integer pe_k;
+    always @(*) begin
+        first_restart_found = 0;
+        first_restart_core  = 0;
+        for (pe_k = 0; pe_k < NUM_CORES; pe_k = pe_k + 1) begin
+            if (!first_restart_found && core_needs_restart[pe_k] && !core_running[pe_k]) begin
+                first_restart_found = 1;
+                first_restart_core  = pe_k[CORE_ID_BITS-1:0];
+            end
+        end
+    end
+
+    wire quiescent = (core_running == 0) && (core_start_r == 0) &&
+                     (core_needs_restart == 0) && (&pcif_empty) && (&cap_empty);
+
+    reg [CORE_ID_BITS-1:0]  route_core_idx;
+    reg [NEURON_BITS-1:0]   route_neuron;
+    reg [7:0]               route_payload;
+    reg [ROUTE_SLOT_BITS-1:0] route_slot;
+    reg [GLOBAL_ROUTE_SLOT_BITS-1:0] global_slot;
+
+    wire signed [31:0] route_weight_ext    = rt_weight;
+    wire signed [31:0] route_payload_ext   = {24'd0, route_payload};
+    wire signed [31:0] route_graded_product = route_weight_ext * route_payload_ext;
+    wire signed [DATA_WIDTH-1:0] route_graded_current = route_graded_product >>> GRADE_SHIFT;
+
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n) begin
+            mesh_state     <= SM_IDLE;
+            timestep_done  <= 0;
+            total_spikes   <= 0;
+            timestep_count <= 0;
+            core_start_r   <= 0;
+            route_core_idx <= 0;
+            route_neuron   <= 0;
+            route_payload  <= 0;
+            route_slot     <= 0;
+            global_slot    <= 0;
+            rt_we          <= 0;
+            rt_addr        <= 0;
+            rt_wdata       <= 0;
+            grt_we         <= 0;
+            grt_addr       <= 0;
+            inj_push       <= 0;
+            inj_pop        <= 0;
+            inj_clear      <= 0;
+            cap_pop        <= 0;
+            cap_clear      <= 0;
+            pcif_push      <= 0;
+            pcif_pop       <= 0;
+            pcif_clear     <= 0;
+            pcif_push_data <= 0;
+            inject_core_idx <= 0;
+            link_tx_push    <= 0;
+            link_tx_core    <= 0;
+            link_tx_neuron  <= 0;
+            link_tx_payload <= 0;
+            link_rx_pop     <= 0;
+            dvfs_wait_cnt   <= 0;
+        end else begin
+            timestep_done <= 0;
+            core_start_r  <= 0;
+            rt_we         <= 0;
+            grt_we        <= 0;
+            inj_push      <= 0;
+            inj_pop       <= 0;
+            inj_clear     <= 0;
+            cap_pop       <= 0;
+            cap_clear     <= 0;
+            pcif_push     <= 0;
+            pcif_pop      <= 0;
+            pcif_clear    <= 0;
+            link_tx_push  <= 0;
+            link_rx_pop   <= 0;
+
+            total_spikes <= total_spikes + popcount(core_spike_valid);
+
+            case (mesh_state)
+                SM_IDLE: begin
+                    if (async_enable && ext_valid) begin
+                        pcif_push[ext_core] <= 1;
+                        pcif_push_data <= {ext_neuron_id, ext_current};
+                    end
+                    if (start) begin
+                        if (async_enable)
+                            mesh_state <= SM_ASYNC_ACTIVE;
+                        else if (CHIP_LINK_EN)
+                            mesh_state <= SM_LINK_RX_DRAIN;
+                        else
+                            mesh_state <= SM_INJECT;
+                    end
+                end
+
+                SM_INJECT: begin
+                    if (inj_empty) begin
+                        mesh_state <= SM_START;
+                    end else begin
+                        inj_pop <= 1;
+                    end
+                end
+
+                SM_START: begin
+                    core_start_r <= {NUM_CORES{1'b1}};
+                    mesh_state   <= SM_RUN_WAIT;
+                end
+
+                SM_RUN_WAIT: begin
+                    if (core_done_latch == {NUM_CORES{1'b1}}) begin
+                        route_core_idx <= 0;
+                        mesh_state     <= SM_ROUTE_POP;
+                    end
+                end
+
+                SM_ROUTE_POP: begin
+                    if (cap_empty[route_core_idx]) begin
+                        if (route_core_idx == NUM_CORES - 1) begin
+                            mesh_state <= SM_DONE;
+                        end else begin
+                            route_core_idx <= route_core_idx + 1;
+                        end
+                    end else begin
+                        cap_pop[route_core_idx] <= 1;
+                        route_neuron  <= (cap_data >> (route_core_idx * CAP_WIDTH + 8));
+                        route_payload <= (cap_data >> (route_core_idx * CAP_WIDTH));
+                        route_slot    <= 0;
+                        mesh_state    <= SM_ROUTE_ADDR;
+                    end
+                end
+
+                SM_ROUTE_ADDR: begin
+                    rt_addr    <= {route_core_idx, route_neuron, route_slot};
+                    mesh_state <= SM_ROUTE_WAIT;
+                end
+
+                SM_ROUTE_WAIT: begin
+                    mesh_state <= SM_ROUTE_READ;
+                end
+
+                SM_ROUTE_READ: begin
+                    if (rt_valid) begin
+                        inj_push <= 1;
+                        if (graded_enable)
+                            inj_push_data <= {rt_dest_core, rt_dest_nrn, route_graded_current};
+                        else
+                            inj_push_data <= {rt_dest_core, rt_dest_nrn, rt_weight};
+                    end
+
+                    if (route_slot < ROUTE_FANOUT - 1) begin
+                        route_slot <= route_slot + 1;
+                        mesh_state <= SM_ROUTE_ADDR;
+                    end else begin
+
+                        global_slot <= 0;
+                        mesh_state  <= SM_GLOBAL_ROUTE_ADDR;
+                    end
+                end
+
+                SM_GLOBAL_ROUTE_ADDR: begin
+                    grt_addr   <= {route_core_idx, route_neuron, global_slot};
+                    mesh_state <= SM_GLOBAL_ROUTE_WAIT;
+                end
+
+                SM_GLOBAL_ROUTE_WAIT: begin
+                    mesh_state <= SM_GLOBAL_ROUTE_READ;
+                end
+
+                SM_GLOBAL_ROUTE_READ: begin
+                    if (grt_valid) begin
+                        if (CHIP_LINK_EN && grt_weight[DATA_WIDTH-1]) begin
+
+                            if (!link_tx_full) begin
+                                link_tx_push    <= 1;
+                                link_tx_core    <= grt_dest_core;
+                                link_tx_neuron  <= grt_dest_nrn;
+                                link_tx_payload <= route_payload;
+                            end
+                        end else begin
+
+                            inj_push <= 1;
+                            if (graded_enable)
+                                inj_push_data <= {grt_dest_core, grt_dest_nrn, grt_graded_current};
+                            else
+                                inj_push_data <= {grt_dest_core, grt_dest_nrn, grt_weight};
+                        end
+                    end
+
+                    if (global_slot < GLOBAL_ROUTE_SLOTS - 1) begin
+                        global_slot <= global_slot + 1;
+                        mesh_state  <= SM_GLOBAL_ROUTE_ADDR;
+                    end else begin
+                        mesh_state <= SM_ROUTE_POP;
+                    end
+                end
+
+                SM_LINK_RX_DRAIN: begin
+                    if (link_rx_empty) begin
+                        mesh_state <= SM_INJECT;
+                    end else if (!inj_full) begin
+                        link_rx_pop <= 1;
+                        inj_push <= 1;
+                        inj_push_data <= {link_rx_core, link_rx_neuron, link_rx_current};
+                        mesh_state <= SM_LINK_RX_WAIT;
+                    end
+                end
+
+                SM_LINK_RX_WAIT: begin
+
+                    mesh_state <= SM_LINK_RX_DRAIN;
+                end
+
+                SM_DONE: begin
+                    cap_clear      <= {NUM_CORES{1'b1}};
+                    timestep_count <= timestep_count + 1;
+                    if (dvfs_stall > 0) begin
+                        dvfs_wait_cnt <= dvfs_stall;
+                        mesh_state    <= SM_DVFS_WAIT;
+                    end else begin
+                        timestep_done <= 1;
+                        mesh_state    <= SM_IDLE;
+                    end
+                end
+
+                SM_DVFS_WAIT: begin
+                    if (dvfs_wait_cnt <= 1) begin
+                        timestep_done <= 1;
+                        mesh_state    <= SM_IDLE;
+                    end else begin
+                        dvfs_wait_cnt <= dvfs_wait_cnt - 1;
+                    end
+                end
+
+                SM_ASYNC_ACTIVE: begin
+                    if (quiescent) begin
+                        mesh_state <= SM_ASYNC_DONE;
+                    end else if (first_inject_found) begin
+                        inject_core_idx <= first_inject_core;
+                        mesh_state <= SM_ASYNC_INJECT;
+                    end else if (first_route_found) begin
+                        route_core_idx <= first_route_core;
+                        mesh_state <= SM_ASYNC_ROUTE_POP;
+                    end else if (first_restart_found) begin
+                        core_start_r <= ({{(NUM_CORES-1){1'b0}}, 1'b1} << first_restart_core);
+                    end
+                end
+
+                SM_ASYNC_INJECT: begin
+                    if (pcif_empty[inject_core_idx]) begin
+                        core_start_r <= ({{(NUM_CORES-1){1'b0}}, 1'b1} << inject_core_idx);
+                        mesh_state <= SM_ASYNC_ACTIVE;
+                    end else begin
+                        pcif_pop[inject_core_idx] <= 1;
+                    end
+                end
+
+                SM_ASYNC_ROUTE_POP: begin
+                    if (cap_empty[route_core_idx]) begin
+                        mesh_state <= SM_ASYNC_ACTIVE;
+                    end else begin
+                        cap_pop[route_core_idx] <= 1;
+                        route_neuron  <= (cap_data >> (route_core_idx * CAP_WIDTH + 8));
+                        route_payload <= (cap_data >> (route_core_idx * CAP_WIDTH));
+                        route_slot    <= 0;
+                        mesh_state    <= SM_ASYNC_ROUTE_ADDR;
+                    end
+                end
+
+                SM_ASYNC_ROUTE_ADDR: begin
+                    rt_addr    <= {route_core_idx, route_neuron, route_slot};
+                    mesh_state <= SM_ASYNC_ROUTE_WAIT;
+                end
+
+                SM_ASYNC_ROUTE_WAIT: begin
+                    mesh_state <= SM_ASYNC_ROUTE_READ;
+                end
+
+                SM_ASYNC_ROUTE_READ: begin
+                    if (rt_valid && !pcif_full[rt_dest_core]) begin
+                        pcif_push[rt_dest_core] <= 1;
+                        if (graded_enable)
+                            pcif_push_data <= {rt_dest_nrn, route_graded_current};
+                        else
+                            pcif_push_data <= {rt_dest_nrn, rt_weight};
+                    end
+
+                    if (route_slot < ROUTE_FANOUT - 1) begin
+                        route_slot <= route_slot + 1;
+                        mesh_state <= SM_ASYNC_ROUTE_ADDR;
+                    end else begin
+                        mesh_state <= SM_ASYNC_ROUTE_POP;
+                    end
+                end
+
+                SM_ASYNC_DONE: begin
+                    pcif_clear     <= {NUM_CORES{1'b1}};
+                    cap_clear      <= {NUM_CORES{1'b1}};
+                    timestep_done  <= 1;
+                    timestep_count <= timestep_count + 1;
+                    mesh_state     <= SM_IDLE;
+                end
+
+                default: mesh_state <= SM_IDLE;
+            endcase
+        end
+    end
+
+endmodule

rtl/neuromorphic_top.v

@@ -0,0 +1,557 @@
+// ============================================================================
+// Neuromorphic Top
+// ============================================================================
+//
+// Copyright 2026 Henry Arthur Shulayev Barnes / Catalyst Neuromorphic Ltd
+// Company No. 17054540 — UK Patent Application No. 2602902.6
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// ============================================================================
+
+module neuromorphic_top #(
+    parameter CLK_FREQ       = 100_000_000,
+    parameter BAUD           = 115200,
+    parameter NUM_CORES      = 128,
+    parameter CORE_ID_BITS   = 12,
+    parameter NUM_NEURONS    = 1024,
+    parameter NEURON_BITS    = 10,
+    parameter DATA_WIDTH     = 16,
+    parameter POOL_DEPTH     = 131072,
+    parameter POOL_ADDR_BITS = 17,
+    parameter COUNT_BITS     = 12,
+    parameter REV_FANIN      = 32,
+    parameter REV_SLOT_BITS  = 5,
+    parameter THRESHOLD      = 16'sd1000,
+    parameter LEAK_RATE      = 16'sd3,
+    parameter REFRAC_CYCLES  = 3,
+    parameter ROUTE_FANOUT   = 8,
+    parameter ROUTE_SLOT_BITS = 3,
+    parameter GLOBAL_ROUTE_SLOTS     = 4,
+    parameter GLOBAL_ROUTE_SLOT_BITS = 2,
+
+    parameter CHIP_LINK_EN = 0,
+    parameter NOC_MODE = 0,
+    parameter MESH_X   = 2,
+    parameter MESH_Y   = 2,
+
+    parameter BYPASS_UART = 0
+)(
+    input  wire clk,
+    input  wire rst_n,
+    input  wire uart_rxd,
+    output wire uart_txd,
+
+    output wire [7:0]  link_tx_data,
+    output wire        link_tx_valid,
+    input  wire        link_tx_ready,
+    input  wire [7:0]  link_rx_data,
+    input  wire        link_rx_valid,
+    output wire        link_rx_ready,
+
+    input  wire [7:0]  rx_data_ext,
+    input  wire        rx_valid_ext,
+    output wire [7:0]  tx_data_ext,
+    output wire        tx_valid_ext,
+    input  wire        tx_ready_ext
+);
+
+    wire [7:0] rx_data;
+    wire       rx_valid;
+    wire [7:0] tx_data;
+    wire       tx_valid;
+    wire       tx_ready;
+
+    generate
+        if (BYPASS_UART == 0) begin : gen_uart
+            uart_rx #(
+                .CLK_FREQ (CLK_FREQ),
+                .BAUD     (BAUD)
+            ) u_uart_rx (
+                .clk   (clk),
+                .rst_n (rst_n),
+                .rx    (uart_rxd),
+                .data  (rx_data),
+                .valid (rx_valid)
+            );
+
+            uart_tx #(
+                .CLK_FREQ (CLK_FREQ),
+                .BAUD     (BAUD)
+            ) u_uart_tx (
+                .clk   (clk),
+                .rst_n (rst_n),
+                .data  (tx_data),
+                .valid (tx_valid),
+                .tx    (uart_txd),
+                .ready (tx_ready)
+            );
+        end else begin : gen_bypass
+            assign rx_data  = rx_data_ext;
+            assign rx_valid = rx_valid_ext;
+            assign tx_ready = tx_ready_ext;
+            assign uart_txd = 1'b1;
+        end
+    endgenerate
+
+    assign tx_data_ext  = tx_data;
+    assign tx_valid_ext = tx_valid;
+
+    wire        hi_mesh_start;
+
+    wire                              hi_prog_pool_we;
+    wire [CORE_ID_BITS-1:0]         hi_prog_pool_core;
+    wire [POOL_ADDR_BITS-1:0]       hi_prog_pool_addr;
+    wire [NEURON_BITS-1:0]          hi_prog_pool_src;
+    wire [NEURON_BITS-1:0]          hi_prog_pool_target;
+    wire signed [DATA_WIDTH-1:0]    hi_prog_pool_weight;
+    wire [1:0]                      hi_prog_pool_comp;
+
+    wire                              hi_prog_index_we;
+    wire [CORE_ID_BITS-1:0]         hi_prog_index_core;
+    wire [NEURON_BITS-1:0]          hi_prog_index_neuron;
+    wire [POOL_ADDR_BITS-1:0]       hi_prog_index_base;
+    wire [COUNT_BITS-1:0]           hi_prog_index_count;
+    wire [1:0]                      hi_prog_index_format;
+
+    wire        hi_prog_route_we;
+    wire [CORE_ID_BITS-1:0]    hi_prog_route_src_core;
+    wire [NEURON_BITS-1:0]     hi_prog_route_src_neuron;
+    wire [ROUTE_SLOT_BITS-1:0] hi_prog_route_slot;
+    wire [CORE_ID_BITS-1:0]    hi_prog_route_dest_core;
+    wire [NEURON_BITS-1:0]     hi_prog_route_dest_neuron;
+    wire signed [DATA_WIDTH-1:0] hi_prog_route_weight;
+
+    wire                              hi_prog_global_route_we;
+    wire [CORE_ID_BITS-1:0]         hi_prog_global_route_src_core;
+    wire [NEURON_BITS-1:0]          hi_prog_global_route_src_neuron;
+    wire [GLOBAL_ROUTE_SLOT_BITS-1:0] hi_prog_global_route_slot;
+    wire [CORE_ID_BITS-1:0]         hi_prog_global_route_dest_core;
+    wire [NEURON_BITS-1:0]          hi_prog_global_route_dest_neuron;
+    wire signed [DATA_WIDTH-1:0]    hi_prog_global_route_weight;
+
+    wire        hi_ext_valid;
+    wire [CORE_ID_BITS-1:0]    hi_ext_core;
+    wire [NEURON_BITS-1:0]     hi_ext_neuron_id;
+    wire signed [DATA_WIDTH-1:0] hi_ext_current;
+
+    wire        hi_learn_enable;
+    wire        hi_graded_enable;
+    wire        hi_dendritic_enable;
+    wire        hi_async_enable;
+    wire        hi_threefactor_enable;
+    wire        hi_noise_enable;
+    wire        hi_skip_idle_enable;
+    wire        hi_scale_u_enable;
+    wire signed [DATA_WIDTH-1:0] hi_reward_value;
+
+    wire                              hi_prog_delay_we;
+    wire [CORE_ID_BITS-1:0]         hi_prog_delay_core;
+    wire [POOL_ADDR_BITS-1:0]       hi_prog_delay_addr;
+    wire [5:0]                      hi_prog_delay_value;
+
+    wire                              hi_prog_ucode_we;
+    wire [CORE_ID_BITS-1:0]         hi_prog_ucode_core;
+    wire [7:0]                      hi_prog_ucode_addr;
+    wire [31:0]                     hi_prog_ucode_data;
+
+    wire        hi_prog_param_we;
+    wire [CORE_ID_BITS-1:0]    hi_prog_param_core;
+    wire [NEURON_BITS-1:0]     hi_prog_param_neuron;
+    wire [4:0]                 hi_prog_param_id;
+    wire signed [DATA_WIDTH-1:0] hi_prog_param_value;
+
+    wire                              hi_probe_read;
+    wire [CORE_ID_BITS-1:0]         hi_probe_core;
+    wire [NEURON_BITS-1:0]          hi_probe_neuron;
+    wire [4:0]                      hi_probe_state_id;
+    wire [POOL_ADDR_BITS-1:0]       hi_probe_pool_addr;
+    wire signed [DATA_WIDTH-1:0]    mesh_probe_data;
+    wire                            mesh_probe_valid;
+
+    wire [7:0]  hi_dvfs_stall;
+
+    wire        mesh_timestep_done;
+    wire [5:0]  mesh_state;
+    wire [31:0] mesh_total_spikes;
+    wire [31:0] mesh_timestep_count;
+
+    host_interface #(
+        .NUM_CORES      (NUM_CORES),
+        .CORE_ID_BITS   (CORE_ID_BITS),
+        .NUM_NEURONS    (NUM_NEURONS),
+        .NEURON_BITS    (NEURON_BITS),
+        .DATA_WIDTH     (DATA_WIDTH),
+        .POOL_ADDR_BITS (POOL_ADDR_BITS),
+        .COUNT_BITS     (COUNT_BITS),
+        .ROUTE_SLOT_BITS(ROUTE_SLOT_BITS),
+        .GLOBAL_ROUTE_SLOT_BITS(GLOBAL_ROUTE_SLOT_BITS)
+    ) u_host_if (
+        .clk       (clk),
+        .rst_n     (rst_n),
+        .rx_data   (rx_data),
+        .rx_valid  (rx_valid),
+        .tx_data   (tx_data),
+        .tx_valid  (tx_valid),
+        .tx_ready  (tx_ready),
+
+        .mesh_start              (hi_mesh_start),
+
+        .mesh_prog_pool_we       (hi_prog_pool_we),
+        .mesh_prog_pool_core     (hi_prog_pool_core),
+        .mesh_prog_pool_addr     (hi_prog_pool_addr),
+        .mesh_prog_pool_src      (hi_prog_pool_src),
+        .mesh_prog_pool_target   (hi_prog_pool_target),
+        .mesh_prog_pool_weight   (hi_prog_pool_weight),
+        .mesh_prog_pool_comp     (hi_prog_pool_comp),
+
+        .mesh_prog_index_we      (hi_prog_index_we),
+        .mesh_prog_index_core    (hi_prog_index_core),
+        .mesh_prog_index_neuron  (hi_prog_index_neuron),
+        .mesh_prog_index_base    (hi_prog_index_base),
+        .mesh_prog_index_count   (hi_prog_index_count),
+        .mesh_prog_index_format  (hi_prog_index_format),
+
+        .mesh_prog_route_we      (hi_prog_route_we),
+        .mesh_prog_route_src_core   (hi_prog_route_src_core),
+        .mesh_prog_route_src_neuron (hi_prog_route_src_neuron),
+        .mesh_prog_route_slot       (hi_prog_route_slot),
+        .mesh_prog_route_dest_core  (hi_prog_route_dest_core),
+        .mesh_prog_route_dest_neuron(hi_prog_route_dest_neuron),
+        .mesh_prog_route_weight     (hi_prog_route_weight),
+
+        .mesh_prog_global_route_we          (hi_prog_global_route_we),
+        .mesh_prog_global_route_src_core    (hi_prog_global_route_src_core),
+        .mesh_prog_global_route_src_neuron  (hi_prog_global_route_src_neuron),
+        .mesh_prog_global_route_slot        (hi_prog_global_route_slot),
+        .mesh_prog_global_route_dest_core   (hi_prog_global_route_dest_core),
+        .mesh_prog_global_route_dest_neuron (hi_prog_global_route_dest_neuron),
+        .mesh_prog_global_route_weight      (hi_prog_global_route_weight),
+
+        .mesh_ext_valid          (hi_ext_valid),
+        .mesh_ext_core           (hi_ext_core),
+        .mesh_ext_neuron_id      (hi_ext_neuron_id),
+        .mesh_ext_current        (hi_ext_current),
+
+        .mesh_learn_enable       (hi_learn_enable),
+        .mesh_graded_enable      (hi_graded_enable),
+        .mesh_dendritic_enable   (hi_dendritic_enable),
+        .mesh_async_enable       (hi_async_enable),
+        .mesh_threefactor_enable (hi_threefactor_enable),
+        .mesh_noise_enable       (hi_noise_enable),
+        .mesh_skip_idle_enable   (hi_skip_idle_enable),
+        .mesh_scale_u_enable     (hi_scale_u_enable),
+        .mesh_reward_value       (hi_reward_value),
+
+        .mesh_prog_delay_we      (hi_prog_delay_we),
+        .mesh_prog_delay_core    (hi_prog_delay_core),
+        .mesh_prog_delay_addr    (hi_prog_delay_addr),
+        .mesh_prog_delay_value   (hi_prog_delay_value),
+
+        .mesh_prog_ucode_we     (hi_prog_ucode_we),
+        .mesh_prog_ucode_core   (hi_prog_ucode_core),
+        .mesh_prog_ucode_addr   (hi_prog_ucode_addr),
+        .mesh_prog_ucode_data   (hi_prog_ucode_data),
+
+        .mesh_prog_param_we      (hi_prog_param_we),
+        .mesh_prog_param_core    (hi_prog_param_core),
+        .mesh_prog_param_neuron  (hi_prog_param_neuron),
+        .mesh_prog_param_id      (hi_prog_param_id),
+        .mesh_prog_param_value   (hi_prog_param_value),
+
+        .mesh_probe_read     (hi_probe_read),
+        .mesh_probe_core     (hi_probe_core),
+        .mesh_probe_neuron   (hi_probe_neuron),
+        .mesh_probe_state_id (hi_probe_state_id),
+        .mesh_probe_pool_addr(hi_probe_pool_addr),
+        .mesh_probe_data     (mesh_probe_data),
+        .mesh_probe_valid    (mesh_probe_valid),
+
+        .mesh_dvfs_stall     (hi_dvfs_stall),
+
+        .mesh_timestep_done  (mesh_timestep_done),
+        .mesh_state          (mesh_state),
+        .mesh_total_spikes   (mesh_total_spikes),
+        .mesh_timestep_count (mesh_timestep_count)
+    );
+
+    wire        mesh_link_tx_push;
+    wire [CORE_ID_BITS-1:0] mesh_link_tx_core;
+    wire [NEURON_BITS-1:0]  mesh_link_tx_neuron;
+    wire [7:0]              mesh_link_tx_payload;
+    wire                    mesh_link_tx_full;
+    wire [CORE_ID_BITS-1:0] mesh_link_rx_core;
+    wire [NEURON_BITS-1:0]  mesh_link_rx_neuron;
+    wire signed [DATA_WIDTH-1:0] mesh_link_rx_current;
+    wire                    mesh_link_rx_pop;
+    wire                    mesh_link_rx_empty;
+
+    wire [NUM_CORES-1:0]             spike_valid_bus;
+    wire [NUM_CORES*NEURON_BITS-1:0] spike_id_bus;
+
+    generate
+        if (NOC_MODE == 1) begin : gen_async_noc
+            async_noc_mesh #(
+                .NUM_CORES      (NUM_CORES),
+                .CORE_ID_BITS   (CORE_ID_BITS),
+                .NUM_NEURONS    (NUM_NEURONS),
+                .NEURON_BITS    (NEURON_BITS),
+                .DATA_WIDTH     (DATA_WIDTH),
+                .POOL_DEPTH     (POOL_DEPTH),
+                .POOL_ADDR_BITS (POOL_ADDR_BITS),
+                .COUNT_BITS     (COUNT_BITS),
+                .REV_FANIN      (REV_FANIN),
+                .REV_SLOT_BITS  (REV_SLOT_BITS),
+                .THRESHOLD      (THRESHOLD),
+                .LEAK_RATE      (LEAK_RATE),
+                .REFRAC_CYCLES  (REFRAC_CYCLES),
+                .ROUTE_FANOUT   (ROUTE_FANOUT),
+                .ROUTE_SLOT_BITS(ROUTE_SLOT_BITS),
+                .GLOBAL_ROUTE_SLOTS    (GLOBAL_ROUTE_SLOTS),
+                .GLOBAL_ROUTE_SLOT_BITS(GLOBAL_ROUTE_SLOT_BITS),
+                .MESH_X         (MESH_X),
+                .MESH_Y         (MESH_Y)
+            ) u_mesh (
+                .clk               (clk),
+                .rst_n             (rst_n),
+                .start             (hi_mesh_start),
+                .learn_enable      (hi_learn_enable),
+                .graded_enable     (hi_graded_enable),
+                .dendritic_enable  (hi_dendritic_enable),
+                .async_enable      (hi_async_enable),
+                .threefactor_enable(hi_threefactor_enable),
+                .noise_enable      (hi_noise_enable),
+                .skip_idle_enable  (hi_skip_idle_enable),
+                .scale_u_enable    (hi_scale_u_enable),
+                .reward_value      (hi_reward_value),
+                .prog_pool_we      (hi_prog_pool_we),
+                .prog_pool_core    (hi_prog_pool_core),
+                .prog_pool_addr    (hi_prog_pool_addr),
+                .prog_pool_src     (hi_prog_pool_src),
+                .prog_pool_target  (hi_prog_pool_target),
+                .prog_pool_weight  (hi_prog_pool_weight),
+                .prog_pool_comp    (hi_prog_pool_comp),
+                .prog_index_we     (hi_prog_index_we),
+                .prog_index_core   (hi_prog_index_core),
+                .prog_index_neuron (hi_prog_index_neuron),
+                .prog_index_base   (hi_prog_index_base),
+                .prog_index_count  (hi_prog_index_count),
+                .prog_index_format (hi_prog_index_format),
+                .prog_route_we         (hi_prog_route_we),
+                .prog_route_src_core   (hi_prog_route_src_core),
+                .prog_route_src_neuron (hi_prog_route_src_neuron),
+                .prog_route_slot       (hi_prog_route_slot),
+                .prog_route_dest_core  (hi_prog_route_dest_core),
+                .prog_route_dest_neuron(hi_prog_route_dest_neuron),
+                .prog_route_weight     (hi_prog_route_weight),
+                .prog_global_route_we          (hi_prog_global_route_we),
+                .prog_global_route_src_core    (hi_prog_global_route_src_core),
+                .prog_global_route_src_neuron  (hi_prog_global_route_src_neuron),
+                .prog_global_route_slot        (hi_prog_global_route_slot),
+                .prog_global_route_dest_core   (hi_prog_global_route_dest_core),
+                .prog_global_route_dest_neuron (hi_prog_global_route_dest_neuron),
+                .prog_global_route_weight      (hi_prog_global_route_weight),
+                .prog_delay_we     (hi_prog_delay_we),
+                .prog_delay_core   (hi_prog_delay_core),
+                .prog_delay_addr   (hi_prog_delay_addr),
+                .prog_delay_value  (hi_prog_delay_value),
+                .prog_ucode_we     (hi_prog_ucode_we),
+                .prog_ucode_core   (hi_prog_ucode_core),
+                .prog_ucode_addr   (hi_prog_ucode_addr),
+                .prog_ucode_data   (hi_prog_ucode_data),
+                .prog_param_we     (hi_prog_param_we),
+                .prog_param_core   (hi_prog_param_core),
+                .prog_param_neuron (hi_prog_param_neuron),
+                .prog_param_id     (hi_prog_param_id),
+                .prog_param_value  (hi_prog_param_value),
+                .probe_read        (hi_probe_read),
+                .probe_core        (hi_probe_core),
+                .probe_neuron      (hi_probe_neuron),
+                .probe_state_id    (hi_probe_state_id),
+                .probe_pool_addr   (hi_probe_pool_addr),
+                .probe_data        (mesh_probe_data),
+                .probe_valid       (mesh_probe_valid),
+                .ext_valid         (hi_ext_valid),
+                .ext_core          (hi_ext_core),
+                .ext_neuron_id     (hi_ext_neuron_id),
+                .ext_current       (hi_ext_current),
+                .timestep_done     (mesh_timestep_done),
+                .spike_valid_bus   (spike_valid_bus),
+                .spike_id_bus      (spike_id_bus),
+                .mesh_state_out    (mesh_state),
+                .total_spikes      (mesh_total_spikes),
+                .timestep_count    (mesh_timestep_count),
+                .core_idle_bus     (),
+                .core_clock_en   (),
+                .energy_counter  (),
+                .power_idle_hint (),
+                .link_tx_push    (mesh_link_tx_push),
+                .link_tx_core    (mesh_link_tx_core),
+                .link_tx_neuron  (mesh_link_tx_neuron),
+                .link_tx_payload (mesh_link_tx_payload),
+                .link_tx_full    (mesh_link_tx_full),
+                .link_rx_core    (mesh_link_rx_core),
+                .link_rx_neuron  (mesh_link_rx_neuron),
+                .link_rx_current (mesh_link_rx_current),
+                .link_rx_pop     (mesh_link_rx_pop),
+                .link_rx_empty   (mesh_link_rx_empty)
+            );
+        end else begin : gen_barrier_mesh
+            neuromorphic_mesh #(
+                .NUM_CORES      (NUM_CORES),
+                .CORE_ID_BITS   (CORE_ID_BITS),
+                .NUM_NEURONS    (NUM_NEURONS),
+                .NEURON_BITS    (NEURON_BITS),
+                .DATA_WIDTH     (DATA_WIDTH),
+                .POOL_DEPTH     (POOL_DEPTH),
+                .POOL_ADDR_BITS (POOL_ADDR_BITS),
+                .COUNT_BITS     (COUNT_BITS),
+                .REV_FANIN      (REV_FANIN),
+                .REV_SLOT_BITS  (REV_SLOT_BITS),
+                .THRESHOLD      (THRESHOLD),
+                .LEAK_RATE      (LEAK_RATE),
+                .REFRAC_CYCLES  (REFRAC_CYCLES),
+                .ROUTE_FANOUT   (ROUTE_FANOUT),
+                .ROUTE_SLOT_BITS(ROUTE_SLOT_BITS),
+                .GLOBAL_ROUTE_SLOTS    (GLOBAL_ROUTE_SLOTS),
+                .GLOBAL_ROUTE_SLOT_BITS(GLOBAL_ROUTE_SLOT_BITS),
+                .CHIP_LINK_EN          (CHIP_LINK_EN)
+            ) u_mesh (
+                .clk               (clk),
+                .rst_n             (rst_n),
+                .start             (hi_mesh_start),
+                .dvfs_stall        (hi_dvfs_stall),
+                .learn_enable      (hi_learn_enable),
+                .graded_enable     (hi_graded_enable),
+                .dendritic_enable  (hi_dendritic_enable),
+                .async_enable      (hi_async_enable),
+                .threefactor_enable(hi_threefactor_enable),
+                .noise_enable      (hi_noise_enable),
+                .skip_idle_enable  (hi_skip_idle_enable),
+                .scale_u_enable    (hi_scale_u_enable),
+                .reward_value      (hi_reward_value),
+                .prog_pool_we      (hi_prog_pool_we),
+                .prog_pool_core    (hi_prog_pool_core),
+                .prog_pool_addr    (hi_prog_pool_addr),
+                .prog_pool_src     (hi_prog_pool_src),
+                .prog_pool_target  (hi_prog_pool_target),
+                .prog_pool_weight  (hi_prog_pool_weight),
+                .prog_pool_comp    (hi_prog_pool_comp),
+                .prog_index_we     (hi_prog_index_we),
+                .prog_index_core   (hi_prog_index_core),
+                .prog_index_neuron (hi_prog_index_neuron),
+                .prog_index_base   (hi_prog_index_base),
+                .prog_index_count  (hi_prog_index_count),
+                .prog_index_format (hi_prog_index_format),
+                .prog_route_we         (hi_prog_route_we),
+                .prog_route_src_core   (hi_prog_route_src_core),
+                .prog_route_src_neuron (hi_prog_route_src_neuron),
+                .prog_route_slot       (hi_prog_route_slot),
+                .prog_route_dest_core  (hi_prog_route_dest_core),
+                .prog_route_dest_neuron(hi_prog_route_dest_neuron),
+                .prog_route_weight     (hi_prog_route_weight),
+                .prog_global_route_we          (hi_prog_global_route_we),
+                .prog_global_route_src_core    (hi_prog_global_route_src_core),
+                .prog_global_route_src_neuron  (hi_prog_global_route_src_neuron),
+                .prog_global_route_slot        (hi_prog_global_route_slot),
+                .prog_global_route_dest_core   (hi_prog_global_route_dest_core),
+                .prog_global_route_dest_neuron (hi_prog_global_route_dest_neuron),
+                .prog_global_route_weight      (hi_prog_global_route_weight),
+                .prog_delay_we     (hi_prog_delay_we),
+                .prog_delay_core   (hi_prog_delay_core),
+                .prog_delay_addr   (hi_prog_delay_addr),
+                .prog_delay_value  (hi_prog_delay_value),
+                .prog_ucode_we     (hi_prog_ucode_we),
+                .prog_ucode_core   (hi_prog_ucode_core),
+                .prog_ucode_addr   (hi_prog_ucode_addr),
+                .prog_ucode_data   (hi_prog_ucode_data),
+                .prog_param_we     (hi_prog_param_we),
+                .prog_param_core   (hi_prog_param_core),
+                .prog_param_neuron (hi_prog_param_neuron),
+                .prog_param_id     (hi_prog_param_id),
+                .prog_param_value  (hi_prog_param_value),
+                .probe_read        (hi_probe_read),
+                .probe_core        (hi_probe_core),
+                .probe_neuron      (hi_probe_neuron),
+                .probe_state_id    (hi_probe_state_id),
+                .probe_pool_addr   (hi_probe_pool_addr),
+                .probe_data        (mesh_probe_data),
+                .probe_valid       (mesh_probe_valid),
+                .ext_valid         (hi_ext_valid),
+                .ext_core          (hi_ext_core),
+                .ext_neuron_id     (hi_ext_neuron_id),
+                .ext_current       (hi_ext_current),
+                .timestep_done     (mesh_timestep_done),
+                .spike_valid_bus   (spike_valid_bus),
+                .spike_id_bus      (spike_id_bus),
+                .mesh_state_out    (mesh_state),
+                .total_spikes      (mesh_total_spikes),
+                .timestep_count    (mesh_timestep_count),
+                .core_idle_bus     (),
+                .core_clock_en   (),
+                .energy_counter  (),
+                .power_idle_hint (),
+                .link_tx_push    (mesh_link_tx_push),
+                .link_tx_core    (mesh_link_tx_core),
+                .link_tx_neuron  (mesh_link_tx_neuron),
+                .link_tx_payload (mesh_link_tx_payload),
+                .link_tx_full    (mesh_link_tx_full),
+                .link_rx_core    (mesh_link_rx_core),
+                .link_rx_neuron  (mesh_link_rx_neuron),
+                .link_rx_current (mesh_link_rx_current),
+                .link_rx_pop     (mesh_link_rx_pop),
+                .link_rx_empty   (mesh_link_rx_empty)
+            );
+        end
+    endgenerate
+
+    generate
+        if (CHIP_LINK_EN) begin : gen_chip_link
+            chip_link #(
+                .CORE_ID_BITS (CORE_ID_BITS),
+                .NEURON_BITS  (NEURON_BITS),
+                .DATA_WIDTH   (DATA_WIDTH),
+                .TX_DEPTH     (256),
+                .RX_DEPTH     (256)
+            ) u_chip_link (
+                .clk            (clk),
+                .rst_n          (rst_n),
+                .tx_push        (mesh_link_tx_push),
+                .tx_core        (mesh_link_tx_core),
+                .tx_neuron      (mesh_link_tx_neuron),
+                .tx_payload     (mesh_link_tx_payload),
+                .tx_full        (mesh_link_tx_full),
+                .rx_core        (mesh_link_rx_core),
+                .rx_neuron      (mesh_link_rx_neuron),
+                .rx_current     (mesh_link_rx_current),
+                .rx_pop         (mesh_link_rx_pop),
+                .rx_empty       (mesh_link_rx_empty),
+                .link_tx_data   (link_tx_data),
+                .link_tx_valid  (link_tx_valid),
+                .link_tx_ready  (link_tx_ready),
+                .link_rx_data   (link_rx_data),
+                .link_rx_valid  (link_rx_valid),
+                .link_rx_ready  (link_rx_ready)
+            );
+        end else begin : gen_no_chip_link
+            assign mesh_link_tx_full  = 1'b0;
+            assign mesh_link_rx_core  = {CORE_ID_BITS{1'b0}};
+            assign mesh_link_rx_neuron = {NEURON_BITS{1'b0}};
+            assign mesh_link_rx_current = {DATA_WIDTH{1'b0}};
+            assign mesh_link_rx_empty = 1'b1;
+            assign link_tx_data  = 8'd0;
+            assign link_tx_valid = 1'b0;
+            assign link_rx_ready = 1'b0;
+        end
+    endgenerate
+
+endmodule

rtl/neuron_core.v

@@ -0,0 +1,112 @@
+// ============================================================================
+// Neuron Core
+// ============================================================================
+//
+// Copyright 2026 Henry Arthur Shulayev Barnes / Catalyst Neuromorphic Ltd
+// Company No. 17054540 — UK Patent Application No. 2602902.6
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// ============================================================================
+
+module neuron_core #(
+    parameter NUM_NEURONS = 4,
+    parameter DATA_WIDTH  = 16,
+    parameter THRESHOLD   = 16'd1000,
+    parameter LEAK_RATE   = 16'd2
+)(
+    input  wire                    clk,
+    input  wire                    rst_n,
+    input  wire                    enable,
+
+    input  wire signed [DATA_WIDTH-1:0] ext_input_0,
+    input  wire signed [DATA_WIDTH-1:0] ext_input_1,
+    input  wire signed [DATA_WIDTH-1:0] ext_input_2,
+    input  wire signed [DATA_WIDTH-1:0] ext_input_3,
+
+    input  wire signed [DATA_WIDTH-1:0] weight_00, weight_01, weight_02, weight_03,
+    input  wire signed [DATA_WIDTH-1:0] weight_10, weight_11, weight_12, weight_13,
+    input  wire signed [DATA_WIDTH-1:0] weight_20, weight_21, weight_22, weight_23,
+    input  wire signed [DATA_WIDTH-1:0] weight_30, weight_31, weight_32, weight_33,
+
+    output wire [NUM_NEURONS-1:0] spikes,
+
+    output wire [DATA_WIDTH-1:0] membrane_0,
+    output wire [DATA_WIDTH-1:0] membrane_1,
+    output wire [DATA_WIDTH-1:0] membrane_2,
+    output wire [DATA_WIDTH-1:0] membrane_3
+);
+
+    wire signed [DATA_WIDTH-1:0] syn_current [0:3][0:3];
+    wire signed [DATA_WIDTH-1:0] total_input [0:3];
+    wire signed [DATA_WIDTH-1:0] weights [0:3][0:3];
+
+    assign weights[0][0] = weight_00; assign weights[0][1] = weight_01;
+    assign weights[0][2] = weight_02; assign weights[0][3] = weight_03;
+    assign weights[1][0] = weight_10; assign weights[1][1] = weight_11;
+    assign weights[1][2] = weight_12; assign weights[1][3] = weight_13;
+    assign weights[2][0] = weight_20; assign weights[2][1] = weight_21;
+    assign weights[2][2] = weight_22; assign weights[2][3] = weight_23;
+    assign weights[3][0] = weight_30; assign weights[3][1] = weight_31;
+    assign weights[3][2] = weight_32; assign weights[3][3] = weight_33;
+
+    wire signed [DATA_WIDTH-1:0] ext_inputs [0:3];
+    assign ext_inputs[0] = ext_input_0;
+    assign ext_inputs[1] = ext_input_1;
+    assign ext_inputs[2] = ext_input_2;
+    assign ext_inputs[3] = ext_input_3;
+
+    genvar src, dst;
+    generate
+        for (src = 0; src < NUM_NEURONS; src = src + 1) begin : syn_src
+            for (dst = 0; dst < NUM_NEURONS; dst = dst + 1) begin : syn_dst
+                synapse #(
+                    .DATA_WIDTH(DATA_WIDTH)
+                ) syn_inst (
+                    .clk         (clk),
+                    .rst_n       (rst_n),
+                    .pre_spike   (spikes[src]),
+                    .weight      (weights[src][dst]),
+                    .post_current(syn_current[src][dst])
+                );
+            end
+        end
+    endgenerate
+
+    assign total_input[0] = ext_inputs[0] + syn_current[0][0] + syn_current[1][0] + syn_current[2][0] + syn_current[3][0];
+    assign total_input[1] = ext_inputs[1] + syn_current[0][1] + syn_current[1][1] + syn_current[2][1] + syn_current[3][1];
+    assign total_input[2] = ext_inputs[2] + syn_current[0][2] + syn_current[1][2] + syn_current[2][2] + syn_current[3][2];
+    assign total_input[3] = ext_inputs[3] + syn_current[0][3] + syn_current[1][3] + syn_current[2][3] + syn_current[3][3];
+
+    generate
+        for (dst = 0; dst < NUM_NEURONS; dst = dst + 1) begin : neurons
+            lif_neuron #(
+                .DATA_WIDTH (DATA_WIDTH),
+                .THRESHOLD  (THRESHOLD),
+                .LEAK_RATE  (LEAK_RATE)
+            ) neuron_inst (
+                .clk            (clk),
+                .rst_n          (rst_n),
+                .enable         (enable),
+                .synaptic_input (total_input[dst]),
+                .spike          (spikes[dst]),
+                .membrane_pot   ()
+            );
+        end
+    endgenerate
+
+    assign membrane_0 = neurons[0].neuron_inst.membrane_pot;
+    assign membrane_1 = neurons[1].neuron_inst.membrane_pot;
+    assign membrane_2 = neurons[2].neuron_inst.membrane_pot;
+    assign membrane_3 = neurons[3].neuron_inst.membrane_pot;
+
+endmodule

rtl/neuron_core_stdp.v

@@ -0,0 +1,132 @@
+// ============================================================================
+// Neuron Core with STDP Learning
+// ============================================================================
+//
+// Copyright 2026 Henry Arthur Shulayev Barnes / Catalyst Neuromorphic Ltd
+// Company No. 17054540 — UK Patent Application No. 2602902.6
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// ============================================================================
+
+module neuron_core_stdp #(
+    parameter NUM_NEURONS  = 4,
+    parameter DATA_WIDTH   = 16,
+    parameter THRESHOLD    = 16'd1000,
+    parameter LEAK_RATE    = 16'd2,
+    parameter WEIGHT_INIT  = 16'd100,
+    parameter WEIGHT_MAX   = 16'd800,
+    parameter LEARN_RATE   = 8'd3
+)(
+    input  wire                    clk,
+    input  wire                    rst_n,
+    input  wire                    enable,
+    input  wire                    learn_enable,
+
+    input  wire signed [DATA_WIDTH-1:0] ext_input_0,
+    input  wire signed [DATA_WIDTH-1:0] ext_input_1,
+    input  wire signed [DATA_WIDTH-1:0] ext_input_2,
+    input  wire signed [DATA_WIDTH-1:0] ext_input_3,
+
+    output wire [NUM_NEURONS-1:0] spikes,
+
+    output wire [DATA_WIDTH-1:0] membrane_0,
+    output wire [DATA_WIDTH-1:0] membrane_1,
+    output wire [DATA_WIDTH-1:0] membrane_2,
+    output wire [DATA_WIDTH-1:0] membrane_3,
+
+    output wire signed [DATA_WIDTH-1:0] w_out_01, w_out_02, w_out_03,
+    output wire signed [DATA_WIDTH-1:0] w_out_10, w_out_12, w_out_13,
+    output wire signed [DATA_WIDTH-1:0] w_out_20, w_out_21, w_out_23,
+    output wire signed [DATA_WIDTH-1:0] w_out_30, w_out_31, w_out_32
+);
+
+    wire signed [DATA_WIDTH-1:0] syn_current [0:3][0:3];
+    wire signed [DATA_WIDTH-1:0] syn_weight  [0:3][0:3];
+    wire signed [DATA_WIDTH-1:0] total_input [0:3];
+
+    wire signed [DATA_WIDTH-1:0] ext_inputs [0:3];
+    assign ext_inputs[0] = ext_input_0;
+    assign ext_inputs[1] = ext_input_1;
+    assign ext_inputs[2] = ext_input_2;
+    assign ext_inputs[3] = ext_input_3;
+
+    genvar src, dst;
+    generate
+        for (src = 0; src < NUM_NEURONS; src = src + 1) begin : syn_src
+            for (dst = 0; dst < NUM_NEURONS; dst = dst + 1) begin : syn_dst
+                if (src != dst) begin : real_syn
+                    stdp_synapse #(
+                        .DATA_WIDTH  (DATA_WIDTH),
+                        .WEIGHT_INIT (WEIGHT_INIT),
+                        .WEIGHT_MAX  (WEIGHT_MAX),
+                        .LEARN_RATE  (LEARN_RATE)
+                    ) syn_inst (
+                        .clk           (clk),
+                        .rst_n         (rst_n),
+                        .learn_enable  (learn_enable),
+                        .pre_spike     (spikes[src]),
+                        .post_spike    (spikes[dst]),
+                        .weight        (syn_weight[src][dst]),
+                        .post_current  (syn_current[src][dst]),
+                        .pre_trace_out (),
+                        .post_trace_out()
+                    );
+                end else begin : no_self
+                    assign syn_current[src][dst] = 0;
+                    assign syn_weight[src][dst]  = 0;
+                end
+            end
+        end
+    endgenerate
+
+    assign total_input[0] = ext_inputs[0] + syn_current[0][0] + syn_current[1][0] + syn_current[2][0] + syn_current[3][0];
+    assign total_input[1] = ext_inputs[1] + syn_current[0][1] + syn_current[1][1] + syn_current[2][1] + syn_current[3][1];
+    assign total_input[2] = ext_inputs[2] + syn_current[0][2] + syn_current[1][2] + syn_current[2][2] + syn_current[3][2];
+    assign total_input[3] = ext_inputs[3] + syn_current[0][3] + syn_current[1][3] + syn_current[2][3] + syn_current[3][3];
+
+    generate
+        for (dst = 0; dst < NUM_NEURONS; dst = dst + 1) begin : neurons
+            lif_neuron #(
+                .DATA_WIDTH (DATA_WIDTH),
+                .THRESHOLD  (THRESHOLD),
+                .LEAK_RATE  (LEAK_RATE)
+            ) neuron_inst (
+                .clk            (clk),
+                .rst_n          (rst_n),
+                .enable         (enable),
+                .synaptic_input (total_input[dst]),
+                .spike          (spikes[dst]),
+                .membrane_pot   ()
+            );
+        end
+    endgenerate
+
+    assign membrane_0 = neurons[0].neuron_inst.membrane_pot;
+    assign membrane_1 = neurons[1].neuron_inst.membrane_pot;
+    assign membrane_2 = neurons[2].neuron_inst.membrane_pot;
+    assign membrane_3 = neurons[3].neuron_inst.membrane_pot;
+
+    assign w_out_01 = syn_weight[0][1];
+    assign w_out_02 = syn_weight[0][2];
+    assign w_out_03 = syn_weight[0][3];
+    assign w_out_10 = syn_weight[1][0];
+    assign w_out_12 = syn_weight[1][2];
+    assign w_out_13 = syn_weight[1][3];
+    assign w_out_20 = syn_weight[2][0];
+    assign w_out_21 = syn_weight[2][1];
+    assign w_out_23 = syn_weight[2][3];
+    assign w_out_30 = syn_weight[3][0];
+    assign w_out_31 = syn_weight[3][1];
+    assign w_out_32 = syn_weight[3][2];
+
+endmodule

rtl/rv32i_core.v

@@ -0,0 +1,751 @@
+// ============================================================================
+// RV32I Core
+// ============================================================================
+//
+// Copyright 2026 Henry Arthur Shulayev Barnes / Catalyst Neuromorphic Ltd
+// Company No. 17054540 — UK Patent Application No. 2602902.6
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// ============================================================================
+
+`timescale 1ns/1ps
+
+module rv32i_core #(
+    parameter IMEM_DEPTH     = 65536,
+    parameter IMEM_ADDR_BITS = 16,
+    parameter DMEM_DEPTH     = 65536,
+    parameter DMEM_ADDR_BITS = 16
+)(
+    input  wire        clk,
+    input  wire        rst_n,
+    input  wire        enable,
+    input  wire        imem_we,
+    input  wire [IMEM_ADDR_BITS-1:0] imem_waddr,
+    input  wire [31:0] imem_wdata,
+    output reg         mmio_valid,
+    output reg         mmio_we,
+    output reg  [15:0] mmio_addr,
+    output reg  [31:0] mmio_wdata,
+    input  wire [31:0] mmio_rdata,
+    input  wire        mmio_ready,
+    output wire        halted,
+    output wire [31:0] pc_out,
+    input  wire [31:0] debug_bp_addr_0,
+    input  wire [31:0] debug_bp_addr_1,
+    input  wire [31:0] debug_bp_addr_2,
+    input  wire [31:0] debug_bp_addr_3,
+    input  wire [3:0]  debug_bp_enable,
+    input  wire        debug_resume,
+    input  wire        debug_halt_req,
+    input  wire        debug_single_step
+);
+
+    reg [31:0] regfile [0:31];
+
+    reg [31:0] fregfile [0:31];
+
+    reg [31:0] imem [0:IMEM_DEPTH-1];
+
+    always @(posedge clk) begin
+        if (imem_we)
+            imem[imem_waddr] <= imem_wdata;
+    end
+
+    reg [31:0] dmem [0:DMEM_DEPTH-1];
+
+    reg [31:0] pc;
+    reg [31:0] instr;
+    reg        fetch_valid;
+    reg        halt_r;
+
+    assign pc_out = pc;
+    assign halted = halt_r;
+
+    wire [IMEM_ADDR_BITS-1:0] pc_word = pc[IMEM_ADDR_BITS+1:2];
+    wire [31:0] fetched_instr = imem[pc_word];
+
+    wire [6:0]  opcode = instr[6:0];
+    wire [4:0]  rd     = instr[11:7];
+    wire [2:0]  funct3 = instr[14:12];
+    wire [4:0]  rs1    = instr[19:15];
+    wire [4:0]  rs2    = instr[24:20];
+    wire [6:0]  funct7 = instr[31:25];
+
+    wire [31:0] imm_i = {{20{instr[31]}}, instr[31:20]};
+    wire [31:0] imm_s = {{20{instr[31]}}, instr[31:25], instr[11:7]};
+    wire [31:0] imm_b = {{19{instr[31]}}, instr[31], instr[7], instr[30:25], instr[11:8], 1'b0};
+    wire [31:0] imm_u = {instr[31:12], 12'b0};
+    wire [31:0] imm_j = {{11{instr[31]}}, instr[31], instr[19:12], instr[20], instr[30:21], 1'b0};
+
+    wire [31:0] rs1_val = (rs1 == 5'd0) ? 32'd0 : regfile[rs1];
+    wire [31:0] rs2_val = (rs2 == 5'd0) ? 32'd0 : regfile[rs2];
+
+    localparam OP_LUI    = 7'b0110111;
+    localparam OP_AUIPC  = 7'b0010111;
+    localparam OP_JAL    = 7'b1101111;
+    localparam OP_JALR   = 7'b1100111;
+    localparam OP_BRANCH = 7'b1100011;
+    localparam OP_LOAD   = 7'b0000011;
+    localparam OP_STORE  = 7'b0100011;
+    localparam OP_IMM    = 7'b0010011;
+    localparam OP_REG    = 7'b0110011;
+    localparam OP_FENCE  = 7'b0001111;
+    localparam OP_SYSTEM = 7'b1110011;
+
+    localparam OP_FLW    = 7'b0000111;
+    localparam OP_FSW    = 7'b0100111;
+    localparam OP_FP     = 7'b1010011;
+
+    function real f32_to_real;
+        input [31:0] f;
+        reg [63:0] d;
+        begin
+            if (f[30:0] == 31'd0) begin
+                d = {f[31], 63'd0};
+            end else if (f[30:23] == 8'hFF) begin
+                d = {f[31], 11'h7FF, f[22:0], 29'd0};
+            end else begin
+                d[63]    = f[31];
+                d[62:52] = {3'd0, f[30:23]} + 11'd896;
+                d[51:0]  = {f[22:0], 29'd0};
+            end
+            f32_to_real = $bitstoreal(d);
+        end
+    endfunction
+
+    function [31:0] real_to_f32;
+        input real r;
+        reg [63:0] d;
+        reg [10:0] dexp;
+        reg [7:0]  fexp;
+        begin
+            d = $realtobits(r);
+            if (d[62:0] == 63'd0) begin
+                real_to_f32 = {d[63], 31'd0};
+            end else begin
+                dexp = d[62:52];
+                if (dexp >= 11'd1151) begin
+                    real_to_f32 = {d[63], 8'hFF, 23'd0};
+                end else if (dexp <= 11'd896) begin
+                    real_to_f32 = {d[63], 31'd0};
+                end else begin
+                    fexp = dexp - 11'd896;
+                    real_to_f32 = {d[63], fexp, d[51:29]};
+                end
+            end
+        end
+    endfunction
+
+    function real fp_sqrt;
+        input real x;
+        real guess;
+        integer i;
+        begin
+            if (x <= 0.0) begin
+                fp_sqrt = 0.0;
+            end else begin
+                guess = x;
+                for (i = 0; i < 25; i = i + 1)
+                    guess = (guess + x / guess) / 2.0;
+                fp_sqrt = guess;
+            end
+        end
+    endfunction
+
+    wire is_muldiv = (opcode == OP_REG) && (funct7 == 7'b0000001);
+
+    wire signed [63:0] mul_ss = $signed(rs1_val) * $signed(rs2_val);
+    wire        [63:0] mul_uu = rs1_val * rs2_val;
+    wire signed [63:0] mul_su = $signed(rs1_val) * $signed({1'b0, rs2_val});
+
+    wire signed [31:0] div_s = (rs2_val == 0) ? -32'sd1 :
+                               (rs1_val == 32'h80000000 && rs2_val == 32'hFFFFFFFF) ? 32'h80000000 :
+                               $signed(rs1_val) / $signed(rs2_val);
+    wire        [31:0] div_u = (rs2_val == 0) ? 32'hFFFFFFFF : rs1_val / rs2_val;
+    wire signed [31:0] rem_s = (rs2_val == 0) ? $signed(rs1_val) :
+                               (rs1_val == 32'h80000000 && rs2_val == 32'hFFFFFFFF) ? 32'sd0 :
+                               $signed(rs1_val) % $signed(rs2_val);
+    wire        [31:0] rem_u = (rs2_val == 0) ? rs1_val : rs1_val % rs2_val;
+
+    reg [31:0] muldiv_result;
+    always @(*) begin
+        case (funct3)
+            3'b000: muldiv_result = mul_ss[31:0];
+            3'b001: muldiv_result = mul_ss[63:32];
+            3'b010: muldiv_result = mul_su[63:32];
+            3'b011: muldiv_result = mul_uu[63:32];
+            3'b100: muldiv_result = div_s;
+            3'b101: muldiv_result = div_u;
+            3'b110: muldiv_result = rem_s;
+            3'b111: muldiv_result = rem_u;
+        endcase
+    end
+
+    reg [31:0] csr_mtvec;
+    reg [31:0] csr_mepc;
+    reg [31:0] csr_mcause;
+    reg [31:0] csr_mstatus;
+    reg [31:0] csr_mie;
+    reg [31:0] csr_mip;
+    reg [63:0] csr_mcycle;
+    reg [63:0] csr_mtimecmp;
+
+    localparam CSR_MSTATUS  = 12'h300;
+    localparam CSR_MIE      = 12'h304;
+    localparam CSR_MTVEC    = 12'h305;
+    localparam CSR_MEPC     = 12'h341;
+    localparam CSR_MCAUSE   = 12'h342;
+    localparam CSR_MIP      = 12'h344;
+    localparam CSR_MCYCLE   = 12'hB00;
+    localparam CSR_MCYCLEH  = 12'hB80;
+    localparam CSR_MTIMECMP  = 12'h7C0;
+    localparam CSR_MTIMECMPH = 12'h7C1;
+
+    wire [11:0] csr_addr = instr[31:20];
+    wire [4:0]  csr_zimm = rs1;
+
+    reg [31:0] csr_rdata;
+    always @(*) begin
+        case (csr_addr)
+            CSR_MSTATUS:  csr_rdata = csr_mstatus;
+            CSR_MIE:      csr_rdata = csr_mie;
+            CSR_MTVEC:    csr_rdata = csr_mtvec;
+            CSR_MEPC:     csr_rdata = csr_mepc;
+            CSR_MCAUSE:   csr_rdata = csr_mcause;
+            CSR_MIP:      csr_rdata = csr_mip;
+            CSR_MCYCLE:   csr_rdata = csr_mcycle[31:0];
+            CSR_MCYCLEH:  csr_rdata = csr_mcycle[63:32];
+            CSR_MTIMECMP: csr_rdata = csr_mtimecmp[31:0];
+            CSR_MTIMECMPH:csr_rdata = csr_mtimecmp[63:32];
+            default:      csr_rdata = 32'd0;
+        endcase
+    end
+
+    wire timer_pending = (csr_mcycle >= csr_mtimecmp);
+
+    wire timer_irq = timer_pending && csr_mstatus[3] && csr_mie[7];
+
+    wire [31:0] alu_b = (opcode == OP_REG) ? rs2_val : imm_i;
+    wire [4:0]  shamt = alu_b[4:0];
+
+    reg [31:0] alu_result;
+    always @(*) begin
+        case (funct3)
+            3'b000: alu_result = (opcode == OP_REG && funct7[5]) ?
+                                 (rs1_val - rs2_val) : (rs1_val + alu_b);
+            3'b001: alu_result = rs1_val << shamt;
+            3'b010: alu_result = ($signed(rs1_val) < $signed(alu_b)) ? 32'd1 : 32'd0;
+            3'b011: alu_result = (rs1_val < alu_b) ? 32'd1 : 32'd0;
+            3'b100: alu_result = rs1_val ^ alu_b;
+            3'b101: alu_result = funct7[5] ? ($signed(rs1_val) >>> shamt) :
+                                             (rs1_val >> shamt);
+            3'b110: alu_result = rs1_val | alu_b;
+            3'b111: alu_result = rs1_val & alu_b;
+            default: alu_result = 32'd0;
+        endcase
+    end
+
+    reg branch_taken;
+    always @(*) begin
+        case (funct3)
+            3'b000: branch_taken = (rs1_val == rs2_val);
+            3'b001: branch_taken = (rs1_val != rs2_val);
+            3'b100: branch_taken = ($signed(rs1_val) < $signed(rs2_val));
+            3'b101: branch_taken = ($signed(rs1_val) >= $signed(rs2_val));
+            3'b110: branch_taken = (rs1_val < rs2_val);
+            3'b111: branch_taken = (rs1_val >= rs2_val);
+            default: branch_taken = 1'b0;
+        endcase
+    end
+
+    wire [31:0] mem_addr = rs1_val + ((opcode == OP_STORE) ? imm_s : imm_i);
+    wire        is_mmio  = (mem_addr[31:16] == 16'hFFFF);
+    wire [DMEM_ADDR_BITS-1:0] dmem_word_addr = mem_addr[DMEM_ADDR_BITS+1:2];
+
+    localparam S_FETCH      = 4'd0;
+    localparam S_EXEC       = 4'd1;
+    localparam S_MEM_RD     = 4'd2;
+    localparam S_MEM_WR     = 4'd3;
+    localparam S_HALT       = 4'd4;
+    localparam S_TRAP       = 4'd5;
+    localparam S_DEBUG_HALT = 4'd6;
+
+    reg [3:0] state;
+
+    reg debug_single_step_pending;
+
+    wire bp_match = (debug_bp_enable[0] && (pc == debug_bp_addr_0)) ||
+                    (debug_bp_enable[1] && (pc == debug_bp_addr_1)) ||
+                    (debug_bp_enable[2] && (pc == debug_bp_addr_2)) ||
+                    (debug_bp_enable[3] && (pc == debug_bp_addr_3));
+
+    real fp_op_a, fp_op_b, fp_op_r;
+    reg  mem_rd_is_float;
+
+    integer ri;
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n) begin
+            pc          <= 32'd0;
+            instr       <= 32'd0;
+            fetch_valid <= 1'b0;
+            halt_r      <= 1'b0;
+            state       <= S_FETCH;
+            mmio_valid  <= 1'b0;
+            mmio_we     <= 1'b0;
+            mmio_addr   <= 16'd0;
+            mmio_wdata  <= 32'd0;
+
+            csr_mtvec    <= 32'd0;
+            csr_mepc     <= 32'd0;
+            csr_mcause   <= 32'd0;
+            csr_mstatus  <= 32'd0;
+            csr_mie      <= 32'd0;
+            csr_mip      <= 32'd0;
+            csr_mcycle   <= 64'd0;
+            csr_mtimecmp <= 64'hFFFFFFFF_FFFFFFFF;
+            mem_rd_is_float <= 1'b0;
+            debug_single_step_pending <= 1'b0;
+            for (ri = 0; ri < 32; ri = ri + 1) begin
+                regfile[ri]  <= 32'd0;
+                fregfile[ri] <= 32'd0;
+            end
+        end else if (!enable) begin
+            state <= S_FETCH;
+            pc    <= 32'd0;
+            halt_r <= 1'b0;
+            mmio_valid <= 1'b0;
+            mem_rd_is_float <= 1'b0;
+            csr_mcycle <= 64'd0;
+            debug_single_step_pending <= 1'b0;
+        end else begin
+
+            csr_mcycle <= csr_mcycle + 64'd1;
+
+            csr_mip[7] <= timer_pending;
+
+            case (state)
+                S_FETCH: begin
+
+                    if (debug_halt_req) begin
+                        halt_r <= 1'b1;
+                        state  <= S_DEBUG_HALT;
+                    end
+
+                    else if (bp_match) begin
+                        halt_r <= 1'b1;
+                        state  <= S_DEBUG_HALT;
+                    end
+
+                    else if (debug_single_step_pending) begin
+                        debug_single_step_pending <= 1'b0;
+                        halt_r <= 1'b1;
+                        state  <= S_DEBUG_HALT;
+                    end
+
+                    else if (timer_irq) begin
+                        csr_mepc    <= pc;
+                        csr_mcause  <= 32'h80000007;
+                        csr_mstatus[3] <= 1'b0;
+                        csr_mstatus[7] <= csr_mstatus[3];
+                        pc          <= csr_mtvec & ~32'd3;
+                        state       <= S_FETCH;
+                    end else begin
+                        instr       <= fetched_instr;
+                        fetch_valid <= 1'b1;
+                        state       <= S_EXEC;
+                    end
+                end
+
+                S_EXEC: begin
+                    mmio_valid <= 1'b0;
+
+                    case (opcode)
+                        OP_LUI: begin
+                            if (rd != 0) regfile[rd] <= imm_u;
+                            pc <= pc + 4;
+                            state <= S_FETCH;
+                        end
+
+                        OP_AUIPC: begin
+                            if (rd != 0) regfile[rd] <= pc + imm_u;
+                            pc <= pc + 4;
+                            state <= S_FETCH;
+                        end
+
+                        OP_JAL: begin
+                            if (rd != 0) regfile[rd] <= pc + 4;
+                            pc <= pc + imm_j;
+                            state <= S_FETCH;
+                        end
+
+                        OP_JALR: begin
+                            if (rd != 0) regfile[rd] <= pc + 4;
+                            pc <= (rs1_val + imm_i) & ~32'd1;
+                            state <= S_FETCH;
+                        end
+
+                        OP_BRANCH: begin
+                            pc <= branch_taken ? (pc + imm_b) : (pc + 4);
+                            state <= S_FETCH;
+                        end
+
+                        OP_LOAD: begin
+                            if (is_mmio) begin
+                                mmio_valid <= 1'b1;
+                                mmio_we    <= 1'b0;
+                                mmio_addr  <= mem_addr[15:0];
+                                mem_rd_is_float <= 1'b0;
+                                state      <= S_MEM_RD;
+                            end else begin
+
+                                if (rd != 0) begin
+                                    case (funct3)
+                                        3'b000: begin
+                                            case (mem_addr[1:0])
+                                                2'd0: regfile[rd] <= {{24{dmem[dmem_word_addr][7]}},  dmem[dmem_word_addr][7:0]};
+                                                2'd1: regfile[rd] <= {{24{dmem[dmem_word_addr][15]}}, dmem[dmem_word_addr][15:8]};
+                                                2'd2: regfile[rd] <= {{24{dmem[dmem_word_addr][23]}}, dmem[dmem_word_addr][23:16]};
+                                                2'd3: regfile[rd] <= {{24{dmem[dmem_word_addr][31]}}, dmem[dmem_word_addr][31:24]};
+                                            endcase
+                                        end
+                                        3'b001: begin
+                                            if (mem_addr[1])
+                                                regfile[rd] <= {{16{dmem[dmem_word_addr][31]}}, dmem[dmem_word_addr][31:16]};
+                                            else
+                                                regfile[rd] <= {{16{dmem[dmem_word_addr][15]}}, dmem[dmem_word_addr][15:0]};
+                                        end
+                                        3'b010: regfile[rd] <= dmem[dmem_word_addr];
+                                        3'b100: begin
+                                            case (mem_addr[1:0])
+                                                2'd0: regfile[rd] <= {24'd0, dmem[dmem_word_addr][7:0]};
+                                                2'd1: regfile[rd] <= {24'd0, dmem[dmem_word_addr][15:8]};
+                                                2'd2: regfile[rd] <= {24'd0, dmem[dmem_word_addr][23:16]};
+                                                2'd3: regfile[rd] <= {24'd0, dmem[dmem_word_addr][31:24]};
+                                            endcase
+                                        end
+                                        3'b101: begin
+                                            if (mem_addr[1])
+                                                regfile[rd] <= {16'd0, dmem[dmem_word_addr][31:16]};
+                                            else
+                                                regfile[rd] <= {16'd0, dmem[dmem_word_addr][15:0]};
+                                        end
+                                        default: ;
+                                    endcase
+                                end
+                                pc    <= pc + 4;
+                                state <= S_FETCH;
+                            end
+                        end
+
+                        OP_STORE: begin
+                            if (is_mmio) begin
+                                mmio_valid <= 1'b1;
+                                mmio_we    <= 1'b1;
+                                mmio_addr  <= mem_addr[15:0];
+                                mmio_wdata <= rs2_val;
+                                state      <= S_MEM_WR;
+                            end else begin
+                                case (funct3)
+                                    3'b000: begin
+                                        case (mem_addr[1:0])
+                                            2'd0: dmem[dmem_word_addr][7:0]   <= rs2_val[7:0];
+                                            2'd1: dmem[dmem_word_addr][15:8]  <= rs2_val[7:0];
+                                            2'd2: dmem[dmem_word_addr][23:16] <= rs2_val[7:0];
+                                            2'd3: dmem[dmem_word_addr][31:24] <= rs2_val[7:0];
+                                        endcase
+                                    end
+                                    3'b001: begin
+                                        if (mem_addr[1])
+                                            dmem[dmem_word_addr][31:16] <= rs2_val[15:0];
+                                        else
+                                            dmem[dmem_word_addr][15:0]  <= rs2_val[15:0];
+                                    end
+                                    3'b010: dmem[dmem_word_addr] <= rs2_val;
+                                    default: ;
+                                endcase
+                                pc    <= pc + 4;
+                                state <= S_FETCH;
+                            end
+                        end
+
+                        OP_IMM: begin
+                            if (rd != 0) regfile[rd] <= alu_result;
+                            pc    <= pc + 4;
+                            state <= S_FETCH;
+                        end
+
+                        OP_REG: begin
+
+                            if (is_muldiv) begin
+                                if (rd != 0) regfile[rd] <= muldiv_result;
+                            end else begin
+                                if (rd != 0) regfile[rd] <= alu_result;
+                            end
+                            pc    <= pc + 4;
+                            state <= S_FETCH;
+                        end
+
+                        OP_FENCE: begin
+
+                            pc    <= pc + 4;
+                            state <= S_FETCH;
+                        end
+
+                        OP_SYSTEM: begin
+                            if (funct3 == 3'b000) begin
+
+                                if (instr[31:20] == 12'h302) begin
+
+                                    pc <= csr_mepc;
+                                    csr_mstatus[3] <= csr_mstatus[7];
+                                    csr_mstatus[7] <= 1'b1;
+                                    state <= S_FETCH;
+                                end else begin
+
+                                    halt_r <= 1'b1;
+                                    state  <= S_HALT;
+                                end
+                            end else begin
+
+                                if (rd != 0) regfile[rd] <= csr_rdata;
+
+                                case (funct3)
+                                    3'b001: begin
+                                        case (csr_addr)
+                                            CSR_MSTATUS:  csr_mstatus  <= rs1_val;
+                                            CSR_MIE:      csr_mie      <= rs1_val;
+                                            CSR_MTVEC:    csr_mtvec    <= rs1_val;
+                                            CSR_MEPC:     csr_mepc     <= rs1_val;
+                                            CSR_MCAUSE:   csr_mcause   <= rs1_val;
+                                            CSR_MTIMECMP: csr_mtimecmp[31:0]  <= rs1_val;
+                                            CSR_MTIMECMPH:csr_mtimecmp[63:32] <= rs1_val;
+                                            default: ;
+                                        endcase
+                                    end
+                                    3'b010: begin
+                                        if (rs1 != 0) begin
+                                            case (csr_addr)
+                                                CSR_MSTATUS:  csr_mstatus  <= csr_mstatus  | rs1_val;
+                                                CSR_MIE:      csr_mie      <= csr_mie      | rs1_val;
+                                                CSR_MTVEC:    csr_mtvec    <= csr_mtvec    | rs1_val;
+                                                default: ;
+                                            endcase
+                                        end
+                                    end
+                                    3'b011: begin
+                                        if (rs1 != 0) begin
+                                            case (csr_addr)
+                                                CSR_MSTATUS:  csr_mstatus  <= csr_mstatus  & ~rs1_val;
+                                                CSR_MIE:      csr_mie      <= csr_mie      & ~rs1_val;
+                                                default: ;
+                                            endcase
+                                        end
+                                    end
+                                    3'b101: begin
+                                        case (csr_addr)
+                                            CSR_MSTATUS:  csr_mstatus  <= {27'd0, csr_zimm};
+                                            CSR_MIE:      csr_mie      <= {27'd0, csr_zimm};
+                                            CSR_MTVEC:    csr_mtvec    <= {27'd0, csr_zimm};
+                                            default: ;
+                                        endcase
+                                    end
+                                    3'b110: begin
+                                        if (csr_zimm != 0) begin
+                                            case (csr_addr)
+                                                CSR_MSTATUS:  csr_mstatus <= csr_mstatus | {27'd0, csr_zimm};
+                                                CSR_MIE:      csr_mie     <= csr_mie     | {27'd0, csr_zimm};
+                                                default: ;
+                                            endcase
+                                        end
+                                    end
+                                    3'b111: begin
+                                        if (csr_zimm != 0) begin
+                                            case (csr_addr)
+                                                CSR_MSTATUS:  csr_mstatus <= csr_mstatus & ~{27'd0, csr_zimm};
+                                                CSR_MIE:      csr_mie     <= csr_mie     & ~{27'd0, csr_zimm};
+                                                default: ;
+                                            endcase
+                                        end
+                                    end
+                                    default: ;
+                                endcase
+
+                                pc    <= pc + 4;
+                                state <= S_FETCH;
+                            end
+                        end
+
+                        OP_FLW: begin
+                            if (is_mmio) begin
+                                mmio_valid <= 1'b1;
+                                mmio_we    <= 1'b0;
+                                mmio_addr  <= mem_addr[15:0];
+                                mem_rd_is_float <= 1'b1;
+                                state      <= S_MEM_RD;
+                            end else begin
+                                fregfile[rd] <= dmem[dmem_word_addr];
+                                pc    <= pc + 4;
+                                state <= S_FETCH;
+                            end
+                        end
+
+                        OP_FSW: begin
+                            if (is_mmio) begin
+                                mmio_valid <= 1'b1;
+                                mmio_we    <= 1'b1;
+                                mmio_addr  <= mem_addr[15:0];
+                                mmio_wdata <= fregfile[rs2];
+                                state      <= S_MEM_WR;
+                            end else begin
+                                dmem[dmem_word_addr] <= fregfile[rs2];
+                                pc    <= pc + 4;
+                                state <= S_FETCH;
+                            end
+                        end
+
+                        OP_FP: begin
+                            case (funct7)
+                                7'b0000000: begin
+                                    fp_op_a = f32_to_real(fregfile[rs1]);
+                                    fp_op_b = f32_to_real(fregfile[rs2]);
+                                    fregfile[rd] <= real_to_f32(fp_op_a + fp_op_b);
+                                end
+                                7'b0000100: begin
+                                    fp_op_a = f32_to_real(fregfile[rs1]);
+                                    fp_op_b = f32_to_real(fregfile[rs2]);
+                                    fregfile[rd] <= real_to_f32(fp_op_a - fp_op_b);
+                                end
+                                7'b0001000: begin
+                                    fp_op_a = f32_to_real(fregfile[rs1]);
+                                    fp_op_b = f32_to_real(fregfile[rs2]);
+                                    fregfile[rd] <= real_to_f32(fp_op_a * fp_op_b);
+                                end
+                                7'b0001100: begin
+                                    fp_op_a = f32_to_real(fregfile[rs1]);
+                                    fp_op_b = f32_to_real(fregfile[rs2]);
+                                    if (fp_op_b != 0.0)
+                                        fregfile[rd] <= real_to_f32(fp_op_a / fp_op_b);
+                                    else
+                                        fregfile[rd] <= 32'h7FC00000;
+                                end
+                                7'b0101100: begin
+                                    fp_op_a = f32_to_real(fregfile[rs1]);
+                                    fp_op_r = fp_sqrt(fp_op_a);
+                                    fregfile[rd] <= real_to_f32(fp_op_r);
+                                end
+                                7'b0010100: begin
+                                    fp_op_a = f32_to_real(fregfile[rs1]);
+                                    fp_op_b = f32_to_real(fregfile[rs2]);
+                                    case (funct3)
+                                        3'b000: fregfile[rd] <= (fp_op_a <= fp_op_b) ?
+                                                    fregfile[rs1] : fregfile[rs2];
+                                        3'b001: fregfile[rd] <= (fp_op_a >= fp_op_b) ?
+                                                    fregfile[rs1] : fregfile[rs2];
+                                        default: ;
+                                    endcase
+                                end
+                                7'b0010000: begin
+                                    case (funct3)
+                                        3'b000: fregfile[rd] <= {fregfile[rs2][31],
+                                                    fregfile[rs1][30:0]};
+                                        3'b001: fregfile[rd] <= {~fregfile[rs2][31],
+                                                    fregfile[rs1][30:0]};
+                                        3'b010: fregfile[rd] <= {fregfile[rs1][31] ^
+                                                    fregfile[rs2][31],
+                                                    fregfile[rs1][30:0]};
+                                        default: ;
+                                    endcase
+                                end
+                                7'b1100000: begin
+                                    fp_op_a = f32_to_real(fregfile[rs1]);
+                                    if (rd != 0) regfile[rd] <= $rtoi(fp_op_a);
+                                end
+                                7'b1101000: begin
+                                    fregfile[rd] <= real_to_f32($itor($signed(rs1_val)));
+                                end
+                                7'b1010000: begin
+                                    fp_op_a = f32_to_real(fregfile[rs1]);
+                                    fp_op_b = f32_to_real(fregfile[rs2]);
+                                    if (rd != 0) begin
+                                        case (funct3)
+                                            3'b010: regfile[rd] <= (fp_op_a == fp_op_b) ?
+                                                        32'd1 : 32'd0;
+                                            3'b001: regfile[rd] <= (fp_op_a < fp_op_b) ?
+                                                        32'd1 : 32'd0;
+                                            3'b000: regfile[rd] <= (fp_op_a <= fp_op_b) ?
+                                                        32'd1 : 32'd0;
+                                            default: ;
+                                        endcase
+                                    end
+                                end
+                                7'b1110000: begin
+                                    if (rd != 0) regfile[rd] <= fregfile[rs1];
+                                end
+                                7'b1111000: begin
+                                    fregfile[rd] <= rs1_val;
+                                end
+                                default: ;
+                            endcase
+                            pc    <= pc + 4;
+                            state <= S_FETCH;
+                        end
+
+                        default: begin
+                            halt_r <= 1'b1;
+                            state  <= S_HALT;
+                        end
+                    endcase
+                end
+
+                S_MEM_RD: begin
+                    if (mmio_ready) begin
+                        mmio_valid <= 1'b0;
+                        if (mem_rd_is_float) begin
+                            fregfile[rd] <= mmio_rdata;
+                            mem_rd_is_float <= 1'b0;
+                        end else begin
+                            if (rd != 0) regfile[rd] <= mmio_rdata;
+                        end
+                        pc    <= pc + 4;
+                        state <= S_FETCH;
+                    end
+                end
+
+                S_MEM_WR: begin
+                    if (mmio_ready) begin
+                        mmio_valid <= 1'b0;
+                        pc    <= pc + 4;
+                        state <= S_FETCH;
+                    end
+                end
+
+                S_HALT: begin
+                end
+
+                S_DEBUG_HALT: begin
+                    if (debug_resume) begin
+                        halt_r <= 1'b0;
+                        state  <= S_FETCH;
+                    end else if (debug_single_step) begin
+                        halt_r <= 1'b0;
+                        debug_single_step_pending <= 1'b1;
+                        state  <= S_FETCH;
+                    end
+                end
+
+                default: state <= S_HALT;
+            endcase
+        end
+    end
+
+endmodule

rtl/rv32im_cluster.v

@@ -0,0 +1,171 @@
+// ============================================================================
+// RV32IM Cluster
+// ============================================================================
+//
+// Copyright 2026 Henry Arthur Shulayev Barnes / Catalyst Neuromorphic Ltd
+// Company No. 17054540 — UK Patent Application No. 2602902.6
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// ============================================================================
+
+`timescale 1ns/1ps
+
+module rv32im_cluster #(
+    parameter IMEM_DEPTH     = 65536,
+    parameter IMEM_ADDR_BITS = 16,
+    parameter DMEM_DEPTH     = 65536,
+    parameter DMEM_ADDR_BITS = 16
+)(
+    input  wire        clk,
+    input  wire        rst_n,
+
+    input  wire [2:0]  enable,
+
+    input  wire                        imem_we_0,
+    input  wire [IMEM_ADDR_BITS-1:0]  imem_waddr_0,
+    input  wire [31:0]                imem_wdata_0,
+
+    input  wire                        imem_we_1,
+    input  wire [IMEM_ADDR_BITS-1:0]  imem_waddr_1,
+    input  wire [31:0]                imem_wdata_1,
+
+    input  wire                        imem_we_2,
+    input  wire [IMEM_ADDR_BITS-1:0]  imem_waddr_2,
+    input  wire [31:0]                imem_wdata_2,
+
+    output wire                        mmio_valid,
+    output wire                        mmio_we,
+    output wire [15:0]                mmio_addr,
+    output wire [31:0]                mmio_wdata,
+    input  wire [31:0]                mmio_rdata,
+    input  wire                        mmio_ready,
+
+    output wire [2:0]  halted,
+    output wire [31:0] pc_out_0,
+    output wire [31:0] pc_out_1,
+    output wire [31:0] pc_out_2
+);
+
+    wire        c0_mmio_valid, c0_mmio_we;
+    wire [15:0] c0_mmio_addr;
+    wire [31:0] c0_mmio_wdata;
+
+    rv32i_core #(
+        .IMEM_DEPTH(IMEM_DEPTH), .IMEM_ADDR_BITS(IMEM_ADDR_BITS),
+        .DMEM_DEPTH(DMEM_DEPTH), .DMEM_ADDR_BITS(DMEM_ADDR_BITS)
+    ) core0 (
+        .clk(clk), .rst_n(rst_n), .enable(enable[0]),
+        .imem_we(imem_we_0), .imem_waddr(imem_waddr_0), .imem_wdata(imem_wdata_0),
+        .mmio_valid(c0_mmio_valid), .mmio_we(c0_mmio_we),
+        .mmio_addr(c0_mmio_addr), .mmio_wdata(c0_mmio_wdata),
+        .mmio_rdata(combined_rdata),
+        .mmio_ready(c0_mmio_valid ? combined_ready : 1'b0),
+        .halted(halted[0]), .pc_out(pc_out_0),
+        .debug_bp_addr_0(32'd0), .debug_bp_addr_1(32'd0),
+        .debug_bp_addr_2(32'd0), .debug_bp_addr_3(32'd0),
+        .debug_bp_enable(4'd0),
+        .debug_resume(1'b0), .debug_halt_req(1'b0), .debug_single_step(1'b0)
+    );
+
+    wire        c1_mmio_valid, c1_mmio_we;
+    wire [15:0] c1_mmio_addr;
+    wire [31:0] c1_mmio_wdata;
+
+    wire c1_grant = c1_mmio_valid && !c0_mmio_valid;
+
+    rv32i_core #(
+        .IMEM_DEPTH(IMEM_DEPTH), .IMEM_ADDR_BITS(IMEM_ADDR_BITS),
+        .DMEM_DEPTH(DMEM_DEPTH), .DMEM_ADDR_BITS(DMEM_ADDR_BITS)
+    ) core1 (
+        .clk(clk), .rst_n(rst_n), .enable(enable[1]),
+        .imem_we(imem_we_1), .imem_waddr(imem_waddr_1), .imem_wdata(imem_wdata_1),
+        .mmio_valid(c1_mmio_valid), .mmio_we(c1_mmio_we),
+        .mmio_addr(c1_mmio_addr), .mmio_wdata(c1_mmio_wdata),
+        .mmio_rdata(combined_rdata),
+        .mmio_ready(c1_grant ? combined_ready : 1'b0),
+        .halted(halted[1]), .pc_out(pc_out_1),
+        .debug_bp_addr_0(32'd0), .debug_bp_addr_1(32'd0),
+        .debug_bp_addr_2(32'd0), .debug_bp_addr_3(32'd0),
+        .debug_bp_enable(4'd0),
+        .debug_resume(1'b0), .debug_halt_req(1'b0), .debug_single_step(1'b0)
+    );
+
+    wire        c2_mmio_valid, c2_mmio_we;
+    wire [15:0] c2_mmio_addr;
+    wire [31:0] c2_mmio_wdata;
+
+    wire c2_grant = c2_mmio_valid && !c0_mmio_valid && !c1_mmio_valid;
+
+    rv32i_core #(
+        .IMEM_DEPTH(IMEM_DEPTH), .IMEM_ADDR_BITS(IMEM_ADDR_BITS),
+        .DMEM_DEPTH(DMEM_DEPTH), .DMEM_ADDR_BITS(DMEM_ADDR_BITS)
+    ) core2 (
+        .clk(clk), .rst_n(rst_n), .enable(enable[2]),
+        .imem_we(imem_we_2), .imem_waddr(imem_waddr_2), .imem_wdata(imem_wdata_2),
+        .mmio_valid(c2_mmio_valid), .mmio_we(c2_mmio_we),
+        .mmio_addr(c2_mmio_addr), .mmio_wdata(c2_mmio_wdata),
+        .mmio_rdata(combined_rdata),
+        .mmio_ready(c2_grant ? combined_ready : 1'b0),
+        .halted(halted[2]), .pc_out(pc_out_2),
+        .debug_bp_addr_0(32'd0), .debug_bp_addr_1(32'd0),
+        .debug_bp_addr_2(32'd0), .debug_bp_addr_3(32'd0),
+        .debug_bp_enable(4'd0),
+        .debug_resume(1'b0), .debug_halt_req(1'b0), .debug_single_step(1'b0)
+    );
+
+    reg [31:0] mailbox [0:3];
+
+    integer mbi;
+
+    wire        arb_valid = c0_mmio_valid | c1_mmio_valid | c2_mmio_valid;
+    wire [15:0] arb_addr  = c0_mmio_valid ? c0_mmio_addr :
+                            c1_mmio_valid ? c1_mmio_addr :
+                                            c2_mmio_addr;
+    wire        arb_we    = c0_mmio_valid ? c0_mmio_we :
+                            c1_mmio_valid ? c1_mmio_we :
+                                            c2_mmio_we;
+    wire [31:0] arb_wdata = c0_mmio_valid ? c0_mmio_wdata :
+                            c1_mmio_valid ? c1_mmio_wdata :
+                                            c2_mmio_wdata;
+
+    wire is_mailbox = arb_valid && (arb_addr >= 16'h0080) && (arb_addr <= 16'h008C);
+    wire [1:0] mailbox_idx = arb_addr[3:2];
+
+    reg [31:0] mailbox_rdata;
+    always @(*) begin
+        mailbox_rdata = mailbox[mailbox_idx];
+    end
+
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n) begin
+            for (mbi = 0; mbi < 4; mbi = mbi + 1)
+                mailbox[mbi] <= 32'd0;
+        end else if (is_mailbox && arb_we) begin
+            mailbox[mailbox_idx] <= arb_wdata;
+        end
+    end
+
+    wire mailbox_ready = is_mailbox;
+
+    assign mmio_valid = arb_valid && !is_mailbox;
+
+    assign mmio_we = arb_we;
+
+    assign mmio_addr = arb_addr;
+
+    assign mmio_wdata = arb_wdata;
+
+    wire [31:0] combined_rdata = is_mailbox ? mailbox_rdata : mmio_rdata;
+    wire        combined_ready = is_mailbox ? mailbox_ready : mmio_ready;
+
+endmodule

rtl/scalable_core.v

@@ -0,0 +1,382 @@
+// ============================================================================
+// Scalable Neuron Core
+// ============================================================================
+//
+// Copyright 2026 Henry Arthur Shulayev Barnes / Catalyst Neuromorphic Ltd
+// Company No. 17054540 — UK Patent Application No. 2602902.6
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// ============================================================================
+
+module scalable_core #(
+    parameter NUM_NEURONS   = 64,
+    parameter DATA_WIDTH    = 16,
+    parameter NEURON_BITS   = 6,
+    parameter WEIGHT_BITS   = 12,
+    parameter THRESHOLD     = 16'sd1000,
+    parameter LEAK_RATE     = 16'sd3,
+    parameter RESTING_POT   = 16'sd0,
+    parameter REFRAC_CYCLES = 4,
+    parameter TRACE_MAX     = 8'd100,
+    parameter TRACE_DECAY   = 8'd3,
+    parameter LEARN_SHIFT   = 3
+)(
+    input  wire                    clk,
+    input  wire                    rst_n,
+    input  wire                    start,
+    input  wire                    learn_enable,
+
+    input  wire                    ext_valid,
+    input  wire [NEURON_BITS-1:0]  ext_neuron_id,
+    input  wire signed [DATA_WIDTH-1:0] ext_current,
+
+    input  wire                    inject_spike_valid,
+    input  wire [NEURON_BITS-1:0]  inject_spike_id,
+
+    input  wire                    weight_we,
+    input  wire [WEIGHT_BITS-1:0]  weight_addr,
+    input  wire signed [DATA_WIDTH-1:0] weight_data,
+
+    output reg                     timestep_done,
+    output reg                     spike_out_valid,
+    output reg  [NEURON_BITS-1:0]  spike_out_id,
+
+    output wire [3:0]              state_out,
+    output reg  [15:0]             total_spikes,
+    output reg  [15:0]             timestep_count
+);
+
+    localparam S_IDLE         = 4'd0;
+    localparam S_DELIVER_INIT = 4'd1;
+    localparam S_DELIVER_READ = 4'd2;
+    localparam S_DELIVER_ACC  = 4'd3;
+    localparam S_DELIVER_NEXT = 4'd4;
+    localparam S_UPDATE_INIT  = 4'd5;
+    localparam S_UPDATE_READ  = 4'd6;
+    localparam S_UPDATE_CALC  = 4'd7;
+    localparam S_UPDATE_WRITE = 4'd8;
+    localparam S_LEARN        = 4'd9;
+    localparam S_LEARN_WRITE  = 4'd10;
+    localparam S_DONE         = 4'd11;
+
+    reg [3:0] state;
+    assign state_out = state;
+
+    reg                    mem_we;
+    reg  [NEURON_BITS-1:0] mem_addr;
+    reg  signed [DATA_WIDTH-1:0] mem_wdata;
+    wire signed [DATA_WIDTH-1:0] mem_rdata;
+
+    sram #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(NEURON_BITS)) neuron_mem (
+        .clk(clk),
+        .we_a(mem_we), .addr_a(mem_addr), .wdata_a(mem_wdata), .rdata_a(mem_rdata),
+        .addr_b({NEURON_BITS{1'b0}}), .rdata_b()
+    );
+
+    reg                    ref_we;
+    reg  [NEURON_BITS-1:0] ref_addr;
+    reg  [3:0]             ref_wdata;
+    wire [3:0]             ref_rdata_raw;
+
+    sram #(.DATA_WIDTH(4), .ADDR_WIDTH(NEURON_BITS)) refrac_mem (
+        .clk(clk),
+        .we_a(ref_we), .addr_a(ref_addr), .wdata_a(ref_wdata), .rdata_a(ref_rdata_raw),
+        .addr_b({NEURON_BITS{1'b0}}), .rdata_b()
+    );
+
+    wire                   wt_we_internal;
+    reg                    wt_we_core;
+    reg  [WEIGHT_BITS-1:0] wt_addr_core;
+    reg  signed [DATA_WIDTH-1:0] wt_wdata_core;
+    wire signed [DATA_WIDTH-1:0] wt_rdata;
+
+    wire                   wt_we_mux   = (state == S_IDLE) ? weight_we : wt_we_core;
+    wire [WEIGHT_BITS-1:0] wt_addr_mux = (state == S_IDLE) ? weight_addr : wt_addr_core;
+    wire signed [DATA_WIDTH-1:0] wt_wdata_mux = (state == S_IDLE) ? weight_data : wt_wdata_core;
+
+    sram #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(WEIGHT_BITS)) weight_mem (
+        .clk(clk),
+        .we_a(wt_we_mux), .addr_a(wt_addr_mux), .wdata_a(wt_wdata_mux), .rdata_a(wt_rdata),
+        .addr_b({WEIGHT_BITS{1'b0}}), .rdata_b()
+    );
+
+    reg                    acc_we;
+    reg  [NEURON_BITS-1:0] acc_addr;
+    reg  signed [DATA_WIDTH-1:0] acc_wdata;
+    wire signed [DATA_WIDTH-1:0] acc_rdata;
+
+    sram #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(NEURON_BITS)) acc_mem (
+        .clk(clk),
+        .we_a(acc_we), .addr_a(acc_addr), .wdata_a(acc_wdata), .rdata_a(acc_rdata),
+        .addr_b({NEURON_BITS{1'b0}}), .rdata_b()
+    );
+
+    reg                    trace_we;
+    reg  [NEURON_BITS-1:0] trace_addr;
+    reg  [7:0]             trace_wdata;
+    wire [7:0]             trace_rdata;
+
+    sram #(.DATA_WIDTH(8), .ADDR_WIDTH(NEURON_BITS)) trace_mem (
+        .clk(clk),
+        .we_a(trace_we), .addr_a(trace_addr), .wdata_a(trace_wdata), .rdata_a(trace_rdata),
+        .addr_b({NEURON_BITS{1'b0}}), .rdata_b()
+    );
+
+    reg [NUM_NEURONS-1:0] spike_buf_prev;
+    reg [NUM_NEURONS-1:0] spike_buf_curr;
+    reg [NUM_NEURONS-1:0] spike_buf_temp;
+
+    reg [NEURON_BITS-1:0]       proc_neuron;
+    reg [NEURON_BITS:0]         deliver_src;
+    reg [NEURON_BITS:0]         deliver_dst;
+    reg signed [DATA_WIDTH-1:0] proc_potential;
+    reg [3:0]                   proc_refrac;
+    reg signed [DATA_WIDTH-1:0] proc_input;
+    reg                         proc_spiked;
+
+    reg [NEURON_BITS-1:0] spike_scan_idx;
+    reg                   found_spike;
+
+    wire ext_acc_we = ext_valid && (state == S_IDLE || state == S_DONE);
+
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n) begin
+            state          <= S_IDLE;
+            spike_buf_prev <= 0;
+            spike_buf_curr <= 0;
+            timestep_done  <= 0;
+            spike_out_valid <= 0;
+            total_spikes   <= 0;
+            timestep_count <= 0;
+            mem_we <= 0; ref_we <= 0; acc_we <= 0;
+            wt_we_core <= 0; trace_we <= 0;
+            proc_neuron <= 0;
+            deliver_src <= 0;
+            deliver_dst <= 0;
+            spike_scan_idx <= 0;
+        end else begin
+            mem_we <= 0;
+            ref_we <= 0;
+            acc_we <= 0;
+            wt_we_core <= 0;
+            trace_we <= 0;
+            timestep_done <= 0;
+            spike_out_valid <= 0;
+
+            if (inject_spike_valid) begin
+                spike_buf_curr[inject_spike_id] <= 1'b1;
+            end
+
+            if (ext_valid && state == S_IDLE) begin
+                acc_we    <= 1;
+                acc_addr  <= ext_neuron_id;
+                acc_wdata <= ext_current;
+            end
+
+            case (state)
+                S_IDLE: begin
+                    if (start) begin
+                        state       <= S_DELIVER_INIT;
+                        deliver_src <= 0;
+                        deliver_dst <= 0;
+                    end
+                end
+
+                S_DELIVER_INIT: begin
+                    if (deliver_src < NUM_NEURONS) begin
+                        if (spike_buf_prev[deliver_src[NEURON_BITS-1:0]]) begin
+                            deliver_dst <= 0;
+                            wt_addr_core <= {deliver_src[NEURON_BITS-1:0], {NEURON_BITS{1'b0}}};
+                            acc_addr <= 0;
+                            state <= S_DELIVER_READ;
+                        end else begin
+                            deliver_src <= deliver_src + 1;
+                        end
+                    end else begin
+                        state       <= S_UPDATE_INIT;
+                        proc_neuron <= 0;
+                    end
+                end
+
+                S_DELIVER_READ: begin
+                    wt_addr_core <= {deliver_src[NEURON_BITS-1:0], deliver_dst[NEURON_BITS-1:0]};
+                    acc_addr     <= deliver_dst[NEURON_BITS-1:0];
+                    state        <= S_DELIVER_ACC;
+                end
+
+                S_DELIVER_ACC: begin
+                    if (deliver_src[NEURON_BITS-1:0] != deliver_dst[NEURON_BITS-1:0]) begin
+                        acc_we    <= 1;
+                        acc_addr  <= deliver_dst[NEURON_BITS-1:0];
+                        acc_wdata <= acc_rdata + wt_rdata;
+                    end
+                    state <= S_DELIVER_NEXT;
+                end
+
+                S_DELIVER_NEXT: begin
+                    if (deliver_dst < NUM_NEURONS - 1) begin
+                        deliver_dst  <= deliver_dst + 1;
+                        wt_addr_core <= {deliver_src[NEURON_BITS-1:0], deliver_dst[NEURON_BITS-1:0] + {{(NEURON_BITS-1){1'b0}}, 1'b1}};
+                        acc_addr     <= deliver_dst[NEURON_BITS-1:0] + 1;
+                        state        <= S_DELIVER_READ;
+                    end else begin
+                        deliver_src <= deliver_src + 1;
+                        state       <= S_DELIVER_INIT;
+                    end
+                end
+
+                S_UPDATE_INIT: begin
+                    mem_addr  <= proc_neuron;
+                    ref_addr  <= proc_neuron;
+                    acc_addr  <= proc_neuron;
+                    trace_addr <= proc_neuron;
+                    state     <= S_UPDATE_READ;
+                end
+
+                S_UPDATE_READ: begin
+                    mem_addr   <= proc_neuron;
+                    ref_addr   <= proc_neuron;
+                    acc_addr   <= proc_neuron;
+                    trace_addr <= proc_neuron;
+                    state      <= S_UPDATE_CALC;
+                end
+
+                S_UPDATE_CALC: begin
+                    proc_potential <= mem_rdata;
+                    proc_refrac   <= ref_rdata_raw;
+                    proc_input    <= acc_rdata;
+                    proc_spiked   <= 0;
+
+                    if (ref_rdata_raw > 0) begin
+                        proc_potential <= RESTING_POT;
+                        proc_refrac   <= ref_rdata_raw - 1;
+                        if (trace_rdata > TRACE_DECAY)
+                            trace_wdata <= trace_rdata - TRACE_DECAY;
+                        else
+                            trace_wdata <= 0;
+                    end else begin
+                        if (mem_rdata + acc_rdata - LEAK_RATE >= THRESHOLD) begin
+                            proc_potential <= RESTING_POT;
+                            proc_refrac   <= REFRAC_CYCLES[3:0];
+                            proc_spiked   <= 1;
+                            trace_wdata   <= TRACE_MAX;
+                        end else if (mem_rdata + acc_rdata > LEAK_RATE) begin
+                            proc_potential <= mem_rdata + acc_rdata - LEAK_RATE;
+                            if (trace_rdata > TRACE_DECAY)
+                                trace_wdata <= trace_rdata - TRACE_DECAY;
+                            else
+                                trace_wdata <= 0;
+                        end else begin
+                            proc_potential <= RESTING_POT;
+                            if (trace_rdata > TRACE_DECAY)
+                                trace_wdata <= trace_rdata - TRACE_DECAY;
+                            else
+                                trace_wdata <= 0;
+                        end
+                    end
+
+                    state <= S_UPDATE_WRITE;
+                end
+
+                S_UPDATE_WRITE: begin
+                    mem_we    <= 1;
+                    mem_addr  <= proc_neuron;
+                    mem_wdata <= proc_potential;
+
+                    ref_we    <= 1;
+                    ref_addr  <= proc_neuron;
+                    ref_wdata <= proc_refrac;
+
+                    acc_we    <= 1;
+                    acc_addr  <= proc_neuron;
+                    acc_wdata <= 0;
+
+                    trace_we   <= 1;
+                    trace_addr <= proc_neuron;
+
+                    if (proc_spiked) begin
+                        spike_buf_curr[proc_neuron] <= 1'b1;
+                        spike_out_valid <= 1;
+                        spike_out_id    <= proc_neuron;
+                        total_spikes    <= total_spikes + 1;
+                    end
+
+                    if (proc_neuron < NUM_NEURONS - 1) begin
+                        proc_neuron <= proc_neuron + 1;
+                        state       <= S_UPDATE_INIT;
+                    end else begin
+                        if (learn_enable)
+                            state <= S_LEARN;
+                        else
+                            state <= S_DONE;
+                        deliver_src <= 0;
+                        deliver_dst <= 0;
+                    end
+                end
+
+                S_LEARN: begin
+                    if (deliver_src < NUM_NEURONS) begin
+                        if (spike_buf_curr[deliver_src[NEURON_BITS-1:0]]) begin
+                            if (deliver_dst < NUM_NEURONS) begin
+                                if (deliver_dst[NEURON_BITS-1:0] != deliver_src[NEURON_BITS-1:0]) begin
+                                    wt_addr_core <= {deliver_dst[NEURON_BITS-1:0], deliver_src[NEURON_BITS-1:0]};
+                                    trace_addr   <= deliver_dst[NEURON_BITS-1:0];
+                                    state        <= S_LEARN_WRITE;
+                                end else begin
+                                    deliver_dst <= deliver_dst + 1;
+                                end
+                            end else begin
+                                deliver_src <= deliver_src + 1;
+                                deliver_dst <= 0;
+                            end
+                        end else begin
+                            deliver_src <= deliver_src + 1;
+                            deliver_dst <= 0;
+                        end
+                    end else begin
+                        state <= S_DONE;
+                    end
+                end
+
+                S_LEARN_WRITE: begin
+                    if (trace_rdata > 0) begin
+                        wt_we_core   <= 1;
+                        wt_addr_core <= {deliver_dst[NEURON_BITS-1:0], deliver_src[NEURON_BITS-1:0]};
+                        if (wt_rdata + (trace_rdata >> LEARN_SHIFT) > $signed(THRESHOLD))
+                            wt_wdata_core <= THRESHOLD;
+                        else
+                            wt_wdata_core <= wt_rdata + (trace_rdata >> LEARN_SHIFT);
+                    end
+
+                    deliver_dst <= deliver_dst + 1;
+                    state       <= S_LEARN;
+                end
+
+                S_DONE: begin
+                    spike_buf_prev <= spike_buf_curr;
+                    spike_buf_curr <= 0;
+
+                    timestep_done  <= 1;
+                    timestep_count <= timestep_count + 1;
+                    proc_neuron    <= 0;
+                    deliver_src    <= 0;
+
+                    state <= S_IDLE;
+                end
+
+                default: state <= S_IDLE;
+            endcase
+        end
+    end
+
+endmodule

rtl/spike_fifo.v

@@ -0,0 +1,70 @@
+// ============================================================================
+// Spike FIFO
+// ============================================================================
+//
+// Copyright 2026 Henry Arthur Shulayev Barnes / Catalyst Neuromorphic Ltd
+// Company No. 17054540 — UK Patent Application No. 2602902.6
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// ============================================================================
+
+module spike_fifo #(
+    parameter ID_WIDTH = 8,
+    parameter DEPTH    = 64,
+    parameter PTR_BITS = 6
+)(
+    input  wire                clk,
+    input  wire                rst_n,
+    input  wire                clear,
+
+    input  wire                push,
+    input  wire [ID_WIDTH-1:0] push_data,
+
+    input  wire                pop,
+    output wire [ID_WIDTH-1:0] pop_data,
+
+    output wire                empty,
+    output wire                full,
+    output wire [PTR_BITS:0]   count
+);
+
+    reg [ID_WIDTH-1:0] mem [0:DEPTH-1];
+
+    reg [PTR_BITS:0] wr_ptr;
+    reg [PTR_BITS:0] rd_ptr;
+
+    assign count = wr_ptr - rd_ptr;
+    assign empty = (wr_ptr == rd_ptr);
+    assign full  = (count == DEPTH);
+
+    assign pop_data = mem[rd_ptr[PTR_BITS-1:0]];
+
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n) begin
+            wr_ptr <= 0;
+            rd_ptr <= 0;
+        end else if (clear) begin
+            wr_ptr <= 0;
+            rd_ptr <= 0;
+        end else begin
+            if (push && !full) begin
+                mem[wr_ptr[PTR_BITS-1:0]] <= push_data;
+                wr_ptr <= wr_ptr + 1;
+            end
+            if (pop && !empty) begin
+                rd_ptr <= rd_ptr + 1;
+            end
+        end
+    end
+
+endmodule

rtl/sram.v

@@ -0,0 +1,56 @@
+// ============================================================================
+// SRAM
+// ============================================================================
+//
+// Copyright 2026 Henry Arthur Shulayev Barnes / Catalyst Neuromorphic Ltd
+// Company No. 17054540 — UK Patent Application No. 2602902.6
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// ============================================================================
+
+module sram #(
+    parameter DATA_WIDTH = 16,
+    parameter ADDR_WIDTH = 6,
+    parameter DEPTH      = (1 << ADDR_WIDTH),
+    parameter [DATA_WIDTH-1:0] INIT_VALUE = {DATA_WIDTH{1'b0}}
+)(
+    input  wire                    clk,
+
+    input  wire                    we_a,
+    input  wire [ADDR_WIDTH-1:0]   addr_a,
+    input  wire [DATA_WIDTH-1:0]   wdata_a,
+    output reg  [DATA_WIDTH-1:0]   rdata_a,
+
+    input  wire [ADDR_WIDTH-1:0]   addr_b,
+    output reg  [DATA_WIDTH-1:0]   rdata_b
+);
+
+    reg [DATA_WIDTH-1:0] mem [0:DEPTH-1];
+
+    always @(posedge clk) begin
+        if (we_a)
+            mem[addr_a] <= wdata_a;
+        rdata_a <= mem[addr_a];
+    end
+
+    always @(posedge clk) begin
+        rdata_b <= mem[addr_b];
+    end
+
+    integer i;
+    initial begin
+        for (i = 0; i < DEPTH; i = i + 1)
+            mem[i] = INIT_VALUE;
+    end
+
+endmodule

rtl/stdp_synapse.v

@@ -0,0 +1,102 @@
+// ============================================================================
+// STDP Synapse
+// ============================================================================
+//
+// Copyright 2026 Henry Arthur Shulayev Barnes / Catalyst Neuromorphic Ltd
+// Company No. 17054540 — UK Patent Application No. 2602902.6
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// ============================================================================
+
+module stdp_synapse #(
+    parameter DATA_WIDTH   = 16,
+    parameter TRACE_WIDTH  = 8,
+    parameter TRACE_MAX    = 8'd127,
+    parameter TRACE_DECAY  = 8'd4,
+    parameter LEARN_RATE   = 8'd4,
+    parameter WEIGHT_MAX   = 16'd800,
+    parameter WEIGHT_MIN   = -16'sd800,
+    parameter WEIGHT_INIT  = 16'd0
+)(
+    input  wire                          clk,
+    input  wire                          rst_n,
+    input  wire                          learn_enable,
+    input  wire                          pre_spike,
+    input  wire                          post_spike,
+    output reg  signed [DATA_WIDTH-1:0]  weight,
+    output reg  signed [DATA_WIDTH-1:0]  post_current,
+    output wire [TRACE_WIDTH-1:0]        pre_trace_out,
+    output wire [TRACE_WIDTH-1:0]        post_trace_out
+);
+
+    reg [TRACE_WIDTH-1:0] pre_trace;
+    reg [TRACE_WIDTH-1:0] post_trace;
+
+    assign pre_trace_out  = pre_trace;
+    assign post_trace_out = post_trace;
+
+    wire signed [DATA_WIDTH-1:0] ltp_delta;
+    wire signed [DATA_WIDTH-1:0] ltd_delta;
+
+    assign ltp_delta = {{(DATA_WIDTH-TRACE_WIDTH){1'b0}}, pre_trace} >>> LEARN_RATE;
+    assign ltd_delta = {{(DATA_WIDTH-TRACE_WIDTH){1'b0}}, post_trace} >>> LEARN_RATE;
+
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n) begin
+            pre_trace    <= 0;
+            post_trace   <= 0;
+            weight       <= WEIGHT_INIT;
+            post_current <= 0;
+
+        end else begin
+            if (pre_spike) begin
+                pre_trace <= TRACE_MAX;
+            end else if (pre_trace > TRACE_DECAY) begin
+                pre_trace <= pre_trace - TRACE_DECAY;
+            end else begin
+                pre_trace <= 0;
+            end
+
+            if (post_spike) begin
+                post_trace <= TRACE_MAX;
+            end else if (post_trace > TRACE_DECAY) begin
+                post_trace <= post_trace - TRACE_DECAY;
+            end else begin
+                post_trace <= 0;
+            end
+
+            if (learn_enable) begin
+                if (post_spike && pre_trace > 0) begin
+                    if (weight + ltp_delta > WEIGHT_MAX)
+                        weight <= WEIGHT_MAX;
+                    else
+                        weight <= weight + ltp_delta;
+                end
+
+                if (pre_spike && post_trace > 0) begin
+                    if (weight - ltd_delta < WEIGHT_MIN)
+                        weight <= WEIGHT_MIN;
+                    else
+                        weight <= weight - ltd_delta;
+                end
+            end
+
+            if (pre_spike) begin
+                post_current <= weight;
+            end else begin
+                post_current <= 0;
+            end
+        end
+    end
+
+endmodule

rtl/synapse.v

@@ -0,0 +1,43 @@
+// ============================================================================
+// Synapse
+// ============================================================================
+//
+// Copyright 2026 Henry Arthur Shulayev Barnes / Catalyst Neuromorphic Ltd
+// Company No. 17054540 — UK Patent Application No. 2602902.6
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// ============================================================================
+
+module synapse #(
+    parameter DATA_WIDTH = 16
+)(
+    input  wire                          clk,
+    input  wire                          rst_n,
+    input  wire                          pre_spike,
+    input  wire signed [DATA_WIDTH-1:0]  weight,
+    output reg  signed [DATA_WIDTH-1:0]  post_current
+);
+
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n) begin
+            post_current <= 0;
+        end else begin
+            if (pre_spike) begin
+                post_current <= weight;
+            end else begin
+                post_current <= 0;
+            end
+        end
+    end
+
+endmodule

rtl/sync_tree.v

@@ -0,0 +1,38 @@
+// ============================================================================
+// Sync Tree
+// ============================================================================
+//
+// Copyright 2026 Henry Arthur Shulayev Barnes / Catalyst Neuromorphic Ltd
+// Company No. 17054540 — UK Patent Application No. 2602902.6
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// ============================================================================
+
+`timescale 1ns/1ps
+
+module sync_tree #(
+    parameter NUM_LEAVES = 4
+)(
+    input  wire                  clk,
+    input  wire                  rst_n,
+    input  wire [NUM_LEAVES-1:0] leaf_done,
+    output wire                  all_done,
+    input  wire                  root_start,
+    output wire [NUM_LEAVES-1:0] leaf_start
+);
+
+    assign all_done = &leaf_done;
+
+    assign leaf_start = {NUM_LEAVES{root_start}};
+
+endmodule

rtl/uart_rx.v

@@ -0,0 +1,107 @@
+// ============================================================================
+// UART Receiver
+// ============================================================================
+//
+// Copyright 2026 Henry Arthur Shulayev Barnes / Catalyst Neuromorphic Ltd
+// Company No. 17054540 — UK Patent Application No. 2602902.6
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// ============================================================================
+
+module uart_rx #(
+    parameter CLK_FREQ = 100_000_000,
+    parameter BAUD     = 115200
+)(
+    input  wire       clk,
+    input  wire       rst_n,
+    input  wire       rx,
+    output reg  [7:0] data,
+    output reg        valid
+);
+
+    localparam CLKS_PER_BIT = CLK_FREQ / BAUD;
+    localparam HALF_BIT     = CLKS_PER_BIT / 2;
+
+    localparam S_IDLE  = 2'd0;
+    localparam S_START = 2'd1;
+    localparam S_DATA  = 2'd2;
+    localparam S_STOP  = 2'd3;
+
+    reg [1:0]  state;
+    reg [15:0] clk_cnt;
+    reg [2:0]  bit_idx;
+    reg [7:0]  shift;
+    reg        rx_s1, rx_s2;
+
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n) begin
+            rx_s1 <= 1;
+            rx_s2 <= 1;
+        end else begin
+            rx_s1 <= rx;
+            rx_s2 <= rx_s1;
+        end
+    end
+
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n) begin
+            state   <= S_IDLE;
+            valid   <= 0;
+            clk_cnt <= 0;
+            bit_idx <= 0;
+            shift   <= 0;
+            data    <= 0;
+        end else begin
+            valid <= 0;
+            case (state)
+                S_IDLE: begin
+                    if (!rx_s2) begin
+                        clk_cnt <= 0;
+                        state   <= S_START;
+                    end
+                end
+                S_START: begin
+                    if (clk_cnt == HALF_BIT - 1) begin
+                        if (!rx_s2) begin
+                            clk_cnt <= 0;
+                            bit_idx <= 0;
+                            state   <= S_DATA;
+                        end else
+                            state <= S_IDLE;
+                    end else
+                        clk_cnt <= clk_cnt + 1;
+                end
+                S_DATA: begin
+                    if (clk_cnt == CLKS_PER_BIT - 1) begin
+                        clk_cnt <= 0;
+                        shift   <= {rx_s2, shift[7:1]};
+                        if (bit_idx == 7)
+                            state <= S_STOP;
+                        else
+                            bit_idx <= bit_idx + 1;
+                    end else
+                        clk_cnt <= clk_cnt + 1;
+                end
+                S_STOP: begin
+                    if (clk_cnt == CLKS_PER_BIT - 1) begin
+                        data  <= shift;
+                        valid <= 1;
+                        state <= S_IDLE;
+                    end else
+                        clk_cnt <= clk_cnt + 1;
+                end
+            endcase
+        end
+    end
+
+endmodule

rtl/uart_tx.v

@@ -0,0 +1,96 @@
+// ============================================================================
+// UART Transmitter
+// ============================================================================
+//
+// Copyright 2026 Henry Arthur Shulayev Barnes / Catalyst Neuromorphic Ltd
+// Company No. 17054540 — UK Patent Application No. 2602902.6
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// ============================================================================
+
+module uart_tx #(
+    parameter CLK_FREQ = 100_000_000,
+    parameter BAUD     = 115200
+)(
+    input  wire       clk,
+    input  wire       rst_n,
+    input  wire [7:0] data,
+    input  wire       valid,
+    output reg        tx,
+    output wire       ready
+);
+
+    localparam CLKS_PER_BIT = CLK_FREQ / BAUD;
+
+    localparam S_IDLE  = 2'd0;
+    localparam S_START = 2'd1;
+    localparam S_DATA  = 2'd2;
+    localparam S_STOP  = 2'd3;
+
+    reg [1:0]  state;
+    reg [15:0] clk_cnt;
+    reg [2:0]  bit_idx;
+    reg [7:0]  shift;
+
+    assign ready = (state == S_IDLE);
+
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n) begin
+            state   <= S_IDLE;
+            tx      <= 1;
+            clk_cnt <= 0;
+            bit_idx <= 0;
+            shift   <= 0;
+        end else begin
+            case (state)
+                S_IDLE: begin
+                    tx <= 1;
+                    if (valid) begin
+                        shift   <= data;
+                        state   <= S_START;
+                        clk_cnt <= 0;
+                    end
+                end
+                S_START: begin
+                    tx <= 0;
+                    if (clk_cnt == CLKS_PER_BIT - 1) begin
+                        clk_cnt <= 0;
+                        bit_idx <= 0;
+                        state   <= S_DATA;
+                    end else
+                        clk_cnt <= clk_cnt + 1;
+                end
+                S_DATA: begin
+                    tx <= shift[0];
+                    if (clk_cnt == CLKS_PER_BIT - 1) begin
+                        clk_cnt <= 0;
+                        shift   <= {1'b0, shift[7:1]};
+                        if (bit_idx == 7)
+                            state <= S_STOP;
+                        else
+                            bit_idx <= bit_idx + 1;
+                    end else
+                        clk_cnt <= clk_cnt + 1;
+                end
+                S_STOP: begin
+                    tx <= 1;
+                    if (clk_cnt == CLKS_PER_BIT - 1)
+                        state <= S_IDLE;
+                    else
+                        clk_cnt <= clk_cnt + 1;
+                end
+            endcase
+        end
+    end
+
+endmodule

run_regression.sh

@@ -0,0 +1,17 @@
+#!/bin/bash
+cd /mnt/c/Users/mrwab/neuromorphic-chip
+
+RTL="rtl/sram.v rtl/spike_fifo.v rtl/uart_tx.v rtl/uart_rx.v rtl/chip_link.v rtl/scalable_core_v2.v rtl/neuromorphic_mesh.v rtl/host_interface.v rtl/neuromorphic_top.v rtl/sync_tree.v rtl/async_router.v rtl/async_noc_mesh.v rtl/rv32i_core.v rtl/mmio_bridge.v rtl/multi_chip_router.v rtl/rv32im_cluster.v"
+
+for tb in tb/tb_p13a.v tb/tb_p15_traces.v tb/tb_p17_delays.v tb/tb_p19_microcode.v tb/tb_p20_hierarchical.v tb/tb_p21a_dendrites.v tb/tb_p21b_observe.v tb/tb_p21c_power.v tb/tb_p21d_learning.v tb/tb_p21e_chiplink.v tb/tb_p22a_cuba.v tb/tb_p22c_learning.v tb/tb_p22b_compartments.v tb/tb_p22d_axontypes.v tb/tb_p22e_noc.v tb/tb_p22f_riscv.v tb/tb_p22g_multichip.v tb/tb_p22h_power.v tb/tb_p23a_neuron_arith.v tb/tb_p23b_comp_synapse.v tb/tb_p23c_scale.v tb/tb_p23d_riscv.v tb/tb_p24_final.v tb/tb_p25_final.v tb/tb_stress.v; do
+    echo "=== $tb ==="
+    # Extract module name from filename (e.g., tb/tb_p13a.v -> tb_p13a)
+    tb_mod=$(basename "$tb" .v)
+    iverilog -g2012 -DSIMULATION -s "$tb_mod" -o test_reg.vvp $RTL $tb 2>&1
+    if [ $? -eq 0 ]; then
+        timeout 120 vvp test_reg.vvp 2>&1 | grep -E "PASSED|FAILED|RESULTS|passed"
+    else
+        echo "COMPILE ERROR"
+    fi
+    echo ""
+done