// ============================================================================
// Synapse
// ============================================================================
//
// Copyright 2026 Henry Arthur Shulayev Barnes / Catalyst Neuromorphic Ltd
// Company No. 17054540 — UK Patent Application No. 2602902.6
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
//     http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// ============================================================================

module synapse #(
    parameter DATA_WIDTH = 16
)(
    input  wire                          clk,
    input  wire                          rst_n,
    input  wire                          pre_spike,
    input  wire signed [DATA_WIDTH-1:0]  weight,
    output reg  signed [DATA_WIDTH-1:0]  post_current
);

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            post_current <= 0;
        end else begin
            if (pre_spike) begin
                post_current <= weight;
            end else begin
                post_current <= 0;
            end
        end
    end

endmodule