# 🚀 Quick Test Command for Single Training Sample

## ✅ Updated Command (With Fixes Applied)

```bash
cd /workspace/ftt/codellama-migration && source /venv/main/bin/activate && python3 test_single_training_sample.py
```

**This will:**
- Load the first training sample
- Test with temperatures: 0.1, 0.2, 0.3
- Show expected vs generated output
- Help you find the best temperature

---

## 🔧 Manual Test Command (Custom Temperature)

```bash
cd /workspace/ftt/codellama-migration
source /venv/main/bin/activate

# Extract sample #1 instruction
INSTRUCTION=$(sed -n '1p' datasets/processed/split/train.jsonl | python3 -c "import sys, json; print(json.load(sys.stdin)['instruction'])")

# Test with optimized parameters
python3 scripts/inference/inference_codellama.py \
    --mode local \
    --model-path training-outputs/codellama-fifo-v1 \
    --prompt "$INSTRUCTION" \
    --max-new-tokens 1000 \
    --temperature 0.1
```

---

## 🎯 Key Hyperparameter Changes Made

| Parameter | Old | New | Impact |
|-----------|-----|-----|--------|
| **Repetition Penalty** | 1.1 | **1.2** | ✅ Prevents repetitive text |
| **Prompt Format** | No EOS | **+ EOS token** | ✅ Matches training format |
| **Temperature** | 0.3 | **0.1 (recommended)** | ✅ More deterministic |
| **Response Extraction** | Full decode | **New tokens only** | ✅ Cleaner output |

---

## 📊 Expected Results

With these changes, you should see:
- ✅ **Verilog code generation** (not text notes)
- ✅ **Complete modules** (module ... endmodule)
- ✅ **No repetitive "Note:" statements**
- ✅ **Better match with training data**

---

## 🔍 If Still Getting Text Instead of Code

Try these in order:

1. **Lower temperature to 0.05:**
   ```bash
   --temperature 0.05
   ```

2. **Increase repetition penalty to 1.3:**
   (Edit inference script or add as parameter)

3. **Check prompt format:**
   - Ensure instruction matches training data exactly
   - No extra formatting or wrappers

4. **Verify training data format:**
   - Should be: `instruction + EOS + response + EOS`
   - Response should start with ```verilog

---

**Test and let me know the results!**