Instruction:
You are Elinnos RTL Code Generator v1.0, a specialized Verilog/SystemVerilog code generation agent. Your role: Generate clean, synthesizable RTL code for hardware design tasks. Output ONLY functional RTL code with no $display, assertions, comments, or debug statements.

Generate a 16-bit synchronous FIFO with depth 128 using AXI-like write_valid/write_ready handshake and read_valid/read_ready handshake.

Response:
```verilog
module sync_fifo_16b_128d_axi (
  input clk,
  input rst,
  input write_valid,
  output write_ready,
  input [15:0] write_data,
  output read_valid,
  input read_ready,
  output [15:0] read_data
);

  reg [15:0] fifo_mem [127:0];
  reg [6:0] write_ptr, read_ptr;
  reg [7:0] count;

  assign write_ready = (count < 128);
  assign read_valid = (count > 0);
  assign read_data = fifo_mem[read_ptr];

  always @(posedge clk) begin
    if (rst) begin
      write_ptr <= 7'b0;
      read_ptr <= 7'b0;
      count <= 8'b0;
    end else begin
      case ({write_valid && write_ready, read_valid && read_ready})
        2'b10: begin
          fifo_mem[write_ptr] <= write_data;
          write_ptr <= write_ptr + 1;
          count <= count + 1;
        end
        2'b01: begin
          read_ptr <= read_ptr + 1;
          count <= count - 1;
        end
        2'b11: begin
          fifo_mem[write_ptr] <= write_data;
          write_ptr <= write_ptr + 1;
          read_ptr <= read_ptr + 1;
        end
      endcase
    end
  end

endmodule
```


Instruction:
You are Elinnos RTL Code Generator v1.0, a specialized Verilog/SystemVerilog code generation agent. Your role: Generate clean, synthesizable RTL code for hardware design tasks. Output ONLY functional RTL code with no $display, assertions, comments, or debug statements.

Generate a synchronous FIFO with 32-bit data width, depth 4, write_enable, read_enable, full flag, empty flag.

Response:
```verilog
module sync_fifo_32b_4d (
  input clk,
  input rst,
  input write_en,
  input read_en,
  input [31:0] write_data,
  output [31:0] read_data
);

  reg [31:0] fifo_mem [3:0];
  reg [1:0] write_ptr, read_ptr;
  reg [2:0] count;

  assign full = (count == 4);
  assign empty = (count == 0);
  assign read_data = fifo_mem[read_ptr];

  always @(posedge clk) begin
    if (rst) begin
      write_ptr <= 2'b0;
      read_ptr <= 2'b0;
      count <= 3'b0;
    end else begin
      if (write_en && ~full) begin
        fifo_mem[write_ptr] <= write_data;
        write_ptr <= write_ptr + 1;
        count <= count + 1;
      end
      if (read_en && ~empty) begin
        read_ptr <= read_ptr + 1;
        count <= count - 1;
      end
    end
  end

endmodule
```


Instruction:
You are Elinnos RTL Code Generator v1.0, a specialized Verilog/SystemVerilog code generation agent. Your role: Generate clean, synthesizable RTL code for hardware design tasks. Output ONLY functional RTL code with no $display, assertions, comments, or debug statements.

Generate a synchronous FIFO with 64-bit data width, depth 8, write_enable, read_enable, full flag, empty flag, and occupancy output showing number of valid entries (0 to 8).

Response:
```verilog
module sync_fifo_64b_8d (
  input clk,
  input rst,
  input write_en,
  input read_en,
  input [63:0] write_data,
  output [63:0] read_data,
  output [2:0] occupancy
);

  reg [63:0] fifo_mem [7:0];
  reg [2:0] write_ptr, read_ptr;
  reg [3:0] count;

  assign full = (count == 8);
  assign empty = (count == 0);
  assign read_data = fifo_mem[read_ptr];
    assign occupancy = count[2:0];

  always @(posedge clk) begin
    if (rst) begin
      write_ptr <= 3'b0;
      read_ptr <= 3'b0;
      count <= 4'b0;
    end else begin
      if (write_en && ~full) begin
        fifo_mem[write_ptr] <= write_data;
        write_ptr <= write_ptr + 1;
        count <= count + 1;
      end
      if (read_en && ~empty) begin
        read_ptr <= read_ptr + 1;
        count <= count - 1;
      end
    end
  end

endmodule
```


Instruction:
You are Elinnos RTL Code Generator v1.0, a specialized Verilog/SystemVerilog code generation agent. Your role: Generate clean, synthesizable RTL code for hardware design tasks. Output ONLY functional RTL code with no $display, assertions, comments, or debug statements.

Generate a synchronous FIFO with 8-bit data width, depth 8, write_enable, read_enable, full flag, empty flag and include clear signal independent of reset.

Response:
```verilog
module sync_fifo_8b_8d (
  input clk,
  input rst,
  input write_en,
  input read_en,
  input [7:0] write_data,
  output [7:0] read_data,
  input clear
);

  reg [7:0] fifo_mem [7:0];
  reg [2:0] write_ptr, read_ptr;
  reg [3:0] count;

  assign full = (count == 8);
  assign empty = (count == 0);
  assign read_data = fifo_mem[read_ptr];

  always @(posedge clk) begin
    if (rst || clear) begin
      write_ptr <= 3'b0;
      read_ptr <= 3'b0;
      count <= 4'b0;
    end else begin
      if (write_en && ~full) begin
        fifo_mem[write_ptr] <= write_data;
        write_ptr <= write_ptr + 1;
        count <= count + 1;
      end
      if (read_en && ~empty) begin
        read_ptr <= read_ptr + 1;
        count <= count - 1;
      end
    end
  end

endmodule
```


Instruction:
You are Elinnos RTL Code Generator v1.0, a specialized Verilog/SystemVerilog code generation agent. Your role: Generate clean, synthesizable RTL code for hardware design tasks. Output ONLY functional RTL code with no $display, assertions, comments, or debug statements.

Generate a synchronous FIFO with 16-bit data width, depth 16, write_enable, read_enable, full flag, empty flag, write_err flag (pulses if write when full), and read_err flag (pulses if read when empty).

Response:
```verilog
module sync_fifo_16b_16d (
  input clk,
  input rst,
  input write_en,
  input read_en,
  input [15:0] write_data,
  output [15:0] read_data,
  output write_err,
  output read_err
);

  reg [15:0] fifo_mem [15:0];
  reg [3:0] write_ptr, read_ptr;
  reg [4:0] count;

  assign full = (count == 16);
  assign empty = (count == 0);
  assign read_data = fifo_mem[read_ptr];
    assign write_err = write_en && full;
  assign read_err = read_en && empty;

  always @(posedge clk) begin
    if (rst) begin
      write_ptr <= 4'b0;
      read_ptr <= 4'b0;
      count <= 5'b0;
    end else begin
      if (write_en && ~full) begin
        fifo_mem[write_ptr] <= write_data;
        write_ptr <= write_ptr + 1;
        count <= count + 1;
      end
      if (read_en && ~empty) begin
        read_ptr <= read_ptr + 1;
        count <= count - 1;
      end
    end
  end

endmodule
```


Instruction:
You are Elinnos RTL Code Generator v1.0, a specialized Verilog/SystemVerilog code generation agent. Your role: Generate clean, synthesizable RTL code for hardware design tasks. Output ONLY functional RTL code with no $display, assertions, comments, or debug statements.

Generate a synchronous FIFO with 32-bit data width, depth 32, write_enable, read_enable, full flag, empty flag, write_addr output, and read_addr output for debugging.

Response:
```verilog
module sync_fifo_32b_32d (
  input clk,
  input rst,
  input write_en,
  input read_en,
  input [31:0] write_data,
  output [31:0] read_data,
  output [4:0] write_addr,
  output [4:0] read_addr
);

  reg [31:0] fifo_mem [31:0];
  reg [4:0] write_ptr, read_ptr;
  reg [5:0] count;

  assign full = (count == 32);
  assign empty = (count == 0);
  assign read_data = fifo_mem[read_ptr];
    assign write_addr = write_ptr;
  assign read_addr = read_ptr;

  always @(posedge clk) begin
    if (rst) begin
      write_ptr <= 5'b0;
      read_ptr <= 5'b0;
      count <= 6'b0;
    end else begin
      if (write_en && ~full) begin
        fifo_mem[write_ptr] <= write_data;
        write_ptr <= write_ptr + 1;
        count <= count + 1;
      end
      if (read_en && ~empty) begin
        read_ptr <= read_ptr + 1;
        count <= count - 1;
      end
    end
  end

endmodule
```


Instruction:
You are Elinnos RTL Code Generator v1.0, a specialized Verilog/SystemVerilog code generation agent. Your role: Generate clean, synthesizable RTL code for hardware design tasks. Output ONLY functional RTL code with no $display, assertions, comments, or debug statements.

Generate a synchronous FIFO with 12-bit data width, depth 24, write_enable, read_enable, full flag, empty flag, and occupancy output showing number of valid entries (0 to 24).

Response:
```verilog
module sync_fifo_12b_24d (
  input clk,
  input rst,
  input write_en,
  input read_en,
  input [11:0] write_data,
  output [11:0] read_data,
  output [4:0] occupancy
);

  reg [11:0] fifo_mem [23:0];
  reg [4:0] write_ptr, read_ptr;
  reg [5:0] count;

  assign full = (count == 24);
  assign empty = (count == 0);
  assign read_data = fifo_mem[read_ptr];
    assign occupancy = count[4:0];

  always @(posedge clk) begin
    if (rst) begin
      write_ptr <= 5'b0;
      read_ptr <= 5'b0;
      count <= 6'b0;
    end else begin
      if (write_en && ~full) begin
        fifo_mem[write_ptr] <= write_data;
        write_ptr <= write_ptr + 1;
        count <= count + 1;
      end
      if (read_en && ~empty) begin
        read_ptr <= read_ptr + 1;
        count <= count - 1;
      end
    end
  end

endmodule
```


Instruction:
You are Elinnos RTL Code Generator v1.0, a specialized Verilog/SystemVerilog code generation agent. Your role: Generate clean, synthesizable RTL code for hardware design tasks. Output ONLY functional RTL code with no $display, assertions, comments, or debug statements.

Generate a synchronous FIFO with 20-bit data width, depth 48, write_enable, read_enable, full flag, empty flag with threshold output indicating if occupancy exceeds 36.

Response:
```verilog
module sync_fifo_20b_48d (
  input clk,
  input rst,
  input write_en,
  input read_en,
  input [19:0] write_data,
  output [19:0] read_data,
  output threshold_high
);

  reg [19:0] fifo_mem [47:0];
  reg [5:0] write_ptr, read_ptr;
  reg [6:0] count;

  assign full = (count == 48);
  assign empty = (count == 0);
  assign read_data = fifo_mem[read_ptr];
    assign threshold_high = (count > 36);

  always @(posedge clk) begin
    if (rst) begin
      write_ptr <= 6'b0;
      read_ptr <= 6'b0;
      count <= 7'b0;
    end else begin
      if (write_en && ~full) begin
        fifo_mem[write_ptr] <= write_data;
        write_ptr <= write_ptr + 1;
        count <= count + 1;
      end
      if (read_en && ~empty) begin
        read_ptr <= read_ptr + 1;
        count <= count - 1;
      end
    end
  end

endmodule
```


Instruction:
You are Elinnos RTL Code Generator v1.0, a specialized Verilog/SystemVerilog code generation agent. Your role: Generate clean, synthesizable RTL code for hardware design tasks. Output ONLY functional RTL code with no $display, assertions, comments, or debug statements.

Generate a synchronous FIFO with 24-bit data width, depth 96, write_enable, read_enable, full flag, empty flag, almost_full at 92 entries, and almost_empty at 4 entries.

Response:
```verilog
module sync_fifo_24b_96d (
  input clk,
  input rst,
  input write_en,
  input read_en,
  input [23:0] write_data,
  output [23:0] read_data,
  output almost_full,
  output almost_empty
);

  reg [23:0] fifo_mem [95:0];
  reg [6:0] write_ptr, read_ptr;
  reg [7:0] count;

  assign full = (count == 96);
  assign empty = (count == 0);
  assign read_data = fifo_mem[read_ptr];
    assign almost_full = (count > 92);
  assign almost_empty = (count < 4);

  always @(posedge clk) begin
    if (rst) begin
      write_ptr <= 7'b0;
      read_ptr <= 7'b0;
      count <= 8'b0;
    end else begin
      if (write_en && ~full) begin
        fifo_mem[write_ptr] <= write_data;
        write_ptr <= write_ptr + 1;
        count <= count + 1;
      end
      if (read_en && ~empty) begin
        read_ptr <= read_ptr + 1;
        count <= count - 1;
      end
    end
  end

endmodule
```


Instruction:
You are Elinnos RTL Code Generator v1.0, a specialized Verilog/SystemVerilog code generation agent. Your role: Generate clean, synthesizable RTL code for hardware design tasks. Output ONLY functional RTL code with no $display, assertions, comments, or debug statements.

Generate a synchronous FIFO with 8-bit data width, depth 16, write_enable, read_enable, full flag, empty flag, and peek capability to read data at arbitrary index without consuming it.

Response:
```verilog
module sync_fifo_8b_16d (
  input clk,
  input rst,
  input write_en,
  input read_en,
  input [7:0] write_data,
  output [7:0] read_data,
  input [3:0] peek_idx,
  output [7:0] peek_data
);

  reg [7:0] fifo_mem [15:0];
  reg [3:0] write_ptr, read_ptr;
  reg [4:0] count;

  assign full = (count == 16);
  assign empty = (count == 0);
  assign read_data = fifo_mem[read_ptr];
    assign peek_data = fifo_mem[(read_ptr + peek_idx) % 16];

  always @(posedge clk) begin
    if (rst) begin
      write_ptr <= 4'b0;
      read_ptr <= 4'b0;
      count <= 5'b0;
    end else begin
      if (write_en && ~full) begin
        fifo_mem[write_ptr] <= write_data;
        write_ptr <= write_ptr + 1;
        count <= count + 1;
      end
      if (read_en && ~empty) begin
        read_ptr <= read_ptr + 1;
        count <= count - 1;
      end
    end
  end

endmodule
```


Instruction:
You are Elinnos RTL Code Generator v1.0, a specialized Verilog/SystemVerilog code generation agent. Your role: Generate clean, synthesizable RTL code for hardware design tasks. Output ONLY functional RTL code with no $display, assertions, comments, or debug statements.

Generate a synchronous FIFO with 16-bit data width, depth 32, write_enable, read_enable, full flag, empty flag and include clear signal independent of reset.

Response:
```verilog
module sync_fifo_16b_32d (
  input clk,
  input rst,
  input write_en,
  input read_en,
  input [15:0] write_data,
  output [15:0] read_data,
  input clear
);

  reg [15:0] fifo_mem [31:0];
  reg [4:0] write_ptr, read_ptr;
  reg [5:0] count;

  assign full = (count == 32);
  assign empty = (count == 0);
  assign read_data = fifo_mem[read_ptr];

  always @(posedge clk) begin
    if (rst || clear) begin
      write_ptr <= 5'b0;
      read_ptr <= 5'b0;
      count <= 6'b0;
    end else begin
      if (write_en && ~full) begin
        fifo_mem[write_ptr] <= write_data;
        write_ptr <= write_ptr + 1;
        count <= count + 1;
      end
      if (read_en && ~empty) begin
        read_ptr <= read_ptr + 1;
        count <= count - 1;
      end
    end
  end

endmodule
```


Instruction:
You are Elinnos RTL Code Generator v1.0, a specialized Verilog/SystemVerilog code generation agent. Your role: Generate clean, synthesizable RTL code for hardware design tasks. Output ONLY functional RTL code with no $display, assertions, comments, or debug statements.

Generate a 32-bit synchronous FIFO with depth 64 using AXI-like write_valid/write_ready handshake and read_valid/read_ready handshake.

Response:
```verilog
module sync_fifo_32b_64d_axi (
  input clk,
  input rst,
  input write_valid,
  output write_ready,
  input [31:0] write_data,
  output read_valid,
  input read_ready,
  output [31:0] read_data
);

  reg [31:0] fifo_mem [63:0];
  reg [5:0] write_ptr, read_ptr;
  reg [6:0] count;

  assign write_ready = (count < 64);
  assign read_valid = (count > 0);
  assign read_data = fifo_mem[read_ptr];

  always @(posedge clk) begin
    if (rst) begin
      write_ptr <= 6'b0;
      read_ptr <= 6'b0;
      count <= 7'b0;
    end else begin
      case ({write_valid && write_ready, read_valid && read_ready})
        2'b10: begin
          fifo_mem[write_ptr] <= write_data;
          write_ptr <= write_ptr + 1;
          count <= count + 1;
        end
        2'b01: begin
          read_ptr <= read_ptr + 1;
          count <= count - 1;
        end
        2'b11: begin
          fifo_mem[write_ptr] <= write_data;
          write_ptr <= write_ptr + 1;
          read_ptr <= read_ptr + 1;
        end
      endcase
    end
  end

endmodule
```


Instruction:
You are Elinnos RTL Code Generator v1.0, a specialized Verilog/SystemVerilog code generation agent. Your role: Generate clean, synthesizable RTL code for hardware design tasks. Output ONLY functional RTL code with no $display, assertions, comments, or debug statements.

Generate a synchronous FIFO with 64-bit data width, depth 256, write_enable, read_enable, full flag, empty flag, and occupancy output showing number of valid entries (0 to 256).

Response:
```verilog
module sync_fifo_64b_256d (
  input clk,
  input rst,
  input write_en,
  input read_en,
  input [63:0] write_data,
  output [63:0] read_data,
  output [7:0] occupancy
);

  reg [63:0] fifo_mem [255:0];
  reg [7:0] write_ptr, read_ptr;
  reg [8:0] count;

  assign full = (count == 256);
  assign empty = (count == 0);
  assign read_data = fifo_mem[read_ptr];
    assign occupancy = count[7:0];

  always @(posedge clk) begin
    if (rst) begin
      write_ptr <= 8'b0;
      read_ptr <= 8'b0;
      count <= 9'b0;
    end else begin
      if (write_en && ~full) begin
        fifo_mem[write_ptr] <= write_data;
        write_ptr <= write_ptr + 1;
        count <= count + 1;
      end
      if (read_en && ~empty) begin
        read_ptr <= read_ptr + 1;
        count <= count - 1;
      end
    end
  end

endmodule
```


Instruction:
You are Elinnos RTL Code Generator v1.0, a specialized Verilog/SystemVerilog code generation agent. Your role: Generate clean, synthesizable RTL code for hardware design tasks. Output ONLY functional RTL code with no $display, assertions, comments, or debug statements.

Generate a synchronous FIFO with 4-bit data width, depth 32, write_enable, read_enable, full flag, empty flag.

Response:
```verilog
module sync_fifo_4b_32d (
  input clk,
  input rst,
  input write_en,
  input read_en,
  input [3:0] write_data,
  output [3:0] read_data
);

  reg [3:0] fifo_mem [31:0];
  reg [4:0] write_ptr, read_ptr;
  reg [5:0] count;

  assign full = (count == 32);
  assign empty = (count == 0);
  assign read_data = fifo_mem[read_ptr];

  always @(posedge clk) begin
    if (rst) begin
      write_ptr <= 5'b0;
      read_ptr <= 5'b0;
      count <= 6'b0;
    end else begin
      if (write_en && ~full) begin
        fifo_mem[write_ptr] <= write_data;
        write_ptr <= write_ptr + 1;
        count <= count + 1;
      end
      if (read_en && ~empty) begin
        read_ptr <= read_ptr + 1;
        count <= count - 1;
      end
    end
  end

endmodule
```


Instruction:
You are Elinnos RTL Code Generator v1.0, a specialized Verilog/SystemVerilog code generation agent. Your role: Generate clean, synthesizable RTL code for hardware design tasks. Output ONLY functional RTL code with no $display, assertions, comments, or debug statements.

Generate a synchronous FIFO with 12-bit data width, depth 8, write_enable, read_enable, full flag, empty flag.

Response:
```verilog
module sync_fifo_12b_8d (
  input clk,
  input rst,
  input write_en,
  input read_en,
  input [11:0] write_data,
  output [11:0] read_data
);

  reg [11:0] fifo_mem [7:0];
  reg [2:0] write_ptr, read_ptr;
  reg [3:0] count;

  assign full = (count == 8);
  assign empty = (count == 0);
  assign read_data = fifo_mem[read_ptr];

  always @(posedge clk) begin
    if (rst) begin
      write_ptr <= 3'b0;
      read_ptr <= 3'b0;
      count <= 4'b0;
    end else begin
      if (write_en && ~full) begin
        fifo_mem[write_ptr] <= write_data;
        write_ptr <= write_ptr + 1;
        count <= count + 1;
      end
      if (read_en && ~empty) begin
        read_ptr <= read_ptr + 1;
        count <= count - 1;
      end
    end
  end

endmodule
```


Instruction:
You are Elinnos RTL Code Generator v1.0, a specialized Verilog/SystemVerilog code generation agent. Your role: Generate clean, synthesizable RTL code for hardware design tasks. Output ONLY functional RTL code with no $display, assertions, comments, or debug statements.

Generate a synchronous FIFO with 20-bit data width, depth 16, write_enable, read_enable, full flag, empty flag.

Response:
```verilog
module sync_fifo_20b_16d (
  input clk,
  input rst,
  input write_en,
  input read_en,
  input [19:0] write_data,
  output [19:0] read_data
);

  reg [19:0] fifo_mem [15:0];
  reg [3:0] write_ptr, read_ptr;
  reg [4:0] count;

  assign full = (count == 16);
  assign empty = (count == 0);
  assign read_data = fifo_mem[read_ptr];

  always @(posedge clk) begin
    if (rst) begin
      write_ptr <= 4'b0;
      read_ptr <= 4'b0;
      count <= 5'b0;
    end else begin
      if (write_en && ~full) begin
        fifo_mem[write_ptr] <= write_data;
        write_ptr <= write_ptr + 1;
        count <= count + 1;
      end
      if (read_en && ~empty) begin
        read_ptr <= read_ptr + 1;
        count <= count - 1;
      end
    end
  end

endmodule
```


Instruction:
You are Elinnos RTL Code Generator v1.0, a specialized Verilog/SystemVerilog code generation agent. Your role: Generate clean, synthesizable RTL code for hardware design tasks. Output ONLY functional RTL code with no $display, assertions, comments, or debug statements.

Generate a synchronous FIFO with 28-bit data width, depth 32, write_enable, read_enable, full flag, empty flag.

Response:
```verilog
module sync_fifo_28b_32d (
  input clk,
  input rst,
  input write_en,
  input read_en,
  input [27:0] write_data,
  output [27:0] read_data
);

  reg [27:0] fifo_mem [31:0];
  reg [4:0] write_ptr, read_ptr;
  reg [5:0] count;

  assign full = (count == 32);
  assign empty = (count == 0);
  assign read_data = fifo_mem[read_ptr];

  always @(posedge clk) begin
    if (rst) begin
      write_ptr <= 5'b0;
      read_ptr <= 5'b0;
      count <= 6'b0;
    end else begin
      if (write_en && ~full) begin
        fifo_mem[write_ptr] <= write_data;
        write_ptr <= write_ptr + 1;
        count <= count + 1;
      end
      if (read_en && ~empty) begin
        read_ptr <= read_ptr + 1;
        count <= count - 1;
      end
    end
  end

endmodule
```


Instruction:
You are Elinnos RTL Code Generator v1.0, a specialized Verilog/SystemVerilog code generation agent. Your role: Generate clean, synthesizable RTL code for hardware design tasks. Output ONLY functional RTL code with no $display, assertions, comments, or debug statements.

Generate a synchronous FIFO with 36-bit data width, depth 64, write_enable, read_enable, full flag, empty flag, and occupancy output showing number of valid entries (0 to 64).

Response:
```verilog
module sync_fifo_36b_64d (
  input clk,
  input rst,
  input write_en,
  input read_en,
  input [35:0] write_data,
  output [35:0] read_data,
  output [5:0] occupancy
);

  reg [35:0] fifo_mem [63:0];
  reg [5:0] write_ptr, read_ptr;
  reg [6:0] count;

  assign full = (count == 64);
  assign empty = (count == 0);
  assign read_data = fifo_mem[read_ptr];
    assign occupancy = count[5:0];

  always @(posedge clk) begin
    if (rst) begin
      write_ptr <= 6'b0;
      read_ptr <= 6'b0;
      count <= 7'b0;
    end else begin
      if (write_en && ~full) begin
        fifo_mem[write_ptr] <= write_data;
        write_ptr <= write_ptr + 1;
        count <= count + 1;
      end
      if (read_en && ~empty) begin
        read_ptr <= read_ptr + 1;
        count <= count - 1;
      end
    end
  end

endmodule
```


Instruction:
You are Elinnos RTL Code Generator v1.0, a specialized Verilog/SystemVerilog code generation agent. Your role: Generate clean, synthesizable RTL code for hardware design tasks. Output ONLY functional RTL code with no $display, assertions, comments, or debug statements.

Generate a synchronous FIFO with 48-bit data width, depth 128, write_enable, read_enable, full flag, empty flag with threshold output indicating if occupancy exceeds 96.

Response:
```verilog
module sync_fifo_48b_128d (
  input clk,
  input rst,
  input write_en,
  input read_en,
  input [47:0] write_data,
  output [47:0] read_data,
  output threshold_high
);

  reg [47:0] fifo_mem [127:0];
  reg [6:0] write_ptr, read_ptr;
  reg [7:0] count;

  assign full = (count == 128);
  assign empty = (count == 0);
  assign read_data = fifo_mem[read_ptr];
    assign threshold_high = (count > 96);

  always @(posedge clk) begin
    if (rst) begin
      write_ptr <= 7'b0;
      read_ptr <= 7'b0;
      count <= 8'b0;
    end else begin
      if (write_en && ~full) begin
        fifo_mem[write_ptr] <= write_data;
        write_ptr <= write_ptr + 1;
        count <= count + 1;
      end
      if (read_en && ~empty) begin
        read_ptr <= read_ptr + 1;
        count <= count - 1;
      end
    end
  end

endmodule
```