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SpecForge-ext/cache/compiled_kernels/triton/2/2HBOMUT44J5WFCUWYGRFAAS3HGVNDHLHT7HCSXUCAOIKU6XGJNTA/__grp__triton_red_fused__to_copy_clone_slice_sum_transpose_5.json

@@ -0,0 +1 @@
+{"child_paths": {"triton_red_fused__to_copy_clone_slice_sum_transpose_5.source": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/2HBOMUT44J5WFCUWYGRFAAS3HGVNDHLHT7HCSXUCAOIKU6XGJNTA/triton_red_fused__to_copy_clone_slice_sum_transpose_5.source", "triton_red_fused__to_copy_clone_slice_sum_transpose_5.ttir": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/2HBOMUT44J5WFCUWYGRFAAS3HGVNDHLHT7HCSXUCAOIKU6XGJNTA/triton_red_fused__to_copy_clone_slice_sum_transpose_5.ttir", "triton_red_fused__to_copy_clone_slice_sum_transpose_5.ttgir": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/2HBOMUT44J5WFCUWYGRFAAS3HGVNDHLHT7HCSXUCAOIKU6XGJNTA/triton_red_fused__to_copy_clone_slice_sum_transpose_5.ttgir", "triton_red_fused__to_copy_clone_slice_sum_transpose_5.llir": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/2HBOMUT44J5WFCUWYGRFAAS3HGVNDHLHT7HCSXUCAOIKU6XGJNTA/triton_red_fused__to_copy_clone_slice_sum_transpose_5.llir", "triton_red_fused__to_copy_clone_slice_sum_transpose_5.ptx": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/2HBOMUT44J5WFCUWYGRFAAS3HGVNDHLHT7HCSXUCAOIKU6XGJNTA/triton_red_fused__to_copy_clone_slice_sum_transpose_5.ptx", "triton_red_fused__to_copy_clone_slice_sum_transpose_5.cubin": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/2HBOMUT44J5WFCUWYGRFAAS3HGVNDHLHT7HCSXUCAOIKU6XGJNTA/triton_red_fused__to_copy_clone_slice_sum_transpose_5.cubin", "triton_red_fused__to_copy_clone_slice_sum_transpose_5.json": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/2HBOMUT44J5WFCUWYGRFAAS3HGVNDHLHT7HCSXUCAOIKU6XGJNTA/triton_red_fused__to_copy_clone_slice_sum_transpose_5.json"}}

SpecForge-ext/cache/compiled_kernels/triton/2/2TU6ZCF6AOXLWQQED5J7FS5ZXMYK7TIOQ6T2MLB767275BROXJCA/__grp__triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0.json

@@ -0,0 +1 @@
+{"child_paths": {"triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0.source": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/2TU6ZCF6AOXLWQQED5J7FS5ZXMYK7TIOQ6T2MLB767275BROXJCA/triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0.source", "triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0.ttir": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/2TU6ZCF6AOXLWQQED5J7FS5ZXMYK7TIOQ6T2MLB767275BROXJCA/triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0.ttir", "triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0.ttgir": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/2TU6ZCF6AOXLWQQED5J7FS5ZXMYK7TIOQ6T2MLB767275BROXJCA/triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0.ttgir", "triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0.llir": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/2TU6ZCF6AOXLWQQED5J7FS5ZXMYK7TIOQ6T2MLB767275BROXJCA/triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0.llir", "triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0.ptx": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/2TU6ZCF6AOXLWQQED5J7FS5ZXMYK7TIOQ6T2MLB767275BROXJCA/triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0.ptx", "triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0.cubin": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/2TU6ZCF6AOXLWQQED5J7FS5ZXMYK7TIOQ6T2MLB767275BROXJCA/triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0.cubin", "triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0.json": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/2TU6ZCF6AOXLWQQED5J7FS5ZXMYK7TIOQ6T2MLB767275BROXJCA/triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0.json"}}

SpecForge-ext/cache/compiled_kernels/triton/2/2TU6ZCF6AOXLWQQED5J7FS5ZXMYK7TIOQ6T2MLB767275BROXJCA/triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0.json

@@ -0,0 +1 @@
+{"hash": "d4e9ec88be03aebb42041f53f2cbb9bb30afcd0e87a7a62c3ff7f5fe862eba44", "target": {"backend": "cuda", "arch": 90, "warp_size": 32}, "num_warps": 4, "num_ctas": 1, "num_stages": 1, "warp_size": 32, "maxnreg": null, "cluster_dims": [1, 1, 1], "ptx_version": null, "ptx_options": null, "ir_override": null, "enable_fp_fusion": true, "launch_cooperative_grid": false, "launch_pdl": false, "supported_fp8_dtypes": ["fp8e4b15", "fp8e4nv", "fp8e5"], "deprecated_fp8_dot_operand_dtypes": ["fp8e4b15"], "default_dot_input_precision": "tf32", "allowed_dot_input_precisions": ["tf32", "tf32x3", "ieee"], "max_num_imprecise_acc_default": 1073741824, "extern_libs": [["libdevice", "/workspace/specforge/lib/python3.11/site-packages/triton/backends/nvidia/lib/libdevice.10.bc"]], "debug": true, "backend_name": "cuda", "sanitize_overflow": false, "arch": "sm90", "instrumentation_mode": "", "triton_version": "3.5.1", "tensordesc_meta": [], "shared": 0, "tmem_size": 0, "global_scratch_size": 0, "global_scratch_align": 1, "profile_scratch_size": 0, "profile_scratch_align": 1, "name": "triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0"}

SpecForge-ext/cache/compiled_kernels/triton/2/2TU6ZCF6AOXLWQQED5J7FS5ZXMYK7TIOQ6T2MLB767275BROXJCA/triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0.llir

@@ -0,0 +1,667 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+target datalayout = "e-p3:32:32-p4:32:32-p5:32:32-p6:32:32-p7:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64"
+
+@assertFunc_1 = internal constant [8 x i8] c"unknown\00"
+@assertFile_1 = internal constant [114 x i8] c"/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py\00"
+@assertMessage_1 = internal constant [38 x i8] c"index out of bounds: 0 <= tmp25 < ks4\00"
+@assertFunc_0 = internal constant [8 x i8] c"unknown\00"
+@assertFile_0 = internal constant [114 x i8] c"/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py\00"
+@assertMessage_0 = internal constant [37 x i8] c"index out of bounds: 0 <= tmp5 < ks2\00"
+
+; Function Attrs: noreturn
+declare !dbg !5 void @__assertfail(ptr, ptr, i32, ptr, i64) local_unnamed_addr #0
+
+define ptx_kernel void @triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0(ptr addrspace(1) %0, ptr addrspace(1) %1, ptr addrspace(1) %2, ptr addrspace(1) %3, ptr addrspace(1) %4, i64 %5, i64 %6, i64 %7, i64 %8, i64 %9, i32 %10, ptr addrspace(1) readnone captures(none) %11, ptr addrspace(1) readnone captures(none) %12) local_unnamed_addr #1 !dbg !9 {
+  %14 = tail call i32 @llvm.nvvm.read.ptx.sreg.ctaid.x(), !dbg !10
+  %15 = shl i32 %14, 10, !dbg !11
+  %16 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !12
+  %17 = shl nuw nsw i32 %16, 3, !dbg !12
+  %18 = and i32 %17, 1016, !dbg !12
+  %19 = or disjoint i32 %18, %15, !dbg !13
+  %20 = or disjoint i32 %19, 1, !dbg !13
+  %21 = or disjoint i32 %19, 2, !dbg !13
+  %22 = or disjoint i32 %19, 3, !dbg !13
+  %23 = or disjoint i32 %19, 4, !dbg !13
+  %24 = or disjoint i32 %19, 5, !dbg !13
+  %25 = or disjoint i32 %19, 6, !dbg !13
+  %26 = or disjoint i32 %19, 7, !dbg !13
+  %27 = insertelement <8 x i32> poison, i32 %26, i64 0, !dbg !14
+  %28 = insertelement <8 x i32> %27, i32 %25, i64 1, !dbg !14
+  %29 = insertelement <8 x i32> %28, i32 %24, i64 2, !dbg !14
+  %30 = insertelement <8 x i32> %29, i32 %23, i64 3, !dbg !14
+  %31 = insertelement <8 x i32> %30, i32 %22, i64 4, !dbg !14
+  %32 = insertelement <8 x i32> %31, i32 %21, i64 5, !dbg !14
+  %33 = insertelement <8 x i32> %32, i32 %20, i64 6, !dbg !14
+  %34 = insertelement <8 x i32> %33, i32 %19, i64 7, !dbg !14
+  %35 = sext <8 x i32> %34 to <8 x i64>, !dbg !14
+  %36 = extractelement <8 x i64> %35, i64 7, !dbg !15
+  %37 = sdiv i64 %36, %5, !dbg !14
+  %38 = extractelement <8 x i64> %35, i64 6, !dbg !15
+  %39 = sdiv i64 %38, %5, !dbg !14
+  %40 = extractelement <8 x i64> %35, i64 5, !dbg !15
+  %41 = sdiv i64 %40, %5, !dbg !14
+  %42 = extractelement <8 x i64> %35, i64 4, !dbg !15
+  %43 = sdiv i64 %42, %5, !dbg !14
+  %44 = extractelement <8 x i64> %35, i64 3, !dbg !15
+  %45 = sdiv i64 %44, %5, !dbg !14
+  %46 = extractelement <8 x i64> %35, i64 2, !dbg !15
+  %47 = sdiv i64 %46, %5, !dbg !14
+  %48 = extractelement <8 x i64> %35, i64 1, !dbg !15
+  %49 = sdiv i64 %48, %5, !dbg !14
+  %50 = extractelement <8 x i64> %35, i64 0, !dbg !15
+  %51 = sdiv i64 %50, %5, !dbg !14
+  %52 = srem i64 %37, %6, !dbg !16
+  %53 = srem i64 %39, %6, !dbg !16
+  %54 = srem i64 %41, %6, !dbg !16
+  %55 = srem i64 %43, %6, !dbg !16
+  %56 = srem i64 %45, %6, !dbg !16
+  %57 = srem i64 %47, %6, !dbg !16
+  %58 = srem i64 %49, %6, !dbg !16
+  %59 = srem i64 %51, %6, !dbg !16
+  %60 = getelementptr bfloat, ptr addrspace(1) %0, i64 %36, !dbg !15
+  %61 = getelementptr bfloat, ptr addrspace(1) %0, i64 %38, !dbg !15
+  %62 = getelementptr bfloat, ptr addrspace(1) %0, i64 %40, !dbg !15
+  %63 = getelementptr bfloat, ptr addrspace(1) %0, i64 %42, !dbg !15
+  %64 = getelementptr bfloat, ptr addrspace(1) %0, i64 %44, !dbg !15
+  %65 = getelementptr bfloat, ptr addrspace(1) %0, i64 %46, !dbg !15
+  %66 = getelementptr bfloat, ptr addrspace(1) %0, i64 %48, !dbg !15
+  %67 = getelementptr bfloat, ptr addrspace(1) %0, i64 %50, !dbg !15
+  %68 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !17
+  %69 = getelementptr i64, ptr addrspace(1) %1, i64 %52, !dbg !18
+  %70 = getelementptr i64, ptr addrspace(1) %1, i64 %53, !dbg !18
+  %71 = getelementptr i64, ptr addrspace(1) %1, i64 %54, !dbg !18
+  %72 = getelementptr i64, ptr addrspace(1) %1, i64 %55, !dbg !18
+  %73 = getelementptr i64, ptr addrspace(1) %1, i64 %56, !dbg !18
+  %74 = getelementptr i64, ptr addrspace(1) %1, i64 %57, !dbg !18
+  %75 = getelementptr i64, ptr addrspace(1) %1, i64 %58, !dbg !18
+  %76 = getelementptr i64, ptr addrspace(1) %1, i64 %59, !dbg !18
+  %77 = insertelement <8 x i32> poison, i32 %19, i64 0, !dbg !19
+  %78 = insertelement <8 x i32> %77, i32 %20, i64 1, !dbg !19
+  %79 = insertelement <8 x i32> %78, i32 %21, i64 2, !dbg !19
+  %80 = insertelement <8 x i32> %79, i32 %22, i64 3, !dbg !19
+  %81 = insertelement <8 x i32> %80, i32 %23, i64 4, !dbg !19
+  %82 = insertelement <8 x i32> %81, i32 %24, i64 5, !dbg !19
+  %83 = insertelement <8 x i32> %82, i32 %25, i64 6, !dbg !19
+  %84 = insertelement <8 x i32> %83, i32 %26, i64 7, !dbg !19
+  %85 = insertelement <8 x i32> poison, i32 %10, i64 0, !dbg !19
+  %86 = shufflevector <8 x i32> %85, <8 x i32> poison, <8 x i32> zeroinitializer, !dbg !19
+  %87 = icmp slt <8 x i32> %84, %86, !dbg !19
+  %88 = extractelement <8 x i1> %87, i64 0, !dbg !17
+  %89 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$3 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $1 + 0 ], $2;", "=c,l,l,b"(ptr addrspace(1) %60, i64 %68, i1 %88) #4, !dbg !17
+  %90 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !17
+  %91 = extractelement <8 x i1> %87, i64 1, !dbg !17
+  %92 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$3 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $1 + 0 ], $2;", "=c,l,l,b"(ptr addrspace(1) %61, i64 %90, i1 %91) #4, !dbg !17
+  %93 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !17
+  %94 = extractelement <8 x i1> %87, i64 2, !dbg !17
+  %95 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$3 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $1 + 0 ], $2;", "=c,l,l,b"(ptr addrspace(1) %62, i64 %93, i1 %94) #4, !dbg !17
+  %96 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !17
+  %97 = extractelement <8 x i1> %87, i64 3, !dbg !17
+  %98 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$3 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $1 + 0 ], $2;", "=c,l,l,b"(ptr addrspace(1) %63, i64 %96, i1 %97) #4, !dbg !17
+  %99 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !17
+  %100 = extractelement <8 x i1> %87, i64 4, !dbg !17
+  %101 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$3 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $1 + 0 ], $2;", "=c,l,l,b"(ptr addrspace(1) %64, i64 %99, i1 %100) #4, !dbg !17
+  %102 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !17
+  %103 = extractelement <8 x i1> %87, i64 5, !dbg !17
+  %104 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$3 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $1 + 0 ], $2;", "=c,l,l,b"(ptr addrspace(1) %65, i64 %102, i1 %103) #4, !dbg !17
+  %105 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !17
+  %106 = extractelement <8 x i1> %87, i64 6, !dbg !17
+  %107 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$3 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $1 + 0 ], $2;", "=c,l,l,b"(ptr addrspace(1) %66, i64 %105, i1 %106) #4, !dbg !17
+  %108 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !17
+  %109 = extractelement <8 x i1> %87, i64 7, !dbg !17
+  %110 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$3 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $1 + 0 ], $2;", "=c,l,l,b"(ptr addrspace(1) %67, i64 %108, i1 %109) #4, !dbg !17
+  %111 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !20
+  %112 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$3 ld.global.L1::evict_last.L2::cache_hint.b64 { $0 }, [ $1 + 0 ], $2;", "=l,l,l,b"(ptr addrspace(1) %69, i64 %111, i1 %88) #4, !dbg !20
+  %113 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !20
+  %114 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$3 ld.global.L1::evict_last.L2::cache_hint.b64 { $0 }, [ $1 + 0 ], $2;", "=l,l,l,b"(ptr addrspace(1) %70, i64 %113, i1 %91) #4, !dbg !20
+  %115 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !20
+  %116 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$3 ld.global.L1::evict_last.L2::cache_hint.b64 { $0 }, [ $1 + 0 ], $2;", "=l,l,l,b"(ptr addrspace(1) %71, i64 %115, i1 %94) #4, !dbg !20
+  %117 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !20
+  %118 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$3 ld.global.L1::evict_last.L2::cache_hint.b64 { $0 }, [ $1 + 0 ], $2;", "=l,l,l,b"(ptr addrspace(1) %72, i64 %117, i1 %97) #4, !dbg !20
+  %119 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !20
+  %120 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$3 ld.global.L1::evict_last.L2::cache_hint.b64 { $0 }, [ $1 + 0 ], $2;", "=l,l,l,b"(ptr addrspace(1) %73, i64 %119, i1 %100) #4, !dbg !20
+  %121 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !20
+  %122 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$3 ld.global.L1::evict_last.L2::cache_hint.b64 { $0 }, [ $1 + 0 ], $2;", "=l,l,l,b"(ptr addrspace(1) %74, i64 %121, i1 %103) #4, !dbg !20
+  %123 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !20
+  %124 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$3 ld.global.L1::evict_last.L2::cache_hint.b64 { $0 }, [ $1 + 0 ], $2;", "=l,l,l,b"(ptr addrspace(1) %75, i64 %123, i1 %106) #4, !dbg !20
+  %125 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !20
+  %126 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$3 ld.global.L1::evict_last.L2::cache_hint.b64 { $0 }, [ $1 + 0 ], $2;", "=l,l,l,b"(ptr addrspace(1) %76, i64 %125, i1 %109) #4, !dbg !20
+  %127 = insertelement <8 x i64> poison, i64 %112, i64 0, !dbg !21
+  %128 = insertelement <8 x i64> %127, i64 %114, i64 1, !dbg !21
+  %129 = insertelement <8 x i64> %128, i64 %116, i64 2, !dbg !21
+  %130 = insertelement <8 x i64> %129, i64 %118, i64 3, !dbg !21
+  %131 = insertelement <8 x i64> %130, i64 %120, i64 4, !dbg !21
+  %132 = insertelement <8 x i64> %131, i64 %122, i64 5, !dbg !21
+  %133 = insertelement <8 x i64> %132, i64 %124, i64 6, !dbg !21
+  %134 = insertelement <8 x i64> %133, i64 %126, i64 7, !dbg !21
+  %135 = icmp slt <8 x i64> %134, zeroinitializer, !dbg !21
+  %136 = insertelement <8 x i64> poison, i64 %7, i64 0, !dbg !22
+  %137 = shufflevector <8 x i64> %136, <8 x i64> poison, <8 x i32> zeroinitializer, !dbg !22
+  %138 = select <8 x i1> %135, <8 x i64> %137, <8 x i64> zeroinitializer, !dbg !22
+  %139 = add <8 x i64> %138, %134, !dbg !22
+  %140 = icmp slt <8 x i64> %139, zeroinitializer, !dbg !23
+  %141 = icmp sge <8 x i64> %139, %137, !dbg !24
+  %142 = or <8 x i1> %140, %141, !dbg !25
+  %143 = and <8 x i1> %87, %142, !dbg !26
+  %144 = bitcast <8 x i1> %143 to i8, !dbg !27
+  %.not = icmp eq i8 %144, 0, !dbg !27
+  br i1 %.not, label %146, label %145, !dbg !27
+
+145:                                              ; preds = %13
+  tail call void @__assertfail(ptr nonnull @assertMessage_0, ptr nonnull @assertFile_0, i32 32, ptr nonnull @assertFunc_0, i64 1), !dbg !27
+  unreachable, !dbg !27
+
+146:                                              ; preds = %13
+  %147 = insertelement <8 x i64> poison, i64 %8, i64 0, !dbg !28
+  %148 = shufflevector <8 x i64> %147, <8 x i64> poison, <8 x i32> zeroinitializer, !dbg !28
+  %149 = srem <8 x i64> %35, %148, !dbg !28
+  tail call void @llvm.nvvm.barrier.cta.sync.aligned.all(i32 0), !dbg !27
+  %150 = extractelement <8 x i64> %139, i64 0, !dbg !29
+  %151 = mul i64 %150, %8, !dbg !29
+  %152 = extractelement <8 x i64> %139, i64 1, !dbg !29
+  %153 = mul i64 %152, %8, !dbg !29
+  %154 = extractelement <8 x i64> %139, i64 2, !dbg !29
+  %155 = mul i64 %154, %8, !dbg !29
+  %156 = extractelement <8 x i64> %139, i64 3, !dbg !29
+  %157 = mul i64 %156, %8, !dbg !29
+  %158 = extractelement <8 x i64> %139, i64 4, !dbg !29
+  %159 = mul i64 %158, %8, !dbg !29
+  %160 = extractelement <8 x i64> %139, i64 5, !dbg !29
+  %161 = mul i64 %160, %8, !dbg !29
+  %162 = extractelement <8 x i64> %139, i64 6, !dbg !29
+  %163 = mul i64 %162, %8, !dbg !29
+  %164 = extractelement <8 x i64> %139, i64 7, !dbg !29
+  %165 = mul i64 %164, %8, !dbg !29
+  %166 = extractelement <8 x i64> %149, i64 7, !dbg !30
+  %167 = getelementptr bfloat, ptr addrspace(1) %2, i64 %166, !dbg !31
+  %168 = getelementptr bfloat, ptr addrspace(1) %167, i64 %151, !dbg !31
+  %169 = extractelement <8 x i64> %149, i64 6, !dbg !30
+  %170 = getelementptr bfloat, ptr addrspace(1) %2, i64 %169, !dbg !31
+  %171 = getelementptr bfloat, ptr addrspace(1) %170, i64 %153, !dbg !31
+  %172 = extractelement <8 x i64> %149, i64 5, !dbg !30
+  %173 = getelementptr bfloat, ptr addrspace(1) %2, i64 %172, !dbg !31
+  %174 = getelementptr bfloat, ptr addrspace(1) %173, i64 %155, !dbg !31
+  %175 = extractelement <8 x i64> %149, i64 4, !dbg !30
+  %176 = getelementptr bfloat, ptr addrspace(1) %2, i64 %175, !dbg !31
+  %177 = getelementptr bfloat, ptr addrspace(1) %176, i64 %157, !dbg !31
+  %178 = extractelement <8 x i64> %149, i64 3, !dbg !30
+  %179 = getelementptr bfloat, ptr addrspace(1) %2, i64 %178, !dbg !31
+  %180 = getelementptr bfloat, ptr addrspace(1) %179, i64 %159, !dbg !31
+  %181 = extractelement <8 x i64> %149, i64 2, !dbg !30
+  %182 = getelementptr bfloat, ptr addrspace(1) %2, i64 %181, !dbg !31
+  %183 = getelementptr bfloat, ptr addrspace(1) %182, i64 %161, !dbg !31
+  %184 = extractelement <8 x i64> %149, i64 1, !dbg !30
+  %185 = getelementptr bfloat, ptr addrspace(1) %2, i64 %184, !dbg !31
+  %186 = getelementptr bfloat, ptr addrspace(1) %185, i64 %163, !dbg !31
+  %187 = extractelement <8 x i64> %149, i64 0, !dbg !30
+  %188 = getelementptr bfloat, ptr addrspace(1) %2, i64 %187, !dbg !31
+  %189 = getelementptr bfloat, ptr addrspace(1) %188, i64 %165, !dbg !31
+  %190 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !32
+  %191 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$3 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $1 + 0 ], $2;", "=c,l,l,b"(ptr addrspace(1) %168, i64 %190, i1 %88) #4, !dbg !32
+  %192 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !32
+  %193 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$3 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $1 + 0 ], $2;", "=c,l,l,b"(ptr addrspace(1) %171, i64 %192, i1 %91) #4, !dbg !32
+  %194 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !32
+  %195 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$3 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $1 + 0 ], $2;", "=c,l,l,b"(ptr addrspace(1) %174, i64 %194, i1 %94) #4, !dbg !32
+  %196 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !32
+  %197 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$3 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $1 + 0 ], $2;", "=c,l,l,b"(ptr addrspace(1) %177, i64 %196, i1 %97) #4, !dbg !32
+  %198 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !32
+  %199 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$3 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $1 + 0 ], $2;", "=c,l,l,b"(ptr addrspace(1) %180, i64 %198, i1 %100) #4, !dbg !32
+  %200 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !32
+  %201 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$3 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $1 + 0 ], $2;", "=c,l,l,b"(ptr addrspace(1) %183, i64 %200, i1 %103) #4, !dbg !32
+  %202 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !32
+  %203 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$3 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $1 + 0 ], $2;", "=c,l,l,b"(ptr addrspace(1) %186, i64 %202, i1 %106) #4, !dbg !32
+  %204 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !32
+  %205 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$3 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $1 + 0 ], $2;", "=c,l,l,b"(ptr addrspace(1) %189, i64 %204, i1 %109) #4, !dbg !32
+  %206 = sdiv i64 %8, 2, !dbg !33
+  %207 = sub i64 %8, %206, !dbg !34
+  %208 = icmp slt i64 %166, %207, !dbg !35
+  %209 = icmp slt i64 %169, %207, !dbg !35
+  %210 = icmp slt i64 %172, %207, !dbg !35
+  %211 = icmp slt i64 %175, %207, !dbg !35
+  %212 = icmp slt i64 %178, %207, !dbg !35
+  %213 = icmp slt i64 %181, %207, !dbg !35
+  %214 = icmp slt i64 %184, %207, !dbg !35
+  %215 = icmp slt i64 %187, %207, !dbg !35
+  %216 = sub nsw i64 %36, %166, !dbg !30
+  %217 = sub nsw i64 %38, %169, !dbg !30
+  %218 = sub nsw i64 %40, %172, !dbg !30
+  %219 = sub nsw i64 %42, %175, !dbg !30
+  %220 = sub nsw i64 %44, %178, !dbg !30
+  %221 = sub nsw i64 %46, %181, !dbg !30
+  %222 = sub nsw i64 %48, %184, !dbg !30
+  %223 = sub nsw i64 %50, %187, !dbg !30
+  %224 = getelementptr bfloat, ptr addrspace(1) %0, i64 %216, !dbg !36
+  %225 = getelementptr bfloat, ptr addrspace(1) %224, i64 %206, !dbg !36
+  %226 = getelementptr bfloat, ptr addrspace(1) %225, i64 %166, !dbg !36
+  %227 = getelementptr bfloat, ptr addrspace(1) %0, i64 %217, !dbg !36
+  %228 = getelementptr bfloat, ptr addrspace(1) %227, i64 %206, !dbg !36
+  %229 = getelementptr bfloat, ptr addrspace(1) %228, i64 %169, !dbg !36
+  %230 = getelementptr bfloat, ptr addrspace(1) %0, i64 %218, !dbg !36
+  %231 = getelementptr bfloat, ptr addrspace(1) %230, i64 %206, !dbg !36
+  %232 = getelementptr bfloat, ptr addrspace(1) %231, i64 %172, !dbg !36
+  %233 = getelementptr bfloat, ptr addrspace(1) %0, i64 %219, !dbg !36
+  %234 = getelementptr bfloat, ptr addrspace(1) %233, i64 %206, !dbg !36
+  %235 = getelementptr bfloat, ptr addrspace(1) %234, i64 %175, !dbg !36
+  %236 = getelementptr bfloat, ptr addrspace(1) %0, i64 %220, !dbg !36
+  %237 = getelementptr bfloat, ptr addrspace(1) %236, i64 %206, !dbg !36
+  %238 = getelementptr bfloat, ptr addrspace(1) %237, i64 %178, !dbg !36
+  %239 = getelementptr bfloat, ptr addrspace(1) %0, i64 %221, !dbg !36
+  %240 = getelementptr bfloat, ptr addrspace(1) %239, i64 %206, !dbg !36
+  %241 = getelementptr bfloat, ptr addrspace(1) %240, i64 %181, !dbg !36
+  %242 = getelementptr bfloat, ptr addrspace(1) %0, i64 %222, !dbg !36
+  %243 = getelementptr bfloat, ptr addrspace(1) %242, i64 %206, !dbg !36
+  %244 = getelementptr bfloat, ptr addrspace(1) %243, i64 %184, !dbg !36
+  %245 = getelementptr bfloat, ptr addrspace(1) %0, i64 %223, !dbg !36
+  %246 = getelementptr bfloat, ptr addrspace(1) %245, i64 %206, !dbg !36
+  %247 = getelementptr bfloat, ptr addrspace(1) %246, i64 %187, !dbg !36
+  %248 = and i1 %88, %208, !dbg !37
+  %249 = and i1 %91, %209, !dbg !37
+  %250 = and i1 %94, %210, !dbg !37
+  %251 = and i1 %97, %211, !dbg !37
+  %252 = and i1 %100, %212, !dbg !37
+  %253 = and i1 %103, %213, !dbg !37
+  %254 = and i1 %106, %214, !dbg !37
+  %255 = and i1 %109, %215, !dbg !37
+  %256 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !38
+  %257 = tail call i16 asm sideeffect "mov.u16 $0, $1;\0A\09@$4 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $2 + 0 ], $3;", "=c,c,l,l,b"(i16 0, ptr addrspace(1) %226, i64 %256, i1 %248) #4, !dbg !38
+  %258 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !38
+  %259 = tail call i16 asm sideeffect "mov.u16 $0, $1;\0A\09@$4 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $2 + 0 ], $3;", "=c,c,l,l,b"(i16 0, ptr addrspace(1) %229, i64 %258, i1 %249) #4, !dbg !38
+  %260 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !38
+  %261 = tail call i16 asm sideeffect "mov.u16 $0, $1;\0A\09@$4 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $2 + 0 ], $3;", "=c,c,l,l,b"(i16 0, ptr addrspace(1) %232, i64 %260, i1 %250) #4, !dbg !38
+  %262 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !38
+  %263 = tail call i16 asm sideeffect "mov.u16 $0, $1;\0A\09@$4 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $2 + 0 ], $3;", "=c,c,l,l,b"(i16 0, ptr addrspace(1) %235, i64 %262, i1 %251) #4, !dbg !38
+  %264 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !38
+  %265 = tail call i16 asm sideeffect "mov.u16 $0, $1;\0A\09@$4 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $2 + 0 ], $3;", "=c,c,l,l,b"(i16 0, ptr addrspace(1) %238, i64 %264, i1 %252) #4, !dbg !38
+  %266 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !38
+  %267 = tail call i16 asm sideeffect "mov.u16 $0, $1;\0A\09@$4 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $2 + 0 ], $3;", "=c,c,l,l,b"(i16 0, ptr addrspace(1) %241, i64 %266, i1 %253) #4, !dbg !38
+  %268 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !38
+  %269 = tail call i16 asm sideeffect "mov.u16 $0, $1;\0A\09@$4 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $2 + 0 ], $3;", "=c,c,l,l,b"(i16 0, ptr addrspace(1) %244, i64 %268, i1 %254) #4, !dbg !38
+  %270 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !38
+  %271 = tail call i16 asm sideeffect "mov.u16 $0, $1;\0A\09@$4 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $2 + 0 ], $3;", "=c,c,l,l,b"(i16 0, ptr addrspace(1) %247, i64 %270, i1 %255) #4, !dbg !38
+  %272 = insertelement <8 x i64> poison, i64 %207, i64 0, !dbg !39
+  %273 = shufflevector <8 x i64> %272, <8 x i64> poison, <8 x i32> zeroinitializer, !dbg !39
+  %274 = icmp sge <8 x i64> %149, %273, !dbg !39
+  %275 = sub i64 %166, %8, !dbg !40
+  %276 = sub i64 %169, %8, !dbg !40
+  %277 = sub i64 %172, %8, !dbg !40
+  %278 = sub i64 %175, %8, !dbg !40
+  %279 = sub i64 %178, %8, !dbg !40
+  %280 = sub i64 %181, %8, !dbg !40
+  %281 = sub i64 %184, %8, !dbg !40
+  %282 = sub i64 %187, %8, !dbg !40
+  %283 = getelementptr bfloat, ptr addrspace(1) %224, i64 %275, !dbg !41
+  %284 = getelementptr bfloat, ptr addrspace(1) %283, i64 %206, !dbg !41
+  %285 = getelementptr bfloat, ptr addrspace(1) %227, i64 %276, !dbg !41
+  %286 = getelementptr bfloat, ptr addrspace(1) %285, i64 %206, !dbg !41
+  %287 = getelementptr bfloat, ptr addrspace(1) %230, i64 %277, !dbg !41
+  %288 = getelementptr bfloat, ptr addrspace(1) %287, i64 %206, !dbg !41
+  %289 = getelementptr bfloat, ptr addrspace(1) %233, i64 %278, !dbg !41
+  %290 = getelementptr bfloat, ptr addrspace(1) %289, i64 %206, !dbg !41
+  %291 = getelementptr bfloat, ptr addrspace(1) %236, i64 %279, !dbg !41
+  %292 = getelementptr bfloat, ptr addrspace(1) %291, i64 %206, !dbg !41
+  %293 = getelementptr bfloat, ptr addrspace(1) %239, i64 %280, !dbg !41
+  %294 = getelementptr bfloat, ptr addrspace(1) %293, i64 %206, !dbg !41
+  %295 = getelementptr bfloat, ptr addrspace(1) %242, i64 %281, !dbg !41
+  %296 = getelementptr bfloat, ptr addrspace(1) %295, i64 %206, !dbg !41
+  %297 = getelementptr bfloat, ptr addrspace(1) %245, i64 %282, !dbg !41
+  %298 = getelementptr bfloat, ptr addrspace(1) %297, i64 %206, !dbg !41
+  %299 = extractelement <8 x i1> %274, i64 7, !dbg !42
+  %300 = and i1 %88, %299, !dbg !42
+  %301 = extractelement <8 x i1> %274, i64 6, !dbg !42
+  %302 = and i1 %91, %301, !dbg !42
+  %303 = extractelement <8 x i1> %274, i64 5, !dbg !42
+  %304 = and i1 %94, %303, !dbg !42
+  %305 = extractelement <8 x i1> %274, i64 4, !dbg !42
+  %306 = and i1 %97, %305, !dbg !42
+  %307 = extractelement <8 x i1> %274, i64 3, !dbg !42
+  %308 = and i1 %100, %307, !dbg !42
+  %309 = extractelement <8 x i1> %274, i64 2, !dbg !42
+  %310 = and i1 %103, %309, !dbg !42
+  %311 = extractelement <8 x i1> %274, i64 1, !dbg !42
+  %312 = and i1 %106, %311, !dbg !42
+  %313 = extractelement <8 x i1> %274, i64 0, !dbg !42
+  %314 = and i1 %109, %313, !dbg !42
+  %315 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !43
+  %316 = tail call i16 asm sideeffect "mov.u16 $0, $1;\0A\09@$4 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $2 + 0 ], $3;", "=c,c,l,l,b"(i16 0, ptr addrspace(1) %284, i64 %315, i1 %300) #4, !dbg !43
+  %317 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !43
+  %318 = tail call i16 asm sideeffect "mov.u16 $0, $1;\0A\09@$4 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $2 + 0 ], $3;", "=c,c,l,l,b"(i16 0, ptr addrspace(1) %286, i64 %317, i1 %302) #4, !dbg !43
+  %319 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !43
+  %320 = tail call i16 asm sideeffect "mov.u16 $0, $1;\0A\09@$4 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $2 + 0 ], $3;", "=c,c,l,l,b"(i16 0, ptr addrspace(1) %288, i64 %319, i1 %304) #4, !dbg !43
+  %321 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !43
+  %322 = tail call i16 asm sideeffect "mov.u16 $0, $1;\0A\09@$4 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $2 + 0 ], $3;", "=c,c,l,l,b"(i16 0, ptr addrspace(1) %290, i64 %321, i1 %306) #4, !dbg !43
+  %323 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !43
+  %324 = tail call i16 asm sideeffect "mov.u16 $0, $1;\0A\09@$4 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $2 + 0 ], $3;", "=c,c,l,l,b"(i16 0, ptr addrspace(1) %292, i64 %323, i1 %308) #4, !dbg !43
+  %325 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !43
+  %326 = tail call i16 asm sideeffect "mov.u16 $0, $1;\0A\09@$4 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $2 + 0 ], $3;", "=c,c,l,l,b"(i16 0, ptr addrspace(1) %294, i64 %325, i1 %310) #4, !dbg !43
+  %327 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !43
+  %328 = tail call i16 asm sideeffect "mov.u16 $0, $1;\0A\09@$4 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $2 + 0 ], $3;", "=c,c,l,l,b"(i16 0, ptr addrspace(1) %296, i64 %327, i1 %312) #4, !dbg !43
+  %329 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !43
+  %330 = tail call i16 asm sideeffect "mov.u16 $0, $1;\0A\09@$4 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $2 + 0 ], $3;", "=c,c,l,l,b"(i16 0, ptr addrspace(1) %298, i64 %329, i1 %314) #4, !dbg !43
+  %331 = insertelement <8 x i64> poison, i64 %9, i64 0, !dbg !44
+  %332 = shufflevector <8 x i64> %331, <8 x i64> poison, <8 x i32> zeroinitializer, !dbg !44
+  %333 = select <8 x i1> %135, <8 x i64> %332, <8 x i64> zeroinitializer, !dbg !44
+  %334 = add <8 x i64> %333, %134, !dbg !44
+  %335 = icmp slt <8 x i64> %334, zeroinitializer, !dbg !45
+  %336 = icmp sge <8 x i64> %334, %332, !dbg !46
+  %337 = or <8 x i1> %335, %336, !dbg !47
+  %338 = and <8 x i1> %87, %337, !dbg !48
+  %339 = bitcast <8 x i1> %338 to i8, !dbg !49
+  %.not87 = icmp eq i8 %339, 0, !dbg !49
+  br i1 %.not87, label %341, label %340, !dbg !49
+
+340:                                              ; preds = %146
+  tail call void @__assertfail(ptr nonnull @assertMessage_1, ptr nonnull @assertFile_1, i32 52, ptr nonnull @assertFunc_1, i64 1), !dbg !49
+  unreachable, !dbg !49
+
+341:                                              ; preds = %146
+  %342 = bitcast i16 %271 to bfloat, !dbg !38
+  %343 = fpext bfloat %342 to float, !dbg !50
+  %344 = fsub float 0.000000e+00, %343, !dbg !51
+  %345 = bitcast i16 %330 to bfloat, !dbg !43
+  %346 = fpext bfloat %345 to float, !dbg !52
+  %347 = select i1 %215, float %344, float %346, !dbg !53
+  %348 = bitcast i16 %269 to bfloat, !dbg !38
+  %349 = fpext bfloat %348 to float, !dbg !50
+  %350 = fsub float 0.000000e+00, %349, !dbg !51
+  %351 = bitcast i16 %328 to bfloat, !dbg !43
+  %352 = fpext bfloat %351 to float, !dbg !52
+  %353 = select i1 %214, float %350, float %352, !dbg !53
+  %354 = bitcast i16 %267 to bfloat, !dbg !38
+  %355 = fpext bfloat %354 to float, !dbg !50
+  %356 = fsub float 0.000000e+00, %355, !dbg !51
+  %357 = bitcast i16 %326 to bfloat, !dbg !43
+  %358 = fpext bfloat %357 to float, !dbg !52
+  %359 = select i1 %213, float %356, float %358, !dbg !53
+  %360 = bitcast i16 %265 to bfloat, !dbg !38
+  %361 = fpext bfloat %360 to float, !dbg !50
+  %362 = fsub float 0.000000e+00, %361, !dbg !51
+  %363 = bitcast i16 %324 to bfloat, !dbg !43
+  %364 = fpext bfloat %363 to float, !dbg !52
+  %365 = select i1 %212, float %362, float %364, !dbg !53
+  %366 = bitcast i16 %263 to bfloat, !dbg !38
+  %367 = fpext bfloat %366 to float, !dbg !50
+  %368 = fsub float 0.000000e+00, %367, !dbg !51
+  %369 = bitcast i16 %322 to bfloat, !dbg !43
+  %370 = fpext bfloat %369 to float, !dbg !52
+  %371 = select i1 %211, float %368, float %370, !dbg !53
+  %372 = bitcast i16 %261 to bfloat, !dbg !38
+  %373 = fpext bfloat %372 to float, !dbg !50
+  %374 = fsub float 0.000000e+00, %373, !dbg !51
+  %375 = bitcast i16 %320 to bfloat, !dbg !43
+  %376 = fpext bfloat %375 to float, !dbg !52
+  %377 = select i1 %210, float %374, float %376, !dbg !53
+  %378 = bitcast i16 %259 to bfloat, !dbg !38
+  %379 = fpext bfloat %378 to float, !dbg !50
+  %380 = fsub float 0.000000e+00, %379, !dbg !51
+  %381 = bitcast i16 %318 to bfloat, !dbg !43
+  %382 = fpext bfloat %381 to float, !dbg !52
+  %383 = select i1 %209, float %380, float %382, !dbg !53
+  %384 = bitcast i16 %257 to bfloat, !dbg !38
+  %385 = fpext bfloat %384 to float, !dbg !50
+  %386 = fsub float 0.000000e+00, %385, !dbg !51
+  %387 = bitcast i16 %316 to bfloat, !dbg !43
+  %388 = fpext bfloat %387 to float, !dbg !52
+  %389 = select i1 %208, float %386, float %388, !dbg !53
+  %390 = bitcast i16 %110 to bfloat, !dbg !17
+  %391 = fpext bfloat %390 to float, !dbg !54
+  %392 = bitcast i16 %107 to bfloat, !dbg !17
+  %393 = fpext bfloat %392 to float, !dbg !54
+  %394 = bitcast i16 %104 to bfloat, !dbg !17
+  %395 = fpext bfloat %394 to float, !dbg !54
+  %396 = bitcast i16 %101 to bfloat, !dbg !17
+  %397 = fpext bfloat %396 to float, !dbg !54
+  %398 = bitcast i16 %98 to bfloat, !dbg !17
+  %399 = fpext bfloat %398 to float, !dbg !54
+  %400 = bitcast i16 %95 to bfloat, !dbg !17
+  %401 = fpext bfloat %400 to float, !dbg !54
+  %402 = bitcast i16 %92 to bfloat, !dbg !17
+  %403 = fpext bfloat %402 to float, !dbg !54
+  %404 = bitcast i16 %89 to bfloat, !dbg !17
+  %405 = fpext bfloat %404 to float, !dbg !54
+  tail call void @llvm.nvvm.barrier.cta.sync.aligned.all(i32 0), !dbg !49
+  %406 = extractelement <8 x i64> %334, i64 0, !dbg !55
+  %407 = mul i64 %406, %8, !dbg !55
+  %408 = extractelement <8 x i64> %334, i64 1, !dbg !55
+  %409 = mul i64 %408, %8, !dbg !55
+  %410 = extractelement <8 x i64> %334, i64 2, !dbg !55
+  %411 = mul i64 %410, %8, !dbg !55
+  %412 = extractelement <8 x i64> %334, i64 3, !dbg !55
+  %413 = mul i64 %412, %8, !dbg !55
+  %414 = extractelement <8 x i64> %334, i64 4, !dbg !55
+  %415 = mul i64 %414, %8, !dbg !55
+  %416 = extractelement <8 x i64> %334, i64 5, !dbg !55
+  %417 = mul i64 %416, %8, !dbg !55
+  %418 = extractelement <8 x i64> %334, i64 6, !dbg !55
+  %419 = mul i64 %418, %8, !dbg !55
+  %420 = extractelement <8 x i64> %334, i64 7, !dbg !55
+  %421 = mul i64 %420, %8, !dbg !55
+  %422 = getelementptr bfloat, ptr addrspace(1) %3, i64 %166, !dbg !56
+  %423 = getelementptr bfloat, ptr addrspace(1) %422, i64 %407, !dbg !56
+  %424 = getelementptr bfloat, ptr addrspace(1) %3, i64 %169, !dbg !56
+  %425 = getelementptr bfloat, ptr addrspace(1) %424, i64 %409, !dbg !56
+  %426 = getelementptr bfloat, ptr addrspace(1) %3, i64 %172, !dbg !56
+  %427 = getelementptr bfloat, ptr addrspace(1) %426, i64 %411, !dbg !56
+  %428 = getelementptr bfloat, ptr addrspace(1) %3, i64 %175, !dbg !56
+  %429 = getelementptr bfloat, ptr addrspace(1) %428, i64 %413, !dbg !56
+  %430 = getelementptr bfloat, ptr addrspace(1) %3, i64 %178, !dbg !56
+  %431 = getelementptr bfloat, ptr addrspace(1) %430, i64 %415, !dbg !56
+  %432 = getelementptr bfloat, ptr addrspace(1) %3, i64 %181, !dbg !56
+  %433 = getelementptr bfloat, ptr addrspace(1) %432, i64 %417, !dbg !56
+  %434 = getelementptr bfloat, ptr addrspace(1) %3, i64 %184, !dbg !56
+  %435 = getelementptr bfloat, ptr addrspace(1) %434, i64 %419, !dbg !56
+  %436 = getelementptr bfloat, ptr addrspace(1) %3, i64 %187, !dbg !56
+  %437 = getelementptr bfloat, ptr addrspace(1) %436, i64 %421, !dbg !56
+  %438 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !57
+  %439 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$3 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $1 + 0 ], $2;", "=c,l,l,b"(ptr addrspace(1) %423, i64 %438, i1 %88) #4, !dbg !57
+  %440 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !57
+  %441 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$3 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $1 + 0 ], $2;", "=c,l,l,b"(ptr addrspace(1) %425, i64 %440, i1 %91) #4, !dbg !57
+  %442 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !57
+  %443 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$3 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $1 + 0 ], $2;", "=c,l,l,b"(ptr addrspace(1) %427, i64 %442, i1 %94) #4, !dbg !57
+  %444 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !57
+  %445 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$3 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $1 + 0 ], $2;", "=c,l,l,b"(ptr addrspace(1) %429, i64 %444, i1 %97) #4, !dbg !57
+  %446 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !57
+  %447 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$3 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $1 + 0 ], $2;", "=c,l,l,b"(ptr addrspace(1) %431, i64 %446, i1 %100) #4, !dbg !57
+  %448 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !57
+  %449 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$3 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $1 + 0 ], $2;", "=c,l,l,b"(ptr addrspace(1) %433, i64 %448, i1 %103) #4, !dbg !57
+  %450 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !57
+  %451 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$3 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $1 + 0 ], $2;", "=c,l,l,b"(ptr addrspace(1) %435, i64 %450, i1 %106) #4, !dbg !57
+  %452 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !57
+  %453 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$3 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $1 + 0 ], $2;", "=c,l,l,b"(ptr addrspace(1) %437, i64 %452, i1 %109) #4, !dbg !57
+  %454 = insertelement <2 x i16> poison, i16 %191, i64 0, !dbg !32
+  %455 = insertelement <2 x i16> %454, i16 %439, i64 1, !dbg !32
+  %456 = bitcast <2 x i16> %455 to <2 x bfloat>, !dbg !32
+  %457 = fpext <2 x bfloat> %456 to <2 x float>, !dbg !58
+  %458 = insertelement <2 x float> poison, float %405, i64 0, !dbg !59
+  %459 = insertelement <2 x float> %458, float %389, i64 1, !dbg !59
+  %460 = fmul <2 x float> %459, %457, !dbg !59
+  %461 = insertelement <2 x i16> poison, i16 %193, i64 0, !dbg !32
+  %462 = insertelement <2 x i16> %461, i16 %441, i64 1, !dbg !32
+  %463 = bitcast <2 x i16> %462 to <2 x bfloat>, !dbg !32
+  %464 = fpext <2 x bfloat> %463 to <2 x float>, !dbg !58
+  %465 = insertelement <2 x float> poison, float %403, i64 0, !dbg !59
+  %466 = insertelement <2 x float> %465, float %383, i64 1, !dbg !59
+  %467 = fmul <2 x float> %466, %464, !dbg !59
+  %468 = insertelement <2 x i16> poison, i16 %195, i64 0, !dbg !32
+  %469 = insertelement <2 x i16> %468, i16 %443, i64 1, !dbg !32
+  %470 = bitcast <2 x i16> %469 to <2 x bfloat>, !dbg !32
+  %471 = fpext <2 x bfloat> %470 to <2 x float>, !dbg !58
+  %472 = insertelement <2 x float> poison, float %401, i64 0, !dbg !59
+  %473 = insertelement <2 x float> %472, float %377, i64 1, !dbg !59
+  %474 = fmul <2 x float> %473, %471, !dbg !59
+  %475 = insertelement <2 x i16> poison, i16 %197, i64 0, !dbg !32
+  %476 = insertelement <2 x i16> %475, i16 %445, i64 1, !dbg !32
+  %477 = bitcast <2 x i16> %476 to <2 x bfloat>, !dbg !32
+  %478 = fpext <2 x bfloat> %477 to <2 x float>, !dbg !58
+  %479 = insertelement <2 x float> poison, float %399, i64 0, !dbg !59
+  %480 = insertelement <2 x float> %479, float %371, i64 1, !dbg !59
+  %481 = fmul <2 x float> %480, %478, !dbg !59
+  %482 = insertelement <2 x i16> poison, i16 %199, i64 0, !dbg !32
+  %483 = insertelement <2 x i16> %482, i16 %447, i64 1, !dbg !32
+  %484 = bitcast <2 x i16> %483 to <2 x bfloat>, !dbg !32
+  %485 = fpext <2 x bfloat> %484 to <2 x float>, !dbg !58
+  %486 = insertelement <2 x float> poison, float %397, i64 0, !dbg !59
+  %487 = insertelement <2 x float> %486, float %365, i64 1, !dbg !59
+  %488 = fmul <2 x float> %487, %485, !dbg !59
+  %489 = insertelement <2 x i16> poison, i16 %201, i64 0, !dbg !32
+  %490 = insertelement <2 x i16> %489, i16 %449, i64 1, !dbg !32
+  %491 = bitcast <2 x i16> %490 to <2 x bfloat>, !dbg !32
+  %492 = fpext <2 x bfloat> %491 to <2 x float>, !dbg !58
+  %493 = insertelement <2 x float> poison, float %395, i64 0, !dbg !59
+  %494 = insertelement <2 x float> %493, float %359, i64 1, !dbg !59
+  %495 = fmul <2 x float> %494, %492, !dbg !59
+  %496 = insertelement <2 x i16> poison, i16 %203, i64 0, !dbg !32
+  %497 = insertelement <2 x i16> %496, i16 %451, i64 1, !dbg !32
+  %498 = bitcast <2 x i16> %497 to <2 x bfloat>, !dbg !32
+  %499 = fpext <2 x bfloat> %498 to <2 x float>, !dbg !58
+  %500 = insertelement <2 x float> poison, float %393, i64 0, !dbg !59
+  %501 = insertelement <2 x float> %500, float %353, i64 1, !dbg !59
+  %502 = fmul <2 x float> %501, %499, !dbg !59
+  %503 = insertelement <2 x i16> poison, i16 %205, i64 0, !dbg !32
+  %504 = insertelement <2 x i16> %503, i16 %453, i64 1, !dbg !32
+  %505 = bitcast <2 x i16> %504 to <2 x bfloat>, !dbg !32
+  %506 = fpext <2 x bfloat> %505 to <2 x float>, !dbg !58
+  %507 = insertelement <2 x float> poison, float %391, i64 0, !dbg !59
+  %508 = insertelement <2 x float> %507, float %347, i64 1, !dbg !59
+  %509 = fmul <2 x float> %508, %506, !dbg !59
+  %shift = shufflevector <2 x float> %460, <2 x float> poison, <2 x i32> <i32 1, i32 poison>, !dbg !60
+  %foldExtExtBinop = fadd <2 x float> %460, %shift, !dbg !60
+  %510 = extractelement <2 x float> %foldExtExtBinop, i64 0, !dbg !60
+  %shift66 = shufflevector <2 x float> %467, <2 x float> poison, <2 x i32> <i32 1, i32 poison>, !dbg !60
+  %foldExtExtBinop67 = fadd <2 x float> %467, %shift66, !dbg !60
+  %511 = extractelement <2 x float> %foldExtExtBinop67, i64 0, !dbg !60
+  %shift69 = shufflevector <2 x float> %474, <2 x float> poison, <2 x i32> <i32 1, i32 poison>, !dbg !60
+  %foldExtExtBinop70 = fadd <2 x float> %474, %shift69, !dbg !60
+  %512 = extractelement <2 x float> %foldExtExtBinop70, i64 0, !dbg !60
+  %shift72 = shufflevector <2 x float> %481, <2 x float> poison, <2 x i32> <i32 1, i32 poison>, !dbg !60
+  %foldExtExtBinop73 = fadd <2 x float> %481, %shift72, !dbg !60
+  %513 = extractelement <2 x float> %foldExtExtBinop73, i64 0, !dbg !60
+  %shift75 = shufflevector <2 x float> %488, <2 x float> poison, <2 x i32> <i32 1, i32 poison>, !dbg !60
+  %foldExtExtBinop76 = fadd <2 x float> %488, %shift75, !dbg !60
+  %514 = extractelement <2 x float> %foldExtExtBinop76, i64 0, !dbg !60
+  %shift78 = shufflevector <2 x float> %495, <2 x float> poison, <2 x i32> <i32 1, i32 poison>, !dbg !60
+  %foldExtExtBinop79 = fadd <2 x float> %495, %shift78, !dbg !60
+  %515 = extractelement <2 x float> %foldExtExtBinop79, i64 0, !dbg !60
+  %shift81 = shufflevector <2 x float> %502, <2 x float> poison, <2 x i32> <i32 1, i32 poison>, !dbg !60
+  %foldExtExtBinop82 = fadd <2 x float> %502, %shift81, !dbg !60
+  %516 = extractelement <2 x float> %foldExtExtBinop82, i64 0, !dbg !60
+  %shift84 = shufflevector <2 x float> %509, <2 x float> poison, <2 x i32> <i32 1, i32 poison>, !dbg !60
+  %foldExtExtBinop85 = fadd <2 x float> %509, %shift84, !dbg !60
+  %517 = extractelement <2 x float> %foldExtExtBinop85, i64 0, !dbg !60
+  %518 = getelementptr bfloat, ptr addrspace(1) %4, i64 %36, !dbg !61
+  %519 = getelementptr bfloat, ptr addrspace(1) %4, i64 %38, !dbg !61
+  %520 = getelementptr bfloat, ptr addrspace(1) %4, i64 %40, !dbg !61
+  %521 = getelementptr bfloat, ptr addrspace(1) %4, i64 %42, !dbg !61
+  %522 = getelementptr bfloat, ptr addrspace(1) %4, i64 %44, !dbg !61
+  %523 = getelementptr bfloat, ptr addrspace(1) %4, i64 %46, !dbg !61
+  %524 = getelementptr bfloat, ptr addrspace(1) %4, i64 %48, !dbg !61
+  %525 = getelementptr bfloat, ptr addrspace(1) %4, i64 %50, !dbg !61
+  %526 = fptrunc float %510 to bfloat, !dbg !62
+  %527 = fptrunc float %511 to bfloat, !dbg !62
+  %528 = fptrunc float %512 to bfloat, !dbg !62
+  %529 = fptrunc float %513 to bfloat, !dbg !62
+  %530 = fptrunc float %514 to bfloat, !dbg !62
+  %531 = fptrunc float %515 to bfloat, !dbg !62
+  %532 = fptrunc float %516 to bfloat, !dbg !62
+  %533 = fptrunc float %517 to bfloat, !dbg !62
+  %534 = bitcast bfloat %526 to i16, !dbg !62
+  tail call void asm sideeffect "@$2 st.global.b16 [ $1 + 0 ], { $0 };", "c,l,b"(i16 %534, ptr addrspace(1) %518, i1 %88) #4, !dbg !62
+  %535 = bitcast bfloat %527 to i16, !dbg !62
+  tail call void asm sideeffect "@$2 st.global.b16 [ $1 + 0 ], { $0 };", "c,l,b"(i16 %535, ptr addrspace(1) %519, i1 %91) #4, !dbg !62
+  %536 = bitcast bfloat %528 to i16, !dbg !62
+  tail call void asm sideeffect "@$2 st.global.b16 [ $1 + 0 ], { $0 };", "c,l,b"(i16 %536, ptr addrspace(1) %520, i1 %94) #4, !dbg !62
+  %537 = bitcast bfloat %529 to i16, !dbg !62
+  tail call void asm sideeffect "@$2 st.global.b16 [ $1 + 0 ], { $0 };", "c,l,b"(i16 %537, ptr addrspace(1) %521, i1 %97) #4, !dbg !62
+  %538 = bitcast bfloat %530 to i16, !dbg !62
+  tail call void asm sideeffect "@$2 st.global.b16 [ $1 + 0 ], { $0 };", "c,l,b"(i16 %538, ptr addrspace(1) %522, i1 %100) #4, !dbg !62
+  %539 = bitcast bfloat %531 to i16, !dbg !62
+  tail call void asm sideeffect "@$2 st.global.b16 [ $1 + 0 ], { $0 };", "c,l,b"(i16 %539, ptr addrspace(1) %523, i1 %103) #4, !dbg !62
+  %540 = bitcast bfloat %532 to i16, !dbg !62
+  tail call void asm sideeffect "@$2 st.global.b16 [ $1 + 0 ], { $0 };", "c,l,b"(i16 %540, ptr addrspace(1) %524, i1 %106) #4, !dbg !62
+  %541 = bitcast bfloat %533 to i16, !dbg !62
+  tail call void asm sideeffect "@$2 st.global.b16 [ $1 + 0 ], { $0 };", "c,l,b"(i16 %541, ptr addrspace(1) %525, i1 %109) #4, !dbg !62
+  ret void, !dbg !63
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef range(i32 0, 2147483647) i32 @llvm.nvvm.read.ptx.sreg.ctaid.x() #2
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef range(i32 0, 1024) i32 @llvm.nvvm.read.ptx.sreg.tid.x() #2
+
+; Function Attrs: convergent nocallback nounwind
+declare void @llvm.nvvm.barrier.cta.sync.aligned.all(i32) #3
+
+attributes #0 = { noreturn }
+attributes #1 = { "nvvm.reqntid"="128" }
+attributes #2 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #3 = { convergent nocallback nounwind }
+attributes #4 = { nounwind }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!2, !3}
+!llvm.ident = !{!4}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C, file: !1, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: LineTablesOnly)
+!1 = !DIFile(filename: "cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py", directory: "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm")
+!2 = !{i32 2, !"Debug Info Version", i32 3}
+!3 = !{i32 4, !"nvvm-reflect-ftz", i32 1}
+!4 = !{!"clang version 3.8.0 (tags/RELEASE_380/final)"}
+!5 = !DISubprogram(name: "__assertfail", linkageName: "__assertfail", scope: !6, file: !6, type: !7, spFlags: DISPFlagOptimized)
+!6 = !DIFile(filename: "<unknown>", directory: "")
+!7 = !DISubroutineType(cc: DW_CC_normal, types: !8)
+!8 = !{}
+!9 = distinct !DISubprogram(name: "triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0", linkageName: "triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0", scope: !1, file: !1, line: 18, type: !7, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0)
+!10 = !DILocation(line: 19, column: 28, scope: !9)
+!11 = !DILocation(line: 19, column: 33, scope: !9)
+!12 = !DILocation(line: 20, column: 36, scope: !9)
+!13 = !DILocation(line: 20, column: 23, scope: !9)
+!14 = !DILocation(line: 23, column: 21, scope: !9)
+!15 = !DILocation(line: 26, column: 30, scope: !9)
+!16 = !DILocation(line: 23, column: 28, scope: !9)
+!17 = !DILocation(line: 26, column: 35, scope: !9)
+!18 = !DILocation(line: 27, column: 30, scope: !9)
+!19 = !DILocation(line: 21, column: 21, scope: !9)
+!20 = !DILocation(line: 27, column: 35, scope: !9)
+!21 = !DILocation(line: 30, column: 18, scope: !9)
+!22 = !DILocation(line: 31, column: 32, scope: !9)
+!23 = !DILocation(line: 32, column: 28, scope: !9)
+!24 = !DILocation(line: 32, column: 44, scope: !9)
+!25 = !DILocation(line: 32, column: 37, scope: !9)
+!26 = !DILocation(line: 32, column: 52, scope: !9)
+!27 = !DILocation(line: 32, column: 62, scope: !9)
+!28 = !DILocation(line: 24, column: 19, scope: !9)
+!29 = !DILocation(line: 33, column: 39, scope: !9)
+!30 = !DILocation(line: 40, column: 35, scope: !9)
+!31 = !DILocation(line: 33, column: 30, scope: !9)
+!32 = !DILocation(line: 33, column: 46, scope: !9)
+!33 = !DILocation(line: 38, column: 31, scope: !9)
+!34 = !DILocation(line: 38, column: 18, scope: !9)
+!35 = !DILocation(line: 39, column: 19, scope: !9)
+!36 = !DILocation(line: 40, column: 31, scope: !9)
+!37 = !DILocation(line: 40, column: 68, scope: !9)
+!38 = !DILocation(line: 40, column: 60, scope: !9)
+!39 = !DILocation(line: 44, column: 20, scope: !9)
+!40 = !DILocation(line: 47, column: 47, scope: !9)
+!41 = !DILocation(line: 47, column: 31, scope: !9)
+!42 = !DILocation(line: 47, column: 81, scope: !9)
+!43 = !DILocation(line: 47, column: 73, scope: !9)
+!44 = !DILocation(line: 51, column: 34, scope: !9)
+!45 = !DILocation(line: 52, column: 28, scope: !9)
+!46 = !DILocation(line: 52, column: 46, scope: !9)
+!47 = !DILocation(line: 52, column: 38, scope: !9)
+!48 = !DILocation(line: 52, column: 54, scope: !9)
+!49 = !DILocation(line: 52, column: 64, scope: !9)
+!50 = !DILocation(line: 40, column: 119, scope: !9)
+!51 = !DILocation(line: 41, column: 13, scope: !9)
+!52 = !DILocation(line: 47, column: 132, scope: !9)
+!53 = !DILocation(line: 0, scope: !9)
+!54 = !DILocation(line: 26, column: 75, scope: !9)
+!55 = !DILocation(line: 53, column: 40, scope: !9)
+!56 = !DILocation(line: 53, column: 31, scope: !9)
+!57 = !DILocation(line: 53, column: 48, scope: !9)
+!58 = !DILocation(line: 33, column: 86, scope: !9)
+!59 = !DILocation(line: 34, column: 18, scope: !9)
+!60 = !DILocation(line: 55, column: 19, scope: !9)
+!61 = !DILocation(line: 56, column: 25, scope: !9)
+!62 = !DILocation(line: 56, column: 37, scope: !9)
+!63 = !DILocation(line: 56, column: 4, scope: !9)

SpecForge-ext/cache/compiled_kernels/triton/2/2TU6ZCF6AOXLWQQED5J7FS5ZXMYK7TIOQ6T2MLB767275BROXJCA/triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0.ptx

@@ -0,0 +1,1534 @@
+//
+// Generated by LLVM NVPTX Back-End
+//
+
+.version 8.7
+.target sm_90a
+.address_size 64
+
+	// .globl	triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0 // -- Begin function triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0
+.extern .func __assertfail
+(
+	.param .b64 __assertfail_param_0,
+	.param .b64 __assertfail_param_1,
+	.param .b32 __assertfail_param_2,
+	.param .b64 __assertfail_param_3,
+	.param .b64 __assertfail_param_4
+)
+.noreturn;
+.global .align 1 .b8 assertFunc_1[8] = {117, 110, 107, 110, 111, 119, 110};
+.global .align 1 .b8 assertFile_1[114] = {47, 119, 111, 114, 107, 115, 112, 97, 99, 101, 47, 104, 97, 110, 114, 117, 105, 47, 83, 112, 101, 99, 70, 111, 114, 103, 101, 45, 101, 120, 116, 47, 99, 97, 99, 104, 101, 47, 99, 111, 109, 112, 105, 108, 101, 100, 95, 107, 101, 114, 110, 101, 108, 115, 47, 118, 109, 47, 99, 118, 109, 55, 54, 107, 116, 106, 97, 119, 117, 109, 115, 106, 109, 113, 97, 119, 108, 104, 108, 105, 107, 53, 119, 98, 104, 120, 54, 104, 114, 105, 122, 53, 99, 103, 114, 97, 55, 53, 52, 103, 115, 114, 115, 122, 118, 108, 112, 117, 117, 117, 46, 112, 121};
+.global .align 1 .b8 assertMessage_1[38] = {105, 110, 100, 101, 120, 32, 111, 117, 116, 32, 111, 102, 32, 98, 111, 117, 110, 100, 115, 58, 32, 48, 32, 60, 61, 32, 116, 109, 112, 50, 53, 32, 60, 32, 107, 115, 52};
+.global .align 1 .b8 assertFunc_0[8] = {117, 110, 107, 110, 111, 119, 110};
+.global .align 1 .b8 assertFile_0[114] = {47, 119, 111, 114, 107, 115, 112, 97, 99, 101, 47, 104, 97, 110, 114, 117, 105, 47, 83, 112, 101, 99, 70, 111, 114, 103, 101, 45, 101, 120, 116, 47, 99, 97, 99, 104, 101, 47, 99, 111, 109, 112, 105, 108, 101, 100, 95, 107, 101, 114, 110, 101, 108, 115, 47, 118, 109, 47, 99, 118, 109, 55, 54, 107, 116, 106, 97, 119, 117, 109, 115, 106, 109, 113, 97, 119, 108, 104, 108, 105, 107, 53, 119, 98, 104, 120, 54, 104, 114, 105, 122, 53, 99, 103, 114, 97, 55, 53, 52, 103, 115, 114, 115, 122, 118, 108, 112, 117, 117, 117, 46, 112, 121};
+.global .align 1 .b8 assertMessage_0[37] = {105, 110, 100, 101, 120, 32, 111, 117, 116, 32, 111, 102, 32, 98, 111, 117, 110, 100, 115, 58, 32, 48, 32, 60, 61, 32, 116, 109, 112, 53, 32, 60, 32, 107, 115, 50};
+                                        // @triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0
+.visible .entry triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0(
+	.param .u64 .ptr .global .align 1 triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0_param_0,
+	.param .u64 .ptr .global .align 1 triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0_param_1,
+	.param .u64 .ptr .global .align 1 triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0_param_2,
+	.param .u64 .ptr .global .align 1 triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0_param_3,
+	.param .u64 .ptr .global .align 1 triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0_param_4,
+	.param .u64 triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0_param_5,
+	.param .u64 triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0_param_6,
+	.param .u64 triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0_param_7,
+	.param .u64 triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0_param_8,
+	.param .u64 triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0_param_9,
+	.param .u32 triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0_param_10,
+	.param .u64 .ptr .global .align 1 triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0_param_11,
+	.param .u64 .ptr .global .align 1 triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0_param_12
+)
+.reqntid 128
+{
+	.reg .pred 	%p<179>;
+	.reg .b16 	%rs<165>;
+	.reg .b32 	%r<160>;
+	.reg .b64 	%rd<500>;
+	.loc	1 18 0                          // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:18:0
+$L__func_begin0:
+	.loc	1 18 0                          // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:18:0
+
+// %bb.0:
+	ld.param.b64 	%rd103, [triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0_param_5];
+$L__tmp0:
+	.loc	1 19 28                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:19:28
+	mov.u32 	%r26, %ctaid.x;
+	.loc	1 19 33                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:19:33
+	shl.b32 	%r27, %r26, 10;
+	.loc	1 20 36                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:20:36
+	mov.u32 	%r28, %tid.x;
+	shl.b32 	%r29, %r28, 3;
+	and.b32 	%r30, %r29, 1016;
+	.loc	1 20 23                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:20:23
+	or.b32 	%r1, %r30, %r27;
+	or.b32 	%r2, %r1, 1;
+	or.b32 	%r3, %r1, 2;
+	.loc	1 23 21                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:23:21
+	cvt.s64.s32 	%rd7, %r2;
+	cvt.s64.s32 	%rd8, %r1;
+	or.b64 	%rd108, %rd8, %rd103;
+	and.b64 	%rd109, %rd108, -4294967296;
+	setp.ne.b64 	%p9, %rd109, 0;
+	@%p9 bra 	$L__BB0_2;
+	bra.uni 	$L__BB0_1;
+$L__BB0_2:
+	div.s64 	%rd484, %rd8, %rd103;
+	bra.uni 	$L__BB0_3;
+$L__BB0_1:
+	cvt.u32.u64 	%r31, %rd103;
+	cvt.u32.u64 	%r32, %rd8;
+	div.u32 	%r33, %r32, %r31;
+	cvt.u64.u32 	%rd484, %r33;
+$L__BB0_3:
+	.loc	1 0 0                           // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:0
+	or.b32 	%r4, %r1, 3;
+	.loc	1 23 21                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:23:21
+	cvt.s64.s32 	%rd6, %r3;
+	or.b64 	%rd110, %rd7, %rd103;
+	and.b64 	%rd111, %rd110, -4294967296;
+	setp.ne.b64 	%p10, %rd111, 0;
+	@%p10 bra 	$L__BB0_5;
+	bra.uni 	$L__BB0_4;
+$L__BB0_5:
+	div.s64 	%rd485, %rd7, %rd103;
+	bra.uni 	$L__BB0_6;
+$L__BB0_4:
+	cvt.u32.u64 	%r34, %rd103;
+	cvt.u32.u64 	%r35, %rd7;
+	div.u32 	%r36, %r35, %r34;
+	cvt.u64.u32 	%rd485, %r36;
+$L__BB0_6:
+	.loc	1 0 0                           // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:0
+	or.b32 	%r5, %r1, 4;
+	.loc	1 23 21                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:23:21
+	cvt.s64.s32 	%rd5, %r4;
+	or.b64 	%rd112, %rd6, %rd103;
+	and.b64 	%rd113, %rd112, -4294967296;
+	setp.ne.b64 	%p11, %rd113, 0;
+	@%p11 bra 	$L__BB0_8;
+	bra.uni 	$L__BB0_7;
+$L__BB0_8:
+	div.s64 	%rd486, %rd6, %rd103;
+	bra.uni 	$L__BB0_9;
+$L__BB0_7:
+	cvt.u32.u64 	%r37, %rd103;
+	cvt.u32.u64 	%r38, %rd6;
+	div.u32 	%r39, %r38, %r37;
+	cvt.u64.u32 	%rd486, %r39;
+$L__BB0_9:
+	.loc	1 0 0                           // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:0
+	or.b32 	%r6, %r1, 5;
+	.loc	1 23 21                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:23:21
+	cvt.s64.s32 	%rd4, %r5;
+	or.b64 	%rd114, %rd5, %rd103;
+	and.b64 	%rd115, %rd114, -4294967296;
+	setp.ne.b64 	%p12, %rd115, 0;
+	@%p12 bra 	$L__BB0_11;
+	bra.uni 	$L__BB0_10;
+$L__BB0_11:
+	div.s64 	%rd487, %rd5, %rd103;
+	bra.uni 	$L__BB0_12;
+$L__BB0_10:
+	cvt.u32.u64 	%r40, %rd103;
+	cvt.u32.u64 	%r41, %rd5;
+	div.u32 	%r42, %r41, %r40;
+	cvt.u64.u32 	%rd487, %r42;
+$L__BB0_12:
+	.loc	1 0 0                           // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:0
+	or.b32 	%r7, %r1, 6;
+	.loc	1 23 21                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:23:21
+	cvt.s64.s32 	%rd3, %r6;
+	or.b64 	%rd116, %rd4, %rd103;
+	and.b64 	%rd117, %rd116, -4294967296;
+	setp.ne.b64 	%p13, %rd117, 0;
+	@%p13 bra 	$L__BB0_14;
+	bra.uni 	$L__BB0_13;
+$L__BB0_14:
+	div.s64 	%rd488, %rd4, %rd103;
+	bra.uni 	$L__BB0_15;
+$L__BB0_13:
+	cvt.u32.u64 	%r43, %rd103;
+	cvt.u32.u64 	%r44, %rd4;
+	div.u32 	%r45, %r44, %r43;
+	cvt.u64.u32 	%rd488, %r45;
+$L__BB0_15:
+	.loc	1 0 0                           // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:0
+	or.b32 	%r8, %r1, 7;
+	.loc	1 23 21                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:23:21
+	cvt.s64.s32 	%rd2, %r7;
+	or.b64 	%rd118, %rd3, %rd103;
+	and.b64 	%rd119, %rd118, -4294967296;
+	setp.ne.b64 	%p14, %rd119, 0;
+	@%p14 bra 	$L__BB0_17;
+	bra.uni 	$L__BB0_16;
+$L__BB0_17:
+	div.s64 	%rd489, %rd3, %rd103;
+	bra.uni 	$L__BB0_18;
+$L__BB0_16:
+	cvt.u32.u64 	%r46, %rd103;
+	cvt.u32.u64 	%r47, %rd3;
+	div.u32 	%r48, %r47, %r46;
+	cvt.u64.u32 	%rd489, %r48;
+$L__BB0_18:
+	cvt.s64.s32 	%rd1, %r8;
+	or.b64 	%rd120, %rd2, %rd103;
+	and.b64 	%rd121, %rd120, -4294967296;
+	setp.ne.b64 	%p15, %rd121, 0;
+	@%p15 bra 	$L__BB0_20;
+	bra.uni 	$L__BB0_19;
+$L__BB0_20:
+	div.s64 	%rd490, %rd2, %rd103;
+	bra.uni 	$L__BB0_21;
+$L__BB0_19:
+	cvt.u32.u64 	%r49, %rd103;
+	cvt.u32.u64 	%r50, %rd2;
+	div.u32 	%r51, %r50, %r49;
+	cvt.u64.u32 	%rd490, %r51;
+$L__BB0_21:
+	.loc	1 0 21                          // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:0:21
+	ld.param.b64 	%rd104, [triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0_param_6];
+	.loc	1 23 21                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:23:21
+	or.b64 	%rd122, %rd1, %rd103;
+	and.b64 	%rd123, %rd122, -4294967296;
+	setp.ne.b64 	%p16, %rd123, 0;
+	@%p16 bra 	$L__BB0_23;
+	bra.uni 	$L__BB0_22;
+$L__BB0_23:
+	div.s64 	%rd491, %rd1, %rd103;
+	bra.uni 	$L__BB0_24;
+$L__BB0_22:
+	cvt.u32.u64 	%r52, %rd103;
+	cvt.u32.u64 	%r53, %rd1;
+	div.u32 	%r54, %r53, %r52;
+	cvt.u64.u32 	%rd491, %r54;
+$L__BB0_24:
+	.loc	1 23 28                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:23:28
+	or.b64 	%rd124, %rd484, %rd104;
+	and.b64 	%rd125, %rd124, -4294967296;
+	setp.ne.b64 	%p17, %rd125, 0;
+	@%p17 bra 	$L__BB0_26;
+	bra.uni 	$L__BB0_25;
+$L__BB0_26:
+	rem.s64 	%rd492, %rd484, %rd104;
+	bra.uni 	$L__BB0_27;
+$L__BB0_25:
+	cvt.u32.u64 	%r55, %rd104;
+	cvt.u32.u64 	%r56, %rd484;
+	rem.u32 	%r57, %r56, %r55;
+	cvt.u64.u32 	%rd492, %r57;
+$L__BB0_27:
+	or.b64 	%rd126, %rd485, %rd104;
+	and.b64 	%rd127, %rd126, -4294967296;
+	setp.ne.b64 	%p18, %rd127, 0;
+	@%p18 bra 	$L__BB0_29;
+	bra.uni 	$L__BB0_28;
+$L__BB0_29:
+	rem.s64 	%rd493, %rd485, %rd104;
+	bra.uni 	$L__BB0_30;
+$L__BB0_28:
+	cvt.u32.u64 	%r58, %rd104;
+	cvt.u32.u64 	%r59, %rd485;
+	rem.u32 	%r60, %r59, %r58;
+	cvt.u64.u32 	%rd493, %r60;
+$L__BB0_30:
+	or.b64 	%rd128, %rd486, %rd104;
+	and.b64 	%rd129, %rd128, -4294967296;
+	setp.ne.b64 	%p19, %rd129, 0;
+	@%p19 bra 	$L__BB0_32;
+	bra.uni 	$L__BB0_31;
+$L__BB0_32:
+	rem.s64 	%rd494, %rd486, %rd104;
+	bra.uni 	$L__BB0_33;
+$L__BB0_31:
+	cvt.u32.u64 	%r61, %rd104;
+	cvt.u32.u64 	%r62, %rd486;
+	rem.u32 	%r63, %r62, %r61;
+	cvt.u64.u32 	%rd494, %r63;
+$L__BB0_33:
+	or.b64 	%rd130, %rd487, %rd104;
+	and.b64 	%rd131, %rd130, -4294967296;
+	setp.ne.b64 	%p20, %rd131, 0;
+	@%p20 bra 	$L__BB0_35;
+	bra.uni 	$L__BB0_34;
+$L__BB0_35:
+	rem.s64 	%rd495, %rd487, %rd104;
+	bra.uni 	$L__BB0_36;
+$L__BB0_34:
+	cvt.u32.u64 	%r64, %rd104;
+	cvt.u32.u64 	%r65, %rd487;
+	rem.u32 	%r66, %r65, %r64;
+	cvt.u64.u32 	%rd495, %r66;
+$L__BB0_36:
+	or.b64 	%rd132, %rd488, %rd104;
+	and.b64 	%rd133, %rd132, -4294967296;
+	setp.ne.b64 	%p21, %rd133, 0;
+	@%p21 bra 	$L__BB0_38;
+	bra.uni 	$L__BB0_37;
+$L__BB0_38:
+	rem.s64 	%rd496, %rd488, %rd104;
+	bra.uni 	$L__BB0_39;
+$L__BB0_37:
+	cvt.u32.u64 	%r67, %rd104;
+	cvt.u32.u64 	%r68, %rd488;
+	rem.u32 	%r69, %r68, %r67;
+	cvt.u64.u32 	%rd496, %r69;
+$L__BB0_39:
+	or.b64 	%rd134, %rd489, %rd104;
+	and.b64 	%rd135, %rd134, -4294967296;
+	setp.ne.b64 	%p22, %rd135, 0;
+	@%p22 bra 	$L__BB0_41;
+	bra.uni 	$L__BB0_40;
+$L__BB0_41:
+	rem.s64 	%rd497, %rd489, %rd104;
+	bra.uni 	$L__BB0_42;
+$L__BB0_40:
+	cvt.u32.u64 	%r70, %rd104;
+	cvt.u32.u64 	%r71, %rd489;
+	rem.u32 	%r72, %r71, %r70;
+	cvt.u64.u32 	%rd497, %r72;
+$L__BB0_42:
+	or.b64 	%rd136, %rd490, %rd104;
+	and.b64 	%rd137, %rd136, -4294967296;
+	setp.ne.b64 	%p23, %rd137, 0;
+	@%p23 bra 	$L__BB0_44;
+	bra.uni 	$L__BB0_43;
+$L__BB0_44:
+	rem.s64 	%rd498, %rd490, %rd104;
+	bra.uni 	$L__BB0_45;
+$L__BB0_43:
+	cvt.u32.u64 	%r73, %rd104;
+	cvt.u32.u64 	%r74, %rd490;
+	rem.u32 	%r75, %r74, %r73;
+	cvt.u64.u32 	%rd498, %r75;
+$L__BB0_45:
+	.loc	1 0 28                          // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:0:28
+	ld.param.b32 	%r25, [triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0_param_10];
+	ld.param.b64 	%rd105, [triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0_param_7];
+	ld.param.b64 	%rd99, [triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0_param_1];
+	ld.param.b64 	%rd98, [triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0_param_0];
+	.loc	1 23 28                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:23:28
+	or.b64 	%rd138, %rd491, %rd104;
+	and.b64 	%rd139, %rd138, -4294967296;
+	setp.ne.b64 	%p24, %rd139, 0;
+	@%p24 bra 	$L__BB0_47;
+	bra.uni 	$L__BB0_46;
+$L__BB0_47:
+	rem.s64 	%rd499, %rd491, %rd104;
+	bra.uni 	$L__BB0_48;
+$L__BB0_46:
+	cvt.u32.u64 	%r76, %rd104;
+	cvt.u32.u64 	%r77, %rd491;
+	rem.u32 	%r78, %r77, %r76;
+	cvt.u64.u32 	%rd499, %r78;
+$L__BB0_48:
+	.loc	1 26 30                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:26:30
+	shl.b64 	%rd196, %rd8, 1;
+	add.s64 	%rd141, %rd98, %rd196;
+	shl.b64 	%rd197, %rd7, 1;
+	add.s64 	%rd144, %rd98, %rd197;
+	shl.b64 	%rd198, %rd6, 1;
+	add.s64 	%rd147, %rd98, %rd198;
+	shl.b64 	%rd199, %rd5, 1;
+	add.s64 	%rd150, %rd98, %rd199;
+	shl.b64 	%rd200, %rd4, 1;
+	add.s64 	%rd153, %rd98, %rd200;
+	shl.b64 	%rd201, %rd3, 1;
+	add.s64 	%rd156, %rd98, %rd201;
+	shl.b64 	%rd202, %rd2, 1;
+	add.s64 	%rd159, %rd98, %rd202;
+	shl.b64 	%rd203, %rd1, 1;
+	add.s64 	%rd162, %rd98, %rd203;
+	.loc	1 26 35                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:26:35
+	// begin inline asm
+	mov.u64 %rd140, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd140, 1.0;
+	// end inline asm
+	.loc	1 27 30                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:27:30
+	shl.b64 	%rd204, %rd492, 3;
+	add.s64 	%rd166, %rd99, %rd204;
+	shl.b64 	%rd205, %rd493, 3;
+	add.s64 	%rd170, %rd99, %rd205;
+	shl.b64 	%rd206, %rd494, 3;
+	add.s64 	%rd174, %rd99, %rd206;
+	shl.b64 	%rd207, %rd495, 3;
+	add.s64 	%rd178, %rd99, %rd207;
+	shl.b64 	%rd208, %rd496, 3;
+	add.s64 	%rd182, %rd99, %rd208;
+	shl.b64 	%rd209, %rd497, 3;
+	add.s64 	%rd186, %rd99, %rd209;
+	shl.b64 	%rd210, %rd498, 3;
+	add.s64 	%rd190, %rd99, %rd210;
+	shl.b64 	%rd211, %rd499, 3;
+	add.s64 	%rd194, %rd99, %rd211;
+	.loc	1 21 21                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:21:21
+	setp.lt.s32 	%p8, %r8, %r25;
+	setp.lt.s32 	%p7, %r7, %r25;
+	setp.lt.s32 	%p6, %r6, %r25;
+	setp.lt.s32 	%p5, %r5, %r25;
+	setp.lt.s32 	%p4, %r4, %r25;
+	setp.lt.s32 	%p3, %r3, %r25;
+	setp.lt.s32 	%p2, %r2, %r25;
+	setp.lt.s32 	%p1, %r1, %r25;
+	.loc	1 26 35                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:26:35
+	// begin inline asm
+	mov.u16 %rs33, 0x0;
+	@%p1 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs33 }, [ %rd141 + 0 ], %rd140;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd143, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd143, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs34, 0x0;
+	@%p2 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs34 }, [ %rd144 + 0 ], %rd143;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd146, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd146, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs35, 0x0;
+	@%p3 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs35 }, [ %rd147 + 0 ], %rd146;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd149, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd149, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs36, 0x0;
+	@%p4 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs36 }, [ %rd150 + 0 ], %rd149;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd152, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd152, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs37, 0x0;
+	@%p5 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs37 }, [ %rd153 + 0 ], %rd152;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd155, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd155, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs38, 0x0;
+	@%p6 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs38 }, [ %rd156 + 0 ], %rd155;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd158, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd158, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs39, 0x0;
+	@%p7 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs39 }, [ %rd159 + 0 ], %rd158;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd161, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd161, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs40, 0x0;
+	@%p8 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs40 }, [ %rd162 + 0 ], %rd161;
+	// end inline asm
+	.loc	1 27 35                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:27:35
+	// begin inline asm
+	mov.u64 %rd164, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd164, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd165, 0x0;
+	@%p1 ld.global.L1::evict_last.L2::cache_hint.b64 { %rd165 }, [ %rd166 + 0 ], %rd164;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd168, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd168, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd169, 0x0;
+	@%p2 ld.global.L1::evict_last.L2::cache_hint.b64 { %rd169 }, [ %rd170 + 0 ], %rd168;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd172, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd172, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd173, 0x0;
+	@%p3 ld.global.L1::evict_last.L2::cache_hint.b64 { %rd173 }, [ %rd174 + 0 ], %rd172;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd176, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd176, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd177, 0x0;
+	@%p4 ld.global.L1::evict_last.L2::cache_hint.b64 { %rd177 }, [ %rd178 + 0 ], %rd176;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd180, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd180, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd181, 0x0;
+	@%p5 ld.global.L1::evict_last.L2::cache_hint.b64 { %rd181 }, [ %rd182 + 0 ], %rd180;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd184, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd184, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd185, 0x0;
+	@%p6 ld.global.L1::evict_last.L2::cache_hint.b64 { %rd185 }, [ %rd186 + 0 ], %rd184;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd188, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd188, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd189, 0x0;
+	@%p7 ld.global.L1::evict_last.L2::cache_hint.b64 { %rd189 }, [ %rd190 + 0 ], %rd188;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd192, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd192, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd193, 0x0;
+	@%p8 ld.global.L1::evict_last.L2::cache_hint.b64 { %rd193 }, [ %rd194 + 0 ], %rd192;
+	// end inline asm
+	.loc	1 31 32                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:31:32
+	shr.s64 	%rd212, %rd173, 63;
+	and.b64 	%rd213, %rd212, %rd105;
+	shr.s64 	%rd214, %rd177, 63;
+	and.b64 	%rd215, %rd214, %rd105;
+	shr.s64 	%rd216, %rd165, 63;
+	and.b64 	%rd217, %rd216, %rd105;
+	shr.s64 	%rd218, %rd169, 63;
+	and.b64 	%rd219, %rd218, %rd105;
+	shr.s64 	%rd220, %rd189, 63;
+	and.b64 	%rd221, %rd220, %rd105;
+	shr.s64 	%rd222, %rd193, 63;
+	and.b64 	%rd223, %rd222, %rd105;
+	shr.s64 	%rd224, %rd181, 63;
+	and.b64 	%rd225, %rd224, %rd105;
+	shr.s64 	%rd226, %rd185, 63;
+	and.b64 	%rd227, %rd226, %rd105;
+	add.s64 	%rd78, %rd227, %rd185;
+	add.s64 	%rd77, %rd225, %rd181;
+	add.s64 	%rd80, %rd223, %rd193;
+	add.s64 	%rd79, %rd221, %rd189;
+	add.s64 	%rd74, %rd219, %rd169;
+	add.s64 	%rd73, %rd217, %rd165;
+	add.s64 	%rd76, %rd215, %rd177;
+	add.s64 	%rd75, %rd213, %rd173;
+	.loc	1 32 28                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:32:28
+	setp.lt.s64 	%p41, %rd75, 0;
+	setp.lt.s64 	%p42, %rd76, 0;
+	setp.lt.s64 	%p43, %rd73, 0;
+	setp.lt.s64 	%p44, %rd74, 0;
+	setp.lt.s64 	%p45, %rd79, 0;
+	setp.lt.s64 	%p46, %rd80, 0;
+	setp.lt.s64 	%p47, %rd77, 0;
+	setp.lt.s64 	%p48, %rd78, 0;
+	.loc	1 32 44                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:32:44
+	setp.ge.s64 	%p49, %rd75, %rd105;
+	setp.ge.s64 	%p50, %rd76, %rd105;
+	setp.ge.s64 	%p51, %rd73, %rd105;
+	setp.ge.s64 	%p52, %rd74, %rd105;
+	setp.ge.s64 	%p53, %rd79, %rd105;
+	setp.ge.s64 	%p54, %rd80, %rd105;
+	setp.ge.s64 	%p55, %rd77, %rd105;
+	setp.ge.s64 	%p56, %rd78, %rd105;
+	.loc	1 32 37                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:32:37
+	or.pred 	%p57, %p48, %p56;
+	or.pred 	%p58, %p47, %p55;
+	or.pred 	%p59, %p46, %p54;
+	or.pred 	%p60, %p45, %p53;
+	or.pred 	%p61, %p44, %p52;
+	or.pred 	%p62, %p43, %p51;
+	or.pred 	%p63, %p42, %p50;
+	or.pred 	%p64, %p41, %p49;
+	.loc	1 32 52                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:32:52
+	and.pred 	%p65, %p3, %p64;
+	selp.b16 	%rs41, 1, 0, %p65;
+	shl.b16 	%rs42, %rs41, 2;
+	and.pred 	%p66, %p4, %p63;
+	selp.b16 	%rs43, -1, 0, %p66;
+	shl.b16 	%rs44, %rs43, 3;
+	or.b16 	%rs45, %rs44, %rs42;
+	and.pred 	%p67, %p1, %p62;
+	selp.b16 	%rs46, 1, 0, %p67;
+	and.pred 	%p68, %p2, %p61;
+	selp.b16 	%rs47, -1, 0, %p68;
+	shl.b16 	%rs48, %rs47, 1;
+	or.b16 	%rs49, %rs46, %rs48;
+	and.b16 	%rs50, %rs49, 3;
+	or.b16 	%rs51, %rs50, %rs45;
+	and.b16 	%rs52, %rs51, 15;
+	and.pred 	%p69, %p7, %p60;
+	selp.b16 	%rs53, 1, 0, %p69;
+	shl.b16 	%rs54, %rs53, 2;
+	and.pred 	%p70, %p8, %p59;
+	selp.b16 	%rs55, -1, 0, %p70;
+	shl.b16 	%rs56, %rs55, 3;
+	or.b16 	%rs57, %rs56, %rs54;
+	and.pred 	%p71, %p5, %p58;
+	selp.b16 	%rs58, 1, 0, %p71;
+	and.pred 	%p72, %p6, %p57;
+	selp.b16 	%rs59, -1, 0, %p72;
+	shl.b16 	%rs60, %rs59, 1;
+	or.b16 	%rs61, %rs58, %rs60;
+	and.b16 	%rs62, %rs61, 3;
+	or.b16 	%rs63, %rs62, %rs57;
+	shl.b16 	%rs64, %rs63, 4;
+	or.b16 	%rs65, %rs52, %rs64;
+	.loc	1 32 62                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:32:62
+	and.b16 	%rs66, %rs65, 255;
+	setp.eq.b16 	%p73, %rs66, 0;
+	@%p73 bra 	$L__BB0_50;
+	bra.uni 	$L__BB0_49;
+$L__BB0_50:
+	.loc	1 0 62                          // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:0:62
+	ld.param.b64 	%rd107, [triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0_param_9];
+	ld.param.b64 	%rd106, [triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0_param_8];
+	ld.param.b64 	%rd100, [triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0_param_2];
+	.loc	1 24 19                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:24:19
+	rem.s64 	%rd88, %rd1, %rd106;
+	rem.s64 	%rd87, %rd2, %rd106;
+	rem.s64 	%rd86, %rd3, %rd106;
+	rem.s64 	%rd85, %rd4, %rd106;
+	rem.s64 	%rd84, %rd5, %rd106;
+	rem.s64 	%rd83, %rd6, %rd106;
+	rem.s64 	%rd82, %rd7, %rd106;
+	rem.s64 	%rd81, %rd8, %rd106;
+	.loc	1 32 62                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:32:62
+	bar.sync 	0;
+	.loc	1 33 39                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:33:39
+	mul.lo.s64 	%rd306, %rd73, %rd106;
+	mul.lo.s64 	%rd307, %rd74, %rd106;
+	mul.lo.s64 	%rd308, %rd75, %rd106;
+	mul.lo.s64 	%rd309, %rd76, %rd106;
+	mul.lo.s64 	%rd310, %rd77, %rd106;
+	mul.lo.s64 	%rd311, %rd78, %rd106;
+	mul.lo.s64 	%rd312, %rd79, %rd106;
+	mul.lo.s64 	%rd313, %rd80, %rd106;
+	.loc	1 33 30                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:33:30
+	shl.b64 	%rd314, %rd81, 1;
+	add.s64 	%rd315, %rd100, %rd314;
+	shl.b64 	%rd316, %rd306, 1;
+	add.s64 	%rd235, %rd315, %rd316;
+	shl.b64 	%rd317, %rd82, 1;
+	add.s64 	%rd318, %rd100, %rd317;
+	shl.b64 	%rd319, %rd307, 1;
+	add.s64 	%rd238, %rd318, %rd319;
+	shl.b64 	%rd320, %rd83, 1;
+	add.s64 	%rd321, %rd100, %rd320;
+	shl.b64 	%rd322, %rd308, 1;
+	add.s64 	%rd241, %rd321, %rd322;
+	shl.b64 	%rd323, %rd84, 1;
+	add.s64 	%rd324, %rd100, %rd323;
+	shl.b64 	%rd325, %rd309, 1;
+	add.s64 	%rd244, %rd324, %rd325;
+	shl.b64 	%rd326, %rd85, 1;
+	add.s64 	%rd327, %rd100, %rd326;
+	shl.b64 	%rd328, %rd310, 1;
+	add.s64 	%rd247, %rd327, %rd328;
+	shl.b64 	%rd329, %rd86, 1;
+	add.s64 	%rd330, %rd100, %rd329;
+	shl.b64 	%rd331, %rd311, 1;
+	add.s64 	%rd250, %rd330, %rd331;
+	shl.b64 	%rd332, %rd87, 1;
+	add.s64 	%rd333, %rd100, %rd332;
+	shl.b64 	%rd334, %rd312, 1;
+	add.s64 	%rd253, %rd333, %rd334;
+	shl.b64 	%rd335, %rd88, 1;
+	add.s64 	%rd336, %rd100, %rd335;
+	shl.b64 	%rd337, %rd313, 1;
+	add.s64 	%rd256, %rd336, %rd337;
+	.loc	1 33 46                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:33:46
+	// begin inline asm
+	mov.u64 %rd234, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd234, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs67, 0x0;
+	@%p1 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs67 }, [ %rd235 + 0 ], %rd234;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd237, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd237, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs68, 0x0;
+	@%p2 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs68 }, [ %rd238 + 0 ], %rd237;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd240, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd240, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs69, 0x0;
+	@%p3 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs69 }, [ %rd241 + 0 ], %rd240;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd243, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd243, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs70, 0x0;
+	@%p4 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs70 }, [ %rd244 + 0 ], %rd243;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd246, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd246, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs71, 0x0;
+	@%p5 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs71 }, [ %rd247 + 0 ], %rd246;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd249, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd249, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs72, 0x0;
+	@%p6 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs72 }, [ %rd250 + 0 ], %rd249;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd252, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd252, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs73, 0x0;
+	@%p7 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs73 }, [ %rd253 + 0 ], %rd252;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd255, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd255, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs74, 0x0;
+	@%p8 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs74 }, [ %rd256 + 0 ], %rd255;
+	// end inline asm
+	.loc	1 38 31                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:38:31
+	shr.u64 	%rd338, %rd106, 63;
+	add.s64 	%rd339, %rd106, %rd338;
+	shr.s64 	%rd340, %rd339, 1;
+	.loc	1 38 18                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:38:18
+	sub.s64 	%rd89, %rd106, %rd340;
+	.loc	1 39 19                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:39:19
+	setp.lt.s64 	%p106, %rd81, %rd89;
+	setp.lt.s64 	%p107, %rd82, %rd89;
+	setp.lt.s64 	%p108, %rd83, %rd89;
+	setp.lt.s64 	%p109, %rd84, %rd89;
+	setp.lt.s64 	%p110, %rd85, %rd89;
+	setp.lt.s64 	%p111, %rd86, %rd89;
+	setp.lt.s64 	%p112, %rd87, %rd89;
+	setp.lt.s64 	%p113, %rd88, %rd89;
+	.loc	1 40 35                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:40:35
+	sub.s64 	%rd341, %rd8, %rd81;
+	sub.s64 	%rd342, %rd7, %rd82;
+	sub.s64 	%rd343, %rd6, %rd83;
+	sub.s64 	%rd344, %rd5, %rd84;
+	sub.s64 	%rd345, %rd4, %rd85;
+	sub.s64 	%rd346, %rd3, %rd86;
+	sub.s64 	%rd347, %rd2, %rd87;
+	sub.s64 	%rd348, %rd1, %rd88;
+	.loc	1 40 31                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:40:31
+	shl.b64 	%rd349, %rd341, 1;
+	add.s64 	%rd350, %rd98, %rd349;
+	and.b64 	%rd351, %rd339, -2;
+	add.s64 	%rd352, %rd350, %rd351;
+	add.s64 	%rd259, %rd352, %rd314;
+	shl.b64 	%rd353, %rd342, 1;
+	add.s64 	%rd354, %rd98, %rd353;
+	add.s64 	%rd355, %rd354, %rd351;
+	add.s64 	%rd262, %rd355, %rd317;
+	shl.b64 	%rd356, %rd343, 1;
+	add.s64 	%rd357, %rd98, %rd356;
+	add.s64 	%rd358, %rd357, %rd351;
+	add.s64 	%rd265, %rd358, %rd320;
+	shl.b64 	%rd359, %rd344, 1;
+	add.s64 	%rd360, %rd98, %rd359;
+	add.s64 	%rd361, %rd360, %rd351;
+	add.s64 	%rd268, %rd361, %rd323;
+	shl.b64 	%rd362, %rd345, 1;
+	add.s64 	%rd363, %rd98, %rd362;
+	add.s64 	%rd364, %rd363, %rd351;
+	add.s64 	%rd271, %rd364, %rd326;
+	shl.b64 	%rd365, %rd346, 1;
+	add.s64 	%rd366, %rd98, %rd365;
+	add.s64 	%rd367, %rd366, %rd351;
+	add.s64 	%rd274, %rd367, %rd329;
+	shl.b64 	%rd368, %rd347, 1;
+	add.s64 	%rd369, %rd98, %rd368;
+	add.s64 	%rd370, %rd369, %rd351;
+	add.s64 	%rd277, %rd370, %rd332;
+	shl.b64 	%rd371, %rd348, 1;
+	add.s64 	%rd372, %rd98, %rd371;
+	add.s64 	%rd373, %rd372, %rd351;
+	add.s64 	%rd280, %rd373, %rd335;
+	.loc	1 40 68                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:40:68
+	and.pred 	%p82, %p1, %p106;
+	and.pred 	%p83, %p2, %p107;
+	and.pred 	%p84, %p3, %p108;
+	and.pred 	%p85, %p4, %p109;
+	and.pred 	%p86, %p5, %p110;
+	and.pred 	%p87, %p6, %p111;
+	and.pred 	%p88, %p7, %p112;
+	and.pred 	%p89, %p8, %p113;
+	.loc	1 40 60                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:40:60
+	// begin inline asm
+	mov.u64 %rd258, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd258, 1.0;
+	// end inline asm
+	mov.b16 	%rs76, 0;
+	// begin inline asm
+	mov.u16 %rs75, %rs76;
+	@%p82 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs75 }, [ %rd259 + 0 ], %rd258;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd261, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd261, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs77, %rs76;
+	@%p83 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs77 }, [ %rd262 + 0 ], %rd261;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd264, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd264, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs79, %rs76;
+	@%p84 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs79 }, [ %rd265 + 0 ], %rd264;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd267, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd267, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs81, %rs76;
+	@%p85 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs81 }, [ %rd268 + 0 ], %rd267;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd270, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd270, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs83, %rs76;
+	@%p86 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs83 }, [ %rd271 + 0 ], %rd270;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd273, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd273, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs85, %rs76;
+	@%p87 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs85 }, [ %rd274 + 0 ], %rd273;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd276, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd276, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs87, %rs76;
+	@%p88 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs87 }, [ %rd277 + 0 ], %rd276;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd279, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd279, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs89, %rs76;
+	@%p89 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs89 }, [ %rd280 + 0 ], %rd279;
+	// end inline asm
+	.loc	1 44 20                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:44:20
+	setp.ge.s64 	%p114, %rd88, %rd89;
+	setp.ge.s64 	%p115, %rd87, %rd89;
+	setp.ge.s64 	%p116, %rd86, %rd89;
+	setp.ge.s64 	%p117, %rd85, %rd89;
+	setp.ge.s64 	%p118, %rd84, %rd89;
+	setp.ge.s64 	%p119, %rd83, %rd89;
+	setp.ge.s64 	%p120, %rd82, %rd89;
+	setp.ge.s64 	%p121, %rd81, %rd89;
+	.loc	1 47 47                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:47:47
+	sub.s64 	%rd374, %rd81, %rd106;
+	sub.s64 	%rd375, %rd82, %rd106;
+	sub.s64 	%rd376, %rd83, %rd106;
+	sub.s64 	%rd377, %rd84, %rd106;
+	sub.s64 	%rd378, %rd85, %rd106;
+	sub.s64 	%rd379, %rd86, %rd106;
+	sub.s64 	%rd380, %rd87, %rd106;
+	sub.s64 	%rd381, %rd88, %rd106;
+	.loc	1 47 31                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:47:31
+	shl.b64 	%rd382, %rd374, 1;
+	add.s64 	%rd283, %rd352, %rd382;
+	shl.b64 	%rd383, %rd375, 1;
+	add.s64 	%rd286, %rd355, %rd383;
+	shl.b64 	%rd384, %rd376, 1;
+	add.s64 	%rd289, %rd358, %rd384;
+	shl.b64 	%rd385, %rd377, 1;
+	add.s64 	%rd292, %rd361, %rd385;
+	shl.b64 	%rd386, %rd378, 1;
+	add.s64 	%rd295, %rd364, %rd386;
+	shl.b64 	%rd387, %rd379, 1;
+	add.s64 	%rd298, %rd367, %rd387;
+	shl.b64 	%rd388, %rd380, 1;
+	add.s64 	%rd301, %rd370, %rd388;
+	shl.b64 	%rd389, %rd381, 1;
+	add.s64 	%rd304, %rd373, %rd389;
+	.loc	1 47 81                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:47:81
+	and.pred 	%p90, %p1, %p121;
+	and.pred 	%p91, %p2, %p120;
+	and.pred 	%p92, %p3, %p119;
+	and.pred 	%p93, %p4, %p118;
+	and.pred 	%p94, %p5, %p117;
+	and.pred 	%p95, %p6, %p116;
+	and.pred 	%p96, %p7, %p115;
+	and.pred 	%p97, %p8, %p114;
+	.loc	1 47 73                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:47:73
+	// begin inline asm
+	mov.u64 %rd282, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd282, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs91, %rs76;
+	@%p90 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs91 }, [ %rd283 + 0 ], %rd282;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd285, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd285, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs93, %rs76;
+	@%p91 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs93 }, [ %rd286 + 0 ], %rd285;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd288, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd288, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs95, %rs76;
+	@%p92 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs95 }, [ %rd289 + 0 ], %rd288;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd291, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd291, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs97, %rs76;
+	@%p93 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs97 }, [ %rd292 + 0 ], %rd291;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd294, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd294, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs99, %rs76;
+	@%p94 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs99 }, [ %rd295 + 0 ], %rd294;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd297, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd297, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs101, %rs76;
+	@%p95 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs101 }, [ %rd298 + 0 ], %rd297;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd300, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd300, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs103, %rs76;
+	@%p96 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs103 }, [ %rd301 + 0 ], %rd300;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd303, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd303, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs105, %rs76;
+	@%p97 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs105 }, [ %rd304 + 0 ], %rd303;
+	// end inline asm
+	.loc	1 51 34                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:51:34
+	and.b64 	%rd391, %rd212, %rd107;
+	and.b64 	%rd393, %rd214, %rd107;
+	and.b64 	%rd395, %rd216, %rd107;
+	and.b64 	%rd397, %rd218, %rd107;
+	and.b64 	%rd399, %rd220, %rd107;
+	and.b64 	%rd401, %rd222, %rd107;
+	and.b64 	%rd403, %rd224, %rd107;
+	and.b64 	%rd405, %rd226, %rd107;
+	add.s64 	%rd95, %rd405, %rd185;
+	add.s64 	%rd94, %rd403, %rd181;
+	add.s64 	%rd97, %rd401, %rd193;
+	add.s64 	%rd96, %rd399, %rd189;
+	add.s64 	%rd91, %rd397, %rd169;
+	add.s64 	%rd90, %rd395, %rd165;
+	add.s64 	%rd93, %rd393, %rd177;
+	add.s64 	%rd92, %rd391, %rd173;
+	.loc	1 52 28                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:52:28
+	setp.lt.s64 	%p122, %rd92, 0;
+	setp.lt.s64 	%p123, %rd93, 0;
+	setp.lt.s64 	%p124, %rd90, 0;
+	setp.lt.s64 	%p125, %rd91, 0;
+	setp.lt.s64 	%p126, %rd96, 0;
+	setp.lt.s64 	%p127, %rd97, 0;
+	setp.lt.s64 	%p128, %rd94, 0;
+	setp.lt.s64 	%p129, %rd95, 0;
+	.loc	1 52 46                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:52:46
+	setp.ge.s64 	%p130, %rd92, %rd107;
+	setp.ge.s64 	%p131, %rd93, %rd107;
+	setp.ge.s64 	%p132, %rd90, %rd107;
+	setp.ge.s64 	%p133, %rd91, %rd107;
+	setp.ge.s64 	%p134, %rd96, %rd107;
+	setp.ge.s64 	%p135, %rd97, %rd107;
+	setp.ge.s64 	%p136, %rd94, %rd107;
+	setp.ge.s64 	%p137, %rd95, %rd107;
+	.loc	1 52 38                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:52:38
+	or.pred 	%p138, %p129, %p137;
+	or.pred 	%p139, %p128, %p136;
+	or.pred 	%p140, %p127, %p135;
+	or.pred 	%p141, %p126, %p134;
+	or.pred 	%p142, %p125, %p133;
+	or.pred 	%p143, %p124, %p132;
+	or.pred 	%p144, %p123, %p131;
+	or.pred 	%p145, %p122, %p130;
+	.loc	1 52 54                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:52:54
+	and.pred 	%p146, %p3, %p145;
+	selp.b16 	%rs107, 1, 0, %p146;
+	shl.b16 	%rs108, %rs107, 2;
+	and.pred 	%p147, %p4, %p144;
+	selp.b16 	%rs109, -1, 0, %p147;
+	shl.b16 	%rs110, %rs109, 3;
+	or.b16 	%rs111, %rs110, %rs108;
+	and.pred 	%p148, %p1, %p143;
+	selp.b16 	%rs112, 1, 0, %p148;
+	and.pred 	%p149, %p2, %p142;
+	selp.b16 	%rs113, -1, 0, %p149;
+	shl.b16 	%rs114, %rs113, 1;
+	or.b16 	%rs115, %rs112, %rs114;
+	and.b16 	%rs116, %rs115, 3;
+	or.b16 	%rs117, %rs116, %rs111;
+	and.b16 	%rs118, %rs117, 15;
+	and.pred 	%p150, %p7, %p141;
+	selp.b16 	%rs119, 1, 0, %p150;
+	shl.b16 	%rs120, %rs119, 2;
+	and.pred 	%p151, %p8, %p140;
+	selp.b16 	%rs121, -1, 0, %p151;
+	shl.b16 	%rs122, %rs121, 3;
+	or.b16 	%rs123, %rs122, %rs120;
+	and.pred 	%p152, %p5, %p139;
+	selp.b16 	%rs124, 1, 0, %p152;
+	and.pred 	%p153, %p6, %p138;
+	selp.b16 	%rs125, -1, 0, %p153;
+	shl.b16 	%rs126, %rs125, 1;
+	or.b16 	%rs127, %rs124, %rs126;
+	and.b16 	%rs128, %rs127, 3;
+	or.b16 	%rs129, %rs128, %rs123;
+	shl.b16 	%rs130, %rs129, 4;
+	or.b16 	%rs131, %rs118, %rs130;
+	.loc	1 52 64                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:52:64
+	and.b16 	%rs132, %rs131, 255;
+	setp.eq.b16 	%p154, %rs132, 0;
+	@%p154 bra 	$L__BB0_52;
+	bra.uni 	$L__BB0_51;
+$L__BB0_52:
+	.loc	1 0 64                          // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:0:64
+	ld.param.b64 	%rd102, [triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0_param_4];
+	ld.param.b64 	%rd101, [triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0_param_3];
+	.loc	1 40 119                        // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:40:119
+	cvt.f32.bf16 	%r79, %rs89;
+	mov.b32 	%r80, 0f00000000;
+	.loc	1 41 13                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:41:13
+	sub.f32 	%r81, %r80, %r79;
+	.loc	1 47 132                        // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:47:132
+	cvt.f32.bf16 	%r82, %rs105;
+	.loc	1 0 0                           // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:0
+	selp.f32 	%r83, %r81, %r82, %p113;
+	.loc	1 40 119                        // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:40:119
+	cvt.f32.bf16 	%r84, %rs87;
+	.loc	1 41 13                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:41:13
+	sub.f32 	%r85, %r80, %r84;
+	.loc	1 47 132                        // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:47:132
+	cvt.f32.bf16 	%r86, %rs103;
+	.loc	1 0 0                           // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:0
+	selp.f32 	%r87, %r85, %r86, %p112;
+	.loc	1 40 119                        // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:40:119
+	cvt.f32.bf16 	%r88, %rs85;
+	.loc	1 41 13                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:41:13
+	sub.f32 	%r89, %r80, %r88;
+	.loc	1 47 132                        // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:47:132
+	cvt.f32.bf16 	%r90, %rs101;
+	.loc	1 0 0                           // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:0
+	selp.f32 	%r91, %r89, %r90, %p111;
+	.loc	1 40 119                        // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:40:119
+	cvt.f32.bf16 	%r92, %rs83;
+	.loc	1 41 13                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:41:13
+	sub.f32 	%r93, %r80, %r92;
+	.loc	1 47 132                        // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:47:132
+	cvt.f32.bf16 	%r94, %rs99;
+	.loc	1 0 0                           // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:0
+	selp.f32 	%r95, %r93, %r94, %p110;
+	.loc	1 40 119                        // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:40:119
+	cvt.f32.bf16 	%r96, %rs81;
+	.loc	1 41 13                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:41:13
+	sub.f32 	%r97, %r80, %r96;
+	.loc	1 47 132                        // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:47:132
+	cvt.f32.bf16 	%r98, %rs97;
+	.loc	1 0 0                           // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:0
+	selp.f32 	%r99, %r97, %r98, %p109;
+	.loc	1 40 119                        // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:40:119
+	cvt.f32.bf16 	%r100, %rs79;
+	.loc	1 41 13                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:41:13
+	sub.f32 	%r101, %r80, %r100;
+	.loc	1 47 132                        // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:47:132
+	cvt.f32.bf16 	%r102, %rs95;
+	.loc	1 0 0                           // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:0
+	selp.f32 	%r103, %r101, %r102, %p108;
+	.loc	1 40 119                        // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:40:119
+	cvt.f32.bf16 	%r104, %rs77;
+	.loc	1 41 13                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:41:13
+	sub.f32 	%r105, %r80, %r104;
+	.loc	1 47 132                        // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:47:132
+	cvt.f32.bf16 	%r106, %rs93;
+	.loc	1 0 0                           // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:0
+	selp.f32 	%r107, %r105, %r106, %p107;
+	.loc	1 40 119                        // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:40:119
+	cvt.f32.bf16 	%r108, %rs75;
+	.loc	1 41 13                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:41:13
+	sub.f32 	%r109, %r80, %r108;
+	.loc	1 47 132                        // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:47:132
+	cvt.f32.bf16 	%r110, %rs91;
+	.loc	1 0 0                           // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:0
+	selp.f32 	%r111, %r109, %r110, %p106;
+	.loc	1 26 75                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:26:75
+	cvt.f32.bf16 	%r112, %rs40;
+	cvt.f32.bf16 	%r113, %rs39;
+	cvt.f32.bf16 	%r114, %rs38;
+	cvt.f32.bf16 	%r115, %rs37;
+	cvt.f32.bf16 	%r116, %rs36;
+	cvt.f32.bf16 	%r117, %rs35;
+	cvt.f32.bf16 	%r118, %rs34;
+	cvt.f32.bf16 	%r119, %rs33;
+	.loc	1 52 64                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:52:64
+	bar.sync 	0;
+	.loc	1 53 40                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:53:40
+	mul.lo.s64 	%rd444, %rd90, %rd106;
+	mul.lo.s64 	%rd445, %rd91, %rd106;
+	mul.lo.s64 	%rd446, %rd92, %rd106;
+	mul.lo.s64 	%rd447, %rd93, %rd106;
+	mul.lo.s64 	%rd448, %rd94, %rd106;
+	mul.lo.s64 	%rd449, %rd95, %rd106;
+	mul.lo.s64 	%rd450, %rd96, %rd106;
+	mul.lo.s64 	%rd451, %rd97, %rd106;
+	.loc	1 53 31                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:53:31
+	add.s64 	%rd453, %rd101, %rd314;
+	shl.b64 	%rd454, %rd444, 1;
+	add.s64 	%rd413, %rd453, %rd454;
+	add.s64 	%rd456, %rd101, %rd317;
+	shl.b64 	%rd457, %rd445, 1;
+	add.s64 	%rd416, %rd456, %rd457;
+	add.s64 	%rd459, %rd101, %rd320;
+	shl.b64 	%rd460, %rd446, 1;
+	add.s64 	%rd419, %rd459, %rd460;
+	add.s64 	%rd462, %rd101, %rd323;
+	shl.b64 	%rd463, %rd447, 1;
+	add.s64 	%rd422, %rd462, %rd463;
+	add.s64 	%rd465, %rd101, %rd326;
+	shl.b64 	%rd466, %rd448, 1;
+	add.s64 	%rd425, %rd465, %rd466;
+	add.s64 	%rd468, %rd101, %rd329;
+	shl.b64 	%rd469, %rd449, 1;
+	add.s64 	%rd428, %rd468, %rd469;
+	add.s64 	%rd471, %rd101, %rd332;
+	shl.b64 	%rd472, %rd450, 1;
+	add.s64 	%rd431, %rd471, %rd472;
+	add.s64 	%rd474, %rd101, %rd335;
+	shl.b64 	%rd475, %rd451, 1;
+	add.s64 	%rd434, %rd474, %rd475;
+	.loc	1 53 48                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:53:48
+	// begin inline asm
+	mov.u64 %rd414, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd414, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs133, 0x0;
+	@%p1 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs133 }, [ %rd413 + 0 ], %rd414;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd417, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd417, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs134, 0x0;
+	@%p2 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs134 }, [ %rd416 + 0 ], %rd417;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd420, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd420, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs135, 0x0;
+	@%p3 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs135 }, [ %rd419 + 0 ], %rd420;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd423, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd423, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs136, 0x0;
+	@%p4 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs136 }, [ %rd422 + 0 ], %rd423;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd426, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd426, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs137, 0x0;
+	@%p5 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs137 }, [ %rd425 + 0 ], %rd426;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd429, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd429, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs138, 0x0;
+	@%p6 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs138 }, [ %rd428 + 0 ], %rd429;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd432, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd432, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs139, 0x0;
+	@%p7 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs139 }, [ %rd431 + 0 ], %rd432;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd435, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd435, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs140, 0x0;
+	@%p8 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs140 }, [ %rd434 + 0 ], %rd435;
+	// end inline asm
+	.loc	1 33 46                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:33:46
+	mov.b32 	%r120, {%rs67, %rs133};
+	.loc	1 33 86                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:33:86
+	mov.b32 	{%rs149, %rs150}, %r120;
+	cvt.f32.bf16 	%r121, %rs149;
+	cvt.f32.bf16 	%r122, %rs150;
+	.loc	1 34 18                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:34:18
+	mul.f32 	%r123, %r111, %r122;
+	.loc	1 33 46                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:33:46
+	mov.b32 	%r124, {%rs68, %rs134};
+	.loc	1 33 86                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:33:86
+	mov.b32 	{%rs151, %rs152}, %r124;
+	cvt.f32.bf16 	%r125, %rs151;
+	cvt.f32.bf16 	%r126, %rs152;
+	.loc	1 34 18                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:34:18
+	mul.f32 	%r127, %r107, %r126;
+	.loc	1 33 46                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:33:46
+	mov.b32 	%r128, {%rs69, %rs135};
+	.loc	1 33 86                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:33:86
+	mov.b32 	{%rs153, %rs154}, %r128;
+	cvt.f32.bf16 	%r129, %rs153;
+	cvt.f32.bf16 	%r130, %rs154;
+	.loc	1 34 18                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:34:18
+	mul.f32 	%r131, %r103, %r130;
+	.loc	1 33 46                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:33:46
+	mov.b32 	%r132, {%rs70, %rs136};
+	.loc	1 33 86                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:33:86
+	mov.b32 	{%rs155, %rs156}, %r132;
+	cvt.f32.bf16 	%r133, %rs155;
+	cvt.f32.bf16 	%r134, %rs156;
+	.loc	1 34 18                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:34:18
+	mul.f32 	%r135, %r99, %r134;
+	.loc	1 33 46                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:33:46
+	mov.b32 	%r136, {%rs71, %rs137};
+	.loc	1 33 86                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:33:86
+	mov.b32 	{%rs157, %rs158}, %r136;
+	cvt.f32.bf16 	%r137, %rs157;
+	cvt.f32.bf16 	%r138, %rs158;
+	.loc	1 34 18                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:34:18
+	mul.f32 	%r139, %r95, %r138;
+	.loc	1 33 46                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:33:46
+	mov.b32 	%r140, {%rs72, %rs138};
+	.loc	1 33 86                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:33:86
+	mov.b32 	{%rs159, %rs160}, %r140;
+	cvt.f32.bf16 	%r141, %rs159;
+	cvt.f32.bf16 	%r142, %rs160;
+	.loc	1 34 18                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:34:18
+	mul.f32 	%r143, %r91, %r142;
+	.loc	1 33 46                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:33:46
+	mov.b32 	%r144, {%rs73, %rs139};
+	.loc	1 33 86                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:33:86
+	mov.b32 	{%rs161, %rs162}, %r144;
+	cvt.f32.bf16 	%r145, %rs161;
+	cvt.f32.bf16 	%r146, %rs162;
+	.loc	1 34 18                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:34:18
+	mul.f32 	%r147, %r87, %r146;
+	.loc	1 33 46                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:33:46
+	mov.b32 	%r148, {%rs74, %rs140};
+	.loc	1 33 86                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:33:86
+	mov.b32 	{%rs163, %rs164}, %r148;
+	cvt.f32.bf16 	%r149, %rs163;
+	cvt.f32.bf16 	%r150, %rs164;
+	.loc	1 34 18                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:34:18
+	mul.f32 	%r151, %r83, %r150;
+	.loc	1 55 19                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:55:19
+	fma.rn.f32 	%r152, %r119, %r121, %r123;
+	fma.rn.f32 	%r153, %r118, %r125, %r127;
+	fma.rn.f32 	%r154, %r117, %r129, %r131;
+	fma.rn.f32 	%r155, %r116, %r133, %r135;
+	fma.rn.f32 	%r156, %r115, %r137, %r139;
+	fma.rn.f32 	%r157, %r114, %r141, %r143;
+	fma.rn.f32 	%r158, %r113, %r145, %r147;
+	fma.rn.f32 	%r159, %r112, %r149, %r151;
+	.loc	1 56 25                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:56:25
+	add.s64 	%rd436, %rd102, %rd196;
+	add.s64 	%rd437, %rd102, %rd197;
+	add.s64 	%rd438, %rd102, %rd198;
+	add.s64 	%rd439, %rd102, %rd199;
+	add.s64 	%rd440, %rd102, %rd200;
+	add.s64 	%rd441, %rd102, %rd201;
+	add.s64 	%rd442, %rd102, %rd202;
+	add.s64 	%rd443, %rd102, %rd203;
+	.loc	1 56 37                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:56:37
+	cvt.rn.bf16.f32 	%rs141, %r152;
+	cvt.rn.bf16.f32 	%rs142, %r153;
+	cvt.rn.bf16.f32 	%rs143, %r154;
+	cvt.rn.bf16.f32 	%rs144, %r155;
+	cvt.rn.bf16.f32 	%rs145, %r156;
+	cvt.rn.bf16.f32 	%rs146, %r157;
+	cvt.rn.bf16.f32 	%rs147, %r158;
+	cvt.rn.bf16.f32 	%rs148, %r159;
+	// begin inline asm
+	@%p1 st.global.b16 [ %rd436 + 0 ], { %rs141 };
+	// end inline asm
+	// begin inline asm
+	@%p2 st.global.b16 [ %rd437 + 0 ], { %rs142 };
+	// end inline asm
+	// begin inline asm
+	@%p3 st.global.b16 [ %rd438 + 0 ], { %rs143 };
+	// end inline asm
+	// begin inline asm
+	@%p4 st.global.b16 [ %rd439 + 0 ], { %rs144 };
+	// end inline asm
+	// begin inline asm
+	@%p5 st.global.b16 [ %rd440 + 0 ], { %rs145 };
+	// end inline asm
+	// begin inline asm
+	@%p6 st.global.b16 [ %rd441 + 0 ], { %rs146 };
+	// end inline asm
+	// begin inline asm
+	@%p7 st.global.b16 [ %rd442 + 0 ], { %rs147 };
+	// end inline asm
+	// begin inline asm
+	@%p8 st.global.b16 [ %rd443 + 0 ], { %rs148 };
+	// end inline asm
+	.loc	1 56 4                          // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:56:4
+	ret;
+$L__BB0_49:
+	.loc	1 32 62                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:32:62
+	{ // callseq 0, 0
+	.param .b64 	param0;
+	.param .b64 	param1;
+	.param .b32 	param2;
+	.param .b64 	param3;
+	.param .b64 	param4;
+	mov.b64 	%rd228, assertFunc_0;
+	cvta.global.u64 	%rd229, %rd228;
+	st.param.b64 	[param3], %rd229;
+	mov.b64 	%rd230, assertFile_0;
+	cvta.global.u64 	%rd231, %rd230;
+	st.param.b64 	[param1], %rd231;
+	mov.b64 	%rd232, assertMessage_0;
+	cvta.global.u64 	%rd233, %rd232;
+	st.param.b64 	[param0], %rd233;
+	st.param.b64 	[param4], 1;
+	st.param.b32 	[param2], 32;
+	call.uni __assertfail, (param0, param1, param2, param3, param4);
+	} // callseq 0
+	trap;
+$L__BB0_51:
+	.loc	1 52 64                         // cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py:52:64
+	{ // callseq 1, 0
+	.param .b64 	param0;
+	.param .b64 	param1;
+	.param .b32 	param2;
+	.param .b64 	param3;
+	.param .b64 	param4;
+	mov.b64 	%rd406, assertFunc_1;
+	cvta.global.u64 	%rd407, %rd406;
+	st.param.b64 	[param3], %rd407;
+	mov.b64 	%rd408, assertFile_1;
+	cvta.global.u64 	%rd409, %rd408;
+	st.param.b64 	[param1], %rd409;
+	mov.b64 	%rd410, assertMessage_1;
+	cvta.global.u64 	%rd411, %rd410;
+	st.param.b64 	[param0], %rd411;
+	st.param.b64 	[param4], 1;
+	st.param.b32 	[param2], 52;
+	call.uni __assertfail, (param0, param1, param2, param3, param4);
+	} // callseq 1
+	trap;
+$L__tmp1:
+$L__func_end0:
+                                        // -- End function
+}
+	.file	1 "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py"
+	.section	.debug_abbrev
+	{
+.b8 1                                   // Abbreviation Code
+.b8 17                                  // DW_TAG_compile_unit
+.b8 0                                   // DW_CHILDREN_no
+.b8 37                                  // DW_AT_producer
+.b8 8                                   // DW_FORM_string
+.b8 19                                  // DW_AT_language
+.b8 5                                   // DW_FORM_data2
+.b8 3                                   // DW_AT_name
+.b8 8                                   // DW_FORM_string
+.b8 16                                  // DW_AT_stmt_list
+.b8 6                                   // DW_FORM_data4
+.b8 27                                  // DW_AT_comp_dir
+.b8 8                                   // DW_FORM_string
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 0                                   // EOM(3)
+	}
+	.section	.debug_info
+	{
+.b32 135                                // Length of Unit
+.b8 2                                   // DWARF version number
+.b8 0
+.b32 .debug_abbrev                      // Offset Into Abbrev. Section
+.b8 8                                   // Address Size (in bytes)
+.b8 1                                   // Abbrev [1] 0xb:0x80 DW_TAG_compile_unit
+.b8 116                                 // DW_AT_producer
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 0
+.b8 2                                   // DW_AT_language
+.b8 0
+.b8 99                                  // DW_AT_name
+.b8 118
+.b8 109
+.b8 55
+.b8 54
+.b8 107
+.b8 116
+.b8 106
+.b8 97
+.b8 119
+.b8 117
+.b8 109
+.b8 115
+.b8 106
+.b8 109
+.b8 113
+.b8 97
+.b8 119
+.b8 108
+.b8 104
+.b8 108
+.b8 105
+.b8 107
+.b8 53
+.b8 119
+.b8 98
+.b8 104
+.b8 120
+.b8 54
+.b8 104
+.b8 114
+.b8 105
+.b8 122
+.b8 53
+.b8 99
+.b8 103
+.b8 114
+.b8 97
+.b8 55
+.b8 53
+.b8 52
+.b8 103
+.b8 115
+.b8 114
+.b8 115
+.b8 122
+.b8 118
+.b8 108
+.b8 112
+.b8 117
+.b8 117
+.b8 117
+.b8 46
+.b8 112
+.b8 121
+.b8 0
+.b32 .debug_line                        // DW_AT_stmt_list
+.b8 47                                  // DW_AT_comp_dir
+.b8 119
+.b8 111
+.b8 114
+.b8 107
+.b8 115
+.b8 112
+.b8 97
+.b8 99
+.b8 101
+.b8 47
+.b8 104
+.b8 97
+.b8 110
+.b8 114
+.b8 117
+.b8 105
+.b8 47
+.b8 83
+.b8 112
+.b8 101
+.b8 99
+.b8 70
+.b8 111
+.b8 114
+.b8 103
+.b8 101
+.b8 45
+.b8 101
+.b8 120
+.b8 116
+.b8 47
+.b8 99
+.b8 97
+.b8 99
+.b8 104
+.b8 101
+.b8 47
+.b8 99
+.b8 111
+.b8 109
+.b8 112
+.b8 105
+.b8 108
+.b8 101
+.b8 100
+.b8 95
+.b8 107
+.b8 101
+.b8 114
+.b8 110
+.b8 101
+.b8 108
+.b8 115
+.b8 47
+.b8 118
+.b8 109
+.b8 0
+	}
+	.section	.debug_macinfo	{	}

SpecForge-ext/cache/compiled_kernels/triton/2/2TU6ZCF6AOXLWQQED5J7FS5ZXMYK7TIOQ6T2MLB767275BROXJCA/triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0.source

@@ -0,0 +1,299 @@
+#loc = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":18:0)
+#loc78 = loc("in_ptr0"(#loc))
+#loc79 = loc("in_ptr1"(#loc))
+#loc80 = loc("in_ptr2"(#loc))
+#loc81 = loc("in_ptr3"(#loc))
+#loc82 = loc("out_ptr0"(#loc))
+#loc83 = loc("ks0"(#loc))
+#loc84 = loc("ks1"(#loc))
+#loc85 = loc("ks2"(#loc))
+#loc86 = loc("ks3"(#loc))
+#loc87 = loc("ks4"(#loc))
+#loc88 = loc("xnumel"(#loc))
+module {
+  tt.func public @triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0(%in_ptr0: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("in_ptr0"(#loc)), %in_ptr1: !tt.ptr<i64> {tt.divisibility = 16 : i32} loc("in_ptr1"(#loc)), %in_ptr2: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("in_ptr2"(#loc)), %in_ptr3: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("in_ptr3"(#loc)), %out_ptr0: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("out_ptr0"(#loc)), %ks0: i64 loc("ks0"(#loc)), %ks1: i64 loc("ks1"(#loc)), %ks2: i64 loc("ks2"(#loc)), %ks3: i64 loc("ks3"(#loc)), %ks4: i64 loc("ks4"(#loc)), %xnumel: i32 loc("xnumel"(#loc))) attributes {noinline = false} {
+    %xoffset = tt.get_program_id x : i32 loc(#loc89)
+    %xoffset_0 = arith.constant 1024 : i32 loc(#loc90)
+    %xoffset_1 = arith.constant 1024 : i32 loc(#loc90)
+    %xoffset_2 = arith.muli %xoffset, %xoffset_1 : i32 loc(#loc90)
+    %xindex = tt.make_range {end = 1024 : i32, start = 0 : i32} : tensor<1024xi32> loc(#loc91)
+    %xindex_3 = tt.splat %xoffset_2 : i32 -> tensor<1024xi32> loc(#loc92)
+    %xindex_4 = arith.addi %xindex_3, %xindex : tensor<1024xi32> loc(#loc92)
+    %xmask = tt.splat %xnumel : i32 -> tensor<1024xi32> loc(#loc93)
+    %xmask_5 = arith.cmpi slt, %xindex_4, %xmask : tensor<1024xi32> loc(#loc93)
+    %x2 = arith.extsi %xindex_4 : tensor<1024xi32> to tensor<1024xi64> loc(#loc94)
+    %x2_6 = tt.splat %ks0 : i64 -> tensor<1024xi64> loc(#loc94)
+    %x2_7 = arith.divsi %x2, %x2_6 : tensor<1024xi64> loc(#loc94)
+    %x2_8 = tt.splat %ks1 : i64 -> tensor<1024xi64> loc(#loc95)
+    %x2_9 = arith.remsi %x2_7, %x2_8 : tensor<1024xi64> loc(#loc95)
+    %x0 = arith.extsi %xindex_4 : tensor<1024xi32> to tensor<1024xi64> loc(#loc96)
+    %x0_10 = tt.splat %ks3 : i64 -> tensor<1024xi64> loc(#loc96)
+    %x0_11 = arith.remsi %x0, %x0_10 : tensor<1024xi64> loc(#loc96)
+    %x5 = arith.extsi %xindex_4 : tensor<1024xi32> to tensor<1024xi64> loc(#loc97)
+    %x5_12 = tt.splat %ks3 : i64 -> tensor<1024xi64> loc(#loc97)
+    %x5_13 = arith.divsi %x5, %x5_12 : tensor<1024xi64> loc(#loc97)
+    %tmp0 = tt.splat %in_ptr0 : !tt.ptr<bf16> -> tensor<1024x!tt.ptr<bf16>> loc(#loc98)
+    %tmp0_14 = tt.addptr %tmp0, %xindex_4 : tensor<1024x!tt.ptr<bf16>>, tensor<1024xi32> loc(#loc98)
+    %tmp0_15 = tt.load %tmp0_14, %xmask_5 evictionPolicy = evict_last : tensor<1024x!tt.ptr<bf16>> loc(#loc99)
+    %tmp0_16 = arith.extf %tmp0_15 : tensor<1024xbf16> to tensor<1024xf32> loc(#loc100)
+    %tmp1 = tt.splat %in_ptr1 : !tt.ptr<i64> -> tensor<1024x!tt.ptr<i64>> loc(#loc101)
+    %tmp1_17 = tt.addptr %tmp1, %x2_9 : tensor<1024x!tt.ptr<i64>>, tensor<1024xi64> loc(#loc101)
+    %tmp1_18 = tt.load %tmp1_17, %xmask_5 evictionPolicy = evict_last : tensor<1024x!tt.ptr<i64>> loc(#loc102)
+    %tmp3 = tt.splat %ks2 : i64 -> tensor<1024xi64> loc(#loc103)
+    %tmp3_19 = arith.addi %tmp1_18, %tmp3 : tensor<1024xi64> loc(#loc103)
+    %tmp4 = arith.constant 0 : i32 loc(#loc104)
+    %tmp4_20 = arith.extsi %tmp4 : i32 to i64 loc(#loc104)
+    %tmp4_21 = tt.splat %tmp4_20 : i64 -> tensor<1024xi64> loc(#loc104)
+    %tmp4_22 = arith.cmpi slt, %tmp1_18, %tmp4_21 : tensor<1024xi64> loc(#loc104)
+    %tmp5 = arith.select %tmp4_22, %tmp3_19, %tmp1_18 : tensor<1024xi1>, tensor<1024xi64> loc(#loc105)
+    %c0_i32 = arith.constant 0 : i32 loc(#loc18)
+    %0 = arith.extsi %c0_i32 : i32 to i64 loc(#loc18)
+    %1 = tt.splat %0 : i64 -> tensor<1024xi64> loc(#loc18)
+    %2 = arith.cmpi sle, %1, %tmp5 : tensor<1024xi64> loc(#loc18)
+    %3 = tt.splat %ks2 : i64 -> tensor<1024xi64> loc(#loc19)
+    %4 = arith.cmpi slt, %tmp5, %3 : tensor<1024xi64> loc(#loc19)
+    %5 = arith.andi %2, %4 : tensor<1024xi1> loc(#loc20)
+    %true = arith.constant true loc(#loc21)
+    %cst = arith.constant dense<true> : tensor<1024xi1> loc(#loc21)
+    %6 = arith.xori %xmask_5, %cst : tensor<1024xi1> loc(#loc21)
+    %7 = arith.ori %5, %6 : tensor<1024xi1> loc(#loc22)
+    tt.assert %7, "index out of bounds: 0 <= tmp5 < ks2" : tensor<1024xi1> loc(#loc23)
+    %tmp7 = tt.splat %ks3 : i64 -> tensor<1024xi64> loc(#loc106)
+    %tmp7_23 = arith.muli %tmp7, %tmp5 : tensor<1024xi64> loc(#loc106)
+    %tmp7_24 = arith.addi %x0_11, %tmp7_23 : tensor<1024xi64> loc(#loc107)
+    %tmp7_25 = tt.splat %in_ptr2 : !tt.ptr<bf16> -> tensor<1024x!tt.ptr<bf16>> loc(#loc108)
+    %tmp7_26 = tt.addptr %tmp7_25, %tmp7_24 : tensor<1024x!tt.ptr<bf16>>, tensor<1024xi64> loc(#loc108)
+    %tmp7_27 = tt.load %tmp7_26, %xmask_5 evictionPolicy = evict_last : tensor<1024x!tt.ptr<bf16>> loc(#loc109)
+    %tmp7_28 = arith.extf %tmp7_27 : tensor<1024xbf16> to tensor<1024xf32> loc(#loc110)
+    %tmp8 = arith.mulf %tmp0_16, %tmp7_28 : tensor<1024xf32> loc(#loc111)
+    %tmp10 = arith.constant 0 : i64 loc(#loc112)
+    %tmp10_29 = arith.constant dense<0> : tensor<1xi64> loc(#loc112)
+    %tmp11 = arith.constant dense<0> : tensor<1024xi64> loc(#loc113)
+    %tmp11_30 = arith.cmpi sge, %x0_11, %tmp11 : tensor<1024xi64> loc(#loc113)
+    %tmp12 = arith.constant 2 : i32 loc(#loc114)
+    %tmp12_31 = arith.constant 2 : i64 loc(#loc114)
+    %tmp12_32 = arith.divsi %ks3, %tmp12_31 : i64 loc(#loc114)
+    %tmp12_33 = arith.constant -1 : i32 loc(#loc115)
+    %tmp12_34 = arith.constant -1 : i64 loc(#loc115)
+    %tmp12_35 = arith.muli %tmp12_34, %tmp12_32 : i64 loc(#loc115)
+    %tmp12_36 = arith.addi %ks3, %tmp12_35 : i64 loc(#loc116)
+    %tmp13 = tt.splat %tmp12_36 : i64 -> tensor<1024xi64> loc(#loc117)
+    %tmp13_37 = arith.cmpi slt, %x0_11, %tmp13 : tensor<1024xi64> loc(#loc117)
+    %tmp14 = tt.splat %ks3 : i64 -> tensor<1024xi64> loc(#loc118)
+    %tmp14_38 = arith.muli %tmp14, %x5_13 : tensor<1024xi64> loc(#loc118)
+    %tmp14_39 = arith.constant 2 : i32 loc(#loc119)
+    %tmp14_40 = arith.constant 2 : i64 loc(#loc119)
+    %tmp14_41 = arith.divsi %ks3, %tmp14_40 : i64 loc(#loc119)
+    %tmp14_42 = tt.splat %tmp14_41 : i64 -> tensor<1024xi64> loc(#loc120)
+    %tmp14_43 = arith.addi %tmp14_38, %tmp14_42 : tensor<1024xi64> loc(#loc120)
+    %tmp14_44 = arith.addi %tmp14_43, %x0_11 : tensor<1024xi64> loc(#loc121)
+    %tmp14_45 = tt.splat %in_ptr0 : !tt.ptr<bf16> -> tensor<1024x!tt.ptr<bf16>> loc(#loc122)
+    %tmp14_46 = tt.addptr %tmp14_45, %tmp14_44 : tensor<1024x!tt.ptr<bf16>>, tensor<1024xi64> loc(#loc122)
+    %tmp14_47 = arith.andi %tmp13_37, %xmask_5 : tensor<1024xi1> loc(#loc123)
+    %tmp14_48 = arith.constant 0.000000e+00 : f32 loc(#loc124)
+    %tmp14_49 = arith.constant dense<0.000000e+00> : tensor<1024xf32> loc(#loc124)
+    %tmp14_50 = arith.truncf %tmp14_49 : tensor<1024xf32> to tensor<1024xbf16> loc(#loc124)
+    %tmp14_51 = tt.load %tmp14_46, %tmp14_47, %tmp14_50 evictionPolicy = evict_last : tensor<1024x!tt.ptr<bf16>> loc(#loc124)
+    %tmp14_52 = arith.extf %tmp14_51 : tensor<1024xbf16> to tensor<1024xf32> loc(#loc125)
+    %tmp15 = arith.constant 0.000000e+00 : f32 loc(#loc126)
+    %tmp15_53 = arith.constant dense<0.000000e+00> : tensor<1024xf32> loc(#loc126)
+    %tmp15_54 = arith.subf %tmp15_53, %tmp14_52 : tensor<1024xf32> loc(#loc126)
+    %tmp16 = arith.constant 0.000000e+00 : f32 loc(#loc127)
+    %tmp16_55 = arith.constant dense<0.000000e+00> : tensor<1024xf32> loc(#loc127)
+    %tmp17 = arith.select %tmp13_37, %tmp15_54, %tmp16_55 : tensor<1024xi1>, tensor<1024xf32> loc(#loc128)
+    %tmp18 = tt.splat %tmp12_36 : i64 -> tensor<1024xi64> loc(#loc129)
+    %tmp18_56 = arith.cmpi sge, %x0_11, %tmp18 : tensor<1024xi64> loc(#loc129)
+    %tmp20 = tt.splat %ks3 : i64 -> tensor<1024xi64> loc(#loc130)
+    %tmp20_57 = arith.cmpi slt, %x0_11, %tmp20 : tensor<1024xi64> loc(#loc130)
+    %tmp21 = tt.splat %ks3 : i64 -> tensor<1024xi64> loc(#loc131)
+    %tmp21_58 = arith.muli %tmp21, %x5_13 : tensor<1024xi64> loc(#loc131)
+    %tmp21_59 = arith.constant -1 : i32 loc(#loc132)
+    %tmp21_60 = arith.constant -1 : i64 loc(#loc132)
+    %tmp21_61 = arith.muli %tmp21_60, %ks3 : i64 loc(#loc132)
+    %tmp21_62 = tt.splat %tmp21_61 : i64 -> tensor<1024xi64> loc(#loc133)
+    %tmp21_63 = arith.addi %x0_11, %tmp21_62 : tensor<1024xi64> loc(#loc133)
+    %tmp21_64 = arith.constant 2 : i32 loc(#loc134)
+    %tmp21_65 = arith.constant 2 : i64 loc(#loc134)
+    %tmp21_66 = arith.divsi %ks3, %tmp21_65 : i64 loc(#loc134)
+    %tmp21_67 = tt.splat %tmp21_66 : i64 -> tensor<1024xi64> loc(#loc135)
+    %tmp21_68 = arith.addi %tmp21_63, %tmp21_67 : tensor<1024xi64> loc(#loc135)
+    %tmp21_69 = arith.addi %tmp21_58, %tmp21_68 : tensor<1024xi64> loc(#loc136)
+    %tmp21_70 = tt.splat %in_ptr0 : !tt.ptr<bf16> -> tensor<1024x!tt.ptr<bf16>> loc(#loc137)
+    %tmp21_71 = tt.addptr %tmp21_70, %tmp21_69 : tensor<1024x!tt.ptr<bf16>>, tensor<1024xi64> loc(#loc137)
+    %tmp21_72 = arith.andi %tmp18_56, %xmask_5 : tensor<1024xi1> loc(#loc138)
+    %tmp21_73 = arith.constant 0.000000e+00 : f32 loc(#loc139)
+    %tmp21_74 = arith.constant dense<0.000000e+00> : tensor<1024xf32> loc(#loc139)
+    %tmp21_75 = arith.truncf %tmp21_74 : tensor<1024xf32> to tensor<1024xbf16> loc(#loc139)
+    %tmp21_76 = tt.load %tmp21_71, %tmp21_72, %tmp21_75 evictionPolicy = evict_last : tensor<1024x!tt.ptr<bf16>> loc(#loc139)
+    %tmp21_77 = arith.extf %tmp21_76 : tensor<1024xbf16> to tensor<1024xf32> loc(#loc140)
+    %tmp22 = arith.select %tmp13_37, %tmp17, %tmp21_77 : tensor<1024xi1>, tensor<1024xf32> loc(#loc141)
+    %tmp24 = tt.splat %ks4 : i64 -> tensor<1024xi64> loc(#loc142)
+    %tmp24_78 = arith.addi %tmp1_18, %tmp24 : tensor<1024xi64> loc(#loc142)
+    %tmp25 = arith.select %tmp4_22, %tmp24_78, %tmp1_18 : tensor<1024xi1>, tensor<1024xi64> loc(#loc143)
+    %c0_i32_79 = arith.constant 0 : i32 loc(#loc62)
+    %8 = arith.extsi %c0_i32_79 : i32 to i64 loc(#loc62)
+    %9 = tt.splat %8 : i64 -> tensor<1024xi64> loc(#loc62)
+    %10 = arith.cmpi sle, %9, %tmp25 : tensor<1024xi64> loc(#loc62)
+    %11 = tt.splat %ks4 : i64 -> tensor<1024xi64> loc(#loc63)
+    %12 = arith.cmpi slt, %tmp25, %11 : tensor<1024xi64> loc(#loc63)
+    %13 = arith.andi %10, %12 : tensor<1024xi1> loc(#loc64)
+    %true_80 = arith.constant true loc(#loc65)
+    %cst_81 = arith.constant dense<true> : tensor<1024xi1> loc(#loc65)
+    %14 = arith.xori %xmask_5, %cst_81 : tensor<1024xi1> loc(#loc65)
+    %15 = arith.ori %13, %14 : tensor<1024xi1> loc(#loc66)
+    tt.assert %15, "index out of bounds: 0 <= tmp25 < ks4" : tensor<1024xi1> loc(#loc67)
+    %tmp27 = tt.splat %ks3 : i64 -> tensor<1024xi64> loc(#loc144)
+    %tmp27_82 = arith.muli %tmp27, %tmp25 : tensor<1024xi64> loc(#loc144)
+    %tmp27_83 = arith.addi %x0_11, %tmp27_82 : tensor<1024xi64> loc(#loc145)
+    %tmp27_84 = tt.splat %in_ptr3 : !tt.ptr<bf16> -> tensor<1024x!tt.ptr<bf16>> loc(#loc146)
+    %tmp27_85 = tt.addptr %tmp27_84, %tmp27_83 : tensor<1024x!tt.ptr<bf16>>, tensor<1024xi64> loc(#loc146)
+    %tmp27_86 = tt.load %tmp27_85, %xmask_5 evictionPolicy = evict_last : tensor<1024x!tt.ptr<bf16>> loc(#loc147)
+    %tmp27_87 = arith.extf %tmp27_86 : tensor<1024xbf16> to tensor<1024xf32> loc(#loc148)
+    %tmp28 = arith.mulf %tmp22, %tmp27_87 : tensor<1024xf32> loc(#loc149)
+    %tmp29 = arith.addf %tmp8, %tmp28 : tensor<1024xf32> loc(#loc150)
+    %16 = tt.splat %out_ptr0 : !tt.ptr<bf16> -> tensor<1024x!tt.ptr<bf16>> loc(#loc75)
+    %17 = tt.addptr %16, %xindex_4 : tensor<1024x!tt.ptr<bf16>>, tensor<1024xi32> loc(#loc75)
+    %18 = arith.truncf %tmp29 : tensor<1024xf32> to tensor<1024xbf16> loc(#loc76)
+    tt.store %17, %18, %xmask_5 : tensor<1024x!tt.ptr<bf16>> loc(#loc76)
+    tt.return loc(#loc77)
+  } loc(#loc)
+} loc(#loc)
+#loc1 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":19:28)
+#loc2 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":19:33)
+#loc3 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":20:36)
+#loc4 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":20:23)
+#loc5 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":21:21)
+#loc6 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":23:21)
+#loc7 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":23:28)
+#loc8 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":24:19)
+#loc9 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":25:19)
+#loc10 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":26:30)
+#loc11 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":26:35)
+#loc12 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":26:75)
+#loc13 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":27:30)
+#loc14 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":27:35)
+#loc15 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":29:18)
+#loc16 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":30:18)
+#loc17 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":31:32)
+#loc18 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":32:28)
+#loc19 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":32:44)
+#loc20 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":32:37)
+#loc21 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":32:54)
+#loc22 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":32:52)
+#loc23 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":32:62)
+#loc24 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":33:39)
+#loc25 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":33:35)
+#loc26 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":33:30)
+#loc27 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":33:46)
+#loc28 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":33:86)
+#loc29 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":34:18)
+#loc30 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":36:28)
+#loc31 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":37:20)
+#loc32 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":38:31)
+#loc33 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":38:24)
+#loc34 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":38:18)
+#loc35 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":39:19)
+#loc36 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":40:35)
+#loc37 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":40:48)
+#loc38 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":40:41)
+#loc39 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":40:54)
+#loc40 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":40:31)
+#loc41 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":40:68)
+#loc42 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":40:60)
+#loc43 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":40:119)
+#loc44 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":41:13)
+#loc45 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":42:38)
+#loc46 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":43:35)
+#loc47 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":44:20)
+#loc48 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":46:19)
+#loc49 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":47:35)
+#loc50 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":47:52)
+#loc51 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":47:47)
+#loc52 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":47:67)
+#loc53 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":47:60)
+#loc54 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":47:41)
+#loc55 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":47:31)
+#loc56 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":47:81)
+#loc57 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":47:73)
+#loc58 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":47:132)
+#loc59 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":48:35)
+#loc60 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":50:19)
+#loc61 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":51:34)
+#loc62 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":52:28)
+#loc63 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":52:46)
+#loc64 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":52:38)
+#loc65 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":52:56)
+#loc66 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":52:54)
+#loc67 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":52:64)
+#loc68 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":53:40)
+#loc69 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":53:36)
+#loc70 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":53:31)
+#loc71 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":53:48)
+#loc72 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":53:88)
+#loc73 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":54:20)
+#loc74 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":55:19)
+#loc75 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":56:25)
+#loc76 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":56:37)
+#loc77 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":56:4)
+#loc89 = loc("xoffset"(#loc1))
+#loc90 = loc("xoffset"(#loc2))
+#loc91 = loc("xindex"(#loc3))
+#loc92 = loc("xindex"(#loc4))
+#loc93 = loc("xmask"(#loc5))
+#loc94 = loc("x2"(#loc6))
+#loc95 = loc("x2"(#loc7))
+#loc96 = loc("x0"(#loc8))
+#loc97 = loc("x5"(#loc9))
+#loc98 = loc("tmp0"(#loc10))
+#loc99 = loc("tmp0"(#loc11))
+#loc100 = loc("tmp0"(#loc12))
+#loc101 = loc("tmp1"(#loc13))
+#loc102 = loc("tmp1"(#loc14))
+#loc103 = loc("tmp3"(#loc15))
+#loc104 = loc("tmp4"(#loc16))
+#loc105 = loc("tmp5"(#loc17))
+#loc106 = loc("tmp7"(#loc24))
+#loc107 = loc("tmp7"(#loc25))
+#loc108 = loc("tmp7"(#loc26))
+#loc109 = loc("tmp7"(#loc27))
+#loc110 = loc("tmp7"(#loc28))
+#loc111 = loc("tmp8"(#loc29))
+#loc112 = loc("tmp10"(#loc30))
+#loc113 = loc("tmp11"(#loc31))
+#loc114 = loc("tmp12"(#loc32))
+#loc115 = loc("tmp12"(#loc33))
+#loc116 = loc("tmp12"(#loc34))
+#loc117 = loc("tmp13"(#loc35))
+#loc118 = loc("tmp14"(#loc36))
+#loc119 = loc("tmp14"(#loc37))
+#loc120 = loc("tmp14"(#loc38))
+#loc121 = loc("tmp14"(#loc39))
+#loc122 = loc("tmp14"(#loc40))
+#loc123 = loc("tmp14"(#loc41))
+#loc124 = loc("tmp14"(#loc42))
+#loc125 = loc("tmp14"(#loc43))
+#loc126 = loc("tmp15"(#loc44))
+#loc127 = loc("tmp16"(#loc45))
+#loc128 = loc("tmp17"(#loc46))
+#loc129 = loc("tmp18"(#loc47))
+#loc130 = loc("tmp20"(#loc48))
+#loc131 = loc("tmp21"(#loc49))
+#loc132 = loc("tmp21"(#loc50))
+#loc133 = loc("tmp21"(#loc51))
+#loc134 = loc("tmp21"(#loc52))
+#loc135 = loc("tmp21"(#loc53))
+#loc136 = loc("tmp21"(#loc54))
+#loc137 = loc("tmp21"(#loc55))
+#loc138 = loc("tmp21"(#loc56))
+#loc139 = loc("tmp21"(#loc57))
+#loc140 = loc("tmp21"(#loc58))
+#loc141 = loc("tmp22"(#loc59))
+#loc142 = loc("tmp24"(#loc60))
+#loc143 = loc("tmp25"(#loc61))
+#loc144 = loc("tmp27"(#loc68))
+#loc145 = loc("tmp27"(#loc69))
+#loc146 = loc("tmp27"(#loc70))
+#loc147 = loc("tmp27"(#loc71))
+#loc148 = loc("tmp27"(#loc72))
+#loc149 = loc("tmp28"(#loc73))
+#loc150 = loc("tmp29"(#loc74))

SpecForge-ext/cache/compiled_kernels/triton/2/2TU6ZCF6AOXLWQQED5J7FS5ZXMYK7TIOQ6T2MLB767275BROXJCA/triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0.ttgir

@@ -0,0 +1,232 @@
+#blocked = #ttg.blocked<{sizePerThread = [8], threadsPerWarp = [32], warpsPerCTA = [4], order = [0]}>
+#loc = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":18:0)
+#loc70 = loc("in_ptr0"(#loc))
+#loc71 = loc("in_ptr1"(#loc))
+#loc72 = loc("in_ptr2"(#loc))
+#loc73 = loc("in_ptr3"(#loc))
+#loc74 = loc("out_ptr0"(#loc))
+#loc75 = loc("ks0"(#loc))
+#loc76 = loc("ks1"(#loc))
+#loc77 = loc("ks2"(#loc))
+#loc78 = loc("ks3"(#loc))
+#loc79 = loc("ks4"(#loc))
+#loc80 = loc("xnumel"(#loc))
+module attributes {"ttg.num-ctas" = 1 : i32, "ttg.num-warps" = 4 : i32, ttg.target = "cuda:90", "ttg.threads-per-warp" = 32 : i32} {
+  tt.func public @triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0(%in_ptr0: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("in_ptr0"(#loc)), %in_ptr1: !tt.ptr<i64> {tt.divisibility = 16 : i32} loc("in_ptr1"(#loc)), %in_ptr2: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("in_ptr2"(#loc)), %in_ptr3: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("in_ptr3"(#loc)), %out_ptr0: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("out_ptr0"(#loc)), %ks0: i64 loc("ks0"(#loc)), %ks1: i64 loc("ks1"(#loc)), %ks2: i64 loc("ks2"(#loc)), %ks3: i64 loc("ks3"(#loc)), %ks4: i64 loc("ks4"(#loc)), %xnumel: i32 loc("xnumel"(#loc))) attributes {noinline = false} {
+    %cst = arith.constant dense<true> : tensor<1024xi1, #blocked> loc(#loc1)
+    %c1024_i32 = arith.constant 1024 : i32 loc(#loc1)
+    %cst_0 = arith.constant dense<0.000000e+00> : tensor<1024xbf16, #blocked> loc(#loc1)
+    %c2_i64 = arith.constant 2 : i64 loc(#loc1)
+    %c-1_i64 = arith.constant -1 : i64 loc(#loc1)
+    %cst_1 = arith.constant dense<0> : tensor<1024xi64, #blocked> loc(#loc1)
+    %cst_2 = arith.constant dense<0.000000e+00> : tensor<1024xf32, #blocked> loc(#loc1)
+    %xoffset = tt.get_program_id x : i32 loc(#loc81)
+    %xoffset_3 = arith.muli %xoffset, %c1024_i32 : i32 loc(#loc82)
+    %xindex = tt.make_range {end = 1024 : i32, start = 0 : i32} : tensor<1024xi32, #blocked> loc(#loc83)
+    %xindex_4 = tt.splat %xoffset_3 : i32 -> tensor<1024xi32, #blocked> loc(#loc84)
+    %xindex_5 = arith.addi %xindex_4, %xindex : tensor<1024xi32, #blocked> loc(#loc84)
+    %xmask = tt.splat %xnumel : i32 -> tensor<1024xi32, #blocked> loc(#loc85)
+    %xmask_6 = arith.cmpi slt, %xindex_5, %xmask : tensor<1024xi32, #blocked> loc(#loc85)
+    %x2 = arith.extsi %xindex_5 : tensor<1024xi32, #blocked> to tensor<1024xi64, #blocked> loc(#loc86)
+    %x2_7 = tt.splat %ks0 : i64 -> tensor<1024xi64, #blocked> loc(#loc86)
+    %x2_8 = arith.divsi %x2, %x2_7 : tensor<1024xi64, #blocked> loc(#loc86)
+    %x2_9 = tt.splat %ks1 : i64 -> tensor<1024xi64, #blocked> loc(#loc87)
+    %x2_10 = arith.remsi %x2_8, %x2_9 : tensor<1024xi64, #blocked> loc(#loc87)
+    %x0 = tt.splat %ks3 : i64 -> tensor<1024xi64, #blocked> loc(#loc88)
+    %x0_11 = arith.remsi %x2, %x0 : tensor<1024xi64, #blocked> loc(#loc88)
+    %x5 = arith.divsi %x2, %x0 : tensor<1024xi64, #blocked> loc(#loc89)
+    %tmp0 = tt.splat %in_ptr0 : !tt.ptr<bf16> -> tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc90)
+    %tmp0_12 = tt.addptr %tmp0, %xindex_5 : tensor<1024x!tt.ptr<bf16>, #blocked>, tensor<1024xi32, #blocked> loc(#loc90)
+    %tmp0_13 = tt.load %tmp0_12, %xmask_6 evictionPolicy = evict_last : tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc91)
+    %tmp0_14 = arith.extf %tmp0_13 : tensor<1024xbf16, #blocked> to tensor<1024xf32, #blocked> loc(#loc92)
+    %tmp1 = tt.splat %in_ptr1 : !tt.ptr<i64> -> tensor<1024x!tt.ptr<i64>, #blocked> loc(#loc93)
+    %tmp1_15 = tt.addptr %tmp1, %x2_10 : tensor<1024x!tt.ptr<i64>, #blocked>, tensor<1024xi64, #blocked> loc(#loc93)
+    %tmp1_16 = tt.load %tmp1_15, %xmask_6 evictionPolicy = evict_last : tensor<1024x!tt.ptr<i64>, #blocked> loc(#loc94)
+    %tmp3 = tt.splat %ks2 : i64 -> tensor<1024xi64, #blocked> loc(#loc95)
+    %tmp3_17 = arith.addi %tmp1_16, %tmp3 : tensor<1024xi64, #blocked> loc(#loc95)
+    %tmp4 = arith.cmpi slt, %tmp1_16, %cst_1 : tensor<1024xi64, #blocked> loc(#loc96)
+    %tmp5 = arith.select %tmp4, %tmp3_17, %tmp1_16 : tensor<1024xi1, #blocked>, tensor<1024xi64, #blocked> loc(#loc97)
+    %0 = arith.cmpi sge, %tmp5, %cst_1 : tensor<1024xi64, #blocked> loc(#loc19)
+    %1 = arith.cmpi slt, %tmp5, %tmp3 : tensor<1024xi64, #blocked> loc(#loc20)
+    %2 = arith.andi %0, %1 : tensor<1024xi1, #blocked> loc(#loc21)
+    %3 = arith.xori %xmask_6, %cst : tensor<1024xi1, #blocked> loc(#loc22)
+    %4 = arith.ori %2, %3 : tensor<1024xi1, #blocked> loc(#loc23)
+    tt.assert %4, "index out of bounds: 0 <= tmp5 < ks2" : tensor<1024xi1, #blocked> loc(#loc24)
+    %tmp7 = arith.muli %x0, %tmp5 : tensor<1024xi64, #blocked> loc(#loc98)
+    %tmp7_18 = arith.addi %x0_11, %tmp7 : tensor<1024xi64, #blocked> loc(#loc99)
+    %tmp7_19 = tt.splat %in_ptr2 : !tt.ptr<bf16> -> tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc100)
+    %tmp7_20 = tt.addptr %tmp7_19, %tmp7_18 : tensor<1024x!tt.ptr<bf16>, #blocked>, tensor<1024xi64, #blocked> loc(#loc100)
+    %tmp7_21 = tt.load %tmp7_20, %xmask_6 evictionPolicy = evict_last : tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc101)
+    %tmp7_22 = arith.extf %tmp7_21 : tensor<1024xbf16, #blocked> to tensor<1024xf32, #blocked> loc(#loc102)
+    %tmp8 = arith.mulf %tmp0_14, %tmp7_22 : tensor<1024xf32, #blocked> loc(#loc103)
+    %tmp12 = arith.divsi %ks3, %c2_i64 : i64 loc(#loc104)
+    %tmp12_23 = arith.subi %ks3, %tmp12 : i64 loc(#loc105)
+    %tmp13 = tt.splat %tmp12_23 : i64 -> tensor<1024xi64, #blocked> loc(#loc106)
+    %tmp13_24 = arith.cmpi slt, %x0_11, %tmp13 : tensor<1024xi64, #blocked> loc(#loc106)
+    %tmp14 = arith.muli %x0, %x5 : tensor<1024xi64, #blocked> loc(#loc107)
+    %tmp14_25 = tt.splat %tmp12 : i64 -> tensor<1024xi64, #blocked> loc(#loc108)
+    %tmp14_26 = arith.addi %tmp14, %tmp14_25 : tensor<1024xi64, #blocked> loc(#loc108)
+    %tmp14_27 = arith.addi %tmp14_26, %x0_11 : tensor<1024xi64, #blocked> loc(#loc109)
+    %tmp14_28 = tt.addptr %tmp0, %tmp14_27 : tensor<1024x!tt.ptr<bf16>, #blocked>, tensor<1024xi64, #blocked> loc(#loc110)
+    %tmp14_29 = arith.andi %tmp13_24, %xmask_6 : tensor<1024xi1, #blocked> loc(#loc111)
+    %tmp14_30 = tt.load %tmp14_28, %tmp14_29, %cst_0 evictionPolicy = evict_last : tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc112)
+    %tmp14_31 = arith.extf %tmp14_30 : tensor<1024xbf16, #blocked> to tensor<1024xf32, #blocked> loc(#loc113)
+    %tmp15 = arith.subf %cst_2, %tmp14_31 : tensor<1024xf32, #blocked> loc(#loc114)
+    %tmp18 = arith.cmpi sge, %x0_11, %tmp13 : tensor<1024xi64, #blocked> loc(#loc115)
+    %tmp21 = arith.muli %ks3, %c-1_i64 : i64 loc(#loc116)
+    %tmp21_32 = tt.splat %tmp21 : i64 -> tensor<1024xi64, #blocked> loc(#loc117)
+    %tmp21_33 = arith.addi %x0_11, %tmp21_32 : tensor<1024xi64, #blocked> loc(#loc117)
+    %tmp21_34 = arith.addi %tmp21_33, %tmp14_25 : tensor<1024xi64, #blocked> loc(#loc118)
+    %tmp21_35 = arith.addi %tmp14, %tmp21_34 : tensor<1024xi64, #blocked> loc(#loc119)
+    %tmp21_36 = tt.addptr %tmp0, %tmp21_35 : tensor<1024x!tt.ptr<bf16>, #blocked>, tensor<1024xi64, #blocked> loc(#loc120)
+    %tmp21_37 = arith.andi %tmp18, %xmask_6 : tensor<1024xi1, #blocked> loc(#loc121)
+    %tmp21_38 = tt.load %tmp21_36, %tmp21_37, %cst_0 evictionPolicy = evict_last : tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc122)
+    %tmp21_39 = arith.extf %tmp21_38 : tensor<1024xbf16, #blocked> to tensor<1024xf32, #blocked> loc(#loc123)
+    %tmp22 = arith.select %tmp13_24, %tmp15, %tmp21_39 : tensor<1024xi1, #blocked>, tensor<1024xf32, #blocked> loc(#loc135)
+    %tmp24 = tt.splat %ks4 : i64 -> tensor<1024xi64, #blocked> loc(#loc126)
+    %tmp24_40 = arith.addi %tmp1_16, %tmp24 : tensor<1024xi64, #blocked> loc(#loc126)
+    %tmp25 = arith.select %tmp4, %tmp24_40, %tmp1_16 : tensor<1024xi1, #blocked>, tensor<1024xi64, #blocked> loc(#loc127)
+    %5 = arith.cmpi sge, %tmp25, %cst_1 : tensor<1024xi64, #blocked> loc(#loc55)
+    %6 = arith.cmpi slt, %tmp25, %tmp24 : tensor<1024xi64, #blocked> loc(#loc56)
+    %7 = arith.andi %5, %6 : tensor<1024xi1, #blocked> loc(#loc57)
+    %8 = arith.ori %7, %3 : tensor<1024xi1, #blocked> loc(#loc58)
+    tt.assert %8, "index out of bounds: 0 <= tmp25 < ks4" : tensor<1024xi1, #blocked> loc(#loc59)
+    %tmp27 = arith.muli %x0, %tmp25 : tensor<1024xi64, #blocked> loc(#loc128)
+    %tmp27_41 = arith.addi %x0_11, %tmp27 : tensor<1024xi64, #blocked> loc(#loc129)
+    %tmp27_42 = tt.splat %in_ptr3 : !tt.ptr<bf16> -> tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc130)
+    %tmp27_43 = tt.addptr %tmp27_42, %tmp27_41 : tensor<1024x!tt.ptr<bf16>, #blocked>, tensor<1024xi64, #blocked> loc(#loc130)
+    %tmp27_44 = tt.load %tmp27_43, %xmask_6 evictionPolicy = evict_last : tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc131)
+    %tmp27_45 = arith.extf %tmp27_44 : tensor<1024xbf16, #blocked> to tensor<1024xf32, #blocked> loc(#loc132)
+    %tmp28 = arith.mulf %tmp22, %tmp27_45 : tensor<1024xf32, #blocked> loc(#loc133)
+    %tmp29 = arith.addf %tmp8, %tmp28 : tensor<1024xf32, #blocked> loc(#loc134)
+    %9 = tt.splat %out_ptr0 : !tt.ptr<bf16> -> tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc67)
+    %10 = tt.addptr %9, %xindex_5 : tensor<1024x!tt.ptr<bf16>, #blocked>, tensor<1024xi32, #blocked> loc(#loc67)
+    %11 = arith.truncf %tmp29 : tensor<1024xf32, #blocked> to tensor<1024xbf16, #blocked> loc(#loc68)
+    tt.store %10, %11, %xmask_6 : tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc68)
+    tt.return loc(#loc69)
+  } loc(#loc)
+} loc(#loc)
+#loc1 = loc(unknown)
+#loc2 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":19:28)
+#loc3 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":19:33)
+#loc4 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":20:36)
+#loc5 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":20:23)
+#loc6 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":21:21)
+#loc7 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":23:21)
+#loc8 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":23:28)
+#loc9 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":24:19)
+#loc10 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":25:19)
+#loc11 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":26:30)
+#loc12 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":26:35)
+#loc13 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":26:75)
+#loc14 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":27:30)
+#loc15 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":27:35)
+#loc16 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":29:18)
+#loc17 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":30:18)
+#loc18 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":31:32)
+#loc19 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":32:28)
+#loc20 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":32:44)
+#loc21 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":32:37)
+#loc22 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":32:54)
+#loc23 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":32:52)
+#loc24 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":32:62)
+#loc25 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":33:39)
+#loc26 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":33:35)
+#loc27 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":33:30)
+#loc28 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":33:46)
+#loc29 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":33:86)
+#loc30 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":34:18)
+#loc31 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":38:31)
+#loc32 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":38:18)
+#loc33 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":39:19)
+#loc34 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":40:35)
+#loc35 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":40:41)
+#loc36 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":40:54)
+#loc37 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":40:31)
+#loc38 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":40:68)
+#loc39 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":40:60)
+#loc40 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":40:119)
+#loc41 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":41:13)
+#loc42 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":44:20)
+#loc43 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":47:52)
+#loc44 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":47:47)
+#loc45 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":47:60)
+#loc46 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":47:41)
+#loc47 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":47:31)
+#loc48 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":47:81)
+#loc49 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":47:73)
+#loc50 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":47:132)
+#loc51 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":48:35)
+#loc52 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":43:35)
+#loc53 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":50:19)
+#loc54 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":51:34)
+#loc55 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":52:28)
+#loc56 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":52:46)
+#loc57 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":52:38)
+#loc58 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":52:54)
+#loc59 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":52:64)
+#loc60 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":53:40)
+#loc61 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":53:36)
+#loc62 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":53:31)
+#loc63 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":53:48)
+#loc64 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":53:88)
+#loc65 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":54:20)
+#loc66 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":55:19)
+#loc67 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":56:25)
+#loc68 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":56:37)
+#loc69 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":56:4)
+#loc81 = loc("xoffset"(#loc2))
+#loc82 = loc("xoffset"(#loc3))
+#loc83 = loc("xindex"(#loc4))
+#loc84 = loc("xindex"(#loc5))
+#loc85 = loc("xmask"(#loc6))
+#loc86 = loc("x2"(#loc7))
+#loc87 = loc("x2"(#loc8))
+#loc88 = loc("x0"(#loc9))
+#loc89 = loc("x5"(#loc10))
+#loc90 = loc("tmp0"(#loc11))
+#loc91 = loc("tmp0"(#loc12))
+#loc92 = loc("tmp0"(#loc13))
+#loc93 = loc("tmp1"(#loc14))
+#loc94 = loc("tmp1"(#loc15))
+#loc95 = loc("tmp3"(#loc16))
+#loc96 = loc("tmp4"(#loc17))
+#loc97 = loc("tmp5"(#loc18))
+#loc98 = loc("tmp7"(#loc25))
+#loc99 = loc("tmp7"(#loc26))
+#loc100 = loc("tmp7"(#loc27))
+#loc101 = loc("tmp7"(#loc28))
+#loc102 = loc("tmp7"(#loc29))
+#loc103 = loc("tmp8"(#loc30))
+#loc104 = loc("tmp12"(#loc31))
+#loc105 = loc("tmp12"(#loc32))
+#loc106 = loc("tmp13"(#loc33))
+#loc107 = loc("tmp14"(#loc34))
+#loc108 = loc("tmp14"(#loc35))
+#loc109 = loc("tmp14"(#loc36))
+#loc110 = loc("tmp14"(#loc37))
+#loc111 = loc("tmp14"(#loc38))
+#loc112 = loc("tmp14"(#loc39))
+#loc113 = loc("tmp14"(#loc40))
+#loc114 = loc("tmp15"(#loc41))
+#loc115 = loc("tmp18"(#loc42))
+#loc116 = loc("tmp21"(#loc43))
+#loc117 = loc("tmp21"(#loc44))
+#loc118 = loc("tmp21"(#loc45))
+#loc119 = loc("tmp21"(#loc46))
+#loc120 = loc("tmp21"(#loc47))
+#loc121 = loc("tmp21"(#loc48))
+#loc122 = loc("tmp21"(#loc49))
+#loc123 = loc("tmp21"(#loc50))
+#loc124 = loc("tmp22"(#loc51))
+#loc125 = loc("tmp17"(#loc52))
+#loc126 = loc("tmp24"(#loc53))
+#loc127 = loc("tmp25"(#loc54))
+#loc128 = loc("tmp27"(#loc60))
+#loc129 = loc("tmp27"(#loc61))
+#loc130 = loc("tmp27"(#loc62))
+#loc131 = loc("tmp27"(#loc63))
+#loc132 = loc("tmp27"(#loc64))
+#loc133 = loc("tmp28"(#loc65))
+#loc134 = loc("tmp29"(#loc66))
+#loc135 = loc(fused[#loc124, #loc125])

SpecForge-ext/cache/compiled_kernels/triton/2/2TU6ZCF6AOXLWQQED5J7FS5ZXMYK7TIOQ6T2MLB767275BROXJCA/triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0.ttir

@@ -0,0 +1,231 @@
+#loc = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":18:0)
+#loc70 = loc("in_ptr0"(#loc))
+#loc71 = loc("in_ptr1"(#loc))
+#loc72 = loc("in_ptr2"(#loc))
+#loc73 = loc("in_ptr3"(#loc))
+#loc74 = loc("out_ptr0"(#loc))
+#loc75 = loc("ks0"(#loc))
+#loc76 = loc("ks1"(#loc))
+#loc77 = loc("ks2"(#loc))
+#loc78 = loc("ks3"(#loc))
+#loc79 = loc("ks4"(#loc))
+#loc80 = loc("xnumel"(#loc))
+module {
+  tt.func public @triton_poi_fused_add_cat_index_mul_neg_slice_squeeze_unsqueeze_0(%in_ptr0: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("in_ptr0"(#loc)), %in_ptr1: !tt.ptr<i64> {tt.divisibility = 16 : i32} loc("in_ptr1"(#loc)), %in_ptr2: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("in_ptr2"(#loc)), %in_ptr3: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("in_ptr3"(#loc)), %out_ptr0: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("out_ptr0"(#loc)), %ks0: i64 loc("ks0"(#loc)), %ks1: i64 loc("ks1"(#loc)), %ks2: i64 loc("ks2"(#loc)), %ks3: i64 loc("ks3"(#loc)), %ks4: i64 loc("ks4"(#loc)), %xnumel: i32 loc("xnumel"(#loc))) attributes {noinline = false} {
+    %cst = arith.constant dense<0.000000e+00> : tensor<1024xbf16> loc(#loc1)
+    %cst_0 = arith.constant dense<0> : tensor<1024xi64> loc(#loc1)
+    %cst_1 = arith.constant dense<0.000000e+00> : tensor<1024xf32> loc(#loc1)
+    %c-1_i64 = arith.constant -1 : i64 loc(#loc1)
+    %c2_i64 = arith.constant 2 : i64 loc(#loc1)
+    %cst_2 = arith.constant dense<true> : tensor<1024xi1> loc(#loc1)
+    %c1024_i32 = arith.constant 1024 : i32 loc(#loc1)
+    %xoffset = tt.get_program_id x : i32 loc(#loc81)
+    %xoffset_3 = arith.muli %xoffset, %c1024_i32 : i32 loc(#loc82)
+    %xindex = tt.make_range {end = 1024 : i32, start = 0 : i32} : tensor<1024xi32> loc(#loc83)
+    %xindex_4 = tt.splat %xoffset_3 : i32 -> tensor<1024xi32> loc(#loc84)
+    %xindex_5 = arith.addi %xindex_4, %xindex : tensor<1024xi32> loc(#loc84)
+    %xmask = tt.splat %xnumel : i32 -> tensor<1024xi32> loc(#loc85)
+    %xmask_6 = arith.cmpi slt, %xindex_5, %xmask : tensor<1024xi32> loc(#loc85)
+    %x2 = arith.extsi %xindex_5 : tensor<1024xi32> to tensor<1024xi64> loc(#loc86)
+    %x2_7 = tt.splat %ks0 : i64 -> tensor<1024xi64> loc(#loc86)
+    %x2_8 = arith.divsi %x2, %x2_7 : tensor<1024xi64> loc(#loc86)
+    %x2_9 = tt.splat %ks1 : i64 -> tensor<1024xi64> loc(#loc87)
+    %x2_10 = arith.remsi %x2_8, %x2_9 : tensor<1024xi64> loc(#loc87)
+    %x0 = tt.splat %ks3 : i64 -> tensor<1024xi64> loc(#loc88)
+    %x0_11 = arith.remsi %x2, %x0 : tensor<1024xi64> loc(#loc88)
+    %x5 = arith.divsi %x2, %x0 : tensor<1024xi64> loc(#loc89)
+    %tmp0 = tt.splat %in_ptr0 : !tt.ptr<bf16> -> tensor<1024x!tt.ptr<bf16>> loc(#loc90)
+    %tmp0_12 = tt.addptr %tmp0, %xindex_5 : tensor<1024x!tt.ptr<bf16>>, tensor<1024xi32> loc(#loc90)
+    %tmp0_13 = tt.load %tmp0_12, %xmask_6 evictionPolicy = evict_last : tensor<1024x!tt.ptr<bf16>> loc(#loc91)
+    %tmp0_14 = arith.extf %tmp0_13 : tensor<1024xbf16> to tensor<1024xf32> loc(#loc92)
+    %tmp1 = tt.splat %in_ptr1 : !tt.ptr<i64> -> tensor<1024x!tt.ptr<i64>> loc(#loc93)
+    %tmp1_15 = tt.addptr %tmp1, %x2_10 : tensor<1024x!tt.ptr<i64>>, tensor<1024xi64> loc(#loc93)
+    %tmp1_16 = tt.load %tmp1_15, %xmask_6 evictionPolicy = evict_last : tensor<1024x!tt.ptr<i64>> loc(#loc94)
+    %tmp3 = tt.splat %ks2 : i64 -> tensor<1024xi64> loc(#loc95)
+    %tmp3_17 = arith.addi %tmp1_16, %tmp3 : tensor<1024xi64> loc(#loc95)
+    %tmp4 = arith.cmpi slt, %tmp1_16, %cst_0 : tensor<1024xi64> loc(#loc96)
+    %tmp5 = arith.select %tmp4, %tmp3_17, %tmp1_16 : tensor<1024xi1>, tensor<1024xi64> loc(#loc97)
+    %0 = arith.cmpi sge, %tmp5, %cst_0 : tensor<1024xi64> loc(#loc19)
+    %1 = arith.cmpi slt, %tmp5, %tmp3 : tensor<1024xi64> loc(#loc20)
+    %2 = arith.andi %0, %1 : tensor<1024xi1> loc(#loc21)
+    %3 = arith.xori %xmask_6, %cst_2 : tensor<1024xi1> loc(#loc22)
+    %4 = arith.ori %2, %3 : tensor<1024xi1> loc(#loc23)
+    tt.assert %4, "index out of bounds: 0 <= tmp5 < ks2" : tensor<1024xi1> loc(#loc24)
+    %tmp7 = arith.muli %x0, %tmp5 : tensor<1024xi64> loc(#loc98)
+    %tmp7_18 = arith.addi %x0_11, %tmp7 : tensor<1024xi64> loc(#loc99)
+    %tmp7_19 = tt.splat %in_ptr2 : !tt.ptr<bf16> -> tensor<1024x!tt.ptr<bf16>> loc(#loc100)
+    %tmp7_20 = tt.addptr %tmp7_19, %tmp7_18 : tensor<1024x!tt.ptr<bf16>>, tensor<1024xi64> loc(#loc100)
+    %tmp7_21 = tt.load %tmp7_20, %xmask_6 evictionPolicy = evict_last : tensor<1024x!tt.ptr<bf16>> loc(#loc101)
+    %tmp7_22 = arith.extf %tmp7_21 : tensor<1024xbf16> to tensor<1024xf32> loc(#loc102)
+    %tmp8 = arith.mulf %tmp0_14, %tmp7_22 : tensor<1024xf32> loc(#loc103)
+    %tmp12 = arith.divsi %ks3, %c2_i64 : i64 loc(#loc104)
+    %tmp12_23 = arith.subi %ks3, %tmp12 : i64 loc(#loc105)
+    %tmp13 = tt.splat %tmp12_23 : i64 -> tensor<1024xi64> loc(#loc106)
+    %tmp13_24 = arith.cmpi slt, %x0_11, %tmp13 : tensor<1024xi64> loc(#loc106)
+    %tmp14 = arith.muli %x0, %x5 : tensor<1024xi64> loc(#loc107)
+    %tmp14_25 = tt.splat %tmp12 : i64 -> tensor<1024xi64> loc(#loc108)
+    %tmp14_26 = arith.addi %tmp14, %tmp14_25 : tensor<1024xi64> loc(#loc108)
+    %tmp14_27 = arith.addi %tmp14_26, %x0_11 : tensor<1024xi64> loc(#loc109)
+    %tmp14_28 = tt.addptr %tmp0, %tmp14_27 : tensor<1024x!tt.ptr<bf16>>, tensor<1024xi64> loc(#loc110)
+    %tmp14_29 = arith.andi %tmp13_24, %xmask_6 : tensor<1024xi1> loc(#loc111)
+    %tmp14_30 = tt.load %tmp14_28, %tmp14_29, %cst evictionPolicy = evict_last : tensor<1024x!tt.ptr<bf16>> loc(#loc112)
+    %tmp14_31 = arith.extf %tmp14_30 : tensor<1024xbf16> to tensor<1024xf32> loc(#loc113)
+    %tmp15 = arith.subf %cst_1, %tmp14_31 : tensor<1024xf32> loc(#loc114)
+    %tmp18 = arith.cmpi sge, %x0_11, %tmp13 : tensor<1024xi64> loc(#loc115)
+    %tmp21 = arith.muli %ks3, %c-1_i64 : i64 loc(#loc116)
+    %tmp21_32 = tt.splat %tmp21 : i64 -> tensor<1024xi64> loc(#loc117)
+    %tmp21_33 = arith.addi %x0_11, %tmp21_32 : tensor<1024xi64> loc(#loc117)
+    %tmp21_34 = arith.addi %tmp21_33, %tmp14_25 : tensor<1024xi64> loc(#loc118)
+    %tmp21_35 = arith.addi %tmp14, %tmp21_34 : tensor<1024xi64> loc(#loc119)
+    %tmp21_36 = tt.addptr %tmp0, %tmp21_35 : tensor<1024x!tt.ptr<bf16>>, tensor<1024xi64> loc(#loc120)
+    %tmp21_37 = arith.andi %tmp18, %xmask_6 : tensor<1024xi1> loc(#loc121)
+    %tmp21_38 = tt.load %tmp21_36, %tmp21_37, %cst evictionPolicy = evict_last : tensor<1024x!tt.ptr<bf16>> loc(#loc122)
+    %tmp21_39 = arith.extf %tmp21_38 : tensor<1024xbf16> to tensor<1024xf32> loc(#loc123)
+    %tmp22 = arith.select %tmp13_24, %tmp15, %tmp21_39 : tensor<1024xi1>, tensor<1024xf32> loc(#loc135)
+    %tmp24 = tt.splat %ks4 : i64 -> tensor<1024xi64> loc(#loc126)
+    %tmp24_40 = arith.addi %tmp1_16, %tmp24 : tensor<1024xi64> loc(#loc126)
+    %tmp25 = arith.select %tmp4, %tmp24_40, %tmp1_16 : tensor<1024xi1>, tensor<1024xi64> loc(#loc127)
+    %5 = arith.cmpi sge, %tmp25, %cst_0 : tensor<1024xi64> loc(#loc55)
+    %6 = arith.cmpi slt, %tmp25, %tmp24 : tensor<1024xi64> loc(#loc56)
+    %7 = arith.andi %5, %6 : tensor<1024xi1> loc(#loc57)
+    %8 = arith.ori %7, %3 : tensor<1024xi1> loc(#loc58)
+    tt.assert %8, "index out of bounds: 0 <= tmp25 < ks4" : tensor<1024xi1> loc(#loc59)
+    %tmp27 = arith.muli %x0, %tmp25 : tensor<1024xi64> loc(#loc128)
+    %tmp27_41 = arith.addi %x0_11, %tmp27 : tensor<1024xi64> loc(#loc129)
+    %tmp27_42 = tt.splat %in_ptr3 : !tt.ptr<bf16> -> tensor<1024x!tt.ptr<bf16>> loc(#loc130)
+    %tmp27_43 = tt.addptr %tmp27_42, %tmp27_41 : tensor<1024x!tt.ptr<bf16>>, tensor<1024xi64> loc(#loc130)
+    %tmp27_44 = tt.load %tmp27_43, %xmask_6 evictionPolicy = evict_last : tensor<1024x!tt.ptr<bf16>> loc(#loc131)
+    %tmp27_45 = arith.extf %tmp27_44 : tensor<1024xbf16> to tensor<1024xf32> loc(#loc132)
+    %tmp28 = arith.mulf %tmp22, %tmp27_45 : tensor<1024xf32> loc(#loc133)
+    %tmp29 = arith.addf %tmp8, %tmp28 : tensor<1024xf32> loc(#loc134)
+    %9 = tt.splat %out_ptr0 : !tt.ptr<bf16> -> tensor<1024x!tt.ptr<bf16>> loc(#loc67)
+    %10 = tt.addptr %9, %xindex_5 : tensor<1024x!tt.ptr<bf16>>, tensor<1024xi32> loc(#loc67)
+    %11 = arith.truncf %tmp29 : tensor<1024xf32> to tensor<1024xbf16> loc(#loc68)
+    tt.store %10, %11, %xmask_6 : tensor<1024x!tt.ptr<bf16>> loc(#loc68)
+    tt.return loc(#loc69)
+  } loc(#loc)
+} loc(#loc)
+#loc1 = loc(unknown)
+#loc2 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":19:28)
+#loc3 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":19:33)
+#loc4 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":20:36)
+#loc5 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":20:23)
+#loc6 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":21:21)
+#loc7 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":23:21)
+#loc8 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":23:28)
+#loc9 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":24:19)
+#loc10 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":25:19)
+#loc11 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":26:30)
+#loc12 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":26:35)
+#loc13 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":26:75)
+#loc14 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":27:30)
+#loc15 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":27:35)
+#loc16 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":29:18)
+#loc17 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":30:18)
+#loc18 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":31:32)
+#loc19 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":32:28)
+#loc20 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":32:44)
+#loc21 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":32:37)
+#loc22 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":32:54)
+#loc23 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":32:52)
+#loc24 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":32:62)
+#loc25 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":33:39)
+#loc26 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":33:35)
+#loc27 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":33:30)
+#loc28 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":33:46)
+#loc29 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":33:86)
+#loc30 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":34:18)
+#loc31 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":38:31)
+#loc32 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":38:18)
+#loc33 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":39:19)
+#loc34 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":40:35)
+#loc35 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":40:41)
+#loc36 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":40:54)
+#loc37 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":40:31)
+#loc38 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":40:68)
+#loc39 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":40:60)
+#loc40 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":40:119)
+#loc41 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":41:13)
+#loc42 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":44:20)
+#loc43 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":47:52)
+#loc44 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":47:47)
+#loc45 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":47:60)
+#loc46 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":47:41)
+#loc47 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":47:31)
+#loc48 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":47:81)
+#loc49 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":47:73)
+#loc50 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":47:132)
+#loc51 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":48:35)
+#loc52 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":43:35)
+#loc53 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":50:19)
+#loc54 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":51:34)
+#loc55 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":52:28)
+#loc56 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":52:46)
+#loc57 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":52:38)
+#loc58 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":52:54)
+#loc59 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":52:64)
+#loc60 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":53:40)
+#loc61 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":53:36)
+#loc62 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":53:31)
+#loc63 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":53:48)
+#loc64 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":53:88)
+#loc65 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":54:20)
+#loc66 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":55:19)
+#loc67 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":56:25)
+#loc68 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":56:37)
+#loc69 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/vm/cvm76ktjawumsjmqawlhlik5wbhx6hriz5cgra754gsrszvlpuuu.py":56:4)
+#loc81 = loc("xoffset"(#loc2))
+#loc82 = loc("xoffset"(#loc3))
+#loc83 = loc("xindex"(#loc4))
+#loc84 = loc("xindex"(#loc5))
+#loc85 = loc("xmask"(#loc6))
+#loc86 = loc("x2"(#loc7))
+#loc87 = loc("x2"(#loc8))
+#loc88 = loc("x0"(#loc9))
+#loc89 = loc("x5"(#loc10))
+#loc90 = loc("tmp0"(#loc11))
+#loc91 = loc("tmp0"(#loc12))
+#loc92 = loc("tmp0"(#loc13))
+#loc93 = loc("tmp1"(#loc14))
+#loc94 = loc("tmp1"(#loc15))
+#loc95 = loc("tmp3"(#loc16))
+#loc96 = loc("tmp4"(#loc17))
+#loc97 = loc("tmp5"(#loc18))
+#loc98 = loc("tmp7"(#loc25))
+#loc99 = loc("tmp7"(#loc26))
+#loc100 = loc("tmp7"(#loc27))
+#loc101 = loc("tmp7"(#loc28))
+#loc102 = loc("tmp7"(#loc29))
+#loc103 = loc("tmp8"(#loc30))
+#loc104 = loc("tmp12"(#loc31))
+#loc105 = loc("tmp12"(#loc32))
+#loc106 = loc("tmp13"(#loc33))
+#loc107 = loc("tmp14"(#loc34))
+#loc108 = loc("tmp14"(#loc35))
+#loc109 = loc("tmp14"(#loc36))
+#loc110 = loc("tmp14"(#loc37))
+#loc111 = loc("tmp14"(#loc38))
+#loc112 = loc("tmp14"(#loc39))
+#loc113 = loc("tmp14"(#loc40))
+#loc114 = loc("tmp15"(#loc41))
+#loc115 = loc("tmp18"(#loc42))
+#loc116 = loc("tmp21"(#loc43))
+#loc117 = loc("tmp21"(#loc44))
+#loc118 = loc("tmp21"(#loc45))
+#loc119 = loc("tmp21"(#loc46))
+#loc120 = loc("tmp21"(#loc47))
+#loc121 = loc("tmp21"(#loc48))
+#loc122 = loc("tmp21"(#loc49))
+#loc123 = loc("tmp21"(#loc50))
+#loc124 = loc("tmp22"(#loc51))
+#loc125 = loc("tmp17"(#loc52))
+#loc126 = loc("tmp24"(#loc53))
+#loc127 = loc("tmp25"(#loc54))
+#loc128 = loc("tmp27"(#loc60))
+#loc129 = loc("tmp27"(#loc61))
+#loc130 = loc("tmp27"(#loc62))
+#loc131 = loc("tmp27"(#loc63))
+#loc132 = loc("tmp27"(#loc64))
+#loc133 = loc("tmp28"(#loc65))
+#loc134 = loc("tmp29"(#loc66))
+#loc135 = loc(fused[#loc124, #loc125])

SpecForge-ext/cache/compiled_kernels/triton/2/4BXPLEVNIV4ISF7IZIVK7CAM4LM5YGYX34PZFJY2Q7MUVWT7ZGUA/__grp__triton_per_fused__to_copy_arange_bitwise_and_eq_gt_index_put_lt_new_zeros_scalar_tensor_sort_sum_unsqueeze_view_where_2.json

@@ -0,0 +1 @@
+{"child_paths": {"triton_per_fused__to_copy_arange_bitwise_and_eq_gt_index_put_lt_new_zeros_scalar_tensor_sort_sum_unsqueeze_view_where_2.source": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/4BXPLEVNIV4ISF7IZIVK7CAM4LM5YGYX34PZFJY2Q7MUVWT7ZGUA/triton_per_fused__to_copy_arange_bitwise_and_eq_gt_index_put_lt_new_zeros_scalar_tensor_sort_sum_unsqueeze_view_where_2.source", "triton_per_fused__to_copy_arange_bitwise_and_eq_gt_index_put_lt_new_zeros_scalar_tensor_sort_sum_unsqueeze_view_where_2.ttir": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/4BXPLEVNIV4ISF7IZIVK7CAM4LM5YGYX34PZFJY2Q7MUVWT7ZGUA/triton_per_fused__to_copy_arange_bitwise_and_eq_gt_index_put_lt_new_zeros_scalar_tensor_sort_sum_unsqueeze_view_where_2.ttir", "triton_per_fused__to_copy_arange_bitwise_and_eq_gt_index_put_lt_new_zeros_scalar_tensor_sort_sum_unsqueeze_view_where_2.ttgir": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/4BXPLEVNIV4ISF7IZIVK7CAM4LM5YGYX34PZFJY2Q7MUVWT7ZGUA/triton_per_fused__to_copy_arange_bitwise_and_eq_gt_index_put_lt_new_zeros_scalar_tensor_sort_sum_unsqueeze_view_where_2.ttgir", "triton_per_fused__to_copy_arange_bitwise_and_eq_gt_index_put_lt_new_zeros_scalar_tensor_sort_sum_unsqueeze_view_where_2.llir": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/4BXPLEVNIV4ISF7IZIVK7CAM4LM5YGYX34PZFJY2Q7MUVWT7ZGUA/triton_per_fused__to_copy_arange_bitwise_and_eq_gt_index_put_lt_new_zeros_scalar_tensor_sort_sum_unsqueeze_view_where_2.llir", "triton_per_fused__to_copy_arange_bitwise_and_eq_gt_index_put_lt_new_zeros_scalar_tensor_sort_sum_unsqueeze_view_where_2.ptx": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/4BXPLEVNIV4ISF7IZIVK7CAM4LM5YGYX34PZFJY2Q7MUVWT7ZGUA/triton_per_fused__to_copy_arange_bitwise_and_eq_gt_index_put_lt_new_zeros_scalar_tensor_sort_sum_unsqueeze_view_where_2.ptx", "triton_per_fused__to_copy_arange_bitwise_and_eq_gt_index_put_lt_new_zeros_scalar_tensor_sort_sum_unsqueeze_view_where_2.cubin": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/4BXPLEVNIV4ISF7IZIVK7CAM4LM5YGYX34PZFJY2Q7MUVWT7ZGUA/triton_per_fused__to_copy_arange_bitwise_and_eq_gt_index_put_lt_new_zeros_scalar_tensor_sort_sum_unsqueeze_view_where_2.cubin", "triton_per_fused__to_copy_arange_bitwise_and_eq_gt_index_put_lt_new_zeros_scalar_tensor_sort_sum_unsqueeze_view_where_2.json": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/4BXPLEVNIV4ISF7IZIVK7CAM4LM5YGYX34PZFJY2Q7MUVWT7ZGUA/triton_per_fused__to_copy_arange_bitwise_and_eq_gt_index_put_lt_new_zeros_scalar_tensor_sort_sum_unsqueeze_view_where_2.json"}}

SpecForge-ext/cache/compiled_kernels/triton/2/4BXPLEVNIV4ISF7IZIVK7CAM4LM5YGYX34PZFJY2Q7MUVWT7ZGUA/triton_per_fused__to_copy_arange_bitwise_and_eq_gt_index_put_lt_new_zeros_scalar_tensor_sort_sum_unsqueeze_view_where_2.json

@@ -0,0 +1 @@
+{"hash": "e06ef592ad45788917e8ca2aaf880ce2d9dc1b17df1f92a71a87d94ada7fc9a8", "target": {"backend": "cuda", "arch": 90, "warp_size": 32}, "num_warps": 8, "num_ctas": 1, "num_stages": 1, "warp_size": 32, "maxnreg": null, "cluster_dims": [1, 1, 1], "ptx_version": null, "ptx_options": null, "ir_override": null, "enable_fp_fusion": true, "launch_cooperative_grid": false, "launch_pdl": false, "supported_fp8_dtypes": ["fp8e4b15", "fp8e4nv", "fp8e5"], "deprecated_fp8_dot_operand_dtypes": ["fp8e4b15"], "default_dot_input_precision": "tf32", "allowed_dot_input_precisions": ["tf32", "tf32x3", "ieee"], "max_num_imprecise_acc_default": 1073741824, "extern_libs": [["libdevice", "/workspace/specforge/lib/python3.11/site-packages/triton/backends/nvidia/lib/libdevice.10.bc"]], "debug": true, "backend_name": "cuda", "sanitize_overflow": false, "arch": "sm90", "instrumentation_mode": "", "triton_version": "3.5.1", "tensordesc_meta": [], "shared": 16384, "tmem_size": 0, "global_scratch_size": 0, "global_scratch_align": 1, "profile_scratch_size": 0, "profile_scratch_align": 1, "name": "triton_per_fused__to_copy_arange_bitwise_and_eq_gt_index_put_lt_new_zeros_scalar_tensor_sort_sum_unsqueeze_view_where_2"}

SpecForge-ext/cache/compiled_kernels/triton/2/4UWYNBR3KPWQGNAZ5LIIRE7YAZWTQP4CP3JS6GOSLWYDF5K7WTAA/__grp__triton_poi_fused_new_zeros_1.json

@@ -0,0 +1 @@
+{"child_paths": {"triton_poi_fused_new_zeros_1.source": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/4UWYNBR3KPWQGNAZ5LIIRE7YAZWTQP4CP3JS6GOSLWYDF5K7WTAA/triton_poi_fused_new_zeros_1.source", "triton_poi_fused_new_zeros_1.ttir": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/4UWYNBR3KPWQGNAZ5LIIRE7YAZWTQP4CP3JS6GOSLWYDF5K7WTAA/triton_poi_fused_new_zeros_1.ttir", "triton_poi_fused_new_zeros_1.ttgir": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/4UWYNBR3KPWQGNAZ5LIIRE7YAZWTQP4CP3JS6GOSLWYDF5K7WTAA/triton_poi_fused_new_zeros_1.ttgir", "triton_poi_fused_new_zeros_1.llir": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/4UWYNBR3KPWQGNAZ5LIIRE7YAZWTQP4CP3JS6GOSLWYDF5K7WTAA/triton_poi_fused_new_zeros_1.llir", "triton_poi_fused_new_zeros_1.ptx": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/4UWYNBR3KPWQGNAZ5LIIRE7YAZWTQP4CP3JS6GOSLWYDF5K7WTAA/triton_poi_fused_new_zeros_1.ptx", "triton_poi_fused_new_zeros_1.cubin": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/4UWYNBR3KPWQGNAZ5LIIRE7YAZWTQP4CP3JS6GOSLWYDF5K7WTAA/triton_poi_fused_new_zeros_1.cubin", "triton_poi_fused_new_zeros_1.json": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/4UWYNBR3KPWQGNAZ5LIIRE7YAZWTQP4CP3JS6GOSLWYDF5K7WTAA/triton_poi_fused_new_zeros_1.json"}}

SpecForge-ext/cache/compiled_kernels/triton/2/4UWYNBR3KPWQGNAZ5LIIRE7YAZWTQP4CP3JS6GOSLWYDF5K7WTAA/triton_poi_fused_new_zeros_1.json

@@ -0,0 +1 @@
+{"hash": "e52d86863b53ed033419ead08893f8066d383f827ed32f19d25db032f55fb4c0", "target": {"backend": "cuda", "arch": 90, "warp_size": 32}, "num_warps": 4, "num_ctas": 1, "num_stages": 1, "warp_size": 32, "maxnreg": null, "cluster_dims": [1, 1, 1], "ptx_version": null, "ptx_options": null, "ir_override": null, "enable_fp_fusion": true, "launch_cooperative_grid": false, "launch_pdl": false, "supported_fp8_dtypes": ["fp8e4b15", "fp8e4nv", "fp8e5"], "deprecated_fp8_dot_operand_dtypes": ["fp8e4b15"], "default_dot_input_precision": "tf32", "allowed_dot_input_precisions": ["tf32", "tf32x3", "ieee"], "max_num_imprecise_acc_default": 1073741824, "extern_libs": [["libdevice", "/workspace/specforge/lib/python3.11/site-packages/triton/backends/nvidia/lib/libdevice.10.bc"]], "debug": true, "backend_name": "cuda", "sanitize_overflow": false, "arch": "sm90", "instrumentation_mode": "", "triton_version": "3.5.1", "tensordesc_meta": [], "shared": 0, "tmem_size": 0, "global_scratch_size": 0, "global_scratch_align": 1, "profile_scratch_size": 0, "profile_scratch_align": 1, "name": "triton_poi_fused_new_zeros_1"}

SpecForge-ext/cache/compiled_kernels/triton/2/4UWYNBR3KPWQGNAZ5LIIRE7YAZWTQP4CP3JS6GOSLWYDF5K7WTAA/triton_poi_fused_new_zeros_1.llir

@@ -0,0 +1,47 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+target datalayout = "e-p3:32:32-p4:32:32-p5:32:32-p6:32:32-p7:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64"
+
+; Function Attrs: nounwind
+define ptx_kernel void @triton_poi_fused_new_zeros_1(ptr addrspace(1) %0, i32 %1, ptr addrspace(1) readnone captures(none) %2, ptr addrspace(1) readnone captures(none) %3) local_unnamed_addr #0 !dbg !4 {
+  %5 = tail call i32 @llvm.nvvm.read.ptx.sreg.ctaid.x(), !dbg !7
+  %6 = shl i32 %5, 8, !dbg !8
+  %7 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !9
+  %8 = shl nuw nsw i32 %7, 1, !dbg !9
+  %9 = and i32 %8, 254, !dbg !9
+  %10 = or disjoint i32 %9, %6, !dbg !10
+  %11 = icmp slt i32 %10, 2176, !dbg !11
+  %12 = sext i32 %10 to i64, !dbg !12
+  %13 = getelementptr i32, ptr addrspace(1) %0, i64 %12, !dbg !12
+  tail call void asm sideeffect "@$3 st.global.v2.b32 [ $2 + 0 ], { $0, $1 };", "r,r,l,b"(i32 0, i32 0, ptr addrspace(1) %13, i1 %11) #2, !dbg !13
+  ret void, !dbg !14
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef range(i32 0, 2147483647) i32 @llvm.nvvm.read.ptx.sreg.ctaid.x() #1
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef range(i32 0, 1024) i32 @llvm.nvvm.read.ptx.sreg.tid.x() #1
+
+attributes #0 = { nounwind "nvvm.reqntid"="128" }
+attributes #1 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #2 = { nounwind }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!2, !3}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C, file: !1, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: LineTablesOnly)
+!1 = !DIFile(filename: "cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py", directory: "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/ib")
+!2 = !{i32 2, !"Debug Info Version", i32 3}
+!3 = !{i32 4, !"nvvm-reflect-ftz", i32 1}
+!4 = distinct !DISubprogram(name: "triton_poi_fused_new_zeros_1", linkageName: "triton_poi_fused_new_zeros_1", scope: !1, file: !1, line: 18, type: !5, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0)
+!5 = !DISubroutineType(cc: DW_CC_normal, types: !6)
+!6 = !{}
+!7 = !DILocation(line: 20, column: 28, scope: !4)
+!8 = !DILocation(line: 20, column: 33, scope: !4)
+!9 = !DILocation(line: 21, column: 36, scope: !4)
+!10 = !DILocation(line: 21, column: 23, scope: !4)
+!11 = !DILocation(line: 22, column: 21, scope: !4)
+!12 = !DILocation(line: 25, column: 25, scope: !4)
+!13 = !DILocation(line: 25, column: 36, scope: !4)
+!14 = !DILocation(line: 25, column: 4, scope: !4)

SpecForge-ext/cache/compiled_kernels/triton/2/4UWYNBR3KPWQGNAZ5LIIRE7YAZWTQP4CP3JS6GOSLWYDF5K7WTAA/triton_poi_fused_new_zeros_1.ptx

@@ -0,0 +1,207 @@
+//
+// Generated by LLVM NVPTX Back-End
+//
+
+.version 8.7
+.target sm_90a
+.address_size 64
+
+	// .globl	triton_poi_fused_new_zeros_1 // -- Begin function triton_poi_fused_new_zeros_1
+                                        // @triton_poi_fused_new_zeros_1
+.visible .entry triton_poi_fused_new_zeros_1(
+	.param .u64 .ptr .global .align 1 triton_poi_fused_new_zeros_1_param_0,
+	.param .u32 triton_poi_fused_new_zeros_1_param_1,
+	.param .u64 .ptr .global .align 1 triton_poi_fused_new_zeros_1_param_2,
+	.param .u64 .ptr .global .align 1 triton_poi_fused_new_zeros_1_param_3
+)
+.reqntid 128
+{
+	.reg .pred 	%p<2>;
+	.reg .b32 	%r<9>;
+	.reg .b64 	%rd<3>;
+	.loc	1 18 0                          // cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py:18:0
+$L__func_begin0:
+	.loc	1 18 0                          // cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py:18:0
+
+// %bb.0:
+	ld.param.b64 	%rd2, [triton_poi_fused_new_zeros_1_param_0];
+$L__tmp0:
+	.loc	1 20 28                         // cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py:20:28
+	mov.u32 	%r3, %ctaid.x;
+	.loc	1 20 33                         // cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py:20:33
+	shl.b32 	%r4, %r3, 8;
+	.loc	1 21 36                         // cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py:21:36
+	mov.u32 	%r5, %tid.x;
+	shl.b32 	%r6, %r5, 1;
+	and.b32 	%r7, %r6, 254;
+	.loc	1 21 23                         // cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py:21:23
+	or.b32 	%r8, %r7, %r4;
+	.loc	1 22 21                         // cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py:22:21
+	setp.lt.s32 	%p1, %r8, 2176;
+	.loc	1 25 25                         // cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py:25:25
+	mad.wide.s32 	%rd1, %r8, 4, %rd2;
+	mov.b32 	%r1, 0;
+	.loc	1 25 36                         // cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py:25:36
+	// begin inline asm
+	@%p1 st.global.v2.b32 [ %rd1 + 0 ], { %r1, %r1 };
+	// end inline asm
+	.loc	1 25 4                          // cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py:25:4
+	ret;
+$L__tmp1:
+$L__func_end0:
+                                        // -- End function
+}
+	.file	1 "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/ib/cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py"
+	.section	.debug_abbrev
+	{
+.b8 1                                   // Abbreviation Code
+.b8 17                                  // DW_TAG_compile_unit
+.b8 0                                   // DW_CHILDREN_no
+.b8 37                                  // DW_AT_producer
+.b8 8                                   // DW_FORM_string
+.b8 19                                  // DW_AT_language
+.b8 5                                   // DW_FORM_data2
+.b8 3                                   // DW_AT_name
+.b8 8                                   // DW_FORM_string
+.b8 16                                  // DW_AT_stmt_list
+.b8 6                                   // DW_FORM_data4
+.b8 27                                  // DW_AT_comp_dir
+.b8 8                                   // DW_FORM_string
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 0                                   // EOM(3)
+	}
+	.section	.debug_info
+	{
+.b32 135                                // Length of Unit
+.b8 2                                   // DWARF version number
+.b8 0
+.b32 .debug_abbrev                      // Offset Into Abbrev. Section
+.b8 8                                   // Address Size (in bytes)
+.b8 1                                   // Abbrev [1] 0xb:0x80 DW_TAG_compile_unit
+.b8 116                                 // DW_AT_producer
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 0
+.b8 2                                   // DW_AT_language
+.b8 0
+.b8 99                                  // DW_AT_name
+.b8 105
+.b8 98
+.b8 103
+.b8 99
+.b8 114
+.b8 101
+.b8 106
+.b8 98
+.b8 55
+.b8 52
+.b8 121
+.b8 122
+.b8 51
+.b8 107
+.b8 52
+.b8 99
+.b8 98
+.b8 111
+.b8 53
+.b8 108
+.b8 113
+.b8 113
+.b8 109
+.b8 51
+.b8 109
+.b8 111
+.b8 107
+.b8 118
+.b8 102
+.b8 52
+.b8 108
+.b8 103
+.b8 52
+.b8 99
+.b8 101
+.b8 108
+.b8 100
+.b8 55
+.b8 101
+.b8 53
+.b8 98
+.b8 99
+.b8 100
+.b8 110
+.b8 120
+.b8 110
+.b8 118
+.b8 121
+.b8 50
+.b8 118
+.b8 101
+.b8 46
+.b8 112
+.b8 121
+.b8 0
+.b32 .debug_line                        // DW_AT_stmt_list
+.b8 47                                  // DW_AT_comp_dir
+.b8 119
+.b8 111
+.b8 114
+.b8 107
+.b8 115
+.b8 112
+.b8 97
+.b8 99
+.b8 101
+.b8 47
+.b8 104
+.b8 97
+.b8 110
+.b8 114
+.b8 117
+.b8 105
+.b8 47
+.b8 83
+.b8 112
+.b8 101
+.b8 99
+.b8 70
+.b8 111
+.b8 114
+.b8 103
+.b8 101
+.b8 45
+.b8 101
+.b8 120
+.b8 116
+.b8 47
+.b8 99
+.b8 97
+.b8 99
+.b8 104
+.b8 101
+.b8 47
+.b8 99
+.b8 111
+.b8 109
+.b8 112
+.b8 105
+.b8 108
+.b8 101
+.b8 100
+.b8 95
+.b8 107
+.b8 101
+.b8 114
+.b8 110
+.b8 101
+.b8 108
+.b8 115
+.b8 47
+.b8 105
+.b8 98
+.b8 0
+	}
+	.section	.debug_macinfo	{	}

SpecForge-ext/cache/compiled_kernels/triton/2/4UWYNBR3KPWQGNAZ5LIIRE7YAZWTQP4CP3JS6GOSLWYDF5K7WTAA/triton_poi_fused_new_zeros_1.source

@@ -0,0 +1,41 @@
+#loc = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/ib/cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py":18:0)
+#loc11 = loc("out_ptr0"(#loc))
+#loc12 = loc("xnumel"(#loc))
+module {
+  tt.func public @triton_poi_fused_new_zeros_1(%out_ptr0: !tt.ptr<i32> {tt.divisibility = 16 : i32} loc("out_ptr0"(#loc)), %xnumel: i32 {tt.divisibility = 16 : i32} loc("xnumel"(#loc))) attributes {noinline = false} {
+    %xnumel_0 = arith.constant 2176 : i32 loc(#loc13)
+    %xoffset = tt.get_program_id x : i32 loc(#loc14)
+    %xoffset_1 = arith.constant 256 : i32 loc(#loc15)
+    %xoffset_2 = arith.constant 256 : i32 loc(#loc15)
+    %xoffset_3 = arith.muli %xoffset, %xoffset_2 : i32 loc(#loc15)
+    %xindex = tt.make_range {end = 256 : i32, start = 0 : i32} : tensor<256xi32> loc(#loc16)
+    %xindex_4 = tt.splat %xoffset_3 : i32 -> tensor<256xi32> loc(#loc17)
+    %xindex_5 = arith.addi %xindex_4, %xindex : tensor<256xi32> loc(#loc17)
+    %xmask = arith.constant dense<2176> : tensor<256xi32> loc(#loc18)
+    %xmask_6 = arith.cmpi slt, %xindex_5, %xmask : tensor<256xi32> loc(#loc18)
+    %tmp0 = arith.constant 0 : i32 loc(#loc19)
+    %tmp0_7 = arith.constant dense<0> : tensor<1xi32> loc(#loc19)
+    %0 = tt.splat %out_ptr0 : !tt.ptr<i32> -> tensor<256x!tt.ptr<i32>> loc(#loc8)
+    %1 = tt.addptr %0, %xindex_5 : tensor<256x!tt.ptr<i32>>, tensor<256xi32> loc(#loc8)
+    %cst = arith.constant dense<0> : tensor<256xi32> loc(#loc9)
+    tt.store %1, %cst, %xmask_6 : tensor<256x!tt.ptr<i32>> loc(#loc9)
+    tt.return loc(#loc10)
+  } loc(#loc)
+} loc(#loc)
+#loc1 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/ib/cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py":19:13)
+#loc2 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/ib/cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py":20:28)
+#loc3 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/ib/cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py":20:33)
+#loc4 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/ib/cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py":21:36)
+#loc5 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/ib/cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py":21:23)
+#loc6 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/ib/cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py":22:21)
+#loc7 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/ib/cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py":24:27)
+#loc8 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/ib/cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py":25:25)
+#loc9 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/ib/cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py":25:36)
+#loc10 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/ib/cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py":25:4)
+#loc13 = loc("xnumel"(#loc1))
+#loc14 = loc("xoffset"(#loc2))
+#loc15 = loc("xoffset"(#loc3))
+#loc16 = loc("xindex"(#loc4))
+#loc17 = loc("xindex"(#loc5))
+#loc18 = loc("xmask"(#loc6))
+#loc19 = loc("tmp0"(#loc7))

SpecForge-ext/cache/compiled_kernels/triton/2/4UWYNBR3KPWQGNAZ5LIIRE7YAZWTQP4CP3JS6GOSLWYDF5K7WTAA/triton_poi_fused_new_zeros_1.ttgir

@@ -0,0 +1,35 @@
+#blocked = #ttg.blocked<{sizePerThread = [2], threadsPerWarp = [32], warpsPerCTA = [4], order = [0]}>
+#loc = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/ib/cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py":18:0)
+#loc10 = loc("out_ptr0"(#loc))
+#loc11 = loc("xnumel"(#loc))
+module attributes {"ttg.num-ctas" = 1 : i32, "ttg.num-warps" = 4 : i32, ttg.target = "cuda:90", "ttg.threads-per-warp" = 32 : i32} {
+  tt.func public @triton_poi_fused_new_zeros_1(%out_ptr0: !tt.ptr<i32> {tt.divisibility = 16 : i32} loc("out_ptr0"(#loc)), %xnumel: i32 {tt.divisibility = 16 : i32} loc("xnumel"(#loc))) attributes {noinline = false} {
+    %cst = arith.constant dense<2176> : tensor<256xi32, #blocked> loc(#loc1)
+    %cst_0 = arith.constant dense<0> : tensor<256xi32, #blocked> loc(#loc1)
+    %c256_i32 = arith.constant 256 : i32 loc(#loc1)
+    %xoffset = tt.get_program_id x : i32 loc(#loc12)
+    %xoffset_1 = arith.muli %xoffset, %c256_i32 : i32 loc(#loc13)
+    %xindex = tt.make_range {end = 256 : i32, start = 0 : i32} : tensor<256xi32, #blocked> loc(#loc14)
+    %xindex_2 = tt.splat %xoffset_1 : i32 -> tensor<256xi32, #blocked> loc(#loc15)
+    %xindex_3 = arith.addi %xindex_2, %xindex : tensor<256xi32, #blocked> loc(#loc15)
+    %xmask = arith.cmpi slt, %xindex_3, %cst : tensor<256xi32, #blocked> loc(#loc16)
+    %0 = tt.splat %out_ptr0 : !tt.ptr<i32> -> tensor<256x!tt.ptr<i32>, #blocked> loc(#loc7)
+    %1 = tt.addptr %0, %xindex_3 : tensor<256x!tt.ptr<i32>, #blocked>, tensor<256xi32, #blocked> loc(#loc7)
+    tt.store %1, %cst_0, %xmask : tensor<256x!tt.ptr<i32>, #blocked> loc(#loc8)
+    tt.return loc(#loc9)
+  } loc(#loc)
+} loc(#loc)
+#loc1 = loc(unknown)
+#loc2 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/ib/cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py":20:28)
+#loc3 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/ib/cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py":20:33)
+#loc4 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/ib/cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py":21:36)
+#loc5 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/ib/cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py":21:23)
+#loc6 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/ib/cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py":22:21)
+#loc7 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/ib/cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py":25:25)
+#loc8 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/ib/cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py":25:36)
+#loc9 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/ib/cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py":25:4)
+#loc12 = loc("xoffset"(#loc2))
+#loc13 = loc("xoffset"(#loc3))
+#loc14 = loc("xindex"(#loc4))
+#loc15 = loc("xindex"(#loc5))
+#loc16 = loc("xmask"(#loc6))

SpecForge-ext/cache/compiled_kernels/triton/2/4UWYNBR3KPWQGNAZ5LIIRE7YAZWTQP4CP3JS6GOSLWYDF5K7WTAA/triton_poi_fused_new_zeros_1.ttir

@@ -0,0 +1,34 @@
+#loc = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/ib/cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py":18:0)
+#loc10 = loc("out_ptr0"(#loc))
+#loc11 = loc("xnumel"(#loc))
+module {
+  tt.func public @triton_poi_fused_new_zeros_1(%out_ptr0: !tt.ptr<i32> {tt.divisibility = 16 : i32} loc("out_ptr0"(#loc)), %xnumel: i32 {tt.divisibility = 16 : i32} loc("xnumel"(#loc))) attributes {noinline = false} {
+    %cst = arith.constant dense<0> : tensor<256xi32> loc(#loc1)
+    %xmask = arith.constant dense<2176> : tensor<256xi32> loc(#loc12)
+    %c256_i32 = arith.constant 256 : i32 loc(#loc3)
+    %xoffset = tt.get_program_id x : i32 loc(#loc13)
+    %xoffset_0 = arith.muli %xoffset, %c256_i32 : i32 loc(#loc14)
+    %xindex = tt.make_range {end = 256 : i32, start = 0 : i32} : tensor<256xi32> loc(#loc15)
+    %xindex_1 = tt.splat %xoffset_0 : i32 -> tensor<256xi32> loc(#loc16)
+    %xindex_2 = arith.addi %xindex_1, %xindex : tensor<256xi32> loc(#loc16)
+    %xmask_3 = arith.cmpi slt, %xindex_2, %xmask : tensor<256xi32> loc(#loc12)
+    %0 = tt.splat %out_ptr0 : !tt.ptr<i32> -> tensor<256x!tt.ptr<i32>> loc(#loc8)
+    %1 = tt.addptr %0, %xindex_2 : tensor<256x!tt.ptr<i32>>, tensor<256xi32> loc(#loc8)
+    tt.store %1, %cst, %xmask_3 : tensor<256x!tt.ptr<i32>> loc(#loc1)
+    tt.return loc(#loc9)
+  } loc(#loc)
+} loc(#loc)
+#loc1 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/ib/cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py":25:36)
+#loc2 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/ib/cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py":22:21)
+#loc3 = loc(unknown)
+#loc4 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/ib/cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py":20:28)
+#loc5 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/ib/cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py":20:33)
+#loc6 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/ib/cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py":21:36)
+#loc7 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/ib/cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py":21:23)
+#loc8 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/ib/cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py":25:25)
+#loc9 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/ib/cibgcrejb74yz3k4cbo5lqqm3mokvf4lg4celd7e5bcdnxnvy2ve.py":25:4)
+#loc12 = loc("xmask"(#loc2))
+#loc13 = loc("xoffset"(#loc4))
+#loc14 = loc("xoffset"(#loc5))
+#loc15 = loc("xindex"(#loc6))
+#loc16 = loc("xindex"(#loc7))

SpecForge-ext/cache/compiled_kernels/triton/2/5KYA3IXELFPSJGJX4ZJXZEGZVFALDHEANQ7YQX554R55QVAC6F5A/__grp__triton_red_fused__to_copy_mul_sum_0.json

@@ -0,0 +1 @@
+{"child_paths": {"triton_red_fused__to_copy_mul_sum_0.source": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/5KYA3IXELFPSJGJX4ZJXZEGZVFALDHEANQ7YQX554R55QVAC6F5A/triton_red_fused__to_copy_mul_sum_0.source", "triton_red_fused__to_copy_mul_sum_0.ttir": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/5KYA3IXELFPSJGJX4ZJXZEGZVFALDHEANQ7YQX554R55QVAC6F5A/triton_red_fused__to_copy_mul_sum_0.ttir", "triton_red_fused__to_copy_mul_sum_0.ttgir": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/5KYA3IXELFPSJGJX4ZJXZEGZVFALDHEANQ7YQX554R55QVAC6F5A/triton_red_fused__to_copy_mul_sum_0.ttgir", "triton_red_fused__to_copy_mul_sum_0.llir": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/5KYA3IXELFPSJGJX4ZJXZEGZVFALDHEANQ7YQX554R55QVAC6F5A/triton_red_fused__to_copy_mul_sum_0.llir", "triton_red_fused__to_copy_mul_sum_0.ptx": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/5KYA3IXELFPSJGJX4ZJXZEGZVFALDHEANQ7YQX554R55QVAC6F5A/triton_red_fused__to_copy_mul_sum_0.ptx", "triton_red_fused__to_copy_mul_sum_0.cubin": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/5KYA3IXELFPSJGJX4ZJXZEGZVFALDHEANQ7YQX554R55QVAC6F5A/triton_red_fused__to_copy_mul_sum_0.cubin", "triton_red_fused__to_copy_mul_sum_0.json": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/5KYA3IXELFPSJGJX4ZJXZEGZVFALDHEANQ7YQX554R55QVAC6F5A/triton_red_fused__to_copy_mul_sum_0.json"}}

SpecForge-ext/cache/compiled_kernels/triton/2/5KYA3IXELFPSJGJX4ZJXZEGZVFALDHEANQ7YQX554R55QVAC6F5A/triton_red_fused__to_copy_mul_sum_0.json

@@ -0,0 +1 @@
+{"hash": "eab00da2e4595f249937e6537c90d9a940b19c806c3f885fbde47bd85402f17a", "target": {"backend": "cuda", "arch": 90, "warp_size": 32}, "num_warps": 4, "num_ctas": 1, "num_stages": 1, "warp_size": 32, "maxnreg": null, "cluster_dims": [1, 1, 1], "ptx_version": null, "ptx_options": null, "ir_override": null, "enable_fp_fusion": true, "launch_cooperative_grid": false, "launch_pdl": false, "supported_fp8_dtypes": ["fp8e4b15", "fp8e4nv", "fp8e5"], "deprecated_fp8_dot_operand_dtypes": ["fp8e4b15"], "default_dot_input_precision": "tf32", "allowed_dot_input_precisions": ["tf32", "tf32x3", "ieee"], "max_num_imprecise_acc_default": 1073741824, "extern_libs": [["libdevice", "/workspace/specforge/lib/python3.11/site-packages/triton/backends/nvidia/lib/libdevice.10.bc"]], "debug": true, "backend_name": "cuda", "sanitize_overflow": false, "arch": "sm90", "instrumentation_mode": "", "triton_version": "3.5.1", "tensordesc_meta": [], "shared": 512, "tmem_size": 0, "global_scratch_size": 0, "global_scratch_align": 1, "profile_scratch_size": 0, "profile_scratch_align": 1, "name": "triton_red_fused__to_copy_mul_sum_0"}

SpecForge-ext/cache/compiled_kernels/triton/2/5KYA3IXELFPSJGJX4ZJXZEGZVFALDHEANQ7YQX554R55QVAC6F5A/triton_red_fused__to_copy_mul_sum_0.llir

@@ -0,0 +1,256 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+target datalayout = "e-p3:32:32-p4:32:32-p5:32:32-p6:32:32-p7:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64"
+
+@global_smem = external addrspace(3) global [0 x i8], align 16
+
+; Function Attrs: nounwind
+define ptx_kernel void @triton_red_fused__to_copy_mul_sum_0(ptr addrspace(1) %0, ptr addrspace(1) %1, ptr addrspace(1) %2, ptr addrspace(1) %3, i64 %4, i64 %5, i64 %6, i32 %7, i32 %8, ptr addrspace(1) readnone captures(none) %9, ptr addrspace(1) readnone captures(none) %10) local_unnamed_addr #0 !dbg !4 {
+  %12 = tail call i32 @llvm.nvvm.read.ptx.sreg.ctaid.x(), !dbg !7
+  %13 = shl i32 %12, 6, !dbg !8
+  %14 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !9
+  %15 = and i32 %14, 63, !dbg !9
+  %16 = or disjoint i32 %13, %15, !dbg !10
+  %17 = icmp slt i32 %16, %7, !dbg !11
+  %18 = lshr i32 %14, 6, !dbg !12
+  %.lobit = and i32 %18, 1, !dbg !12
+  %19 = sext i32 %16 to i64, !dbg !13
+  %.frozen = freeze i64 %4, !dbg !13
+  %20 = sdiv i64 %19, %.frozen, !dbg !13
+  %21 = mul i64 %20, %.frozen, !dbg !14
+  %.decomposed = sub i64 %19, %21, !dbg !14
+  %22 = mul i64 %6, %5, !dbg !15
+  %23 = add i64 %22, 31, !dbg !16
+  %24 = sdiv i64 %23, 32, !dbg !17
+  %25 = mul i64 %20, %24, !dbg !18
+  %26 = icmp sgt i32 %8, 0, !dbg !19
+  br i1 %26, label %.lr.ph.preheader, label %._crit_edge, !dbg !19
+
+.lr.ph.preheader:                                 ; preds = %11
+  %27 = insertelement <4 x i32> poison, i32 %8, i64 0
+  %28 = shufflevector <4 x i32> %27, <4 x i32> poison, <4 x i32> zeroinitializer
+  %29 = insertelement <4 x i64> poison, i64 %25, i64 0
+  %30 = shufflevector <4 x i64> %29, <4 x i64> poison, <4 x i32> zeroinitializer
+  %31 = insertelement <4 x i64> poison, i64 %22, i64 0
+  %32 = shufflevector <4 x i64> %31, <4 x i64> poison, <4 x i32> zeroinitializer
+  %33 = insertelement <4 x i1> poison, i1 %17, i64 0
+  %34 = shufflevector <4 x i1> %33, <4 x i1> poison, <4 x i32> zeroinitializer
+  br label %.lr.ph, !dbg !19
+
+.lr.ph:                                           ; preds = %.lr.ph.preheader, %.lr.ph
+  %35 = phi i32 [ %132, %.lr.ph ], [ 0, %.lr.ph.preheader ]
+  %36 = phi <4 x float> [ %131, %.lr.ph ], [ zeroinitializer, %.lr.ph.preheader ]
+  %37 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !20
+  %38 = or disjoint i32 %35, %.lobit, !dbg !21
+  %39 = or disjoint i32 %38, 2, !dbg !21
+  %40 = or disjoint i32 %38, 4, !dbg !21
+  %41 = or disjoint i32 %38, 6, !dbg !21
+  %42 = insertelement <4 x i32> poison, i32 %38, i64 0, !dbg !22
+  %43 = insertelement <4 x i32> %42, i32 %39, i64 1, !dbg !22
+  %44 = insertelement <4 x i32> %43, i32 %40, i64 2, !dbg !22
+  %45 = insertelement <4 x i32> %44, i32 %41, i64 3, !dbg !22
+  %46 = icmp slt <4 x i32> %45, %28, !dbg !22
+  %47 = sext <4 x i32> %45 to <4 x i64>, !dbg !23
+  %48 = add <4 x i64> %30, %47, !dbg !23
+  %49 = icmp slt <4 x i64> %48, %32, !dbg !24
+  %50 = extractelement <4 x i64> %48, i64 0, !dbg !25
+  %51 = srem i64 %50, %22, !dbg !25
+  %52 = extractelement <4 x i64> %48, i64 1, !dbg !25
+  %53 = srem i64 %52, %22, !dbg !25
+  %54 = extractelement <4 x i64> %48, i64 2, !dbg !25
+  %55 = srem i64 %54, %22, !dbg !25
+  %56 = extractelement <4 x i64> %48, i64 3, !dbg !25
+  %57 = srem i64 %56, %22, !dbg !25
+  %58 = mul i64 %51, %4, !dbg !26
+  %59 = mul i64 %53, %4, !dbg !26
+  %60 = mul i64 %55, %4, !dbg !26
+  %61 = mul i64 %57, %4, !dbg !26
+  %62 = add i64 %58, %.decomposed, !dbg !27
+  %63 = add i64 %59, %.decomposed, !dbg !27
+  %64 = add i64 %60, %.decomposed, !dbg !27
+  %65 = add i64 %61, %.decomposed, !dbg !27
+  %66 = getelementptr bfloat, ptr addrspace(1) %0, i64 %62, !dbg !28
+  %67 = getelementptr bfloat, ptr addrspace(1) %0, i64 %63, !dbg !28
+  %68 = getelementptr bfloat, ptr addrspace(1) %0, i64 %64, !dbg !28
+  %69 = getelementptr bfloat, ptr addrspace(1) %0, i64 %65, !dbg !28
+  %foldExtExtBinop = and <4 x i1> %46, %49, !dbg !29
+  %70 = extractelement <4 x i1> %foldExtExtBinop, i64 0, !dbg !29
+  %foldExtExtBinop8 = and <4 x i1> %46, %49, !dbg !29
+  %71 = extractelement <4 x i1> %foldExtExtBinop8, i64 1, !dbg !29
+  %foldExtExtBinop10 = and <4 x i1> %46, %49, !dbg !29
+  %72 = extractelement <4 x i1> %foldExtExtBinop10, i64 2, !dbg !29
+  %foldExtExtBinop12 = and <4 x i1> %46, %49, !dbg !29
+  %73 = extractelement <4 x i1> %foldExtExtBinop12, i64 3, !dbg !29
+  %74 = and i1 %17, %70, !dbg !30
+  %75 = and i1 %17, %71, !dbg !30
+  %76 = and i1 %17, %72, !dbg !30
+  %77 = and i1 %17, %73, !dbg !30
+  %78 = tail call i16 asm sideeffect "mov.u16 $0, $1;\0A\09@$4 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $2 + 0 ], $3;", "=c,c,l,l,b"(i16 0, ptr addrspace(1) %66, i64 %37, i1 %74) #4, !dbg !20
+  %79 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !20
+  %80 = tail call i16 asm sideeffect "mov.u16 $0, $1;\0A\09@$4 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $2 + 0 ], $3;", "=c,c,l,l,b"(i16 0, ptr addrspace(1) %67, i64 %79, i1 %75) #4, !dbg !20
+  %81 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !20
+  %82 = tail call i16 asm sideeffect "mov.u16 $0, $1;\0A\09@$4 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $2 + 0 ], $3;", "=c,c,l,l,b"(i16 0, ptr addrspace(1) %68, i64 %81, i1 %76) #4, !dbg !20
+  %83 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !20
+  %84 = tail call i16 asm sideeffect "mov.u16 $0, $1;\0A\09@$4 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $2 + 0 ], $3;", "=c,c,l,l,b"(i16 0, ptr addrspace(1) %69, i64 %83, i1 %77) #4, !dbg !20
+  %85 = insertelement <4 x i16> poison, i16 %78, i64 0, !dbg !20
+  %86 = insertelement <4 x i16> %85, i16 %80, i64 1, !dbg !20
+  %87 = insertelement <4 x i16> %86, i16 %82, i64 2, !dbg !20
+  %88 = insertelement <4 x i16> %87, i16 %84, i64 3, !dbg !20
+  %89 = bitcast <4 x i16> %88 to <4 x bfloat>, !dbg !20
+  %90 = fpext <4 x bfloat> %89 to <4 x float>, !dbg !31
+  %91 = getelementptr bfloat, ptr addrspace(1) %1, i64 %62, !dbg !32
+  %92 = getelementptr bfloat, ptr addrspace(1) %1, i64 %63, !dbg !32
+  %93 = getelementptr bfloat, ptr addrspace(1) %1, i64 %64, !dbg !32
+  %94 = getelementptr bfloat, ptr addrspace(1) %1, i64 %65, !dbg !32
+  %95 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !33
+  %96 = tail call i16 asm sideeffect "mov.u16 $0, $1;\0A\09@$4 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $2 + 0 ], $3;", "=c,c,l,l,b"(i16 0, ptr addrspace(1) %91, i64 %95, i1 %74) #4, !dbg !33
+  %97 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !33
+  %98 = tail call i16 asm sideeffect "mov.u16 $0, $1;\0A\09@$4 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $2 + 0 ], $3;", "=c,c,l,l,b"(i16 0, ptr addrspace(1) %92, i64 %97, i1 %75) #4, !dbg !33
+  %99 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !33
+  %100 = tail call i16 asm sideeffect "mov.u16 $0, $1;\0A\09@$4 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $2 + 0 ], $3;", "=c,c,l,l,b"(i16 0, ptr addrspace(1) %93, i64 %99, i1 %76) #4, !dbg !33
+  %101 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !33
+  %102 = tail call i16 asm sideeffect "mov.u16 $0, $1;\0A\09@$4 ld.global.L1::evict_last.L2::cache_hint.b16 { $0 }, [ $2 + 0 ], $3;", "=c,c,l,l,b"(i16 0, ptr addrspace(1) %94, i64 %101, i1 %77) #4, !dbg !33
+  %103 = insertelement <4 x i16> poison, i16 %96, i64 0, !dbg !33
+  %104 = insertelement <4 x i16> %103, i16 %98, i64 1, !dbg !33
+  %105 = insertelement <4 x i16> %104, i16 %100, i64 2, !dbg !33
+  %106 = insertelement <4 x i16> %105, i16 %102, i64 3, !dbg !33
+  %107 = bitcast <4 x i16> %106 to <4 x bfloat>, !dbg !33
+  %108 = fpext <4 x bfloat> %107 to <4 x float>, !dbg !34
+  %109 = getelementptr float, ptr addrspace(1) %2, i64 %51, !dbg !35
+  %110 = getelementptr float, ptr addrspace(1) %2, i64 %53, !dbg !35
+  %111 = getelementptr float, ptr addrspace(1) %2, i64 %55, !dbg !35
+  %112 = getelementptr float, ptr addrspace(1) %2, i64 %57, !dbg !35
+  %113 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !36
+  %114 = tail call i32 asm sideeffect "mov.u32 $0, $1;\0A\09@$4 ld.global.L1::evict_last.L2::cache_hint.b32 { $0 }, [ $2 + 0 ], $3;", "=r,r,l,l,b"(i32 0, ptr addrspace(1) %109, i64 %113, i1 %74) #4, !dbg !36
+  %115 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !36
+  %116 = tail call i32 asm sideeffect "mov.u32 $0, $1;\0A\09@$4 ld.global.L1::evict_last.L2::cache_hint.b32 { $0 }, [ $2 + 0 ], $3;", "=r,r,l,l,b"(i32 0, ptr addrspace(1) %110, i64 %115, i1 %75) #4, !dbg !36
+  %117 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !36
+  %118 = tail call i32 asm sideeffect "mov.u32 $0, $1;\0A\09@$4 ld.global.L1::evict_last.L2::cache_hint.b32 { $0 }, [ $2 + 0 ], $3;", "=r,r,l,l,b"(i32 0, ptr addrspace(1) %111, i64 %117, i1 %76) #4, !dbg !36
+  %119 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09createpolicy.fractional.L2::evict_last.b64 $0, 1.0;", "=l"() #4, !dbg !36
+  %120 = tail call i32 asm sideeffect "mov.u32 $0, $1;\0A\09@$4 ld.global.L1::evict_last.L2::cache_hint.b32 { $0 }, [ $2 + 0 ], $3;", "=r,r,l,l,b"(i32 0, ptr addrspace(1) %112, i64 %119, i1 %77) #4, !dbg !36
+  %121 = insertelement <4 x i32> poison, i32 %114, i64 0, !dbg !36
+  %122 = insertelement <4 x i32> %121, i32 %116, i64 1, !dbg !36
+  %123 = insertelement <4 x i32> %122, i32 %118, i64 2, !dbg !36
+  %124 = insertelement <4 x i32> %123, i32 %120, i64 3, !dbg !36
+  %125 = bitcast <4 x i32> %124 to <4 x float>, !dbg !36
+  %126 = fmul <4 x float> %108, %125, !dbg !37
+  %127 = fmul <4 x float> %126, %90, !dbg !38
+  %128 = select <4 x i1> %49, <4 x float> %127, <4 x float> zeroinitializer, !dbg !39
+  %129 = fadd <4 x float> %36, %128, !dbg !40
+  %130 = and <4 x i1> %34, %46, !dbg !41
+  %131 = select <4 x i1> %130, <4 x float> %129, <4 x float> %36, !dbg !42
+  %132 = add i32 %35, 8, !dbg !19
+  %133 = icmp slt i32 %132, %8, !dbg !19
+  br i1 %133, label %.lr.ph, label %._crit_edge.loopexit, !dbg !19
+
+._crit_edge.loopexit:                             ; preds = %.lr.ph
+  %shift = shufflevector <4 x float> %131, <4 x float> poison, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>, !dbg !43
+  %foldExtExtBinop14 = fadd <4 x float> %131, %shift, !dbg !43
+  %shift16 = shufflevector <4 x float> %131, <4 x float> poison, <4 x i32> <i32 2, i32 poison, i32 poison, i32 poison>, !dbg !43
+  %foldExtExtBinop17 = fadd <4 x float> %shift16, %foldExtExtBinop14, !dbg !43
+  %shift19 = shufflevector <4 x float> %131, <4 x float> poison, <4 x i32> <i32 3, i32 poison, i32 poison, i32 poison>, !dbg !43
+  %foldExtExtBinop20 = fadd <4 x float> %shift19, %foldExtExtBinop17, !dbg !43
+  %134 = extractelement <4 x float> %foldExtExtBinop20, i64 0, !dbg !43
+  %135 = bitcast float %134 to <1 x i32>, !dbg !47
+  br label %._crit_edge, !dbg !43
+
+._crit_edge:                                      ; preds = %._crit_edge.loopexit, %11
+  %136 = phi <1 x i32> [ zeroinitializer, %11 ], [ %135, %._crit_edge.loopexit ], !dbg !43
+  %.idx = shl nuw nsw i32 %15, 3, !dbg !47
+  %137 = getelementptr i8, ptr addrspace(3) @global_smem, i32 %.idx, !dbg !47
+  %138 = getelementptr float, ptr addrspace(3) %137, i32 %.lobit, !dbg !47
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %138, <1 x i32> %136, i1 true) #4, !dbg !47
+  tail call void @llvm.nvvm.barrier.cta.sync.aligned.all(i32 0), !dbg !47
+  %139 = icmp samesign ult i32 %14, 128, !dbg !47
+  %140 = getelementptr float, ptr addrspace(3) @global_smem, i32 %14, !dbg !47
+  %141 = tail call i32 asm sideeffect "@$2 ld.shared.b32 $0, [ $1 + 0 ];", "=r,r,b"(ptr addrspace(3) %140, i1 %139) #4, !dbg !47
+  %142 = bitcast i32 %141 to float, !dbg !47
+  %143 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %141, i32 1, i32 31), !dbg !47
+  %144 = bitcast i32 %143 to float, !dbg !47
+  %145 = fadd float %142, %144, !dbg !43
+  %146 = and i32 %14, 897, !dbg !47
+  %147 = icmp eq i32 %146, 0, !dbg !47
+  %148 = bitcast float %145 to <1 x i32>, !dbg !47
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %140, <1 x i32> %148, i1 %147) #4, !dbg !47
+  tail call void @llvm.nvvm.barrier.cta.sync.aligned.all(i32 0), !dbg !47
+  %149 = load i32, ptr addrspace(3) %137, align 8, !dbg !47
+  %150 = getelementptr float, ptr addrspace(1) %3, i64 %19, !dbg !48
+  %151 = and i32 %14, 64, !dbg !49
+  %152 = icmp eq i32 %151, 0, !dbg !49
+  %153 = and i1 %152, %17, !dbg !49
+  tail call void asm sideeffect "@$2 st.global.b32 [ $1 + 0 ], { $0 };", "r,l,b"(i32 %149, ptr addrspace(1) %150, i1 %153) #4, !dbg !49
+  ret void, !dbg !50
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef range(i32 0, 2147483647) i32 @llvm.nvvm.read.ptx.sreg.ctaid.x() #1
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef range(i32 0, 1024) i32 @llvm.nvvm.read.ptx.sreg.tid.x() #1
+
+; Function Attrs: convergent nocallback nounwind
+declare void @llvm.nvvm.barrier.cta.sync.aligned.all(i32) #2
+
+; Function Attrs: convergent nocallback nounwind memory(inaccessiblemem: readwrite)
+declare i32 @llvm.nvvm.shfl.sync.bfly.i32(i32, i32, i32, i32) #3
+
+attributes #0 = { nounwind "nvvm.reqntid"="128" }
+attributes #1 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #2 = { convergent nocallback nounwind }
+attributes #3 = { convergent nocallback nounwind memory(inaccessiblemem: readwrite) }
+attributes #4 = { nounwind }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!2, !3}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C, file: !1, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: LineTablesOnly)
+!1 = !DIFile(filename: "c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py", directory: "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k")
+!2 = !{i32 2, !"Debug Info Version", i32 3}
+!3 = !{i32 4, !"nvvm-reflect-ftz", i32 1}
+!4 = distinct !DISubprogram(name: "triton_red_fused__to_copy_mul_sum_0", linkageName: "triton_red_fused__to_copy_mul_sum_0", scope: !1, file: !1, line: 18, type: !5, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0)
+!5 = !DISubroutineType(cc: DW_CC_normal, types: !6)
+!6 = !{}
+!7 = !DILocation(line: 21, column: 28, scope: !4)
+!8 = !DILocation(line: 21, column: 33, scope: !4)
+!9 = !DILocation(line: 22, column: 44, scope: !4)
+!10 = !DILocation(line: 22, column: 23, scope: !4)
+!11 = !DILocation(line: 23, column: 21, scope: !4)
+!12 = !DILocation(line: 24, column: 37, scope: !4)
+!13 = !DILocation(line: 26, column: 19, scope: !4)
+!14 = !DILocation(line: 27, column: 19, scope: !4)
+!15 = !DILocation(line: 36, column: 36, scope: !4)
+!16 = !DILocation(line: 36, column: 32, scope: !4)
+!17 = !DILocation(line: 36, column: 44, scope: !4)
+!18 = !DILocation(line: 36, column: 26, scope: !4)
+!19 = !DILocation(line: 30, column: 40, scope: !4)
+!20 = !DILocation(line: 39, column: 96, scope: !4)
+!21 = !DILocation(line: 31, column: 31, scope: !4)
+!22 = !DILocation(line: 32, column: 29, scope: !4)
+!23 = !DILocation(line: 36, column: 22, scope: !4)
+!24 = !DILocation(line: 38, column: 22, scope: !4)
+!25 = !DILocation(line: 39, column: 83, scope: !4)
+!26 = !DILocation(line: 39, column: 45, scope: !4)
+!27 = !DILocation(line: 39, column: 39, scope: !4)
+!28 = !DILocation(line: 39, column: 34, scope: !4)
+!29 = !DILocation(line: 39, column: 106, scope: !4)
+!30 = !DILocation(line: 39, column: 113, scope: !4)
+!31 = !DILocation(line: 39, column: 164, scope: !4)
+!32 = !DILocation(line: 40, column: 34, scope: !4)
+!33 = !DILocation(line: 40, column: 96, scope: !4)
+!34 = !DILocation(line: 40, column: 164, scope: !4)
+!35 = !DILocation(line: 42, column: 35, scope: !4)
+!36 = !DILocation(line: 42, column: 85, scope: !4)
+!37 = !DILocation(line: 43, column: 22, scope: !4)
+!38 = !DILocation(line: 45, column: 22, scope: !4)
+!39 = !DILocation(line: 47, column: 37, scope: !4)
+!40 = !DILocation(line: 49, column: 25, scope: !4)
+!41 = !DILocation(line: 50, column: 36, scope: !4)
+!42 = !DILocation(line: 50, column: 50, scope: !4)
+!43 = !DILocation(line: 261, column: 15, scope: !44, inlinedAt: !46)
+!44 = distinct !DILexicalBlockFile(scope: !4, file: !45, discriminator: 0)
+!45 = !DIFile(filename: "standard.py", directory: "/workspace/specforge/lib/python3.11/site-packages/triton/language")
+!46 = !DILocation(line: 51, column: 27, scope: !4)
+!47 = !DILocation(line: 291, column: 36, scope: !44, inlinedAt: !46)
+!48 = !DILocation(line: 52, column: 25, scope: !4)
+!49 = !DILocation(line: 52, column: 37, scope: !4)
+!50 = !DILocation(line: 52, column: 4, scope: !4)

SpecForge-ext/cache/compiled_kernels/triton/2/5KYA3IXELFPSJGJX4ZJXZEGZVFALDHEANQ7YQX554R55QVAC6F5A/triton_red_fused__to_copy_mul_sum_0.ptx

@@ -0,0 +1,688 @@
+//
+// Generated by LLVM NVPTX Back-End
+//
+
+.version 8.7
+.target sm_90a
+.address_size 64
+
+	// .globl	triton_red_fused__to_copy_mul_sum_0 // -- Begin function triton_red_fused__to_copy_mul_sum_0
+.extern .shared .align 16 .b8 global_smem[];
+                                        // @triton_red_fused__to_copy_mul_sum_0
+.visible .entry triton_red_fused__to_copy_mul_sum_0(
+	.param .u64 .ptr .global .align 1 triton_red_fused__to_copy_mul_sum_0_param_0,
+	.param .u64 .ptr .global .align 1 triton_red_fused__to_copy_mul_sum_0_param_1,
+	.param .u64 .ptr .global .align 1 triton_red_fused__to_copy_mul_sum_0_param_2,
+	.param .u64 .ptr .global .align 1 triton_red_fused__to_copy_mul_sum_0_param_3,
+	.param .u64 triton_red_fused__to_copy_mul_sum_0_param_4,
+	.param .u64 triton_red_fused__to_copy_mul_sum_0_param_5,
+	.param .u64 triton_red_fused__to_copy_mul_sum_0_param_6,
+	.param .u32 triton_red_fused__to_copy_mul_sum_0_param_7,
+	.param .u32 triton_red_fused__to_copy_mul_sum_0_param_8,
+	.param .u64 .ptr .global .align 1 triton_red_fused__to_copy_mul_sum_0_param_9,
+	.param .u64 .ptr .global .align 1 triton_red_fused__to_copy_mul_sum_0_param_10
+)
+.reqntid 128
+{
+	.reg .pred 	%p<43>;
+	.reg .b16 	%rs<25>;
+	.reg .b32 	%r<119>;
+	.reg .b64 	%rd<137>;
+	.loc	1 18 0                          // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:18:0
+$L__func_begin0:
+	.loc	1 18 0                          // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:18:0
+
+// %bb.0:
+	ld.param.b32 	%r17, [triton_red_fused__to_copy_mul_sum_0_param_8];
+	ld.param.b64 	%rd46, [triton_red_fused__to_copy_mul_sum_0_param_4];
+$L__tmp0:
+	.loc	1 21 28                         // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:21:28
+	mov.u32 	%r18, %ctaid.x;
+	.loc	1 21 33                         // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:21:33
+	shl.b32 	%r19, %r18, 6;
+	.loc	1 22 44                         // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:22:44
+	mov.u32 	%r1, %tid.x;
+	and.b32 	%r2, %r1, 63;
+	.loc	1 22 23                         // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:22:23
+	or.b32 	%r20, %r19, %r2;
+	.loc	1 26 19                         // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:26:19
+	cvt.s64.s32 	%rd1, %r20;
+	or.b64 	%rd50, %rd1, %rd46;
+	and.b64 	%rd51, %rd50, -4294967296;
+	setp.ne.b64 	%p5, %rd51, 0;
+	cvt.u32.u64 	%r116, %rd1;
+	@%p5 bra 	$L__BB0_2;
+	bra.uni 	$L__BB0_1;
+$L__BB0_2:
+	div.s64 	%rd130, %rd1, %rd46;
+	bra.uni 	$L__BB0_3;
+$L__BB0_1:
+	cvt.u32.u64 	%r21, %rd46;
+	div.u32 	%r23, %r116, %r21;
+	cvt.u64.u32 	%rd130, %r23;
+$L__BB0_3:
+	.loc	1 0 19                          // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:0:19
+	ld.param.b32 	%r16, [triton_red_fused__to_copy_mul_sum_0_param_7];
+	ld.param.b64 	%rd45, [triton_red_fused__to_copy_mul_sum_0_param_3];
+	bfe.u32 	%r3, %r1, 6, 1;
+	.loc	1 30 40                         // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:30:40
+	setp.lt.s32 	%p6, %r17, 1;
+	mov.b32 	%r118, 0;
+	@%p6 bra 	$L__BB0_19;
+// %bb.4:                               // %.lr.ph.preheader
+	.loc	1 0 40                          // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:0:40
+	ld.param.b64 	%rd48, [triton_red_fused__to_copy_mul_sum_0_param_6];
+	ld.param.b64 	%rd47, [triton_red_fused__to_copy_mul_sum_0_param_5];
+	ld.param.b64 	%rd44, [triton_red_fused__to_copy_mul_sum_0_param_2];
+	ld.param.b64 	%rd43, [triton_red_fused__to_copy_mul_sum_0_param_1];
+	ld.param.b64 	%rd42, [triton_red_fused__to_copy_mul_sum_0_param_0];
+	mul.lo.s64 	%rd52, %rd130, %rd46;
+	sub.s64 	%rd6, %rd1, %rd52;
+	mul.lo.s64 	%rd7, %rd48, %rd47;
+	add.s64 	%rd53, %rd7, 31;
+	shr.s64 	%rd54, %rd53, 63;
+	shr.u64 	%rd55, %rd54, 59;
+	add.s64 	%rd56, %rd53, %rd55;
+	shr.s64 	%rd57, %rd56, 5;
+	mul.lo.s64 	%rd8, %rd130, %rd57;
+	.loc	1 23 21                         // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:23:21
+	setp.lt.s32 	%p1, %r116, %r16;
+	mov.b32 	%r27, 0f00000000;
+	mov.b64 	%rd131, {%r27, %r27};
+	mov.b32 	%r117, 0;
+	mov.b64 	%rd132, %rd131;
+	bra.uni 	$L__BB0_5;
+$L__BB0_16:                             //   in Loop: Header=BB0_5 Depth=1
+	.loc	1 39 83                         // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:39:83
+	rem.s64 	%rd136, %rd23, %rd7;
+$L__BB0_17:                             //   in Loop: Header=BB0_5 Depth=1
+	.loc	1 38 22                         // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:38:22
+	setp.lt.s64 	%p23, %rd20, %rd7;
+	setp.lt.s64 	%p24, %rd21, %rd7;
+	setp.lt.s64 	%p25, %rd22, %rd7;
+	setp.lt.s64 	%p26, %rd23, %rd7;
+	.loc	1 32 29                         // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:32:29
+	setp.lt.s32 	%p27, %r9, %r17;
+	setp.lt.s32 	%p28, %r10, %r17;
+	setp.lt.s32 	%p29, %r11, %r17;
+	setp.lt.s32 	%p30, %r12, %r17;
+	.loc	1 39 39                         // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:39:39
+	mad.lo.s64 	%rd108, %rd133, %rd46, %rd6;
+	mad.lo.s64 	%rd109, %rd134, %rd46, %rd6;
+	mad.lo.s64 	%rd110, %rd135, %rd46, %rd6;
+	mad.lo.s64 	%rd111, %rd136, %rd46, %rd6;
+	.loc	1 39 34                         // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:39:34
+	shl.b64 	%rd112, %rd108, 1;
+	add.s64 	%rd73, %rd42, %rd112;
+	shl.b64 	%rd113, %rd109, 1;
+	add.s64 	%rd76, %rd42, %rd113;
+	shl.b64 	%rd114, %rd110, 1;
+	add.s64 	%rd79, %rd42, %rd114;
+	shl.b64 	%rd115, %rd111, 1;
+	add.s64 	%rd82, %rd42, %rd115;
+	.loc	1 39 106                        // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:39:106
+	and.pred 	%p32, %p30, %p26;
+	and.pred 	%p33, %p29, %p25;
+	and.pred 	%p34, %p28, %p24;
+	and.pred 	%p35, %p27, %p23;
+	.loc	1 39 113                        // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:39:113
+	and.pred 	%p11, %p1, %p35;
+	and.pred 	%p12, %p1, %p34;
+	and.pred 	%p13, %p1, %p33;
+	and.pred 	%p14, %p1, %p32;
+	mov.b16 	%rs2, 0;
+	.loc	1 39 96                         // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:39:96
+	// begin inline asm
+	mov.u16 %rs1, %rs2;
+	@%p11 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs1 }, [ %rd73 + 0 ], %rd60;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd75, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd75, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs3, %rs2;
+	@%p12 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs3 }, [ %rd76 + 0 ], %rd75;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd78, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd78, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs5, %rs2;
+	@%p13 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs5 }, [ %rd79 + 0 ], %rd78;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd81, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd81, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs7, %rs2;
+	@%p14 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs7 }, [ %rd82 + 0 ], %rd81;
+	// end inline asm
+	mov.b32 	%r49, {%rs5, %rs7};
+	mov.b32 	%r50, {%rs1, %rs3};
+	.loc	1 39 164                        // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:39:164
+	mov.b32 	{%rs17, %rs18}, %r50;
+	cvt.f32.bf16 	%r51, %rs18;
+	cvt.f32.bf16 	%r52, %rs17;
+	mov.b32 	{%rs19, %rs20}, %r49;
+	cvt.f32.bf16 	%r53, %rs20;
+	cvt.f32.bf16 	%r54, %rs19;
+	.loc	1 40 34                         // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:40:34
+	add.s64 	%rd85, %rd43, %rd112;
+	add.s64 	%rd88, %rd43, %rd113;
+	add.s64 	%rd91, %rd43, %rd114;
+	add.s64 	%rd94, %rd43, %rd115;
+	.loc	1 40 96                         // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:40:96
+	// begin inline asm
+	mov.u64 %rd84, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd84, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs9, %rs2;
+	@%p11 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs9 }, [ %rd85 + 0 ], %rd84;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd87, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd87, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs11, %rs2;
+	@%p12 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs11 }, [ %rd88 + 0 ], %rd87;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd90, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd90, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs13, %rs2;
+	@%p13 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs13 }, [ %rd91 + 0 ], %rd90;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd93, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd93, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs15, %rs2;
+	@%p14 ld.global.L1::evict_last.L2::cache_hint.b16 { %rs15 }, [ %rd94 + 0 ], %rd93;
+	// end inline asm
+	mov.b32 	%r55, {%rs9, %rs11};
+	mov.b32 	%r56, {%rs13, %rs15};
+	.loc	1 40 164                        // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:40:164
+	mov.b32 	{%rs21, %rs22}, %r56;
+	cvt.f32.bf16 	%r57, %rs21;
+	cvt.f32.bf16 	%r58, %rs22;
+	mov.b32 	{%rs23, %rs24}, %r55;
+	cvt.f32.bf16 	%r59, %rs23;
+	cvt.f32.bf16 	%r60, %rs24;
+	.loc	1 42 35                         // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:42:35
+	shl.b64 	%rd116, %rd133, 2;
+	add.s64 	%rd97, %rd44, %rd116;
+	shl.b64 	%rd117, %rd134, 2;
+	add.s64 	%rd100, %rd44, %rd117;
+	shl.b64 	%rd118, %rd135, 2;
+	add.s64 	%rd103, %rd44, %rd118;
+	shl.b64 	%rd119, %rd136, 2;
+	add.s64 	%rd106, %rd44, %rd119;
+	.loc	1 42 85                         // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:42:85
+	// begin inline asm
+	mov.u64 %rd96, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd96, 1.0;
+	// end inline asm
+	mov.b32 	%r41, 0;
+	// begin inline asm
+	mov.u32 %r40, %r41;
+	@%p11 ld.global.L1::evict_last.L2::cache_hint.b32 { %r40 }, [ %rd97 + 0 ], %rd96;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd99, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd99, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u32 %r42, %r41;
+	@%p12 ld.global.L1::evict_last.L2::cache_hint.b32 { %r42 }, [ %rd100 + 0 ], %rd99;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd102, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd102, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u32 %r44, %r41;
+	@%p13 ld.global.L1::evict_last.L2::cache_hint.b32 { %r44 }, [ %rd103 + 0 ], %rd102;
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd105, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd105, 1.0;
+	// end inline asm
+	// begin inline asm
+	mov.u32 %r46, %r41;
+	@%p14 ld.global.L1::evict_last.L2::cache_hint.b32 { %r46 }, [ %rd106 + 0 ], %rd105;
+	// end inline asm
+	cvt.u64.u32 	%rd120, %r44;
+	cvt.u64.u32 	%rd121, %r46;
+	shl.b64 	%rd122, %rd121, 32;
+	or.b64 	%rd123, %rd120, %rd122;
+	cvt.u64.u32 	%rd124, %r40;
+	cvt.u64.u32 	%rd125, %r42;
+	shl.b64 	%rd126, %rd125, 32;
+	or.b64 	%rd127, %rd124, %rd126;
+	.loc	1 43 22                         // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:43:22
+	mov.b64 	{%r61, %r62}, %rd127;
+	mul.f32 	%r63, %r60, %r62;
+	mul.f32 	%r64, %r59, %r61;
+	mov.b64 	{%r65, %r66}, %rd123;
+	mul.f32 	%r67, %r58, %r66;
+	mul.f32 	%r68, %r57, %r65;
+	.loc	1 45 22                         // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:45:22
+	mul.f32 	%r69, %r68, %r54;
+	mul.f32 	%r70, %r67, %r53;
+	mul.f32 	%r71, %r64, %r52;
+	mul.f32 	%r72, %r63, %r51;
+	.loc	1 47 37                         // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:47:37
+	selp.f32 	%r73, %r72, 0f00000000, %p24;
+	selp.f32 	%r74, %r71, 0f00000000, %p23;
+	selp.f32 	%r75, %r70, 0f00000000, %p26;
+	selp.f32 	%r76, %r69, 0f00000000, %p25;
+	.loc	1 49 25                         // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:49:25
+	mov.b64 	{%r77, %r78}, %rd132;
+	add.f32 	%r79, %r77, %r76;
+	add.f32 	%r80, %r78, %r75;
+	mov.b64 	{%r81, %r82}, %rd131;
+	add.f32 	%r83, %r81, %r74;
+	add.f32 	%r84, %r82, %r73;
+	.loc	1 50 50                         // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:50:50
+	selp.f32 	%r85, %r84, %r82, %p28;
+	selp.f32 	%r86, %r85, %r82, %p1;
+	selp.f32 	%r87, %r83, %r81, %p27;
+	selp.f32 	%r88, %r87, %r81, %p1;
+	mov.b64 	%rd131, {%r88, %r86};
+	selp.f32 	%r89, %r80, %r78, %p30;
+	selp.f32 	%r90, %r89, %r78, %p1;
+	selp.f32 	%r91, %r79, %r77, %p29;
+	selp.f32 	%r92, %r91, %r77, %p1;
+	mov.b64 	%rd132, {%r92, %r90};
+	.loc	1 30 40                         // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:30:40
+	add.s32 	%r117, %r117, 8;
+	setp.lt.s32 	%p36, %r117, %r17;
+	@%p36 bra 	$L__BB0_5;
+	bra.uni 	$L__BB0_18;
+$L__BB0_5:                              // %.lr.ph
+                                        // =>This Inner Loop Header: Depth=1
+	.loc	1 39 96                         // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:39:96
+	// begin inline asm
+	mov.u64 %rd60, 0x0;
+	createpolicy.fractional.L2::evict_last.b64 %rd60, 1.0;
+	// end inline asm
+	.loc	1 31 31                         // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:31:31
+	add.s32 	%r9, %r3, %r117;
+	add.s32 	%r10, %r9, 2;
+	.loc	1 36 22                         // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:36:22
+	cvt.s64.s32 	%rd61, %r9;
+	cvt.s64.s32 	%rd62, %r10;
+	add.s64 	%rd21, %rd8, %rd62;
+	add.s64 	%rd20, %rd8, %rd61;
+	.loc	1 39 83                         // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:39:83
+	or.b64 	%rd65, %rd20, %rd7;
+	and.b64 	%rd66, %rd65, -4294967296;
+	setp.ne.b64 	%p7, %rd66, 0;
+	@%p7 bra 	$L__BB0_7;
+	bra.uni 	$L__BB0_6;
+$L__BB0_7:                              //   in Loop: Header=BB0_5 Depth=1
+	rem.s64 	%rd133, %rd20, %rd7;
+	bra.uni 	$L__BB0_8;
+$L__BB0_6:                              //   in Loop: Header=BB0_5 Depth=1
+	cvt.u32.u64 	%r28, %rd7;
+	cvt.u32.u64 	%r29, %rd20;
+	rem.u32 	%r30, %r29, %r28;
+	cvt.u64.u32 	%rd133, %r30;
+$L__BB0_8:                              //   in Loop: Header=BB0_5 Depth=1
+	.loc	1 0 0                           // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:0
+	add.s32 	%r11, %r9, 4;
+	cvt.s64.s32 	%rd63, %r11;
+	add.s64 	%rd22, %rd8, %rd63;
+	.loc	1 39 83                         // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:39:83
+	or.b64 	%rd67, %rd21, %rd7;
+	and.b64 	%rd68, %rd67, -4294967296;
+	setp.ne.b64 	%p8, %rd68, 0;
+	@%p8 bra 	$L__BB0_10;
+	bra.uni 	$L__BB0_9;
+$L__BB0_10:                             //   in Loop: Header=BB0_5 Depth=1
+	rem.s64 	%rd134, %rd21, %rd7;
+	bra.uni 	$L__BB0_11;
+$L__BB0_9:                              //   in Loop: Header=BB0_5 Depth=1
+	cvt.u32.u64 	%r31, %rd7;
+	cvt.u32.u64 	%r32, %rd21;
+	rem.u32 	%r33, %r32, %r31;
+	cvt.u64.u32 	%rd134, %r33;
+$L__BB0_11:                             //   in Loop: Header=BB0_5 Depth=1
+	.loc	1 0 0                           // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:0
+	add.s32 	%r12, %r9, 6;
+	cvt.s64.s32 	%rd64, %r12;
+	add.s64 	%rd23, %rd8, %rd64;
+	.loc	1 39 83                         // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:39:83
+	or.b64 	%rd69, %rd22, %rd7;
+	and.b64 	%rd70, %rd69, -4294967296;
+	setp.ne.b64 	%p9, %rd70, 0;
+	@%p9 bra 	$L__BB0_13;
+	bra.uni 	$L__BB0_12;
+$L__BB0_13:                             //   in Loop: Header=BB0_5 Depth=1
+	rem.s64 	%rd135, %rd22, %rd7;
+	bra.uni 	$L__BB0_14;
+$L__BB0_12:                             //   in Loop: Header=BB0_5 Depth=1
+	cvt.u32.u64 	%r34, %rd7;
+	cvt.u32.u64 	%r35, %rd22;
+	rem.u32 	%r36, %r35, %r34;
+	cvt.u64.u32 	%rd135, %r36;
+$L__BB0_14:                             //   in Loop: Header=BB0_5 Depth=1
+	or.b64 	%rd71, %rd23, %rd7;
+	and.b64 	%rd72, %rd71, -4294967296;
+	setp.ne.b64 	%p10, %rd72, 0;
+	@%p10 bra 	$L__BB0_16;
+// %bb.15:                              //   in Loop: Header=BB0_5 Depth=1
+	cvt.u32.u64 	%r37, %rd7;
+	cvt.u32.u64 	%r38, %rd23;
+	rem.u32 	%r39, %r38, %r37;
+	cvt.u64.u32 	%rd136, %r39;
+	bra.uni 	$L__BB0_17;
+$L__BB0_18:                             // %._crit_edge.loopexit
+$L__tmp1:
+	.loc	2 261 15                        // standard.py:261:15 @[ c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:51:27 ]
+	mov.b64 	{%r93, %r94}, %rd131;
+	add.f32 	%r95, %r93, %r94;
+	mov.b64 	{%r96, %r97}, %rd132;
+	add.f32 	%r98, %r96, %r95;
+	add.f32 	%r118, %r97, %r98;
+$L__tmp2:
+$L__BB0_19:                             // %._crit_edge
+	.loc	1 23 21                         // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:23:21
+	setp.lt.s32 	%p41, %r116, %r16;
+$L__tmp3:
+	.loc	2 291 36                        // standard.py:291:36 @[ c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:51:27 ]
+	shl.b32 	%r107, %r2, 3;
+	mov.b32 	%r108, global_smem;
+	add.s32 	%r109, %r108, %r107;
+	shl.b32 	%r110, %r3, 2;
+	add.s32 	%r99, %r109, %r110;
+	mov.pred 	%p37, -1;
+	// begin inline asm
+	@%p37 st.shared.b32 [ %r99 + 0 ], %r118;
+	// end inline asm
+	bar.sync 	0;
+	setp.lt.u32 	%p38, %r1, 128;
+	shl.b32 	%r111, %r1, 2;
+	add.s32 	%r102, %r108, %r111;
+	// begin inline asm
+	@%p38 ld.shared.b32 %r101, [ %r102 + 0 ];
+	// end inline asm
+	shfl.sync.bfly.b32 	%r112, %r101, 1, 31, -1;
+	.loc	2 261 15                        // standard.py:261:15 @[ c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:51:27 ]
+	add.f32 	%r104, %r101, %r112;
+	.loc	2 291 36                        // standard.py:291:36 @[ c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:51:27 ]
+	and.b32 	%r113, %r1, 897;
+	setp.eq.b32 	%p39, %r113, 0;
+	// begin inline asm
+	@%p39 st.shared.b32 [ %r102 + 0 ], %r104;
+	// end inline asm
+	bar.sync 	0;
+	ld.shared.b32 	%r105, [%r109];
+$L__tmp4:
+	.loc	1 52 25                         // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:52:25
+	shl.b64 	%rd129, %rd1, 2;
+	add.s64 	%rd128, %rd45, %rd129;
+	.loc	1 52 37                         // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:52:37
+	and.b32 	%r114, %r1, 64;
+	setp.eq.b32 	%p42, %r114, 0;
+	and.pred 	%p40, %p42, %p41;
+	// begin inline asm
+	@%p40 st.global.b32 [ %rd128 + 0 ], { %r105 };
+	// end inline asm
+	.loc	1 52 4                          // c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py:52:4
+	ret;
+$L__tmp5:
+$L__func_end0:
+                                        // -- End function
+}
+	.file	1 "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py"
+	.file	2 "/workspace/specforge/lib/python3.11/site-packages/triton/language/standard.py"
+	.section	.debug_abbrev
+	{
+.b8 1                                   // Abbreviation Code
+.b8 17                                  // DW_TAG_compile_unit
+.b8 1                                   // DW_CHILDREN_yes
+.b8 37                                  // DW_AT_producer
+.b8 8                                   // DW_FORM_string
+.b8 19                                  // DW_AT_language
+.b8 5                                   // DW_FORM_data2
+.b8 3                                   // DW_AT_name
+.b8 8                                   // DW_FORM_string
+.b8 16                                  // DW_AT_stmt_list
+.b8 6                                   // DW_FORM_data4
+.b8 27                                  // DW_AT_comp_dir
+.b8 8                                   // DW_FORM_string
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 2                                   // Abbreviation Code
+.b8 46                                  // DW_TAG_subprogram
+.b8 0                                   // DW_CHILDREN_no
+.b8 3                                   // DW_AT_name
+.b8 8                                   // DW_FORM_string
+.b8 32                                  // DW_AT_inline
+.b8 11                                  // DW_FORM_data1
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 3                                   // Abbreviation Code
+.b8 46                                  // DW_TAG_subprogram
+.b8 1                                   // DW_CHILDREN_yes
+.b8 17                                  // DW_AT_low_pc
+.b8 1                                   // DW_FORM_addr
+.b8 18                                  // DW_AT_high_pc
+.b8 1                                   // DW_FORM_addr
+.b8 49                                  // DW_AT_abstract_origin
+.b8 19                                  // DW_FORM_ref4
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 4                                   // Abbreviation Code
+.b8 29                                  // DW_TAG_inlined_subroutine
+.b8 0                                   // DW_CHILDREN_no
+.b8 49                                  // DW_AT_abstract_origin
+.b8 19                                  // DW_FORM_ref4
+.b8 17                                  // DW_AT_low_pc
+.b8 1                                   // DW_FORM_addr
+.b8 18                                  // DW_AT_high_pc
+.b8 1                                   // DW_FORM_addr
+.b8 88                                  // DW_AT_call_file
+.b8 11                                  // DW_FORM_data1
+.b8 89                                  // DW_AT_call_line
+.b8 11                                  // DW_FORM_data1
+.b8 87                                  // DW_AT_call_column
+.b8 11                                  // DW_FORM_data1
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 0                                   // EOM(3)
+	}
+	.section	.debug_info
+	{
+.b32 220                                // Length of Unit
+.b8 2                                   // DWARF version number
+.b8 0
+.b32 .debug_abbrev                      // Offset Into Abbrev. Section
+.b8 8                                   // Address Size (in bytes)
+.b8 1                                   // Abbrev [1] 0xb:0xd5 DW_TAG_compile_unit
+.b8 116                                 // DW_AT_producer
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 0
+.b8 2                                   // DW_AT_language
+.b8 0
+.b8 99                                  // DW_AT_name
+.b8 50
+.b8 107
+.b8 122
+.b8 53
+.b8 53
+.b8 103
+.b8 114
+.b8 114
+.b8 115
+.b8 104
+.b8 112
+.b8 99
+.b8 51
+.b8 113
+.b8 107
+.b8 118
+.b8 103
+.b8 54
+.b8 106
+.b8 101
+.b8 115
+.b8 98
+.b8 117
+.b8 54
+.b8 51
+.b8 116
+.b8 115
+.b8 53
+.b8 119
+.b8 108
+.b8 104
+.b8 107
+.b8 119
+.b8 116
+.b8 106
+.b8 117
+.b8 107
+.b8 109
+.b8 55
+.b8 122
+.b8 107
+.b8 99
+.b8 118
+.b8 104
+.b8 107
+.b8 105
+.b8 108
+.b8 103
+.b8 110
+.b8 55
+.b8 54
+.b8 46
+.b8 112
+.b8 121
+.b8 0
+.b32 .debug_line                        // DW_AT_stmt_list
+.b8 47                                  // DW_AT_comp_dir
+.b8 119
+.b8 111
+.b8 114
+.b8 107
+.b8 115
+.b8 112
+.b8 97
+.b8 99
+.b8 101
+.b8 47
+.b8 104
+.b8 97
+.b8 110
+.b8 114
+.b8 117
+.b8 105
+.b8 47
+.b8 83
+.b8 112
+.b8 101
+.b8 99
+.b8 70
+.b8 111
+.b8 114
+.b8 103
+.b8 101
+.b8 45
+.b8 101
+.b8 120
+.b8 116
+.b8 47
+.b8 99
+.b8 97
+.b8 99
+.b8 104
+.b8 101
+.b8 47
+.b8 99
+.b8 111
+.b8 109
+.b8 112
+.b8 105
+.b8 108
+.b8 101
+.b8 100
+.b8 95
+.b8 107
+.b8 101
+.b8 114
+.b8 110
+.b8 101
+.b8 108
+.b8 115
+.b8 47
+.b8 50
+.b8 107
+.b8 0
+.b8 2                                   // Abbrev [2] 0x8b:0x26 DW_TAG_subprogram
+.b8 116                                 // DW_AT_name
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 114
+.b8 101
+.b8 100
+.b8 95
+.b8 102
+.b8 117
+.b8 115
+.b8 101
+.b8 100
+.b8 95
+.b8 95
+.b8 116
+.b8 111
+.b8 95
+.b8 99
+.b8 111
+.b8 112
+.b8 121
+.b8 95
+.b8 109
+.b8 117
+.b8 108
+.b8 95
+.b8 115
+.b8 117
+.b8 109
+.b8 95
+.b8 48
+.b8 0
+.b8 1                                   // DW_AT_inline
+.b8 3                                   // Abbrev [3] 0xb1:0x2e DW_TAG_subprogram
+.b64 $L__func_begin0                    // DW_AT_low_pc
+.b64 $L__func_end0                      // DW_AT_high_pc
+.b32 139                                // DW_AT_abstract_origin
+.b8 4                                   // Abbrev [4] 0xc6:0x18 DW_TAG_inlined_subroutine
+.b32 139                                // DW_AT_abstract_origin
+.b64 $L__tmp1                           // DW_AT_low_pc
+.b64 $L__tmp4                           // DW_AT_high_pc
+.b8 1                                   // DW_AT_call_file
+.b8 51                                  // DW_AT_call_line
+.b8 27                                  // DW_AT_call_column
+.b8 0                                   // End Of Children Mark
+.b8 0                                   // End Of Children Mark
+	}
+	.section	.debug_macinfo	{	}

SpecForge-ext/cache/compiled_kernels/triton/2/5KYA3IXELFPSJGJX4ZJXZEGZVFALDHEANQ7YQX554R55QVAC6F5A/triton_red_fused__to_copy_mul_sum_0.source

@@ -0,0 +1,338 @@
+#loc = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":18:0)
+#loc74 = loc("/workspace/specforge/lib/python3.11/site-packages/triton/language/standard.py":285:0)
+#loc76 = loc(unknown)
+#loc79 = loc("/workspace/specforge/lib/python3.11/site-packages/triton/language/standard.py":260:0)
+#loc83 = loc("in_ptr0"(#loc))
+#loc84 = loc("in_ptr1"(#loc))
+#loc85 = loc("in_ptr2"(#loc))
+#loc86 = loc("out_ptr0"(#loc))
+#loc87 = loc("ks0"(#loc))
+#loc88 = loc("ks1"(#loc))
+#loc89 = loc("ks2"(#loc))
+#loc90 = loc("xnumel"(#loc))
+#loc91 = loc("r0_numel"(#loc))
+#loc161 = loc("input"(#loc74))
+#loc162 = loc("a"(#loc79))
+#loc163 = loc("b"(#loc79))
+module {
+  tt.func public @triton_red_fused__to_copy_mul_sum_0(%in_ptr0: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("in_ptr0"(#loc)), %in_ptr1: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("in_ptr1"(#loc)), %in_ptr2: !tt.ptr<f32> {tt.divisibility = 16 : i32} loc("in_ptr2"(#loc)), %out_ptr0: !tt.ptr<f32> {tt.divisibility = 16 : i32} loc("out_ptr0"(#loc)), %ks0: i64 loc("ks0"(#loc)), %ks1: i64 loc("ks1"(#loc)), %ks2: i64 loc("ks2"(#loc)), %xnumel: i32 {tt.divisibility = 16 : i32} loc("xnumel"(#loc)), %r0_numel: i32 loc("r0_numel"(#loc))) attributes {noinline = false} {
+    %xoffset = tt.get_program_id x : i32 loc(#loc92)
+    %xoffset_0 = arith.constant 64 : i32 loc(#loc93)
+    %xoffset_1 = arith.constant 64 : i32 loc(#loc93)
+    %xoffset_2 = arith.muli %xoffset, %xoffset_1 : i32 loc(#loc93)
+    %xindex = tt.make_range {end = 64 : i32, start = 0 : i32} : tensor<64xi32> loc(#loc94)
+    %xindex_3 = tt.expand_dims %xindex {axis = 1 : i32} : tensor<64xi32> -> tensor<64x1xi32> loc(#loc95)
+    %xindex_4 = tt.splat %xoffset_2 : i32 -> tensor<64x1xi32> loc(#loc96)
+    %xindex_5 = arith.addi %xindex_4, %xindex_3 : tensor<64x1xi32> loc(#loc96)
+    %xmask = tt.splat %xnumel : i32 -> tensor<64x1xi32> loc(#loc97)
+    %xmask_6 = arith.cmpi slt, %xindex_5, %xmask : tensor<64x1xi32> loc(#loc97)
+    %r0_base = tt.make_range {end = 8 : i32, start = 0 : i32} : tensor<8xi32> loc(#loc98)
+    %r0_base_7 = tt.expand_dims %r0_base {axis = 0 : i32} : tensor<8xi32> -> tensor<1x8xi32> loc(#loc99)
+    %x1 = arith.extsi %xindex_5 : tensor<64x1xi32> to tensor<64x1xi64> loc(#loc100)
+    %x1_8 = tt.splat %ks0 : i64 -> tensor<64x1xi64> loc(#loc100)
+    %x1_9 = arith.divsi %x1, %x1_8 : tensor<64x1xi64> loc(#loc100)
+    %x0 = arith.extsi %xindex_5 : tensor<64x1xi32> to tensor<64x1xi64> loc(#loc101)
+    %x0_10 = tt.splat %ks0 : i64 -> tensor<64x1xi64> loc(#loc101)
+    %x0_11 = arith.remsi %x0, %x0_10 : tensor<64x1xi64> loc(#loc101)
+    %_tmp13 = arith.constant 0.000000e+00 : f32 loc(#loc102)
+    %_tmp13_12 = arith.constant dense<0.000000e+00> : tensor<64x8xf32> loc(#loc102)
+    %c0_i32 = arith.constant 0 : i32 loc(#loc12)
+    %c8_i32 = arith.constant 8 : i32 loc(#loc12)
+    %0 = arith.bitcast %c0_i32 : i32 to i32 loc(#loc12)
+    %1 = arith.bitcast %r0_numel : i32 to i32 loc(#loc12)
+    %2 = arith.bitcast %c8_i32 : i32 to i32 loc(#loc12)
+    %3 = ub.poison : i32 loc(#loc12)
+    %_tmp13_13 = scf.for %r0_offset = %0 to %1 step %2 iter_args(%_tmp13_15 = %_tmp13_12) -> (tensor<64x8xf32>)  : i32 {
+      %r0_index = tt.splat %r0_offset : i32 -> tensor<1x8xi32> loc(#loc104)
+      %r0_index_16 = arith.addi %r0_index, %r0_base_7 : tensor<1x8xi32> loc(#loc104)
+      %r0_mask = tt.splat %r0_numel : i32 -> tensor<1x8xi32> loc(#loc105)
+      %r0_mask_17 = arith.cmpi slt, %r0_index_16, %r0_mask : tensor<1x8xi32> loc(#loc105)
+      %tmp0 = arith.muli %ks1, %ks2 : i64 loc(#loc106)
+      %tmp0_18 = arith.constant 31 : i32 loc(#loc107)
+      %tmp0_19 = arith.constant 31 : i64 loc(#loc107)
+      %tmp0_20 = arith.addi %tmp0_19, %tmp0 : i64 loc(#loc107)
+      %tmp0_21 = arith.constant 32 : i32 loc(#loc108)
+      %tmp0_22 = arith.constant 32 : i64 loc(#loc108)
+      %tmp0_23 = arith.divsi %tmp0_20, %tmp0_22 : i64 loc(#loc108)
+      %tmp0_24 = tt.splat %tmp0_23 : i64 -> tensor<64x1xi64> loc(#loc109)
+      %tmp0_25 = arith.muli %x1_9, %tmp0_24 : tensor<64x1xi64> loc(#loc109)
+      %tmp0_26 = arith.extsi %r0_index_16 : tensor<1x8xi32> to tensor<1x8xi64> loc(#loc110)
+      %tmp0_27 = tt.broadcast %tmp0_26 : tensor<1x8xi64> -> tensor<64x8xi64> loc(#loc110)
+      %tmp0_28 = tt.broadcast %tmp0_25 : tensor<64x1xi64> -> tensor<64x8xi64> loc(#loc110)
+      %tmp0_29 = arith.addi %tmp0_27, %tmp0_28 : tensor<64x8xi64> loc(#loc110)
+      %tmp1 = arith.muli %ks1, %ks2 : i64 loc(#loc111)
+      %tmp2 = tt.splat %tmp1 : i64 -> tensor<64x8xi64> loc(#loc112)
+      %tmp2_30 = arith.cmpi slt, %tmp0_29, %tmp2 : tensor<64x8xi64> loc(#loc112)
+      %tmp3 = arith.muli %ks1, %ks2 : i64 loc(#loc113)
+      %tmp3_31 = arith.constant 31 : i32 loc(#loc114)
+      %tmp3_32 = arith.constant 31 : i64 loc(#loc114)
+      %tmp3_33 = arith.addi %tmp3_32, %tmp3 : i64 loc(#loc114)
+      %tmp3_34 = arith.constant 32 : i32 loc(#loc115)
+      %tmp3_35 = arith.constant 32 : i64 loc(#loc115)
+      %tmp3_36 = arith.divsi %tmp3_33, %tmp3_35 : i64 loc(#loc115)
+      %tmp3_37 = tt.splat %tmp3_36 : i64 -> tensor<64x1xi64> loc(#loc116)
+      %tmp3_38 = arith.muli %x1_9, %tmp3_37 : tensor<64x1xi64> loc(#loc116)
+      %tmp3_39 = arith.extsi %r0_index_16 : tensor<1x8xi32> to tensor<1x8xi64> loc(#loc117)
+      %tmp3_40 = tt.broadcast %tmp3_39 : tensor<1x8xi64> -> tensor<64x8xi64> loc(#loc117)
+      %tmp3_41 = tt.broadcast %tmp3_38 : tensor<64x1xi64> -> tensor<64x8xi64> loc(#loc117)
+      %tmp3_42 = arith.addi %tmp3_40, %tmp3_41 : tensor<64x8xi64> loc(#loc117)
+      %tmp3_43 = arith.muli %ks1, %ks2 : i64 loc(#loc118)
+      %tmp3_44 = tt.splat %tmp3_43 : i64 -> tensor<64x8xi64> loc(#loc119)
+      %tmp3_45 = arith.remsi %tmp3_42, %tmp3_44 : tensor<64x8xi64> loc(#loc119)
+      %tmp3_46 = tt.splat %ks0 : i64 -> tensor<64x8xi64> loc(#loc120)
+      %tmp3_47 = arith.muli %tmp3_46, %tmp3_45 : tensor<64x8xi64> loc(#loc120)
+      %tmp3_48 = tt.broadcast %x0_11 : tensor<64x1xi64> -> tensor<64x8xi64> loc(#loc121)
+      %tmp3_49 = arith.addi %tmp3_48, %tmp3_47 : tensor<64x8xi64> loc(#loc121)
+      %tmp3_50 = tt.splat %in_ptr0 : !tt.ptr<bf16> -> tensor<64x8x!tt.ptr<bf16>> loc(#loc122)
+      %tmp3_51 = tt.addptr %tmp3_50, %tmp3_49 : tensor<64x8x!tt.ptr<bf16>>, tensor<64x8xi64> loc(#loc122)
+      %tmp3_52 = tt.broadcast %r0_mask_17 : tensor<1x8xi1> -> tensor<64x8xi1> loc(#loc123)
+      %tmp3_53 = arith.andi %tmp3_52, %tmp2_30 : tensor<64x8xi1> loc(#loc123)
+      %tmp3_54 = tt.broadcast %xmask_6 : tensor<64x1xi1> -> tensor<64x8xi1> loc(#loc124)
+      %tmp3_55 = arith.andi %tmp3_53, %tmp3_54 : tensor<64x8xi1> loc(#loc124)
+      %tmp3_56 = arith.constant 0.000000e+00 : f32 loc(#loc125)
+      %tmp3_57 = arith.constant dense<0.000000e+00> : tensor<64x8xf32> loc(#loc125)
+      %tmp3_58 = arith.truncf %tmp3_57 : tensor<64x8xf32> to tensor<64x8xbf16> loc(#loc125)
+      %tmp3_59 = tt.load %tmp3_51, %tmp3_55, %tmp3_58 evictionPolicy = evict_last : tensor<64x8x!tt.ptr<bf16>> loc(#loc125)
+      %tmp3_60 = arith.extf %tmp3_59 : tensor<64x8xbf16> to tensor<64x8xf32> loc(#loc126)
+      %tmp4 = arith.muli %ks1, %ks2 : i64 loc(#loc127)
+      %tmp4_61 = arith.constant 31 : i32 loc(#loc128)
+      %tmp4_62 = arith.constant 31 : i64 loc(#loc128)
+      %tmp4_63 = arith.addi %tmp4_62, %tmp4 : i64 loc(#loc128)
+      %tmp4_64 = arith.constant 32 : i32 loc(#loc129)
+      %tmp4_65 = arith.constant 32 : i64 loc(#loc129)
+      %tmp4_66 = arith.divsi %tmp4_63, %tmp4_65 : i64 loc(#loc129)
+      %tmp4_67 = tt.splat %tmp4_66 : i64 -> tensor<64x1xi64> loc(#loc130)
+      %tmp4_68 = arith.muli %x1_9, %tmp4_67 : tensor<64x1xi64> loc(#loc130)
+      %tmp4_69 = arith.extsi %r0_index_16 : tensor<1x8xi32> to tensor<1x8xi64> loc(#loc131)
+      %tmp4_70 = tt.broadcast %tmp4_69 : tensor<1x8xi64> -> tensor<64x8xi64> loc(#loc131)
+      %tmp4_71 = tt.broadcast %tmp4_68 : tensor<64x1xi64> -> tensor<64x8xi64> loc(#loc131)
+      %tmp4_72 = arith.addi %tmp4_70, %tmp4_71 : tensor<64x8xi64> loc(#loc131)
+      %tmp4_73 = arith.muli %ks1, %ks2 : i64 loc(#loc132)
+      %tmp4_74 = tt.splat %tmp4_73 : i64 -> tensor<64x8xi64> loc(#loc133)
+      %tmp4_75 = arith.remsi %tmp4_72, %tmp4_74 : tensor<64x8xi64> loc(#loc133)
+      %tmp4_76 = tt.splat %ks0 : i64 -> tensor<64x8xi64> loc(#loc134)
+      %tmp4_77 = arith.muli %tmp4_76, %tmp4_75 : tensor<64x8xi64> loc(#loc134)
+      %tmp4_78 = tt.broadcast %x0_11 : tensor<64x1xi64> -> tensor<64x8xi64> loc(#loc135)
+      %tmp4_79 = arith.addi %tmp4_78, %tmp4_77 : tensor<64x8xi64> loc(#loc135)
+      %tmp4_80 = tt.splat %in_ptr1 : !tt.ptr<bf16> -> tensor<64x8x!tt.ptr<bf16>> loc(#loc136)
+      %tmp4_81 = tt.addptr %tmp4_80, %tmp4_79 : tensor<64x8x!tt.ptr<bf16>>, tensor<64x8xi64> loc(#loc136)
+      %tmp4_82 = tt.broadcast %r0_mask_17 : tensor<1x8xi1> -> tensor<64x8xi1> loc(#loc137)
+      %tmp4_83 = arith.andi %tmp4_82, %tmp2_30 : tensor<64x8xi1> loc(#loc137)
+      %tmp4_84 = tt.broadcast %xmask_6 : tensor<64x1xi1> -> tensor<64x8xi1> loc(#loc138)
+      %tmp4_85 = arith.andi %tmp4_83, %tmp4_84 : tensor<64x8xi1> loc(#loc138)
+      %tmp4_86 = arith.constant 0.000000e+00 : f32 loc(#loc139)
+      %tmp4_87 = arith.constant dense<0.000000e+00> : tensor<64x8xf32> loc(#loc139)
+      %tmp4_88 = arith.truncf %tmp4_87 : tensor<64x8xf32> to tensor<64x8xbf16> loc(#loc139)
+      %tmp4_89 = tt.load %tmp4_81, %tmp4_85, %tmp4_88 evictionPolicy = evict_last : tensor<64x8x!tt.ptr<bf16>> loc(#loc139)
+      %tmp4_90 = arith.extf %tmp4_89 : tensor<64x8xbf16> to tensor<64x8xf32> loc(#loc140)
+      %tmp6 = arith.muli %ks1, %ks2 : i64 loc(#loc141)
+      %tmp6_91 = arith.constant 31 : i32 loc(#loc142)
+      %tmp6_92 = arith.constant 31 : i64 loc(#loc142)
+      %tmp6_93 = arith.addi %tmp6_92, %tmp6 : i64 loc(#loc142)
+      %tmp6_94 = arith.constant 32 : i32 loc(#loc143)
+      %tmp6_95 = arith.constant 32 : i64 loc(#loc143)
+      %tmp6_96 = arith.divsi %tmp6_93, %tmp6_95 : i64 loc(#loc143)
+      %tmp6_97 = tt.splat %tmp6_96 : i64 -> tensor<64x1xi64> loc(#loc144)
+      %tmp6_98 = arith.muli %x1_9, %tmp6_97 : tensor<64x1xi64> loc(#loc144)
+      %tmp6_99 = arith.extsi %r0_index_16 : tensor<1x8xi32> to tensor<1x8xi64> loc(#loc145)
+      %tmp6_100 = tt.broadcast %tmp6_99 : tensor<1x8xi64> -> tensor<64x8xi64> loc(#loc145)
+      %tmp6_101 = tt.broadcast %tmp6_98 : tensor<64x1xi64> -> tensor<64x8xi64> loc(#loc145)
+      %tmp6_102 = arith.addi %tmp6_100, %tmp6_101 : tensor<64x8xi64> loc(#loc145)
+      %tmp6_103 = arith.muli %ks1, %ks2 : i64 loc(#loc146)
+      %tmp6_104 = tt.splat %tmp6_103 : i64 -> tensor<64x8xi64> loc(#loc147)
+      %tmp6_105 = arith.remsi %tmp6_102, %tmp6_104 : tensor<64x8xi64> loc(#loc147)
+      %tmp6_106 = tt.splat %in_ptr2 : !tt.ptr<f32> -> tensor<64x8x!tt.ptr<f32>> loc(#loc148)
+      %tmp6_107 = tt.addptr %tmp6_106, %tmp6_105 : tensor<64x8x!tt.ptr<f32>>, tensor<64x8xi64> loc(#loc148)
+      %tmp6_108 = tt.broadcast %r0_mask_17 : tensor<1x8xi1> -> tensor<64x8xi1> loc(#loc149)
+      %tmp6_109 = arith.andi %tmp6_108, %tmp2_30 : tensor<64x8xi1> loc(#loc149)
+      %tmp6_110 = tt.broadcast %xmask_6 : tensor<64x1xi1> -> tensor<64x8xi1> loc(#loc150)
+      %tmp6_111 = arith.andi %tmp6_109, %tmp6_110 : tensor<64x8xi1> loc(#loc150)
+      %tmp6_112 = arith.constant 0.000000e+00 : f32 loc(#loc151)
+      %tmp6_113 = arith.constant dense<0.000000e+00> : tensor<64x8xf32> loc(#loc151)
+      %tmp6_114 = tt.load %tmp6_107, %tmp6_111, %tmp6_113 evictionPolicy = evict_last : tensor<64x8x!tt.ptr<f32>> loc(#loc151)
+      %tmp7 = arith.mulf %tmp4_90, %tmp6_114 : tensor<64x8xf32> loc(#loc152)
+      %tmp9 = arith.mulf %tmp3_60, %tmp7 : tensor<64x8xf32> loc(#loc153)
+      %tmp10 = arith.constant 0.000000e+00 : f32 loc(#loc154)
+      %tmp10_115 = arith.constant dense<0.000000e+00> : tensor<64x8xf32> loc(#loc154)
+      %tmp11 = arith.select %tmp2_30, %tmp9, %tmp10_115 : tensor<64x8xi1>, tensor<64x8xf32> loc(#loc155)
+      %tmp14 = arith.addf %_tmp13_15, %tmp11 : tensor<64x8xf32> loc(#loc156)
+      %_tmp13_116 = tt.broadcast %r0_mask_17 : tensor<1x8xi1> -> tensor<64x8xi1> loc(#loc157)
+      %_tmp13_117 = tt.broadcast %xmask_6 : tensor<64x1xi1> -> tensor<64x8xi1> loc(#loc157)
+      %_tmp13_118 = arith.andi %_tmp13_116, %_tmp13_117 : tensor<64x8xi1> loc(#loc157)
+      %_tmp13_119 = arith.select %_tmp13_118, %tmp14, %_tmp13_15 : tensor<64x8xi1>, tensor<64x8xf32> loc(#loc158)
+      scf.yield %_tmp13_119 : tensor<64x8xf32> loc(#loc68)
+    } loc(#loc103)
+    %tmp13 = tt.call @"triton.language.standard.sum__fp32S64_8S__(1,)cconstexpr_1__(2,)cconstexpr_False__(3,)cNone"(%_tmp13_13) : (tensor<64x8xf32>) -> tensor<64xf32> loc(#loc159)
+    %tmp13_14 = tt.expand_dims %tmp13 {axis = 1 : i32} : tensor<64xf32> -> tensor<64x1xf32> loc(#loc160)
+    %4 = tt.splat %out_ptr0 : !tt.ptr<f32> -> tensor<64x1x!tt.ptr<f32>> loc(#loc71)
+    %5 = tt.addptr %4, %xindex_5 : tensor<64x1x!tt.ptr<f32>>, tensor<64x1xi32> loc(#loc71)
+    tt.store %5, %tmp13_14, %xmask_6 : tensor<64x1x!tt.ptr<f32>> loc(#loc72)
+    tt.return loc(#loc73)
+  } loc(#loc)
+  tt.func private @"triton.language.standard.sum__fp32S64_8S__(1,)cconstexpr_1__(2,)cconstexpr_False__(3,)cNone"(%input: tensor<64x8xf32> loc("input"(#loc74))) -> tensor<64xf32> attributes {noinline = false} {
+    %0 = "tt.reduce"(%input) <{axis = 1 : i32}> ({
+    ^bb0(%arg1: f32 loc(unknown), %arg2: f32 loc(unknown)):
+      %2 = tt.call @triton.language.standard._sum_combine__fp32_fp32__(%arg1, %arg2) : (f32, f32) -> f32 loc(#loc75)
+      tt.reduce.return %2 : f32 loc(#loc75)
+    }) : (tensor<64x8xf32>) -> tensor<64xf32> loc(#loc75)
+    tt.return %0 : tensor<64xf32> loc(#loc77)
+  ^bb1:  // no predecessors
+    %1 = ub.poison : tensor<64xf32> loc(#loc78)
+    tt.return %1 : tensor<64xf32> loc(#loc78)
+  } loc(#loc74)
+  tt.func private @triton.language.standard._sum_combine__fp32_fp32__(%a: f32 loc("a"(#loc79)), %b: f32 loc("b"(#loc79))) -> f32 attributes {noinline = false} {
+    %0 = arith.addf %a, %b : f32 loc(#loc80)
+    tt.return %0 : f32 loc(#loc81)
+  ^bb1:  // no predecessors
+    %1 = ub.poison : f32 loc(#loc82)
+    tt.return %1 : f32 loc(#loc82)
+  } loc(#loc79)
+} loc(#loc)
+#loc1 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":21:28)
+#loc2 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":21:33)
+#loc3 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":22:36)
+#loc4 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":22:44)
+#loc5 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":22:23)
+#loc6 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":23:21)
+#loc7 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":24:27)
+#loc8 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":24:37)
+#loc9 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":26:19)
+#loc10 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":27:19)
+#loc11 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":28:44)
+#loc12 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":30:40)
+#loc13 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":31:31)
+#loc14 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":32:29)
+#loc15 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":36:36)
+#loc16 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":36:32)
+#loc17 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":36:44)
+#loc18 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":36:26)
+#loc19 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":36:22)
+#loc20 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":37:19)
+#loc21 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":38:22)
+#loc22 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":39:67)
+#loc23 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":39:63)
+#loc24 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":39:75)
+#loc25 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":39:57)
+#loc26 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":39:53)
+#loc27 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":39:87)
+#loc28 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":39:83)
+#loc29 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":39:45)
+#loc30 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":39:39)
+#loc31 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":39:34)
+#loc32 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":39:106)
+#loc33 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":39:113)
+#loc34 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":39:96)
+#loc35 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":39:164)
+#loc36 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":40:67)
+#loc37 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":40:63)
+#loc38 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":40:75)
+#loc39 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":40:57)
+#loc40 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":40:53)
+#loc41 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":40:87)
+#loc42 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":40:83)
+#loc43 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":40:45)
+#loc44 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":40:39)
+#loc45 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":40:34)
+#loc46 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":40:106)
+#loc47 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":40:113)
+#loc48 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":40:96)
+#loc49 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":40:164)
+#loc50 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":42:57)
+#loc51 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":42:53)
+#loc52 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":42:65)
+#loc53 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":42:47)
+#loc54 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":42:43)
+#loc55 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":42:77)
+#loc56 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":42:73)
+#loc57 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":42:35)
+#loc58 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":42:95)
+#loc59 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":42:102)
+#loc60 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":42:85)
+#loc61 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":43:22)
+#loc62 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":45:22)
+#loc63 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":46:39)
+#loc64 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":47:37)
+#loc65 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":49:25)
+#loc66 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":50:36)
+#loc67 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":50:50)
+#loc68 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":50:8)
+#loc69 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":51:27)
+#loc70 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":51:30)
+#loc71 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":52:25)
+#loc72 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":52:37)
+#loc73 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":52:4)
+#loc75 = loc("/workspace/specforge/lib/python3.11/site-packages/triton/language/standard.py":291:36)
+#loc77 = loc("/workspace/specforge/lib/python3.11/site-packages/triton/language/standard.py":291:11)
+#loc78 = loc("/workspace/specforge/lib/python3.11/site-packages/triton/language/standard.py":291:4)
+#loc80 = loc("/workspace/specforge/lib/python3.11/site-packages/triton/language/standard.py":261:15)
+#loc81 = loc("/workspace/specforge/lib/python3.11/site-packages/triton/language/standard.py":261:11)
+#loc82 = loc("/workspace/specforge/lib/python3.11/site-packages/triton/language/standard.py":261:4)
+#loc92 = loc("xoffset"(#loc1))
+#loc93 = loc("xoffset"(#loc2))
+#loc94 = loc("xindex"(#loc3))
+#loc95 = loc("xindex"(#loc4))
+#loc96 = loc("xindex"(#loc5))
+#loc97 = loc("xmask"(#loc6))
+#loc98 = loc("r0_base"(#loc7))
+#loc99 = loc("r0_base"(#loc8))
+#loc100 = loc("x1"(#loc9))
+#loc101 = loc("x0"(#loc10))
+#loc102 = loc("_tmp13"(#loc11))
+#loc103 = loc("_tmp13"(#loc12))
+#loc104 = loc("r0_index"(#loc13))
+#loc105 = loc("r0_mask"(#loc14))
+#loc106 = loc("tmp0"(#loc15))
+#loc107 = loc("tmp0"(#loc16))
+#loc108 = loc("tmp0"(#loc17))
+#loc109 = loc("tmp0"(#loc18))
+#loc110 = loc("tmp0"(#loc19))
+#loc111 = loc("tmp1"(#loc20))
+#loc112 = loc("tmp2"(#loc21))
+#loc113 = loc("tmp3"(#loc22))
+#loc114 = loc("tmp3"(#loc23))
+#loc115 = loc("tmp3"(#loc24))
+#loc116 = loc("tmp3"(#loc25))
+#loc117 = loc("tmp3"(#loc26))
+#loc118 = loc("tmp3"(#loc27))
+#loc119 = loc("tmp3"(#loc28))
+#loc120 = loc("tmp3"(#loc29))
+#loc121 = loc("tmp3"(#loc30))
+#loc122 = loc("tmp3"(#loc31))
+#loc123 = loc("tmp3"(#loc32))
+#loc124 = loc("tmp3"(#loc33))
+#loc125 = loc("tmp3"(#loc34))
+#loc126 = loc("tmp3"(#loc35))
+#loc127 = loc("tmp4"(#loc36))
+#loc128 = loc("tmp4"(#loc37))
+#loc129 = loc("tmp4"(#loc38))
+#loc130 = loc("tmp4"(#loc39))
+#loc131 = loc("tmp4"(#loc40))
+#loc132 = loc("tmp4"(#loc41))
+#loc133 = loc("tmp4"(#loc42))
+#loc134 = loc("tmp4"(#loc43))
+#loc135 = loc("tmp4"(#loc44))
+#loc136 = loc("tmp4"(#loc45))
+#loc137 = loc("tmp4"(#loc46))
+#loc138 = loc("tmp4"(#loc47))
+#loc139 = loc("tmp4"(#loc48))
+#loc140 = loc("tmp4"(#loc49))
+#loc141 = loc("tmp6"(#loc50))
+#loc142 = loc("tmp6"(#loc51))
+#loc143 = loc("tmp6"(#loc52))
+#loc144 = loc("tmp6"(#loc53))
+#loc145 = loc("tmp6"(#loc54))
+#loc146 = loc("tmp6"(#loc55))
+#loc147 = loc("tmp6"(#loc56))
+#loc148 = loc("tmp6"(#loc57))
+#loc149 = loc("tmp6"(#loc58))
+#loc150 = loc("tmp6"(#loc59))
+#loc151 = loc("tmp6"(#loc60))
+#loc152 = loc("tmp7"(#loc61))
+#loc153 = loc("tmp9"(#loc62))
+#loc154 = loc("tmp10"(#loc63))
+#loc155 = loc("tmp11"(#loc64))
+#loc156 = loc("tmp14"(#loc65))
+#loc157 = loc("_tmp13"(#loc66))
+#loc158 = loc("_tmp13"(#loc67))
+#loc159 = loc("tmp13"(#loc69))
+#loc160 = loc("tmp13"(#loc70))

SpecForge-ext/cache/compiled_kernels/triton/2/5KYA3IXELFPSJGJX4ZJXZEGZVFALDHEANQ7YQX554R55QVAC6F5A/triton_red_fused__to_copy_mul_sum_0.ttgir

@@ -0,0 +1,176 @@
+#blocked = #ttg.blocked<{sizePerThread = [1, 1], threadsPerWarp = [32, 1], warpsPerCTA = [2, 2], order = [0, 1]}>
+#loc = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":18:0)
+#loc1 = loc(unknown)
+#loc40 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":51:27)
+#loc46 = loc("in_ptr0"(#loc))
+#loc47 = loc("in_ptr1"(#loc))
+#loc48 = loc("in_ptr2"(#loc))
+#loc49 = loc("out_ptr0"(#loc))
+#loc50 = loc("ks0"(#loc))
+#loc51 = loc("ks1"(#loc))
+#loc52 = loc("ks2"(#loc))
+#loc53 = loc("xnumel"(#loc))
+#loc54 = loc("r0_numel"(#loc))
+#loc91 = loc("tmp13"(#loc40))
+#loc94 = loc(callsite(#loc1 at #loc91))
+module attributes {"ttg.num-ctas" = 1 : i32, "ttg.num-warps" = 4 : i32, ttg.target = "cuda:90", "ttg.threads-per-warp" = 32 : i32} {
+  tt.func public @triton_red_fused__to_copy_mul_sum_0(%in_ptr0: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("in_ptr0"(#loc)), %in_ptr1: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("in_ptr1"(#loc)), %in_ptr2: !tt.ptr<f32> {tt.divisibility = 16 : i32} loc("in_ptr2"(#loc)), %out_ptr0: !tt.ptr<f32> {tt.divisibility = 16 : i32} loc("out_ptr0"(#loc)), %ks0: i64 loc("ks0"(#loc)), %ks1: i64 loc("ks1"(#loc)), %ks2: i64 loc("ks2"(#loc)), %xnumel: i32 {tt.divisibility = 16 : i32} loc("xnumel"(#loc)), %r0_numel: i32 loc("r0_numel"(#loc))) attributes {noinline = false} {
+    %cst = arith.constant dense<0.000000e+00> : tensor<64x8xf32, #blocked> loc(#loc1)
+    %c31_i64 = arith.constant 31 : i64 loc(#loc1)
+    %c32_i64 = arith.constant 32 : i64 loc(#loc1)
+    %c0_i32 = arith.constant 0 : i32 loc(#loc1)
+    %c8_i32 = arith.constant 8 : i32 loc(#loc1)
+    %c64_i32 = arith.constant 64 : i32 loc(#loc1)
+    %cst_0 = arith.constant dense<0.000000e+00> : tensor<64x8xbf16, #blocked> loc(#loc1)
+    %xoffset = tt.get_program_id x : i32 loc(#loc55)
+    %xoffset_1 = arith.muli %xoffset, %c64_i32 : i32 loc(#loc56)
+    %xindex = tt.make_range {end = 64 : i32, start = 0 : i32} : tensor<64xi32, #ttg.slice<{dim = 1, parent = #blocked}>> loc(#loc57)
+    %xindex_2 = tt.expand_dims %xindex {axis = 1 : i32} : tensor<64xi32, #ttg.slice<{dim = 1, parent = #blocked}>> -> tensor<64x1xi32, #blocked> loc(#loc57)
+    %xindex_3 = tt.splat %xoffset_1 : i32 -> tensor<64x1xi32, #blocked> loc(#loc58)
+    %xindex_4 = arith.addi %xindex_3, %xindex_2 : tensor<64x1xi32, #blocked> loc(#loc58)
+    %xmask = tt.splat %xnumel : i32 -> tensor<64x1xi32, #blocked> loc(#loc59)
+    %xmask_5 = arith.cmpi slt, %xindex_4, %xmask : tensor<64x1xi32, #blocked> loc(#loc59)
+    %r0_base = tt.make_range {end = 8 : i32, start = 0 : i32} : tensor<8xi32, #ttg.slice<{dim = 0, parent = #blocked}>> loc(#loc60)
+    %r0_base_6 = tt.expand_dims %r0_base {axis = 0 : i32} : tensor<8xi32, #ttg.slice<{dim = 0, parent = #blocked}>> -> tensor<1x8xi32, #blocked> loc(#loc60)
+    %x1 = arith.extsi %xindex_4 : tensor<64x1xi32, #blocked> to tensor<64x1xi64, #blocked> loc(#loc61)
+    %x1_7 = tt.splat %ks0 : i64 -> tensor<64x1xi64, #blocked> loc(#loc61)
+    %x1_8 = arith.divsi %x1, %x1_7 : tensor<64x1xi64, #blocked> loc(#loc61)
+    %x0 = arith.remsi %x1, %x1_7 : tensor<64x1xi64, #blocked> loc(#loc62)
+    %r0_mask = tt.splat %r0_numel : i32 -> tensor<1x8xi32, #blocked> loc(#loc63)
+    %tmp0 = arith.muli %ks1, %ks2 : i64 loc(#loc64)
+    %tmp0_9 = arith.addi %tmp0, %c31_i64 : i64 loc(#loc65)
+    %tmp0_10 = arith.divsi %tmp0_9, %c32_i64 : i64 loc(#loc66)
+    %tmp0_11 = tt.splat %tmp0_10 : i64 -> tensor<64x1xi64, #blocked> loc(#loc67)
+    %tmp0_12 = arith.muli %x1_8, %tmp0_11 : tensor<64x1xi64, #blocked> loc(#loc67)
+    %tmp0_13 = tt.broadcast %tmp0_12 : tensor<64x1xi64, #blocked> -> tensor<64x8xi64, #blocked> loc(#loc68)
+    %tmp2 = tt.splat %tmp0 : i64 -> tensor<64x8xi64, #blocked> loc(#loc69)
+    %tmp3 = tt.splat %ks0 : i64 -> tensor<64x8xi64, #blocked> loc(#loc70)
+    %tmp3_14 = tt.broadcast %x0 : tensor<64x1xi64, #blocked> -> tensor<64x8xi64, #blocked> loc(#loc71)
+    %tmp3_15 = tt.splat %in_ptr0 : !tt.ptr<bf16> -> tensor<64x8x!tt.ptr<bf16>, #blocked> loc(#loc72)
+    %tmp3_16 = tt.broadcast %xmask_5 : tensor<64x1xi1, #blocked> -> tensor<64x8xi1, #blocked> loc(#loc73)
+    %tmp4 = tt.splat %in_ptr1 : !tt.ptr<bf16> -> tensor<64x8x!tt.ptr<bf16>, #blocked> loc(#loc74)
+    %tmp6 = tt.splat %in_ptr2 : !tt.ptr<f32> -> tensor<64x8x!tt.ptr<f32>, #blocked> loc(#loc75)
+    %_tmp13 = scf.for %_tmp13_18 = %c0_i32 to %r0_numel step %c8_i32 iter_args(%arg10 = %cst) -> (tensor<64x8xf32, #blocked>)  : i32 {
+      %r0_index = tt.splat %_tmp13_18 : i32 -> tensor<1x8xi32, #blocked> loc(#loc77)
+      %r0_index_19 = arith.addi %r0_index, %r0_base_6 : tensor<1x8xi32, #blocked> loc(#loc77)
+      %r0_mask_20 = arith.cmpi slt, %r0_index_19, %r0_mask : tensor<1x8xi32, #blocked> loc(#loc63)
+      %tmp0_21 = arith.extsi %r0_index_19 : tensor<1x8xi32, #blocked> to tensor<1x8xi64, #blocked> loc(#loc68)
+      %tmp0_22 = tt.broadcast %tmp0_21 : tensor<1x8xi64, #blocked> -> tensor<64x8xi64, #blocked> loc(#loc68)
+      %tmp0_23 = arith.addi %tmp0_22, %tmp0_13 : tensor<64x8xi64, #blocked> loc(#loc68)
+      %tmp2_24 = arith.cmpi slt, %tmp0_23, %tmp2 : tensor<64x8xi64, #blocked> loc(#loc69)
+      %tmp3_25 = arith.remsi %tmp0_23, %tmp2 : tensor<64x8xi64, #blocked> loc(#loc78)
+      %tmp3_26 = arith.muli %tmp3, %tmp3_25 : tensor<64x8xi64, #blocked> loc(#loc70)
+      %tmp3_27 = arith.addi %tmp3_14, %tmp3_26 : tensor<64x8xi64, #blocked> loc(#loc71)
+      %tmp3_28 = tt.addptr %tmp3_15, %tmp3_27 : tensor<64x8x!tt.ptr<bf16>, #blocked>, tensor<64x8xi64, #blocked> loc(#loc72)
+      %tmp3_29 = tt.broadcast %r0_mask_20 : tensor<1x8xi1, #blocked> -> tensor<64x8xi1, #blocked> loc(#loc79)
+      %tmp3_30 = arith.andi %tmp3_29, %tmp2_24 : tensor<64x8xi1, #blocked> loc(#loc79)
+      %tmp3_31 = arith.andi %tmp3_30, %tmp3_16 : tensor<64x8xi1, #blocked> loc(#loc73)
+      %tmp3_32 = tt.load %tmp3_28, %tmp3_31, %cst_0 evictionPolicy = evict_last : tensor<64x8x!tt.ptr<bf16>, #blocked> loc(#loc80)
+      %tmp3_33 = arith.extf %tmp3_32 : tensor<64x8xbf16, #blocked> to tensor<64x8xf32, #blocked> loc(#loc81)
+      %tmp4_34 = tt.addptr %tmp4, %tmp3_27 : tensor<64x8x!tt.ptr<bf16>, #blocked>, tensor<64x8xi64, #blocked> loc(#loc74)
+      %tmp4_35 = tt.load %tmp4_34, %tmp3_31, %cst_0 evictionPolicy = evict_last : tensor<64x8x!tt.ptr<bf16>, #blocked> loc(#loc82)
+      %tmp4_36 = arith.extf %tmp4_35 : tensor<64x8xbf16, #blocked> to tensor<64x8xf32, #blocked> loc(#loc83)
+      %tmp6_37 = tt.addptr %tmp6, %tmp3_25 : tensor<64x8x!tt.ptr<f32>, #blocked>, tensor<64x8xi64, #blocked> loc(#loc75)
+      %tmp6_38 = tt.load %tmp6_37, %tmp3_31, %cst evictionPolicy = evict_last : tensor<64x8x!tt.ptr<f32>, #blocked> loc(#loc84)
+      %tmp7 = arith.mulf %tmp4_36, %tmp6_38 : tensor<64x8xf32, #blocked> loc(#loc85)
+      %tmp9 = arith.mulf %tmp3_33, %tmp7 : tensor<64x8xf32, #blocked> loc(#loc86)
+      %tmp11 = arith.select %tmp2_24, %tmp9, %cst : tensor<64x8xi1, #blocked>, tensor<64x8xf32, #blocked> loc(#loc87)
+      %tmp14 = arith.addf %arg10, %tmp11 : tensor<64x8xf32, #blocked> loc(#loc88)
+      %_tmp13_39 = arith.andi %tmp3_29, %tmp3_16 : tensor<64x8xi1, #blocked> loc(#loc89)
+      %_tmp13_40 = arith.select %_tmp13_39, %tmp14, %arg10 : tensor<64x8xi1, #blocked>, tensor<64x8xf32, #blocked> loc(#loc90)
+      scf.yield %_tmp13_40 : tensor<64x8xf32, #blocked> loc(#loc38)
+    } loc(#loc76)
+    %tmp13 = "tt.reduce"(%_tmp13) <{axis = 1 : i32}> ({
+    ^bb0(%tmp13_18: f32 loc(callsite(#loc1 at #loc91)), %tmp13_19: f32 loc(callsite(#loc1 at #loc91))):
+      %tmp13_20 = arith.addf %tmp13_18, %tmp13_19 : f32 loc(#loc95)
+      tt.reduce.return %tmp13_20 : f32 loc(#loc93)
+    }) : (tensor<64x8xf32, #blocked>) -> tensor<64xf32, #ttg.slice<{dim = 1, parent = #blocked}>> loc(#loc93)
+    %tmp13_17 = tt.expand_dims %tmp13 {axis = 1 : i32} : tensor<64xf32, #ttg.slice<{dim = 1, parent = #blocked}>> -> tensor<64x1xf32, #blocked> loc(#loc92)
+    %0 = tt.splat %out_ptr0 : !tt.ptr<f32> -> tensor<64x1x!tt.ptr<f32>, #blocked> loc(#loc43)
+    %1 = tt.addptr %0, %xindex_4 : tensor<64x1x!tt.ptr<f32>, #blocked>, tensor<64x1xi32, #blocked> loc(#loc43)
+    tt.store %1, %tmp13_17, %xmask_5 : tensor<64x1x!tt.ptr<f32>, #blocked> loc(#loc44)
+    tt.return loc(#loc45)
+  } loc(#loc)
+} loc(#loc)
+#loc2 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":21:28)
+#loc3 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":21:33)
+#loc4 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":22:44)
+#loc5 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":22:23)
+#loc6 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":23:21)
+#loc7 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":24:37)
+#loc8 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":26:19)
+#loc9 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":27:19)
+#loc10 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":32:29)
+#loc11 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":36:36)
+#loc12 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":36:32)
+#loc13 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":36:44)
+#loc14 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":36:26)
+#loc15 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":36:22)
+#loc16 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":38:22)
+#loc17 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":39:45)
+#loc18 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":39:39)
+#loc19 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":39:34)
+#loc20 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":39:113)
+#loc21 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":40:34)
+#loc22 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":42:35)
+#loc23 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":30:40)
+#loc24 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":31:31)
+#loc25 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":39:83)
+#loc26 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":39:106)
+#loc27 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":39:96)
+#loc28 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":39:164)
+#loc29 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":40:96)
+#loc30 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":40:164)
+#loc31 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":42:85)
+#loc32 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":43:22)
+#loc33 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":45:22)
+#loc34 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":47:37)
+#loc35 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":49:25)
+#loc36 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":50:36)
+#loc37 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":50:50)
+#loc38 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":50:8)
+#loc39 = loc("/workspace/specforge/lib/python3.11/site-packages/triton/language/standard.py":291:36)
+#loc41 = loc("/workspace/specforge/lib/python3.11/site-packages/triton/language/standard.py":261:15)
+#loc42 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":51:30)
+#loc43 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":52:25)
+#loc44 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":52:37)
+#loc45 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":52:4)
+#loc55 = loc("xoffset"(#loc2))
+#loc56 = loc("xoffset"(#loc3))
+#loc57 = loc("xindex"(#loc4))
+#loc58 = loc("xindex"(#loc5))
+#loc59 = loc("xmask"(#loc6))
+#loc60 = loc("r0_base"(#loc7))
+#loc61 = loc("x1"(#loc8))
+#loc62 = loc("x0"(#loc9))
+#loc63 = loc("r0_mask"(#loc10))
+#loc64 = loc("tmp0"(#loc11))
+#loc65 = loc("tmp0"(#loc12))
+#loc66 = loc("tmp0"(#loc13))
+#loc67 = loc("tmp0"(#loc14))
+#loc68 = loc("tmp0"(#loc15))
+#loc69 = loc("tmp2"(#loc16))
+#loc70 = loc("tmp3"(#loc17))
+#loc71 = loc("tmp3"(#loc18))
+#loc72 = loc("tmp3"(#loc19))
+#loc73 = loc("tmp3"(#loc20))
+#loc74 = loc("tmp4"(#loc21))
+#loc75 = loc("tmp6"(#loc22))
+#loc76 = loc("_tmp13"(#loc23))
+#loc77 = loc("r0_index"(#loc24))
+#loc78 = loc("tmp3"(#loc25))
+#loc79 = loc("tmp3"(#loc26))
+#loc80 = loc("tmp3"(#loc27))
+#loc81 = loc("tmp3"(#loc28))
+#loc82 = loc("tmp4"(#loc29))
+#loc83 = loc("tmp4"(#loc30))
+#loc84 = loc("tmp6"(#loc31))
+#loc85 = loc("tmp7"(#loc32))
+#loc86 = loc("tmp9"(#loc33))
+#loc87 = loc("tmp11"(#loc34))
+#loc88 = loc("tmp14"(#loc35))
+#loc89 = loc("_tmp13"(#loc36))
+#loc90 = loc("_tmp13"(#loc37))
+#loc92 = loc("tmp13"(#loc42))
+#loc93 = loc(callsite(#loc39 at #loc91))
+#loc95 = loc(callsite(#loc41 at #loc93))

SpecForge-ext/cache/compiled_kernels/triton/2/5KYA3IXELFPSJGJX4ZJXZEGZVFALDHEANQ7YQX554R55QVAC6F5A/triton_red_fused__to_copy_mul_sum_0.ttir

@@ -0,0 +1,179 @@
+#loc = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":18:0)
+#loc1 = loc(unknown)
+#loc42 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":51:27)
+#loc48 = loc("in_ptr0"(#loc))
+#loc49 = loc("in_ptr1"(#loc))
+#loc50 = loc("in_ptr2"(#loc))
+#loc51 = loc("out_ptr0"(#loc))
+#loc52 = loc("ks0"(#loc))
+#loc53 = loc("ks1"(#loc))
+#loc54 = loc("ks2"(#loc))
+#loc55 = loc("xnumel"(#loc))
+#loc56 = loc("r0_numel"(#loc))
+#loc95 = loc("tmp13"(#loc42))
+#loc98 = loc(callsite(#loc1 at #loc95))
+module {
+  tt.func public @triton_red_fused__to_copy_mul_sum_0(%in_ptr0: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("in_ptr0"(#loc)), %in_ptr1: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("in_ptr1"(#loc)), %in_ptr2: !tt.ptr<f32> {tt.divisibility = 16 : i32} loc("in_ptr2"(#loc)), %out_ptr0: !tt.ptr<f32> {tt.divisibility = 16 : i32} loc("out_ptr0"(#loc)), %ks0: i64 loc("ks0"(#loc)), %ks1: i64 loc("ks1"(#loc)), %ks2: i64 loc("ks2"(#loc)), %xnumel: i32 {tt.divisibility = 16 : i32} loc("xnumel"(#loc)), %r0_numel: i32 loc("r0_numel"(#loc))) attributes {noinline = false} {
+    %cst = arith.constant dense<0.000000e+00> : tensor<64x8xbf16> loc(#loc1)
+    %c8_i32 = arith.constant 8 : i32 loc(#loc2)
+    %c0_i32 = arith.constant 0 : i32 loc(#loc2)
+    %c32_i64 = arith.constant 32 : i64 loc(#loc1)
+    %c31_i64 = arith.constant 31 : i64 loc(#loc1)
+    %cst_0 = arith.constant dense<0.000000e+00> : tensor<64x8xf32> loc(#loc1)
+    %c64_i32 = arith.constant 64 : i32 loc(#loc1)
+    %xoffset = tt.get_program_id x : i32 loc(#loc57)
+    %xoffset_1 = arith.muli %xoffset, %c64_i32 : i32 loc(#loc58)
+    %xindex = tt.make_range {end = 64 : i32, start = 0 : i32} : tensor<64xi32> loc(#loc59)
+    %xindex_2 = tt.expand_dims %xindex {axis = 1 : i32} : tensor<64xi32> -> tensor<64x1xi32> loc(#loc60)
+    %xindex_3 = tt.splat %xoffset_1 : i32 -> tensor<64x1xi32> loc(#loc61)
+    %xindex_4 = arith.addi %xindex_3, %xindex_2 : tensor<64x1xi32> loc(#loc61)
+    %xmask = tt.splat %xnumel : i32 -> tensor<64x1xi32> loc(#loc62)
+    %xmask_5 = arith.cmpi slt, %xindex_4, %xmask : tensor<64x1xi32> loc(#loc62)
+    %r0_base = tt.make_range {end = 8 : i32, start = 0 : i32} : tensor<8xi32> loc(#loc63)
+    %r0_base_6 = tt.expand_dims %r0_base {axis = 0 : i32} : tensor<8xi32> -> tensor<1x8xi32> loc(#loc64)
+    %x1 = arith.extsi %xindex_4 : tensor<64x1xi32> to tensor<64x1xi64> loc(#loc65)
+    %x1_7 = tt.splat %ks0 : i64 -> tensor<64x1xi64> loc(#loc65)
+    %x1_8 = arith.divsi %x1, %x1_7 : tensor<64x1xi64> loc(#loc65)
+    %x0 = arith.remsi %x1, %x1_7 : tensor<64x1xi64> loc(#loc66)
+    %_tmp13 = scf.for %r0_offset = %c0_i32 to %r0_numel step %c8_i32 iter_args(%_tmp13_10 = %cst_0) -> (tensor<64x8xf32>)  : i32 {
+      %r0_index = tt.splat %r0_offset : i32 -> tensor<1x8xi32> loc(#loc68)
+      %r0_index_11 = arith.addi %r0_index, %r0_base_6 : tensor<1x8xi32> loc(#loc68)
+      %r0_mask = tt.splat %r0_numel : i32 -> tensor<1x8xi32> loc(#loc69)
+      %r0_mask_12 = arith.cmpi slt, %r0_index_11, %r0_mask : tensor<1x8xi32> loc(#loc69)
+      %tmp0 = arith.muli %ks1, %ks2 : i64 loc(#loc70)
+      %tmp0_13 = arith.addi %tmp0, %c31_i64 : i64 loc(#loc71)
+      %tmp0_14 = arith.divsi %tmp0_13, %c32_i64 : i64 loc(#loc72)
+      %tmp0_15 = tt.splat %tmp0_14 : i64 -> tensor<64x1xi64> loc(#loc73)
+      %tmp0_16 = arith.muli %x1_8, %tmp0_15 : tensor<64x1xi64> loc(#loc73)
+      %tmp0_17 = arith.extsi %r0_index_11 : tensor<1x8xi32> to tensor<1x8xi64> loc(#loc74)
+      %tmp0_18 = tt.broadcast %tmp0_17 : tensor<1x8xi64> -> tensor<64x8xi64> loc(#loc74)
+      %tmp0_19 = tt.broadcast %tmp0_16 : tensor<64x1xi64> -> tensor<64x8xi64> loc(#loc74)
+      %tmp0_20 = arith.addi %tmp0_18, %tmp0_19 : tensor<64x8xi64> loc(#loc74)
+      %tmp2 = tt.splat %tmp0 : i64 -> tensor<64x8xi64> loc(#loc75)
+      %tmp2_21 = arith.cmpi slt, %tmp0_20, %tmp2 : tensor<64x8xi64> loc(#loc75)
+      %tmp3 = arith.remsi %tmp0_20, %tmp2 : tensor<64x8xi64> loc(#loc76)
+      %tmp3_22 = tt.splat %ks0 : i64 -> tensor<64x8xi64> loc(#loc77)
+      %tmp3_23 = arith.muli %tmp3_22, %tmp3 : tensor<64x8xi64> loc(#loc77)
+      %tmp3_24 = tt.broadcast %x0 : tensor<64x1xi64> -> tensor<64x8xi64> loc(#loc78)
+      %tmp3_25 = arith.addi %tmp3_24, %tmp3_23 : tensor<64x8xi64> loc(#loc78)
+      %tmp3_26 = tt.splat %in_ptr0 : !tt.ptr<bf16> -> tensor<64x8x!tt.ptr<bf16>> loc(#loc79)
+      %tmp3_27 = tt.addptr %tmp3_26, %tmp3_25 : tensor<64x8x!tt.ptr<bf16>>, tensor<64x8xi64> loc(#loc79)
+      %tmp3_28 = tt.broadcast %r0_mask_12 : tensor<1x8xi1> -> tensor<64x8xi1> loc(#loc80)
+      %tmp3_29 = arith.andi %tmp3_28, %tmp2_21 : tensor<64x8xi1> loc(#loc80)
+      %tmp3_30 = tt.broadcast %xmask_5 : tensor<64x1xi1> -> tensor<64x8xi1> loc(#loc81)
+      %tmp3_31 = arith.andi %tmp3_29, %tmp3_30 : tensor<64x8xi1> loc(#loc81)
+      %tmp3_32 = tt.load %tmp3_27, %tmp3_31, %cst evictionPolicy = evict_last : tensor<64x8x!tt.ptr<bf16>> loc(#loc82)
+      %tmp3_33 = arith.extf %tmp3_32 : tensor<64x8xbf16> to tensor<64x8xf32> loc(#loc83)
+      %tmp4 = tt.splat %in_ptr1 : !tt.ptr<bf16> -> tensor<64x8x!tt.ptr<bf16>> loc(#loc84)
+      %tmp4_34 = tt.addptr %tmp4, %tmp3_25 : tensor<64x8x!tt.ptr<bf16>>, tensor<64x8xi64> loc(#loc84)
+      %tmp4_35 = tt.load %tmp4_34, %tmp3_31, %cst evictionPolicy = evict_last : tensor<64x8x!tt.ptr<bf16>> loc(#loc85)
+      %tmp4_36 = arith.extf %tmp4_35 : tensor<64x8xbf16> to tensor<64x8xf32> loc(#loc86)
+      %tmp6 = tt.splat %in_ptr2 : !tt.ptr<f32> -> tensor<64x8x!tt.ptr<f32>> loc(#loc87)
+      %tmp6_37 = tt.addptr %tmp6, %tmp3 : tensor<64x8x!tt.ptr<f32>>, tensor<64x8xi64> loc(#loc87)
+      %tmp6_38 = tt.load %tmp6_37, %tmp3_31, %cst_0 evictionPolicy = evict_last : tensor<64x8x!tt.ptr<f32>> loc(#loc88)
+      %tmp7 = arith.mulf %tmp4_36, %tmp6_38 : tensor<64x8xf32> loc(#loc89)
+      %tmp9 = arith.mulf %tmp3_33, %tmp7 : tensor<64x8xf32> loc(#loc90)
+      %tmp11 = arith.select %tmp2_21, %tmp9, %cst_0 : tensor<64x8xi1>, tensor<64x8xf32> loc(#loc91)
+      %tmp14 = arith.addf %_tmp13_10, %tmp11 : tensor<64x8xf32> loc(#loc92)
+      %_tmp13_39 = arith.andi %tmp3_28, %tmp3_30 : tensor<64x8xi1> loc(#loc93)
+      %_tmp13_40 = arith.select %_tmp13_39, %tmp14, %_tmp13_10 : tensor<64x8xi1>, tensor<64x8xf32> loc(#loc94)
+      scf.yield %_tmp13_40 : tensor<64x8xf32> loc(#loc40)
+    } loc(#loc67)
+    %tmp13 = "tt.reduce"(%_tmp13) <{axis = 1 : i32}> ({
+    ^bb0(%tmp13_10: f32 loc(callsite(#loc1 at #loc95)), %tmp13_11: f32 loc(callsite(#loc1 at #loc95))):
+      %tmp13_12 = arith.addf %tmp13_10, %tmp13_11 : f32 loc(#loc99)
+      tt.reduce.return %tmp13_12 : f32 loc(#loc97)
+    }) : (tensor<64x8xf32>) -> tensor<64xf32> loc(#loc97)
+    %tmp13_9 = tt.expand_dims %tmp13 {axis = 1 : i32} : tensor<64xf32> -> tensor<64x1xf32> loc(#loc96)
+    %0 = tt.splat %out_ptr0 : !tt.ptr<f32> -> tensor<64x1x!tt.ptr<f32>> loc(#loc45)
+    %1 = tt.addptr %0, %xindex_4 : tensor<64x1x!tt.ptr<f32>>, tensor<64x1xi32> loc(#loc45)
+    tt.store %1, %tmp13_9, %xmask_5 : tensor<64x1x!tt.ptr<f32>> loc(#loc46)
+    tt.return loc(#loc47)
+  } loc(#loc)
+} loc(#loc)
+#loc2 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":30:40)
+#loc3 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":21:28)
+#loc4 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":21:33)
+#loc5 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":22:36)
+#loc6 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":22:44)
+#loc7 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":22:23)
+#loc8 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":23:21)
+#loc9 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":24:27)
+#loc10 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":24:37)
+#loc11 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":26:19)
+#loc12 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":27:19)
+#loc13 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":31:31)
+#loc14 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":32:29)
+#loc15 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":36:36)
+#loc16 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":36:32)
+#loc17 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":36:44)
+#loc18 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":36:26)
+#loc19 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":36:22)
+#loc20 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":38:22)
+#loc21 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":39:83)
+#loc22 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":39:45)
+#loc23 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":39:39)
+#loc24 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":39:34)
+#loc25 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":39:106)
+#loc26 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":39:113)
+#loc27 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":39:96)
+#loc28 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":39:164)
+#loc29 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":40:34)
+#loc30 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":40:96)
+#loc31 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":40:164)
+#loc32 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":42:35)
+#loc33 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":42:85)
+#loc34 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":43:22)
+#loc35 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":45:22)
+#loc36 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":47:37)
+#loc37 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":49:25)
+#loc38 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":50:36)
+#loc39 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":50:50)
+#loc40 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":50:8)
+#loc41 = loc("/workspace/specforge/lib/python3.11/site-packages/triton/language/standard.py":291:36)
+#loc43 = loc("/workspace/specforge/lib/python3.11/site-packages/triton/language/standard.py":261:15)
+#loc44 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":51:30)
+#loc45 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":52:25)
+#loc46 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":52:37)
+#loc47 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/2k/c2kz55grrshpc3qkvg6jesbu63ts5wlhkwtjukm7zkcvhkilgn76.py":52:4)
+#loc57 = loc("xoffset"(#loc3))
+#loc58 = loc("xoffset"(#loc4))
+#loc59 = loc("xindex"(#loc5))
+#loc60 = loc("xindex"(#loc6))
+#loc61 = loc("xindex"(#loc7))
+#loc62 = loc("xmask"(#loc8))
+#loc63 = loc("r0_base"(#loc9))
+#loc64 = loc("r0_base"(#loc10))
+#loc65 = loc("x1"(#loc11))
+#loc66 = loc("x0"(#loc12))
+#loc67 = loc("_tmp13"(#loc2))
+#loc68 = loc("r0_index"(#loc13))
+#loc69 = loc("r0_mask"(#loc14))
+#loc70 = loc("tmp0"(#loc15))
+#loc71 = loc("tmp0"(#loc16))
+#loc72 = loc("tmp0"(#loc17))
+#loc73 = loc("tmp0"(#loc18))
+#loc74 = loc("tmp0"(#loc19))
+#loc75 = loc("tmp2"(#loc20))
+#loc76 = loc("tmp3"(#loc21))
+#loc77 = loc("tmp3"(#loc22))
+#loc78 = loc("tmp3"(#loc23))
+#loc79 = loc("tmp3"(#loc24))
+#loc80 = loc("tmp3"(#loc25))
+#loc81 = loc("tmp3"(#loc26))
+#loc82 = loc("tmp3"(#loc27))
+#loc83 = loc("tmp3"(#loc28))
+#loc84 = loc("tmp4"(#loc29))
+#loc85 = loc("tmp4"(#loc30))
+#loc86 = loc("tmp4"(#loc31))
+#loc87 = loc("tmp6"(#loc32))
+#loc88 = loc("tmp6"(#loc33))
+#loc89 = loc("tmp7"(#loc34))
+#loc90 = loc("tmp9"(#loc35))
+#loc91 = loc("tmp11"(#loc36))
+#loc92 = loc("tmp14"(#loc37))
+#loc93 = loc("_tmp13"(#loc38))
+#loc94 = loc("_tmp13"(#loc39))
+#loc96 = loc("tmp13"(#loc44))
+#loc97 = loc(callsite(#loc41 at #loc95))
+#loc99 = loc(callsite(#loc43 at #loc97))

SpecForge-ext/cache/compiled_kernels/triton/2/5QCATXXJOHVG6NQ75K46KBBWQRORJ7QMSXCTH7GV3JOSAQPCCD4Q/__grp__triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4.json

@@ -0,0 +1 @@
+{"child_paths": {"triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4.source": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/5QCATXXJOHVG6NQ75K46KBBWQRORJ7QMSXCTH7GV3JOSAQPCCD4Q/triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4.source", "triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4.ttir": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/5QCATXXJOHVG6NQ75K46KBBWQRORJ7QMSXCTH7GV3JOSAQPCCD4Q/triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4.ttir", "triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4.ttgir": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/5QCATXXJOHVG6NQ75K46KBBWQRORJ7QMSXCTH7GV3JOSAQPCCD4Q/triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4.ttgir", "triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4.llir": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/5QCATXXJOHVG6NQ75K46KBBWQRORJ7QMSXCTH7GV3JOSAQPCCD4Q/triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4.llir", "triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4.ptx": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/5QCATXXJOHVG6NQ75K46KBBWQRORJ7QMSXCTH7GV3JOSAQPCCD4Q/triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4.ptx", "triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4.cubin": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/5QCATXXJOHVG6NQ75K46KBBWQRORJ7QMSXCTH7GV3JOSAQPCCD4Q/triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4.cubin", "triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4.json": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/5QCATXXJOHVG6NQ75K46KBBWQRORJ7QMSXCTH7GV3JOSAQPCCD4Q/triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4.json"}}

SpecForge-ext/cache/compiled_kernels/triton/2/5QCATXXJOHVG6NQ75K46KBBWQRORJ7QMSXCTH7GV3JOSAQPCCD4Q/triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4.json

@@ -0,0 +1 @@
+{"hash": "ec0409dee971ea6f361feab9e50436845d14fe0c95c533fcd5da5d2041e210f9", "target": {"backend": "cuda", "arch": 90, "warp_size": 32}, "num_warps": 2, "num_ctas": 1, "num_stages": 1, "warp_size": 32, "maxnreg": null, "cluster_dims": [1, 1, 1], "ptx_version": null, "ptx_options": null, "ir_override": null, "enable_fp_fusion": true, "launch_cooperative_grid": false, "launch_pdl": false, "supported_fp8_dtypes": ["fp8e4b15", "fp8e4nv", "fp8e5"], "deprecated_fp8_dot_operand_dtypes": ["fp8e4b15"], "default_dot_input_precision": "tf32", "allowed_dot_input_precisions": ["tf32", "tf32x3", "ieee"], "max_num_imprecise_acc_default": 1073741824, "extern_libs": [["libdevice", "/workspace/specforge/lib/python3.11/site-packages/triton/backends/nvidia/lib/libdevice.10.bc"]], "debug": true, "backend_name": "cuda", "sanitize_overflow": false, "arch": "sm90", "instrumentation_mode": "", "triton_version": "3.5.1", "tensordesc_meta": [], "shared": 0, "tmem_size": 0, "global_scratch_size": 0, "global_scratch_align": 1, "profile_scratch_size": 0, "profile_scratch_align": 1, "name": "triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4"}

SpecForge-ext/cache/compiled_kernels/triton/2/5QCATXXJOHVG6NQ75K46KBBWQRORJ7QMSXCTH7GV3JOSAQPCCD4Q/triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4.llir

@@ -0,0 +1,91 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+target datalayout = "e-p3:32:32-p4:32:32-p5:32:32-p6:32:32-p7:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64"
+
+; Function Attrs: nounwind
+define ptx_kernel void @triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4(ptr addrspace(1) %0, ptr addrspace(1) %1, ptr addrspace(1) %2, i32 %3, ptr addrspace(1) readnone captures(none) %4, ptr addrspace(1) readnone captures(none) %5) local_unnamed_addr #0 !dbg !4 {
+  %7 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !7
+  %8 = and i32 %7, 1, !dbg !7
+  %9 = zext nneg i32 %8 to i64, !dbg !8
+  %10 = getelementptr i64, ptr addrspace(1) %0, i64 %9, !dbg !8
+  %11 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09ld.global.b64 { $0 }, [ $1 + 0 ];", "=l,l"(ptr addrspace(1) %10) #4, !dbg !9
+  %12 = getelementptr i64, ptr addrspace(1) %1, i64 %9, !dbg !10
+  %13 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09ld.global.b64 { $0 }, [ $1 + 0 ];", "=l,l"(ptr addrspace(1) %12) #4, !dbg !11
+  %extelt.offset = lshr i64 %11, 32, !dbg !12
+  %14 = trunc nuw i64 %extelt.offset to i32, !dbg !12
+  %15 = trunc i64 %11 to i32, !dbg !12
+  %16 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %15, i32 1, i32 31), !dbg !12
+  %17 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %14, i32 1, i32 31), !dbg !12
+  %18 = insertelement <2 x i32> poison, i32 %16, i64 0, !dbg !12
+  %19 = insertelement <2 x i32> %18, i32 %17, i64 1, !dbg !12
+  %20 = bitcast <2 x i32> %19 to i64, !dbg !12
+  %21 = add i64 %11, %20, !dbg !16
+  %extelt.offset1 = lshr i64 %13, 32, !dbg !17
+  %22 = trunc nuw i64 %extelt.offset1 to i32, !dbg !17
+  %23 = trunc i64 %13 to i32, !dbg !17
+  %24 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %23, i32 1, i32 31), !dbg !17
+  %25 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %22, i32 1, i32 31), !dbg !17
+  %26 = insertelement <2 x i32> poison, i32 %24, i64 0, !dbg !17
+  %27 = insertelement <2 x i32> %26, i32 %25, i64 1, !dbg !17
+  %28 = bitcast <2 x i32> %27 to i64, !dbg !17
+  %29 = add i64 %13, %28, !dbg !19
+  %30 = sitofp i64 %21 to float, !dbg !20
+  %31 = sitofp i64 %29 to float, !dbg !21
+  %32 = icmp sgt i64 %29, 0, !dbg !22
+  %33 = select i1 %32, float %31, float 0x3EB0C6F7A0000000, !dbg !26
+  %34 = tail call float @llvm.nvvm.div.full(float %30, float %33), !dbg !27
+  %35 = and i32 %7, 63, !dbg !28
+  %36 = icmp eq i32 %35, 0, !dbg !28
+  %37 = bitcast float %34 to i32, !dbg !28
+  tail call void asm sideeffect "@$2 st.global.b32 [ $1 + 0 ], { $0 };", "r,l,b"(i32 %37, ptr addrspace(1) %2, i1 %36) #4, !dbg !28
+  ret void, !dbg !29
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef range(i32 0, 1024) i32 @llvm.nvvm.read.ptx.sreg.tid.x() #1
+
+; Function Attrs: convergent nocallback nounwind memory(inaccessiblemem: readwrite)
+declare i32 @llvm.nvvm.shfl.sync.bfly.i32(i32, i32, i32, i32) #2
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
+declare float @llvm.nvvm.div.full(float, float) #3
+
+attributes #0 = { nounwind "nvvm.reqntid"="64" }
+attributes #1 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #2 = { convergent nocallback nounwind memory(inaccessiblemem: readwrite) }
+attributes #3 = { mustprogress nocallback nofree nosync nounwind willreturn memory(none) }
+attributes #4 = { nounwind }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!2, !3}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C, file: !1, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: LineTablesOnly)
+!1 = !DIFile(filename: "corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py", directory: "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or")
+!2 = !{i32 2, !"Debug Info Version", i32 3}
+!3 = !{i32 4, !"nvvm-reflect-ftz", i32 1}
+!4 = distinct !DISubprogram(name: "triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4", linkageName: "triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4", scope: !1, file: !1, line: 18, type: !5, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0)
+!5 = !DISubroutineType(cc: DW_CC_normal, types: !6)
+!6 = !{}
+!7 = !DILocation(line: 27, column: 38, scope: !4)
+!8 = !DILocation(line: 33, column: 30, scope: !4)
+!9 = !DILocation(line: 33, column: 37, scope: !4)
+!10 = !DILocation(line: 34, column: 30, scope: !4)
+!11 = !DILocation(line: 34, column: 37, scope: !4)
+!12 = !DILocation(line: 291, column: 36, scope: !13, inlinedAt: !15)
+!13 = distinct !DILexicalBlockFile(scope: !4, file: !14, discriminator: 0)
+!14 = !DIFile(filename: "standard.py", directory: "/workspace/specforge/lib/python3.11/site-packages/triton/language")
+!15 = !DILocation(line: 36, column: 24, scope: !4)
+!16 = !DILocation(line: 261, column: 15, scope: !13, inlinedAt: !15)
+!17 = !DILocation(line: 291, column: 36, scope: !13, inlinedAt: !18)
+!18 = !DILocation(line: 38, column: 24, scope: !4)
+!19 = !DILocation(line: 261, column: 15, scope: !13, inlinedAt: !18)
+!20 = !DILocation(line: 39, column: 19, scope: !4)
+!21 = !DILocation(line: 40, column: 19, scope: !4)
+!22 = !DILocation(line: 110, column: 15, scope: !23, inlinedAt: !25)
+!23 = distinct !DILexicalBlockFile(scope: !4, file: !24, discriminator: 0)
+!24 = !DIFile(filename: "triton_helpers.py", directory: "/workspace/specforge/lib/python3.11/site-packages/torch/_inductor/runtime")
+!25 = !DILocation(line: 42, column: 41, scope: !4)
+!26 = !DILocation(line: 113, column: 29, scope: !23, inlinedAt: !25)
+!27 = !DILocation(line: 43, column: 20, scope: !4)
+!28 = !DILocation(line: 44, column: 68, scope: !4)
+!29 = !DILocation(line: 44, column: 4, scope: !4)

SpecForge-ext/cache/compiled_kernels/triton/2/5QCATXXJOHVG6NQ75K46KBBWQRORJ7QMSXCTH7GV3JOSAQPCCD4Q/triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4.ptx

@@ -0,0 +1,373 @@
+//
+// Generated by LLVM NVPTX Back-End
+//
+
+.version 8.7
+.target sm_90a
+.address_size 64
+
+	// .globl	triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4 // -- Begin function triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4
+                                        // @triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4
+.visible .entry triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4(
+	.param .u64 .ptr .global .align 1 triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4_param_0,
+	.param .u64 .ptr .global .align 1 triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4_param_1,
+	.param .u64 .ptr .global .align 1 triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4_param_2,
+	.param .u32 triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4_param_3,
+	.param .u64 .ptr .global .align 1 triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4_param_4,
+	.param .u64 .ptr .global .align 1 triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4_param_5
+)
+.reqntid 64
+{
+	.reg .pred 	%p<3>;
+	.reg .b32 	%r<16>;
+	.reg .b64 	%rd<19>;
+	.loc	1 18 0                          // corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py:18:0
+$L__func_begin0:
+	.loc	1 18 0                          // corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py:18:0
+
+// %bb.0:
+	ld.param.b64 	%rd6, [triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4_param_0];
+	ld.param.b64 	%rd7, [triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4_param_1];
+$L__tmp0:
+	.loc	1 27 38                         // corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py:27:38
+	mov.u32 	%r2, %tid.x;
+	and.b32 	%r3, %r2, 1;
+	ld.param.b64 	%rd5, [triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4_param_2];
+	.loc	1 33 30                         // corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py:33:30
+	mul.wide.u32 	%rd8, %r3, 8;
+	add.s64 	%rd2, %rd6, %rd8;
+	.loc	1 33 37                         // corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py:33:37
+	// begin inline asm
+	mov.u64 %rd1, 0x0;
+	ld.global.b64 { %rd1 }, [ %rd2 + 0 ];
+	// end inline asm
+	.loc	1 34 30                         // corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py:34:30
+	add.s64 	%rd4, %rd7, %rd8;
+	.loc	1 34 37                         // corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py:34:37
+	// begin inline asm
+	mov.u64 %rd3, 0x0;
+	ld.global.b64 { %rd3 }, [ %rd4 + 0 ];
+	// end inline asm
+$L__tmp1:
+	.loc	2 291 36                        // standard.py:291:36 @[ corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py:36:24 ]
+	mov.b64 	{_, %r4}, %rd1;
+	cvt.u32.u64 	%r5, %rd1;
+	shfl.sync.bfly.b32 	%r6, %r5, 1, 31, -1;
+	shfl.sync.bfly.b32 	%r7, %r4, 1, 31, -1;
+	cvt.u64.u32 	%rd9, %r6;
+	cvt.u64.u32 	%rd10, %r7;
+	shl.b64 	%rd11, %rd10, 32;
+	or.b64 	%rd12, %rd9, %rd11;
+	.loc	2 261 15                        // standard.py:261:15 @[ corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py:36:24 ]
+	add.s64 	%rd13, %rd1, %rd12;
+$L__tmp2:
+	.loc	2 291 36                        // standard.py:291:36 @[ corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py:38:24 ]
+	mov.b64 	{_, %r8}, %rd3;
+	cvt.u32.u64 	%r9, %rd3;
+	shfl.sync.bfly.b32 	%r10, %r9, 1, 31, -1;
+	shfl.sync.bfly.b32 	%r11, %r8, 1, 31, -1;
+	cvt.u64.u32 	%rd14, %r10;
+	cvt.u64.u32 	%rd15, %r11;
+	shl.b64 	%rd16, %rd15, 32;
+	or.b64 	%rd17, %rd14, %rd16;
+	.loc	2 261 15                        // standard.py:261:15 @[ corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py:38:24 ]
+	add.s64 	%rd18, %rd3, %rd17;
+$L__tmp3:
+	.loc	1 39 19                         // corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py:39:19
+	cvt.rn.f32.s64 	%r12, %rd13;
+	.loc	1 40 19                         // corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py:40:19
+	cvt.rn.f32.s64 	%r13, %rd18;
+$L__tmp4:
+	.loc	3 110 15                        // triton_helpers.py:110:15 @[ corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py:42:41 ]
+	setp.gt.s64 	%p2, %rd18, 0;
+	.loc	3 113 29                        // triton_helpers.py:113:29 @[ corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py:42:41 ]
+	selp.f32 	%r14, %r13, 0f358637BD, %p2;
+$L__tmp5:
+	.loc	1 43 20                         // corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py:43:20
+	div.full.f32 	%r1, %r12, %r14;
+	.loc	1 44 68                         // corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py:44:68
+	and.b32 	%r15, %r2, 63;
+	setp.eq.b32 	%p1, %r15, 0;
+	// begin inline asm
+	@%p1 st.global.b32 [ %rd5 + 0 ], { %r1 };
+	// end inline asm
+	.loc	1 44 4                          // corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py:44:4
+	ret;
+$L__tmp6:
+$L__func_end0:
+                                        // -- End function
+}
+	.file	1 "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py"
+	.file	2 "/workspace/specforge/lib/python3.11/site-packages/triton/language/standard.py"
+	.file	3 "/workspace/specforge/lib/python3.11/site-packages/torch/_inductor/runtime/triton_helpers.py"
+	.section	.debug_abbrev
+	{
+.b8 1                                   // Abbreviation Code
+.b8 17                                  // DW_TAG_compile_unit
+.b8 1                                   // DW_CHILDREN_yes
+.b8 37                                  // DW_AT_producer
+.b8 8                                   // DW_FORM_string
+.b8 19                                  // DW_AT_language
+.b8 5                                   // DW_FORM_data2
+.b8 3                                   // DW_AT_name
+.b8 8                                   // DW_FORM_string
+.b8 16                                  // DW_AT_stmt_list
+.b8 6                                   // DW_FORM_data4
+.b8 27                                  // DW_AT_comp_dir
+.b8 8                                   // DW_FORM_string
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 2                                   // Abbreviation Code
+.b8 46                                  // DW_TAG_subprogram
+.b8 0                                   // DW_CHILDREN_no
+.b8 3                                   // DW_AT_name
+.b8 8                                   // DW_FORM_string
+.b8 32                                  // DW_AT_inline
+.b8 11                                  // DW_FORM_data1
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 3                                   // Abbreviation Code
+.b8 46                                  // DW_TAG_subprogram
+.b8 1                                   // DW_CHILDREN_yes
+.b8 17                                  // DW_AT_low_pc
+.b8 1                                   // DW_FORM_addr
+.b8 18                                  // DW_AT_high_pc
+.b8 1                                   // DW_FORM_addr
+.b8 49                                  // DW_AT_abstract_origin
+.b8 19                                  // DW_FORM_ref4
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 4                                   // Abbreviation Code
+.b8 29                                  // DW_TAG_inlined_subroutine
+.b8 0                                   // DW_CHILDREN_no
+.b8 49                                  // DW_AT_abstract_origin
+.b8 19                                  // DW_FORM_ref4
+.b8 17                                  // DW_AT_low_pc
+.b8 1                                   // DW_FORM_addr
+.b8 18                                  // DW_AT_high_pc
+.b8 1                                   // DW_FORM_addr
+.b8 88                                  // DW_AT_call_file
+.b8 11                                  // DW_FORM_data1
+.b8 89                                  // DW_AT_call_line
+.b8 11                                  // DW_FORM_data1
+.b8 87                                  // DW_AT_call_column
+.b8 11                                  // DW_FORM_data1
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 0                                   // EOM(3)
+	}
+	.section	.debug_info
+	{
+.b32 284                                // Length of Unit
+.b8 2                                   // DWARF version number
+.b8 0
+.b32 .debug_abbrev                      // Offset Into Abbrev. Section
+.b8 8                                   // Address Size (in bytes)
+.b8 1                                   // Abbrev [1] 0xb:0x115 DW_TAG_compile_unit
+.b8 116                                 // DW_AT_producer
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 0
+.b8 2                                   // DW_AT_language
+.b8 0
+.b8 99                                  // DW_AT_name
+.b8 111
+.b8 114
+.b8 121
+.b8 100
+.b8 109
+.b8 50
+.b8 99
+.b8 51
+.b8 120
+.b8 120
+.b8 107
+.b8 115
+.b8 97
+.b8 99
+.b8 105
+.b8 52
+.b8 110
+.b8 116
+.b8 117
+.b8 118
+.b8 101
+.b8 54
+.b8 54
+.b8 53
+.b8 102
+.b8 106
+.b8 53
+.b8 98
+.b8 50
+.b8 51
+.b8 98
+.b8 55
+.b8 107
+.b8 116
+.b8 114
+.b8 110
+.b8 105
+.b8 110
+.b8 112
+.b8 54
+.b8 101
+.b8 111
+.b8 55
+.b8 118
+.b8 51
+.b8 54
+.b8 109
+.b8 110
+.b8 108
+.b8 109
+.b8 119
+.b8 46
+.b8 112
+.b8 121
+.b8 0
+.b32 .debug_line                        // DW_AT_stmt_list
+.b8 47                                  // DW_AT_comp_dir
+.b8 119
+.b8 111
+.b8 114
+.b8 107
+.b8 115
+.b8 112
+.b8 97
+.b8 99
+.b8 101
+.b8 47
+.b8 104
+.b8 97
+.b8 110
+.b8 114
+.b8 117
+.b8 105
+.b8 47
+.b8 83
+.b8 112
+.b8 101
+.b8 99
+.b8 70
+.b8 111
+.b8 114
+.b8 103
+.b8 101
+.b8 45
+.b8 101
+.b8 120
+.b8 116
+.b8 47
+.b8 99
+.b8 97
+.b8 99
+.b8 104
+.b8 101
+.b8 47
+.b8 99
+.b8 111
+.b8 109
+.b8 112
+.b8 105
+.b8 108
+.b8 101
+.b8 100
+.b8 95
+.b8 107
+.b8 101
+.b8 114
+.b8 110
+.b8 101
+.b8 108
+.b8 115
+.b8 47
+.b8 111
+.b8 114
+.b8 0
+.b8 2                                   // Abbrev [2] 0x8b:0x36 DW_TAG_subprogram
+.b8 116                                 // DW_AT_name
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 112
+.b8 101
+.b8 114
+.b8 95
+.b8 102
+.b8 117
+.b8 115
+.b8 101
+.b8 100
+.b8 95
+.b8 99
+.b8 108
+.b8 97
+.b8 109
+.b8 112
+.b8 95
+.b8 109
+.b8 105
+.b8 110
+.b8 95
+.b8 100
+.b8 105
+.b8 118
+.b8 95
+.b8 101
+.b8 113
+.b8 95
+.b8 109
+.b8 117
+.b8 108
+.b8 95
+.b8 115
+.b8 113
+.b8 117
+.b8 101
+.b8 101
+.b8 122
+.b8 101
+.b8 95
+.b8 115
+.b8 117
+.b8 109
+.b8 95
+.b8 52
+.b8 0
+.b8 1                                   // DW_AT_inline
+.b8 3                                   // Abbrev [3] 0xc1:0x5e DW_TAG_subprogram
+.b64 $L__func_begin0                    // DW_AT_low_pc
+.b64 $L__func_end0                      // DW_AT_high_pc
+.b32 139                                // DW_AT_abstract_origin
+.b8 4                                   // Abbrev [4] 0xd6:0x18 DW_TAG_inlined_subroutine
+.b32 139                                // DW_AT_abstract_origin
+.b64 $L__tmp1                           // DW_AT_low_pc
+.b64 $L__tmp2                           // DW_AT_high_pc
+.b8 1                                   // DW_AT_call_file
+.b8 36                                  // DW_AT_call_line
+.b8 24                                  // DW_AT_call_column
+.b8 4                                   // Abbrev [4] 0xee:0x18 DW_TAG_inlined_subroutine
+.b32 139                                // DW_AT_abstract_origin
+.b64 $L__tmp2                           // DW_AT_low_pc
+.b64 $L__tmp3                           // DW_AT_high_pc
+.b8 1                                   // DW_AT_call_file
+.b8 38                                  // DW_AT_call_line
+.b8 24                                  // DW_AT_call_column
+.b8 4                                   // Abbrev [4] 0x106:0x18 DW_TAG_inlined_subroutine
+.b32 139                                // DW_AT_abstract_origin
+.b64 $L__tmp4                           // DW_AT_low_pc
+.b64 $L__tmp5                           // DW_AT_high_pc
+.b8 1                                   // DW_AT_call_file
+.b8 42                                  // DW_AT_call_line
+.b8 41                                  // DW_AT_call_column
+.b8 0                                   // End Of Children Mark
+.b8 0                                   // End Of Children Mark
+	}
+	.section	.debug_macinfo	{	}

SpecForge-ext/cache/compiled_kernels/triton/2/5QCATXXJOHVG6NQ75K46KBBWQRORJ7QMSXCTH7GV3JOSAQPCCD4Q/triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4.source

@@ -0,0 +1,206 @@
+#loc = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":18:0)
+#loc30 = loc("/workspace/specforge/lib/python3.11/site-packages/triton/language/standard.py":285:0)
+#loc32 = loc(unknown)
+#loc35 = loc("/workspace/specforge/lib/python3.11/site-packages/triton/language/standard.py":260:0)
+#loc39 = loc("/workspace/specforge/lib/python3.11/site-packages/torch/_inductor/runtime/triton_helpers.py":109:0)
+#loc48 = loc("/workspace/specforge/lib/python3.11/site-packages/torch/_inductor/runtime/triton_helpers.py":86:0)
+#loc52 = loc("/workspace/specforge/lib/python3.11/site-packages/torch/_inductor/runtime/triton_helpers.py":63:0)
+#loc61 = loc("in_ptr0"(#loc))
+#loc62 = loc("in_ptr1"(#loc))
+#loc63 = loc("out_ptr2"(#loc))
+#loc64 = loc("r0_numel"(#loc))
+#loc90 = loc("input"(#loc30))
+#loc91 = loc("a"(#loc35))
+#loc92 = loc("b"(#loc35))
+#loc93 = loc("a"(#loc39))
+#loc94 = loc("b"(#loc39))
+#loc98 = loc("x"(#loc48))
+#loc99 = loc("x"(#loc52))
+module {
+  tt.func public @triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4(%in_ptr0: !tt.ptr<i64> {tt.divisibility = 16 : i32} loc("in_ptr0"(#loc)), %in_ptr1: !tt.ptr<i64> {tt.divisibility = 16 : i32} loc("in_ptr1"(#loc)), %out_ptr2: !tt.ptr<f32> {tt.divisibility = 16 : i32} loc("out_ptr2"(#loc)), %r0_numel: i32 loc("r0_numel"(#loc))) attributes {noinline = false} {
+    %xnumel = arith.constant 1 : i32 loc(#loc65)
+    %r0_numel_0 = arith.constant 2 : i32 loc(#loc66)
+    %xoffset = tt.get_program_id x : i32 loc(#loc67)
+    %xoffset_1 = arith.constant 1 : i32 loc(#loc68)
+    %xoffset_2 = arith.constant 1 : i32 loc(#loc68)
+    %xoffset_3 = arith.muli %xoffset, %xoffset_2 : i32 loc(#loc68)
+    %xindex = tt.make_range {end = 1 : i32, start = 0 : i32} : tensor<1xi32> loc(#loc69)
+    %xindex_4 = tt.expand_dims %xindex {axis = 1 : i32} : tensor<1xi32> -> tensor<1x1xi32> loc(#loc70)
+    %xindex_5 = tt.splat %xoffset_3 : i32 -> tensor<1x1xi32> loc(#loc71)
+    %xindex_6 = arith.addi %xindex_5, %xindex_4 : tensor<1x1xi32> loc(#loc71)
+    %xmask = arith.constant true loc(#loc72)
+    %xmask_7 = arith.constant dense<true> : tensor<1x2xi1> loc(#loc72)
+    %r0_index = tt.make_range {end = 2 : i32, start = 0 : i32} : tensor<2xi32> loc(#loc73)
+    %r0_index_8 = tt.expand_dims %r0_index {axis = 0 : i32} : tensor<2xi32> -> tensor<1x2xi32> loc(#loc74)
+    %r0_offset = arith.constant 0 : i32 loc(#loc75)
+    %r0_mask = arith.constant true loc(#loc76)
+    %r0_mask_9 = arith.constant dense<true> : tensor<1x2xi1> loc(#loc76)
+    %tmp0 = tt.splat %in_ptr0 : !tt.ptr<i64> -> tensor<1x2x!tt.ptr<i64>> loc(#loc77)
+    %tmp0_10 = tt.addptr %tmp0, %r0_index_8 : tensor<1x2x!tt.ptr<i64>>, tensor<1x2xi32> loc(#loc77)
+    %tmp0_11 = tt.load %tmp0_10 : tensor<1x2x!tt.ptr<i64>> loc(#loc78)
+    %tmp4 = tt.splat %in_ptr1 : !tt.ptr<i64> -> tensor<1x2x!tt.ptr<i64>> loc(#loc79)
+    %tmp4_12 = tt.addptr %tmp4, %r0_index_8 : tensor<1x2x!tt.ptr<i64>>, tensor<1x2xi32> loc(#loc79)
+    %tmp4_13 = tt.load %tmp4_12 : tensor<1x2x!tt.ptr<i64>> loc(#loc80)
+    %tmp3 = tt.call @"triton.language.standard.sum__i64S1_2S__(1,)cconstexpr_1__(2,)cconstexpr_False__(3,)cNone"(%tmp0_11) : (tensor<1x2xi64>) -> tensor<1xi64> loc(#loc81)
+    %tmp3_14 = tt.expand_dims %tmp3 {axis = 1 : i32} : tensor<1xi64> -> tensor<1x1xi64> loc(#loc82)
+    %tmp7 = tt.call @"triton.language.standard.sum__i64S1_2S__(1,)cconstexpr_1__(2,)cconstexpr_False__(3,)cNone"(%tmp4_13) : (tensor<1x2xi64>) -> tensor<1xi64> loc(#loc83)
+    %tmp7_15 = tt.expand_dims %tmp7 {axis = 1 : i32} : tensor<1xi64> -> tensor<1x1xi64> loc(#loc84)
+    %tmp8 = arith.sitofp %tmp3_14 : tensor<1x1xi64> to tensor<1x1xf32> loc(#loc85)
+    %tmp9 = arith.sitofp %tmp7_15 : tensor<1x1xi64> to tensor<1x1xf32> loc(#loc86)
+    %tmp10 = arith.constant 9.99999997E-7 : f32 loc(#loc87)
+    %tmp11 = tt.call @torch._inductor.runtime.triton_helpers.maximum__fp32S1_1S_fp32__(%tmp9, %tmp10) : (tensor<1x1xf32>, f32) -> tensor<1x1xf32> loc(#loc88)
+    %tmp12 = arith.divf %tmp8, %tmp11 : tensor<1x1xf32> loc(#loc89)
+    %c0_i32 = arith.constant 0 : i32 loc(#loc26)
+    %cst = arith.constant dense<0> : tensor<1x1xi32> loc(#loc26)
+    %0 = tt.splat %out_ptr2 : !tt.ptr<f32> -> tensor<1x1x!tt.ptr<f32>> loc(#loc27)
+    %1 = tt.addptr %0, %cst : tensor<1x1x!tt.ptr<f32>>, tensor<1x1xi32> loc(#loc27)
+    tt.store %1, %tmp12 : tensor<1x1x!tt.ptr<f32>> loc(#loc28)
+    tt.return loc(#loc29)
+  } loc(#loc)
+  tt.func private @"triton.language.standard.sum__i64S1_2S__(1,)cconstexpr_1__(2,)cconstexpr_False__(3,)cNone"(%input: tensor<1x2xi64> loc("input"(#loc30))) -> tensor<1xi64> attributes {noinline = false} {
+    %0 = "tt.reduce"(%input) <{axis = 1 : i32}> ({
+    ^bb0(%arg1: i64 loc(unknown), %arg2: i64 loc(unknown)):
+      %2 = tt.call @triton.language.standard._sum_combine__i64_i64__(%arg1, %arg2) : (i64, i64) -> i64 loc(#loc31)
+      tt.reduce.return %2 : i64 loc(#loc31)
+    }) : (tensor<1x2xi64>) -> tensor<1xi64> loc(#loc31)
+    tt.return %0 : tensor<1xi64> loc(#loc33)
+  ^bb1:  // no predecessors
+    %1 = ub.poison : tensor<1xi64> loc(#loc34)
+    tt.return %1 : tensor<1xi64> loc(#loc34)
+  } loc(#loc30)
+  tt.func private @triton.language.standard._sum_combine__i64_i64__(%a: i64 loc("a"(#loc35)), %b: i64 loc("b"(#loc35))) -> i64 attributes {noinline = false} {
+    %0 = arith.addi %a, %b : i64 loc(#loc36)
+    tt.return %0 : i64 loc(#loc37)
+  ^bb1:  // no predecessors
+    %1 = ub.poison : i64 loc(#loc38)
+    tt.return %1 : i64 loc(#loc38)
+  } loc(#loc35)
+  tt.func private @torch._inductor.runtime.triton_helpers.maximum__fp32S1_1S_fp32__(%a: tensor<1x1xf32> loc("a"(#loc39)), %b: f32 loc("b"(#loc39))) -> tensor<1x1xf32> attributes {noinline = false} {
+    %mask = tt.splat %b : f32 -> tensor<1x1xf32> loc(#loc95)
+    %mask_0 = arith.cmpf ogt, %a, %mask : tensor<1x1xf32> loc(#loc100)
+    %0 = tt.call @torch._inductor.runtime.triton_helpers.is_floating__fp32S1_1S__(%a) : (tensor<1x1xf32>) -> i1 loc(#loc41)
+    %1 = scf.if %0 -> (tensor<1x1xi1>) {
+      %mask_1 = arith.cmpf une, %a, %a : tensor<1x1xf32> loc(#loc96)
+      %mask_2 = arith.ori %mask_0, %mask_1 : tensor<1x1xi1> loc(#loc101)
+      scf.yield %mask_2 : tensor<1x1xi1> loc(#loc101)
+    } else {
+      scf.yield %mask_0 : tensor<1x1xi1> loc(#loc32)
+    } loc(#loc42)
+    %2 = tt.splat %b : f32 -> tensor<1x1xf32> loc(#loc45)
+    %3 = arith.select %1, %a, %2 : tensor<1x1xi1>, tensor<1x1xf32> loc(#loc45)
+    tt.return %3 : tensor<1x1xf32> loc(#loc46)
+  ^bb1:  // no predecessors
+    %4 = ub.poison : tensor<1x1xf32> loc(#loc47)
+    tt.return %4 : tensor<1x1xf32> loc(#loc47)
+  } loc(#loc39)
+  tt.func private @torch._inductor.runtime.triton_helpers.is_floating__fp32S1_1S__(%x: tensor<1x1xf32> loc("x"(#loc48))) -> i1 attributes {noinline = false} {
+    %0 = tt.call @torch._inductor.runtime.triton_helpers.promote_to_tensor__fp32S1_1S__(%x) : (tensor<1x1xf32>) -> tensor<1x1xf32> loc(#loc49)
+    %true = arith.constant true loc(#loc50)
+    tt.return %true : i1 loc(#loc50)
+  ^bb1:  // no predecessors
+    %1 = ub.poison : i1 loc(#loc51)
+    tt.return %1 : i1 loc(#loc51)
+  } loc(#loc48)
+  tt.func private @torch._inductor.runtime.triton_helpers.promote_to_tensor__fp32S1_1S__(%x: tensor<1x1xf32> loc("x"(#loc52))) -> tensor<1x1xf32> attributes {noinline = false} {
+    %0 = tt.call @"triton.language.standard.zeros____(0, 0)cconstexpr_1__(1,)cconstexpr_int1_"() : () -> tensor<1xi1> loc(#loc53)
+    %1 = arith.uitofp %0 : tensor<1xi1> to tensor<1xf32> loc(#loc54)
+    %2 = tt.expand_dims %1 {axis = 0 : i32} : tensor<1xf32> -> tensor<1x1xf32> loc(#loc54)
+    %3 = arith.addf %x, %2 : tensor<1x1xf32> loc(#loc54)
+    tt.return %3 : tensor<1x1xf32> loc(#loc55)
+  ^bb1:  // no predecessors
+    %4 = ub.poison : tensor<1x1xf32> loc(#loc56)
+    tt.return %4 : tensor<1x1xf32> loc(#loc56)
+  } loc(#loc52)
+  tt.func private @"triton.language.standard.zeros____(0, 0)cconstexpr_1__(1,)cconstexpr_int1_"() -> tensor<1xi1> attributes {noinline = false} {
+    %false = arith.constant false loc(#loc58)
+    %cst = arith.constant dense<false> : tensor<1xi1> loc(#loc58)
+    tt.return %cst : tensor<1xi1> loc(#loc59)
+  ^bb1:  // no predecessors
+    %0 = ub.poison : tensor<1xi1> loc(#loc60)
+    tt.return %0 : tensor<1xi1> loc(#loc60)
+  } loc(#loc57)
+} loc(#loc)
+#loc1 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":19:13)
+#loc2 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":20:15)
+#loc3 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":24:28)
+#loc4 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":24:33)
+#loc5 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":25:36)
+#loc6 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":25:44)
+#loc7 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":25:23)
+#loc8 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":26:46)
+#loc9 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":27:28)
+#loc10 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":27:38)
+#loc11 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":28:16)
+#loc12 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":29:48)
+#loc13 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":33:30)
+#loc14 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":33:37)
+#loc15 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":34:30)
+#loc16 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":34:37)
+#loc17 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":36:24)
+#loc18 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":36:27)
+#loc19 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":38:24)
+#loc20 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":38:27)
+#loc21 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":39:19)
+#loc22 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":40:19)
+#loc23 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":41:12)
+#loc24 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":42:41)
+#loc25 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":43:20)
+#loc26 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":44:49)
+#loc27 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":44:25)
+#loc28 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":44:68)
+#loc29 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":44:4)
+#loc31 = loc("/workspace/specforge/lib/python3.11/site-packages/triton/language/standard.py":291:36)
+#loc33 = loc("/workspace/specforge/lib/python3.11/site-packages/triton/language/standard.py":291:11)
+#loc34 = loc("/workspace/specforge/lib/python3.11/site-packages/triton/language/standard.py":291:4)
+#loc36 = loc("/workspace/specforge/lib/python3.11/site-packages/triton/language/standard.py":261:15)
+#loc37 = loc("/workspace/specforge/lib/python3.11/site-packages/triton/language/standard.py":261:11)
+#loc38 = loc("/workspace/specforge/lib/python3.11/site-packages/triton/language/standard.py":261:4)
+#loc40 = loc("/workspace/specforge/lib/python3.11/site-packages/torch/_inductor/runtime/triton_helpers.py":110:15)
+#loc41 = loc("/workspace/specforge/lib/python3.11/site-packages/torch/_inductor/runtime/triton_helpers.py":111:19)
+#loc42 = loc("/workspace/specforge/lib/python3.11/site-packages/torch/_inductor/runtime/triton_helpers.py":111:7)
+#loc43 = loc("/workspace/specforge/lib/python3.11/site-packages/torch/_inductor/runtime/triton_helpers.py":112:21)
+#loc44 = loc("/workspace/specforge/lib/python3.11/site-packages/torch/_inductor/runtime/triton_helpers.py":112:16)
+#loc45 = loc("/workspace/specforge/lib/python3.11/site-packages/torch/_inductor/runtime/triton_helpers.py":113:29)
+#loc46 = loc("/workspace/specforge/lib/python3.11/site-packages/torch/_inductor/runtime/triton_helpers.py":113:11)
+#loc47 = loc("/workspace/specforge/lib/python3.11/site-packages/torch/_inductor/runtime/triton_helpers.py":113:4)
+#loc49 = loc("/workspace/specforge/lib/python3.11/site-packages/torch/_inductor/runtime/triton_helpers.py":87:29)
+#loc50 = loc("/workspace/specforge/lib/python3.11/site-packages/torch/_inductor/runtime/triton_helpers.py":87:11)
+#loc51 = loc("/workspace/specforge/lib/python3.11/site-packages/torch/_inductor/runtime/triton_helpers.py":87:4)
+#loc53 = loc("/workspace/specforge/lib/python3.11/site-packages/torch/_inductor/runtime/triton_helpers.py":65:30)
+#loc54 = loc("/workspace/specforge/lib/python3.11/site-packages/torch/_inductor/runtime/triton_helpers.py":65:15)
+#loc55 = loc("/workspace/specforge/lib/python3.11/site-packages/torch/_inductor/runtime/triton_helpers.py":65:11)
+#loc56 = loc("/workspace/specforge/lib/python3.11/site-packages/torch/_inductor/runtime/triton_helpers.py":65:4)
+#loc57 = loc("/workspace/specforge/lib/python3.11/site-packages/triton/language/standard.py":118:0)
+#loc58 = loc("/workspace/specforge/lib/python3.11/site-packages/triton/language/standard.py":127:31)
+#loc59 = loc("/workspace/specforge/lib/python3.11/site-packages/triton/language/standard.py":127:11)
+#loc60 = loc("/workspace/specforge/lib/python3.11/site-packages/triton/language/standard.py":127:4)
+#loc65 = loc("xnumel"(#loc1))
+#loc66 = loc("r0_numel"(#loc2))
+#loc67 = loc("xoffset"(#loc3))
+#loc68 = loc("xoffset"(#loc4))
+#loc69 = loc("xindex"(#loc5))
+#loc70 = loc("xindex"(#loc6))
+#loc71 = loc("xindex"(#loc7))
+#loc72 = loc("xmask"(#loc8))
+#loc73 = loc("r0_index"(#loc9))
+#loc74 = loc("r0_index"(#loc10))
+#loc75 = loc("r0_offset"(#loc11))
+#loc76 = loc("r0_mask"(#loc12))
+#loc77 = loc("tmp0"(#loc13))
+#loc78 = loc("tmp0"(#loc14))
+#loc79 = loc("tmp4"(#loc15))
+#loc80 = loc("tmp4"(#loc16))
+#loc81 = loc("tmp3"(#loc17))
+#loc82 = loc("tmp3"(#loc18))
+#loc83 = loc("tmp7"(#loc19))
+#loc84 = loc("tmp7"(#loc20))
+#loc85 = loc("tmp8"(#loc21))
+#loc86 = loc("tmp9"(#loc22))
+#loc87 = loc("tmp10"(#loc23))
+#loc88 = loc("tmp11"(#loc24))
+#loc89 = loc("tmp12"(#loc25))
+#loc95 = loc("mask"(#loc40))
+#loc96 = loc("mask"(#loc43))
+#loc97 = loc("mask"(#loc44))
+#loc100 = loc("mask"(#loc95))
+#loc101 = loc("mask"(#loc97))

SpecForge-ext/cache/compiled_kernels/triton/2/5QCATXXJOHVG6NQ75K46KBBWQRORJ7QMSXCTH7GV3JOSAQPCCD4Q/triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4.ttgir

@@ -0,0 +1,91 @@
+#blocked = #ttg.blocked<{sizePerThread = [1, 1], threadsPerWarp = [1, 32], warpsPerCTA = [1, 2], order = [0, 1]}>
+#loc = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":18:0)
+#loc1 = loc(unknown)
+#loc8 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":36:24)
+#loc11 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":38:24)
+#loc23 = loc("in_ptr0"(#loc))
+#loc24 = loc("in_ptr1"(#loc))
+#loc25 = loc("out_ptr2"(#loc))
+#loc26 = loc("r0_numel"(#loc))
+#loc32 = loc("tmp3"(#loc8))
+#loc34 = loc("tmp7"(#loc11))
+#loc44 = loc(callsite(#loc1 at #loc32))
+#loc46 = loc(callsite(#loc1 at #loc34))
+module attributes {"ttg.num-ctas" = 1 : i32, "ttg.num-warps" = 2 : i32, ttg.target = "cuda:90", "ttg.threads-per-warp" = 32 : i32} {
+  tt.func public @triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4(%in_ptr0: !tt.ptr<i64> {tt.divisibility = 16 : i32} loc("in_ptr0"(#loc)), %in_ptr1: !tt.ptr<i64> {tt.divisibility = 16 : i32} loc("in_ptr1"(#loc)), %out_ptr2: !tt.ptr<f32> {tt.divisibility = 16 : i32} loc("out_ptr2"(#loc)), %r0_numel: i32 loc("r0_numel"(#loc))) attributes {noinline = false} {
+    %cst = arith.constant dense<9.99999997E-7> : tensor<1x1xf32, #blocked> loc(#loc1)
+    %r0_index = tt.make_range {end = 2 : i32, start = 0 : i32} : tensor<2xi32, #ttg.slice<{dim = 0, parent = #blocked}>> loc(#loc27)
+    %r0_index_0 = tt.expand_dims %r0_index {axis = 0 : i32} : tensor<2xi32, #ttg.slice<{dim = 0, parent = #blocked}>> -> tensor<1x2xi32, #blocked> loc(#loc27)
+    %tmp0 = tt.splat %in_ptr0 : !tt.ptr<i64> -> tensor<1x2x!tt.ptr<i64>, #blocked> loc(#loc28)
+    %tmp0_1 = tt.addptr %tmp0, %r0_index_0 : tensor<1x2x!tt.ptr<i64>, #blocked>, tensor<1x2xi32, #blocked> loc(#loc28)
+    %tmp0_2 = tt.load %tmp0_1 : tensor<1x2x!tt.ptr<i64>, #blocked> loc(#loc29)
+    %tmp4 = tt.splat %in_ptr1 : !tt.ptr<i64> -> tensor<1x2x!tt.ptr<i64>, #blocked> loc(#loc30)
+    %tmp4_3 = tt.addptr %tmp4, %r0_index_0 : tensor<1x2x!tt.ptr<i64>, #blocked>, tensor<1x2xi32, #blocked> loc(#loc30)
+    %tmp4_4 = tt.load %tmp4_3 : tensor<1x2x!tt.ptr<i64>, #blocked> loc(#loc31)
+    %tmp3 = "tt.reduce"(%tmp0_2) <{axis = 1 : i32}> ({
+    ^bb0(%tmp3_9: i64 loc(callsite(#loc1 at #loc32)), %tmp3_10: i64 loc(callsite(#loc1 at #loc32))):
+      %tmp3_11 = arith.addi %tmp3_9, %tmp3_10 : i64 loc(#loc51)
+      tt.reduce.return %tmp3_11 : i64 loc(#loc43)
+    }) : (tensor<1x2xi64, #blocked>) -> tensor<1xi64, #ttg.slice<{dim = 1, parent = #blocked}>> loc(#loc43)
+    %tmp3_5 = tt.expand_dims %tmp3 {axis = 1 : i32} : tensor<1xi64, #ttg.slice<{dim = 1, parent = #blocked}>> -> tensor<1x1xi64, #blocked> loc(#loc33)
+    %tmp7 = "tt.reduce"(%tmp4_4) <{axis = 1 : i32}> ({
+    ^bb0(%tmp7_9: i64 loc(callsite(#loc1 at #loc34)), %tmp7_10: i64 loc(callsite(#loc1 at #loc34))):
+      %tmp7_11 = arith.addi %tmp7_9, %tmp7_10 : i64 loc(#loc52)
+      tt.reduce.return %tmp7_11 : i64 loc(#loc45)
+    }) : (tensor<1x2xi64, #blocked>) -> tensor<1xi64, #ttg.slice<{dim = 1, parent = #blocked}>> loc(#loc45)
+    %tmp7_6 = tt.expand_dims %tmp7 {axis = 1 : i32} : tensor<1xi64, #ttg.slice<{dim = 1, parent = #blocked}>> -> tensor<1x1xi64, #blocked> loc(#loc35)
+    %tmp8 = arith.sitofp %tmp3_5 : tensor<1x1xi64, #blocked> to tensor<1x1xf32, #blocked> loc(#loc36)
+    %tmp9 = arith.sitofp %tmp7_6 : tensor<1x1xi64, #blocked> to tensor<1x1xf32, #blocked> loc(#loc37)
+    %mask = arith.cmpf ogt, %tmp9, %cst : tensor<1x1xf32, #blocked> loc(#loc53)
+    %mask_7 = arith.cmpf une, %tmp9, %tmp9 : tensor<1x1xf32, #blocked> loc(#loc48)
+    %mask_8 = arith.ori %mask, %mask_7 : tensor<1x1xi1, #blocked> loc(#loc54)
+    %tmp11 = arith.select %mask_8, %tmp9, %cst : tensor<1x1xi1, #blocked>, tensor<1x1xf32, #blocked> loc(#loc50)
+    %tmp12 = arith.divf %tmp8, %tmp11 : tensor<1x1xf32, #blocked> loc(#loc42)
+    %0 = tt.splat %out_ptr2 : !tt.ptr<f32> -> tensor<1x1x!tt.ptr<f32>, #blocked> loc(#loc21)
+    tt.store %0, %tmp12 : tensor<1x1x!tt.ptr<f32>, #blocked> loc(#loc21)
+    tt.return loc(#loc22)
+  } loc(#loc)
+} loc(#loc)
+#loc2 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":27:38)
+#loc3 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":33:30)
+#loc4 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":33:37)
+#loc5 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":34:30)
+#loc6 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":34:37)
+#loc7 = loc("/workspace/specforge/lib/python3.11/site-packages/triton/language/standard.py":291:36)
+#loc9 = loc("/workspace/specforge/lib/python3.11/site-packages/triton/language/standard.py":261:15)
+#loc10 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":36:27)
+#loc12 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":38:27)
+#loc13 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":39:19)
+#loc14 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":40:19)
+#loc15 = loc("/workspace/specforge/lib/python3.11/site-packages/torch/_inductor/runtime/triton_helpers.py":110:15)
+#loc16 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":42:41)
+#loc17 = loc("/workspace/specforge/lib/python3.11/site-packages/torch/_inductor/runtime/triton_helpers.py":112:21)
+#loc18 = loc("/workspace/specforge/lib/python3.11/site-packages/torch/_inductor/runtime/triton_helpers.py":112:16)
+#loc19 = loc("/workspace/specforge/lib/python3.11/site-packages/torch/_inductor/runtime/triton_helpers.py":113:29)
+#loc20 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":43:20)
+#loc21 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":44:68)
+#loc22 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":44:4)
+#loc27 = loc("r0_index"(#loc2))
+#loc28 = loc("tmp0"(#loc3))
+#loc29 = loc("tmp0"(#loc4))
+#loc30 = loc("tmp4"(#loc5))
+#loc31 = loc("tmp4"(#loc6))
+#loc33 = loc("tmp3"(#loc10))
+#loc35 = loc("tmp7"(#loc12))
+#loc36 = loc("tmp8"(#loc13))
+#loc37 = loc("tmp9"(#loc14))
+#loc38 = loc("mask"(#loc15))
+#loc39 = loc("tmp11"(#loc16))
+#loc40 = loc("mask"(#loc17))
+#loc41 = loc("mask"(#loc18))
+#loc42 = loc("tmp12"(#loc20))
+#loc43 = loc(callsite(#loc7 at #loc32))
+#loc45 = loc(callsite(#loc7 at #loc34))
+#loc47 = loc("mask"(#loc38))
+#loc48 = loc(callsite(#loc40 at #loc39))
+#loc49 = loc("mask"(#loc41))
+#loc50 = loc(callsite(#loc19 at #loc39))
+#loc51 = loc(callsite(#loc9 at #loc43))
+#loc52 = loc(callsite(#loc9 at #loc45))
+#loc53 = loc(callsite(#loc47 at #loc39))
+#loc54 = loc(callsite(#loc49 at #loc39))

SpecForge-ext/cache/compiled_kernels/triton/2/5QCATXXJOHVG6NQ75K46KBBWQRORJ7QMSXCTH7GV3JOSAQPCCD4Q/triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4.ttir

@@ -0,0 +1,93 @@
+#loc = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":18:0)
+#loc1 = loc(unknown)
+#loc9 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":36:24)
+#loc12 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":38:24)
+#loc25 = loc("in_ptr0"(#loc))
+#loc26 = loc("in_ptr1"(#loc))
+#loc27 = loc("out_ptr2"(#loc))
+#loc28 = loc("r0_numel"(#loc))
+#loc35 = loc("tmp3"(#loc9))
+#loc37 = loc("tmp7"(#loc12))
+#loc47 = loc(callsite(#loc1 at #loc35))
+#loc49 = loc(callsite(#loc1 at #loc37))
+module {
+  tt.func public @triton_per_fused_clamp_min_div_eq_mul_squeeze_sum_4(%in_ptr0: !tt.ptr<i64> {tt.divisibility = 16 : i32} loc("in_ptr0"(#loc)), %in_ptr1: !tt.ptr<i64> {tt.divisibility = 16 : i32} loc("in_ptr1"(#loc)), %out_ptr2: !tt.ptr<f32> {tt.divisibility = 16 : i32} loc("out_ptr2"(#loc)), %r0_numel: i32 loc("r0_numel"(#loc))) attributes {noinline = false} {
+    %cst = arith.constant dense<9.99999997E-7> : tensor<1x1xf32> loc(#loc1)
+    %r0_index = tt.make_range {end = 2 : i32, start = 0 : i32} : tensor<2xi32> loc(#loc29)
+    %r0_index_0 = tt.expand_dims %r0_index {axis = 0 : i32} : tensor<2xi32> -> tensor<1x2xi32> loc(#loc30)
+    %tmp0 = tt.splat %in_ptr0 : !tt.ptr<i64> -> tensor<1x2x!tt.ptr<i64>> loc(#loc31)
+    %tmp0_1 = tt.addptr %tmp0, %r0_index_0 : tensor<1x2x!tt.ptr<i64>>, tensor<1x2xi32> loc(#loc31)
+    %tmp0_2 = tt.load %tmp0_1 : tensor<1x2x!tt.ptr<i64>> loc(#loc32)
+    %tmp4 = tt.splat %in_ptr1 : !tt.ptr<i64> -> tensor<1x2x!tt.ptr<i64>> loc(#loc33)
+    %tmp4_3 = tt.addptr %tmp4, %r0_index_0 : tensor<1x2x!tt.ptr<i64>>, tensor<1x2xi32> loc(#loc33)
+    %tmp4_4 = tt.load %tmp4_3 : tensor<1x2x!tt.ptr<i64>> loc(#loc34)
+    %tmp3 = "tt.reduce"(%tmp0_2) <{axis = 1 : i32}> ({
+    ^bb0(%tmp3_9: i64 loc(callsite(#loc1 at #loc35)), %tmp3_10: i64 loc(callsite(#loc1 at #loc35))):
+      %tmp3_11 = arith.addi %tmp3_9, %tmp3_10 : i64 loc(#loc54)
+      tt.reduce.return %tmp3_11 : i64 loc(#loc46)
+    }) : (tensor<1x2xi64>) -> tensor<1xi64> loc(#loc46)
+    %tmp3_5 = tt.expand_dims %tmp3 {axis = 1 : i32} : tensor<1xi64> -> tensor<1x1xi64> loc(#loc36)
+    %tmp7 = "tt.reduce"(%tmp4_4) <{axis = 1 : i32}> ({
+    ^bb0(%tmp7_9: i64 loc(callsite(#loc1 at #loc37)), %tmp7_10: i64 loc(callsite(#loc1 at #loc37))):
+      %tmp7_11 = arith.addi %tmp7_9, %tmp7_10 : i64 loc(#loc55)
+      tt.reduce.return %tmp7_11 : i64 loc(#loc48)
+    }) : (tensor<1x2xi64>) -> tensor<1xi64> loc(#loc48)
+    %tmp7_6 = tt.expand_dims %tmp7 {axis = 1 : i32} : tensor<1xi64> -> tensor<1x1xi64> loc(#loc38)
+    %tmp8 = arith.sitofp %tmp3_5 : tensor<1x1xi64> to tensor<1x1xf32> loc(#loc39)
+    %tmp9 = arith.sitofp %tmp7_6 : tensor<1x1xi64> to tensor<1x1xf32> loc(#loc40)
+    %mask = arith.cmpf ogt, %tmp9, %cst : tensor<1x1xf32> loc(#loc56)
+    %mask_7 = arith.cmpf une, %tmp9, %tmp9 : tensor<1x1xf32> loc(#loc51)
+    %mask_8 = arith.ori %mask, %mask_7 : tensor<1x1xi1> loc(#loc57)
+    %tmp11 = arith.select %mask_8, %tmp9, %cst : tensor<1x1xi1>, tensor<1x1xf32> loc(#loc53)
+    %tmp12 = arith.divf %tmp8, %tmp11 : tensor<1x1xf32> loc(#loc45)
+    %0 = tt.splat %out_ptr2 : !tt.ptr<f32> -> tensor<1x1x!tt.ptr<f32>> loc(#loc22)
+    tt.store %0, %tmp12 : tensor<1x1x!tt.ptr<f32>> loc(#loc23)
+    tt.return loc(#loc24)
+  } loc(#loc)
+} loc(#loc)
+#loc2 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":27:28)
+#loc3 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":27:38)
+#loc4 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":33:30)
+#loc5 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":33:37)
+#loc6 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":34:30)
+#loc7 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":34:37)
+#loc8 = loc("/workspace/specforge/lib/python3.11/site-packages/triton/language/standard.py":291:36)
+#loc10 = loc("/workspace/specforge/lib/python3.11/site-packages/triton/language/standard.py":261:15)
+#loc11 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":36:27)
+#loc13 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":38:27)
+#loc14 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":39:19)
+#loc15 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":40:19)
+#loc16 = loc("/workspace/specforge/lib/python3.11/site-packages/torch/_inductor/runtime/triton_helpers.py":110:15)
+#loc17 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":42:41)
+#loc18 = loc("/workspace/specforge/lib/python3.11/site-packages/torch/_inductor/runtime/triton_helpers.py":112:21)
+#loc19 = loc("/workspace/specforge/lib/python3.11/site-packages/torch/_inductor/runtime/triton_helpers.py":112:16)
+#loc20 = loc("/workspace/specforge/lib/python3.11/site-packages/torch/_inductor/runtime/triton_helpers.py":113:29)
+#loc21 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":43:20)
+#loc22 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":44:25)
+#loc23 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":44:68)
+#loc24 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/or/corydm2c3xxksaci4ntuve665fj5b23b7ktrninp6eo7v36mnlmw.py":44:4)
+#loc29 = loc("r0_index"(#loc2))
+#loc30 = loc("r0_index"(#loc3))
+#loc31 = loc("tmp0"(#loc4))
+#loc32 = loc("tmp0"(#loc5))
+#loc33 = loc("tmp4"(#loc6))
+#loc34 = loc("tmp4"(#loc7))
+#loc36 = loc("tmp3"(#loc11))
+#loc38 = loc("tmp7"(#loc13))
+#loc39 = loc("tmp8"(#loc14))
+#loc40 = loc("tmp9"(#loc15))
+#loc41 = loc("mask"(#loc16))
+#loc42 = loc("tmp11"(#loc17))
+#loc43 = loc("mask"(#loc18))
+#loc44 = loc("mask"(#loc19))
+#loc45 = loc("tmp12"(#loc21))
+#loc46 = loc(callsite(#loc8 at #loc35))
+#loc48 = loc(callsite(#loc8 at #loc37))
+#loc50 = loc("mask"(#loc41))
+#loc51 = loc(callsite(#loc43 at #loc42))
+#loc52 = loc("mask"(#loc44))
+#loc53 = loc(callsite(#loc20 at #loc42))
+#loc54 = loc(callsite(#loc10 at #loc46))
+#loc55 = loc(callsite(#loc10 at #loc48))
+#loc56 = loc(callsite(#loc50 at #loc42))
+#loc57 = loc(callsite(#loc52 at #loc42))

SpecForge-ext/cache/compiled_kernels/triton/2/6FB7I6IASCIGI3DSKLBL4Q2CXFFWPYWXW7AMHNUUDLPGKUCB3PDA/__grp__triton_poi_fused_new_zeros_1.json

@@ -0,0 +1 @@
+{"child_paths": {"triton_poi_fused_new_zeros_1.source": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/6FB7I6IASCIGI3DSKLBL4Q2CXFFWPYWXW7AMHNUUDLPGKUCB3PDA/triton_poi_fused_new_zeros_1.source", "triton_poi_fused_new_zeros_1.ttir": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/6FB7I6IASCIGI3DSKLBL4Q2CXFFWPYWXW7AMHNUUDLPGKUCB3PDA/triton_poi_fused_new_zeros_1.ttir", "triton_poi_fused_new_zeros_1.ttgir": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/6FB7I6IASCIGI3DSKLBL4Q2CXFFWPYWXW7AMHNUUDLPGKUCB3PDA/triton_poi_fused_new_zeros_1.ttgir", "triton_poi_fused_new_zeros_1.llir": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/6FB7I6IASCIGI3DSKLBL4Q2CXFFWPYWXW7AMHNUUDLPGKUCB3PDA/triton_poi_fused_new_zeros_1.llir", "triton_poi_fused_new_zeros_1.ptx": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/6FB7I6IASCIGI3DSKLBL4Q2CXFFWPYWXW7AMHNUUDLPGKUCB3PDA/triton_poi_fused_new_zeros_1.ptx", "triton_poi_fused_new_zeros_1.cubin": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/6FB7I6IASCIGI3DSKLBL4Q2CXFFWPYWXW7AMHNUUDLPGKUCB3PDA/triton_poi_fused_new_zeros_1.cubin", "triton_poi_fused_new_zeros_1.json": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/6FB7I6IASCIGI3DSKLBL4Q2CXFFWPYWXW7AMHNUUDLPGKUCB3PDA/triton_poi_fused_new_zeros_1.json"}}

SpecForge-ext/cache/compiled_kernels/triton/2/6FB7I6IASCIGI3DSKLBL4Q2CXFFWPYWXW7AMHNUUDLPGKUCB3PDA/triton_poi_fused_new_zeros_1.json

@@ -0,0 +1 @@
+{"hash": "f143f479009090646c7252c2be4342b94b67e2d7b7c0c3b6941ade655041dbc6", "target": {"backend": "cuda", "arch": 90, "warp_size": 32}, "num_warps": 4, "num_ctas": 1, "num_stages": 1, "warp_size": 32, "maxnreg": null, "cluster_dims": [1, 1, 1], "ptx_version": null, "ptx_options": null, "ir_override": null, "enable_fp_fusion": true, "launch_cooperative_grid": false, "launch_pdl": false, "supported_fp8_dtypes": ["fp8e4b15", "fp8e4nv", "fp8e5"], "deprecated_fp8_dot_operand_dtypes": ["fp8e4b15"], "default_dot_input_precision": "tf32", "allowed_dot_input_precisions": ["tf32", "tf32x3", "ieee"], "max_num_imprecise_acc_default": 1073741824, "extern_libs": [["libdevice", "/workspace/specforge/lib/python3.11/site-packages/triton/backends/nvidia/lib/libdevice.10.bc"]], "debug": true, "backend_name": "cuda", "sanitize_overflow": false, "arch": "sm90", "instrumentation_mode": "", "triton_version": "3.5.1", "tensordesc_meta": [], "shared": 0, "tmem_size": 0, "global_scratch_size": 0, "global_scratch_align": 1, "profile_scratch_size": 0, "profile_scratch_align": 1, "name": "triton_poi_fused_new_zeros_1"}

SpecForge-ext/cache/compiled_kernels/triton/2/6FB7I6IASCIGI3DSKLBL4Q2CXFFWPYWXW7AMHNUUDLPGKUCB3PDA/triton_poi_fused_new_zeros_1.llir

@@ -0,0 +1,47 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+target datalayout = "e-p3:32:32-p4:32:32-p5:32:32-p6:32:32-p7:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64"
+
+; Function Attrs: nounwind
+define ptx_kernel void @triton_poi_fused_new_zeros_1(ptr addrspace(1) %0, i32 %1, ptr addrspace(1) readnone captures(none) %2, ptr addrspace(1) readnone captures(none) %3) local_unnamed_addr #0 !dbg !4 {
+  %5 = tail call i32 @llvm.nvvm.read.ptx.sreg.ctaid.x(), !dbg !7
+  %6 = shl i32 %5, 8, !dbg !8
+  %7 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !9
+  %8 = shl nuw nsw i32 %7, 1, !dbg !9
+  %9 = and i32 %8, 254, !dbg !9
+  %10 = or disjoint i32 %9, %6, !dbg !10
+  %11 = icmp slt i32 %10, 544, !dbg !11
+  %12 = sext i32 %10 to i64, !dbg !12
+  %13 = getelementptr i32, ptr addrspace(1) %0, i64 %12, !dbg !12
+  tail call void asm sideeffect "@$3 st.global.v2.b32 [ $2 + 0 ], { $0, $1 };", "r,r,l,b"(i32 0, i32 0, ptr addrspace(1) %13, i1 %11) #2, !dbg !13
+  ret void, !dbg !14
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef range(i32 0, 2147483647) i32 @llvm.nvvm.read.ptx.sreg.ctaid.x() #1
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef range(i32 0, 1024) i32 @llvm.nvvm.read.ptx.sreg.tid.x() #1
+
+attributes #0 = { nounwind "nvvm.reqntid"="128" }
+attributes #1 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #2 = { nounwind }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!2, !3}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C, file: !1, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: LineTablesOnly)
+!1 = !DIFile(filename: "ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py", directory: "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/cm")
+!2 = !{i32 2, !"Debug Info Version", i32 3}
+!3 = !{i32 4, !"nvvm-reflect-ftz", i32 1}
+!4 = distinct !DISubprogram(name: "triton_poi_fused_new_zeros_1", linkageName: "triton_poi_fused_new_zeros_1", scope: !1, file: !1, line: 18, type: !5, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0)
+!5 = !DISubroutineType(cc: DW_CC_normal, types: !6)
+!6 = !{}
+!7 = !DILocation(line: 20, column: 28, scope: !4)
+!8 = !DILocation(line: 20, column: 33, scope: !4)
+!9 = !DILocation(line: 21, column: 36, scope: !4)
+!10 = !DILocation(line: 21, column: 23, scope: !4)
+!11 = !DILocation(line: 22, column: 21, scope: !4)
+!12 = !DILocation(line: 25, column: 25, scope: !4)
+!13 = !DILocation(line: 25, column: 36, scope: !4)
+!14 = !DILocation(line: 25, column: 4, scope: !4)

SpecForge-ext/cache/compiled_kernels/triton/2/6FB7I6IASCIGI3DSKLBL4Q2CXFFWPYWXW7AMHNUUDLPGKUCB3PDA/triton_poi_fused_new_zeros_1.ptx

@@ -0,0 +1,207 @@
+//
+// Generated by LLVM NVPTX Back-End
+//
+
+.version 8.7
+.target sm_90a
+.address_size 64
+
+	// .globl	triton_poi_fused_new_zeros_1 // -- Begin function triton_poi_fused_new_zeros_1
+                                        // @triton_poi_fused_new_zeros_1
+.visible .entry triton_poi_fused_new_zeros_1(
+	.param .u64 .ptr .global .align 1 triton_poi_fused_new_zeros_1_param_0,
+	.param .u32 triton_poi_fused_new_zeros_1_param_1,
+	.param .u64 .ptr .global .align 1 triton_poi_fused_new_zeros_1_param_2,
+	.param .u64 .ptr .global .align 1 triton_poi_fused_new_zeros_1_param_3
+)
+.reqntid 128
+{
+	.reg .pred 	%p<2>;
+	.reg .b32 	%r<9>;
+	.reg .b64 	%rd<3>;
+	.loc	1 18 0                          // ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py:18:0
+$L__func_begin0:
+	.loc	1 18 0                          // ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py:18:0
+
+// %bb.0:
+	ld.param.b64 	%rd2, [triton_poi_fused_new_zeros_1_param_0];
+$L__tmp0:
+	.loc	1 20 28                         // ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py:20:28
+	mov.u32 	%r3, %ctaid.x;
+	.loc	1 20 33                         // ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py:20:33
+	shl.b32 	%r4, %r3, 8;
+	.loc	1 21 36                         // ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py:21:36
+	mov.u32 	%r5, %tid.x;
+	shl.b32 	%r6, %r5, 1;
+	and.b32 	%r7, %r6, 254;
+	.loc	1 21 23                         // ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py:21:23
+	or.b32 	%r8, %r7, %r4;
+	.loc	1 22 21                         // ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py:22:21
+	setp.lt.s32 	%p1, %r8, 544;
+	.loc	1 25 25                         // ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py:25:25
+	mad.wide.s32 	%rd1, %r8, 4, %rd2;
+	mov.b32 	%r1, 0;
+	.loc	1 25 36                         // ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py:25:36
+	// begin inline asm
+	@%p1 st.global.v2.b32 [ %rd1 + 0 ], { %r1, %r1 };
+	// end inline asm
+	.loc	1 25 4                          // ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py:25:4
+	ret;
+$L__tmp1:
+$L__func_end0:
+                                        // -- End function
+}
+	.file	1 "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/cm/ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py"
+	.section	.debug_abbrev
+	{
+.b8 1                                   // Abbreviation Code
+.b8 17                                  // DW_TAG_compile_unit
+.b8 0                                   // DW_CHILDREN_no
+.b8 37                                  // DW_AT_producer
+.b8 8                                   // DW_FORM_string
+.b8 19                                  // DW_AT_language
+.b8 5                                   // DW_FORM_data2
+.b8 3                                   // DW_AT_name
+.b8 8                                   // DW_FORM_string
+.b8 16                                  // DW_AT_stmt_list
+.b8 6                                   // DW_FORM_data4
+.b8 27                                  // DW_AT_comp_dir
+.b8 8                                   // DW_FORM_string
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 0                                   // EOM(3)
+	}
+	.section	.debug_info
+	{
+.b32 135                                // Length of Unit
+.b8 2                                   // DWARF version number
+.b8 0
+.b32 .debug_abbrev                      // Offset Into Abbrev. Section
+.b8 8                                   // Address Size (in bytes)
+.b8 1                                   // Abbrev [1] 0xb:0x80 DW_TAG_compile_unit
+.b8 116                                 // DW_AT_producer
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 0
+.b8 2                                   // DW_AT_language
+.b8 0
+.b8 99                                  // DW_AT_name
+.b8 99
+.b8 109
+.b8 113
+.b8 107
+.b8 121
+.b8 52
+.b8 109
+.b8 54
+.b8 53
+.b8 121
+.b8 105
+.b8 102
+.b8 113
+.b8 106
+.b8 109
+.b8 102
+.b8 117
+.b8 117
+.b8 55
+.b8 118
+.b8 103
+.b8 118
+.b8 112
+.b8 117
+.b8 104
+.b8 119
+.b8 112
+.b8 97
+.b8 52
+.b8 121
+.b8 98
+.b8 97
+.b8 120
+.b8 102
+.b8 102
+.b8 105
+.b8 121
+.b8 51
+.b8 109
+.b8 117
+.b8 50
+.b8 101
+.b8 54
+.b8 121
+.b8 122
+.b8 103
+.b8 101
+.b8 99
+.b8 103
+.b8 104
+.b8 101
+.b8 46
+.b8 112
+.b8 121
+.b8 0
+.b32 .debug_line                        // DW_AT_stmt_list
+.b8 47                                  // DW_AT_comp_dir
+.b8 119
+.b8 111
+.b8 114
+.b8 107
+.b8 115
+.b8 112
+.b8 97
+.b8 99
+.b8 101
+.b8 47
+.b8 104
+.b8 97
+.b8 110
+.b8 114
+.b8 117
+.b8 105
+.b8 47
+.b8 83
+.b8 112
+.b8 101
+.b8 99
+.b8 70
+.b8 111
+.b8 114
+.b8 103
+.b8 101
+.b8 45
+.b8 101
+.b8 120
+.b8 116
+.b8 47
+.b8 99
+.b8 97
+.b8 99
+.b8 104
+.b8 101
+.b8 47
+.b8 99
+.b8 111
+.b8 109
+.b8 112
+.b8 105
+.b8 108
+.b8 101
+.b8 100
+.b8 95
+.b8 107
+.b8 101
+.b8 114
+.b8 110
+.b8 101
+.b8 108
+.b8 115
+.b8 47
+.b8 99
+.b8 109
+.b8 0
+	}
+	.section	.debug_macinfo	{	}

SpecForge-ext/cache/compiled_kernels/triton/2/6FB7I6IASCIGI3DSKLBL4Q2CXFFWPYWXW7AMHNUUDLPGKUCB3PDA/triton_poi_fused_new_zeros_1.source

@@ -0,0 +1,41 @@
+#loc = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/cm/ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py":18:0)
+#loc11 = loc("out_ptr0"(#loc))
+#loc12 = loc("xnumel"(#loc))
+module {
+  tt.func public @triton_poi_fused_new_zeros_1(%out_ptr0: !tt.ptr<i32> {tt.divisibility = 16 : i32} loc("out_ptr0"(#loc)), %xnumel: i32 {tt.divisibility = 16 : i32} loc("xnumel"(#loc))) attributes {noinline = false} {
+    %xnumel_0 = arith.constant 544 : i32 loc(#loc13)
+    %xoffset = tt.get_program_id x : i32 loc(#loc14)
+    %xoffset_1 = arith.constant 256 : i32 loc(#loc15)
+    %xoffset_2 = arith.constant 256 : i32 loc(#loc15)
+    %xoffset_3 = arith.muli %xoffset, %xoffset_2 : i32 loc(#loc15)
+    %xindex = tt.make_range {end = 256 : i32, start = 0 : i32} : tensor<256xi32> loc(#loc16)
+    %xindex_4 = tt.splat %xoffset_3 : i32 -> tensor<256xi32> loc(#loc17)
+    %xindex_5 = arith.addi %xindex_4, %xindex : tensor<256xi32> loc(#loc17)
+    %xmask = arith.constant dense<544> : tensor<256xi32> loc(#loc18)
+    %xmask_6 = arith.cmpi slt, %xindex_5, %xmask : tensor<256xi32> loc(#loc18)
+    %tmp0 = arith.constant 0 : i32 loc(#loc19)
+    %tmp0_7 = arith.constant dense<0> : tensor<1xi32> loc(#loc19)
+    %0 = tt.splat %out_ptr0 : !tt.ptr<i32> -> tensor<256x!tt.ptr<i32>> loc(#loc8)
+    %1 = tt.addptr %0, %xindex_5 : tensor<256x!tt.ptr<i32>>, tensor<256xi32> loc(#loc8)
+    %cst = arith.constant dense<0> : tensor<256xi32> loc(#loc9)
+    tt.store %1, %cst, %xmask_6 : tensor<256x!tt.ptr<i32>> loc(#loc9)
+    tt.return loc(#loc10)
+  } loc(#loc)
+} loc(#loc)
+#loc1 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/cm/ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py":19:13)
+#loc2 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/cm/ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py":20:28)
+#loc3 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/cm/ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py":20:33)
+#loc4 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/cm/ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py":21:36)
+#loc5 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/cm/ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py":21:23)
+#loc6 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/cm/ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py":22:21)
+#loc7 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/cm/ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py":24:27)
+#loc8 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/cm/ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py":25:25)
+#loc9 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/cm/ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py":25:36)
+#loc10 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/cm/ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py":25:4)
+#loc13 = loc("xnumel"(#loc1))
+#loc14 = loc("xoffset"(#loc2))
+#loc15 = loc("xoffset"(#loc3))
+#loc16 = loc("xindex"(#loc4))
+#loc17 = loc("xindex"(#loc5))
+#loc18 = loc("xmask"(#loc6))
+#loc19 = loc("tmp0"(#loc7))

SpecForge-ext/cache/compiled_kernels/triton/2/6FB7I6IASCIGI3DSKLBL4Q2CXFFWPYWXW7AMHNUUDLPGKUCB3PDA/triton_poi_fused_new_zeros_1.ttgir

@@ -0,0 +1,35 @@
+#blocked = #ttg.blocked<{sizePerThread = [2], threadsPerWarp = [32], warpsPerCTA = [4], order = [0]}>
+#loc = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/cm/ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py":18:0)
+#loc10 = loc("out_ptr0"(#loc))
+#loc11 = loc("xnumel"(#loc))
+module attributes {"ttg.num-ctas" = 1 : i32, "ttg.num-warps" = 4 : i32, ttg.target = "cuda:90", "ttg.threads-per-warp" = 32 : i32} {
+  tt.func public @triton_poi_fused_new_zeros_1(%out_ptr0: !tt.ptr<i32> {tt.divisibility = 16 : i32} loc("out_ptr0"(#loc)), %xnumel: i32 {tt.divisibility = 16 : i32} loc("xnumel"(#loc))) attributes {noinline = false} {
+    %cst = arith.constant dense<544> : tensor<256xi32, #blocked> loc(#loc1)
+    %cst_0 = arith.constant dense<0> : tensor<256xi32, #blocked> loc(#loc1)
+    %c256_i32 = arith.constant 256 : i32 loc(#loc1)
+    %xoffset = tt.get_program_id x : i32 loc(#loc12)
+    %xoffset_1 = arith.muli %xoffset, %c256_i32 : i32 loc(#loc13)
+    %xindex = tt.make_range {end = 256 : i32, start = 0 : i32} : tensor<256xi32, #blocked> loc(#loc14)
+    %xindex_2 = tt.splat %xoffset_1 : i32 -> tensor<256xi32, #blocked> loc(#loc15)
+    %xindex_3 = arith.addi %xindex_2, %xindex : tensor<256xi32, #blocked> loc(#loc15)
+    %xmask = arith.cmpi slt, %xindex_3, %cst : tensor<256xi32, #blocked> loc(#loc16)
+    %0 = tt.splat %out_ptr0 : !tt.ptr<i32> -> tensor<256x!tt.ptr<i32>, #blocked> loc(#loc7)
+    %1 = tt.addptr %0, %xindex_3 : tensor<256x!tt.ptr<i32>, #blocked>, tensor<256xi32, #blocked> loc(#loc7)
+    tt.store %1, %cst_0, %xmask : tensor<256x!tt.ptr<i32>, #blocked> loc(#loc8)
+    tt.return loc(#loc9)
+  } loc(#loc)
+} loc(#loc)
+#loc1 = loc(unknown)
+#loc2 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/cm/ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py":20:28)
+#loc3 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/cm/ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py":20:33)
+#loc4 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/cm/ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py":21:36)
+#loc5 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/cm/ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py":21:23)
+#loc6 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/cm/ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py":22:21)
+#loc7 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/cm/ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py":25:25)
+#loc8 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/cm/ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py":25:36)
+#loc9 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/cm/ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py":25:4)
+#loc12 = loc("xoffset"(#loc2))
+#loc13 = loc("xoffset"(#loc3))
+#loc14 = loc("xindex"(#loc4))
+#loc15 = loc("xindex"(#loc5))
+#loc16 = loc("xmask"(#loc6))

SpecForge-ext/cache/compiled_kernels/triton/2/6FB7I6IASCIGI3DSKLBL4Q2CXFFWPYWXW7AMHNUUDLPGKUCB3PDA/triton_poi_fused_new_zeros_1.ttir

@@ -0,0 +1,34 @@
+#loc = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/cm/ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py":18:0)
+#loc10 = loc("out_ptr0"(#loc))
+#loc11 = loc("xnumel"(#loc))
+module {
+  tt.func public @triton_poi_fused_new_zeros_1(%out_ptr0: !tt.ptr<i32> {tt.divisibility = 16 : i32} loc("out_ptr0"(#loc)), %xnumel: i32 {tt.divisibility = 16 : i32} loc("xnumel"(#loc))) attributes {noinline = false} {
+    %cst = arith.constant dense<0> : tensor<256xi32> loc(#loc1)
+    %xmask = arith.constant dense<544> : tensor<256xi32> loc(#loc12)
+    %c256_i32 = arith.constant 256 : i32 loc(#loc3)
+    %xoffset = tt.get_program_id x : i32 loc(#loc13)
+    %xoffset_0 = arith.muli %xoffset, %c256_i32 : i32 loc(#loc14)
+    %xindex = tt.make_range {end = 256 : i32, start = 0 : i32} : tensor<256xi32> loc(#loc15)
+    %xindex_1 = tt.splat %xoffset_0 : i32 -> tensor<256xi32> loc(#loc16)
+    %xindex_2 = arith.addi %xindex_1, %xindex : tensor<256xi32> loc(#loc16)
+    %xmask_3 = arith.cmpi slt, %xindex_2, %xmask : tensor<256xi32> loc(#loc12)
+    %0 = tt.splat %out_ptr0 : !tt.ptr<i32> -> tensor<256x!tt.ptr<i32>> loc(#loc8)
+    %1 = tt.addptr %0, %xindex_2 : tensor<256x!tt.ptr<i32>>, tensor<256xi32> loc(#loc8)
+    tt.store %1, %cst, %xmask_3 : tensor<256x!tt.ptr<i32>> loc(#loc1)
+    tt.return loc(#loc9)
+  } loc(#loc)
+} loc(#loc)
+#loc1 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/cm/ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py":25:36)
+#loc2 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/cm/ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py":22:21)
+#loc3 = loc(unknown)
+#loc4 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/cm/ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py":20:28)
+#loc5 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/cm/ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py":20:33)
+#loc6 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/cm/ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py":21:36)
+#loc7 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/cm/ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py":21:23)
+#loc8 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/cm/ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py":25:25)
+#loc9 = loc("/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/cm/ccmqky4m65yifqjmfuu7vgvpuhwpa4ybaxffiy3mu2e6yzgecghe.py":25:4)
+#loc12 = loc("xmask"(#loc2))
+#loc13 = loc("xoffset"(#loc4))
+#loc14 = loc("xoffset"(#loc5))
+#loc15 = loc("xindex"(#loc6))
+#loc16 = loc("xindex"(#loc7))

SpecForge-ext/cache/compiled_kernels/triton/2/7Y3WXJA5F4C76K5XYE6DPME3QXZYZM2B2JXSRQ4JEXGQ6AZL2CMA/__grp__triton_red_fused__to_copy_arange_index_put_lt_new_zeros_scalar_tensor_sum_unsqueeze_view_where_2.json

@@ -0,0 +1 @@
+{"child_paths": {"triton_red_fused__to_copy_arange_index_put_lt_new_zeros_scalar_tensor_sum_unsqueeze_view_where_2.source": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/7Y3WXJA5F4C76K5XYE6DPME3QXZYZM2B2JXSRQ4JEXGQ6AZL2CMA/triton_red_fused__to_copy_arange_index_put_lt_new_zeros_scalar_tensor_sum_unsqueeze_view_where_2.source", "triton_red_fused__to_copy_arange_index_put_lt_new_zeros_scalar_tensor_sum_unsqueeze_view_where_2.ttir": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/7Y3WXJA5F4C76K5XYE6DPME3QXZYZM2B2JXSRQ4JEXGQ6AZL2CMA/triton_red_fused__to_copy_arange_index_put_lt_new_zeros_scalar_tensor_sum_unsqueeze_view_where_2.ttir", "triton_red_fused__to_copy_arange_index_put_lt_new_zeros_scalar_tensor_sum_unsqueeze_view_where_2.ttgir": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/7Y3WXJA5F4C76K5XYE6DPME3QXZYZM2B2JXSRQ4JEXGQ6AZL2CMA/triton_red_fused__to_copy_arange_index_put_lt_new_zeros_scalar_tensor_sum_unsqueeze_view_where_2.ttgir", "triton_red_fused__to_copy_arange_index_put_lt_new_zeros_scalar_tensor_sum_unsqueeze_view_where_2.llir": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/7Y3WXJA5F4C76K5XYE6DPME3QXZYZM2B2JXSRQ4JEXGQ6AZL2CMA/triton_red_fused__to_copy_arange_index_put_lt_new_zeros_scalar_tensor_sum_unsqueeze_view_where_2.llir", "triton_red_fused__to_copy_arange_index_put_lt_new_zeros_scalar_tensor_sum_unsqueeze_view_where_2.ptx": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/7Y3WXJA5F4C76K5XYE6DPME3QXZYZM2B2JXSRQ4JEXGQ6AZL2CMA/triton_red_fused__to_copy_arange_index_put_lt_new_zeros_scalar_tensor_sum_unsqueeze_view_where_2.ptx", "triton_red_fused__to_copy_arange_index_put_lt_new_zeros_scalar_tensor_sum_unsqueeze_view_where_2.cubin": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/7Y3WXJA5F4C76K5XYE6DPME3QXZYZM2B2JXSRQ4JEXGQ6AZL2CMA/triton_red_fused__to_copy_arange_index_put_lt_new_zeros_scalar_tensor_sum_unsqueeze_view_where_2.cubin", "triton_red_fused__to_copy_arange_index_put_lt_new_zeros_scalar_tensor_sum_unsqueeze_view_where_2.json": "/workspace/hanrui/SpecForge-ext/cache/compiled_kernels/triton/2/7Y3WXJA5F4C76K5XYE6DPME3QXZYZM2B2JXSRQ4JEXGQ6AZL2CMA/triton_red_fused__to_copy_arange_index_put_lt_new_zeros_scalar_tensor_sum_unsqueeze_view_where_2.json"}}