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edit//Qwen3-TTS-test//.venv//Lib//site-packages//torch//include//ATen//native//cuda//fused_adam_utils.cuh
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| 1 |
+
#pragma once
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| 2 |
+
#include <ATen/core/Tensor.h>
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| 3 |
+
#include <ATen/native/cuda/ForeachFunctors.cuh>
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| 4 |
+
#include <ATen/native/cuda/MultiTensorApply.cuh>
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| 5 |
+
#include <ATen/native/cuda/Pow.cuh>
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| 6 |
+
#include <utility>
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| 7 |
+
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| 8 |
+
namespace at::native {
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| 9 |
+
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| 10 |
+
enum class ADAM_MODE : uint8_t { ORIGINAL = 0, ADAMW = 1 };
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| 11 |
+
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| 12 |
+
namespace {
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| 13 |
+
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| 14 |
+
constexpr uint8_t kParamIdx = 0;
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| 15 |
+
constexpr uint8_t kGradIdx = 1;
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| 16 |
+
constexpr uint8_t kExpAvgIdx = 2;
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| 17 |
+
constexpr uint8_t kExpAvgSqIdx = 3;
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| 18 |
+
constexpr uint8_t kMaxExpAvgSqIdx = 4;
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| 19 |
+
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| 20 |
+
template <
|
| 21 |
+
typename scalar_type,
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| 22 |
+
typename opmath_t,
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| 23 |
+
int depth,
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| 24 |
+
ADAM_MODE adam_mode,
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| 25 |
+
bool amsgrad>
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| 26 |
+
C10_DEVICE inline void adam_math(
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| 27 |
+
scalar_type r_args[depth][kILP],
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| 28 |
+
const double& lr,
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| 29 |
+
const double& beta1,
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| 30 |
+
const double& beta2,
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| 31 |
+
const double& weight_decay,
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| 32 |
+
const double& eps,
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| 33 |
+
const bool& maximize,
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| 34 |
+
const float* grad_scale_ptr,
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| 35 |
+
const float* found_inf_ptr,
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| 36 |
+
const opmath_t& bias_correction1,
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| 37 |
+
const opmath_t& bias_correction2_sqrt) {
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| 38 |
+
static_assert(depth == 4 || depth == 5);
|
| 39 |
+
#pragma unroll
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| 40 |
+
for (int ii = 0; ii < kILP; ii++) {
|
| 41 |
+
// Load values.
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| 42 |
+
opmath_t param = static_cast<opmath_t>(r_args[kParamIdx][ii]);
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| 43 |
+
opmath_t grad = static_cast<opmath_t>(r_args[kGradIdx][ii]);
|
| 44 |
+
if (grad_scale_ptr) {
|
| 45 |
+
grad /= (static_cast<double>(*grad_scale_ptr));
|
| 46 |
+
}
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| 47 |
+
const opmath_t grad_to_store = grad;
|
| 48 |
+
if (maximize) {
|
| 49 |
+
grad = -grad;
|
| 50 |
+
}
|
| 51 |
+
opmath_t exp_avg = static_cast<opmath_t>(r_args[kExpAvgIdx][ii]);
|
| 52 |
+
opmath_t exp_avg_sq = static_cast<opmath_t>(r_args[kExpAvgSqIdx][ii]);
|
| 53 |
+
opmath_t max_exp_avg_sq;
|
| 54 |
+
if (amsgrad) {
|
| 55 |
+
max_exp_avg_sq = static_cast<opmath_t>(r_args[kMaxExpAvgSqIdx][ii]);
|
| 56 |
+
}
|
| 57 |
+
// Update param, grad, 1st and 2nd order momentum.
|
| 58 |
+
if (weight_decay != 0) {
|
| 59 |
+
if constexpr (adam_mode == ADAM_MODE::ORIGINAL) {
|
| 60 |
+
grad += param * weight_decay;
|
| 61 |
+
} else if constexpr (adam_mode == ADAM_MODE::ADAMW) {
|
| 62 |
+
param -= lr * weight_decay * param;
|
| 63 |
+
}
|
| 64 |
+
}
|
| 65 |
+
// todo(crcrpar): use lerp
|
| 66 |
+
// ref: https://developer.nvidia.com/blog/lerp-faster-cuda/
|
| 67 |
+
exp_avg = beta1 * exp_avg + (1 - beta1) * grad;
|
| 68 |
+
exp_avg_sq = beta2 * exp_avg_sq + (1 - beta2) * grad * grad;
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| 69 |
+
const opmath_t step_size = lr / bias_correction1;
|
| 70 |
+
opmath_t denom;
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| 71 |
+
if (amsgrad) {
|
| 72 |
+
max_exp_avg_sq = std::max(max_exp_avg_sq, exp_avg_sq);
|
| 73 |
+
denom = (std::sqrt(max_exp_avg_sq) / bias_correction2_sqrt) + eps;
|
| 74 |
+
} else {
|
| 75 |
+
denom = (std::sqrt(exp_avg_sq) / bias_correction2_sqrt) + eps;
|
| 76 |
+
}
|
| 77 |
+
param -= step_size * exp_avg / denom;
|
| 78 |
+
|
| 79 |
+
// Store results.
|
| 80 |
+
r_args[kParamIdx][ii] = param;
|
| 81 |
+
if (grad_scale_ptr) {
|
| 82 |
+
r_args[kGradIdx][ii] = grad_to_store;
|
| 83 |
+
}
|
| 84 |
+
r_args[kExpAvgIdx][ii] = exp_avg;
|
| 85 |
+
r_args[kExpAvgSqIdx][ii] = exp_avg_sq;
|
| 86 |
+
if (amsgrad) {
|
| 87 |
+
r_args[kMaxExpAvgSqIdx][ii] = max_exp_avg_sq;
|
| 88 |
+
}
|
| 89 |
+
}
|
| 90 |
+
}
|
| 91 |
+
|
| 92 |
+
// [note: Conditional Gradient Store when `optimizer.step` is called by
|
| 93 |
+
// GradScaler] When a user is training their model(s) with an FP16 AMP recipe,
|
| 94 |
+
// parameter updates are done via `grad_scaler.step(optimizer)` instead of
|
| 95 |
+
// `optimizer.step()`. For most optimizers, GradScaler unscales gradients on
|
| 96 |
+
// behalf of those optimizers. Also, before `.step`, it makes sure that all the
|
| 97 |
+
// gradients involved are finite, which incurs a device sync. On the other hand,
|
| 98 |
+
// fused optimizers set their member variable of `_step_supports_amp_scaling` to
|
| 99 |
+
// `True` in order to remove the device sync above. This means that fused
|
| 100 |
+
// optimizers have to have their CUDA kernels (a) unscale gradients and (b) skip
|
| 101 |
+
// parameter updates accordingly. To be functionally on par with `torch.optim`
|
| 102 |
+
// optimizers and `_multi_tensor` ones, the kernel below writes out gradients
|
| 103 |
+
// only when `grad_scale_ptr != nullptr.
|
| 104 |
+
template <typename scalar_type, int depth, ADAM_MODE adam_mode, bool amsgrad>
|
| 105 |
+
struct FusedAdamMathFunctor {
|
| 106 |
+
static_assert(
|
| 107 |
+
depth == 4 || depth == 5,
|
| 108 |
+
"depth of 4 for Adam, depth of 5 for Adam with AMSGrad.");
|
| 109 |
+
using opmath_t = at::opmath_type<scalar_type>;
|
| 110 |
+
C10_DEVICE __forceinline__ void operator()(
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| 111 |
+
int chunk_size,
|
| 112 |
+
FusedOptimizerTensorListMetadata<depth>& tl,
|
| 113 |
+
const float* lr_ptr,
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| 114 |
+
const double& lr,
|
| 115 |
+
const double& beta1,
|
| 116 |
+
const double& beta2,
|
| 117 |
+
const double& weight_decay,
|
| 118 |
+
const double& eps,
|
| 119 |
+
const bool& maximize,
|
| 120 |
+
const float* grad_scale_ptr,
|
| 121 |
+
const float* found_inf_ptr) {
|
| 122 |
+
const auto tensor_loc = tl.block_to_tensor[blockIdx.x];
|
| 123 |
+
const auto chunk_idx = tl.block_to_chunk[blockIdx.x];
|
| 124 |
+
const double lr_double = lr_ptr ? *lr_ptr : lr;
|
| 125 |
+
|
| 126 |
+
if (found_inf_ptr && *found_inf_ptr == 1) {
|
| 127 |
+
return;
|
| 128 |
+
}
|
| 129 |
+
const auto [bias_correction1, bias_correction2_sqrt] =
|
| 130 |
+
[&]() -> std::pair<double, double> {
|
| 131 |
+
auto* step_count =
|
| 132 |
+
reinterpret_cast<const float*>(tl.state_steps_addresses[tensor_loc]);
|
| 133 |
+
const auto bias_correction1 = 1 - at::native::pow_(beta1, *step_count);
|
| 134 |
+
const auto bias_correction2 = 1 - at::native::pow_(beta2, *step_count);
|
| 135 |
+
const auto bias_correction2_sqrt = std::sqrt(bias_correction2);
|
| 136 |
+
return {bias_correction1, bias_correction2_sqrt};
|
| 137 |
+
}();
|
| 138 |
+
|
| 139 |
+
scalar_type* args[depth];
|
| 140 |
+
scalar_type r_args[depth][kILP];
|
| 141 |
+
const auto n = tl.numel_for_tensor[tensor_loc] - chunk_idx * chunk_size;
|
| 142 |
+
|
| 143 |
+
const bool all_aligned{
|
| 144 |
+
init_args<depth>(args, tl, chunk_idx, chunk_size, tensor_loc)};
|
| 145 |
+
if ((n % kILP == 0) && (chunk_size % kILP == 0) && all_aligned) {
|
| 146 |
+
for (int64_t i_start = threadIdx.x;
|
| 147 |
+
i_start * kILP < n && i_start * kILP < chunk_size;
|
| 148 |
+
i_start += blockDim.x) {
|
| 149 |
+
#pragma unroll
|
| 150 |
+
for (int i = 0; i < depth; i++) {
|
| 151 |
+
load_store(r_args[i], args[i], 0, i_start);
|
| 152 |
+
}
|
| 153 |
+
adam_math<scalar_type, opmath_t, depth, adam_mode, amsgrad>(
|
| 154 |
+
r_args,
|
| 155 |
+
lr_double,
|
| 156 |
+
beta1,
|
| 157 |
+
beta2,
|
| 158 |
+
weight_decay,
|
| 159 |
+
eps,
|
| 160 |
+
maximize,
|
| 161 |
+
grad_scale_ptr,
|
| 162 |
+
found_inf_ptr,
|
| 163 |
+
bias_correction1,
|
| 164 |
+
bias_correction2_sqrt);
|
| 165 |
+
#pragma unroll
|
| 166 |
+
for (int i = 0; i < depth; i++) {
|
| 167 |
+
if (i != kGradIdx || grad_scale_ptr) {
|
| 168 |
+
load_store(args[i], r_args[i], i_start, 0);
|
| 169 |
+
}
|
| 170 |
+
}
|
| 171 |
+
}
|
| 172 |
+
} else {
|
| 173 |
+
for (int64_t i_start = 0; i_start < n && i_start < chunk_size;
|
| 174 |
+
i_start += blockDim.x * kILP) {
|
| 175 |
+
load_args<depth>(r_args, args, i_start, chunk_size, n);
|
| 176 |
+
adam_math<scalar_type, opmath_t, depth, adam_mode, amsgrad>(
|
| 177 |
+
r_args,
|
| 178 |
+
lr_double,
|
| 179 |
+
beta1,
|
| 180 |
+
beta2,
|
| 181 |
+
weight_decay,
|
| 182 |
+
eps,
|
| 183 |
+
maximize,
|
| 184 |
+
grad_scale_ptr,
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| 185 |
+
found_inf_ptr,
|
| 186 |
+
bias_correction1,
|
| 187 |
+
bias_correction2_sqrt);
|
| 188 |
+
#pragma unroll
|
| 189 |
+
for (int i = 0; i < depth; i++) {
|
| 190 |
+
if (i != kGradIdx || grad_scale_ptr) {
|
| 191 |
+
store_args(args[i], r_args[i], i_start, chunk_size, n);
|
| 192 |
+
}
|
| 193 |
+
}
|
| 194 |
+
}
|
| 195 |
+
}
|
| 196 |
+
}
|
| 197 |
+
};
|
| 198 |
+
} // namespace
|
| 199 |
+
|
| 200 |
+
} // namespace at::native
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