[
  {
    "role": "system",
    "content": "Respond in the following format:\n\n<think>\n...\n</think>\n<total_design>\n...\n</total_design>"
  },
  {
    "role": "user",
    "content": "## RULE #1: KEEP EVERY LINE OF THE ORIGINAL RTL\nThis is the most important rule. The #RTL CODE# section below contains the complete RTL.\nYou MUST output the FULL module -- every line stays exactly as it is, except for additions required by the chosen TPI mode:\n  (a) CP or CP+OP: add `cp_en` using the same port declaration style as the original RTL. OP-only: do NOT add `cp_en`.\n  (b) OP or CP+OP: add `tp_xxx` ports using the same port declaration style as the original RTL. CP-only: no `tp_*` port is required for that bit.\n  (c) CP or CP+OP: add CP function definitions at the TOP of the module body.\n  (d) CP or CP+OP: modify the target register assignment inside always blocks by wrapping the next value with the CP function call.\n  (e) OP or CP+OP: add OP instantiations inside the module body (before `endmodule`).\n  (f) OP or CP+OP: add only the required TestPointOBType_* module definitions AFTER the top module's `endmodule`.\n  DO NOT remove, rewrite, reformat, or regenerate any original RTL code.\n  DO NOT touch the module name, port list (except adding required cp_en/tp_* ports), parameters, reg/wire declarations,\n  always blocks, assign statements, or any other original code.\n\nPORT STYLE: The original RTL uses ANSI-style ports.\n  - Add new ports directly in the module port list with direction/type.\n  - CP/CP+OP example: `input wire cp_en, output wire tp_sig1`.\n  - OP-only example: `output wire tp_sig1`.\n  - Do NOT add separate `input cp_en;` / `output tp_sig1;` declarations in the module body.\n\n## ACTUAL TASK INPUT SUMMARY (READ THIS BEFORE ANY TESTABILITY SCORING)\n#Required TPI Count#: 3\n#Forbidden Scan Cell Bits for THIS sample#:\ncounter[0]\n\nLegality equation for this sample:\n  chosen_tpi_bits ∩ forbidden_scan_bits MUST be empty.\n  If even one chosen CP-only, OP-only, or CP+OP bit is in the forbidden list, the answer is invalid.\nCRITICAL LOW-BIT WARNING for this sample:\n  The following attractive low-order bits are FORBIDDEN here: counter[0]\n  Do not choose them even if they toggle frequently. Start scoring only after removing them.\n\nHow to derive legal non-scan candidates from the RTL and scan-cell list:\n  1) Parse the ORIGINAL RTL declarations and sequential assignments to identify real register bits only.\n     Legal targets must be declared as `reg`, `output reg`, or be assigned in a clocked always block.\n     Do NOT choose plain `wire`, `input`, combinational temporary wires, or invented signal names.\n  2) Expand vectors bit-by-bit. Example: `reg [7:0] data_reg;` creates `data_reg[7]` ... `data_reg[0]`.\n     Scalar registers keep their exact scalar name unless the RTL itself uses an indexed form.\n     Unpacked register arrays are allowed only with exact static indices: `reg [31:0] stack [7:0];` creates\n     bits such as `stack[7][8]`. Do NOT select dynamic elements such as `stack[write_ptr]`.\n  3) Normalize scan-cell names conservatively: remove a leading backslash, remove ONLY the final `_reg` suffix,\n     keep every other part of the RTL name, and keep the bit index.\n     Example: `\\data_reg_reg[8]` -> `data_reg[8]`, NOT `data[8]`.\n     Example: `\\cc_reg[31]` -> `cc[31]`.\n  4) Compute: legal_non_scan_register_bits = RTL_declared_register_bits - normalized_forbidden_scan_bits.\n  5) Choose TPI bits only from legal_non_scan_register_bits. If a chosen name is not an exact RTL register bit,\n     the answer is invalid even if the name looks semantically reasonable.\n\nYour first reasoning step must remove these exact forbidden bits from consideration.\nNever say the scan-cell list is empty unless the list above is literally empty.\n\n## MANDATORY RULES\n\n1. SCAN-CELL EXCLUSION CONSTRAINT (HIGHEST PRIORITY after Rule #1)\n   #Scan Cell Bits# are scan cells selected by AutoPSS.\n   These bits are already scan-controllable/observable and MUST NOT be selected for TPI.\n   Treat #Scan Cell Bits# as an exact FORBIDDEN bit list, not as a recommendation.\n   All test points MUST be inserted on non-scan register bits, i.e. register bits NOT listed in #Scan Cell Bits#.\n   If a vector is partially scanned, legality is bit-specific: if cnt[0], cnt[1], cnt[2], cnt[3] are scan cells, then cnt[4] may be legal but cnt[0]..cnt[3] are forbidden.\n   Low-order bits such as cnt[0], Q[0], state[0], filter[0], data[0] are often attractive because they toggle frequently, but they are STILL ILLEGAL if listed in #Scan Cell Bits#.\n   Do not select a scan bit for CP-only, OP-only, or CP+OP under any circumstance.\n   WRONG: Selecting a register bit that appears in #Scan Cell Bits#, even if it has high activity or strong testability.\n   RIGHT: First remove every scan-cell bit from the candidate set, then choose TPI only from the remaining non-scan bits.\n\n1b. RTL REGISTER-BIT GROUNDING CONSTRAINT\n   Before selecting TPI, explicitly derive legal candidates as:\n     RTL_declared_register_bits - normalized_forbidden_scan_bits.\n   Use the exact RTL signal name. Do not shorten, singularize, or rename registers.\n   WRONG: RTL declares `data_reg`; selecting `data`.\n   WRONG: scan cell `\\data_reg_reg[8]` is normalized to `data[8]`.\n   RIGHT: scan cell `\\data_reg_reg[8]` is normalized to `data_reg[8]` because only the final `_reg` is removed.\n   If the RTL declares `state`, do not select `state_reg` unless that exact register exists in the RTL.\n   Every selected bit must be visible in the original RTL declaration or clocked assignment.\n\n   Register arrays/memories are legal only when the target is bit-precise and statically indexed.\n   RIGHT: `stack[7][8]` if RTL declares `reg [31:0] stack [7:0];`.\n   WRONG: `stack[write_ptr]`, `stack[7]` as a whole row when the budget is for single bits, or any dynamic index.\n\n2. TPI Counting (IS = Intervention Site = 1 bit)\n   - 1-bit CP-only = 1 IS | 1-bit OP-only = 1 IS | 1-bit CP+OP = 1 IS\n   - N-bit OP = N IS (must use `TestPointOBType_Nbit`)\n   - `output [7:0] tp_a;` = 8 IS. You CANNOT pack multiple IS into one vector.\n   - Total IS MUST equal exactly 3.\n   Counting EXAMPLES (CRITICAL -- same bit shared by CP+OP counts as 1 IS):\n     Ex-A: cnt[3:0] OP (4 IS) + cnt[2] CP+OP (same bit, already counted) = 4 IS total (NOT 5!)\n     Ex-B: result[15:0] OP (16 IS) + result[0] CP (same bit) = 16 IS total\n     Ex-C: state[1] CP-only (1 IS) + state[0] OP-only (1 IS) = 2 IS total\n\n3. Port Declaration: Match the original RTL style exactly\n   Add `cp_en` only if at least one selected bit uses CP or CP+OP.\n   OP-only designs must not add `cp_en`.\n   ANSI-style original: add directed ports in the module header, e.g. `input wire cp_en, output wire tp_sig1`.\n   Non-ANSI-style original: add bare names in the port list and add `input cp_en;` / `output tp_sig1;` declarations in the body.\n   Never mix ANSI declarations into a non-ANSI port list.\n\n4. CP Function: Use only for CP or CP+OP. Define at TOP of module body, call inside always-block with <=\n   WRONG: CP on wire/assign. WRONG: function outside module.\n   WRONG: `assign sig = sig_in & ~cp_en;` (never use assign for CP)\n   WRONG: `sig = InsertCP_1bit(sig, cp_en);` (forgot <=)\n   WRONG: `InsertCP_8bit = sig_in & {8{~cp_en}};` when only some bits are selected (this zeroes ALL bits!)\n   CORRECT: `reg <= InsertCP_1bit(sig_next, cp_en);` (inside always block)\n   CP Semantics: cp_en=0 means NORMAL (pass-through), cp_en=1 means FORCE-0.\n   Partial mask (RECOMMENDED): `InsertCP_8bit = {sig_in[7:1], sig_in[0] & ~cp_en};`\n   Full-vector mask is allowed only when EVERY bit of that vector is selected for CP.\n\n5. OP Instantiation: Use only for OP or CP+OP. Inside module body (before endmodule). NEVER use assign.\n   CORRECT: `TestPointOBType_1bit op_sig1 (.funcin(signal1[0]), .tp_out(tp_sig1));`\n   CORRECT: `TestPointOBType_8bit op_sig8 (.funcin(signal[7:0]), .tp_out(tp_sig8));`\n   Width MUST match: N-bit signal -> `TestPointOBType_Nbit`\n\n6. Module Definition Order:\n   (a) Original ports + required new ports (`cp_en` only for CP/CP+OP, `tp_*` only for OP/CP+OP)\n   (b) CP function definitions only if CP/CP+OP exists (at TOP, before always blocks)\n   (c) OP instantiations only if OP/CP+OP exists (before endmodule)\n   (d) Original always/assign blocks (UNCHANGED except CP wrapping)\n   (e) endmodule\n   (f) `module TestPointOBType_* ... endmodule` definitions only for used OP widths\n\n7. Comments: Do not add new comments. Preserve comments that already exist in the original RTL.\n\n8. Directives: Do not add new `timescale or `include directives. Preserve directives that already exist in the original RTL.\n\n9. Chain-of-Thought (inside <think>):\n   Step 1: Circuit Analysis + Scan-Cell Exclusion Filtering\n     - Explicitly identify the scan-cell bits as FORBIDDEN.\n     - List the real RTL register bits or register-bit groups that can be considered.\n     - Normalize the scan-cell list using the rule above.\n     - Build the legal candidate set by computing RTL_declared_register_bits - normalized_forbidden_scan_bits before scoring testability.\n     - Never justify choosing a forbidden scan bit because it toggles often or looks useful.\n   Step 2: Testability Scoring for non-scan register bits\n   Step 3: Budget Allocation and mode choice (CP-only, OP-only, or CP+OP; prove sum of bits = 3)\n     - Include a compact allocation table: bit | mode | count contribution | implementation line.\n     - The table must use the exact RTL bit names that will appear in <total_design>.\n   Step 4: Syntax Pre-simulation\n   Step 5: Final Engineering Check\n     - Every bit listed in your allocation table MUST be physically implemented in <total_design>.\n     - Do not claim a bit such as filter[2] in <think> and then omit its CP/OP construct in RTL.\n     - Recount physical RTL bits from actual InsertCP/TestPointOBType constructs, not from the prose table.\n     - Write this exact legality check in words: `chosen_tpi_bits ∩ forbidden_scan_bits = empty`.\n     - If the intersection is non-empty, you MUST replace the offending bit before writing <total_design>.\n     - This is especially important for state[0], cnt[0], Q[0], filter[0], received[2], and other attractive low bits.\n   Inside <total_design>: ONLY modified RTL. No markdown fences, no text.\n   Stop immediately after </total_design>. Nothing after it.\n\n## STYLE EXAMPLE (follow the syntax style; choose CP/OP/CP+OP according to the actual design)\n\nExample input RTL -- simple state machine with 2 test points:\n`timescale 1ns/1ps\nmodule fsm_example #(parameter WIDTH=8) (\n  input wire clk, rst_n,\n  input wire [WIDTH-1:0] data_in,\n  output reg [WIDTH-1:0] data_out,\n  output wire ready\n);\n  localparam IDLE=2'b00, WORK=2'b01, DONE=2'b10;\n  reg [1:0] state, next_state;\n  reg [WIDTH-1:0] buffer;\n  assign ready = (state == DONE);\n  always @(posedge clk or negedge rst_n)\n    if (!rst_n) state <= IDLE;\n    else state <= next_state;\n  always @* begin\n    next_state = state;\n    case (state)\n      IDLE: if (data_in[0]) next_state = WORK;\n      WORK: next_state = DONE;\n      DONE: next_state = IDLE;\n    endcase\n  end\n  always @(posedge clk or negedge rst_n)\n    if (!rst_n) buffer <= {WIDTH{1'b0}};\n    else if (state == WORK) buffer <= data_in;\n  always @(posedge clk or negedge rst_n)\n    if (!rst_n) data_out <= {WIDTH{1'b0}};\n    else data_out <= buffer;\nendmodule\n\nCORRECT output -- original RTL fully preserved, CP+OP example added:\n`timescale 1ns/1ps\nmodule fsm_example #(parameter WIDTH=8) (\n  input wire clk, rst_n,\n  input wire [WIDTH-1:0] data_in,\n  output reg [WIDTH-1:0] data_out,\n  output wire ready,\n  input wire cp_en,\n  output wire tp_state_1,\n  output wire tp_buffer_7\n);\n  localparam IDLE=2'b00, WORK=2'b01, DONE=2'b10;\n  reg [1:0] state, next_state;\n  reg [WIDTH-1:0] buffer;\n  assign ready = (state == DONE);\n  function [1:0] InsertCP_2bit_state;\n    input [1:0] sig_in;\n    input cp_en;\n    begin\n      InsertCP_2bit_state = {sig_in[1] & ~cp_en, sig_in[0]};\n    end\n  endfunction\n  function [WIDTH-1:0] InsertCP_Wbit_buffer;\n    input [WIDTH-1:0] sig_in;\n    input cp_en;\n    begin\n      InsertCP_Wbit_buffer = {sig_in[WIDTH-1:8], sig_in[7] & ~cp_en, sig_in[6:0]};\n    end\n  endfunction\n  TestPointOBType_1bit op_state_1 (.funcin(state[1]), .tp_out(tp_state_1));\n  TestPointOBType_1bit op_buffer_7 (.funcin(buffer[7]), .tp_out(tp_buffer_7));\n  always @(posedge clk or negedge rst_n)\n    if (!rst_n) state <= IDLE;\n    else state <= InsertCP_2bit_state(next_state, cp_en);\n  always @* begin\n    next_state = state;\n    case (state)\n      IDLE: if (data_in[0]) next_state = WORK;\n      WORK: next_state = DONE;\n      DONE: next_state = IDLE;\n    endcase\n  end\n  always @(posedge clk or negedge rst_n)\n    if (!rst_n) buffer <= {WIDTH{1'b0}};\n    else if (state == WORK) buffer <= InsertCP_Wbit_buffer(data_in, cp_en);\n  always @(posedge clk or negedge rst_n)\n    if (!rst_n) data_out <= {WIDTH{1'b0}};\n    else data_out <= buffer;\nendmodule\nmodule TestPointOBType_1bit (input funcin, output tp_out);\n  assign tp_out = funcin;\nendmodule\nmodule TestPointOBType_2bit (input [1:0] funcin, output [1:0] tp_out);\n  assign tp_out = funcin;\nendmodule\n\n## CP/OP SYNTAX REFERENCE\n\nUse only the syntax needed by your selected modes. OP-only samples do not need `cp_en` or CP functions.\n\n### CP Function (ONLY for CP or CP+OP; AND-type: cp_en=0=normal/pass-through, cp_en=1=force target bit to 0)\nThe key principle: only the masked bits are forced to 0; ALL other bits PASS THROUGH unchanged.\n\nMode A -- Single bit CP (most common):\n  function InsertCP_1bit;\n    input sig_in; input cp_en;\n    begin InsertCP_1bit = sig_in & ~cp_en; end\n  endfunction\n\nMode B -- Multi-bit, only bit[0] controlled, rest PASS THROUGH:\n  function [7:0] InsertCP_8bit_bit0;\n    input [7:0] sig_in; input cp_en;\n    begin\n      InsertCP_8bit_bit0 = {sig_in[7:1], sig_in[0] & ~cp_en};\n    end\n  endfunction\n\nMode C -- Multi-bit, specific bits controlled (bit[7] + bit[3]), rest PASS THROUGH:\n  function [7:0] InsertCP_8bit_bit73;\n    input [7:0] sig_in; input cp_en;\n    begin\n      InsertCP_8bit_bit73 = {\n        sig_in[7] & ~cp_en, sig_in[6:4],\n        sig_in[3] & ~cp_en, sig_in[2:0]\n      };\n    end\n  endfunction\n\nMode D -- Full-vector mask is usually wrong:\n  Do NOT write `sig_in & {N{~cp_en}}` unless all N bits are selected for CP.\n\n### CP Usage (inside always block, use <= non-blocking)\n  reg <= InsertCP_1bit(reg_next, cp_en);\n  reg <= InsertCP_8bit_bit0(reg_next, cp_en);\n  reg <= InsertCP_8bit_bit73(reg_next, cp_en);\nFull-vector mask is rarely correct -- it zeroes every bit of the vector!\n\n### OP Instantiation\n  TestPointOBType_1bit op_sig1 (.funcin(signal1), .tp_out(tp_sig1));\n  TestPointOBType_8bit op_sig8 (.funcin(signal[7:0]), .tp_out(tp_sig8));\n\n  For unpacked register arrays, use exact static bit indices:\n  TestPointOBType_1bit op_stack_7_8 (.funcin(stack[7][8]), .tp_out(tp_stack_7_8));\n  Do not use dynamic array indices for TPI targets.\n\n### Port Declaration\n  Preserve the original port declaration style.\n  ANSI original: add directed ports in the header.\n  Non-ANSI original: add bare names in the header and declarations in the body.\n  `cp_en` is only for CP or CP+OP. `tp_*` is only for OP or CP+OP.\n\n### Module Definition Order\n  1) Original ports + required added ports\n  2) CP function definitions, only if CP/CP+OP exists (at TOP of module body)\n  3) OP instantiations, only if OP/CP+OP exists (before endmodule)\n  4) Original logic (unchanged)\n  5) endmodule\n  6) TestPointOBType_* module definitions, only for used OP widths\n\n#RTL CODE#:\nmodule gen_sync ( input clock,input reset,input enable,input [7:0] rate,output wire sync );\n \n  reg [7:0] counter; \n  assign sync = |(((rate+1)>>1)& counter); \n  always @(posedge clock) \n  if(reset || ~enable) \n  counter <= #1 0; \n  else if(counter == rate) \n  counter <= #1 0; \n  else \n  counter <= #1 counter + 8'd1; \n endmodule\n\n#Scan Cell Bits (DO NOT select):\ncounter[0]\n\n#Required TPI Count: 3"
  }
]