| # Tiny Tapeout project information | |
| project: | |
| title: "Bit-String Accelerator" | |
| author: "Ahmad Ali Parr" | |
| discord: "" | |
| description: "Single-bit GET/TEST/SET/CLEAR/TOGGLE on 64-bit words over a UART" | |
| language: "SystemVerilog" | |
| clock_hz: 12000000 # Any clock works: set the UART divisor pins to match | |
| # How many tiles your design occupies? A single tile is about 167x108 uM. | |
| tiles: "2x2" # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2 | |
| # Your top module name must start with "tt_um_". Make it unique by including your github username: | |
| top_module: "tt_um_snapkittyagent9nova_bitacc" | |
| # List your project's source files here. | |
| # Source files must be in ./src and you must list each source file separately, one per line. | |
| # Don't forget to also update `PROJECT_SOURCES` in test/Makefile. | |
| source_files: | |
| - "bit_accelerator.sv" | |
| - "uart_rx.sv" | |
| - "uart_tx.sv" | |
| - "tt_um_snapkittyagent9nova_bitacc.sv" | |
| # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins. | |
| # This section is for the datasheet/website. Use descriptive names (e.g., RX, TX, MOSI, SCL, SEG_A, etc.). | |
| pinout: | |
| # Inputs | |
| ui[0]: "DIV0" | |
| ui[1]: "DIV1" | |
| ui[2]: "DIV2" | |
| ui[3]: "RX" | |
| ui[4]: "DIV3" | |
| ui[5]: "DIV4" | |
| ui[6]: "DIV5" | |
| ui[7]: "DIV6" | |
| # Outputs | |
| uo[0]: "BUSY" | |
| uo[1]: "ERROR" | |
| uo[2]: "RESULT" | |
| uo[3]: "" | |
| uo[4]: "TX" | |
| uo[5]: "" | |
| uo[6]: "" | |
| uo[7]: "" | |
| # Bidirectional pins | |
| uio[0]: "" | |
| uio[1]: "" | |
| uio[2]: "" | |
| uio[3]: "" | |
| uio[4]: "" | |
| uio[5]: "" | |
| uio[6]: "" | |
| uio[7]: "" | |
| # Do not change! | |
| yaml_version: 6 | |