# Pins are arbitrary bank-16 I/Os of the XC7A100T-FGG484; only internal timing is of interest.
set_property LOC C18 [get_ports clk]
set_property LOC A13 [get_ports rst]
set_property LOC A14 [get_ports sin]
set_property LOC A15 [get_ports ctl[0]]
set_property LOC A16 [get_ports ctl[1]]
set_property LOC A18 [get_ports ctl[2]]
set_property LOC A19 [get_ports ctl[3]]
set_property LOC A20 [get_ports sout[0]]
set_property LOC A21 [get_ports sout[1]]
set_property LOC B13 [get_ports sout[2]]
set_property LOC B15 [get_ports sout[3]]
set_property LOC B16 [get_ports sout[4]]
set_property LOC B17 [get_ports sout[5]]
set_property LOC B18 [get_ports sout[6]]
set_property LOC B20 [get_ports sout[7]]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports rst]
set_property IOSTANDARD LVCMOS33 [get_ports sin]
set_property IOSTANDARD LVCMOS33 [get_ports ctl[0]]
set_property IOSTANDARD LVCMOS33 [get_ports ctl[1]]
set_property IOSTANDARD LVCMOS33 [get_ports ctl[2]]
set_property IOSTANDARD LVCMOS33 [get_ports ctl[3]]
set_property IOSTANDARD LVCMOS33 [get_ports sout[0]]
set_property IOSTANDARD LVCMOS33 [get_ports sout[1]]
set_property IOSTANDARD LVCMOS33 [get_ports sout[2]]
set_property IOSTANDARD LVCMOS33 [get_ports sout[3]]
set_property IOSTANDARD LVCMOS33 [get_ports sout[4]]
set_property IOSTANDARD LVCMOS33 [get_ports sout[5]]
set_property IOSTANDARD LVCMOS33 [get_ports sout[6]]
set_property IOSTANDARD LVCMOS33 [get_ports sout[7]]