{
  "//": "DO NOT EDIT THIS FILE before reading the comments below:",

  "//": "This is the default configuration for Tiny Tapeout projects. It should fit most designs.",
  "//": "If you change it, please make sure you understand what you are doing. We are not responsible",
  "//": "if your project fails because of a bad configuration.",

  "//": "!!! DO NOT EDIT THIS FILE unless you know what you are doing !!!",

  "//": "If you get stuck with this config, please open an issue or get in touch via the discord.",

  "//": "Here are some of the variables you may want to change:",

  "//": "PL_TARGET_DENSITY_PCT - You can increase this if Global Placement fails with error GPL-0302.",
  "//": "Users have reported that values up to 80 worked well for them.",
  "PL_TARGET_DENSITY_PCT": 60,

  "//": "CLOCK_PERIOD - Increase this in case you are getting setup time violations.",
  "//": "The value is in nanoseconds, so 20ns == 50MHz.",
  "CLOCK_PERIOD": 20,

  "//": "Hold slack margin - Increase them in case you are getting hold violations.",
  "PL_RESIZER_HOLD_SLACK_MARGIN": 0.1,
  "GRT_RESIZER_HOLD_SLACK_MARGIN": 0.05,

  "//": "RUN_LINTER, LINTER_INCLUDE_PDK_MODELS - Disabling the linter is not recommended!",
  "RUN_LINTER": 1,
  "LINTER_INCLUDE_PDK_MODELS": 1,

  "//": "If you need a custom clock configuration, read the following documentation first:",
  "//": "https://tinytapeout.com/faq/#how-can-i-map-an-additional-external-clock-to-one-of-the-gpios",
  "CLOCK_PORT": "clk",

  "//": "Configuration docs: https://librelane.readthedocs.io/en/latest/reference/configuration.html",

  "//": "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!",
  "//": "!!! DO NOT CHANGE ANYTHING BELOW THIS POINT !!!",
  "//": "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!",

  "//": "Save some time",
  "RUN_KLAYOUT_XOR": 0,
  "RUN_KLAYOUT_DRC": 0,

  "//": "Don't put clock buffers on the outputs",
  "DESIGN_REPAIR_BUFFER_OUTPUT_PORTS": 0,

  "//": "Reduce wasted space",
  "TOP_MARGIN_MULT": 1,
  "BOTTOM_MARGIN_MULT": 1,
  "LEFT_MARGIN_MULT": 6,
  "RIGHT_MARGIN_MULT": 6,

  "//": "Absolute die size",
  "FP_SIZING": "absolute",

  "GRT_ALLOW_CONGESTION": 1,

  "FP_IO_HLENGTH": 2,
  "FP_IO_VLENGTH": 2,

  "FP_PDN_VPITCH": 38.87,

  "//": "Clock",
  "RUN_CTS": 1,

  "//": "Don't generate power rings",
  "FP_PDN_MULTILAYER": 0,

  "//": "MAGIC_DEF_LABELS may cause issues with LVS",
  "MAGIC_DEF_LABELS": 0,

  "//": "Only export pin area in LEF (without any connected nets)",
  "MAGIC_WRITE_LEF_PINONLY": 1
}