Create README.md
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README.md
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## Example
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```python
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from transformers import AutoModelForCausalLM, AutoTokenizer
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import torch
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import re
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model_name = "TabCanNotTab/SALV-Qwen2.5-Coder-7B-Instruct"
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model = AutoModelForCausalLM.from_pretrained(
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model_name,
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torch_dtype=torch.bfloat16,
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device_map="auto",
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)
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tokenizer = AutoTokenizer.from_pretrained(model_name)
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prompt = """
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Please act as a professional verilog designer.
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Implement a module of an 8-bit adder with multiple bit-level adders in combinational logic.
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Module name:
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adder_8bit
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Input ports:
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a[7:0]: 8-bit input operand A.
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b[7:0]: 8-bit input operand B.
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cin: Carry-in input.
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Output ports:
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sum[7:0]: 8-bit output representing the sum of A and B.
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cout: Carry-out output.
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Implementation:
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The module utilizes a series of bit-level adders (full adders) to perform the addition operation.
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Give me the complete code.
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"""
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messages = [
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{"role": "system", "content": "You are a helpful assistant."},
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{"role": "user", "content": prompt}
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]
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text = tokenizer.apply_chat_template(messages, tokenize=False, add_generation_prompt=True)
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model_inputs = tokenizer(text, return_tensors="pt").to(model.device)
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# inference
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outputs = model.generate(
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**model_inputs,
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max_new_tokens=2048,
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do_sample=True,
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temperature=0.5,
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top_p=0.95
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)
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# get response text
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input_length = model_inputs.input_ids.shape[1]
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generated_tokens = outputs[0][input_length:]
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response = tokenizer.decode(generated_tokens, skip_special_tokens=True)
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# get code text
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pattern = r"```verilog\s*(.*?)\s*```"
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matches = re.findall(pattern, response, re.DOTALL)
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if matches:
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code=matches[-1]
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print(code)
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else:
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print("No Verilog code found in the response!")
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```
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