Update README.md

README.md

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 # Pollux-1920 10k — Native H24 Leech-Lattice Language Model
 
-**Pollux-1920** is a **991M-parameter** decoder-only causal transformer trained from scratch at **native 0.76-bit quantization resolution** (V = 50,688, n_embd = 1920). By mapping the parameter manifold natively onto the H24 Leech lattice, the **796M-parameter backbone** compresses to just **76 MB of active SRAM**.
+**Pollux-1920** is a **991M-parameter** decoder-only causal transformer trained from scratch at **native 0.76-bit quantization resolution** (V = 50,688, n_embd = 1920). By mapping the parameter manifold natively onto the H24 Leech lattice, the **796M-parameter backbone** compresses to just **76 MB of active SRAM**. For the complete architectural and mathematical breakdown, read the official paper: [*0.76 Bits Is All You Need: Vector Ternary Logic via Native H24 Leech-Lattice Quantization in LLMs*](https://papers.ssrn.com/abstract=6973978).
 
 This checkpoint represents the **thermodynamic crystallisation peak** at **10,000 steps** (~2.6B tokens). All benchmark scores below are measured directly on the fully serialized **265 MB `.plx` deployment artifact**, confirming that the stated Iso-Memory footprints reflect true Edge AI deployment realities without statistical degradation.
 
@@ -91,6 +91,6 @@ Commercial utilization requires a license (pending WIPO Application No. PCT/AT20
   author  = {Lavicka, Alexander},
   year    = {2026},
   note    = {Preprint. WIPO Patent Application No. PCT/AT2026/060108 and Austrian Patent Application No. A65086/2026},
-  url     = {[https://github.com/alavicka/pollux](https://github.com/alavicka/pollux)}
+  url     = {https://papers.ssrn.com/abstract=6973978}
 
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