bitsandbytes/pr_1353/en/_app/immutable/nodes/12.e1552b79.js

import{s as $e,o as be,n as xe}from"../chunks/scheduler.852ec091.js";import{S as ye,i as ve,g as o,s as l,r as A,A as we,h as r,f as n,c as s,j as ce,u as L,x as f,k as he,y as ge,a,v as H,d as G,t as D,w as F}from"../chunks/index.28275fd3.js";import{T as ke}from"../chunks/Tip.9f398c59.js";import{H as N,E as _e}from"../chunks/EditOnGithub.582011f0.js";function Ce(R){let i,m='Apple Silicon support is planned for Q4 2024. We are actively seeking contributors to help implement this, develop a concrete plan, and create a detailed list of requirements. Due to limited resources, we rely on community contributions for this implementation effort. To discuss further, please spell out your thoughts and discuss in <a href="https://github.com/bitsandbytes-foundation/bitsandbytes/discussions/1340" rel="nofollow">this GitHub discussion</a> and tag <code>@Titus-von-Koeller</code> and <code>@matthewdouglas</code>. Thank you!';return{c(){i=o("p"),i.innerHTML=m},l(p){i=r(p,"P",{"data-svelte-h":!0}),f(i)!=="svelte-ztwrs6"&&(i.innerHTML=m)},m(p,I){a(p,i,I)},p:xe,d(p){p&&n(i)}}}function Te(R){let i,m,p,I,d,U,c,ae="As part of a recent refactoring effort, we will soon offer official multi-backend support. Currently, this feature is available in a preview alpha release, allowing us to gather early feedback from users to improve the functionality and identify any bugs.",O,h,le="At present, the Intel CPU and AMD ROCm backends are considered fully functional. The Intel XPU backend has limited functionality and is less mature.",S,$,se='Please refer to the <a href="./installation#multi-backend">installation instructions</a> for details on installing the backend you intend to test (and hopefully provide feedback on).',q,u,B,b,j,x,ie="As we are currently in the alpha testing phase, bugs are expected, and performance might not meet expectations. However, this is exactly what we want to discover from <strong>your</strong> perspective as the end user!",z,y,oe="Please share and discuss your feedback with us here:",X,v,re='<li><a href="https://github.com/bitsandbytes-foundation/bitsandbytes/discussions/1339" rel="nofollow">Github Discussion: Multi-backend refactor: Alpha release ( AMD ROCm ONLY )</a></li> <li><a href="https://github.com/bitsandbytes-foundation/bitsandbytes/discussions/1338" rel="nofollow">Github Discussion: Multi-backend refactor: Alpha release ( Intel ONLY )</a></li>',Y,w,pe="Thank you for your support!",K,g,Q,k,W,_,fe='The following performance data is collected from Intel 4th Gen Xeon (SPR) platform. The tables show speed-up and memory compared with different data types of <a href="https://huggingface.co/meta-llama/Llama-2-7b-chat-hf" rel="nofollow">Llama-2-7b-chat-hf</a>.',J,C,ue=`For inference:
|          | BF16   | INT8   | NF4   | FP4   |
| speed-up | 1.0x   | 0.6x   | 2.3x  | 0.03x |
| memory   | 13.1G  | 7.6G   | 5.0G  | 4.6G  |`,V,T,me=`For fine-tune:
|          | AMP BF16   | INT8   | NF4   | FP4   |
| speed-up | 1.0x       | 0.38x  | 0.07x | 0.07x |
| memory   | 40G        | 9G     | 6.6G  | 6.6G  |`,Z,P,ee,M,te,E,ne;return d=new N({props:{title:"Multi-backend support (non-CUDA backends)",local:"multi-backend-support-non-cuda-backends",headingTag:"h1"}}),u=new ke({props:{warning:!1,$$slots:{default:[Ce]},$$scope:{ctx:R}}}),b=new N({props:{title:"Alpha Release",local:"alpha-release",headingTag:"h2"}}),g=new N({props:{title:"Benchmarks",local:"benchmarks",headingTag:"h2"}}),k=new N({props:{title:"Intel",local:"intel",headingTag:"h3"}}),P=new N({props:{title:"AMD",local:"amd",headingTag:"h3"}}),M=new _e({props:{source:"https://github.com/bitsandbytes-foundation/bitsandbytes/blob/main/docs/source/non_cuda_backends.mdx"}}),{c(){i=o("meta"),m=l(),p=o("p"),I=l(),A(d.$$.fragment),U=l(),c=o("p"),c.textContent=ae,O=l(),h=o("p"),h.textContent=le,S=l(),$=o("p"),$.innerHTML=se,q=l(),A(u.$$.fragment),B=l(),A(b.$$.fragment),j=l(),x=o("p"),x.innerHTML=ie,z=l(),y=o("p"),y.textContent=oe,X=l(),v=o("ul"),v.innerHTML=re,Y=l(),w=o("p"),w.textContent=pe,K=l(),A(g.$$.fragment),Q=l(),A(k.$$.fragment),W=l(),_=o("p"),_.innerHTML=fe,J=l(),C=o("p"),C.textContent=ue,V=l(),T=o("p"),T.textContent=me,Z=l(),A(P.$$.fragment),ee=l(),A(M.$$.fragment),te=l(),E=o("p"),this.h()},l(e){const t=we("svelte-u9bgzb",document.head);i=r(t,"META",{name:!0,content:!0}),t.forEach(n),m=s(e),p=r(e,"P",{}),ce(p).forEach(n),I=s(e),L(d.$$.fragment,e),U=s(e),c=r(e,"P",{"data-svelte-h":!0}),f(c)!=="svelte-vyk3k9"&&(c.textContent=ae),O=s(e),h=r(e,"P",{"data-svelte-h":!0}),f(h)!=="svelte-12ne44y"&&(h.textContent=le),S=s(e),$=r(e,"P",{"data-svelte-h":!0}),f($)!=="svelte-1wpsr8f"&&($.innerHTML=se),q=s(e),L(u.$$.fragment,e),B=s(e),L(b.$$.fragment,e),j=s(e),x=r(e,"P",{"data-svelte-h":!0}),f(x)!=="svelte-njzoox"&&(x.innerHTML=ie),z=s(e),y=r(e,"P",{"data-svelte-h":!0}),f(y)!=="svelte-5kenpg"&&(y.textContent=oe),X=s(e),v=r(e,"UL",{"data-svelte-h":!0}),f(v)!=="svelte-7ea0dg"&&(v.innerHTML=re),Y=s(e),w=r(e,"P",{"data-svelte-h":!0}),f(w)!=="svelte-16dyb3n"&&(w.textContent=pe),K=s(e),L(g.$$.fragment,e),Q=s(e),L(k.$$.fragment,e),W=s(e),_=r(e,"P",{"data-svelte-h":!0}),f(_)!=="svelte-1qmjl0d"&&(_.innerHTML=fe),J=s(e),C=r(e,"P",{"data-svelte-h":!0}),f(C)!=="svelte-12rda40"&&(C.textContent=ue),V=s(e),T=r(e,"P",{"data-svelte-h":!0}),f(T)!=="svelte-1klq3ob"&&(T.textContent=me),Z=s(e),L(P.$$.fragment,e),ee=s(e),L(M.$$.fragment,e),te=s(e),E=r(e,"P",{}),ce(E).forEach(n),this.h()},h(){he(i,"name","hf:doc:metadata"),he(i,"content",Pe)},m(e,t){ge(document.head,i),a(e,m,t),a(e,p,t),a(e,I,t),H(d,e,t),a(e,U,t),a(e,c,t),a(e,O,t),a(e,h,t),a(e,S,t),a(e,$,t),a(e,q,t),H(u,e,t),a(e,B,t),H(b,e,t),a(e,j,t),a(e,x,t),a(e,z,t),a(e,y,t),a(e,X,t),a(e,v,t),a(e,Y,t),a(e,w,t),a(e,K,t),H(g,e,t),a(e,Q,t),H(k,e,t),a(e,W,t),a(e,_,t),a(e,J,t),a(e,C,t),a(e,V,t),a(e,T,t),a(e,Z,t),H(P,e,t),a(e,ee,t),H(M,e,t),a(e,te,t),a(e,E,t),ne=!0},p(e,[t]){const de={};t&2&&(de.$$scope={dirty:t,ctx:e}),u.$set(de)},i(e){ne||(G(d.$$.fragment,e),G(u.$$.fragment,e),G(b.$$.fragment,e),G(g.$$.fragment,e),G(k.$$.fragment,e),G(P.$$.fragment,e),G(M.$$.fragment,e),ne=!0)},o(e){D(d.$$.fragment,e),D(u.$$.fragment,e),D(b.$$.fragment,e),D(g.$$.fragment,e),D(k.$$.fragment,e),D(P.$$.fragment,e),D(M.$$.fragment,e),ne=!1},d(e){e&&(n(m),n(p),n(I),n(U),n(c),n(O),n(h),n(S),n($),n(q),n(B),n(j),n(x),n(z),n(y),n(X),n(v),n(Y),n(w),n(K),n(Q),n(W),n(_),n(J),n(C),n(V),n(T),n(Z),n(ee),n(te),n(E)),n(i),F(d,e),F(u,e),F(b,e),F(g,e),F(k,e),F(P,e),F(M,e)}}}const Pe='{"title":"Multi-backend support (non-CUDA backends)","local":"multi-backend-support-non-cuda-backends","sections":[{"title":"Alpha Release","local":"alpha-release","sections":[],"depth":2},{"title":"Benchmarks","local":"benchmarks","sections":[{"title":"Intel","local":"intel","sections":[],"depth":3},{"title":"AMD","local":"amd","sections":[],"depth":3}],"depth":2}],"depth":1}';function Me(R){return be(()=>{new URLSearchParams(window.location.search).get("fw")}),[]}class De extends ye{constructor(i){super(),ve(this,i,Me,Te,$e,{})}}export{De as component};