education/CSAPP-Lectures_2015Fall/Lecture17/generation_task/judge_prompt.json

{
  "material_dependent_checklist_1": [
    "\n**Title & Scope: The Intel Core i7/Linux Case Study**\n\n**Topic Identification**\n* Does the material clearly identify the subject as a case study of the \"Intel Core i7/Linux Memory System\"?\n* Is the context established as bridging hardware architecture (Core i7) with operating system software (Linux)?\n  Note: Check only for presence. If missing, specify if the link between HW and OS is ignored.\n",
    "\n**Coverage of Core Implementations**\n* Does the content explicitly specify the supported address spaces for current Core i7 implementations?\n  * 48-bit virtual address space (256 TB)?\n  * 52-bit physical address space (4 PB)?\n  * Compatibility mode for 32-bit (4 GB)?\n  If no, indicate which address limits are omitted.\n",
    "\n**Hardware Architecture: The Core i7 Hierarchy**\n\n**Processor Package Components**\n* Are the major components of the processor package listed?\n  * Four cores?\n  * Large shared L3 cache?\n  * DDR3 memory controller?\n  * QuickPath Interconnect (for core-to-core and I/O communication)?\n",
    "\n**Per-Core Cache and TLB Detail**\n* Does the detailed breakdown per core include specific capacities and associativities?\n  * L1 i-cache and d-cache (32 KB, 8-way)?\n  * L2 unified cache (256 KB, 8-way)?\n  * TLB Hierarchy: L1 d-TLB (64 entries), L1 i-TLB (128 entries), and L2 unified TLB (512 entries)?\n  If no, specify if the distinction between Instruction and Data caches/TLBs is missing.\n",
    "\n**Address Translation & Page Tables**\n\n**Translation Mechanics**\n* Is the four-level page table hierarchy explicitly illustrated or described?\n* Is the function of the CR3 control register (pointing to the L1 page table base) explained?\n",
    "\n**Page Table Entry (PTE) Bits**\n* Are the specific permission and status bits within a PTE defined?\n  * **P (Present):** Memory residency status?\n  * **R/W (Read/Write):** Access permissions?\n  * **U/S (User/Supervisor):** User vs. Kernel mode protection?\n  * **XD (Execute Disable):** Protection against buffer overflow attacks?\n  * **A (Accessed) & D (Dirty):** Bits used for page replacement algorithms?\n  If no, specify if security features like XD are omitted.\n",
    "\n**Linux Virtual Memory System**\n\n**Process Address Space Organization**\n* Does the content detail the separate virtual address space for each process?\n* Are the key segments identified: Kernel virtual memory (top), User stack, Shared libraries, Heap, Data, and Text (Code)?\n",
    "\n**Kernel Data Structures**\n* Are the specific Linux kernel structures for memory management introduced?\n  * **task_struct:** The process descriptor?\n  * **mm_struct:** Containing `pgd` (page global directory) and `mmap` (area list)?\n  * **vm_area_struct:** Defining contiguous regions (`vm_start`, `vm_end`, `vm_prot`, `vm_flags`)?\n  If no, specify if the link between the task structure and the virtual memory areas is missing.\n",
    "\n**Exception Handling & Memory Mapping**\n\n**Page Fault Handling Logic**\n* Is the sequential logic of the Linux page fault handler presented?\n  1. Is the address legal? (Check `vm_area_struct` list).\n  2. Is the access permitted? (Check `vm_prot`).\n  3. Handle fault (Swap in victim page).\n  If no, specify if the distinction between a Segmentation Fault and a Protection Exception is unclear.\n",
    "\n**Memory Mapping Types**\n* Does the section on Memory Mapping distinguish between:\n  * **Regular Files:** File-backed mapping (demand paging)?\n  * **Anonymous Files:** Demand-zero pages (binary zeros)?\n  * **Swap Space:** The bounding limit for allocated virtual pages?\n",
    "\n**Process Control & System Calls**\n\n**Functionality of `fork`, `execve`, and `mmap`**\n* Is the **Copy-on-Write (COW)** mechanism explained in the context of `fork` (sharing physical pages until a write occurs)?\n* Are the four steps of `execve` listed (Delete areas, Map private, Map shared, Set PC)?\n* Is the `mmap` function prototype and its arguments (`prot`, `flags`, `fd`) detailed for user-level mapping?\n"
  ],
  "material_dependent_checklist_2": [
    "\n**Hardware Specifications & Constants**\n\n* **Cache Parameters:** Are the cache parameters accurate to the text?\n  * *Detail Check:* Verify L3 is listed as **16-way** associative, while L1 and L2 are **8-way**. Ensure block size is cited as **64 bytes**.\n",
    "\n* **TLB Capacities:** Are the TLB entry counts correct?\n  * *Detail Check:* Confirm L1 d-TLB is 64 entries, L1 i-TLB is 128 entries, and L2 is 512 entries.\n",
    "\n* **Address Translation Bits:** Is the partitioning of the Virtual Address (VA) correct for 4 KB pages?\n  * *Detail Check:* Verify the 36-bit VPN is split into four 9-bit chunks, with a 12-bit VPO (Virtual Page Offset).\n",
    "\n**PTE Format & Permissions**\n\n* **Address Alignment:** Does the content explain the alignment requirement imposed by the PPN?\n  * *Detail Check:* Verify the statement that the 40-bit PPN points to a 4 KB aligned page table or physical page.\n",
    "\n* **Security Bits:** Is the XD bit correctly attributed to 64-bit systems for disabling instruction fetches?\n  * *Detail Check:* Ensure the link between the XD bit and preventing buffer overflow attacks is made.\n",
    "\n* **Reference Bits:** Are the 'A' (Accessed) and 'D' (Dirty) bits correctly described as being set by the MMU and cleared by the kernel software?\n",
    "\n**Linux Data Structures & Logic**\n\n* **Structure Hierarchy:** Is the relationship between `task_struct`, `mm_struct`, and `vm_area_struct` logically consistent?\n  * *Detail Check:* `task_struct` points to `mm_struct`, which points to both `pgd` (hardware context) and the list of `vm_area_structs` (logical context).\n",
    "\n* **Fault Classification:** Are the failure modes accurately named?\n  * *Detail Check:* Accessing a non-existent page (not in an area struct) must be labeled a **Segmentation Fault**. Violating permissions (e.g., writing to read-only) must be labeled a **Protection Exception**.\n",
    "\n* **Optimization Logic:** Is the overlap of TLB access and L1 cache access explained correctly?\n  * *Detail Check:* Verify the explanation that VPO bits are used to index the L1 cache while the MMU translates the VPN, allowing parallel operations.\n",
    "\n**Memory Mapping & Shared Objects**\n\n* **Copy-on-Write (COW) Mechanics:** Is the COW process accurately described?\n  * *Detail Check:* Confirm that initially, pages are flagged **read-only** in the page table and **private copy-on-write** in the area struct. A write triggers a protection fault, not a segfault.\n",
    "\n* **`execve` Mapping Steps:** Are the specific mapping types for the new program correct?\n  * *Detail Check:* Code and Data are **private, file-backed**. BSS and Stack are **private, demand-zero**. Shared libraries (libc) are **shared, file-backed**.\n",
    "\n* **`mmap` Flags:** Are the flag definitions accurate?\n  * *Detail Check:* `MAP_ANON` implies demand-zero pages; `MAP_PRIVATE` implies copy-on-write behavior.\n"
  ]
}