chip__ADDB__src___ADDB___15fcc13a37/testbench/tb_prompt.txt

You are an expert RTL verification engineer. Generate a single self-contained `tb.py` cocotb script for the Verilog sample below.

Goal:
- Write a practical cocotb testbench that checks the reference RTL passes.
- The testbench does not need perfect coverage, but it must reflect important behaviors described by the prompt.
- Prefer 3-6 focused checks instead of an overly ambitious exhaustive test.

Hard requirements:
- Output only valid Python source code for one file named `tb.py`
- The file must be directly runnable with: `python tb.py`
- Use only Python stdlib + cocotb
- Use `from cocotb_tools.runner import get_runner`
- Use Icarus Verilog as the simulator (`get_runner("icarus")`)
- The script must work from inside the item's `testbench/` directory
- Resolve project paths with `project_root = Path(__file__).resolve().parents[1]`
- Build the DUT from `project_root / "reference" / "top.v"` plus any support files listed below
- Top-level module name is `ADDB`
- If undefined backtick macros are listed below, add build-time `-DNAME=32` defines for them in the runner build args unless you can infer a better small integer value
- Include at least one reset/initialization check if the interface suggests reset exists
- If a signal may or may not exist, guard access with `hasattr(dut, "signal")`
- Avoid external data files, Makefiles, pytest, or shell calls
- Keep the testbench robust and concise

Implementation guidance:
- If there is a clock input, create a cocotb clock.
- If there is a reset input, drive reset first.
- Derive checks from the prompt and visible RTL behavior.
- Prefer checking observable outputs, state-related outputs, or handshake progress.
- If the prompt is vague, test the clearest core behavior visible in the RTL.
- The Python file should contain both the cocotb tests and a `if __name__ == "__main__":` runner section.

## Sample metadata
```json
{
  "task_id": "chip__ADDB__src___ADDB___15fcc13a37",
  "split": "train",
  "source_dataset": "lcm-rtl-code-annotations-by-gpt",
  "category": "fsm",
  "difficulty": "hard",
  "quality_tier": "compile_only",
  "module_name": "ADDB",
  "prompt_path": "prompt.txt",
  "module_header_path": "module_header.vh",
  "reference_top_path": "reference/top.v",
  "support_file_paths": [],
  "testbench_path": null,
  "compilation_verified": true,
  "simulation_verified": null,
  "metadata": {
    "raw_unit_dir": "/root/autodl-tmp/distill/lcm-dataset/chip/ADPCM_Processor/2.0.SingleResourceMCAC/ADDB/src/_ADDB_",
    "prompt_source": "spec/spec.txt",
    "screen_bucket": "standalone_leaf_hc",
    "prompt_word_count": 286,
    "token_count": 258
  }
}
```

## Source metadata
```json
{
  "item_id": "chip__ADDB__src___ADDB___15fcc13a37",
  "raw_path": "/root/autodl-tmp/distill/lcm-dataset/chip/ADPCM_Processor/2.0.SingleResourceMCAC/ADDB/src/_ADDB_",
  "main_v_file": "ADDB.v",
  "prompt_source": "spec/spec.txt",
  "source_dataset": "lcm-rtl-code-annotations-by-gpt"
}
```

## Verify metadata
```json
{
  "compilation_verified": true,
  "simulation_verified": null,
  "compile_log_path": "logs/compile.log",
  "compile_returncode": 0,
  "compile_error_summary": null
}
```

## Undefined macro warnings detected during prior compile
(none observed)

## Natural-language prompt
The ADDB module serves the purpose of conducting an arithmetic add operation between two given numbers. It uniquely processes two input numbers, DQ, a 16-bit input, and SE, a 15-bit input according to certain conditions before executing the addition operation. In addition, the module supports a scan testing system with scan_in and scan_out ports that are triggered in the test mode. The ADDB module operates on several input ports namely reset, clk, scan_in0, scan_in1, scan_in2, scan_in3, scan_in4, scan_enable, test_mode, DQ, and SE. The reset and clk signals are used for initiating and controlling the clock pulses respectively. The scan_in signals, along with scan_enable and test_mode, are provided for enabling the scan test mode. DQ and SE are the two main data inputs to be manipulated and used for the succeeding addition operation. The output ports include scan_out0, scan_out1, scan_out2, scan_out3, scan_out4, and SR. The scan_out ports are responsible for outputting the results from the scan testing, whilst SR stands as the endpoint for revealing the result of the performed addition. Internally, the ADDB module utilizes four signals, namely DQS, SES, DQI, and SEI for processing the operation. Both DQS and SES employ selective bits from DQ and SE respectively. DQI and SEI are derived signals based on conditions checked on DQS and SES respectively. The module operates in blocks where assign statements are used to compute internal and final results. DQS and SES select specific bits from DQ and SE inputs. Derived signals, DQI and SEI, are computed by processing DQ and SE through conditions checked on DQS and SES. Finally, the addition operation is executed on DQI and SEI to produce the sum 'SR', thereby completing the general feature of the ADDB module.

## Module header
```verilog
module ADDB (
           reset,
           clk,
           scan_in0,
           scan_in1,
           scan_in2,
           scan_in3,
           scan_in4,
           scan_enable,
           test_mode,
           scan_out0,
           scan_out1,
           scan_out2,
           scan_out3,
           scan_out4,
	   DQ,
	   SE,
	   SR
	   );
```

## Main RTL
```verilog
/*

Description : Adds quantized difference signal & signal estimate to get
    reconstructed signal

Author : Siddharth Ramkrishnan

Revision History :
//----------------------------------------------------------------------------------
2/12/16	-	Siddharth	- Initial creation
2/15/16	-	Siddharth	- Removal of Variable Size of DQ & Changes to improve Test Coverage
2/17/16	-	Adam		- Created an actual description, removed unncessary comma 
3/30/16	-	Siddharth	- Addition of comments to the (already easy to read) operations
//----------------------------------------------------------------------------------

*/

module ADDB (
           reset,
           clk,
           scan_in0,
           scan_in1,
           scan_in2,
           scan_in3,
           scan_in4,
           scan_enable,
           test_mode,
           scan_out0,
           scan_out1,
           scan_out2,
           scan_out3,
           scan_out4,
	   DQ,
	   SE,
	   SR
	   );

input
    reset,                      // system reSEt
    clk;                        // system clock

input
    scan_in0,                   // test scan mode data input
    scan_in1,                   // test scan mode data input
    scan_in2,                   // test scan mode data input
    scan_in3,                   // test scan mode data input
    scan_in4,                   // test scan mode data input
    scan_enable,                // test scan mode enable
    test_mode;                  // test mode 

output
    scan_out0,                  // test scan mode data output
    scan_out1,                  // test scan mode data output
    scan_out2,                  // test scan mode data output
    scan_out3,                  // test scan mode data output
    scan_out4;                  // test scan mode data output

input [15:0]
	DQ;

input [14:0]	
	SE;

output wire [15:0]
	SR;

wire
	DQS,
	SES;

wire [15:0] 
	DQI,
	SEI;

assign DQS	= DQ[15];									// Read the sign of DQ and update to DQS

assign DQI	= (DQS == 1'b0)	?	DQ	:	(65536 - ({1'b0,DQ[14:0]}))	;	// Convert DQ from Sign Magnitude to 2's Complement

assign SES	= SE[14];									// Read the sign of SE and update to SES
	
assign SEI	= (SES == 1'b0)	?	SE	:	(32768 + SE)	;			// Convert SE from 15 bit 2's complement to 16bits  

assign SR	= (DQI + SEI);									// 2's complement addition of DQ and SE

endmodule // ADDB

```

## Support RTL files
(none)