chip__ADV7513-Example__Verilog___pattern_vg___112318f044/module_header.vh

module pattern_vg
 #(
 parameter B=8, // number of bits per channel
 X_BITS=13,
 Y_BITS=13,
 FRACTIONAL_BITS = 12
 )
 (input reset, clk_in,
 input wire [X_BITS-1:0] x,
 input wire [Y_BITS-1:0] y,
 input wire vn_in, hn_in, dn_in,
 input wire [B-1:0] r_in, g_in, b_in,
 output reg vn_out, hn_out, den_out,
 output reg [B-1:0] r_out, g_out, b_out,
 input wire [X_BITS-1:0] total_active_pix,
 input wire [Y_BITS-1:0] total_active_lines,
 input wire [7:0] pattern,
 input wire [B+FRACTIONAL_BITS-1:0] ramp_step);