chip__ADV7513-Example__Verilog___pattern_vg___112318f044/testbench/sim_build/results.xml

<testsuites name="results">
  <testsuite name="all" package="all">
    <property name="random_seed" value="1774180228" />
    <testcase name="test_reset" classname="tb" file="/root/autodl-tmp/distill/distill-dataset/items/lcm-dataset-final-compile-only-v1/chip__ADV7513-Example__Verilog___pattern_vg___112318f044/testbench/tb.py" lineno="18" time="0.0006387233734130859" sim_time_ns="0" ratio_time="0.0">
      <failure error_type="ValueError" error_msg="Bad `period`: Unable to accurately represent 10(ns) with the simulator precision of 1e0" />
    </testcase>
    <testcase name="test_pattern_border" classname="tb" file="/root/autodl-tmp/distill/distill-dataset/items/lcm-dataset-final-compile-only-v1/chip__ADV7513-Example__Verilog___pattern_vg___112318f044/testbench/tb.py" lineno="58" time="0.00030732154846191406" sim_time_ns="0" ratio_time="0.0">
      <failure error_type="ValueError" error_msg="Bad `period`: Unable to accurately represent 10(ns) with the simulator precision of 1e0" />
    </testcase>
    <testcase name="test_pattern_moirex" classname="tb" file="/root/autodl-tmp/distill/distill-dataset/items/lcm-dataset-final-compile-only-v1/chip__ADV7513-Example__Verilog___pattern_vg___112318f044/testbench/tb.py" lineno="122" time="0.00023412704467773438" sim_time_ns="0" ratio_time="0.0">
      <failure error_type="ValueError" error_msg="Bad `period`: Unable to accurately represent 10(ns) with the simulator precision of 1e0" />
    </testcase>
    <testcase name="test_pattern_ramp" classname="tb" file="/root/autodl-tmp/distill/distill-dataset/items/lcm-dataset-final-compile-only-v1/chip__ADV7513-Example__Verilog___pattern_vg___112318f044/testbench/tb.py" lineno="162" time="0.00021791458129882812" sim_time_ns="0" ratio_time="0.0">
      <failure error_type="ValueError" error_msg="Bad `period`: Unable to accurately represent 10(ns) with the simulator precision of 1e0" />
    </testcase>
  </testsuite>
</testsuites>