chip__ADV7513-Example__Verilog___pattern_vg___112318f044/testbench/tb_result.json

{
  "item_id": "chip__ADV7513-Example__Verilog___pattern_vg___112318f044",
  "item_dir": "/root/autodl-tmp/distill/distill-dataset/items/lcm-dataset-final-meaningful-v1/chip__ADV7513-Example__Verilog___pattern_vg___112318f044",
  "module_name": "pattern_vg",
  "tb_path": "/root/autodl-tmp/distill/distill-dataset/items/lcm-dataset-final-meaningful-v1/chip__ADV7513-Example__Verilog___pattern_vg___112318f044/testbench/tb.py",
  "tb_prompt_path": "/root/autodl-tmp/distill/distill-dataset/items/lcm-dataset-final-meaningful-v1/chip__ADV7513-Example__Verilog___pattern_vg___112318f044/testbench/tb_prompt.txt",
  "tb_response_path": "/root/autodl-tmp/distill/distill-dataset/items/lcm-dataset-final-meaningful-v1/chip__ADV7513-Example__Verilog___pattern_vg___112318f044/testbench/tb_response.txt",
  "tb_run_log_path": "/root/autodl-tmp/distill/distill-dataset/items/lcm-dataset-final-meaningful-v1/chip__ADV7513-Example__Verilog___pattern_vg___112318f044/testbench/tb_run.log",
  "attempt": 1,
  "thinking_budget": 1024,
  "returncode": 0,
  "passed": true,
  "final": true,
  "retrying_to_budget": null,
  "error": null,
  "cached": null
}