chip__ADV7513-Example__Verilog___pattern_vg___5940205a5d/testbench/sim_build/results.xml

<testsuites name="results">
  <testsuite name="all" package="all">
    <property name="random_seed" value="1774180230" />
    <testcase name="test_reset_and_control_signals" classname="tb" file="/root/autodl-tmp/distill/distill-dataset/items/lcm-dataset-final-compile-only-v1/chip__ADV7513-Example__Verilog___pattern_vg___5940205a5d/testbench/tb.py" lineno="31" time="0.0007243156433105469" sim_time_ns="0" ratio_time="0.0">
      <failure error_type="ValueError" error_msg="Bad `period`: Unable to accurately represent 10(ns) with the simulator precision of 1e0" />
    </testcase>
    <testcase name="test_pattern_0_no_pattern" classname="tb" file="/root/autodl-tmp/distill/distill-dataset/items/lcm-dataset-final-compile-only-v1/chip__ADV7513-Example__Verilog___pattern_vg___5940205a5d/testbench/tb.py" lineno="60" time="0.0003209114074707031" sim_time_ns="0" ratio_time="0.0">
      <failure error_type="ValueError" error_msg="Bad `period`: Unable to accurately represent 10(ns) with the simulator precision of 1e0" />
    </testcase>
    <testcase name="test_pattern_1_border" classname="tb" file="/root/autodl-tmp/distill/distill-dataset/items/lcm-dataset-final-compile-only-v1/chip__ADV7513-Example__Verilog___pattern_vg___5940205a5d/testbench/tb.py" lineno="91" time="0.0002694129943847656" sim_time_ns="0" ratio_time="0.0">
      <failure error_type="ValueError" error_msg="Bad `period`: Unable to accurately represent 10(ns) with the simulator precision of 1e0" />
    </testcase>
    <testcase name="test_pattern_2_moirex" classname="tb" file="/root/autodl-tmp/distill/distill-dataset/items/lcm-dataset-final-compile-only-v1/chip__ADV7513-Example__Verilog___pattern_vg___5940205a5d/testbench/tb.py" lineno="147" time="0.0002582073211669922" sim_time_ns="0" ratio_time="0.0">
      <failure error_type="ValueError" error_msg="Bad `period`: Unable to accurately represent 10(ns) with the simulator precision of 1e0" />
    </testcase>
    <testcase name="test_pattern_4_ramp" classname="tb" file="/root/autodl-tmp/distill/distill-dataset/items/lcm-dataset-final-compile-only-v1/chip__ADV7513-Example__Verilog___pattern_vg___5940205a5d/testbench/tb.py" lineno="184" time="0.0002989768981933594" sim_time_ns="0" ratio_time="0.0">
      <failure error_type="ValueError" error_msg="Bad `period`: Unable to accurately represent 10(ns) with the simulator precision of 1e0" />
    </testcase>
  </testsuite>
</testsuites>