diff --git "a/cvdp_expert_problems.json" "b/cvdp_expert_problems.json" new file mode 100644--- /dev/null +++ "b/cvdp_expert_problems.json" @@ -0,0 +1,2379 @@ +[ + { + "id": "cvdp_agentic_DES_0005", + "index": 497, + "source_config": "cvdp_agentic_code_generation_no_commercial", + "instruction": "Context: You are a language model that has the following file operations available at your disposal:\n - **List files in a directory** by running one of the following commands: \n - `ls`\n - `tree`\n - **Read files** by using:\n - `cat `\n - **Write files** by using:\n - `echo > `\n - **Compile Verilog** by using `iverilog` such as:\n - `iverilog -o .out -g2012 `\n - **Run Simulation** by using:\n - `vvp .out`\n - **Find current working directory** by using:\n - `pwd`\n - **Update the contents of a text file from a old content to new content**\n - `sed -i \"line_number s/old_statement/new_statement/\" file.sv`\n - **To access a specific line of the file**\n - `awk 'NR==line_number' file_name.sv`\n\nYou will be given a prompt and your task is to understand it and solve the given issue by using the above-mentioned commands as needed. In the final step, you should create a Linux patch to highlight the necessary file updates to achieve the targeted goal.\n\n You will solve the problem step by step using the following approach of \n - thought (thinking process of the step you're going to take)\n - action (the command you will be running to get more details/context that's helpful to solve the problem)\n - observation (the output from the action you will observe based on which you will take your next step)\n\n The last step will be the final output summary and the patch itself in the following format \n - thought (the summary of what you did and some introduction of the patch file itself)\n - patch (a Linux-based patch that needs to be applied to reach the relevant solution)\n\nTask: Integrate the `des_enc` and `des_dec` modules to perform the Triple Data Encryption Standard (TDES) encryption. This new module must allow burst operation, where in multiple cycles in a row the valid signal can be asserted with a new data and a new key. No changes are required in any of the RTLs provided. A testbench for this module is available at `verif/tb_3des_enc.sv`.\n\n---\n\n## Specifications\n\n- **Module Name**: `des3_enc`\n\n- **File Name**: `des3_enc.sv` (to be added in `rtl` directory)\n\n- **Parameters**:\n - `NBW_DATA`: Bit width of the input and output data blocks.\n - Default: 64.\n - Related interface signals: `i_data`, `o_data`.\n - `NBW_KEY`: Bit width of the key.\n - Default: 192.\n - Related interface signal: `i_key`. \n - The 192-bit key is interpreted as three concatenated 64-bit DES keys (K1, K2, K3) used for Triple DES encryption, where `K1 = i_key[1:64]`, K2 = `i_key[65:128]`, and `K3 = i_key[129:192]`.\n\n- **Functionality**: Implements 3DES encryption in EDE (Encrypt-Decrypt-Encrypt) mode using three 64-bit keys (K1, K2, K3). The input plaintext is encrypted with K1, decrypted with K2, and encrypted again with K3.\n\n- **Latency**: The block's latency, from when `i_valid` is read until `o_valid` is asserted, is **48 cycles**, where each DES stage takes 16 cycles and the process is fully pipelined.\n\n---\n\n## Interface Signals\n\n | Signal | Direction | Width | Description |\n |---------------------|-----------|------------------|--------------------------------------------------------------------------------------------------------------------- |\n | `clk` | Input | 1 | Drives the sequential logic on the rising edge. |\n | `rst_async_n` | Input | 1 | Active-low asynchronous reset; clears all internal registers and state. |\n | `i_valid` | Input | 1 | Active high. Indicates that `i_data` and `i_key` are valid and ready to be processed. |\n | `i_data` | Input | [1:NBW_DATA] | 64-bit plaintext input block (MSB-first). |\n | `i_key` | Input | [1:NBW_KEY] | 192-bit 3DES key, treated as three concatenated 64-bit keys: `{K1, K2, K3}`. |\n | `o_valid` | Output | 1 | Asserted high when `o_data` contains valid encrypted data. It is asserted for as many cycles as `i_valid` is asserted. |\n | `o_data` | Output | [1:NBW_DATA] | 64-bit ciphertext output block (MSB-first). |", + "verilog_code": { + "code_block_2_0": "module must allow burst operation, where in multiple cycles in a row the valid signal can be asserted with a new data and a new key. No changes are required in any of the RTLs provided. A testbench for this module is available at `verif/tb_3des_enc.sv`.\n\n---\n\n## Specifications\n\n- **Module Name**: `des3_enc`\n\n- **File Name**: `des3_enc.sv` (to be added in `rtl` directory)\n\n- **Parameters**:\n - `NBW_DATA`: Bit width of the input and output data blocks.\n - Default: 64.\n - Related interface signals: `i_data`, `o_data`.\n - `NBW_KEY`: Bit width of the key.\n - Default: 192.\n - Related interface signal: `i_key`. \n - The 192-bit key is interpreted as three concatenated 64-bit DES keys (K1, K2, K3) used for Triple DES encryption, where `K1 = i_key[1:64]`, K2 = `i_key[65:128]`, and `K3 = i_key[129:192]`.\n\n- **Functionality**: Implements 3DES encryption in EDE (Encrypt-Decrypt-Encrypt) mode using three 64-bit keys (K1, K2, K3). The input plaintext is encrypted with K1, decrypted with K2, and encrypted again with K3.\n\n- **Latency**: The block's latency, from when `i_valid` is read until `o_valid` is asserted, is **48 cycles**, where each DES stage takes 16 cycles and the process is fully pipelined.\n\n---\n\n## Interface Signals\n\n | Signal | Direction | Width | Description |\n |---------------------|-----------|------------------|--------------------------------------------------------------------------------------------------------------------- |\n | `clk` | Input | 1 | Drives the sequential logic on the rising edge. |\n | `rst_async_n` | Input | 1 | Active-low asynchronous reset; clears all internal registers and state. |\n | `i_valid` | Input | 1 | Active high. Indicates that `i_data` and `i_key` are valid and ready to be processed. |\n | `i_data` | Input | [1:NBW_DATA] | 64-bit plaintext input block (MSB-first). |\n | `i_key` | Input | [1:NBW_KEY] | 192-bit 3DES key, treated as three concatenated 64-bit keys: `{K1, K2, K3}`. |\n | `o_valid` | Output | 1 | Asserted high when `o_data` contains valid encrypted data. It is asserted for as many cycles as `i_valid` is asserted. |\n | `o_data` | Output | [1:NBW_DATA] | 64-bit ciphertext output block (MSB-first). |", + "code_block_2_1": "module S1(\\n input logic [5:0] i_data,\\n output logic [3:0] o_data\\n);\\n\\nalways_comb begin\\n case (i_data)\\n 6'b0_0000_0 : o_data = 4'd14;\\n 6'b0_0001_0 : o_data = 4'd4;\\n 6'b0_0010_0 : o_data = 4'd13;\\n 6'b0_0011_0 : o_data = 4'd1;\\n 6'b0_0100_0 : o_data = 4'd2;\\n 6'b0_0101_0 : o_data = 4'd15;\\n 6'b0_0110_0 : o_data = 4'd11;\\n 6'b0_0111_0 : o_data = 4'd8;\\n 6'b0_1000_0 : o_data = 4'd3;\\n 6'b0_1001_0 : o_data = 4'd10;\\n 6'b0_1010_0 : o_data = 4'd6;\\n 6'b0_1011_0 : o_data = 4'd12;\\n 6'b0_1100_0 : o_data = 4'd5;\\n 6'b0_1101_0 : o_data = 4'd9;\\n 6'b0_1110_0 : o_data = 4'd0;\\n 6'b0_1111_0 : o_data = 4'd7;\\n 6'b0_0000_1 : o_data = 4'd0;\\n 6'b0_0001_1 : o_data = 4'd15;\\n 6'b0_0010_1 : o_data = 4'd7;\\n 6'b0_0011_1 : o_data = 4'd4;\\n 6'b0_0100_1 : o_data = 4'd14;\\n 6'b0_0101_1 : o_data = 4'd2;\\n 6'b0_0110_1 : o_data = 4'd13;\\n 6'b0_0111_1 : o_data = 4'd1;\\n 6'b0_1000_1 : o_data = 4'd10;\\n 6'b0_1001_1 : o_data = 4'd6;\\n 6'b0_1010_1 : o_data = 4'd12;\\n 6'b0_1011_1 : o_data = 4'd11;\\n 6'b0_1100_1 : o_data = 4'd9;\\n 6'b0_1101_1 : o_data = 4'd5;\\n 6'b0_1110_1 : o_data = 4'd3;\\n 6'b0_1111_1 : o_data = 4'd8;\\n 6'b1_0000_0 : o_data = 4'd4;\\n 6'b1_0001_0 : o_data = 4'd1;\\n 6'b1_0010_0 : o_data = 4'd14;\\n 6'b1_0011_0 : o_data = 4'd8;\\n 6'b1_0100_0 : o_data = 4'd13;\\n 6'b1_0101_0 : o_data = 4'd6;\\n 6'b1_0110_0 : o_data = 4'd2;\\n 6'b1_0111_0 : o_data = 4'd11;\\n 6'b1_1000_0 : o_data = 4'd15;\\n 6'b1_1001_0 : o_data = 4'd12;\\n 6'b1_1010_0 : o_data = 4'd9;\\n 6'b1_1011_0 : o_data = 4'd7;\\n 6'b1_1100_0 : o_data = 4'd3;\\n 6'b1_1101_0 : o_data = 4'd10;\\n 6'b1_1110_0 : o_data = 4'd5;\\n 6'b1_1111_0 : o_data = 4'd0;\\n 6'b1_0000_1 : o_data = 4'd15;\\n 6'b1_0001_1 : o_data = 4'd12;\\n 6'b1_0010_1 : o_data = 4'd8;\\n 6'b1_0011_1 : o_data = 4'd2;\\n 6'b1_0100_1 : o_data = 4'd4;\\n 6'b1_0101_1 : o_data = 4'd9;\\n 6'b1_0110_1 : o_data = 4'd1;\\n 6'b1_0111_1 : o_data = 4'd7;\\n 6'b1_1000_1 : o_data = 4'd5;\\n 6'b1_1001_1 : o_data = 4'd11;\\n 6'b1_1010_1 : o_data = 4'd3;\\n 6'b1_1011_1 : o_data = 4'd14;\\n 6'b1_1100_1 : o_data = 4'd10;\\n 6'b1_1101_1 : o_data = 4'd0;\\n 6'b1_1110_1 : o_data = 4'd6;\\n 6'b1_1111_1 : o_data = 4'd13;\\n default: o_data = 4'd0;\\n endcase\\nend\\n\\nendmodule : S1\", 'rtl/S2.sv': \"module S2(\\n input logic [5:0] i_data,\\n output logic [3:0] o_data\\n);\\n\\nalways_comb begin\\n case (i_data)\\n 6'b0_0000_0 : o_data = 4'd15;\\n 6'b0_0001_0 : o_data = 4'd1;\\n 6'b0_0010_0 : o_data = 4'd8;\\n 6'b0_0011_0 : o_data = 4'd14;\\n 6'b0_0100_0 : o_data = 4'd6;\\n 6'b0_0101_0 : o_data = 4'd11;\\n 6'b0_0110_0 : o_data = 4'd3;\\n 6'b0_0111_0 : o_data = 4'd4;\\n 6'b0_1000_0 : o_data = 4'd9;\\n 6'b0_1001_0 : o_data = 4'd7;\\n 6'b0_1010_0 : o_data = 4'd2;\\n 6'b0_1011_0 : o_data = 4'd13;\\n 6'b0_1100_0 : o_data = 4'd12;\\n 6'b0_1101_0 : o_data = 4'd0;\\n 6'b0_1110_0 : o_data = 4'd5;\\n 6'b0_1111_0 : o_data = 4'd10;\\n 6'b0_0000_1 : o_data = 4'd3;\\n 6'b0_0001_1 : o_data = 4'd13;\\n 6'b0_0010_1 : o_data = 4'd4;\\n 6'b0_0011_1 : o_data = 4'd7;\\n 6'b0_0100_1 : o_data = 4'd15;\\n 6'b0_0101_1 : o_data = 4'd2;\\n 6'b0_0110_1 : o_data = 4'd8;\\n 6'b0_0111_1 : o_data = 4'd14;\\n 6'b0_1000_1 : o_data = 4'd12;\\n 6'b0_1001_1 : o_data = 4'd0;\\n 6'b0_1010_1 : o_data = 4'd1;\\n 6'b0_1011_1 : o_data = 4'd10;\\n 6'b0_1100_1 : o_data = 4'd6;\\n 6'b0_1101_1 : o_data = 4'd9;\\n 6'b0_1110_1 : o_data = 4'd11;\\n 6'b0_1111_1 : o_data = 4'd5;\\n 6'b1_0000_0 : o_data = 4'd0;\\n 6'b1_0001_0 : o_data = 4'd14;\\n 6'b1_0010_0 : o_data = 4'd7;\\n 6'b1_0011_0 : o_data = 4'd11;\\n 6'b1_0100_0 : o_data = 4'd10;\\n 6'b1_0101_0 : o_data = 4'd4;\\n 6'b1_0110_0 : o_data = 4'd13;\\n 6'b1_0111_0 : o_data = 4'd1;\\n 6'b1_1000_0 : o_data = 4'd5;\\n 6'b1_1001_0 : o_data = 4'd8;\\n 6'b1_1010_0 : o_data = 4'd12;\\n 6'b1_1011_0 : o_data = 4'd6;\\n 6'b1_1100_0 : o_data = 4'd9;\\n 6'b1_1101_0 : o_data = 4'd3;\\n 6'b1_1110_0 : o_data = 4'd2;\\n 6'b1_1111_0 : o_data = 4'd15;\\n 6'b1_0000_1 : o_data = 4'd13;\\n 6'b1_0001_1 : o_data = 4'd8;\\n 6'b1_0010_1 : o_data = 4'd10;\\n 6'b1_0011_1 : o_data = 4'd1;\\n 6'b1_0100_1 : o_data = 4'd3;\\n 6'b1_0101_1 : o_data = 4'd15;\\n 6'b1_0110_1 : o_data = 4'd4;\\n 6'b1_0111_1 : o_data = 4'd2;\\n 6'b1_1000_1 : o_data = 4'd11;\\n 6'b1_1001_1 : o_data = 4'd6;\\n 6'b1_1010_1 : o_data = 4'd7;\\n 6'b1_1011_1 : o_data = 4'd12;\\n 6'b1_1100_1 : o_data = 4'd0;\\n 6'b1_1101_1 : o_data = 4'd5;\\n 6'b1_1110_1 : o_data = 4'd14;\\n 6'b1_1111_1 : o_data = 4'd9;\\n default: o_data = 4'd0;\\n endcase\\nend\\n\\nendmodule : S2\", 'rtl/S3.sv': \"module S3(\\n input logic [5:0] i_data,\\n output logic [3:0] o_data\\n);\\n\\nalways_comb begin\\n case (i_data)\\n 6'b0_0000_0 : o_data = 4'd10;\\n 6'b0_0001_0 : o_data = 4'd0;\\n 6'b0_0010_0 : o_data = 4'd9;\\n 6'b0_0011_0 : o_data = 4'd14;\\n 6'b0_0100_0 : o_data = 4'd6;\\n 6'b0_0101_0 : o_data = 4'd3;\\n 6'b0_0110_0 : o_data = 4'd15;\\n 6'b0_0111_0 : o_data = 4'd5;\\n 6'b0_1000_0 : o_data = 4'd1;\\n 6'b0_1001_0 : o_data = 4'd13;\\n 6'b0_1010_0 : o_data = 4'd12;\\n 6'b0_1011_0 : o_data = 4'd7;\\n 6'b0_1100_0 : o_data = 4'd11;\\n 6'b0_1101_0 : o_data = 4'd4;\\n 6'b0_1110_0 : o_data = 4'd2;\\n 6'b0_1111_0 : o_data = 4'd8;\\n 6'b0_0000_1 : o_data = 4'd13;\\n 6'b0_0001_1 : o_data = 4'd7;\\n 6'b0_0010_1 : o_data = 4'd0;\\n 6'b0_0011_1 : o_data = 4'd9;\\n 6'b0_0100_1 : o_data = 4'd3;\\n 6'b0_0101_1 : o_data = 4'd4;\\n 6'b0_0110_1 : o_data = 4'd6;\\n 6'b0_0111_1 : o_data = 4'd10;\\n 6'b0_1000_1 : o_data = 4'd2;\\n 6'b0_1001_1 : o_data = 4'd8;\\n 6'b0_1010_1 : o_data = 4'd5;\\n 6'b0_1011_1 : o_data = 4'd14;\\n 6'b0_1100_1 : o_data = 4'd12;\\n 6'b0_1101_1 : o_data = 4'd11;\\n 6'b0_1110_1 : o_data = 4'd15;\\n 6'b0_1111_1 : o_data = 4'd1;\\n 6'b1_0000_0 : o_data = 4'd13;\\n 6'b1_0001_0 : o_data = 4'd6;\\n 6'b1_0010_0 : o_data = 4'd4;\\n 6'b1_0011_0 : o_data = 4'd9;\\n 6'b1_0100_0 : o_data = 4'd8;\\n 6'b1_0101_0 : o_data = 4'd15;\\n 6'b1_0110_0 : o_data = 4'd3;\\n 6'b1_0111_0 : o_data = 4'd0;\\n 6'b1_1000_0 : o_data = 4'd11;\\n 6'b1_1001_0 : o_data = 4'd1;\\n 6'b1_1010_0 : o_data = 4'd2;\\n 6'b1_1011_0 : o_data = 4'd12;\\n 6'b1_1100_0 : o_data = 4'd5;\\n 6'b1_1101_0 : o_data = 4'd10;\\n 6'b1_1110_0 : o_data = 4'd14;\\n 6'b1_1111_0 : o_data = 4'd7;\\n 6'b1_0000_1 : o_data = 4'd1;\\n 6'b1_0001_1 : o_data = 4'd10;\\n 6'b1_0010_1 : o_data = 4'd13;\\n 6'b1_0011_1 : o_data = 4'd0;\\n 6'b1_0100_1 : o_data = 4'd6;\\n 6'b1_0101_1 : o_data = 4'd9;\\n 6'b1_0110_1 : o_data = 4'd8;\\n 6'b1_0111_1 : o_data = 4'd7;\\n 6'b1_1000_1 : o_data = 4'd4;\\n 6'b1_1001_1 : o_data = 4'd15;\\n 6'b1_1010_1 : o_data = 4'd14;\\n 6'b1_1011_1 : o_data = 4'd3;\\n 6'b1_1100_1 : o_data = 4'd11;\\n 6'b1_1101_1 : o_data = 4'd5;\\n 6'b1_1110_1 : o_data = 4'd2;\\n 6'b1_1111_1 : o_data = 4'd12;\\n default: o_data = 4'd0;\\n endcase\\nend\\n\\nendmodule : S3\", 'rtl/S4.sv': \"module S4(\\n input logic [5:0] i_data,\\n output logic [3:0] o_data\\n);\\n\\nalways_comb begin\\n case (i_data)\\n 6'b0_0000_0 : o_data = 4'd7;\\n 6'b0_0001_0 : o_data = 4'd13;\\n 6'b0_0010_0 : o_data = 4'd14;\\n 6'b0_0011_0 : o_data = 4'd3;\\n 6'b0_0100_0 : o_data = 4'd0;\\n 6'b0_0101_0 : o_data = 4'd6;\\n 6'b0_0110_0 : o_data = 4'd9;\\n 6'b0_0111_0 : o_data = 4'd10;\\n 6'b0_1000_0 : o_data = 4'd1;\\n 6'b0_1001_0 : o_data = 4'd2;\\n 6'b0_1010_0 : o_data = 4'd8;\\n 6'b0_1011_0 : o_data = 4'd5;\\n 6'b0_1100_0 : o_data = 4'd11;\\n 6'b0_1101_0 : o_data = 4'd12;\\n 6'b0_1110_0 : o_data = 4'd4;\\n 6'b0_1111_0 : o_data = 4'd15;\\n 6'b0_0000_1 : o_data = 4'd13;\\n 6'b0_0001_1 : o_data = 4'd8;\\n 6'b0_0010_1 : o_data = 4'd11;\\n 6'b0_0011_1 : o_data = 4'd5;\\n 6'b0_0100_1 : o_data = 4'd6;\\n 6'b0_0101_1 : o_data = 4'd15;\\n 6'b0_0110_1 : o_data = 4'd0;\\n 6'b0_0111_1 : o_data = 4'd3;\\n 6'b0_1000_1 : o_data = 4'd4;\\n 6'b0_1001_1 : o_data = 4'd7;\\n 6'b0_1010_1 : o_data = 4'd2;\\n 6'b0_1011_1 : o_data = 4'd12;\\n 6'b0_1100_1 : o_data = 4'd1;\\n 6'b0_1101_1 : o_data = 4'd10;\\n 6'b0_1110_1 : o_data = 4'd14;\\n 6'b0_1111_1 : o_data = 4'd9;\\n 6'b1_0000_0 : o_data = 4'd10;\\n 6'b1_0001_0 : o_data = 4'd6;\\n 6'b1_0010_0 : o_data = 4'd9;\\n 6'b1_0011_0 : o_data = 4'd0;\\n 6'b1_0100_0 : o_data = 4'd12;\\n 6'b1_0101_0 : o_data = 4'd11;\\n 6'b1_0110_0 : o_data = 4'd7;\\n 6'b1_0111_0 : o_data = 4'd13;\\n 6'b1_1000_0 : o_data = 4'd15;\\n 6'b1_1001_0 : o_data = 4'd1;\\n 6'b1_1010_0 : o_data = 4'd3;\\n 6'b1_1011_0 : o_data = 4'd14;\\n 6'b1_1100_0 : o_data = 4'd5;\\n 6'b1_1101_0 : o_data = 4'd2;\\n 6'b1_1110_0 : o_data = 4'd8;\\n 6'b1_1111_0 : o_data = 4'd4;\\n 6'b1_0000_1 : o_data = 4'd3;\\n 6'b1_0001_1 : o_data = 4'd15;\\n 6'b1_0010_1 : o_data = 4'd0;\\n 6'b1_0011_1 : o_data = 4'd6;\\n 6'b1_0100_1 : o_data = 4'd10;\\n 6'b1_0101_1 : o_data = 4'd1;\\n 6'b1_0110_1 : o_data = 4'd13;\\n 6'b1_0111_1 : o_data = 4'd8;\\n 6'b1_1000_1 : o_data = 4'd9;\\n 6'b1_1001_1 : o_data = 4'd4;\\n 6'b1_1010_1 : o_data = 4'd5;\\n 6'b1_1011_1 : o_data = 4'd11;\\n 6'b1_1100_1 : o_data = 4'd12;\\n 6'b1_1101_1 : o_data = 4'd7;\\n 6'b1_1110_1 : o_data = 4'd2;\\n 6'b1_1111_1 : o_data = 4'd14;\\n default: o_data = 4'd0;\\n endcase\\nend\\n\\nendmodule : S4\", 'rtl/S5.sv': \"module S5(\\n input logic [5:0] i_data,\\n output logic [3:0] o_data\\n);\\n\\nalways_comb begin\\n case (i_data)\\n 6'b0_0000_0 : o_data = 4'd2;\\n 6'b0_0001_0 : o_data = 4'd12;\\n 6'b0_0010_0 : o_data = 4'd4;\\n 6'b0_0011_0 : o_data = 4'd1;\\n 6'b0_0100_0 : o_data = 4'd7;\\n 6'b0_0101_0 : o_data = 4'd10;\\n 6'b0_0110_0 : o_data = 4'd11;\\n 6'b0_0111_0 : o_data = 4'd6;\\n 6'b0_1000_0 : o_data = 4'd8;\\n 6'b0_1001_0 : o_data = 4'd5;\\n 6'b0_1010_0 : o_data = 4'd3;\\n 6'b0_1011_0 : o_data = 4'd15;\\n 6'b0_1100_0 : o_data = 4'd13;\\n 6'b0_1101_0 : o_data = 4'd0;\\n 6'b0_1110_0 : o_data = 4'd14;\\n 6'b0_1111_0 : o_data = 4'd9;\\n 6'b0_0000_1 : o_data = 4'd14;\\n 6'b0_0001_1 : o_data = 4'd11;\\n 6'b0_0010_1 : o_data = 4'd2;\\n 6'b0_0011_1 : o_data = 4'd12;\\n 6'b0_0100_1 : o_data = 4'd4;\\n 6'b0_0101_1 : o_data = 4'd7;\\n 6'b0_0110_1 : o_data = 4'd13;\\n 6'b0_0111_1 : o_data = 4'd1;\\n 6'b0_1000_1 : o_data = 4'd5;\\n 6'b0_1001_1 : o_data = 4'd0;\\n 6'b0_1010_1 : o_data = 4'd15;\\n 6'b0_1011_1 : o_data = 4'd10;\\n 6'b0_1100_1 : o_data = 4'd3;\\n 6'b0_1101_1 : o_data = 4'd9;\\n 6'b0_1110_1 : o_data = 4'd8;\\n 6'b0_1111_1 : o_data = 4'd6;\\n 6'b1_0000_0 : o_data = 4'd4;\\n 6'b1_0001_0 : o_data = 4'd2;\\n 6'b1_0010_0 : o_data = 4'd1;\\n 6'b1_0011_0 : o_data = 4'd11;\\n 6'b1_0100_0 : o_data = 4'd10;\\n 6'b1_0101_0 : o_data = 4'd13;\\n 6'b1_0110_0 : o_data = 4'd7;\\n 6'b1_0111_0 : o_data = 4'd8;\\n 6'b1_1000_0 : o_data = 4'd15;\\n 6'b1_1001_0 : o_data = 4'd9;\\n 6'b1_1010_0 : o_data = 4'd12;\\n 6'b1_1011_0 : o_data = 4'd5;\\n 6'b1_1100_0 : o_data = 4'd6;\\n 6'b1_1101_0 : o_data = 4'd3;\\n 6'b1_1110_0 : o_data = 4'd0;\\n 6'b1_1111_0 : o_data = 4'd14;\\n 6'b1_0000_1 : o_data = 4'd11;\\n 6'b1_0001_1 : o_data = 4'd8;\\n 6'b1_0010_1 : o_data = 4'd12;\\n 6'b1_0011_1 : o_data = 4'd7;\\n 6'b1_0100_1 : o_data = 4'd1;\\n 6'b1_0101_1 : o_data = 4'd14;\\n 6'b1_0110_1 : o_data = 4'd2;\\n 6'b1_0111_1 : o_data = 4'd13;\\n 6'b1_1000_1 : o_data = 4'd6;\\n 6'b1_1001_1 : o_data = 4'd15;\\n 6'b1_1010_1 : o_data = 4'd0;\\n 6'b1_1011_1 : o_data = 4'd9;\\n 6'b1_1100_1 : o_data = 4'd10;\\n 6'b1_1101_1 : o_data = 4'd4;\\n 6'b1_1110_1 : o_data = 4'd5;\\n 6'b1_1111_1 : o_data = 4'd3;\\n default: o_data = 4'd0;\\n endcase\\nend\\n\\nendmodule : S5\", 'rtl/S6.sv': \"module S6(\\n input logic [5:0] i_data,\\n output logic [3:0] o_data\\n);\\n\\nalways_comb begin\\n case (i_data)\\n 6'b0_0000_0 : o_data = 4'd12;\\n 6'b0_0001_0 : o_data = 4'd1;\\n 6'b0_0010_0 : o_data = 4'd10;\\n 6'b0_0011_0 : o_data = 4'd15;\\n 6'b0_0100_0 : o_data = 4'd9;\\n 6'b0_0101_0 : o_data = 4'd2;\\n 6'b0_0110_0 : o_data = 4'd6;\\n 6'b0_0111_0 : o_data = 4'd8;\\n 6'b0_1000_0 : o_data = 4'd0;\\n 6'b0_1001_0 : o_data = 4'd13;\\n 6'b0_1010_0 : o_data = 4'd3;\\n 6'b0_1011_0 : o_data = 4'd4;\\n 6'b0_1100_0 : o_data = 4'd14;\\n 6'b0_1101_0 : o_data = 4'd7;\\n 6'b0_1110_0 : o_data = 4'd5;\\n 6'b0_1111_0 : o_data = 4'd11;\\n 6'b0_0000_1 : o_data = 4'd10;\\n 6'b0_0001_1 : o_data = 4'd15;\\n 6'b0_0010_1 : o_data = 4'd4;\\n 6'b0_0011_1 : o_data = 4'd2;\\n 6'b0_0100_1 : o_data = 4'd7;\\n 6'b0_0101_1 : o_data = 4'd12;\\n 6'b0_0110_1 : o_data = 4'd9;\\n 6'b0_0111_1 : o_data = 4'd5;\\n 6'b0_1000_1 : o_data = 4'd6;\\n 6'b0_1001_1 : o_data = 4'd1;\\n 6'b0_1010_1 : o_data = 4'd13;\\n 6'b0_1011_1 : o_data = 4'd14;\\n 6'b0_1100_1 : o_data = 4'd0;\\n 6'b0_1101_1 : o_data = 4'd11;\\n 6'b0_1110_1 : o_data = 4'd3;\\n 6'b0_1111_1 : o_data = 4'd8;\\n 6'b1_0000_0 : o_data = 4'd9;\\n 6'b1_0001_0 : o_data = 4'd14;\\n 6'b1_0010_0 : o_data = 4'd15;\\n 6'b1_0011_0 : o_data = 4'd5;\\n 6'b1_0100_0 : o_data = 4'd2;\\n 6'b1_0101_0 : o_data = 4'd8;\\n 6'b1_0110_0 : o_data = 4'd12;\\n 6'b1_0111_0 : o_data = 4'd3;\\n 6'b1_1000_0 : o_data = 4'd7;\\n 6'b1_1001_0 : o_data = 4'd0;\\n 6'b1_1010_0 : o_data = 4'd4;\\n 6'b1_1011_0 : o_data = 4'd10;\\n 6'b1_1100_0 : o_data = 4'd1;\\n 6'b1_1101_0 : o_data = 4'd13;\\n 6'b1_1110_0 : o_data = 4'd11;\\n 6'b1_1111_0 : o_data = 4'd6;\\n 6'b1_0000_1 : o_data = 4'd4;\\n 6'b1_0001_1 : o_data = 4'd3;\\n 6'b1_0010_1 : o_data = 4'd2;\\n 6'b1_0011_1 : o_data = 4'd12;\\n 6'b1_0100_1 : o_data = 4'd9;\\n 6'b1_0101_1 : o_data = 4'd5;\\n 6'b1_0110_1 : o_data = 4'd15;\\n 6'b1_0111_1 : o_data = 4'd10;\\n 6'b1_1000_1 : o_data = 4'd11;\\n 6'b1_1001_1 : o_data = 4'd14;\\n 6'b1_1010_1 : o_data = 4'd1;\\n 6'b1_1011_1 : o_data = 4'd7;\\n 6'b1_1100_1 : o_data = 4'd6;\\n 6'b1_1101_1 : o_data = 4'd0;\\n 6'b1_1110_1 : o_data = 4'd8;\\n 6'b1_1111_1 : o_data = 4'd13;\\n default: o_data = 4'd0;\\n endcase\\nend\\n\\nendmodule : S6\", 'rtl/S7.sv': \"module S7(\\n input logic [5:0] i_data,\\n output logic [3:0] o_data\\n);\\n\\nalways_comb begin\\n case (i_data)\\n 6'b0_0000_0 : o_data = 4'd4;\\n 6'b0_0001_0 : o_data = 4'd11;\\n 6'b0_0010_0 : o_data = 4'd2;\\n 6'b0_0011_0 : o_data = 4'd14;\\n 6'b0_0100_0 : o_data = 4'd15;\\n 6'b0_0101_0 : o_data = 4'd0;\\n 6'b0_0110_0 : o_data = 4'd8;\\n 6'b0_0111_0 : o_data = 4'd13;\\n 6'b0_1000_0 : o_data = 4'd3;\\n 6'b0_1001_0 : o_data = 4'd12;\\n 6'b0_1010_0 : o_data = 4'd9;\\n 6'b0_1011_0 : o_data = 4'd7;\\n 6'b0_1100_0 : o_data = 4'd5;\\n 6'b0_1101_0 : o_data = 4'd10;\\n 6'b0_1110_0 : o_data = 4'd6;\\n 6'b0_1111_0 : o_data = 4'd1;\\n 6'b0_0000_1 : o_data = 4'd13;\\n 6'b0_0001_1 : o_data = 4'd0;\\n 6'b0_0010_1 : o_data = 4'd11;\\n 6'b0_0011_1 : o_data = 4'd7;\\n 6'b0_0100_1 : o_data = 4'd4;\\n 6'b0_0101_1 : o_data = 4'd9;\\n 6'b0_0110_1 : o_data = 4'd1;\\n 6'b0_0111_1 : o_data = 4'd10;\\n 6'b0_1000_1 : o_data = 4'd14;\\n 6'b0_1001_1 : o_data = 4'd3;\\n 6'b0_1010_1 : o_data = 4'd5;\\n 6'b0_1011_1 : o_data = 4'd12;\\n 6'b0_1100_1 : o_data = 4'd2;\\n 6'b0_1101_1 : o_data = 4'd15;\\n 6'b0_1110_1 : o_data = 4'd8;\\n 6'b0_1111_1 : o_data = 4'd6;\\n 6'b1_0000_0 : o_data = 4'd1;\\n 6'b1_0001_0 : o_data = 4'd4;\\n 6'b1_0010_0 : o_data = 4'd11;\\n 6'b1_0011_0 : o_data = 4'd13;\\n 6'b1_0100_0 : o_data = 4'd12;\\n 6'b1_0101_0 : o_data = 4'd3;\\n 6'b1_0110_0 : o_data = 4'd7;\\n 6'b1_0111_0 : o_data = 4'd14;\\n 6'b1_1000_0 : o_data = 4'd10;\\n 6'b1_1001_0 : o_data = 4'd15;\\n 6'b1_1010_0 : o_data = 4'd6;\\n 6'b1_1011_0 : o_data = 4'd8;\\n 6'b1_1100_0 : o_data = 4'd0;\\n 6'b1_1101_0 : o_data = 4'd5;\\n 6'b1_1110_0 : o_data = 4'd9;\\n 6'b1_1111_0 : o_data = 4'd2;\\n 6'b1_0000_1 : o_data = 4'd6;\\n 6'b1_0001_1 : o_data = 4'd11;\\n 6'b1_0010_1 : o_data = 4'd13;\\n 6'b1_0011_1 : o_data = 4'd8;\\n 6'b1_0100_1 : o_data = 4'd1;\\n 6'b1_0101_1 : o_data = 4'd4;\\n 6'b1_0110_1 : o_data = 4'd10;\\n 6'b1_0111_1 : o_data = 4'd7;\\n 6'b1_1000_1 : o_data = 4'd9;\\n 6'b1_1001_1 : o_data = 4'd5;\\n 6'b1_1010_1 : o_data = 4'd0;\\n 6'b1_1011_1 : o_data = 4'd15;\\n 6'b1_1100_1 : o_data = 4'd14;\\n 6'b1_1101_1 : o_data = 4'd2;\\n 6'b1_1110_1 : o_data = 4'd3;\\n 6'b1_1111_1 : o_data = 4'd12;\\n default: o_data = 4'd0;\\n endcase\\nend\\n\\nendmodule : S7\", 'rtl/S8.sv': \"module S8(\\n input logic [5:0] i_data,\\n output logic [3:0] o_data\\n);\\n\\nalways_comb begin\\n case (i_data)\\n 6'b0_0000_0 : o_data = 4'd13;\\n 6'b0_0001_0 : o_data = 4'd2;\\n 6'b0_0010_0 : o_data = 4'd8;\\n 6'b0_0011_0 : o_data = 4'd4;\\n 6'b0_0100_0 : o_data = 4'd6;\\n 6'b0_0101_0 : o_data = 4'd15;\\n 6'b0_0110_0 : o_data = 4'd11;\\n 6'b0_0111_0 : o_data = 4'd1;\\n 6'b0_1000_0 : o_data = 4'd10;\\n 6'b0_1001_0 : o_data = 4'd9;\\n 6'b0_1010_0 : o_data = 4'd3;\\n 6'b0_1011_0 : o_data = 4'd14;\\n 6'b0_1100_0 : o_data = 4'd5;\\n 6'b0_1101_0 : o_data = 4'd0;\\n 6'b0_1110_0 : o_data = 4'd12;\\n 6'b0_1111_0 : o_data = 4'd7;\\n 6'b0_0000_1 : o_data = 4'd1;\\n 6'b0_0001_1 : o_data = 4'd15;\\n 6'b0_0010_1 : o_data = 4'd13;\\n 6'b0_0011_1 : o_data = 4'd8;\\n 6'b0_0100_1 : o_data = 4'd10;\\n 6'b0_0101_1 : o_data = 4'd3;\\n 6'b0_0110_1 : o_data = 4'd7;\\n 6'b0_0111_1 : o_data = 4'd4;\\n 6'b0_1000_1 : o_data = 4'd12;\\n 6'b0_1001_1 : o_data = 4'd5;\\n 6'b0_1010_1 : o_data = 4'd6;\\n 6'b0_1011_1 : o_data = 4'd11;\\n 6'b0_1100_1 : o_data = 4'd0;\\n 6'b0_1101_1 : o_data = 4'd14;\\n 6'b0_1110_1 : o_data = 4'd9;\\n 6'b0_1111_1 : o_data = 4'd2;\\n 6'b1_0000_0 : o_data = 4'd7;\\n 6'b1_0001_0 : o_data = 4'd11;\\n 6'b1_0010_0 : o_data = 4'd4;\\n 6'b1_0011_0 : o_data = 4'd1;\\n 6'b1_0100_0 : o_data = 4'd9;\\n 6'b1_0101_0 : o_data = 4'd12;\\n 6'b1_0110_0 : o_data = 4'd14;\\n 6'b1_0111_0 : o_data = 4'd2;\\n 6'b1_1000_0 : o_data = 4'd0;\\n 6'b1_1001_0 : o_data = 4'd6;\\n 6'b1_1010_0 : o_data = 4'd10;\\n 6'b1_1011_0 : o_data = 4'd13;\\n 6'b1_1100_0 : o_data = 4'd15;\\n 6'b1_1101_0 : o_data = 4'd3;\\n 6'b1_1110_0 : o_data = 4'd5;\\n 6'b1_1111_0 : o_data = 4'd8;\\n 6'b1_0000_1 : o_data = 4'd2;\\n 6'b1_0001_1 : o_data = 4'd1;\\n 6'b1_0010_1 : o_data = 4'd14;\\n 6'b1_0011_1 : o_data = 4'd7;\\n 6'b1_0100_1 : o_data = 4'd4;\\n 6'b1_0101_1 : o_data = 4'd10;\\n 6'b1_0110_1 : o_data = 4'd8;\\n 6'b1_0111_1 : o_data = 4'd13;\\n 6'b1_1000_1 : o_data = 4'd15;\\n 6'b1_1001_1 : o_data = 4'd12;\\n 6'b1_1010_1 : o_data = 4'd9;\\n 6'b1_1011_1 : o_data = 4'd0;\\n 6'b1_1100_1 : o_data = 4'd3;\\n 6'b1_1101_1 : o_data = 4'd5;\\n 6'b1_1110_1 : o_data = 4'd6;\\n 6'b1_1111_1 : o_data = 4'd11;\\n default: o_data = 4'd0;\\n endcase\\nend\\n\\nendmodule : S8\", 'rtl/des_enc.sv': \"module des_enc #(\\n parameter NBW_DATA = 'd64,\\n parameter NBW_KEY = 'd64\\n) (\\n input logic clk,\\n input logic rst_async_n,\\n input logic i_valid,\\n input logic [1:NBW_DATA] i_data,\\n input logic [1:NBW_KEY] i_key,\\n output logic o_valid,\\n output logic [1:NBW_DATA] o_data\\n);\\n\\nlocalparam ROUNDS = 'd16;\\nlocalparam EXPANDED_BLOCK = 'd48;\\nlocalparam USED_KEY = 'd56;\\n\\nlogic [1:NBW_DATA] IP;\\nlogic [1:(NBW_DATA/2)] L0;\\nlogic [1:(NBW_DATA/2)] R0;\\nlogic [1:(NBW_DATA/2)] L_ff [1:ROUNDS];\\nlogic [1:(NBW_DATA/2)] R_ff [1:ROUNDS];\\nlogic [1:(USED_KEY/2)] C0;\\nlogic [1:(USED_KEY/2)] D0;\\nlogic [1:(USED_KEY/2)] C_ff [1:ROUNDS];\\nlogic [1:(USED_KEY/2)] D_ff [1:ROUNDS];\\nlogic [1:NBW_DATA] last_perm;\\nlogic [ROUNDS-1:0] valid_ff;\\n\\nalways_ff @ (posedge clk or negedge rst_async_n) begin\\n if(!rst_async_n) begin\\n valid_ff <= 0;\\n end else begin\\n valid_ff <= {valid_ff[ROUNDS-2:0], i_valid};\\n end\\nend\\n\\nassign o_valid = valid_ff[ROUNDS-1];\\n\\nassign IP = {i_data[58], i_data[50], i_data[42], i_data[34], i_data[26], i_data[18], i_data[10], i_data[2],\\n i_data[60], i_data[52], i_data[44], i_data[36], i_data[28], i_data[20], i_data[12], i_data[4],\\n i_data[62], i_data[54], i_data[46], i_data[38], i_data[30], i_data[22], i_data[14], i_data[6],\\n i_data[64], i_data[56], i_data[48], i_data[40], i_data[32], i_data[24], i_data[16], i_data[8],\\n i_data[57], i_data[49], i_data[41], i_data[33], i_data[25], i_data[17], i_data[ 9], i_data[1],\\n i_data[59], i_data[51], i_data[43], i_data[35], i_data[27], i_data[19], i_data[11], i_data[3],\\n i_data[61], i_data[53], i_data[45], i_data[37], i_data[29], i_data[21], i_data[13], i_data[5],\\n i_data[63], i_data[55], i_data[47], i_data[39], i_data[31], i_data[23], i_data[15], i_data[7]};\\n\\nassign L0 = IP[1:NBW_DATA/2];\\nassign R0 = IP[(NBW_DATA/2)+1:NBW_DATA];\\n\\nassign C0 = {i_key[57], i_key[49], i_key[41], i_key[33], i_key[25], i_key[17], i_key[ 9],\\n i_key[ 1], i_key[58], i_key[50], i_key[42], i_key[34], i_key[26], i_key[18],\\n i_key[10], i_key[ 2], i_key[59], i_key[51], i_key[43], i_key[35], i_key[27],\\n i_key[19], i_key[11], i_key[ 3], i_key[60], i_key[52], i_key[44], i_key[36]};\\n\\nassign D0 = {i_key[63], i_key[55], i_key[47], i_key[39], i_key[31], i_key[23], i_key[15],\\n i_key[ 7], i_key[62], i_key[54], i_key[46], i_key[38], i_key[30], i_key[22],\\n i_key[14], i_key[ 6], i_key[61], i_key[53], i_key[45], i_key[37], i_key[29],\\n i_key[21], i_key[13], i_key[ 5], i_key[28], i_key[20], i_key[12], i_key[ 4]};\\n\\ngenerate\\n for (genvar i = 1; i <= ROUNDS; i++) begin : rounds\\n logic [1:EXPANDED_BLOCK] round_key;\\n logic [1:(USED_KEY/2)] C_nx;\\n logic [1:(USED_KEY/2)] D_nx;\\n logic [1:USED_KEY] perm_ch;\\n logic [1:(NBW_DATA/2)] R_nx;\\n logic [1:EXPANDED_BLOCK] R_expanded;\\n logic [1:6] Primitive_input [1:8];\\n logic [1:4] Primitive_output [1:8];\\n logic [1:(NBW_DATA/2)] perm_in;\\n\\n assign perm_ch = {C_nx, D_nx};\\n assign round_key = {perm_ch[14], perm_ch[17], perm_ch[11], perm_ch[24], perm_ch[ 1], perm_ch[ 5],\\n perm_ch[ 3], perm_ch[28], perm_ch[15], perm_ch[ 6], perm_ch[21], perm_ch[10],\\n perm_ch[23], perm_ch[19], perm_ch[12], perm_ch[ 4], perm_ch[26], perm_ch[ 8],\\n perm_ch[16], perm_ch[ 7], perm_ch[27], perm_ch[20], perm_ch[13], perm_ch[ 2],\\n perm_ch[41], perm_ch[52], perm_ch[31], perm_ch[37], perm_ch[47], perm_ch[55],\\n perm_ch[30], perm_ch[40], perm_ch[51], perm_ch[45], perm_ch[33], perm_ch[48],\\n perm_ch[44], perm_ch[49], perm_ch[39], perm_ch[56], perm_ch[34], perm_ch[53],\\n perm_ch[46], perm_ch[42], perm_ch[50], perm_ch[36], perm_ch[29], perm_ch[32]};\\n\\n if(i == 1 || i == 2 || i == 9 || i == 16) begin\\n if(i == 1) begin\\n assign C_nx = {C0[2:(USED_KEY/2)], C0[1]};\\n assign D_nx = {D0[2:(USED_KEY/2)], D0[1]};\\n end else begin\\n assign C_nx = {C_ff[i-1][2:(USED_KEY/2)], C_ff[i-1][1]};\\n assign D_nx = {D_ff[i-1][2:(USED_KEY/2)], D_ff[i-1][1]};\\n end\\n end else begin\\n assign C_nx = {C_ff[i-1][3:(USED_KEY/2)], C_ff[i-1][1:2]};\\n assign D_nx = {D_ff[i-1][3:(USED_KEY/2)], D_ff[i-1][1:2]};\\n end\\n\\n assign Primitive_input[1] = R_expanded[ 1:6 ] ^ round_key[ 1:6 ];\\n assign Primitive_input[2] = R_expanded[ 7:12] ^ round_key[ 7:12];\\n assign Primitive_input[3] = R_expanded[13:18] ^ round_key[13:18];\\n assign Primitive_input[4] = R_expanded[19:24] ^ round_key[19:24];\\n assign Primitive_input[5] = R_expanded[25:30] ^ round_key[25:30];\\n assign Primitive_input[6] = R_expanded[31:36] ^ round_key[31:36];\\n assign Primitive_input[7] = R_expanded[37:42] ^ round_key[37:42];\\n assign Primitive_input[8] = R_expanded[43:48] ^ round_key[43:48];\\n\\n S1 uu_S1 (\\n .i_data(Primitive_input [1]),\\n .o_data(Primitive_output[1])\\n );\\n\\n S2 uu_S2 (\\n .i_data(Primitive_input [2]),\\n .o_data(Primitive_output[2])\\n );\\n\\n S3 uu_S3 (\\n .i_data(Primitive_input [3]),\\n .o_data(Primitive_output[3])\\n );\\n\\n S4 uu_S4 (\\n .i_data(Primitive_input [4]),\\n .o_data(Primitive_output[4])\\n );\\n\\n S5 uu_S5 (\\n .i_data(Primitive_input [5]),\\n .o_data(Primitive_output[5])\\n );\\n\\n S6 uu_S6 (\\n .i_data(Primitive_input [6]),\\n .o_data(Primitive_output[6])\\n );\\n\\n S7 uu_S7 (\\n .i_data(Primitive_input [7]),\\n .o_data(Primitive_output[7])\\n );\\n\\n S8 uu_S8 (\\n .i_data(Primitive_input [8]),\\n .o_data(Primitive_output[8])\\n );\\n\\n assign perm_in = {Primitive_output[1], Primitive_output[2], Primitive_output[3], Primitive_output[4],\\n Primitive_output[5], Primitive_output[6], Primitive_output[7], Primitive_output[8]};\\n\\n assign R_nx = {perm_in[16], perm_in[ 7], perm_in[20], perm_in[21],\\n perm_in[29], perm_in[12], perm_in[28], perm_in[17],\\n perm_in[ 1], perm_in[15], perm_in[23], perm_in[26],\\n perm_in[ 5], perm_in[18], perm_in[31], perm_in[10],\\n perm_in[ 2], perm_in[ 8], perm_in[24], perm_in[14],\\n perm_in[32], perm_in[27], perm_in[ 3], perm_in[ 9],\\n perm_in[19], perm_in[13], perm_in[30], perm_in[ 6],\\n perm_in[22], perm_in[11], perm_in[ 4], perm_in[25]};\\n\\n if(i == 1) begin\\n assign R_expanded = {R0[32], R0[ 1], R0[ 2], R0[ 3], R0[ 4], R0[ 5],\\n R0[ 4], R0[ 5], R0[ 6], R0[ 7], R0[ 8], R0[ 9],\\n R0[ 8], R0[ 9], R0[10], R0[11], R0[12], R0[13],\\n R0[12], R0[13], R0[14], R0[15], R0[16], R0[17],\\n R0[16], R0[17], R0[18], R0[19], R0[20], R0[21],\\n R0[20], R0[21], R0[22], R0[23], R0[24], R0[25],\\n R0[24], R0[25], R0[26], R0[27], R0[28], R0[29],\\n R0[28], R0[29], R0[30], R0[31], R0[32], R0[ 1]};\\n\\n always_ff @ (posedge clk or negedge rst_async_n) begin\\n if(!rst_async_n) begin\\n L_ff[i] <= 0;\\n R_ff[i] <= 0;\\n C_ff[i] <= 0;\\n D_ff[i] <= 0;\\n end else begin\\n if(i_valid) begin\\n L_ff[i] <= R0;\\n R_ff[i] <= R_nx ^ L0;\\n C_ff[i] <= C_nx;\\n D_ff[i] <= D_nx;\\n end\\n end\\n end\\n end else begin\\n assign R_expanded = {R_ff[i-1][32], R_ff[i-1][ 1], R_ff[i-1][ 2], R_ff[i-1][ 3], R_ff[i-1][ 4], R_ff[i-1][ 5],\\n R_ff[i-1][ 4], R_ff[i-1][ 5], R_ff[i-1][ 6], R_ff[i-1][ 7], R_ff[i-1][ 8], R_ff[i-1][ 9],\\n R_ff[i-1][ 8], R_ff[i-1][ 9], R_ff[i-1][10], R_ff[i-1][11], R_ff[i-1][12], R_ff[i-1][13],\\n R_ff[i-1][12], R_ff[i-1][13], R_ff[i-1][14], R_ff[i-1][15], R_ff[i-1][16], R_ff[i-1][17],\\n R_ff[i-1][16], R_ff[i-1][17], R_ff[i-1][18], R_ff[i-1][19], R_ff[i-1][20], R_ff[i-1][21],\\n R_ff[i-1][20], R_ff[i-1][21], R_ff[i-1][22], R_ff[i-1][23], R_ff[i-1][24], R_ff[i-1][25],\\n R_ff[i-1][24], R_ff[i-1][25], R_ff[i-1][26], R_ff[i-1][27], R_ff[i-1][28], R_ff[i-1][29],\\n R_ff[i-1][28], R_ff[i-1][29], R_ff[i-1][30], R_ff[i-1][31], R_ff[i-1][32], R_ff[i-1][ 1]};\\n\\n always_ff @ (posedge clk or negedge rst_async_n) begin\\n if(!rst_async_n) begin\\n L_ff[i] <= 0;\\n R_ff[i] <= 0;\\n C_ff[i] <= 0;\\n D_ff[i] <= 0;\\n end else begin\\n L_ff[i] <= R_ff[i-1];\\n R_ff[i] <= R_nx ^ L_ff[i-1];\\n C_ff[i] <= C_nx;\\n D_ff[i] <= D_nx;\\n end\\n end\\n end\\n end\\nendgenerate\\n\\nassign last_perm = {R_ff[ROUNDS], L_ff[ROUNDS]};\\n\\nassign o_data = {last_perm[40], last_perm[8], last_perm[48], last_perm[16], last_perm[56], last_perm[24], last_perm[64], last_perm[32],\\n last_perm[39], last_perm[7], last_perm[47], last_perm[15], last_perm[55], last_perm[23], last_perm[63], last_perm[31],\\n last_perm[38], last_perm[6], last_perm[46], last_perm[14], last_perm[54], last_perm[22], last_perm[62], last_perm[30],\\n last_perm[37], last_perm[5], last_perm[45], last_perm[13], last_perm[53], last_perm[21], last_perm[61], last_perm[29],\\n last_perm[36], last_perm[4], last_perm[44], last_perm[12], last_perm[52], last_perm[20], last_perm[60], last_perm[28],\\n last_perm[35], last_perm[3], last_perm[43], last_perm[11], last_perm[51], last_perm[19], last_perm[59], last_perm[27],\\n last_perm[34], last_perm[2], last_perm[42], last_perm[10], last_perm[50], last_perm[18], last_perm[58], last_perm[26],\\n last_perm[33], last_perm[1], last_perm[41], last_perm[ 9], last_perm[49], last_perm[17], last_perm[57], last_perm[25]};\\n\\nendmodule : des_enc\", 'verif/tb_des_dec.sv': None, 'docs/Encryption.md': None, 'rtl/des_dec.sv': \"module des_dec #(\\n parameter NBW_DATA = 'd64,\\n parameter NBW_KEY = 'd64\\n) (\\n input logic clk,\\n input logic rst_async_n,\\n input logic i_valid,\\n input logic [1:NBW_DATA] i_data,\\n input logic [1:NBW_KEY] i_key,\\n output logic o_valid,\\n output logic [1:NBW_DATA] o_data\\n);\\n\\nlocalparam ROUNDS = 'd16;\\nlocalparam EXPANDED_BLOCK = 'd48;\\nlocalparam USED_KEY = 'd56;\\n\\nlogic [1:(NBW_DATA/2)] L16;\\nlogic [1:(NBW_DATA/2)] R16;\\nlogic [1:(NBW_DATA/2)] L_ff [0:ROUNDS-1];\\nlogic [1:(NBW_DATA/2)] R_ff [0:ROUNDS-1];\\nlogic [1:(USED_KEY/2)] C16;\\nlogic [1:(USED_KEY/2)] D16;\\nlogic [1:(USED_KEY/2)] C_ff [0:ROUNDS-1];\\nlogic [1:(USED_KEY/2)] D_ff [0:ROUNDS-1];\\nlogic [1:NBW_DATA] last_perm;\\nlogic [ROUNDS-1:0] valid_ff;\\n\\nalways_ff @ (posedge clk or negedge rst_async_n) begin\\n if(!rst_async_n) begin\\n valid_ff <= 0;\\n end else begin\\n valid_ff <= {valid_ff[ROUNDS-2:0], i_valid};\\n end\\nend\\n\\nassign o_valid = valid_ff[ROUNDS-1];\\n\\nassign R16 = {i_data[58], i_data[50], i_data[42], i_data[34], i_data[26], i_data[18], i_data[10], i_data[2],\\n i_data[60], i_data[52], i_data[44], i_data[36], i_data[28], i_data[20], i_data[12], i_data[4],\\n i_data[62], i_data[54], i_data[46], i_data[38], i_data[30], i_data[22], i_data[14], i_data[6],\\n i_data[64], i_data[56], i_data[48], i_data[40], i_data[32], i_data[24], i_data[16], i_data[8]};\\n\\nassign L16 = {i_data[57], i_data[49], i_data[41], i_data[33], i_data[25], i_data[17], i_data[ 9], i_data[1],\\n i_data[59], i_data[51], i_data[43], i_data[35], i_data[27], i_data[19], i_data[11], i_data[3],\\n i_data[61], i_data[53], i_data[45], i_data[37], i_data[29], i_data[21], i_data[13], i_data[5],\\n i_data[63], i_data[55], i_data[47], i_data[39], i_data[31], i_data[23], i_data[15], i_data[7]};\\n\\nassign C16 = {i_key[57], i_key[49], i_key[41], i_key[33], i_key[25], i_key[17], i_key[ 9],\\n i_key[ 1], i_key[58], i_key[50], i_key[42], i_key[34], i_key[26], i_key[18],\\n i_key[10], i_key[ 2], i_key[59], i_key[51], i_key[43], i_key[35], i_key[27],\\n i_key[19], i_key[11], i_key[ 3], i_key[60], i_key[52], i_key[44], i_key[36]};\\n\\nassign D16 = {i_key[63], i_key[55], i_key[47], i_key[39], i_key[31], i_key[23], i_key[15],\\n i_key[ 7], i_key[62], i_key[54], i_key[46], i_key[38], i_key[30], i_key[22],\\n i_key[14], i_key[ 6], i_key[61], i_key[53], i_key[45], i_key[37], i_key[29],\\n i_key[21], i_key[13], i_key[ 5], i_key[28], i_key[20], i_key[12], i_key[ 4]};\\n\\ngenerate\\n for (genvar i = ROUNDS-1; i >= 0; i--) begin : rounds\\n logic [1:EXPANDED_BLOCK] round_key;\\n logic [1:(USED_KEY/2)] C_nx;\\n logic [1:(USED_KEY/2)] D_nx;\\n logic [1:USED_KEY] perm_ch;\\n logic [1:(NBW_DATA/2)] L_nx;\\n logic [1:EXPANDED_BLOCK] L_expanded;\\n logic [1:6] Primitive_input [1:8];\\n logic [1:4] Primitive_output [1:8];\\n logic [1:(NBW_DATA/2)] perm_in;\\n\\n if(i == 15) begin\\n assign perm_ch = {C16, D16};\\n end else begin\\n assign perm_ch = {C_ff[i+1], D_ff[i+1]};\\n end\\n assign round_key = {perm_ch[14], perm_ch[17], perm_ch[11], perm_ch[24], perm_ch[ 1], perm_ch[ 5],\\n perm_ch[ 3], perm_ch[28], perm_ch[15], perm_ch[ 6], perm_ch[21], perm_ch[10],\\n perm_ch[23], perm_ch[19], perm_ch[12], perm_ch[ 4], perm_ch[26], perm_ch[ 8],\\n perm_ch[16], perm_ch[ 7], perm_ch[27], perm_ch[20], perm_ch[13], perm_ch[ 2],\\n perm_ch[41], perm_ch[52], perm_ch[31], perm_ch[37], perm_ch[47], perm_ch[55],\\n perm_ch[30], perm_ch[40], perm_ch[51], perm_ch[45], perm_ch[33], perm_ch[48],\\n perm_ch[44], perm_ch[49], perm_ch[39], perm_ch[56], perm_ch[34], perm_ch[53],\\n perm_ch[46], perm_ch[42], perm_ch[50], perm_ch[36], perm_ch[29], perm_ch[32]};\\n\\n if(i == 0 || i == 1 || i == 8 || i == 15) begin\\n if(i == 15) begin\\n assign C_nx = {C16[(USED_KEY/2)], C16[1:(USED_KEY/2)-1]};\\n assign D_nx = {D16[(USED_KEY/2)], D16[1:(USED_KEY/2)-1]};\\n end else begin\\n assign C_nx = {C_ff[i+1][(USED_KEY/2)], C_ff[i+1][1:(USED_KEY/2)-1]};\\n assign D_nx = {D_ff[i+1][(USED_KEY/2)], D_ff[i+1][1:(USED_KEY/2)-1]};\\n end\\n end else begin\\n assign C_nx = {C_ff[i+1][(USED_KEY/2)-1+:2], C_ff[i+1][1:(USED_KEY/2)-2]};\\n assign D_nx = {D_ff[i+1][(USED_KEY/2)-1+:2], D_ff[i+1][1:(USED_KEY/2)-2]};\\n end\\n\\n assign Primitive_input[1] = L_expanded[ 1:6 ] ^ round_key[ 1:6 ];\\n assign Primitive_input[2] = L_expanded[ 7:12] ^ round_key[ 7:12];\\n assign Primitive_input[3] = L_expanded[13:18] ^ round_key[13:18];\\n assign Primitive_input[4] = L_expanded[19:24] ^ round_key[19:24];\\n assign Primitive_input[5] = L_expanded[25:30] ^ round_key[25:30];\\n assign Primitive_input[6] = L_expanded[31:36] ^ round_key[31:36];\\n assign Primitive_input[7] = L_expanded[37:42] ^ round_key[37:42];\\n assign Primitive_input[8] = L_expanded[43:48] ^ round_key[43:48];\\n\\n S1 uu_S1 (\\n .i_data(Primitive_input [1]),\\n .o_data(Primitive_output[1])\\n );\\n\\n S2 uu_S2 (\\n .i_data(Primitive_input [2]),\\n .o_data(Primitive_output[2])\\n );\\n\\n S3 uu_S3 (\\n .i_data(Primitive_input [3]),\\n .o_data(Primitive_output[3])\\n );\\n\\n S4 uu_S4 (\\n .i_data(Primitive_input [4]),\\n .o_data(Primitive_output[4])\\n );\\n\\n S5 uu_S5 (\\n .i_data(Primitive_input [5]),\\n .o_data(Primitive_output[5])\\n );\\n\\n S6 uu_S6 (\\n .i_data(Primitive_input [6]),\\n .o_data(Primitive_output[6])\\n );\\n\\n S7 uu_S7 (\\n .i_data(Primitive_input [7]),\\n .o_data(Primitive_output[7])\\n );\\n\\n S8 uu_S8 (\\n .i_data(Primitive_input [8]),\\n .o_data(Primitive_output[8])\\n );\\n\\n assign perm_in = {Primitive_output[1], Primitive_output[2], Primitive_output[3], Primitive_output[4],\\n Primitive_output[5], Primitive_output[6], Primitive_output[7], Primitive_output[8]};\\n\\n assign L_nx = {perm_in[16], perm_in[ 7], perm_in[20], perm_in[21],\\n perm_in[29], perm_in[12], perm_in[28], perm_in[17],\\n perm_in[ 1], perm_in[15], perm_in[23], perm_in[26],\\n perm_in[ 5], perm_in[18], perm_in[31], perm_in[10],\\n perm_in[ 2], perm_in[ 8], perm_in[24], perm_in[14],\\n perm_in[32], perm_in[27], perm_in[ 3], perm_in[ 9],\\n perm_in[19], perm_in[13], perm_in[30], perm_in[ 6],\\n perm_in[22], perm_in[11], perm_in[ 4], perm_in[25]};\\n\\n if(i == 15) begin\\n assign L_expanded = {L16[32], L16[ 1], L16[ 2], L16[ 3], L16[ 4], L16[ 5],\\n L16[ 4], L16[ 5], L16[ 6], L16[ 7], L16[ 8], L16[ 9],\\n L16[ 8], L16[ 9], L16[10], L16[11], L16[12], L16[13],\\n L16[12], L16[13], L16[14], L16[15], L16[16], L16[17],\\n L16[16], L16[17], L16[18], L16[19], L16[20], L16[21],\\n L16[20], L16[21], L16[22], L16[23], L16[24], L16[25],\\n L16[24], L16[25], L16[26], L16[27], L16[28], L16[29],\\n L16[28], L16[29], L16[30], L16[31], L16[32], L16[ 1]};\\n\\n always_ff @ (posedge clk or negedge rst_async_n) begin\\n if(!rst_async_n) begin\\n L_ff[i] <= 0;\\n R_ff[i] <= 0;\\n C_ff[i] <= 0;\\n D_ff[i] <= 0;\\n end else begin\\n if(i_valid) begin\\n L_ff[i] <= L_nx ^ R16;\\n R_ff[i] <= L16;\\n C_ff[i] <= C_nx;\\n D_ff[i] <= D_nx;\\n end\\n end\\n end\\n end else begin\\n assign L_expanded = {L_ff[i+1][32], L_ff[i+1][ 1], L_ff[i+1][ 2], L_ff[i+1][ 3], L_ff[i+1][ 4], L_ff[i+1][ 5],\\n L_ff[i+1][ 4], L_ff[i+1][ 5], L_ff[i+1][ 6], L_ff[i+1][ 7], L_ff[i+1][ 8], L_ff[i+1][ 9],\\n L_ff[i+1][ 8], L_ff[i+1][ 9], L_ff[i+1][10], L_ff[i+1][11], L_ff[i+1][12], L_ff[i+1][13],\\n L_ff[i+1][12], L_ff[i+1][13], L_ff[i+1][14], L_ff[i+1][15], L_ff[i+1][16], L_ff[i+1][17],\\n L_ff[i+1][16], L_ff[i+1][17], L_ff[i+1][18], L_ff[i+1][19], L_ff[i+1][20], L_ff[i+1][21],\\n L_ff[i+1][20], L_ff[i+1][21], L_ff[i+1][22], L_ff[i+1][23], L_ff[i+1][24], L_ff[i+1][25],\\n L_ff[i+1][24], L_ff[i+1][25], L_ff[i+1][26], L_ff[i+1][27], L_ff[i+1][28], L_ff[i+1][29],\\n L_ff[i+1][28], L_ff[i+1][29], L_ff[i+1][30], L_ff[i+1][31], L_ff[i+1][32], L_ff[i+1][ 1]};\\n\\n always_ff @ (posedge clk or negedge rst_async_n) begin\\n if(!rst_async_n) begin\\n L_ff[i] <= 0;\\n R_ff[i] <= 0;\\n C_ff[i] <= 0;\\n D_ff[i] <= 0;\\n end else begin\\n L_ff[i] <= L_nx ^ R_ff[i+1];\\n R_ff[i] <= L_ff[i+1];\\n C_ff[i] <= C_nx;\\n D_ff[i] <= D_nx;\\n end\\n end\\n end\\n end\\nendgenerate\\n\\nassign last_perm = {L_ff[0], R_ff[0]};\\n\\nassign o_data = {last_perm[40], last_perm[8], last_perm[48], last_perm[16], last_perm[56], last_perm[24], last_perm[64], last_perm[32],\\n last_perm[39], last_perm[7], last_perm[47], last_perm[15], last_perm[55], last_perm[23], last_perm[63], last_perm[31],\\n last_perm[38], last_perm[6], last_perm[46], last_perm[14], last_perm[54], last_perm[22], last_perm[62], last_perm[30],\\n last_perm[37], last_perm[5], last_perm[45], last_perm[13], last_perm[53], last_perm[21], last_perm[61], last_perm[29],\\n last_perm[36], last_perm[4], last_perm[44], last_perm[12], last_perm[52], last_perm[20], last_perm[60], last_perm[28],\\n last_perm[35], last_perm[3], last_perm[43], last_perm[11], last_perm[51], last_perm[19], last_perm[59], last_perm[27],\\n last_perm[34], last_perm[2], last_perm[42], last_perm[10], last_perm[50], last_perm[18], last_perm[58], last_perm[26],\\n last_perm[33], last_perm[1], last_perm[41], last_perm[ 9], last_perm[49], last_perm[17], last_perm[57], last_perm[25]};\\n\\nendmodule : des_dec\", 'verif/tb_3des_enc.sv': 'module tb;\\n\\nparameter NBW_DATA = \\'d64;\\nparameter NBW_KEY = \\'d192;\\n\\nlogic clk;\\nlogic rst_async_n;\\nlogic i_valid;\\nlogic [1:NBW_DATA] i_data;\\nlogic [1:NBW_KEY ] i_key;\\nlogic o_valid;\\nlogic [1:NBW_DATA] o_data;\\n\\ndes3_enc #(\\n .NBW_DATA(NBW_DATA),\\n .NBW_KEY (NBW_KEY )\\n) uu_des3_enc (\\n .clk (clk ),\\n .rst_async_n(rst_async_n),\\n .i_valid (i_valid ),\\n .i_data (i_data ),\\n .i_key (i_key ),\\n .o_valid (o_valid ),\\n .o_data (o_data )\\n);\\n\\ninitial begin\\n $dumpfile(\"test.vcd\");\\n $dumpvars(0,tb);\\nend\\n\\nalways #5 clk = ~clk;\\n\\ntask Single_test(logic [1:NBW_KEY] key, logic [1:NBW_DATA] data, logic [1:NBW_DATA] expected);\\n i_key = key;\\n i_data = data;\\n i_valid = 1;\\n\\n @(negedge clk);\\n i_valid = 0;\\n\\n @(posedge o_valid);\\n @(negedge clk);\\n if(o_data != expected) begin\\n $display(\"FAIL!\");\\n $display(\"Expected %h, got %h\", expected, o_data);\\n end else begin\\n $display(\"PASS!\");\\n end\\nendtask\\n\\ntask Burst_test();\\n i_key = 192\\'hB1FECAFEBEBAB1FEABCDABCDABCDABCD8765432187654321;\\n i_data = 64\\'h4321432143214321;\\n i_valid = 1;\\n\\n @(negedge clk);\\n i_data = 64\\'h123456789ABCDEF0;\\n\\n @(negedge clk);\\n i_data = 64\\'h1234123412341234;\\n i_key = 192\\'hABCDABCDABCDABCD8765432187654321B1FECAFEBEBAB1FE;\\n\\n @(negedge clk);\\n i_valid = 0;\\n\\n @(posedge o_valid);\\n @(negedge clk);\\n if(o_data != 64\\'h2749c9efcaed543a) begin\\n $display(\"FAIL!\");\\n $display(\"Expected %h, got %h\", 64\\'h2749c9efcaed543a, o_data);\\n end else begin\\n $display(\"PASS!\");\\n end\\n\\n @(negedge clk);\\n if(o_valid != 1) begin\\n $display(\"FAIL! o_valid should be asserted here.\");\\n end\\n if(o_data != 64\\'h984d23ecef8df5fd) begin\\n $display(\"FAIL!\");\\n $display(\"Expected %h, got %h\", 64\\'h984d23ecef8df5fd, o_data);\\n end else begin\\n $display(\"PASS!\");\\n end\\n\\n @(negedge clk);\\n if(o_valid != 1) begin\\n $display(\"FAIL! o_valid should be asserted here.\");\\n end\\n if(o_data != 64\\'h972161012599c927) begin\\n $display(\"FAIL!\");\\n $display(\"Expected %h, got %h\", 64\\'h972161012599c927, o_data);\\n end else begin\\n $display(\"PASS!\");\\n end\\n \\nendtask\\n\\ninitial begin\\n clk = 0;\\n i_valid = 0;\\n rst_async_n = 1;\\n #1;\\n rst_async_n = 0;\\n #2;\\n rst_async_n = 1;\\n @(negedge clk);\\n\\n $display(\"\\\\nSingle Tests\");\\n Single_test(192\\'h0123456789abcdeffedcba9876543210abcdef9876543210, 64\\'h0123456789ABCDEF, 64\\'ha4688b153da3f95b);\\n Single_test(192\\'h0123456789abcdeffedcba9876543210abcdef9876543210, 64\\'hFEDCBA9876543210, 64\\'h7b9325d305515107);\\n Single_test(192\\'hBEBACAFE12345678B1FECAFE876543219898898974744747, 64\\'hFEDCBA9876543210, 64\\'h71f4eedd55b0f964);\\n Single_test(192\\'hBEBACAFE12345678B1FECAFE876543219898898974744747, 64\\'hB1FECAFEBEBAB1FE, 64\\'h2038ea8568d3f771);\\n\\n $display(\"\\\\nBurst Test\");\\n Burst_test();\\n\\n @(negedge clk);\\n @(negedge clk);\\n\\n $finish();\\nend\\n\\nendmodule', 'verif/tb_3des_dec.sv': None, 'docs/min_hamming_distance_finder_spec.md': None, 'rtl/Bit_Difference_Counter.sv': None, 'rtl/Bitwise_Reduction.sv': None, 'rtl/Data_Reduction.sv': None, 'verif/tb_Min_Hamming_Distance_Finder.sv': None, 'docs/specs.md': None, 'rtl/arithmetic_progression_generator.sv': None, 'docs/algorithms.md': None, 'docs/coeff_update_spec.md': None, 'docs/equalizer_spec.md': None, 'docs/error_calc_spec.md': None, 'rtl/coeff_update.sv': None, 'rtl/dynamic_equalizer.sv': None, 'rtl/error_calc.sv': None, 'docs/awgn_spec.md': None, 'docs/equalizer_top_spec.md': None, 'rtl/elevator_control_system.sv': None, 'docs/tx_specification.md': None, 'rtl/ethernet_fifo_cdc.sv': None, 'docs/tx_mac_specification.md': None, 'verif/event_scheduler_tb.sv': None, 'docs/modified_specs.md': None, 'rtl/event_scheduler.sv': None, 'verif/tb_event_scheduler.sv': None, 'rtl/column_selector.sv': None, 'rtl/event_storage.sv': None, 'verif/tb.sv': None, 'rtl/fixed_priority_arbiter.sv': None, 'verif/fixed_priority_arbiter_tb.sv': None, 'docs/Modified_specification.md': None, 'docs/GCD_specification.md': None, 'docs/crypto_accelerator_specification.md': None, 'docs/modular_exponentiation_specification.md': None, 'docs/modular_multiplier_specification.md': None, 'rtl/gcd_controlpath_3.sv': None, 'rtl/gcd_controlpath_4.sv': None, 'rtl/gcd_datapath_5.sv': None, 'rtl/gcd_datapath_6.sv': None, 'rtl/gcd_top_1.sv': None, 'rtl/gcd_top_2.sv': None, 'rtl/modular_exponentiation.sv': None, 'rtl/modular_multiplier.sv': None, 'rtl/lfsr_8bit.sv': None, 'verif/lfsr_8bit_tb.sv': None, 'rtl/bit16_lfsr.sv': None, 'rtl/low_power_ctrl.sv': None, 'rtl/sync_fifo.sv': None, 'verif/tb_low_power_channel.sv': None, 'rtl/cross_domain_sync.sv': None, 'rtl/dsp_input_stage.sv': None, 'rtl/dsp_output_stage.sv': None, 'rtl/lfsr_generator.sv': None, 'rtl/monte_carlo_dsp_monitor_top.sv': None, 'verif/monte_carlo_dsp_monitor_top_tb.sv': None, 'docs/multiplexer_specification.md': None, 'verif/multiplexer_tb.sv': None, 'docs/nbit_swizzling_spec.md': None, 'verif/nbit_swizzling_tb.sv': None, 'docs/nmea_decoder_spec.md': None, 'rtl/nmea_decoder.sv': None, 'verif/nmea_decoder_tb.sv': None, 'docs/fifo.md': None, 'rtl/fifo_memory.sv': None, 'rtl/read_to_write_pointer_sync.sv': None, 'rtl/rptr_empty.sv': None, 'rtl/wptr_full.sv': None, 'rtl/write_to_read_pointer_sync.sv': None, 'docs/spec.md': None, 'verif/async_filo_tb.sv': None, 'docs/axilite_to_pcie_config_module.md': None, 'rtl/axi4lite_to_pcie_cfg_bridge.sv': None, 'rtl/axis_broadcast.sv': None, 'verif/tb_axis_broadcast.sv': None, 'docs/axis_to_uart_tx_specs.md': None, 'docs/uart_rx_to_axis_specs.md': None, 'rtl/barrel_shifter.sv': None, 'verif/barrel_shifter_tb.sv': None, 'rtl/bcd_adder.sv': None, 'rtl/full_adder.sv': None, 'rtl/four_bit_adder.sv': None, 'rtl/search_binary_search_tree.sv': None, 'rtl/delete_node_binary_search_tree.sv': None, 'docs/bst_operations.md': None, 'rtl/binary_search_tree_sort_construct.sv': None, 'docs/Spec.md': None, 'verif/tb_binary_to_gray.sv': None, 'verif/tb_custom_byte_enable_ram.sv': None, 'verif/cache_controller_tb.sv': None, 'rtl/caesar_cipher.sv': None, 'verif/caesar_cipher_tb.sv': None, 'verif/tb_pseudoRandGenerator_ca.sv': None, 'docs/continuous_adder_specification.md': None, 'verif/continuous_adder_tb.sv': None, 'rtl/fifo_buffer.sv': None, 'verif/tb_fifo_buffer.sv': None, 'docs/direct_map_cache_spec.md': None, 'verif/tb_direct_map_cache.sv': None, 'rtl/direct_map_cache.sv': None, 'rtl/dual_port_memory.sv': None, 'rtl/gen_cos_sin_lut.sv': None, 'rtl/phase_lut.sv': None, 'rtl/phase_rotation.sv': None, 'rtl/power4.sv': None, 'rtl/saturation.sv': None, 'rtl/top_phase_rotation.sv': None, 'docs/spec_viterbi.md': None, 'docs/spec_slicer_top.md': None, 'docs/spec_top_phase_rotation.md': None, 'rtl/slicer.sv': None, 'rtl/slicer_top.sv': None, 'docs/swizzler_specification.md': None, 'verif/swizzler_tb.sv': None, 'rtl/swizzler.sv': None, 'docs/sync_serial_communication_tx_rx_spec.md': None, 'verif/sync_serial_communication_tb.sv': None, 'rtl/weight_stationary_pe.sv': None, 'verif/systolic_array_tb.sv': None, 'rtl/thermostat.v': None, 'docs/Traffic_controller.md': None, 'rtl/traffic_light_controller.sv': None, 'docs/Universal_Shift_Register_spec.md': None, 'verif/tb_universal_shift_register.sv': None, 'rtl/universal_shift_register.sv': None, 'docs/spec_conj.md': None, 'docs/spec_cross_correlation.md': None, 'docs/spec_detect_sequence.md': None, 'rtl/adder_2d_layers.sv': None, 'rtl/adder_tree_2d.sv': None, 'rtl/correlate.sv': None, 'rtl/cross_correlation.sv': None, 'docs/valid_modes.md': None, 'docs/words_counting.md': None, 'rtl/detect_sequence.sv': None, 'docs/proc_fsm_spec.md': None, 'docs/adder_tree.md': None, 'docs/coeff_ram.md': None, 'docs/poly_decimator.md': None, 'docs/poly_filter.md': None, 'docs/shift_register.md': None, 'rtl/adder_tree.sv': None, 'rtl/coeff_ram.sv': None, 'rtl/poly_filter.sv': None, 'rtl/shift_register.sv': None, 'docs/prbs_specification.md': None, 'rtl/prbs_gen_check.sv': None, 'rtl/fsm.sv': None, 'verif/fsm_tb.sv': None, 'rtl/CA_1.sv': None, 'rtl/CA_2.sv': None, 'rtl/CA_3.sv': None, 'rtl/CA_4.sv': None, 'rtl/rgb_color_space_conversion.sv': None, 'rtl/APBGlobalHistoryRegister.v': None, 'docs/signed_comparator_specification.md': None, 'verif/signed_comparator_tb.sv': None, 'rtl/sorting_engine.sv': None, 'rtl/brick_sort.sv': None, 'rtl/bubble_sort.sv': None, 'rtl/merge_sort.sv': None, 'rtl/selection_sort.sv': None}", + "rtl/S1.sv": "module S1(\n input logic [5:0] i_data,\n output logic [3:0] o_data\n);\n\nalways_comb begin\n case (i_data)\n 6'b0_0000_0 : o_data = 4'd14;\n 6'b0_0001_0 : o_data = 4'd4;\n 6'b0_0010_0 : o_data = 4'd13;\n 6'b0_0011_0 : o_data = 4'd1;\n 6'b0_0100_0 : o_data = 4'd2;\n 6'b0_0101_0 : o_data = 4'd15;\n 6'b0_0110_0 : o_data = 4'd11;\n 6'b0_0111_0 : o_data = 4'd8;\n 6'b0_1000_0 : o_data = 4'd3;\n 6'b0_1001_0 : o_data = 4'd10;\n 6'b0_1010_0 : o_data = 4'd6;\n 6'b0_1011_0 : o_data = 4'd12;\n 6'b0_1100_0 : o_data = 4'd5;\n 6'b0_1101_0 : o_data = 4'd9;\n 6'b0_1110_0 : o_data = 4'd0;\n 6'b0_1111_0 : o_data = 4'd7;\n 6'b0_0000_1 : o_data = 4'd0;\n 6'b0_0001_1 : o_data = 4'd15;\n 6'b0_0010_1 : o_data = 4'd7;\n 6'b0_0011_1 : o_data = 4'd4;\n 6'b0_0100_1 : o_data = 4'd14;\n 6'b0_0101_1 : o_data = 4'd2;\n 6'b0_0110_1 : o_data = 4'd13;\n 6'b0_0111_1 : o_data = 4'd1;\n 6'b0_1000_1 : o_data = 4'd10;\n 6'b0_1001_1 : o_data = 4'd6;\n 6'b0_1010_1 : o_data = 4'd12;\n 6'b0_1011_1 : o_data = 4'd11;\n 6'b0_1100_1 : o_data = 4'd9;\n 6'b0_1101_1 : o_data = 4'd5;\n 6'b0_1110_1 : o_data = 4'd3;\n 6'b0_1111_1 : o_data = 4'd8;\n 6'b1_0000_0 : o_data = 4'd4;\n 6'b1_0001_0 : o_data = 4'd1;\n 6'b1_0010_0 : o_data = 4'd14;\n 6'b1_0011_0 : o_data = 4'd8;\n 6'b1_0100_0 : o_data = 4'd13;\n 6'b1_0101_0 : o_data = 4'd6;\n 6'b1_0110_0 : o_data = 4'd2;\n 6'b1_0111_0 : o_data = 4'd11;\n 6'b1_1000_0 : o_data = 4'd15;\n 6'b1_1001_0 : o_data = 4'd12;\n 6'b1_1010_0 : o_data = 4'd9;\n 6'b1_1011_0 : o_data = 4'd7;\n 6'b1_1100_0 : o_data = 4'd3;\n 6'b1_1101_0 : o_data = 4'd10;\n 6'b1_1110_0 : o_data = 4'd5;\n 6'b1_1111_0 : o_data = 4'd0;\n 6'b1_0000_1 : o_data = 4'd15;\n 6'b1_0001_1 : o_data = 4'd12;\n 6'b1_0010_1 : o_data = 4'd8;\n 6'b1_0011_1 : o_data = 4'd2;\n 6'b1_0100_1 : o_data = 4'd4;\n 6'b1_0101_1 : o_data = 4'd9;\n 6'b1_0110_1 : o_data = 4'd1;\n 6'b1_0111_1 : o_data = 4'd7;\n 6'b1_1000_1 : o_data = 4'd5;\n 6'b1_1001_1 : o_data = 4'd11;\n 6'b1_1010_1 : o_data = 4'd3;\n 6'b1_1011_1 : o_data = 4'd14;\n 6'b1_1100_1 : o_data = 4'd10;\n 6'b1_1101_1 : o_data = 4'd0;\n 6'b1_1110_1 : o_data = 4'd6;\n 6'b1_1111_1 : o_data = 4'd13;\n default: o_data = 4'd0;\n endcase\nend\n\nendmodule : S1", + "rtl/S2.sv": "module S2(\n input logic [5:0] i_data,\n output logic [3:0] o_data\n);\n\nalways_comb begin\n case (i_data)\n 6'b0_0000_0 : o_data = 4'd15;\n 6'b0_0001_0 : o_data = 4'd1;\n 6'b0_0010_0 : o_data = 4'd8;\n 6'b0_0011_0 : o_data = 4'd14;\n 6'b0_0100_0 : o_data = 4'd6;\n 6'b0_0101_0 : o_data = 4'd11;\n 6'b0_0110_0 : o_data = 4'd3;\n 6'b0_0111_0 : o_data = 4'd4;\n 6'b0_1000_0 : o_data = 4'd9;\n 6'b0_1001_0 : o_data = 4'd7;\n 6'b0_1010_0 : o_data = 4'd2;\n 6'b0_1011_0 : o_data = 4'd13;\n 6'b0_1100_0 : o_data = 4'd12;\n 6'b0_1101_0 : o_data = 4'd0;\n 6'b0_1110_0 : o_data = 4'd5;\n 6'b0_1111_0 : o_data = 4'd10;\n 6'b0_0000_1 : o_data = 4'd3;\n 6'b0_0001_1 : o_data = 4'd13;\n 6'b0_0010_1 : o_data = 4'd4;\n 6'b0_0011_1 : o_data = 4'd7;\n 6'b0_0100_1 : o_data = 4'd15;\n 6'b0_0101_1 : o_data = 4'd2;\n 6'b0_0110_1 : o_data = 4'd8;\n 6'b0_0111_1 : o_data = 4'd14;\n 6'b0_1000_1 : o_data = 4'd12;\n 6'b0_1001_1 : o_data = 4'd0;\n 6'b0_1010_1 : o_data = 4'd1;\n 6'b0_1011_1 : o_data = 4'd10;\n 6'b0_1100_1 : o_data = 4'd6;\n 6'b0_1101_1 : o_data = 4'd9;\n 6'b0_1110_1 : o_data = 4'd11;\n 6'b0_1111_1 : o_data = 4'd5;\n 6'b1_0000_0 : o_data = 4'd0;\n 6'b1_0001_0 : o_data = 4'd14;\n 6'b1_0010_0 : o_data = 4'd7;\n 6'b1_0011_0 : o_data = 4'd11;\n 6'b1_0100_0 : o_data = 4'd10;\n 6'b1_0101_0 : o_data = 4'd4;\n 6'b1_0110_0 : o_data = 4'd13;\n 6'b1_0111_0 : o_data = 4'd1;\n 6'b1_1000_0 : o_data = 4'd5;\n 6'b1_1001_0 : o_data = 4'd8;\n 6'b1_1010_0 : o_data = 4'd12;\n 6'b1_1011_0 : o_data = 4'd6;\n 6'b1_1100_0 : o_data = 4'd9;\n 6'b1_1101_0 : o_data = 4'd3;\n 6'b1_1110_0 : o_data = 4'd2;\n 6'b1_1111_0 : o_data = 4'd15;\n 6'b1_0000_1 : o_data = 4'd13;\n 6'b1_0001_1 : o_data = 4'd8;\n 6'b1_0010_1 : o_data = 4'd10;\n 6'b1_0011_1 : o_data = 4'd1;\n 6'b1_0100_1 : o_data = 4'd3;\n 6'b1_0101_1 : o_data = 4'd15;\n 6'b1_0110_1 : o_data = 4'd4;\n 6'b1_0111_1 : o_data = 4'd2;\n 6'b1_1000_1 : o_data = 4'd11;\n 6'b1_1001_1 : o_data = 4'd6;\n 6'b1_1010_1 : o_data = 4'd7;\n 6'b1_1011_1 : o_data = 4'd12;\n 6'b1_1100_1 : o_data = 4'd0;\n 6'b1_1101_1 : o_data = 4'd5;\n 6'b1_1110_1 : o_data = 4'd14;\n 6'b1_1111_1 : o_data = 4'd9;\n default: o_data = 4'd0;\n endcase\nend\n\nendmodule : S2", + "rtl/S3.sv": "module S3(\n input logic [5:0] i_data,\n output logic [3:0] o_data\n);\n\nalways_comb begin\n case (i_data)\n 6'b0_0000_0 : o_data = 4'd10;\n 6'b0_0001_0 : o_data = 4'd0;\n 6'b0_0010_0 : o_data = 4'd9;\n 6'b0_0011_0 : o_data = 4'd14;\n 6'b0_0100_0 : o_data = 4'd6;\n 6'b0_0101_0 : o_data = 4'd3;\n 6'b0_0110_0 : o_data = 4'd15;\n 6'b0_0111_0 : o_data = 4'd5;\n 6'b0_1000_0 : o_data = 4'd1;\n 6'b0_1001_0 : o_data = 4'd13;\n 6'b0_1010_0 : o_data = 4'd12;\n 6'b0_1011_0 : o_data = 4'd7;\n 6'b0_1100_0 : o_data = 4'd11;\n 6'b0_1101_0 : o_data = 4'd4;\n 6'b0_1110_0 : o_data = 4'd2;\n 6'b0_1111_0 : o_data = 4'd8;\n 6'b0_0000_1 : o_data = 4'd13;\n 6'b0_0001_1 : o_data = 4'd7;\n 6'b0_0010_1 : o_data = 4'd0;\n 6'b0_0011_1 : o_data = 4'd9;\n 6'b0_0100_1 : o_data = 4'd3;\n 6'b0_0101_1 : o_data = 4'd4;\n 6'b0_0110_1 : o_data = 4'd6;\n 6'b0_0111_1 : o_data = 4'd10;\n 6'b0_1000_1 : o_data = 4'd2;\n 6'b0_1001_1 : o_data = 4'd8;\n 6'b0_1010_1 : o_data = 4'd5;\n 6'b0_1011_1 : o_data = 4'd14;\n 6'b0_1100_1 : o_data = 4'd12;\n 6'b0_1101_1 : o_data = 4'd11;\n 6'b0_1110_1 : o_data = 4'd15;\n 6'b0_1111_1 : o_data = 4'd1;\n 6'b1_0000_0 : o_data = 4'd13;\n 6'b1_0001_0 : o_data = 4'd6;\n 6'b1_0010_0 : o_data = 4'd4;\n 6'b1_0011_0 : o_data = 4'd9;\n 6'b1_0100_0 : o_data = 4'd8;\n 6'b1_0101_0 : o_data = 4'd15;\n 6'b1_0110_0 : o_data = 4'd3;\n 6'b1_0111_0 : o_data = 4'd0;\n 6'b1_1000_0 : o_data = 4'd11;\n 6'b1_1001_0 : o_data = 4'd1;\n 6'b1_1010_0 : o_data = 4'd2;\n 6'b1_1011_0 : o_data = 4'd12;\n 6'b1_1100_0 : o_data = 4'd5;\n 6'b1_1101_0 : o_data = 4'd10;\n 6'b1_1110_0 : o_data = 4'd14;\n 6'b1_1111_0 : o_data = 4'd7;\n 6'b1_0000_1 : o_data = 4'd1;\n 6'b1_0001_1 : o_data = 4'd10;\n 6'b1_0010_1 : o_data = 4'd13;\n 6'b1_0011_1 : o_data = 4'd0;\n 6'b1_0100_1 : o_data = 4'd6;\n 6'b1_0101_1 : o_data = 4'd9;\n 6'b1_0110_1 : o_data = 4'd8;\n 6'b1_0111_1 : o_data = 4'd7;\n 6'b1_1000_1 : o_data = 4'd4;\n 6'b1_1001_1 : o_data = 4'd15;\n 6'b1_1010_1 : o_data = 4'd14;\n 6'b1_1011_1 : o_data = 4'd3;\n 6'b1_1100_1 : o_data = 4'd11;\n 6'b1_1101_1 : o_data = 4'd5;\n 6'b1_1110_1 : o_data = 4'd2;\n 6'b1_1111_1 : o_data = 4'd12;\n default: o_data = 4'd0;\n endcase\nend\n\nendmodule : S3", + "rtl/S4.sv": "module S4(\n input logic [5:0] i_data,\n output logic [3:0] o_data\n);\n\nalways_comb begin\n case (i_data)\n 6'b0_0000_0 : o_data = 4'd7;\n 6'b0_0001_0 : o_data = 4'd13;\n 6'b0_0010_0 : o_data = 4'd14;\n 6'b0_0011_0 : o_data = 4'd3;\n 6'b0_0100_0 : o_data = 4'd0;\n 6'b0_0101_0 : o_data = 4'd6;\n 6'b0_0110_0 : o_data = 4'd9;\n 6'b0_0111_0 : o_data = 4'd10;\n 6'b0_1000_0 : o_data = 4'd1;\n 6'b0_1001_0 : o_data = 4'd2;\n 6'b0_1010_0 : o_data = 4'd8;\n 6'b0_1011_0 : o_data = 4'd5;\n 6'b0_1100_0 : o_data = 4'd11;\n 6'b0_1101_0 : o_data = 4'd12;\n 6'b0_1110_0 : o_data = 4'd4;\n 6'b0_1111_0 : o_data = 4'd15;\n 6'b0_0000_1 : o_data = 4'd13;\n 6'b0_0001_1 : o_data = 4'd8;\n 6'b0_0010_1 : o_data = 4'd11;\n 6'b0_0011_1 : o_data = 4'd5;\n 6'b0_0100_1 : o_data = 4'd6;\n 6'b0_0101_1 : o_data = 4'd15;\n 6'b0_0110_1 : o_data = 4'd0;\n 6'b0_0111_1 : o_data = 4'd3;\n 6'b0_1000_1 : o_data = 4'd4;\n 6'b0_1001_1 : o_data = 4'd7;\n 6'b0_1010_1 : o_data = 4'd2;\n 6'b0_1011_1 : o_data = 4'd12;\n 6'b0_1100_1 : o_data = 4'd1;\n 6'b0_1101_1 : o_data = 4'd10;\n 6'b0_1110_1 : o_data = 4'd14;\n 6'b0_1111_1 : o_data = 4'd9;\n 6'b1_0000_0 : o_data = 4'd10;\n 6'b1_0001_0 : o_data = 4'd6;\n 6'b1_0010_0 : o_data = 4'd9;\n 6'b1_0011_0 : o_data = 4'd0;\n 6'b1_0100_0 : o_data = 4'd12;\n 6'b1_0101_0 : o_data = 4'd11;\n 6'b1_0110_0 : o_data = 4'd7;\n 6'b1_0111_0 : o_data = 4'd13;\n 6'b1_1000_0 : o_data = 4'd15;\n 6'b1_1001_0 : o_data = 4'd1;\n 6'b1_1010_0 : o_data = 4'd3;\n 6'b1_1011_0 : o_data = 4'd14;\n 6'b1_1100_0 : o_data = 4'd5;\n 6'b1_1101_0 : o_data = 4'd2;\n 6'b1_1110_0 : o_data = 4'd8;\n 6'b1_1111_0 : o_data = 4'd4;\n 6'b1_0000_1 : o_data = 4'd3;\n 6'b1_0001_1 : o_data = 4'd15;\n 6'b1_0010_1 : o_data = 4'd0;\n 6'b1_0011_1 : o_data = 4'd6;\n 6'b1_0100_1 : o_data = 4'd10;\n 6'b1_0101_1 : o_data = 4'd1;\n 6'b1_0110_1 : o_data = 4'd13;\n 6'b1_0111_1 : o_data = 4'd8;\n 6'b1_1000_1 : o_data = 4'd9;\n 6'b1_1001_1 : o_data = 4'd4;\n 6'b1_1010_1 : o_data = 4'd5;\n 6'b1_1011_1 : o_data = 4'd11;\n 6'b1_1100_1 : o_data = 4'd12;\n 6'b1_1101_1 : o_data = 4'd7;\n 6'b1_1110_1 : o_data = 4'd2;\n 6'b1_1111_1 : o_data = 4'd14;\n default: o_data = 4'd0;\n endcase\nend\n\nendmodule : S4", + "rtl/S5.sv": "module S5(\n input logic [5:0] i_data,\n output logic [3:0] o_data\n);\n\nalways_comb begin\n case (i_data)\n 6'b0_0000_0 : o_data = 4'd2;\n 6'b0_0001_0 : o_data = 4'd12;\n 6'b0_0010_0 : o_data = 4'd4;\n 6'b0_0011_0 : o_data = 4'd1;\n 6'b0_0100_0 : o_data = 4'd7;\n 6'b0_0101_0 : o_data = 4'd10;\n 6'b0_0110_0 : o_data = 4'd11;\n 6'b0_0111_0 : o_data = 4'd6;\n 6'b0_1000_0 : o_data = 4'd8;\n 6'b0_1001_0 : o_data = 4'd5;\n 6'b0_1010_0 : o_data = 4'd3;\n 6'b0_1011_0 : o_data = 4'd15;\n 6'b0_1100_0 : o_data = 4'd13;\n 6'b0_1101_0 : o_data = 4'd0;\n 6'b0_1110_0 : o_data = 4'd14;\n 6'b0_1111_0 : o_data = 4'd9;\n 6'b0_0000_1 : o_data = 4'd14;\n 6'b0_0001_1 : o_data = 4'd11;\n 6'b0_0010_1 : o_data = 4'd2;\n 6'b0_0011_1 : o_data = 4'd12;\n 6'b0_0100_1 : o_data = 4'd4;\n 6'b0_0101_1 : o_data = 4'd7;\n 6'b0_0110_1 : o_data = 4'd13;\n 6'b0_0111_1 : o_data = 4'd1;\n 6'b0_1000_1 : o_data = 4'd5;\n 6'b0_1001_1 : o_data = 4'd0;\n 6'b0_1010_1 : o_data = 4'd15;\n 6'b0_1011_1 : o_data = 4'd10;\n 6'b0_1100_1 : o_data = 4'd3;\n 6'b0_1101_1 : o_data = 4'd9;\n 6'b0_1110_1 : o_data = 4'd8;\n 6'b0_1111_1 : o_data = 4'd6;\n 6'b1_0000_0 : o_data = 4'd4;\n 6'b1_0001_0 : o_data = 4'd2;\n 6'b1_0010_0 : o_data = 4'd1;\n 6'b1_0011_0 : o_data = 4'd11;\n 6'b1_0100_0 : o_data = 4'd10;\n 6'b1_0101_0 : o_data = 4'd13;\n 6'b1_0110_0 : o_data = 4'd7;\n 6'b1_0111_0 : o_data = 4'd8;\n 6'b1_1000_0 : o_data = 4'd15;\n 6'b1_1001_0 : o_data = 4'd9;\n 6'b1_1010_0 : o_data = 4'd12;\n 6'b1_1011_0 : o_data = 4'd5;\n 6'b1_1100_0 : o_data = 4'd6;\n 6'b1_1101_0 : o_data = 4'd3;\n 6'b1_1110_0 : o_data = 4'd0;\n 6'b1_1111_0 : o_data = 4'd14;\n 6'b1_0000_1 : o_data = 4'd11;\n 6'b1_0001_1 : o_data = 4'd8;\n 6'b1_0010_1 : o_data = 4'd12;\n 6'b1_0011_1 : o_data = 4'd7;\n 6'b1_0100_1 : o_data = 4'd1;\n 6'b1_0101_1 : o_data = 4'd14;\n 6'b1_0110_1 : o_data = 4'd2;\n 6'b1_0111_1 : o_data = 4'd13;\n 6'b1_1000_1 : o_data = 4'd6;\n 6'b1_1001_1 : o_data = 4'd15;\n 6'b1_1010_1 : o_data = 4'd0;\n 6'b1_1011_1 : o_data = 4'd9;\n 6'b1_1100_1 : o_data = 4'd10;\n 6'b1_1101_1 : o_data = 4'd4;\n 6'b1_1110_1 : o_data = 4'd5;\n 6'b1_1111_1 : o_data = 4'd3;\n default: o_data = 4'd0;\n endcase\nend\n\nendmodule : S5", + "rtl/S6.sv": "module S6(\n input logic [5:0] i_data,\n output logic [3:0] o_data\n);\n\nalways_comb begin\n case (i_data)\n 6'b0_0000_0 : o_data = 4'd12;\n 6'b0_0001_0 : o_data = 4'd1;\n 6'b0_0010_0 : o_data = 4'd10;\n 6'b0_0011_0 : o_data = 4'd15;\n 6'b0_0100_0 : o_data = 4'd9;\n 6'b0_0101_0 : o_data = 4'd2;\n 6'b0_0110_0 : o_data = 4'd6;\n 6'b0_0111_0 : o_data = 4'd8;\n 6'b0_1000_0 : o_data = 4'd0;\n 6'b0_1001_0 : o_data = 4'd13;\n 6'b0_1010_0 : o_data = 4'd3;\n 6'b0_1011_0 : o_data = 4'd4;\n 6'b0_1100_0 : o_data = 4'd14;\n 6'b0_1101_0 : o_data = 4'd7;\n 6'b0_1110_0 : o_data = 4'd5;\n 6'b0_1111_0 : o_data = 4'd11;\n 6'b0_0000_1 : o_data = 4'd10;\n 6'b0_0001_1 : o_data = 4'd15;\n 6'b0_0010_1 : o_data = 4'd4;\n 6'b0_0011_1 : o_data = 4'd2;\n 6'b0_0100_1 : o_data = 4'd7;\n 6'b0_0101_1 : o_data = 4'd12;\n 6'b0_0110_1 : o_data = 4'd9;\n 6'b0_0111_1 : o_data = 4'd5;\n 6'b0_1000_1 : o_data = 4'd6;\n 6'b0_1001_1 : o_data = 4'd1;\n 6'b0_1010_1 : o_data = 4'd13;\n 6'b0_1011_1 : o_data = 4'd14;\n 6'b0_1100_1 : o_data = 4'd0;\n 6'b0_1101_1 : o_data = 4'd11;\n 6'b0_1110_1 : o_data = 4'd3;\n 6'b0_1111_1 : o_data = 4'd8;\n 6'b1_0000_0 : o_data = 4'd9;\n 6'b1_0001_0 : o_data = 4'd14;\n 6'b1_0010_0 : o_data = 4'd15;\n 6'b1_0011_0 : o_data = 4'd5;\n 6'b1_0100_0 : o_data = 4'd2;\n 6'b1_0101_0 : o_data = 4'd8;\n 6'b1_0110_0 : o_data = 4'd12;\n 6'b1_0111_0 : o_data = 4'd3;\n 6'b1_1000_0 : o_data = 4'd7;\n 6'b1_1001_0 : o_data = 4'd0;\n 6'b1_1010_0 : o_data = 4'd4;\n 6'b1_1011_0 : o_data = 4'd10;\n 6'b1_1100_0 : o_data = 4'd1;\n 6'b1_1101_0 : o_data = 4'd13;\n 6'b1_1110_0 : o_data = 4'd11;\n 6'b1_1111_0 : o_data = 4'd6;\n 6'b1_0000_1 : o_data = 4'd4;\n 6'b1_0001_1 : o_data = 4'd3;\n 6'b1_0010_1 : o_data = 4'd2;\n 6'b1_0011_1 : o_data = 4'd12;\n 6'b1_0100_1 : o_data = 4'd9;\n 6'b1_0101_1 : o_data = 4'd5;\n 6'b1_0110_1 : o_data = 4'd15;\n 6'b1_0111_1 : o_data = 4'd10;\n 6'b1_1000_1 : o_data = 4'd11;\n 6'b1_1001_1 : o_data = 4'd14;\n 6'b1_1010_1 : o_data = 4'd1;\n 6'b1_1011_1 : o_data = 4'd7;\n 6'b1_1100_1 : o_data = 4'd6;\n 6'b1_1101_1 : o_data = 4'd0;\n 6'b1_1110_1 : o_data = 4'd8;\n 6'b1_1111_1 : o_data = 4'd13;\n default: o_data = 4'd0;\n endcase\nend\n\nendmodule : S6", + "rtl/S7.sv": "module S7(\n input logic [5:0] i_data,\n output logic [3:0] o_data\n);\n\nalways_comb begin\n case (i_data)\n 6'b0_0000_0 : o_data = 4'd4;\n 6'b0_0001_0 : o_data = 4'd11;\n 6'b0_0010_0 : o_data = 4'd2;\n 6'b0_0011_0 : o_data = 4'd14;\n 6'b0_0100_0 : o_data = 4'd15;\n 6'b0_0101_0 : o_data = 4'd0;\n 6'b0_0110_0 : o_data = 4'd8;\n 6'b0_0111_0 : o_data = 4'd13;\n 6'b0_1000_0 : o_data = 4'd3;\n 6'b0_1001_0 : o_data = 4'd12;\n 6'b0_1010_0 : o_data = 4'd9;\n 6'b0_1011_0 : o_data = 4'd7;\n 6'b0_1100_0 : o_data = 4'd5;\n 6'b0_1101_0 : o_data = 4'd10;\n 6'b0_1110_0 : o_data = 4'd6;\n 6'b0_1111_0 : o_data = 4'd1;\n 6'b0_0000_1 : o_data = 4'd13;\n 6'b0_0001_1 : o_data = 4'd0;\n 6'b0_0010_1 : o_data = 4'd11;\n 6'b0_0011_1 : o_data = 4'd7;\n 6'b0_0100_1 : o_data = 4'd4;\n 6'b0_0101_1 : o_data = 4'd9;\n 6'b0_0110_1 : o_data = 4'd1;\n 6'b0_0111_1 : o_data = 4'd10;\n 6'b0_1000_1 : o_data = 4'd14;\n 6'b0_1001_1 : o_data = 4'd3;\n 6'b0_1010_1 : o_data = 4'd5;\n 6'b0_1011_1 : o_data = 4'd12;\n 6'b0_1100_1 : o_data = 4'd2;\n 6'b0_1101_1 : o_data = 4'd15;\n 6'b0_1110_1 : o_data = 4'd8;\n 6'b0_1111_1 : o_data = 4'd6;\n 6'b1_0000_0 : o_data = 4'd1;\n 6'b1_0001_0 : o_data = 4'd4;\n 6'b1_0010_0 : o_data = 4'd11;\n 6'b1_0011_0 : o_data = 4'd13;\n 6'b1_0100_0 : o_data = 4'd12;\n 6'b1_0101_0 : o_data = 4'd3;\n 6'b1_0110_0 : o_data = 4'd7;\n 6'b1_0111_0 : o_data = 4'd14;\n 6'b1_1000_0 : o_data = 4'd10;\n 6'b1_1001_0 : o_data = 4'd15;\n 6'b1_1010_0 : o_data = 4'd6;\n 6'b1_1011_0 : o_data = 4'd8;\n 6'b1_1100_0 : o_data = 4'd0;\n 6'b1_1101_0 : o_data = 4'd5;\n 6'b1_1110_0 : o_data = 4'd9;\n 6'b1_1111_0 : o_data = 4'd2;\n 6'b1_0000_1 : o_data = 4'd6;\n 6'b1_0001_1 : o_data = 4'd11;\n 6'b1_0010_1 : o_data = 4'd13;\n 6'b1_0011_1 : o_data = 4'd8;\n 6'b1_0100_1 : o_data = 4'd1;\n 6'b1_0101_1 : o_data = 4'd4;\n 6'b1_0110_1 : o_data = 4'd10;\n 6'b1_0111_1 : o_data = 4'd7;\n 6'b1_1000_1 : o_data = 4'd9;\n 6'b1_1001_1 : o_data = 4'd5;\n 6'b1_1010_1 : o_data = 4'd0;\n 6'b1_1011_1 : o_data = 4'd15;\n 6'b1_1100_1 : o_data = 4'd14;\n 6'b1_1101_1 : o_data = 4'd2;\n 6'b1_1110_1 : o_data = 4'd3;\n 6'b1_1111_1 : o_data = 4'd12;\n default: o_data = 4'd0;\n endcase\nend\n\nendmodule : S7", + "rtl/S8.sv": "module S8(\n input logic [5:0] i_data,\n output logic [3:0] o_data\n);\n\nalways_comb begin\n case (i_data)\n 6'b0_0000_0 : o_data = 4'd13;\n 6'b0_0001_0 : o_data = 4'd2;\n 6'b0_0010_0 : o_data = 4'd8;\n 6'b0_0011_0 : o_data = 4'd4;\n 6'b0_0100_0 : o_data = 4'd6;\n 6'b0_0101_0 : o_data = 4'd15;\n 6'b0_0110_0 : o_data = 4'd11;\n 6'b0_0111_0 : o_data = 4'd1;\n 6'b0_1000_0 : o_data = 4'd10;\n 6'b0_1001_0 : o_data = 4'd9;\n 6'b0_1010_0 : o_data = 4'd3;\n 6'b0_1011_0 : o_data = 4'd14;\n 6'b0_1100_0 : o_data = 4'd5;\n 6'b0_1101_0 : o_data = 4'd0;\n 6'b0_1110_0 : o_data = 4'd12;\n 6'b0_1111_0 : o_data = 4'd7;\n 6'b0_0000_1 : o_data = 4'd1;\n 6'b0_0001_1 : o_data = 4'd15;\n 6'b0_0010_1 : o_data = 4'd13;\n 6'b0_0011_1 : o_data = 4'd8;\n 6'b0_0100_1 : o_data = 4'd10;\n 6'b0_0101_1 : o_data = 4'd3;\n 6'b0_0110_1 : o_data = 4'd7;\n 6'b0_0111_1 : o_data = 4'd4;\n 6'b0_1000_1 : o_data = 4'd12;\n 6'b0_1001_1 : o_data = 4'd5;\n 6'b0_1010_1 : o_data = 4'd6;\n 6'b0_1011_1 : o_data = 4'd11;\n 6'b0_1100_1 : o_data = 4'd0;\n 6'b0_1101_1 : o_data = 4'd14;\n 6'b0_1110_1 : o_data = 4'd9;\n 6'b0_1111_1 : o_data = 4'd2;\n 6'b1_0000_0 : o_data = 4'd7;\n 6'b1_0001_0 : o_data = 4'd11;\n 6'b1_0010_0 : o_data = 4'd4;\n 6'b1_0011_0 : o_data = 4'd1;\n 6'b1_0100_0 : o_data = 4'd9;\n 6'b1_0101_0 : o_data = 4'd12;\n 6'b1_0110_0 : o_data = 4'd14;\n 6'b1_0111_0 : o_data = 4'd2;\n 6'b1_1000_0 : o_data = 4'd0;\n 6'b1_1001_0 : o_data = 4'd6;\n 6'b1_1010_0 : o_data = 4'd10;\n 6'b1_1011_0 : o_data = 4'd13;\n 6'b1_1100_0 : o_data = 4'd15;\n 6'b1_1101_0 : o_data = 4'd3;\n 6'b1_1110_0 : o_data = 4'd5;\n 6'b1_1111_0 : o_data = 4'd8;\n 6'b1_0000_1 : o_data = 4'd2;\n 6'b1_0001_1 : o_data = 4'd1;\n 6'b1_0010_1 : o_data = 4'd14;\n 6'b1_0011_1 : o_data = 4'd7;\n 6'b1_0100_1 : o_data = 4'd4;\n 6'b1_0101_1 : o_data = 4'd10;\n 6'b1_0110_1 : o_data = 4'd8;\n 6'b1_0111_1 : o_data = 4'd13;\n 6'b1_1000_1 : o_data = 4'd15;\n 6'b1_1001_1 : o_data = 4'd12;\n 6'b1_1010_1 : o_data = 4'd9;\n 6'b1_1011_1 : o_data = 4'd0;\n 6'b1_1100_1 : o_data = 4'd3;\n 6'b1_1101_1 : o_data = 4'd5;\n 6'b1_1110_1 : o_data = 4'd6;\n 6'b1_1111_1 : o_data = 4'd11;\n default: o_data = 4'd0;\n endcase\nend\n\nendmodule : S8", + "rtl/des_enc.sv": "module des_enc #(\n parameter NBW_DATA = 'd64,\n parameter NBW_KEY = 'd64\n) (\n input logic clk,\n input logic rst_async_n,\n input logic i_valid,\n input logic [1:NBW_DATA] i_data,\n input logic [1:NBW_KEY] i_key,\n output logic o_valid,\n output logic [1:NBW_DATA] o_data\n);\n\nlocalparam ROUNDS = 'd16;\nlocalparam EXPANDED_BLOCK = 'd48;\nlocalparam USED_KEY = 'd56;\n\nlogic [1:NBW_DATA] IP;\nlogic [1:(NBW_DATA/2)] L0;\nlogic [1:(NBW_DATA/2)] R0;\nlogic [1:(NBW_DATA/2)] L_ff [1:ROUNDS];\nlogic [1:(NBW_DATA/2)] R_ff [1:ROUNDS];\nlogic [1:(USED_KEY/2)] C0;\nlogic [1:(USED_KEY/2)] D0;\nlogic [1:(USED_KEY/2)] C_ff [1:ROUNDS];\nlogic [1:(USED_KEY/2)] D_ff [1:ROUNDS];\nlogic [1:NBW_DATA] last_perm;\nlogic [ROUNDS-1:0] valid_ff;\n\nalways_ff @ (posedge clk or negedge rst_async_n) begin\n if(!rst_async_n) begin\n valid_ff <= 0;\n end else begin\n valid_ff <= {valid_ff[ROUNDS-2:0], i_valid};\n end\nend\n\nassign o_valid = valid_ff[ROUNDS-1];\n\nassign IP = {i_data[58], i_data[50], i_data[42], i_data[34], i_data[26], i_data[18], i_data[10], i_data[2],\n i_data[60], i_data[52], i_data[44], i_data[36], i_data[28], i_data[20], i_data[12], i_data[4],\n i_data[62], i_data[54], i_data[46], i_data[38], i_data[30], i_data[22], i_data[14], i_data[6],\n i_data[64], i_data[56], i_data[48], i_data[40], i_data[32], i_data[24], i_data[16], i_data[8],\n i_data[57], i_data[49], i_data[41], i_data[33], i_data[25], i_data[17], i_data[ 9], i_data[1],\n i_data[59], i_data[51], i_data[43], i_data[35], i_data[27], i_data[19], i_data[11], i_data[3],\n i_data[61], i_data[53], i_data[45], i_data[37], i_data[29], i_data[21], i_data[13], i_data[5],\n i_data[63], i_data[55], i_data[47], i_data[39], i_data[31], i_data[23], i_data[15], i_data[7]};\n\nassign L0 = IP[1:NBW_DATA/2];\nassign R0 = IP[(NBW_DATA/2)+1:NBW_DATA];\n\nassign C0 = {i_key[57], i_key[49], i_key[41], i_key[33], i_key[25], i_key[17], i_key[ 9],\n i_key[ 1], i_key[58], i_key[50], i_key[42], i_key[34], i_key[26], i_key[18],\n i_key[10], i_key[ 2], i_key[59], i_key[51], i_key[43], i_key[35], i_key[27],\n i_key[19], i_key[11], i_key[ 3], i_key[60], i_key[52], i_key[44], i_key[36]};\n\nassign D0 = {i_key[63], i_key[55], i_key[47], i_key[39], i_key[31], i_key[23], i_key[15],\n i_key[ 7], i_key[62], i_key[54], i_key[46], i_key[38], i_key[30], i_key[22],\n i_key[14], i_key[ 6], i_key[61], i_key[53], i_key[45], i_key[37], i_key[29],\n i_key[21], i_key[13], i_key[ 5], i_key[28], i_key[20], i_key[12], i_key[ 4]};\n\ngenerate\n for (genvar i = 1; i <= ROUNDS; i++) begin : rounds\n logic [1:EXPANDED_BLOCK] round_key;\n logic [1:(USED_KEY/2)] C_nx;\n logic [1:(USED_KEY/2)] D_nx;\n logic [1:USED_KEY] perm_ch;\n logic [1:(NBW_DATA/2)] R_nx;\n logic [1:EXPANDED_BLOCK] R_expanded;\n logic [1:6] Primitive_input [1:8];\n logic [1:4] Primitive_output [1:8];\n logic [1:(NBW_DATA/2)] perm_in;\n\n assign perm_ch = {C_nx, D_nx};\n assign round_key = {perm_ch[14], perm_ch[17], perm_ch[11], perm_ch[24], perm_ch[ 1], perm_ch[ 5],\n perm_ch[ 3], perm_ch[28], perm_ch[15], perm_ch[ 6], perm_ch[21], perm_ch[10],\n perm_ch[23], perm_ch[19], perm_ch[12], perm_ch[ 4], perm_ch[26], perm_ch[ 8],\n perm_ch[16], perm_ch[ 7], perm_ch[27], perm_ch[20], perm_ch[13], perm_ch[ 2],\n perm_ch[41], perm_ch[52], perm_ch[31], perm_ch[37], perm_ch[47], perm_ch[55],\n perm_ch[30], perm_ch[40], perm_ch[51], perm_ch[45], perm_ch[33], perm_ch[48],\n perm_ch[44], perm_ch[49], perm_ch[39], perm_ch[56], perm_ch[34], perm_ch[53],\n perm_ch[46], perm_ch[42], perm_ch[50], perm_ch[36], perm_ch[29], perm_ch[32]};\n\n if(i == 1 || i == 2 || i == 9 || i == 16) begin\n if(i == 1) begin\n assign C_nx = {C0[2:(USED_KEY/2)], C0[1]};\n assign D_nx = {D0[2:(USED_KEY/2)], D0[1]};\n end else begin\n assign C_nx = {C_ff[i-1][2:(USED_KEY/2)], C_ff[i-1][1]};\n assign D_nx = {D_ff[i-1][2:(USED_KEY/2)], D_ff[i-1][1]};\n end\n end else begin\n assign C_nx = {C_ff[i-1][3:(USED_KEY/2)], C_ff[i-1][1:2]};\n assign D_nx = {D_ff[i-1][3:(USED_KEY/2)], D_ff[i-1][1:2]};\n end\n\n assign Primitive_input[1] = R_expanded[ 1:6 ] ^ round_key[ 1:6 ];\n assign Primitive_input[2] = R_expanded[ 7:12] ^ round_key[ 7:12];\n assign Primitive_input[3] = R_expanded[13:18] ^ round_key[13:18];\n assign Primitive_input[4] = R_expanded[19:24] ^ round_key[19:24];\n assign Primitive_input[5] = R_expanded[25:30] ^ round_key[25:30];\n assign Primitive_input[6] = R_expanded[31:36] ^ round_key[31:36];\n assign Primitive_input[7] = R_expanded[37:42] ^ round_key[37:42];\n assign Primitive_input[8] = R_expanded[43:48] ^ round_key[43:48];\n\n S1 uu_S1 (\n .i_data(Primitive_input [1]),\n .o_data(Primitive_output[1])\n );\n\n S2 uu_S2 (\n .i_data(Primitive_input [2]),\n .o_data(Primitive_output[2])\n );\n\n S3 uu_S3 (\n .i_data(Primitive_input [3]),\n .o_data(Primitive_output[3])\n );\n\n S4 uu_S4 (\n .i_data(Primitive_input [4]),\n .o_data(Primitive_output[4])\n );\n\n S5 uu_S5 (\n .i_data(Primitive_input [5]),\n .o_data(Primitive_output[5])\n );\n\n S6 uu_S6 (\n .i_data(Primitive_input [6]),\n .o_data(Primitive_output[6])\n );\n\n S7 uu_S7 (\n .i_data(Primitive_input [7]),\n .o_data(Primitive_output[7])\n );\n\n S8 uu_S8 (\n .i_data(Primitive_input [8]),\n .o_data(Primitive_output[8])\n );\n\n assign perm_in = {Primitive_output[1], Primitive_output[2], Primitive_output[3], Primitive_output[4],\n Primitive_output[5], Primitive_output[6], Primitive_output[7], Primitive_output[8]};\n\n assign R_nx = {perm_in[16], perm_in[ 7], perm_in[20], perm_in[21],\n perm_in[29], perm_in[12], perm_in[28], perm_in[17],\n perm_in[ 1], perm_in[15], perm_in[23], perm_in[26],\n perm_in[ 5], perm_in[18], perm_in[31], perm_in[10],\n perm_in[ 2], perm_in[ 8], perm_in[24], perm_in[14],\n perm_in[32], perm_in[27], perm_in[ 3], perm_in[ 9],\n perm_in[19], perm_in[13], perm_in[30], perm_in[ 6],\n perm_in[22], perm_in[11], perm_in[ 4], perm_in[25]};\n\n if(i == 1) begin\n assign R_expanded = {R0[32], R0[ 1], R0[ 2], R0[ 3], R0[ 4], R0[ 5],\n R0[ 4], R0[ 5], R0[ 6], R0[ 7], R0[ 8], R0[ 9],\n R0[ 8], R0[ 9], R0[10], R0[11], R0[12], R0[13],\n R0[12], R0[13], R0[14], R0[15], R0[16], R0[17],\n R0[16], R0[17], R0[18], R0[19], R0[20], R0[21],\n R0[20], R0[21], R0[22], R0[23], R0[24], R0[25],\n R0[24], R0[25], R0[26], R0[27], R0[28], R0[29],\n R0[28], R0[29], R0[30], R0[31], R0[32], R0[ 1]};\n\n always_ff @ (posedge clk or negedge rst_async_n) begin\n if(!rst_async_n) begin\n L_ff[i] <= 0;\n R_ff[i] <= 0;\n C_ff[i] <= 0;\n D_ff[i] <= 0;\n end else begin\n if(i_valid) begin\n L_ff[i] <= R0;\n R_ff[i] <= R_nx ^ L0;\n C_ff[i] <= C_nx;\n D_ff[i] <= D_nx;\n end\n end\n end\n end else begin\n assign R_expanded = {R_ff[i-1][32], R_ff[i-1][ 1], R_ff[i-1][ 2], R_ff[i-1][ 3], R_ff[i-1][ 4], R_ff[i-1][ 5],\n R_ff[i-1][ 4], R_ff[i-1][ 5], R_ff[i-1][ 6], R_ff[i-1][ 7], R_ff[i-1][ 8], R_ff[i-1][ 9],\n R_ff[i-1][ 8], R_ff[i-1][ 9], R_ff[i-1][10], R_ff[i-1][11], R_ff[i-1][12], R_ff[i-1][13],\n R_ff[i-1][12], R_ff[i-1][13], R_ff[i-1][14], R_ff[i-1][15], R_ff[i-1][16], R_ff[i-1][17],\n R_ff[i-1][16], R_ff[i-1][17], R_ff[i-1][18], R_ff[i-1][19], R_ff[i-1][20], R_ff[i-1][21],\n R_ff[i-1][20], R_ff[i-1][21], R_ff[i-1][22], R_ff[i-1][23], R_ff[i-1][24], R_ff[i-1][25],\n R_ff[i-1][24], R_ff[i-1][25], R_ff[i-1][26], R_ff[i-1][27], R_ff[i-1][28], R_ff[i-1][29],\n R_ff[i-1][28], R_ff[i-1][29], R_ff[i-1][30], R_ff[i-1][31], R_ff[i-1][32], R_ff[i-1][ 1]};\n\n always_ff @ (posedge clk or negedge rst_async_n) begin\n if(!rst_async_n) begin\n L_ff[i] <= 0;\n R_ff[i] <= 0;\n C_ff[i] <= 0;\n D_ff[i] <= 0;\n end else begin\n L_ff[i] <= R_ff[i-1];\n R_ff[i] <= R_nx ^ L_ff[i-1];\n C_ff[i] <= C_nx;\n D_ff[i] <= D_nx;\n end\n end\n end\n end\nendgenerate\n\nassign last_perm = {R_ff[ROUNDS], L_ff[ROUNDS]};\n\nassign o_data = {last_perm[40], last_perm[8], last_perm[48], last_perm[16], last_perm[56], last_perm[24], last_perm[64], last_perm[32],\n last_perm[39], last_perm[7], last_perm[47], last_perm[15], last_perm[55], last_perm[23], last_perm[63], last_perm[31],\n last_perm[38], last_perm[6], last_perm[46], last_perm[14], last_perm[54], last_perm[22], last_perm[62], last_perm[30],\n last_perm[37], last_perm[5], last_perm[45], last_perm[13], last_perm[53], last_perm[21], last_perm[61], last_perm[29],\n last_perm[36], last_perm[4], last_perm[44], last_perm[12], last_perm[52], last_perm[20], last_perm[60], last_perm[28],\n last_perm[35], last_perm[3], last_perm[43], last_perm[11], last_perm[51], last_perm[19], last_perm[59], last_perm[27],\n last_perm[34], last_perm[2], last_perm[42], last_perm[10], last_perm[50], last_perm[18], last_perm[58], last_perm[26],\n last_perm[33], last_perm[1], last_perm[41], last_perm[ 9], last_perm[49], last_perm[17], last_perm[57], last_perm[25]};\n\nendmodule : des_enc", + "rtl/des_dec.sv": "module des_dec #(\n parameter NBW_DATA = 'd64,\n parameter NBW_KEY = 'd64\n) (\n input logic clk,\n input logic rst_async_n,\n input logic i_valid,\n input logic [1:NBW_DATA] i_data,\n input logic [1:NBW_KEY] i_key,\n output logic o_valid,\n output logic [1:NBW_DATA] o_data\n);\n\nlocalparam ROUNDS = 'd16;\nlocalparam EXPANDED_BLOCK = 'd48;\nlocalparam USED_KEY = 'd56;\n\nlogic [1:(NBW_DATA/2)] L16;\nlogic [1:(NBW_DATA/2)] R16;\nlogic [1:(NBW_DATA/2)] L_ff [0:ROUNDS-1];\nlogic [1:(NBW_DATA/2)] R_ff [0:ROUNDS-1];\nlogic [1:(USED_KEY/2)] C16;\nlogic [1:(USED_KEY/2)] D16;\nlogic [1:(USED_KEY/2)] C_ff [0:ROUNDS-1];\nlogic [1:(USED_KEY/2)] D_ff [0:ROUNDS-1];\nlogic [1:NBW_DATA] last_perm;\nlogic [ROUNDS-1:0] valid_ff;\n\nalways_ff @ (posedge clk or negedge rst_async_n) begin\n if(!rst_async_n) begin\n valid_ff <= 0;\n end else begin\n valid_ff <= {valid_ff[ROUNDS-2:0], i_valid};\n end\nend\n\nassign o_valid = valid_ff[ROUNDS-1];\n\nassign R16 = {i_data[58], i_data[50], i_data[42], i_data[34], i_data[26], i_data[18], i_data[10], i_data[2],\n i_data[60], i_data[52], i_data[44], i_data[36], i_data[28], i_data[20], i_data[12], i_data[4],\n i_data[62], i_data[54], i_data[46], i_data[38], i_data[30], i_data[22], i_data[14], i_data[6],\n i_data[64], i_data[56], i_data[48], i_data[40], i_data[32], i_data[24], i_data[16], i_data[8]};\n\nassign L16 = {i_data[57], i_data[49], i_data[41], i_data[33], i_data[25], i_data[17], i_data[ 9], i_data[1],\n i_data[59], i_data[51], i_data[43], i_data[35], i_data[27], i_data[19], i_data[11], i_data[3],\n i_data[61], i_data[53], i_data[45], i_data[37], i_data[29], i_data[21], i_data[13], i_data[5],\n i_data[63], i_data[55], i_data[47], i_data[39], i_data[31], i_data[23], i_data[15], i_data[7]};\n\nassign C16 = {i_key[57], i_key[49], i_key[41], i_key[33], i_key[25], i_key[17], i_key[ 9],\n i_key[ 1], i_key[58], i_key[50], i_key[42], i_key[34], i_key[26], i_key[18],\n i_key[10], i_key[ 2], i_key[59], i_key[51], i_key[43], i_key[35], i_key[27],\n i_key[19], i_key[11], i_key[ 3], i_key[60], i_key[52], i_key[44], i_key[36]};\n\nassign D16 = {i_key[63], i_key[55], i_key[47], i_key[39], i_key[31], i_key[23], i_key[15],\n i_key[ 7], i_key[62], i_key[54], i_key[46], i_key[38], i_key[30], i_key[22],\n i_key[14], i_key[ 6], i_key[61], i_key[53], i_key[45], i_key[37], i_key[29],\n i_key[21], i_key[13], i_key[ 5], i_key[28], i_key[20], i_key[12], i_key[ 4]};\n\ngenerate\n for (genvar i = ROUNDS-1; i >= 0; i--) begin : rounds\n logic [1:EXPANDED_BLOCK] round_key;\n logic [1:(USED_KEY/2)] C_nx;\n logic [1:(USED_KEY/2)] D_nx;\n logic [1:USED_KEY] perm_ch;\n logic [1:(NBW_DATA/2)] L_nx;\n logic [1:EXPANDED_BLOCK] L_expanded;\n logic [1:6] Primitive_input [1:8];\n logic [1:4] Primitive_output [1:8];\n logic [1:(NBW_DATA/2)] perm_in;\n\n if(i == 15) begin\n assign perm_ch = {C16, D16};\n end else begin\n assign perm_ch = {C_ff[i+1], D_ff[i+1]};\n end\n assign round_key = {perm_ch[14], perm_ch[17], perm_ch[11], perm_ch[24], perm_ch[ 1], perm_ch[ 5],\n perm_ch[ 3], perm_ch[28], perm_ch[15], perm_ch[ 6], perm_ch[21], perm_ch[10],\n perm_ch[23], perm_ch[19], perm_ch[12], perm_ch[ 4], perm_ch[26], perm_ch[ 8],\n perm_ch[16], perm_ch[ 7], perm_ch[27], perm_ch[20], perm_ch[13], perm_ch[ 2],\n perm_ch[41], perm_ch[52], perm_ch[31], perm_ch[37], perm_ch[47], perm_ch[55],\n perm_ch[30], perm_ch[40], perm_ch[51], perm_ch[45], perm_ch[33], perm_ch[48],\n perm_ch[44], perm_ch[49], perm_ch[39], perm_ch[56], perm_ch[34], perm_ch[53],\n perm_ch[46], perm_ch[42], perm_ch[50], perm_ch[36], perm_ch[29], perm_ch[32]};\n\n if(i == 0 || i == 1 || i == 8 || i == 15) begin\n if(i == 15) begin\n assign C_nx = {C16[(USED_KEY/2)], C16[1:(USED_KEY/2)-1]};\n assign D_nx = {D16[(USED_KEY/2)], D16[1:(USED_KEY/2)-1]};\n end else begin\n assign C_nx = {C_ff[i+1][(USED_KEY/2)], C_ff[i+1][1:(USED_KEY/2)-1]};\n assign D_nx = {D_ff[i+1][(USED_KEY/2)], D_ff[i+1][1:(USED_KEY/2)-1]};\n end\n end else begin\n assign C_nx = {C_ff[i+1][(USED_KEY/2)-1+:2], C_ff[i+1][1:(USED_KEY/2)-2]};\n assign D_nx = {D_ff[i+1][(USED_KEY/2)-1+:2], D_ff[i+1][1:(USED_KEY/2)-2]};\n end\n\n assign Primitive_input[1] = L_expanded[ 1:6 ] ^ round_key[ 1:6 ];\n assign Primitive_input[2] = L_expanded[ 7:12] ^ round_key[ 7:12];\n assign Primitive_input[3] = L_expanded[13:18] ^ round_key[13:18];\n assign Primitive_input[4] = L_expanded[19:24] ^ round_key[19:24];\n assign Primitive_input[5] = L_expanded[25:30] ^ round_key[25:30];\n assign Primitive_input[6] = L_expanded[31:36] ^ round_key[31:36];\n assign Primitive_input[7] = L_expanded[37:42] ^ round_key[37:42];\n assign Primitive_input[8] = L_expanded[43:48] ^ round_key[43:48];\n\n S1 uu_S1 (\n .i_data(Primitive_input [1]),\n .o_data(Primitive_output[1])\n );\n\n S2 uu_S2 (\n .i_data(Primitive_input [2]),\n .o_data(Primitive_output[2])\n );\n\n S3 uu_S3 (\n .i_data(Primitive_input [3]),\n .o_data(Primitive_output[3])\n );\n\n S4 uu_S4 (\n .i_data(Primitive_input [4]),\n .o_data(Primitive_output[4])\n );\n\n S5 uu_S5 (\n .i_data(Primitive_input [5]),\n .o_data(Primitive_output[5])\n );\n\n S6 uu_S6 (\n .i_data(Primitive_input [6]),\n .o_data(Primitive_output[6])\n );\n\n S7 uu_S7 (\n .i_data(Primitive_input [7]),\n .o_data(Primitive_output[7])\n );\n\n S8 uu_S8 (\n .i_data(Primitive_input [8]),\n .o_data(Primitive_output[8])\n );\n\n assign perm_in = {Primitive_output[1], Primitive_output[2], Primitive_output[3], Primitive_output[4],\n Primitive_output[5], Primitive_output[6], Primitive_output[7], Primitive_output[8]};\n\n assign L_nx = {perm_in[16], perm_in[ 7], perm_in[20], perm_in[21],\n perm_in[29], perm_in[12], perm_in[28], perm_in[17],\n perm_in[ 1], perm_in[15], perm_in[23], perm_in[26],\n perm_in[ 5], perm_in[18], perm_in[31], perm_in[10],\n perm_in[ 2], perm_in[ 8], perm_in[24], perm_in[14],\n perm_in[32], perm_in[27], perm_in[ 3], perm_in[ 9],\n perm_in[19], perm_in[13], perm_in[30], perm_in[ 6],\n perm_in[22], perm_in[11], perm_in[ 4], perm_in[25]};\n\n if(i == 15) begin\n assign L_expanded = {L16[32], L16[ 1], L16[ 2], L16[ 3], L16[ 4], L16[ 5],\n L16[ 4], L16[ 5], L16[ 6], L16[ 7], L16[ 8], L16[ 9],\n L16[ 8], L16[ 9], L16[10], L16[11], L16[12], L16[13],\n L16[12], L16[13], L16[14], L16[15], L16[16], L16[17],\n L16[16], L16[17], L16[18], L16[19], L16[20], L16[21],\n L16[20], L16[21], L16[22], L16[23], L16[24], L16[25],\n L16[24], L16[25], L16[26], L16[27], L16[28], L16[29],\n L16[28], L16[29], L16[30], L16[31], L16[32], L16[ 1]};\n\n always_ff @ (posedge clk or negedge rst_async_n) begin\n if(!rst_async_n) begin\n L_ff[i] <= 0;\n R_ff[i] <= 0;\n C_ff[i] <= 0;\n D_ff[i] <= 0;\n end else begin\n if(i_valid) begin\n L_ff[i] <= L_nx ^ R16;\n R_ff[i] <= L16;\n C_ff[i] <= C_nx;\n D_ff[i] <= D_nx;\n end\n end\n end\n end else begin\n assign L_expanded = {L_ff[i+1][32], L_ff[i+1][ 1], L_ff[i+1][ 2], L_ff[i+1][ 3], L_ff[i+1][ 4], L_ff[i+1][ 5],\n L_ff[i+1][ 4], L_ff[i+1][ 5], L_ff[i+1][ 6], L_ff[i+1][ 7], L_ff[i+1][ 8], L_ff[i+1][ 9],\n L_ff[i+1][ 8], L_ff[i+1][ 9], L_ff[i+1][10], L_ff[i+1][11], L_ff[i+1][12], L_ff[i+1][13],\n L_ff[i+1][12], L_ff[i+1][13], L_ff[i+1][14], L_ff[i+1][15], L_ff[i+1][16], L_ff[i+1][17],\n L_ff[i+1][16], L_ff[i+1][17], L_ff[i+1][18], L_ff[i+1][19], L_ff[i+1][20], L_ff[i+1][21],\n L_ff[i+1][20], L_ff[i+1][21], L_ff[i+1][22], L_ff[i+1][23], L_ff[i+1][24], L_ff[i+1][25],\n L_ff[i+1][24], L_ff[i+1][25], L_ff[i+1][26], L_ff[i+1][27], L_ff[i+1][28], L_ff[i+1][29],\n L_ff[i+1][28], L_ff[i+1][29], L_ff[i+1][30], L_ff[i+1][31], L_ff[i+1][32], L_ff[i+1][ 1]};\n\n always_ff @ (posedge clk or negedge rst_async_n) begin\n if(!rst_async_n) begin\n L_ff[i] <= 0;\n R_ff[i] <= 0;\n C_ff[i] <= 0;\n D_ff[i] <= 0;\n end else begin\n L_ff[i] <= L_nx ^ R_ff[i+1];\n R_ff[i] <= L_ff[i+1];\n C_ff[i] <= C_nx;\n D_ff[i] <= D_nx;\n end\n end\n end\n end\nendgenerate\n\nassign last_perm = {L_ff[0], R_ff[0]};\n\nassign o_data = {last_perm[40], last_perm[8], last_perm[48], last_perm[16], last_perm[56], last_perm[24], last_perm[64], last_perm[32],\n last_perm[39], last_perm[7], last_perm[47], last_perm[15], last_perm[55], last_perm[23], last_perm[63], last_perm[31],\n last_perm[38], last_perm[6], last_perm[46], last_perm[14], last_perm[54], last_perm[22], last_perm[62], last_perm[30],\n last_perm[37], last_perm[5], last_perm[45], last_perm[13], last_perm[53], last_perm[21], last_perm[61], last_perm[29],\n last_perm[36], last_perm[4], last_perm[44], last_perm[12], last_perm[52], last_perm[20], last_perm[60], last_perm[28],\n last_perm[35], last_perm[3], last_perm[43], last_perm[11], last_perm[51], last_perm[19], last_perm[59], last_perm[27],\n last_perm[34], last_perm[2], last_perm[42], last_perm[10], last_perm[50], last_perm[18], last_perm[58], last_perm[26],\n last_perm[33], last_perm[1], last_perm[41], last_perm[ 9], last_perm[49], last_perm[17], last_perm[57], last_perm[25]};\n\nendmodule : des_dec", + "verif/tb_3des_enc.sv": "module tb;\n\nparameter NBW_DATA = 'd64;\nparameter NBW_KEY = 'd192;\n\nlogic clk;\nlogic rst_async_n;\nlogic i_valid;\nlogic [1:NBW_DATA] i_data;\nlogic [1:NBW_KEY ] i_key;\nlogic o_valid;\nlogic [1:NBW_DATA] o_data;\n\ndes3_enc #(\n .NBW_DATA(NBW_DATA),\n .NBW_KEY (NBW_KEY )\n) uu_des3_enc (\n .clk (clk ),\n .rst_async_n(rst_async_n),\n .i_valid (i_valid ),\n .i_data (i_data ),\n .i_key (i_key ),\n .o_valid (o_valid ),\n .o_data (o_data )\n);\n\ninitial begin\n $dumpfile(\"test.vcd\");\n $dumpvars(0,tb);\nend\n\nalways #5 clk = ~clk;\n\ntask Single_test(logic [1:NBW_KEY] key, logic [1:NBW_DATA] data, logic [1:NBW_DATA] expected);\n i_key = key;\n i_data = data;\n i_valid = 1;\n\n @(negedge clk);\n i_valid = 0;\n\n @(posedge o_valid);\n @(negedge clk);\n if(o_data != expected) begin\n $display(\"FAIL!\");\n $display(\"Expected %h, got %h\", expected, o_data);\n end else begin\n $display(\"PASS!\");\n end\nendtask\n\ntask Burst_test();\n i_key = 192'hB1FECAFEBEBAB1FEABCDABCDABCDABCD8765432187654321;\n i_data = 64'h4321432143214321;\n i_valid = 1;\n\n @(negedge clk);\n i_data = 64'h123456789ABCDEF0;\n\n @(negedge clk);\n i_data = 64'h1234123412341234;\n i_key = 192'hABCDABCDABCDABCD8765432187654321B1FECAFEBEBAB1FE;\n\n @(negedge clk);\n i_valid = 0;\n\n @(posedge o_valid);\n @(negedge clk);\n if(o_data != 64'h2749c9efcaed543a) begin\n $display(\"FAIL!\");\n $display(\"Expected %h, got %h\", 64'h2749c9efcaed543a, o_data);\n end else begin\n $display(\"PASS!\");\n end\n\n @(negedge clk);\n if(o_valid != 1) begin\n $display(\"FAIL! o_valid should be asserted here.\");\n end\n if(o_data != 64'h984d23ecef8df5fd) begin\n $display(\"FAIL!\");\n $display(\"Expected %h, got %h\", 64'h984d23ecef8df5fd, o_data);\n end else begin\n $display(\"PASS!\");\n end\n\n @(negedge clk);\n if(o_valid != 1) begin\n $display(\"FAIL! o_valid should be asserted here.\");\n end\n if(o_data != 64'h972161012599c927) begin\n $display(\"FAIL!\");\n $display(\"Expected %h, got %h\", 64'h972161012599c927, o_data);\n end else begin\n $display(\"PASS!\");\n end\n \nendtask\n\ninitial begin\n clk = 0;\n i_valid = 0;\n rst_async_n = 1;\n #1;\n rst_async_n = 0;\n #2;\n rst_async_n = 1;\n @(negedge clk);\n\n $display(\"\\nSingle Tests\");\n Single_test(192'h0123456789abcdeffedcba9876543210abcdef9876543210, 64'h0123456789ABCDEF, 64'ha4688b153da3f95b);\n Single_test(192'h0123456789abcdeffedcba9876543210abcdef9876543210, 64'hFEDCBA9876543210, 64'h7b9325d305515107);\n Single_test(192'hBEBACAFE12345678B1FECAFE876543219898898974744747, 64'hFEDCBA9876543210, 64'h71f4eedd55b0f964);\n Single_test(192'hBEBACAFE12345678B1FECAFE876543219898898974744747, 64'hB1FECAFEBEBAB1FE, 64'h2038ea8568d3f771);\n\n $display(\"\\nBurst Test\");\n Burst_test();\n\n @(negedge clk);\n @(negedge clk);\n\n $finish();\nend\n\nendmodule" + }, + "test_info": { + "test_criteria_0": [ + "for this module is available at `verif/tb_3des_enc.sv`." + ] + }, + "expected_behavior": [ + "allow burst operation, where in multiple cycles in a row the valid signal can be asserted with a new data and a new key", + "**: Implements 3DES encryption in EDE (Encrypt-Decrypt-Encrypt) mode using three 64-bit keys (K1, K2, K3). The input plaintext is encrypted with K1, decrypted with K2, and encrypted again with K3." + ], + "metadata": { + "categories": [ + "cid005", + "medium" + ], + "domain": "memory", + "complexity": "expert", + "problem_type": "design", + "has_code": true, + "has_tests": true + }, + "full_prompt": "Integrate the `des_enc` and `des_dec` modules to perform the Triple Data Encryption Standard (TDES) encryption. This new module must allow burst operation, where in multiple cycles in a row the valid signal can be asserted with a new data and a new key. No changes are required in any of the RTLs provided. A testbench for this module is available at `verif/tb_3des_enc.sv`.\n\n---\n\n## Specifications\n\n- **Module Name**: `des3_enc`\n\n- **File Name**: `des3_enc.sv` (to be added in `rtl` directory)\n\n- **Parameters**:\n - `NBW_DATA`: Bit width of the input and output data blocks.\n - Default: 64.\n - Related interface signals: `i_data`, `o_data`.\n - `NBW_KEY`: Bit width of the key.\n - Default: 192.\n - Related interface signal: `i_key`. \n - The 192-bit key is interpreted as three concatenated 64-bit DES keys (K1, K2, K3) used for Triple DES encryption, where `K1 = i_key[1:64]`, K2 = `i_key[65:128]`, and `K3 = i_key[129:192]`.\n\n- **Functionality**: Implements 3DES encryption in EDE (Encrypt-Decrypt-Encrypt) mode using three 64-bit keys (K1, K2, K3). The input plaintext is encrypted with K1, decrypted with K2, and encrypted again with K3.\n\n- **Latency**: The block's latency, from when `i_valid` is read until `o_valid` is asserted, is **48 cycles**, where each DES stage takes 16 cycles and the process is fully pipelined.\n\n---\n\n## Interface Signals\n\n | Signal | Direction | Width | Description |\n |---------------------|-----------|------------------|--------------------------------------------------------------------------------------------------------------------- |\n | `clk` | Input | 1 | Drives the sequential logic on the rising edge. |\n | `rst_async_n` | Input | 1 | Active-low asynchronous reset; clears all internal registers and state. |\n | `i_valid` | Input | 1 | Active high. Indicates that `i_data` and `i_key` are valid and ready to be processed. |\n | `i_data` | Input | [1:NBW_DATA] | 64-bit plaintext input block (MSB-first). |\n | `i_key` | Input | [1:NBW_KEY] | 192-bit 3DES key, treated as three concatenated 64-bit keys: `{K1, K2, K3}`. |\n | `o_valid` | Output | 1 | Asserted high when `o_data` contains valid encrypted data. It is asserted for as many cycles as `i_valid` is asserted. |\n | `o_data` | Output | [1:NBW_DATA] | 64-bit ciphertext output block (MSB-first). |\n\n", + "system_message": "You are a language model that has the following file operations available at your disposal:\n - **List files in a directory** by running one of the following commands: \n - `ls`\n - `tree`\n - **Read files** by using:\n - `cat `\n - **Write files** by using:\n - `echo > `\n - **Compile Verilog** by using `iverilog` such as:\n - `iverilog -o .out -g2012 `\n - **Run Simulation** by using:\n - `vvp .out`\n - **Find current working directory** by using:\n - `pwd`\n - **Update the contents of a text file from a old content to new content**\n - `sed -i \"line_number s/old_statement/new_statement/\" file.sv`\n - **To access a specific line of the file**\n - `awk 'NR==line_number' file_name.sv`\n\nYou will be given a prompt and your task is to understand it and solve the given issue by using the above-mentioned commands as needed. In the final step, you should create a Linux patch to highlight the necessary file updates to achieve the targeted goal.\n\n You will solve the problem step by step using the following approach of \n - thought (thinking process of the step you're going to take)\n - action (the command you will be running to get more details/context that's helpful to solve the problem)\n - observation (the output from the action you will observe based on which you will take your next step)\n\n The last step will be the final output summary and the patch itself in the following format \n - thought (the summary of what you did and some introduction of the patch file itself)\n - patch (a Linux-based patch that needs to be applied to reach the relevant solution)", + "raw_context": { + "docs/specification.md": null, + "rtl/decoder_data_control_64b66b.sv": null, + "rtl/encoder_control_64b66b.sv": null, + "rtl/encoder_data_64b66b.sv": null, + "rtl/aes128_encrypt.sv": null, + "verif/tb_aes128_enc.sv": null, + "rtl/aes128_decrypt.sv": null, + "rtl/aes128_key_expansion.sv": null, + "rtl/inv_sbox.sv": null, + "rtl/sbox.sv": null, + "verif/tb_aes128_dec.sv": null, + "rtl/aes_encrypt.sv": null, + "verif/tb_aes_encrypt.sv": null, + "rtl/aes_decrypt.sv": null, + "rtl/aes_ke.sv": null, + "verif/tb_aes_decrypt.sv": null, + "rtl/aes_dec_top.sv": null, + "rtl/aes_enc_top.sv": null, + "verif/tb_padding_top.sv": null, + "verif/tb_des_enc.sv": null, + "docs/Key_schedule.md": null, + "docs/Permutations.md": null, + "docs/S_box_creation.md": null, + "rtl/S1.sv": "module S1(\n input logic [5:0] i_data,\n output logic [3:0] o_data\n);\n\nalways_comb begin\n case (i_data)\n 6'b0_0000_0 : o_data = 4'd14;\n 6'b0_0001_0 : o_data = 4'd4;\n 6'b0_0010_0 : o_data = 4'd13;\n 6'b0_0011_0 : o_data = 4'd1;\n 6'b0_0100_0 : o_data = 4'd2;\n 6'b0_0101_0 : o_data = 4'd15;\n 6'b0_0110_0 : o_data = 4'd11;\n 6'b0_0111_0 : o_data = 4'd8;\n 6'b0_1000_0 : o_data = 4'd3;\n 6'b0_1001_0 : o_data = 4'd10;\n 6'b0_1010_0 : o_data = 4'd6;\n 6'b0_1011_0 : o_data = 4'd12;\n 6'b0_1100_0 : o_data = 4'd5;\n 6'b0_1101_0 : o_data = 4'd9;\n 6'b0_1110_0 : o_data = 4'd0;\n 6'b0_1111_0 : o_data = 4'd7;\n 6'b0_0000_1 : o_data = 4'd0;\n 6'b0_0001_1 : o_data = 4'd15;\n 6'b0_0010_1 : o_data = 4'd7;\n 6'b0_0011_1 : o_data = 4'd4;\n 6'b0_0100_1 : o_data = 4'd14;\n 6'b0_0101_1 : o_data = 4'd2;\n 6'b0_0110_1 : o_data = 4'd13;\n 6'b0_0111_1 : o_data = 4'd1;\n 6'b0_1000_1 : o_data = 4'd10;\n 6'b0_1001_1 : o_data = 4'd6;\n 6'b0_1010_1 : o_data = 4'd12;\n 6'b0_1011_1 : o_data = 4'd11;\n 6'b0_1100_1 : o_data = 4'd9;\n 6'b0_1101_1 : o_data = 4'd5;\n 6'b0_1110_1 : o_data = 4'd3;\n 6'b0_1111_1 : o_data = 4'd8;\n 6'b1_0000_0 : o_data = 4'd4;\n 6'b1_0001_0 : o_data = 4'd1;\n 6'b1_0010_0 : o_data = 4'd14;\n 6'b1_0011_0 : o_data = 4'd8;\n 6'b1_0100_0 : o_data = 4'd13;\n 6'b1_0101_0 : o_data = 4'd6;\n 6'b1_0110_0 : o_data = 4'd2;\n 6'b1_0111_0 : o_data = 4'd11;\n 6'b1_1000_0 : o_data = 4'd15;\n 6'b1_1001_0 : o_data = 4'd12;\n 6'b1_1010_0 : o_data = 4'd9;\n 6'b1_1011_0 : o_data = 4'd7;\n 6'b1_1100_0 : o_data = 4'd3;\n 6'b1_1101_0 : o_data = 4'd10;\n 6'b1_1110_0 : o_data = 4'd5;\n 6'b1_1111_0 : o_data = 4'd0;\n 6'b1_0000_1 : o_data = 4'd15;\n 6'b1_0001_1 : o_data = 4'd12;\n 6'b1_0010_1 : o_data = 4'd8;\n 6'b1_0011_1 : o_data = 4'd2;\n 6'b1_0100_1 : o_data = 4'd4;\n 6'b1_0101_1 : o_data = 4'd9;\n 6'b1_0110_1 : o_data = 4'd1;\n 6'b1_0111_1 : o_data = 4'd7;\n 6'b1_1000_1 : o_data = 4'd5;\n 6'b1_1001_1 : o_data = 4'd11;\n 6'b1_1010_1 : o_data = 4'd3;\n 6'b1_1011_1 : o_data = 4'd14;\n 6'b1_1100_1 : o_data = 4'd10;\n 6'b1_1101_1 : o_data = 4'd0;\n 6'b1_1110_1 : o_data = 4'd6;\n 6'b1_1111_1 : o_data = 4'd13;\n default: o_data = 4'd0;\n endcase\nend\n\nendmodule : S1", + "rtl/S2.sv": "module S2(\n input logic [5:0] i_data,\n output logic [3:0] o_data\n);\n\nalways_comb begin\n case (i_data)\n 6'b0_0000_0 : o_data = 4'd15;\n 6'b0_0001_0 : o_data = 4'd1;\n 6'b0_0010_0 : o_data = 4'd8;\n 6'b0_0011_0 : o_data = 4'd14;\n 6'b0_0100_0 : o_data = 4'd6;\n 6'b0_0101_0 : o_data = 4'd11;\n 6'b0_0110_0 : o_data = 4'd3;\n 6'b0_0111_0 : o_data = 4'd4;\n 6'b0_1000_0 : o_data = 4'd9;\n 6'b0_1001_0 : o_data = 4'd7;\n 6'b0_1010_0 : o_data = 4'd2;\n 6'b0_1011_0 : o_data = 4'd13;\n 6'b0_1100_0 : o_data = 4'd12;\n 6'b0_1101_0 : o_data = 4'd0;\n 6'b0_1110_0 : o_data = 4'd5;\n 6'b0_1111_0 : o_data = 4'd10;\n 6'b0_0000_1 : o_data = 4'd3;\n 6'b0_0001_1 : o_data = 4'd13;\n 6'b0_0010_1 : o_data = 4'd4;\n 6'b0_0011_1 : o_data = 4'd7;\n 6'b0_0100_1 : o_data = 4'd15;\n 6'b0_0101_1 : o_data = 4'd2;\n 6'b0_0110_1 : o_data = 4'd8;\n 6'b0_0111_1 : o_data = 4'd14;\n 6'b0_1000_1 : o_data = 4'd12;\n 6'b0_1001_1 : o_data = 4'd0;\n 6'b0_1010_1 : o_data = 4'd1;\n 6'b0_1011_1 : o_data = 4'd10;\n 6'b0_1100_1 : o_data = 4'd6;\n 6'b0_1101_1 : o_data = 4'd9;\n 6'b0_1110_1 : o_data = 4'd11;\n 6'b0_1111_1 : o_data = 4'd5;\n 6'b1_0000_0 : o_data = 4'd0;\n 6'b1_0001_0 : o_data = 4'd14;\n 6'b1_0010_0 : o_data = 4'd7;\n 6'b1_0011_0 : o_data = 4'd11;\n 6'b1_0100_0 : o_data = 4'd10;\n 6'b1_0101_0 : o_data = 4'd4;\n 6'b1_0110_0 : o_data = 4'd13;\n 6'b1_0111_0 : o_data = 4'd1;\n 6'b1_1000_0 : o_data = 4'd5;\n 6'b1_1001_0 : o_data = 4'd8;\n 6'b1_1010_0 : o_data = 4'd12;\n 6'b1_1011_0 : o_data = 4'd6;\n 6'b1_1100_0 : o_data = 4'd9;\n 6'b1_1101_0 : o_data = 4'd3;\n 6'b1_1110_0 : o_data = 4'd2;\n 6'b1_1111_0 : o_data = 4'd15;\n 6'b1_0000_1 : o_data = 4'd13;\n 6'b1_0001_1 : o_data = 4'd8;\n 6'b1_0010_1 : o_data = 4'd10;\n 6'b1_0011_1 : o_data = 4'd1;\n 6'b1_0100_1 : o_data = 4'd3;\n 6'b1_0101_1 : o_data = 4'd15;\n 6'b1_0110_1 : o_data = 4'd4;\n 6'b1_0111_1 : o_data = 4'd2;\n 6'b1_1000_1 : o_data = 4'd11;\n 6'b1_1001_1 : o_data = 4'd6;\n 6'b1_1010_1 : o_data = 4'd7;\n 6'b1_1011_1 : o_data = 4'd12;\n 6'b1_1100_1 : o_data = 4'd0;\n 6'b1_1101_1 : o_data = 4'd5;\n 6'b1_1110_1 : o_data = 4'd14;\n 6'b1_1111_1 : o_data = 4'd9;\n default: o_data = 4'd0;\n endcase\nend\n\nendmodule : S2", + "rtl/S3.sv": "module S3(\n input logic [5:0] i_data,\n output logic [3:0] o_data\n);\n\nalways_comb begin\n case (i_data)\n 6'b0_0000_0 : o_data = 4'd10;\n 6'b0_0001_0 : o_data = 4'd0;\n 6'b0_0010_0 : o_data = 4'd9;\n 6'b0_0011_0 : o_data = 4'd14;\n 6'b0_0100_0 : o_data = 4'd6;\n 6'b0_0101_0 : o_data = 4'd3;\n 6'b0_0110_0 : o_data = 4'd15;\n 6'b0_0111_0 : o_data = 4'd5;\n 6'b0_1000_0 : o_data = 4'd1;\n 6'b0_1001_0 : o_data = 4'd13;\n 6'b0_1010_0 : o_data = 4'd12;\n 6'b0_1011_0 : o_data = 4'd7;\n 6'b0_1100_0 : o_data = 4'd11;\n 6'b0_1101_0 : o_data = 4'd4;\n 6'b0_1110_0 : o_data = 4'd2;\n 6'b0_1111_0 : o_data = 4'd8;\n 6'b0_0000_1 : o_data = 4'd13;\n 6'b0_0001_1 : o_data = 4'd7;\n 6'b0_0010_1 : o_data = 4'd0;\n 6'b0_0011_1 : o_data = 4'd9;\n 6'b0_0100_1 : o_data = 4'd3;\n 6'b0_0101_1 : o_data = 4'd4;\n 6'b0_0110_1 : o_data = 4'd6;\n 6'b0_0111_1 : o_data = 4'd10;\n 6'b0_1000_1 : o_data = 4'd2;\n 6'b0_1001_1 : o_data = 4'd8;\n 6'b0_1010_1 : o_data = 4'd5;\n 6'b0_1011_1 : o_data = 4'd14;\n 6'b0_1100_1 : o_data = 4'd12;\n 6'b0_1101_1 : o_data = 4'd11;\n 6'b0_1110_1 : o_data = 4'd15;\n 6'b0_1111_1 : o_data = 4'd1;\n 6'b1_0000_0 : o_data = 4'd13;\n 6'b1_0001_0 : o_data = 4'd6;\n 6'b1_0010_0 : o_data = 4'd4;\n 6'b1_0011_0 : o_data = 4'd9;\n 6'b1_0100_0 : o_data = 4'd8;\n 6'b1_0101_0 : o_data = 4'd15;\n 6'b1_0110_0 : o_data = 4'd3;\n 6'b1_0111_0 : o_data = 4'd0;\n 6'b1_1000_0 : o_data = 4'd11;\n 6'b1_1001_0 : o_data = 4'd1;\n 6'b1_1010_0 : o_data = 4'd2;\n 6'b1_1011_0 : o_data = 4'd12;\n 6'b1_1100_0 : o_data = 4'd5;\n 6'b1_1101_0 : o_data = 4'd10;\n 6'b1_1110_0 : o_data = 4'd14;\n 6'b1_1111_0 : o_data = 4'd7;\n 6'b1_0000_1 : o_data = 4'd1;\n 6'b1_0001_1 : o_data = 4'd10;\n 6'b1_0010_1 : o_data = 4'd13;\n 6'b1_0011_1 : o_data = 4'd0;\n 6'b1_0100_1 : o_data = 4'd6;\n 6'b1_0101_1 : o_data = 4'd9;\n 6'b1_0110_1 : o_data = 4'd8;\n 6'b1_0111_1 : o_data = 4'd7;\n 6'b1_1000_1 : o_data = 4'd4;\n 6'b1_1001_1 : o_data = 4'd15;\n 6'b1_1010_1 : o_data = 4'd14;\n 6'b1_1011_1 : o_data = 4'd3;\n 6'b1_1100_1 : o_data = 4'd11;\n 6'b1_1101_1 : o_data = 4'd5;\n 6'b1_1110_1 : o_data = 4'd2;\n 6'b1_1111_1 : o_data = 4'd12;\n default: o_data = 4'd0;\n endcase\nend\n\nendmodule : S3", + "rtl/S4.sv": "module S4(\n input logic [5:0] i_data,\n output logic [3:0] o_data\n);\n\nalways_comb begin\n case (i_data)\n 6'b0_0000_0 : o_data = 4'd7;\n 6'b0_0001_0 : o_data = 4'd13;\n 6'b0_0010_0 : o_data = 4'd14;\n 6'b0_0011_0 : o_data = 4'd3;\n 6'b0_0100_0 : o_data = 4'd0;\n 6'b0_0101_0 : o_data = 4'd6;\n 6'b0_0110_0 : o_data = 4'd9;\n 6'b0_0111_0 : o_data = 4'd10;\n 6'b0_1000_0 : o_data = 4'd1;\n 6'b0_1001_0 : o_data = 4'd2;\n 6'b0_1010_0 : o_data = 4'd8;\n 6'b0_1011_0 : o_data = 4'd5;\n 6'b0_1100_0 : o_data = 4'd11;\n 6'b0_1101_0 : o_data = 4'd12;\n 6'b0_1110_0 : o_data = 4'd4;\n 6'b0_1111_0 : o_data = 4'd15;\n 6'b0_0000_1 : o_data = 4'd13;\n 6'b0_0001_1 : o_data = 4'd8;\n 6'b0_0010_1 : o_data = 4'd11;\n 6'b0_0011_1 : o_data = 4'd5;\n 6'b0_0100_1 : o_data = 4'd6;\n 6'b0_0101_1 : o_data = 4'd15;\n 6'b0_0110_1 : o_data = 4'd0;\n 6'b0_0111_1 : o_data = 4'd3;\n 6'b0_1000_1 : o_data = 4'd4;\n 6'b0_1001_1 : o_data = 4'd7;\n 6'b0_1010_1 : o_data = 4'd2;\n 6'b0_1011_1 : o_data = 4'd12;\n 6'b0_1100_1 : o_data = 4'd1;\n 6'b0_1101_1 : o_data = 4'd10;\n 6'b0_1110_1 : o_data = 4'd14;\n 6'b0_1111_1 : o_data = 4'd9;\n 6'b1_0000_0 : o_data = 4'd10;\n 6'b1_0001_0 : o_data = 4'd6;\n 6'b1_0010_0 : o_data = 4'd9;\n 6'b1_0011_0 : o_data = 4'd0;\n 6'b1_0100_0 : o_data = 4'd12;\n 6'b1_0101_0 : o_data = 4'd11;\n 6'b1_0110_0 : o_data = 4'd7;\n 6'b1_0111_0 : o_data = 4'd13;\n 6'b1_1000_0 : o_data = 4'd15;\n 6'b1_1001_0 : o_data = 4'd1;\n 6'b1_1010_0 : o_data = 4'd3;\n 6'b1_1011_0 : o_data = 4'd14;\n 6'b1_1100_0 : o_data = 4'd5;\n 6'b1_1101_0 : o_data = 4'd2;\n 6'b1_1110_0 : o_data = 4'd8;\n 6'b1_1111_0 : o_data = 4'd4;\n 6'b1_0000_1 : o_data = 4'd3;\n 6'b1_0001_1 : o_data = 4'd15;\n 6'b1_0010_1 : o_data = 4'd0;\n 6'b1_0011_1 : o_data = 4'd6;\n 6'b1_0100_1 : o_data = 4'd10;\n 6'b1_0101_1 : o_data = 4'd1;\n 6'b1_0110_1 : o_data = 4'd13;\n 6'b1_0111_1 : o_data = 4'd8;\n 6'b1_1000_1 : o_data = 4'd9;\n 6'b1_1001_1 : o_data = 4'd4;\n 6'b1_1010_1 : o_data = 4'd5;\n 6'b1_1011_1 : o_data = 4'd11;\n 6'b1_1100_1 : o_data = 4'd12;\n 6'b1_1101_1 : o_data = 4'd7;\n 6'b1_1110_1 : o_data = 4'd2;\n 6'b1_1111_1 : o_data = 4'd14;\n default: o_data = 4'd0;\n endcase\nend\n\nendmodule : S4", + "rtl/S5.sv": "module S5(\n input logic [5:0] i_data,\n output logic [3:0] o_data\n);\n\nalways_comb begin\n case (i_data)\n 6'b0_0000_0 : o_data = 4'd2;\n 6'b0_0001_0 : o_data = 4'd12;\n 6'b0_0010_0 : o_data = 4'd4;\n 6'b0_0011_0 : o_data = 4'd1;\n 6'b0_0100_0 : o_data = 4'd7;\n 6'b0_0101_0 : o_data = 4'd10;\n 6'b0_0110_0 : o_data = 4'd11;\n 6'b0_0111_0 : o_data = 4'd6;\n 6'b0_1000_0 : o_data = 4'd8;\n 6'b0_1001_0 : o_data = 4'd5;\n 6'b0_1010_0 : o_data = 4'd3;\n 6'b0_1011_0 : o_data = 4'd15;\n 6'b0_1100_0 : o_data = 4'd13;\n 6'b0_1101_0 : o_data = 4'd0;\n 6'b0_1110_0 : o_data = 4'd14;\n 6'b0_1111_0 : o_data = 4'd9;\n 6'b0_0000_1 : o_data = 4'd14;\n 6'b0_0001_1 : o_data = 4'd11;\n 6'b0_0010_1 : o_data = 4'd2;\n 6'b0_0011_1 : o_data = 4'd12;\n 6'b0_0100_1 : o_data = 4'd4;\n 6'b0_0101_1 : o_data = 4'd7;\n 6'b0_0110_1 : o_data = 4'd13;\n 6'b0_0111_1 : o_data = 4'd1;\n 6'b0_1000_1 : o_data = 4'd5;\n 6'b0_1001_1 : o_data = 4'd0;\n 6'b0_1010_1 : o_data = 4'd15;\n 6'b0_1011_1 : o_data = 4'd10;\n 6'b0_1100_1 : o_data = 4'd3;\n 6'b0_1101_1 : o_data = 4'd9;\n 6'b0_1110_1 : o_data = 4'd8;\n 6'b0_1111_1 : o_data = 4'd6;\n 6'b1_0000_0 : o_data = 4'd4;\n 6'b1_0001_0 : o_data = 4'd2;\n 6'b1_0010_0 : o_data = 4'd1;\n 6'b1_0011_0 : o_data = 4'd11;\n 6'b1_0100_0 : o_data = 4'd10;\n 6'b1_0101_0 : o_data = 4'd13;\n 6'b1_0110_0 : o_data = 4'd7;\n 6'b1_0111_0 : o_data = 4'd8;\n 6'b1_1000_0 : o_data = 4'd15;\n 6'b1_1001_0 : o_data = 4'd9;\n 6'b1_1010_0 : o_data = 4'd12;\n 6'b1_1011_0 : o_data = 4'd5;\n 6'b1_1100_0 : o_data = 4'd6;\n 6'b1_1101_0 : o_data = 4'd3;\n 6'b1_1110_0 : o_data = 4'd0;\n 6'b1_1111_0 : o_data = 4'd14;\n 6'b1_0000_1 : o_data = 4'd11;\n 6'b1_0001_1 : o_data = 4'd8;\n 6'b1_0010_1 : o_data = 4'd12;\n 6'b1_0011_1 : o_data = 4'd7;\n 6'b1_0100_1 : o_data = 4'd1;\n 6'b1_0101_1 : o_data = 4'd14;\n 6'b1_0110_1 : o_data = 4'd2;\n 6'b1_0111_1 : o_data = 4'd13;\n 6'b1_1000_1 : o_data = 4'd6;\n 6'b1_1001_1 : o_data = 4'd15;\n 6'b1_1010_1 : o_data = 4'd0;\n 6'b1_1011_1 : o_data = 4'd9;\n 6'b1_1100_1 : o_data = 4'd10;\n 6'b1_1101_1 : o_data = 4'd4;\n 6'b1_1110_1 : o_data = 4'd5;\n 6'b1_1111_1 : o_data = 4'd3;\n default: o_data = 4'd0;\n endcase\nend\n\nendmodule : S5", + "rtl/S6.sv": "module S6(\n input logic [5:0] i_data,\n output logic [3:0] o_data\n);\n\nalways_comb begin\n case (i_data)\n 6'b0_0000_0 : o_data = 4'd12;\n 6'b0_0001_0 : o_data = 4'd1;\n 6'b0_0010_0 : o_data = 4'd10;\n 6'b0_0011_0 : o_data = 4'd15;\n 6'b0_0100_0 : o_data = 4'd9;\n 6'b0_0101_0 : o_data = 4'd2;\n 6'b0_0110_0 : o_data = 4'd6;\n 6'b0_0111_0 : o_data = 4'd8;\n 6'b0_1000_0 : o_data = 4'd0;\n 6'b0_1001_0 : o_data = 4'd13;\n 6'b0_1010_0 : o_data = 4'd3;\n 6'b0_1011_0 : o_data = 4'd4;\n 6'b0_1100_0 : o_data = 4'd14;\n 6'b0_1101_0 : o_data = 4'd7;\n 6'b0_1110_0 : o_data = 4'd5;\n 6'b0_1111_0 : o_data = 4'd11;\n 6'b0_0000_1 : o_data = 4'd10;\n 6'b0_0001_1 : o_data = 4'd15;\n 6'b0_0010_1 : o_data = 4'd4;\n 6'b0_0011_1 : o_data = 4'd2;\n 6'b0_0100_1 : o_data = 4'd7;\n 6'b0_0101_1 : o_data = 4'd12;\n 6'b0_0110_1 : o_data = 4'd9;\n 6'b0_0111_1 : o_data = 4'd5;\n 6'b0_1000_1 : o_data = 4'd6;\n 6'b0_1001_1 : o_data = 4'd1;\n 6'b0_1010_1 : o_data = 4'd13;\n 6'b0_1011_1 : o_data = 4'd14;\n 6'b0_1100_1 : o_data = 4'd0;\n 6'b0_1101_1 : o_data = 4'd11;\n 6'b0_1110_1 : o_data = 4'd3;\n 6'b0_1111_1 : o_data = 4'd8;\n 6'b1_0000_0 : o_data = 4'd9;\n 6'b1_0001_0 : o_data = 4'd14;\n 6'b1_0010_0 : o_data = 4'd15;\n 6'b1_0011_0 : o_data = 4'd5;\n 6'b1_0100_0 : o_data = 4'd2;\n 6'b1_0101_0 : o_data = 4'd8;\n 6'b1_0110_0 : o_data = 4'd12;\n 6'b1_0111_0 : o_data = 4'd3;\n 6'b1_1000_0 : o_data = 4'd7;\n 6'b1_1001_0 : o_data = 4'd0;\n 6'b1_1010_0 : o_data = 4'd4;\n 6'b1_1011_0 : o_data = 4'd10;\n 6'b1_1100_0 : o_data = 4'd1;\n 6'b1_1101_0 : o_data = 4'd13;\n 6'b1_1110_0 : o_data = 4'd11;\n 6'b1_1111_0 : o_data = 4'd6;\n 6'b1_0000_1 : o_data = 4'd4;\n 6'b1_0001_1 : o_data = 4'd3;\n 6'b1_0010_1 : o_data = 4'd2;\n 6'b1_0011_1 : o_data = 4'd12;\n 6'b1_0100_1 : o_data = 4'd9;\n 6'b1_0101_1 : o_data = 4'd5;\n 6'b1_0110_1 : o_data = 4'd15;\n 6'b1_0111_1 : o_data = 4'd10;\n 6'b1_1000_1 : o_data = 4'd11;\n 6'b1_1001_1 : o_data = 4'd14;\n 6'b1_1010_1 : o_data = 4'd1;\n 6'b1_1011_1 : o_data = 4'd7;\n 6'b1_1100_1 : o_data = 4'd6;\n 6'b1_1101_1 : o_data = 4'd0;\n 6'b1_1110_1 : o_data = 4'd8;\n 6'b1_1111_1 : o_data = 4'd13;\n default: o_data = 4'd0;\n endcase\nend\n\nendmodule : S6", + "rtl/S7.sv": "module S7(\n input logic [5:0] i_data,\n output logic [3:0] o_data\n);\n\nalways_comb begin\n case (i_data)\n 6'b0_0000_0 : o_data = 4'd4;\n 6'b0_0001_0 : o_data = 4'd11;\n 6'b0_0010_0 : o_data = 4'd2;\n 6'b0_0011_0 : o_data = 4'd14;\n 6'b0_0100_0 : o_data = 4'd15;\n 6'b0_0101_0 : o_data = 4'd0;\n 6'b0_0110_0 : o_data = 4'd8;\n 6'b0_0111_0 : o_data = 4'd13;\n 6'b0_1000_0 : o_data = 4'd3;\n 6'b0_1001_0 : o_data = 4'd12;\n 6'b0_1010_0 : o_data = 4'd9;\n 6'b0_1011_0 : o_data = 4'd7;\n 6'b0_1100_0 : o_data = 4'd5;\n 6'b0_1101_0 : o_data = 4'd10;\n 6'b0_1110_0 : o_data = 4'd6;\n 6'b0_1111_0 : o_data = 4'd1;\n 6'b0_0000_1 : o_data = 4'd13;\n 6'b0_0001_1 : o_data = 4'd0;\n 6'b0_0010_1 : o_data = 4'd11;\n 6'b0_0011_1 : o_data = 4'd7;\n 6'b0_0100_1 : o_data = 4'd4;\n 6'b0_0101_1 : o_data = 4'd9;\n 6'b0_0110_1 : o_data = 4'd1;\n 6'b0_0111_1 : o_data = 4'd10;\n 6'b0_1000_1 : o_data = 4'd14;\n 6'b0_1001_1 : o_data = 4'd3;\n 6'b0_1010_1 : o_data = 4'd5;\n 6'b0_1011_1 : o_data = 4'd12;\n 6'b0_1100_1 : o_data = 4'd2;\n 6'b0_1101_1 : o_data = 4'd15;\n 6'b0_1110_1 : o_data = 4'd8;\n 6'b0_1111_1 : o_data = 4'd6;\n 6'b1_0000_0 : o_data = 4'd1;\n 6'b1_0001_0 : o_data = 4'd4;\n 6'b1_0010_0 : o_data = 4'd11;\n 6'b1_0011_0 : o_data = 4'd13;\n 6'b1_0100_0 : o_data = 4'd12;\n 6'b1_0101_0 : o_data = 4'd3;\n 6'b1_0110_0 : o_data = 4'd7;\n 6'b1_0111_0 : o_data = 4'd14;\n 6'b1_1000_0 : o_data = 4'd10;\n 6'b1_1001_0 : o_data = 4'd15;\n 6'b1_1010_0 : o_data = 4'd6;\n 6'b1_1011_0 : o_data = 4'd8;\n 6'b1_1100_0 : o_data = 4'd0;\n 6'b1_1101_0 : o_data = 4'd5;\n 6'b1_1110_0 : o_data = 4'd9;\n 6'b1_1111_0 : o_data = 4'd2;\n 6'b1_0000_1 : o_data = 4'd6;\n 6'b1_0001_1 : o_data = 4'd11;\n 6'b1_0010_1 : o_data = 4'd13;\n 6'b1_0011_1 : o_data = 4'd8;\n 6'b1_0100_1 : o_data = 4'd1;\n 6'b1_0101_1 : o_data = 4'd4;\n 6'b1_0110_1 : o_data = 4'd10;\n 6'b1_0111_1 : o_data = 4'd7;\n 6'b1_1000_1 : o_data = 4'd9;\n 6'b1_1001_1 : o_data = 4'd5;\n 6'b1_1010_1 : o_data = 4'd0;\n 6'b1_1011_1 : o_data = 4'd15;\n 6'b1_1100_1 : o_data = 4'd14;\n 6'b1_1101_1 : o_data = 4'd2;\n 6'b1_1110_1 : o_data = 4'd3;\n 6'b1_1111_1 : o_data = 4'd12;\n default: o_data = 4'd0;\n endcase\nend\n\nendmodule : S7", + "rtl/S8.sv": "module S8(\n input logic [5:0] i_data,\n output logic [3:0] o_data\n);\n\nalways_comb begin\n case (i_data)\n 6'b0_0000_0 : o_data = 4'd13;\n 6'b0_0001_0 : o_data = 4'd2;\n 6'b0_0010_0 : o_data = 4'd8;\n 6'b0_0011_0 : o_data = 4'd4;\n 6'b0_0100_0 : o_data = 4'd6;\n 6'b0_0101_0 : o_data = 4'd15;\n 6'b0_0110_0 : o_data = 4'd11;\n 6'b0_0111_0 : o_data = 4'd1;\n 6'b0_1000_0 : o_data = 4'd10;\n 6'b0_1001_0 : o_data = 4'd9;\n 6'b0_1010_0 : o_data = 4'd3;\n 6'b0_1011_0 : o_data = 4'd14;\n 6'b0_1100_0 : o_data = 4'd5;\n 6'b0_1101_0 : o_data = 4'd0;\n 6'b0_1110_0 : o_data = 4'd12;\n 6'b0_1111_0 : o_data = 4'd7;\n 6'b0_0000_1 : o_data = 4'd1;\n 6'b0_0001_1 : o_data = 4'd15;\n 6'b0_0010_1 : o_data = 4'd13;\n 6'b0_0011_1 : o_data = 4'd8;\n 6'b0_0100_1 : o_data = 4'd10;\n 6'b0_0101_1 : o_data = 4'd3;\n 6'b0_0110_1 : o_data = 4'd7;\n 6'b0_0111_1 : o_data = 4'd4;\n 6'b0_1000_1 : o_data = 4'd12;\n 6'b0_1001_1 : o_data = 4'd5;\n 6'b0_1010_1 : o_data = 4'd6;\n 6'b0_1011_1 : o_data = 4'd11;\n 6'b0_1100_1 : o_data = 4'd0;\n 6'b0_1101_1 : o_data = 4'd14;\n 6'b0_1110_1 : o_data = 4'd9;\n 6'b0_1111_1 : o_data = 4'd2;\n 6'b1_0000_0 : o_data = 4'd7;\n 6'b1_0001_0 : o_data = 4'd11;\n 6'b1_0010_0 : o_data = 4'd4;\n 6'b1_0011_0 : o_data = 4'd1;\n 6'b1_0100_0 : o_data = 4'd9;\n 6'b1_0101_0 : o_data = 4'd12;\n 6'b1_0110_0 : o_data = 4'd14;\n 6'b1_0111_0 : o_data = 4'd2;\n 6'b1_1000_0 : o_data = 4'd0;\n 6'b1_1001_0 : o_data = 4'd6;\n 6'b1_1010_0 : o_data = 4'd10;\n 6'b1_1011_0 : o_data = 4'd13;\n 6'b1_1100_0 : o_data = 4'd15;\n 6'b1_1101_0 : o_data = 4'd3;\n 6'b1_1110_0 : o_data = 4'd5;\n 6'b1_1111_0 : o_data = 4'd8;\n 6'b1_0000_1 : o_data = 4'd2;\n 6'b1_0001_1 : o_data = 4'd1;\n 6'b1_0010_1 : o_data = 4'd14;\n 6'b1_0011_1 : o_data = 4'd7;\n 6'b1_0100_1 : o_data = 4'd4;\n 6'b1_0101_1 : o_data = 4'd10;\n 6'b1_0110_1 : o_data = 4'd8;\n 6'b1_0111_1 : o_data = 4'd13;\n 6'b1_1000_1 : o_data = 4'd15;\n 6'b1_1001_1 : o_data = 4'd12;\n 6'b1_1010_1 : o_data = 4'd9;\n 6'b1_1011_1 : o_data = 4'd0;\n 6'b1_1100_1 : o_data = 4'd3;\n 6'b1_1101_1 : o_data = 4'd5;\n 6'b1_1110_1 : o_data = 4'd6;\n 6'b1_1111_1 : o_data = 4'd11;\n default: o_data = 4'd0;\n endcase\nend\n\nendmodule : S8", + "rtl/des_enc.sv": "module des_enc #(\n parameter NBW_DATA = 'd64,\n parameter NBW_KEY = 'd64\n) (\n input logic clk,\n input logic rst_async_n,\n input logic i_valid,\n input logic [1:NBW_DATA] i_data,\n input logic [1:NBW_KEY] i_key,\n output logic o_valid,\n output logic [1:NBW_DATA] o_data\n);\n\nlocalparam ROUNDS = 'd16;\nlocalparam EXPANDED_BLOCK = 'd48;\nlocalparam USED_KEY = 'd56;\n\nlogic [1:NBW_DATA] IP;\nlogic [1:(NBW_DATA/2)] L0;\nlogic [1:(NBW_DATA/2)] R0;\nlogic [1:(NBW_DATA/2)] L_ff [1:ROUNDS];\nlogic [1:(NBW_DATA/2)] R_ff [1:ROUNDS];\nlogic [1:(USED_KEY/2)] C0;\nlogic [1:(USED_KEY/2)] D0;\nlogic [1:(USED_KEY/2)] C_ff [1:ROUNDS];\nlogic [1:(USED_KEY/2)] D_ff [1:ROUNDS];\nlogic [1:NBW_DATA] last_perm;\nlogic [ROUNDS-1:0] valid_ff;\n\nalways_ff @ (posedge clk or negedge rst_async_n) begin\n if(!rst_async_n) begin\n valid_ff <= 0;\n end else begin\n valid_ff <= {valid_ff[ROUNDS-2:0], i_valid};\n end\nend\n\nassign o_valid = valid_ff[ROUNDS-1];\n\nassign IP = {i_data[58], i_data[50], i_data[42], i_data[34], i_data[26], i_data[18], i_data[10], i_data[2],\n i_data[60], i_data[52], i_data[44], i_data[36], i_data[28], i_data[20], i_data[12], i_data[4],\n i_data[62], i_data[54], i_data[46], i_data[38], i_data[30], i_data[22], i_data[14], i_data[6],\n i_data[64], i_data[56], i_data[48], i_data[40], i_data[32], i_data[24], i_data[16], i_data[8],\n i_data[57], i_data[49], i_data[41], i_data[33], i_data[25], i_data[17], i_data[ 9], i_data[1],\n i_data[59], i_data[51], i_data[43], i_data[35], i_data[27], i_data[19], i_data[11], i_data[3],\n i_data[61], i_data[53], i_data[45], i_data[37], i_data[29], i_data[21], i_data[13], i_data[5],\n i_data[63], i_data[55], i_data[47], i_data[39], i_data[31], i_data[23], i_data[15], i_data[7]};\n\nassign L0 = IP[1:NBW_DATA/2];\nassign R0 = IP[(NBW_DATA/2)+1:NBW_DATA];\n\nassign C0 = {i_key[57], i_key[49], i_key[41], i_key[33], i_key[25], i_key[17], i_key[ 9],\n i_key[ 1], i_key[58], i_key[50], i_key[42], i_key[34], i_key[26], i_key[18],\n i_key[10], i_key[ 2], i_key[59], i_key[51], i_key[43], i_key[35], i_key[27],\n i_key[19], i_key[11], i_key[ 3], i_key[60], i_key[52], i_key[44], i_key[36]};\n\nassign D0 = {i_key[63], i_key[55], i_key[47], i_key[39], i_key[31], i_key[23], i_key[15],\n i_key[ 7], i_key[62], i_key[54], i_key[46], i_key[38], i_key[30], i_key[22],\n i_key[14], i_key[ 6], i_key[61], i_key[53], i_key[45], i_key[37], i_key[29],\n i_key[21], i_key[13], i_key[ 5], i_key[28], i_key[20], i_key[12], i_key[ 4]};\n\ngenerate\n for (genvar i = 1; i <= ROUNDS; i++) begin : rounds\n logic [1:EXPANDED_BLOCK] round_key;\n logic [1:(USED_KEY/2)] C_nx;\n logic [1:(USED_KEY/2)] D_nx;\n logic [1:USED_KEY] perm_ch;\n logic [1:(NBW_DATA/2)] R_nx;\n logic [1:EXPANDED_BLOCK] R_expanded;\n logic [1:6] Primitive_input [1:8];\n logic [1:4] Primitive_output [1:8];\n logic [1:(NBW_DATA/2)] perm_in;\n\n assign perm_ch = {C_nx, D_nx};\n assign round_key = {perm_ch[14], perm_ch[17], perm_ch[11], perm_ch[24], perm_ch[ 1], perm_ch[ 5],\n perm_ch[ 3], perm_ch[28], perm_ch[15], perm_ch[ 6], perm_ch[21], perm_ch[10],\n perm_ch[23], perm_ch[19], perm_ch[12], perm_ch[ 4], perm_ch[26], perm_ch[ 8],\n perm_ch[16], perm_ch[ 7], perm_ch[27], perm_ch[20], perm_ch[13], perm_ch[ 2],\n perm_ch[41], perm_ch[52], perm_ch[31], perm_ch[37], perm_ch[47], perm_ch[55],\n perm_ch[30], perm_ch[40], perm_ch[51], perm_ch[45], perm_ch[33], perm_ch[48],\n perm_ch[44], perm_ch[49], perm_ch[39], perm_ch[56], perm_ch[34], perm_ch[53],\n perm_ch[46], perm_ch[42], perm_ch[50], perm_ch[36], perm_ch[29], perm_ch[32]};\n\n if(i == 1 || i == 2 || i == 9 || i == 16) begin\n if(i == 1) begin\n assign C_nx = {C0[2:(USED_KEY/2)], C0[1]};\n assign D_nx = {D0[2:(USED_KEY/2)], D0[1]};\n end else begin\n assign C_nx = {C_ff[i-1][2:(USED_KEY/2)], C_ff[i-1][1]};\n assign D_nx = {D_ff[i-1][2:(USED_KEY/2)], D_ff[i-1][1]};\n end\n end else begin\n assign C_nx = {C_ff[i-1][3:(USED_KEY/2)], C_ff[i-1][1:2]};\n assign D_nx = {D_ff[i-1][3:(USED_KEY/2)], D_ff[i-1][1:2]};\n end\n\n assign Primitive_input[1] = R_expanded[ 1:6 ] ^ round_key[ 1:6 ];\n assign Primitive_input[2] = R_expanded[ 7:12] ^ round_key[ 7:12];\n assign Primitive_input[3] = R_expanded[13:18] ^ round_key[13:18];\n assign Primitive_input[4] = R_expanded[19:24] ^ round_key[19:24];\n assign Primitive_input[5] = R_expanded[25:30] ^ round_key[25:30];\n assign Primitive_input[6] = R_expanded[31:36] ^ round_key[31:36];\n assign Primitive_input[7] = R_expanded[37:42] ^ round_key[37:42];\n assign Primitive_input[8] = R_expanded[43:48] ^ round_key[43:48];\n\n S1 uu_S1 (\n .i_data(Primitive_input [1]),\n .o_data(Primitive_output[1])\n );\n\n S2 uu_S2 (\n .i_data(Primitive_input [2]),\n .o_data(Primitive_output[2])\n );\n\n S3 uu_S3 (\n .i_data(Primitive_input [3]),\n .o_data(Primitive_output[3])\n );\n\n S4 uu_S4 (\n .i_data(Primitive_input [4]),\n .o_data(Primitive_output[4])\n );\n\n S5 uu_S5 (\n .i_data(Primitive_input [5]),\n .o_data(Primitive_output[5])\n );\n\n S6 uu_S6 (\n .i_data(Primitive_input [6]),\n .o_data(Primitive_output[6])\n );\n\n S7 uu_S7 (\n .i_data(Primitive_input [7]),\n .o_data(Primitive_output[7])\n );\n\n S8 uu_S8 (\n .i_data(Primitive_input [8]),\n .o_data(Primitive_output[8])\n );\n\n assign perm_in = {Primitive_output[1], Primitive_output[2], Primitive_output[3], Primitive_output[4],\n Primitive_output[5], Primitive_output[6], Primitive_output[7], Primitive_output[8]};\n\n assign R_nx = {perm_in[16], perm_in[ 7], perm_in[20], perm_in[21],\n perm_in[29], perm_in[12], perm_in[28], perm_in[17],\n perm_in[ 1], perm_in[15], perm_in[23], perm_in[26],\n perm_in[ 5], perm_in[18], perm_in[31], perm_in[10],\n perm_in[ 2], perm_in[ 8], perm_in[24], perm_in[14],\n perm_in[32], perm_in[27], perm_in[ 3], perm_in[ 9],\n perm_in[19], perm_in[13], perm_in[30], perm_in[ 6],\n perm_in[22], perm_in[11], perm_in[ 4], perm_in[25]};\n\n if(i == 1) begin\n assign R_expanded = {R0[32], R0[ 1], R0[ 2], R0[ 3], R0[ 4], R0[ 5],\n R0[ 4], R0[ 5], R0[ 6], R0[ 7], R0[ 8], R0[ 9],\n R0[ 8], R0[ 9], R0[10], R0[11], R0[12], R0[13],\n R0[12], R0[13], R0[14], R0[15], R0[16], R0[17],\n R0[16], R0[17], R0[18], R0[19], R0[20], R0[21],\n R0[20], R0[21], R0[22], R0[23], R0[24], R0[25],\n R0[24], R0[25], R0[26], R0[27], R0[28], R0[29],\n R0[28], R0[29], R0[30], R0[31], R0[32], R0[ 1]};\n\n always_ff @ (posedge clk or negedge rst_async_n) begin\n if(!rst_async_n) begin\n L_ff[i] <= 0;\n R_ff[i] <= 0;\n C_ff[i] <= 0;\n D_ff[i] <= 0;\n end else begin\n if(i_valid) begin\n L_ff[i] <= R0;\n R_ff[i] <= R_nx ^ L0;\n C_ff[i] <= C_nx;\n D_ff[i] <= D_nx;\n end\n end\n end\n end else begin\n assign R_expanded = {R_ff[i-1][32], R_ff[i-1][ 1], R_ff[i-1][ 2], R_ff[i-1][ 3], R_ff[i-1][ 4], R_ff[i-1][ 5],\n R_ff[i-1][ 4], R_ff[i-1][ 5], R_ff[i-1][ 6], R_ff[i-1][ 7], R_ff[i-1][ 8], R_ff[i-1][ 9],\n R_ff[i-1][ 8], R_ff[i-1][ 9], R_ff[i-1][10], R_ff[i-1][11], R_ff[i-1][12], R_ff[i-1][13],\n R_ff[i-1][12], R_ff[i-1][13], R_ff[i-1][14], R_ff[i-1][15], R_ff[i-1][16], R_ff[i-1][17],\n R_ff[i-1][16], R_ff[i-1][17], R_ff[i-1][18], R_ff[i-1][19], R_ff[i-1][20], R_ff[i-1][21],\n R_ff[i-1][20], R_ff[i-1][21], R_ff[i-1][22], R_ff[i-1][23], R_ff[i-1][24], R_ff[i-1][25],\n R_ff[i-1][24], R_ff[i-1][25], R_ff[i-1][26], R_ff[i-1][27], R_ff[i-1][28], R_ff[i-1][29],\n R_ff[i-1][28], R_ff[i-1][29], R_ff[i-1][30], R_ff[i-1][31], R_ff[i-1][32], R_ff[i-1][ 1]};\n\n always_ff @ (posedge clk or negedge rst_async_n) begin\n if(!rst_async_n) begin\n L_ff[i] <= 0;\n R_ff[i] <= 0;\n C_ff[i] <= 0;\n D_ff[i] <= 0;\n end else begin\n L_ff[i] <= R_ff[i-1];\n R_ff[i] <= R_nx ^ L_ff[i-1];\n C_ff[i] <= C_nx;\n D_ff[i] <= D_nx;\n end\n end\n end\n end\nendgenerate\n\nassign last_perm = {R_ff[ROUNDS], L_ff[ROUNDS]};\n\nassign o_data = {last_perm[40], last_perm[8], last_perm[48], last_perm[16], last_perm[56], last_perm[24], last_perm[64], last_perm[32],\n last_perm[39], last_perm[7], last_perm[47], last_perm[15], last_perm[55], last_perm[23], last_perm[63], last_perm[31],\n last_perm[38], last_perm[6], last_perm[46], last_perm[14], last_perm[54], last_perm[22], last_perm[62], last_perm[30],\n last_perm[37], last_perm[5], last_perm[45], last_perm[13], last_perm[53], last_perm[21], last_perm[61], last_perm[29],\n last_perm[36], last_perm[4], last_perm[44], last_perm[12], last_perm[52], last_perm[20], last_perm[60], last_perm[28],\n last_perm[35], last_perm[3], last_perm[43], last_perm[11], last_perm[51], last_perm[19], last_perm[59], last_perm[27],\n last_perm[34], last_perm[2], last_perm[42], last_perm[10], last_perm[50], last_perm[18], last_perm[58], last_perm[26],\n last_perm[33], last_perm[1], last_perm[41], last_perm[ 9], last_perm[49], last_perm[17], last_perm[57], last_perm[25]};\n\nendmodule : des_enc", + "verif/tb_des_dec.sv": null, + "docs/Encryption.md": null, + "rtl/des_dec.sv": "module des_dec #(\n parameter NBW_DATA = 'd64,\n parameter NBW_KEY = 'd64\n) (\n input logic clk,\n input logic rst_async_n,\n input logic i_valid,\n input logic [1:NBW_DATA] i_data,\n input logic [1:NBW_KEY] i_key,\n output logic o_valid,\n output logic [1:NBW_DATA] o_data\n);\n\nlocalparam ROUNDS = 'd16;\nlocalparam EXPANDED_BLOCK = 'd48;\nlocalparam USED_KEY = 'd56;\n\nlogic [1:(NBW_DATA/2)] L16;\nlogic [1:(NBW_DATA/2)] R16;\nlogic [1:(NBW_DATA/2)] L_ff [0:ROUNDS-1];\nlogic [1:(NBW_DATA/2)] R_ff [0:ROUNDS-1];\nlogic [1:(USED_KEY/2)] C16;\nlogic [1:(USED_KEY/2)] D16;\nlogic [1:(USED_KEY/2)] C_ff [0:ROUNDS-1];\nlogic [1:(USED_KEY/2)] D_ff [0:ROUNDS-1];\nlogic [1:NBW_DATA] last_perm;\nlogic [ROUNDS-1:0] valid_ff;\n\nalways_ff @ (posedge clk or negedge rst_async_n) begin\n if(!rst_async_n) begin\n valid_ff <= 0;\n end else begin\n valid_ff <= {valid_ff[ROUNDS-2:0], i_valid};\n end\nend\n\nassign o_valid = valid_ff[ROUNDS-1];\n\nassign R16 = {i_data[58], i_data[50], i_data[42], i_data[34], i_data[26], i_data[18], i_data[10], i_data[2],\n i_data[60], i_data[52], i_data[44], i_data[36], i_data[28], i_data[20], i_data[12], i_data[4],\n i_data[62], i_data[54], i_data[46], i_data[38], i_data[30], i_data[22], i_data[14], i_data[6],\n i_data[64], i_data[56], i_data[48], i_data[40], i_data[32], i_data[24], i_data[16], i_data[8]};\n\nassign L16 = {i_data[57], i_data[49], i_data[41], i_data[33], i_data[25], i_data[17], i_data[ 9], i_data[1],\n i_data[59], i_data[51], i_data[43], i_data[35], i_data[27], i_data[19], i_data[11], i_data[3],\n i_data[61], i_data[53], i_data[45], i_data[37], i_data[29], i_data[21], i_data[13], i_data[5],\n i_data[63], i_data[55], i_data[47], i_data[39], i_data[31], i_data[23], i_data[15], i_data[7]};\n\nassign C16 = {i_key[57], i_key[49], i_key[41], i_key[33], i_key[25], i_key[17], i_key[ 9],\n i_key[ 1], i_key[58], i_key[50], i_key[42], i_key[34], i_key[26], i_key[18],\n i_key[10], i_key[ 2], i_key[59], i_key[51], i_key[43], i_key[35], i_key[27],\n i_key[19], i_key[11], i_key[ 3], i_key[60], i_key[52], i_key[44], i_key[36]};\n\nassign D16 = {i_key[63], i_key[55], i_key[47], i_key[39], i_key[31], i_key[23], i_key[15],\n i_key[ 7], i_key[62], i_key[54], i_key[46], i_key[38], i_key[30], i_key[22],\n i_key[14], i_key[ 6], i_key[61], i_key[53], i_key[45], i_key[37], i_key[29],\n i_key[21], i_key[13], i_key[ 5], i_key[28], i_key[20], i_key[12], i_key[ 4]};\n\ngenerate\n for (genvar i = ROUNDS-1; i >= 0; i--) begin : rounds\n logic [1:EXPANDED_BLOCK] round_key;\n logic [1:(USED_KEY/2)] C_nx;\n logic [1:(USED_KEY/2)] D_nx;\n logic [1:USED_KEY] perm_ch;\n logic [1:(NBW_DATA/2)] L_nx;\n logic [1:EXPANDED_BLOCK] L_expanded;\n logic [1:6] Primitive_input [1:8];\n logic [1:4] Primitive_output [1:8];\n logic [1:(NBW_DATA/2)] perm_in;\n\n if(i == 15) begin\n assign perm_ch = {C16, D16};\n end else begin\n assign perm_ch = {C_ff[i+1], D_ff[i+1]};\n end\n assign round_key = {perm_ch[14], perm_ch[17], perm_ch[11], perm_ch[24], perm_ch[ 1], perm_ch[ 5],\n perm_ch[ 3], perm_ch[28], perm_ch[15], perm_ch[ 6], perm_ch[21], perm_ch[10],\n perm_ch[23], perm_ch[19], perm_ch[12], perm_ch[ 4], perm_ch[26], perm_ch[ 8],\n perm_ch[16], perm_ch[ 7], perm_ch[27], perm_ch[20], perm_ch[13], perm_ch[ 2],\n perm_ch[41], perm_ch[52], perm_ch[31], perm_ch[37], perm_ch[47], perm_ch[55],\n perm_ch[30], perm_ch[40], perm_ch[51], perm_ch[45], perm_ch[33], perm_ch[48],\n perm_ch[44], perm_ch[49], perm_ch[39], perm_ch[56], perm_ch[34], perm_ch[53],\n perm_ch[46], perm_ch[42], perm_ch[50], perm_ch[36], perm_ch[29], perm_ch[32]};\n\n if(i == 0 || i == 1 || i == 8 || i == 15) begin\n if(i == 15) begin\n assign C_nx = {C16[(USED_KEY/2)], C16[1:(USED_KEY/2)-1]};\n assign D_nx = {D16[(USED_KEY/2)], D16[1:(USED_KEY/2)-1]};\n end else begin\n assign C_nx = {C_ff[i+1][(USED_KEY/2)], C_ff[i+1][1:(USED_KEY/2)-1]};\n assign D_nx = {D_ff[i+1][(USED_KEY/2)], D_ff[i+1][1:(USED_KEY/2)-1]};\n end\n end else begin\n assign C_nx = {C_ff[i+1][(USED_KEY/2)-1+:2], C_ff[i+1][1:(USED_KEY/2)-2]};\n assign D_nx = {D_ff[i+1][(USED_KEY/2)-1+:2], D_ff[i+1][1:(USED_KEY/2)-2]};\n end\n\n assign Primitive_input[1] = L_expanded[ 1:6 ] ^ round_key[ 1:6 ];\n assign Primitive_input[2] = L_expanded[ 7:12] ^ round_key[ 7:12];\n assign Primitive_input[3] = L_expanded[13:18] ^ round_key[13:18];\n assign Primitive_input[4] = L_expanded[19:24] ^ round_key[19:24];\n assign Primitive_input[5] = L_expanded[25:30] ^ round_key[25:30];\n assign Primitive_input[6] = L_expanded[31:36] ^ round_key[31:36];\n assign Primitive_input[7] = L_expanded[37:42] ^ round_key[37:42];\n assign Primitive_input[8] = L_expanded[43:48] ^ round_key[43:48];\n\n S1 uu_S1 (\n .i_data(Primitive_input [1]),\n .o_data(Primitive_output[1])\n );\n\n S2 uu_S2 (\n .i_data(Primitive_input [2]),\n .o_data(Primitive_output[2])\n );\n\n S3 uu_S3 (\n .i_data(Primitive_input [3]),\n .o_data(Primitive_output[3])\n );\n\n S4 uu_S4 (\n .i_data(Primitive_input [4]),\n .o_data(Primitive_output[4])\n );\n\n S5 uu_S5 (\n .i_data(Primitive_input [5]),\n .o_data(Primitive_output[5])\n );\n\n S6 uu_S6 (\n .i_data(Primitive_input [6]),\n .o_data(Primitive_output[6])\n );\n\n S7 uu_S7 (\n .i_data(Primitive_input [7]),\n .o_data(Primitive_output[7])\n );\n\n S8 uu_S8 (\n .i_data(Primitive_input [8]),\n .o_data(Primitive_output[8])\n );\n\n assign perm_in = {Primitive_output[1], Primitive_output[2], Primitive_output[3], Primitive_output[4],\n Primitive_output[5], Primitive_output[6], Primitive_output[7], Primitive_output[8]};\n\n assign L_nx = {perm_in[16], perm_in[ 7], perm_in[20], perm_in[21],\n perm_in[29], perm_in[12], perm_in[28], perm_in[17],\n perm_in[ 1], perm_in[15], perm_in[23], perm_in[26],\n perm_in[ 5], perm_in[18], perm_in[31], perm_in[10],\n perm_in[ 2], perm_in[ 8], perm_in[24], perm_in[14],\n perm_in[32], perm_in[27], perm_in[ 3], perm_in[ 9],\n perm_in[19], perm_in[13], perm_in[30], perm_in[ 6],\n perm_in[22], perm_in[11], perm_in[ 4], perm_in[25]};\n\n if(i == 15) begin\n assign L_expanded = {L16[32], L16[ 1], L16[ 2], L16[ 3], L16[ 4], L16[ 5],\n L16[ 4], L16[ 5], L16[ 6], L16[ 7], L16[ 8], L16[ 9],\n L16[ 8], L16[ 9], L16[10], L16[11], L16[12], L16[13],\n L16[12], L16[13], L16[14], L16[15], L16[16], L16[17],\n L16[16], L16[17], L16[18], L16[19], L16[20], L16[21],\n L16[20], L16[21], L16[22], L16[23], L16[24], L16[25],\n L16[24], L16[25], L16[26], L16[27], L16[28], L16[29],\n L16[28], L16[29], L16[30], L16[31], L16[32], L16[ 1]};\n\n always_ff @ (posedge clk or negedge rst_async_n) begin\n if(!rst_async_n) begin\n L_ff[i] <= 0;\n R_ff[i] <= 0;\n C_ff[i] <= 0;\n D_ff[i] <= 0;\n end else begin\n if(i_valid) begin\n L_ff[i] <= L_nx ^ R16;\n R_ff[i] <= L16;\n C_ff[i] <= C_nx;\n D_ff[i] <= D_nx;\n end\n end\n end\n end else begin\n assign L_expanded = {L_ff[i+1][32], L_ff[i+1][ 1], L_ff[i+1][ 2], L_ff[i+1][ 3], L_ff[i+1][ 4], L_ff[i+1][ 5],\n L_ff[i+1][ 4], L_ff[i+1][ 5], L_ff[i+1][ 6], L_ff[i+1][ 7], L_ff[i+1][ 8], L_ff[i+1][ 9],\n L_ff[i+1][ 8], L_ff[i+1][ 9], L_ff[i+1][10], L_ff[i+1][11], L_ff[i+1][12], L_ff[i+1][13],\n L_ff[i+1][12], L_ff[i+1][13], L_ff[i+1][14], L_ff[i+1][15], L_ff[i+1][16], L_ff[i+1][17],\n L_ff[i+1][16], L_ff[i+1][17], L_ff[i+1][18], L_ff[i+1][19], L_ff[i+1][20], L_ff[i+1][21],\n L_ff[i+1][20], L_ff[i+1][21], L_ff[i+1][22], L_ff[i+1][23], L_ff[i+1][24], L_ff[i+1][25],\n L_ff[i+1][24], L_ff[i+1][25], L_ff[i+1][26], L_ff[i+1][27], L_ff[i+1][28], L_ff[i+1][29],\n L_ff[i+1][28], L_ff[i+1][29], L_ff[i+1][30], L_ff[i+1][31], L_ff[i+1][32], L_ff[i+1][ 1]};\n\n always_ff @ (posedge clk or negedge rst_async_n) begin\n if(!rst_async_n) begin\n L_ff[i] <= 0;\n R_ff[i] <= 0;\n C_ff[i] <= 0;\n D_ff[i] <= 0;\n end else begin\n L_ff[i] <= L_nx ^ R_ff[i+1];\n R_ff[i] <= L_ff[i+1];\n C_ff[i] <= C_nx;\n D_ff[i] <= D_nx;\n end\n end\n end\n end\nendgenerate\n\nassign last_perm = {L_ff[0], R_ff[0]};\n\nassign o_data = {last_perm[40], last_perm[8], last_perm[48], last_perm[16], last_perm[56], last_perm[24], last_perm[64], last_perm[32],\n last_perm[39], last_perm[7], last_perm[47], last_perm[15], last_perm[55], last_perm[23], last_perm[63], last_perm[31],\n last_perm[38], last_perm[6], last_perm[46], last_perm[14], last_perm[54], last_perm[22], last_perm[62], last_perm[30],\n last_perm[37], last_perm[5], last_perm[45], last_perm[13], last_perm[53], last_perm[21], last_perm[61], last_perm[29],\n last_perm[36], last_perm[4], last_perm[44], last_perm[12], last_perm[52], last_perm[20], last_perm[60], last_perm[28],\n last_perm[35], last_perm[3], last_perm[43], last_perm[11], last_perm[51], last_perm[19], last_perm[59], last_perm[27],\n last_perm[34], last_perm[2], last_perm[42], last_perm[10], last_perm[50], last_perm[18], last_perm[58], last_perm[26],\n last_perm[33], last_perm[1], last_perm[41], last_perm[ 9], last_perm[49], last_perm[17], last_perm[57], last_perm[25]};\n\nendmodule : des_dec", + "verif/tb_3des_enc.sv": "module tb;\n\nparameter NBW_DATA = 'd64;\nparameter NBW_KEY = 'd192;\n\nlogic clk;\nlogic rst_async_n;\nlogic i_valid;\nlogic [1:NBW_DATA] i_data;\nlogic [1:NBW_KEY ] i_key;\nlogic o_valid;\nlogic [1:NBW_DATA] o_data;\n\ndes3_enc #(\n .NBW_DATA(NBW_DATA),\n .NBW_KEY (NBW_KEY )\n) uu_des3_enc (\n .clk (clk ),\n .rst_async_n(rst_async_n),\n .i_valid (i_valid ),\n .i_data (i_data ),\n .i_key (i_key ),\n .o_valid (o_valid ),\n .o_data (o_data )\n);\n\ninitial begin\n $dumpfile(\"test.vcd\");\n $dumpvars(0,tb);\nend\n\nalways #5 clk = ~clk;\n\ntask Single_test(logic [1:NBW_KEY] key, logic [1:NBW_DATA] data, logic [1:NBW_DATA] expected);\n i_key = key;\n i_data = data;\n i_valid = 1;\n\n @(negedge clk);\n i_valid = 0;\n\n @(posedge o_valid);\n @(negedge clk);\n if(o_data != expected) begin\n $display(\"FAIL!\");\n $display(\"Expected %h, got %h\", expected, o_data);\n end else begin\n $display(\"PASS!\");\n end\nendtask\n\ntask Burst_test();\n i_key = 192'hB1FECAFEBEBAB1FEABCDABCDABCDABCD8765432187654321;\n i_data = 64'h4321432143214321;\n i_valid = 1;\n\n @(negedge clk);\n i_data = 64'h123456789ABCDEF0;\n\n @(negedge clk);\n i_data = 64'h1234123412341234;\n i_key = 192'hABCDABCDABCDABCD8765432187654321B1FECAFEBEBAB1FE;\n\n @(negedge clk);\n i_valid = 0;\n\n @(posedge o_valid);\n @(negedge clk);\n if(o_data != 64'h2749c9efcaed543a) begin\n $display(\"FAIL!\");\n $display(\"Expected %h, got %h\", 64'h2749c9efcaed543a, o_data);\n end else begin\n $display(\"PASS!\");\n end\n\n @(negedge clk);\n if(o_valid != 1) begin\n $display(\"FAIL! o_valid should be asserted here.\");\n end\n if(o_data != 64'h984d23ecef8df5fd) begin\n $display(\"FAIL!\");\n $display(\"Expected %h, got %h\", 64'h984d23ecef8df5fd, o_data);\n end else begin\n $display(\"PASS!\");\n end\n\n @(negedge clk);\n if(o_valid != 1) begin\n $display(\"FAIL! o_valid should be asserted here.\");\n end\n if(o_data != 64'h972161012599c927) begin\n $display(\"FAIL!\");\n $display(\"Expected %h, got %h\", 64'h972161012599c927, o_data);\n end else begin\n $display(\"PASS!\");\n end\n \nendtask\n\ninitial begin\n clk = 0;\n i_valid = 0;\n rst_async_n = 1;\n #1;\n rst_async_n = 0;\n #2;\n rst_async_n = 1;\n @(negedge clk);\n\n $display(\"\\nSingle Tests\");\n Single_test(192'h0123456789abcdeffedcba9876543210abcdef9876543210, 64'h0123456789ABCDEF, 64'ha4688b153da3f95b);\n Single_test(192'h0123456789abcdeffedcba9876543210abcdef9876543210, 64'hFEDCBA9876543210, 64'h7b9325d305515107);\n Single_test(192'hBEBACAFE12345678B1FECAFE876543219898898974744747, 64'hFEDCBA9876543210, 64'h71f4eedd55b0f964);\n Single_test(192'hBEBACAFE12345678B1FECAFE876543219898898974744747, 64'hB1FECAFEBEBAB1FE, 64'h2038ea8568d3f771);\n\n $display(\"\\nBurst Test\");\n Burst_test();\n\n @(negedge clk);\n @(negedge clk);\n\n $finish();\nend\n\nendmodule", + "verif/tb_3des_dec.sv": null, + "docs/min_hamming_distance_finder_spec.md": null, + "rtl/Bit_Difference_Counter.sv": null, + "rtl/Bitwise_Reduction.sv": null, + "rtl/Data_Reduction.sv": null, + "verif/tb_Min_Hamming_Distance_Finder.sv": null, + "docs/specs.md": null, + "rtl/arithmetic_progression_generator.sv": null, + "docs/algorithms.md": null, + "docs/coeff_update_spec.md": null, + "docs/equalizer_spec.md": null, + "docs/error_calc_spec.md": null, + "rtl/coeff_update.sv": null, + "rtl/dynamic_equalizer.sv": null, + "rtl/error_calc.sv": null, + "docs/awgn_spec.md": null, + "docs/equalizer_top_spec.md": null, + "rtl/elevator_control_system.sv": null, + "docs/tx_specification.md": null, + "rtl/ethernet_fifo_cdc.sv": null, + "docs/tx_mac_specification.md": null, + "verif/event_scheduler_tb.sv": null, + "docs/modified_specs.md": null, + "rtl/event_scheduler.sv": null, + "verif/tb_event_scheduler.sv": null, + "rtl/column_selector.sv": null, + "rtl/event_storage.sv": null, + "verif/tb.sv": null, + "rtl/fixed_priority_arbiter.sv": null, + "verif/fixed_priority_arbiter_tb.sv": null, + "docs/Modified_specification.md": null, + "docs/GCD_specification.md": null, + "docs/crypto_accelerator_specification.md": null, + "docs/modular_exponentiation_specification.md": null, + "docs/modular_multiplier_specification.md": null, + "rtl/gcd_controlpath_3.sv": null, + "rtl/gcd_controlpath_4.sv": null, + "rtl/gcd_datapath_5.sv": null, + "rtl/gcd_datapath_6.sv": null, + "rtl/gcd_top_1.sv": null, + "rtl/gcd_top_2.sv": null, + "rtl/modular_exponentiation.sv": null, + "rtl/modular_multiplier.sv": null, + "rtl/lfsr_8bit.sv": null, + "verif/lfsr_8bit_tb.sv": null, + "rtl/bit16_lfsr.sv": null, + "rtl/low_power_ctrl.sv": null, + "rtl/sync_fifo.sv": null, + "verif/tb_low_power_channel.sv": null, + "rtl/cross_domain_sync.sv": null, + "rtl/dsp_input_stage.sv": null, + "rtl/dsp_output_stage.sv": null, + "rtl/lfsr_generator.sv": null, + "rtl/monte_carlo_dsp_monitor_top.sv": null, + "verif/monte_carlo_dsp_monitor_top_tb.sv": null, + "docs/multiplexer_specification.md": null, + "verif/multiplexer_tb.sv": null, + "docs/nbit_swizzling_spec.md": null, + "verif/nbit_swizzling_tb.sv": null, + "docs/nmea_decoder_spec.md": null, + "rtl/nmea_decoder.sv": null, + "verif/nmea_decoder_tb.sv": null, + "docs/fifo.md": null, + "rtl/fifo_memory.sv": null, + "rtl/read_to_write_pointer_sync.sv": null, + "rtl/rptr_empty.sv": null, + "rtl/wptr_full.sv": null, + "rtl/write_to_read_pointer_sync.sv": null, + "docs/spec.md": null, + "verif/async_filo_tb.sv": null, + "docs/axilite_to_pcie_config_module.md": null, + "rtl/axi4lite_to_pcie_cfg_bridge.sv": null, + "rtl/axis_broadcast.sv": null, + "verif/tb_axis_broadcast.sv": null, + "docs/axis_to_uart_tx_specs.md": null, + "docs/uart_rx_to_axis_specs.md": null, + "rtl/barrel_shifter.sv": null, + "verif/barrel_shifter_tb.sv": null, + "rtl/bcd_adder.sv": null, + "rtl/full_adder.sv": null, + "rtl/four_bit_adder.sv": null, + "rtl/search_binary_search_tree.sv": null, + "rtl/delete_node_binary_search_tree.sv": null, + "docs/bst_operations.md": null, + "rtl/binary_search_tree_sort_construct.sv": null, + "docs/Spec.md": null, + "verif/tb_binary_to_gray.sv": null, + "verif/tb_custom_byte_enable_ram.sv": null, + "verif/cache_controller_tb.sv": null, + "rtl/caesar_cipher.sv": null, + "verif/caesar_cipher_tb.sv": null, + "verif/tb_pseudoRandGenerator_ca.sv": null, + "docs/continuous_adder_specification.md": null, + "verif/continuous_adder_tb.sv": null, + "rtl/fifo_buffer.sv": null, + "verif/tb_fifo_buffer.sv": null, + "docs/direct_map_cache_spec.md": null, + "verif/tb_direct_map_cache.sv": null, + "rtl/direct_map_cache.sv": null, + "rtl/dual_port_memory.sv": null, + "rtl/gen_cos_sin_lut.sv": null, + "rtl/phase_lut.sv": null, + "rtl/phase_rotation.sv": null, + "rtl/power4.sv": null, + "rtl/saturation.sv": null, + "rtl/top_phase_rotation.sv": null, + "docs/spec_viterbi.md": null, + "docs/spec_slicer_top.md": null, + "docs/spec_top_phase_rotation.md": null, + "rtl/slicer.sv": null, + "rtl/slicer_top.sv": null, + "docs/swizzler_specification.md": null, + "verif/swizzler_tb.sv": null, + "rtl/swizzler.sv": null, + "docs/sync_serial_communication_tx_rx_spec.md": null, + "verif/sync_serial_communication_tb.sv": null, + "rtl/weight_stationary_pe.sv": null, + "verif/systolic_array_tb.sv": null, + "rtl/thermostat.v": null, + "docs/Traffic_controller.md": null, + "rtl/traffic_light_controller.sv": null, + "docs/Universal_Shift_Register_spec.md": null, + "verif/tb_universal_shift_register.sv": null, + "rtl/universal_shift_register.sv": null, + "docs/spec_conj.md": null, + "docs/spec_cross_correlation.md": null, + "docs/spec_detect_sequence.md": null, + "rtl/adder_2d_layers.sv": null, + "rtl/adder_tree_2d.sv": null, + "rtl/correlate.sv": null, + "rtl/cross_correlation.sv": null, + "docs/valid_modes.md": null, + "docs/words_counting.md": null, + "rtl/detect_sequence.sv": null, + "docs/proc_fsm_spec.md": null, + "docs/adder_tree.md": null, + "docs/coeff_ram.md": null, + "docs/poly_decimator.md": null, + "docs/poly_filter.md": null, + "docs/shift_register.md": null, + "rtl/adder_tree.sv": null, + "rtl/coeff_ram.sv": null, + "rtl/poly_filter.sv": null, + "rtl/shift_register.sv": null, + "docs/prbs_specification.md": null, + "rtl/prbs_gen_check.sv": null, + "rtl/fsm.sv": null, + "verif/fsm_tb.sv": null, + "rtl/CA_1.sv": null, + "rtl/CA_2.sv": null, + "rtl/CA_3.sv": null, + "rtl/CA_4.sv": null, + "rtl/rgb_color_space_conversion.sv": null, + "rtl/APBGlobalHistoryRegister.v": null, + "docs/signed_comparator_specification.md": null, + "verif/signed_comparator_tb.sv": null, + "rtl/sorting_engine.sv": null, + "rtl/brick_sort.sv": null, + "rtl/bubble_sort.sv": null, + "rtl/merge_sort.sv": null, + "rtl/selection_sort.sv": null + } + }, + { + "id": "cvdp_agentic_PCIe_endpoint_0001", + "index": 500, + "source_config": "cvdp_agentic_code_generation_no_commercial", + "instruction": "Context: You are a language model that has the following file operations available at your disposal:\n - **List files in a directory** by running one of the following commands: \n - `ls`\n - `tree`\n - **Read files** by using:\n - `cat `\n - **Write files** by using:\n - `echo > `\n - **Compile Verilog** by using `iverilog` such as:\n - `iverilog -o .out -g2012 `\n - **Run Simulation** by using:\n - `vvp .out`\n - **Find current working directory** by using:\n - `pwd`\n \nYou will be given a prompt and your task is to understand it and solve the given issue by using the above mentioned commands as needed. At the final step you should create a linux patch to highlight the necessary file updates to achieve the targeted goal.\n\n You will solve the problem step by step using the following approach of \n - thought (thinking process of the step you're going to take)\n - action (the command you will be running to get more details/context that's helpful to solve the problem)\n - observation (the output from the action you will observe based on which you will take your next step)\n\n The last step will be the final output summary and the patch itelf in the following format \n - thought (the summary of what you did and some introduction of the patch file itself)\n - patch (a linux based patch that needs to be applied to reach to the relevant solution)\n\n The patch file should only be applied to a single file to reach to the required solution.\n\nTask: `pcie_endpoint` module in System Verilog which is responsible for handling `PCIe transactions`, interfacing with a `DMA engine`, and managing `MSI-X interrupts`. It processes `PCIe Transaction Layer Packets` (TLPs), decodes them, and executes the corresponding read/operations. This module follows a `Finite State Machine` (FSM) approach to ensure proper sequencing of PCIe endpoint nd read transactions. The is parameterizable, allowing flexibility in configuring data width and address width. Please refer to the specification provided in `docs/specs.md` for detailed description.\n\n## **Parameterization**\n- **Address Width (`ADDR_WIDTH`)**: Default **64 bits**, configurable for different PCIe address sizes.\n- **Data Width (`DATA_WIDTH`)**: Default **128 bits**, supporting high-speed PCIe transfers.\n\n## **1. Features**\n### **PCIe Transaction Handling**\n- Receives PCIe TLPs and processes valid transactions.\n- Decodes received TLPs and forwards them for execution.\n- Transmits processed transactions.\n\n### **DMA Engine Interface**\n- Supports DMA requests and generates corresponding complete requests.\n- Provides `dma_address` and `dma_data` signals to interact with external memory controllers.\n\n### **MSI-X Interrupt Management**\n- Generates MSI-X interrupts upon DMA completion.\n- Ensures proper sequencing of interrupt generation to prevent missed events.\n\n## **2. Functional Description**\nThe `pcie_endpoint` module consists of multiple FSMs, each handling a distinct function:\n\n### **PCIe Transaction FSM**\n- Manages the reception and processing of incoming PCIe TLPs.\n- Decodes received transactions and prepares them for further execution.\n\n### **PCIe Data Link FSM**\n- Handles transmission of PCIe transactions.\n- Ensures data integrity and proper sequencing of outgoing TLPs.\n\n### **DMA FSM**\n- Manages the interaction with the DMA engine.\n- Tracks DMA requests and ensures completion of memory operations.\n\n### **MSI-X FSM**\n- Generates MSI-X interrupts upon successful completion of DMA operations.\n- Ensures correct signaling of interrupts to the host system.\n\n## **3. Transaction Flow**\n### **PCIe Transaction**\n1. Receives a PCIe TLP.\n2. Decodes and processes the transaction.\n3. Stores the data in the appropriate memory location.\n\n### **PCIe Read Transaction**\n1. Receives a read request from PCIe.\n2. Fetches the required data from memory.\n3. Sends the data as a PCIe response.\n\n### **DMA Transaction**\n1. Receives a DMA request.\n2. Reads or writes data from/to memory.\n3. Signals DMA completion.\n\n### **MSI-X Interrupt Generation**\n1. Detects completion of DMA operations.\n2. Generates an MSI-X interrupt signal.\n3. Waits for acknowledgment before resetting the interrupt state.\n\n## **4. SystemVerilog Best Practices**\n- **Modular Design:** FSMs are independently implemented for different functions, ensuring better maintainability.\n- **Parameterization:** Address and data width are configurable to accommodate various PCIe configurations.\n- **Clock Domain Handling:** All FSMs operate under a single `clk` domain to maintain synchronization.\n- **Reset Handling:** The `rst_n` signal ensures proper initialization of all FSMs and state registers.\n\nThe code follows best practices in SystemVerilog, ensuring readability, reusability, and maintainability. Proper comments and documentation are included to explain the functionality of each major block.", + "verilog_code": { + "code_block_1_4": "PCIe Transaction Layer Packets" + }, + "test_info": {}, + "expected_behavior": [], + "metadata": { + "categories": [ + "cid003", + "medium" + ], + "domain": "control", + "complexity": "expert", + "problem_type": "design", + "has_code": true, + "has_tests": false + }, + "full_prompt": "Design a `pcie_endpoint` module in System Verilog which is responsible for handling `PCIe transactions`, interfacing with a `DMA engine`, and managing `MSI-X interrupts`. It processes `PCIe Transaction Layer Packets` (TLPs), decodes them, and executes the corresponding read/write operations. This module follows a `Finite State Machine` (FSM) approach to ensure proper sequencing of PCIe endpoint write and read transactions. The design is parameterizable, allowing flexibility in configuring data width and address width. Please refer to the specification provided in `docs/specs.md` for detailed design description.\n\n## **Parameterization**\n- **Address Width (`ADDR_WIDTH`)**: Default **64 bits**, configurable for different PCIe address sizes.\n- **Data Width (`DATA_WIDTH`)**: Default **128 bits**, supporting high-speed PCIe transfers.\n\n## **1. Features**\n### **PCIe Transaction Handling**\n- Receives PCIe TLPs and processes valid transactions.\n- Decodes received TLPs and forwards them for execution.\n- Transmits processed transactions.\n\n### **DMA Engine Interface**\n- Supports DMA requests and generates corresponding complete requests.\n- Provides `dma_address` and `dma_data` signals to interact with external memory controllers.\n\n### **MSI-X Interrupt Management**\n- Generates MSI-X interrupts upon DMA completion.\n- Ensures proper sequencing of interrupt generation to prevent missed events.\n\n## **2. Functional Description**\nThe `pcie_endpoint` module consists of multiple FSMs, each handling a distinct function:\n\n### **PCIe Transaction FSM**\n- Manages the reception and processing of incoming PCIe TLPs.\n- Decodes received transactions and prepares them for further execution.\n\n### **PCIe Data Link FSM**\n- Handles transmission of PCIe transactions.\n- Ensures data integrity and proper sequencing of outgoing TLPs.\n\n### **DMA FSM**\n- Manages the interaction with the DMA engine.\n- Tracks DMA requests and ensures completion of memory operations.\n\n### **MSI-X FSM**\n- Generates MSI-X interrupts upon successful completion of DMA operations.\n- Ensures correct signaling of interrupts to the host system.\n\n## **3. Transaction Flow**\n### **PCIe Write Transaction**\n1. Receives a PCIe TLP.\n2. Decodes and processes the transaction.\n3. Stores the data in the appropriate memory location.\n\n### **PCIe Read Transaction**\n1. Receives a read request from PCIe.\n2. Fetches the required data from memory.\n3. Sends the data as a PCIe response.\n\n### **DMA Transaction**\n1. Receives a DMA request.\n2. Reads or writes data from/to memory.\n3. Signals DMA completion.\n\n### **MSI-X Interrupt Generation**\n1. Detects completion of DMA operations.\n2. Generates an MSI-X interrupt signal.\n3. Waits for acknowledgment before resetting the interrupt state.\n\n## **4. SystemVerilog Best Practices**\n- **Modular Design:** FSMs are independently implemented for different functions, ensuring better maintainability.\n- **Parameterization:** Address and data width are configurable to accommodate various PCIe configurations.\n- **Clock Domain Handling:** All FSMs operate under a single `clk` domain to maintain synchronization.\n- **Reset Handling:** The `rst_n` signal ensures proper initialization of all FSMs and state registers.\n\nThe code follows best practices in SystemVerilog, ensuring readability, reusability, and maintainability. Proper comments and documentation are included to explain the functionality of each major block.\n", + "system_message": " You are a language model that has the following file operations available at your disposal:\n - **List files in a directory** by running one of the following commands: \n - `ls`\n - `tree`\n - **Read files** by using:\n - `cat `\n - **Write files** by using:\n - `echo > `\n - **Compile Verilog** by using `iverilog` such as:\n - `iverilog -o .out -g2012 `\n - **Run Simulation** by using:\n - `vvp .out`\n - **Find current working directory** by using:\n - `pwd`\n \nYou will be given a prompt and your task is to understand it and solve the given issue by using the above mentioned commands as needed. At the final step you should create a linux patch to highlight the necessary file updates to achieve the targeted goal.\n\n You will solve the problem step by step using the following approach of \n - thought (thinking process of the step you're going to take)\n - action (the command you will be running to get more details/context that's helpful to solve the problem)\n - observation (the output from the action you will observe based on which you will take your next step)\n\n The last step will be the final output summary and the patch itelf in the following format \n - thought (the summary of what you did and some introduction of the patch file itself)\n - patch (a linux based patch that needs to be applied to reach to the relevant solution)\n\n The patch file should only be applied to a single file to reach to the required solution.", + "raw_context": { + "docs/specification.md": null, + "rtl/decoder_data_control_64b66b.sv": null, + "rtl/encoder_control_64b66b.sv": null, + "rtl/encoder_data_64b66b.sv": null, + "rtl/aes128_encrypt.sv": null, + "verif/tb_aes128_enc.sv": null, + "rtl/aes128_decrypt.sv": null, + "rtl/aes128_key_expansion.sv": null, + "rtl/inv_sbox.sv": null, + "rtl/sbox.sv": null, + "verif/tb_aes128_dec.sv": null, + "rtl/aes_encrypt.sv": null, + "verif/tb_aes_encrypt.sv": null, + "rtl/aes_decrypt.sv": null, + "rtl/aes_ke.sv": null, + "verif/tb_aes_decrypt.sv": null, + "rtl/aes_dec_top.sv": null, + "rtl/aes_enc_top.sv": null, + "verif/tb_padding_top.sv": null, + "verif/tb_des_enc.sv": null, + "docs/Key_schedule.md": null, + "docs/Permutations.md": null, + "docs/S_box_creation.md": null, + "rtl/S1.sv": null, + "rtl/S2.sv": null, + "rtl/S3.sv": null, + "rtl/S4.sv": null, + "rtl/S5.sv": null, + "rtl/S6.sv": null, + "rtl/S7.sv": null, + "rtl/S8.sv": null, + "rtl/des_enc.sv": null, + "verif/tb_des_dec.sv": null, + "docs/Encryption.md": null, + "rtl/des_dec.sv": null, + "verif/tb_3des_enc.sv": null, + "verif/tb_3des_dec.sv": null, + "docs/min_hamming_distance_finder_spec.md": null, + "rtl/Bit_Difference_Counter.sv": null, + "rtl/Bitwise_Reduction.sv": null, + "rtl/Data_Reduction.sv": null, + "verif/tb_Min_Hamming_Distance_Finder.sv": null, + "docs/specs.md": "# PCIe Endpoint Module (`pcie_endpoint.sv`)\n\n## Overview\nThe `pcie_endpoint` module implements a PCIe endpoint logic block that:\n- Receives and processes PCIe Transaction Layer Packets (TLPs),\n- Initiates and monitors DMA transfers,\n- Triggers MSI-X interrupts on DMA completion.\n\nIt is architected using multiple finite state machines (FSMs) to separate concerns and ensure robust design: one FSM each for PCIe transaction management, data link layer coordination, DMA handling, and interrupt generation.\n\n---\n\n## Parameterization\n\n| Parameter | Description | Default |\n|---------------|----------------------------------------------|---------|\n| `ADDR_WIDTH` | Bit-width of the DMA address signals | 64 |\n| `DATA_WIDTH` | Bit-width of the PCIe and DMA data bus | 128 |\n\nThese parameters enable adaptation to various PCIe configurations and host systems.\n\n---\n\n## Interfaces\n\n### Clock and Reset\n| Signal | Direction | Width | Description |\n|----------|-----------|-------|----------------------------------------|\n| `clk` | Input | 1 | Clock signal for synchronous logic |\n| `rst_n` | Input | 1 | Active-low reset |\n\n### PCIe Interface\n| Signal | Direction | Width | Description |\n|------------------|-----------|---------------|-------------------------------------------------|\n| `pcie_rx_tlp` | Input | `DATA_WIDTH` | Incoming PCIe TLP data |\n| `pcie_rx_valid` | Input | 1 | Indicates `pcie_rx_tlp` contains valid data |\n| `pcie_rx_ready` | Output | 1 | Indicates endpoint is ready to receive TLP |\n| `pcie_tx_tlp` | Output | `DATA_WIDTH` | Outgoing PCIe TLP data |\n| `pcie_tx_valid` | Output | 1 | Indicates valid TLP data on `pcie_tx_tlp` |\n| `pcie_tx_ready` | Input | 1 | Indicates host is ready to accept outgoing TLP |\n\n### DMA Interface\n| Signal | Direction | Width | Description |\n|----------------|-----------|-------|---------------------------------------------|\n| `dma_request` | Input | 1 | Request to initiate a DMA transfer |\n| `dma_complete` | Output | 1 | Indicates that DMA operation is complete |\n\n### MSI-X Interrupt Interface\n| Signal | Direction | Width | Description |\n|------------------|-----------|-------|-------------------------------------------------|\n| `msix_interrupt` | Output | 1 | MSI-X interrupt generated after DMA completion |\n\n---\n\n## Internal Signals\n\n| Signal | Width | Description |\n|--------------------|--------------|-----------------------------------------------------|\n| `tlp_decoded_data` | `DATA_WIDTH` | Latched copy of received PCIe TLP |\n| `tlp_valid` | 1 | Indicates valid TLP is available for processing |\n| `dma_address` | `ADDR_WIDTH` | Address for DMA operation |\n| `dma_data` | `DATA_WIDTH` | Data for DMA write operation |\n| `dma_start` | 1 | Trigger signal to begin DMA |\n\n---\n\n## Functional Description\n\n### PCIe Transaction FSM (`pcie_transaction_fsm`)\nHandles incoming PCIe TLPs:\n- **States**: `IDLE`, `RECEIVE`, `PROCESS`, `SEND_RESPONSE`\n- When a TLP is received (`pcie_rx_valid`), the FSM transitions to `RECEIVE`, captures the data, and marks it valid.\n- In `PROCESS`, it may trigger DMA or other logic.\n- In `SEND_RESPONSE`, it transitions to data link FSM for sending a response.\n\n### PCIe Data Link FSM (`pcie_data_link_fsm`)\nManages transmission of TLPs over PCIe:\n- **States**: `DLL_IDLE`, `TRANSMIT`, `WAIT_ACK`, `RETRY`\n- When valid TLP data is ready, FSM asserts `pcie_tx_valid` and waits for `pcie_tx_ready`.\n- Retries transmission if not acknowledged.\n\n### DMA FSM (`dma_fsm`)\nPerforms memory operations via DMA engine:\n- **States**: `DMA_IDLE`, `READ_DESC`, `FETCH_DATA`, `WRITE_DMA`\n- On `dma_request`, begins reading descriptors and fetching data.\n- Once data is written to the target, it asserts `dma_complete`.\n\n### MSI-X FSM (`msix_fsm`)\nGenerates interrupts after DMA:\n- **States**: `MSIX_IDLE`, `GENERATE_INT`\n- Monitors `dma_complete`, and upon detection, asserts `msix_interrupt` for one clock cycle.\n\n---\n\n## Timing and Handshake Behavior\n\n- **`pcie_rx_ready`** is high only when the module is in `IDLE` state and ready to receive.\n- **`pcie_tx_valid`** is asserted when in `TRANSMIT` state and remains high until `pcie_tx_ready` is received.\n- **`dma_complete`** and **`msix_interrupt`** are single-cycle pulses triggered by respective FSM transitions.\n\n---\n\n## Summary\n\nThe `pcie_endpoint` is a modular and FSM-driven PCIe endpoint logic capable of:\n\n- Accepting and decoding PCIe TLPs.\n- Coordinating DMA data transfers using descriptors.\n- Sending completion or response TLPs.\n- Triggering MSI-X interrupts for host notification.\n\n### Key Features:\n- Parameterized for address and data width.\n- Separated FSMs for clean logic partitioning.\n- PCIe TLP RX/TX handshake compliant.\n- Single-cycle MSI-X interrupt signaling.\n- Scalable for integration with full PCIe/DMA systems.", + "rtl/arithmetic_progression_generator.sv": null, + "docs/algorithms.md": null, + "docs/coeff_update_spec.md": null, + "docs/equalizer_spec.md": null, + "docs/error_calc_spec.md": null, + "rtl/coeff_update.sv": null, + "rtl/dynamic_equalizer.sv": null, + "rtl/error_calc.sv": null, + "docs/awgn_spec.md": null, + "docs/equalizer_top_spec.md": null, + "rtl/elevator_control_system.sv": null, + "docs/tx_specification.md": null, + "rtl/ethernet_fifo_cdc.sv": null, + "docs/tx_mac_specification.md": null, + "verif/event_scheduler_tb.sv": null, + "docs/modified_specs.md": null, + "rtl/event_scheduler.sv": null, + "verif/tb_event_scheduler.sv": null, + "rtl/column_selector.sv": null, + "rtl/event_storage.sv": null, + "verif/tb.sv": null, + "rtl/fixed_priority_arbiter.sv": null, + "verif/fixed_priority_arbiter_tb.sv": null, + "docs/Modified_specification.md": null, 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**List files in a directory** by running one of the following commands: \n - `ls`\n - `tree`\n - **Read files** by using:\n - `cat `\n - **Write files** by using:\n - `echo > `\n - **Compile Verilog** by using `iverilog` such as:\n - `iverilog -o .out -g2012 `\n - **Run Simulation** by using:\n - `vvp .out`\n - **Update the file content** by using:\n - `sed -i '3s/old/new/' file.txt`\n - **Find current working directory** by using:\n - `pwd`\n\nYou will be given a prompt and your task is to understand it and solve the given issue by using the above-mentioned commands as needed. In the final step, you should create a Linux patch to highlight the necessary file updates to achieve the targeted goal.\n\n You will solve the problem step by step using the following approach of \n - thought (thinking process of the step you're going to take)\n - action (the command you will be running to get more details/context that's helpful to solve the problem)\n - observation (the output from the action you will observe based on which you will take your next step)\n\n The last step will be the final output summary and the patch itself in the following format \n - thought (the summary of what you did and some introduction of the patch file itself)\n - patch (a Linux-based patch that needs to be applied to reach the relevant solution)\n\n The patch file should only be applied to a single file to reach the required solution.\n\nTask: Develop a SystemVerilog-based `csr_apb_interface` that supports read and ccess to internal control, data, and interrupt registers. The module must handle APB transactions using standard protocol signals (`pselx`, `penable`, `pwrite`) and expose register data through a 32-bit bus. It should also support interrupt status flag handling, protection for specific registers, and expose the current FSM state via a debug output.\n\n## **Key Functional Requirements**\n\n### 1. APB Protocol Compliance\nThe module must support the AMBA APB protocol, managing read and operations through the standard `pselx`, `penable`, and `pwrite` signals. \nAll transactions must follow the three-phase handshake: \n**IDLE \u2192 SETUP \u2192 ACCESS**\n\n### 2. Register Map and Access\nThe controller provides access to four key registers via the APB interface:\n\n- DATA_REG (0x10):\n Holds `data1` (bits 19:10), `data2` (bits 9:0), and 12 bits of reserved data (31:20).\n\n- CONTROL_REG (0x14): \n Includes `enable`, `mode`, and 30 bits of reserved control fields.\n\n- INTERRUPT_REG (0x18): \n Stores interrupt enable bits: `overflow_ie`, `sign_ie`, `parity_ie`, and `zero_ie`, along with 28 reserved bits.\n\n- ISR_REG (0x1C): \n Holds interrupt status flags (`*_is`). These flags can be cleared by writing `1` to the corresponding enable bits in the `INTERRUPT_REG`.\n\n### 3. FSM State Management\nThe uses a finite-state machine with four states:\n\n- IDLE: \n Waits for `pselx` to be asserted.\n\n- SETUP:\n Accepts and processes transaction requests, transitions to `READ_STATE` or `WRITE_STATE`.\n\n- READ_STATE: \n Outputs register data on `prdata` based on the address. Transitions back to `IDLE`.\n\n- WRITE_STATE: \n Writes data into registers from `pwdata`, with a protection mechanism for `ISR_REG` (writes are blocked). Transitions back to `IDLE`.\n\n### 4. Protection Mechanism\nThe `ISR_REG` is write-protected. Any attempt to it should assert `pslverr`. \nWrites to `INTERRUPT_REG` can clear corresponding ISR bits by writing `1` to the enable flags.", + "verilog_code": {}, + "test_info": { + "test_criteria_2": [ + "also support interrupt status flag handling, write protection for specific registers, and expose the current fsm state via a debug output.", + "assert `pslverr`." + ] + }, + "expected_behavior": [ + "handle APB transactions using standard protocol signals (`pselx`, `penable`, `pwrite`) and expose register data through a 32-bit bus", + "also support interrupt status flag handling, write protection for specific registers, and expose the current FSM state via a debug output", + "support the AMBA APB protocol, managing read and write operations through the standard `pselx`, `penable`, and `pwrite` signals", + "follow the three-phase handshake:", + "assert `pslverr`" + ], + "metadata": { + "categories": [ + "cid003", + "medium" + ], + "domain": "control", + "complexity": "expert", + "problem_type": "design", + "has_code": false, + "has_tests": true + }, + "full_prompt": "Develop a SystemVerilog-based `csr_apb_interface` that supports read and write access to internal control, data, and interrupt registers. The module must handle APB transactions using standard protocol signals (`pselx`, `penable`, `pwrite`) and expose register data through a 32-bit bus. It should also support interrupt status flag handling, write protection for specific registers, and expose the current FSM state via a debug output.\n\n## **Key Functional Requirements**\n\n### 1. APB Protocol Compliance\nThe module must support the AMBA APB protocol, managing read and write operations through the standard `pselx`, `penable`, and `pwrite` signals. \nAll transactions must follow the three-phase handshake: \n**IDLE \u2192 SETUP \u2192 ACCESS**\n\n### 2. Register Map and Access\nThe controller provides access to four key registers via the APB interface:\n\n- DATA_REG (0x10):\n Holds `data1` (bits 19:10), `data2` (bits 9:0), and 12 bits of reserved data (31:20).\n\n- CONTROL_REG (0x14): \n Includes `enable`, `mode`, and 30 bits of reserved control fields.\n\n- INTERRUPT_REG (0x18): \n Stores interrupt enable bits: `overflow_ie`, `sign_ie`, `parity_ie`, and `zero_ie`, along with 28 reserved bits.\n\n- ISR_REG (0x1C): \n Holds interrupt status flags (`*_is`). These flags can be cleared by writing `1` to the corresponding enable bits in the `INTERRUPT_REG`.\n\n### 3. FSM State Management\nThe design uses a finite-state machine with four states:\n\n- IDLE: \n Waits for `pselx` to be asserted.\n\n- SETUP:\n Accepts and processes transaction requests, transitions to `READ_STATE` or `WRITE_STATE`.\n\n- READ_STATE: \n Outputs register data on `prdata` based on the address. Transitions back to `IDLE`.\n\n- WRITE_STATE: \n Writes data into registers from `pwdata`, with a protection mechanism for `ISR_REG` (writes are blocked). Transitions back to `IDLE`.\n\n### 4. Write Protection Mechanism\nThe `ISR_REG` is write-protected. Any attempt to write to it should assert `pslverr`. \nWrites to `INTERRUPT_REG` can clear corresponding ISR bits by writing `1` to the enable flags.\n", + "system_message": " You are a language model that has the following file operations available at your disposal:\n - **List files in a directory** by running one of the following commands: \n - `ls`\n - `tree`\n - **Read files** by using:\n - `cat `\n - **Write files** by using:\n - `echo > `\n - **Compile Verilog** by using `iverilog` such as:\n - `iverilog -o .out -g2012 `\n - **Run Simulation** by using:\n - `vvp .out`\n - **Update the file content** by using:\n - `sed -i '3s/old/new/' file.txt`\n - **Find current working directory** by using:\n - `pwd`\n\nYou will be given a prompt and your task is to understand it and solve the given issue by using the above-mentioned commands as needed. In the final step, you should create a Linux patch to highlight the necessary file updates to achieve the targeted goal.\n\n You will solve the problem step by step using the following approach of \n - thought (thinking process of the step you're going to take)\n - action (the command you will be running to get more details/context that's helpful to solve the problem)\n - observation (the output from the action you will observe based on which you will take your next step)\n\n The last step will be the final output summary and the patch itself in the following format \n - thought (the summary of what you did and some introduction of the patch file itself)\n - patch (a Linux-based patch that needs to be applied to reach the relevant solution)\n\n The patch file should only be applied to a single file to reach the required solution.", + "raw_context": { + "docs/specification.md": null, + "rtl/decoder_data_control_64b66b.sv": null, + "rtl/encoder_control_64b66b.sv": null, + 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language model that has the following file operations available at your disposal:\n - **List files in a directory** by running one of the following commands: \n - `ls`\n - `tree`\n - **Read files** by using:\n - `cat `\n - **Write files** by using:\n - `echo > `\n - **Compile Verilog** by using `iverilog` such as:\n - `iverilog -o .out -g2012 `\n - **Run Simulation** by using:\n - `vvp .out`\n - **Find current working directory** by using:\n - `pwd`\n - **Update the contents of a text file from a old content to new content**\n - `sed -i \"line_number s/old_statement/new_statement/\" file.sv`\n - **To access a specific line of the file**\n - `awk 'NR==line_number' file_name.sv`\n\nYou will be given a prompt and your task is to understand it and solve the given issue by using the above-mentioned commands as needed. In the final step, you should create a Linux patch to highlight the necessary file updates to achieve the targeted goal.\n\n You will solve the problem step by step using the following approach of \n - thought (thinking process of the step you're going to take)\n - action (the command you will be running to get more details/context that's helpful to solve the problem)\n - observation (the output from the action you will observe based on which you will take your next step)\n\n The last step will be the final output summary and the patch itself in the following format \n - thought (the summary of what you did and some introduction of the patch file itself)\n - patch (a Linux-based patch that needs to be applied to reach the relevant solution)\n\nTask: The `event_storage` module in rtl directory synchronously stores events from the input `i_event` in a register bank. Each `i_event` input has an equivalent register. If the interface signal `i_en_overflow` is asserted, the register bank may wrap around when it reaches its maximum value, and an event occurs. If not asserted, the data stored in the register bank must be saturated.\n\nThe signals `i_bypass`, `i_data`, `i_raddr` are used to set the `o_data` signal such as:\n- If `i_bypass == 1`, then `o_data = i_data`.\n- If `i_bypass == 0`, then `o_data = reg_bank[i_raddr]`.\n\n**Modify** the module `event_storage` so that it is fully parameterizable. The parameters for this block are:\n\n- `NBW_STR`: Defines the bit width of the input and output data, as well as the bit width of each register in the register bank.\n- `NS_EVT`: Defines the number of parallel events stored by the module.\n- `NBW_EVT`: Defines the bit width of the read address used to select one of the event counters in `reg_bank`.\n\n----------\n\nThe `event_array` module implements a **2D pipeline of event processors** (called `event_storage` units), structured as a grid of **NS_ROWS \u00d7 NS_COLS**. Each processor operates on a stream of input data and associated events, performing updates and passing data to the next row in the same column. **All of the top module connections are fully combinational**. A testbench for it is provided.\n\n**Create** an `event_array` module in the rtl directory, and make sure it is fully parameterizable.\n\n### Specifications\n\n- **Module Name**: `event_array`\n\n- **Parameters**:\n - `NS_ROWS`: Number of rows in the 2D processing array.\n - Default value: 4.\n - Related interface signals: `i_en_overflow`, `i_event`, `i_bypass`.\n - `NS_COLS`: Number of columns in the 2D processing array.\n - Default value: 4. Must always be $`2^{NBW\\_COL}`$\n - Related interface signals: `i_en_overflow`, `i_event`, `i_data`, `i_col_sel`.\n - `NBW_COL`: Bit width of the column selection signal.\n - Default value: 2.\n - Related interface signals: `i_col_sel`.\n - `NBW_STR`: Bit width of the data processed in each `event_storage`.\n - Default value: 8.\n - Related interface signals: `i_data`, `o_data`.\n - `NS_EVT`: Number of event bits handled by each `event_storage`.\n - Default value: 8. Must always be $`2^{NBW\\_EVT}`$\n - Related interface signals: `i_event`.\n - `NBW_EVT`: Bit width of the read address used for event selection inside each `event_storage`.\n - Default value: 3.\n - Related interface signals: `i_raddr`.\n\n### Interface Signals\n\n- **Clock** (`clk`): Synchronizes operation at the rising edge.\n- **Reset** (`rst_async_n`): Active-low asynchronous reset. Resets the internal storage elements.\n- **Column Select** (`[NBW_COL-1:0] i_col_sel`): Selects which column\u2019s output from the last row will be assigned to `o_data`.\n- **Overflow Enable** (`[NS_ROWS*NS_COLS-1:0] i_en_overflow`): One-bit flag per `event_storage`. When high, enables overflow in `event_storage`'s internal registers.\n- **Event Input** (`[(NS_ROWS*NS_COLS*NS_EVT)-1:0] i_event`): All events (flattened) to be applied across the array. Each `event_storage` receives `NS_EVT` bits.\n- **Input Data** (`[(NS_COLS*NBW_STR)-1:0] i_data`): Parallel input data for the **first row only**, one value per column.\n- **Bypass Control** (`[NS_ROWS-1:0] i_bypass`): One bit per row. When high, it bypasses the event logic in that row's `event_storage`.\n- **Read Address** (`[NBW_EVT-1:0] i_raddr`): Address input used to read specific event-mapped data from each `event_storage`.\n- **Output Data** (`[NBW_STR-1:0] o_data`): Output from the selected column in the **last row**.\n\n### Functional Description\n\nThe `event_array` module is structured as a **2D pipeline** of `event_storage` units. Each unit represents a processing cell that performs bit-based updates to its internal data register according to the received `i_event` bits and the `i_en_overflow` flag.\n\nThe array is organized as `NS_ROWS` rows and `NS_COLS` columns.\n\n#### Input Flow:\n- Input data (`i_data`) is injected only into the **first row** of the array.\n- Each subsequent row receives the processed output from the `event_storage` directly above it in the same column.\n- All `event_storage` receive a unique slice of the flattened `i_event` and `i_en_overflow` arrays:\n - In `event_array`, the `i_event` input is a flat vector that holds all event bits for every cell in the grid, with each `event_storage` requiring `NS_EVT` bits. The module slices this vector by assigning `NS_EVT` bits to each `event_storage` based on its row and column. The slicing starts from the most significant bit and moves left to right across columns, then top to bottom across rows \u2014 like reading a table row by row. This way, each cell gets exactly the bits intended for its position in the array.\n - For example, if `NS_ROWS = 2`, `NS_COLS = 2`, and `NS_EVT = 4`, then `i_event` is 16 bits wide. The cell at row 0, column 0 gets the top 4 bits `[15:12]`, row 0, column 1 gets `[11:8]`, row 1, column 0 gets `[7:4]`, and row 1, column 1 gets the lowest 4 bits `[3:0]`.\n\n - The `i_en_overflow` input is a flat bit vector with one bit per `event_storage` in the grid. The vector is sliced using a row-major order: starting from the least significant bit, it maps left to right across columns, then top to bottom across rows.\n - For example, if `NS_ROWS = 2` and `NS_COLS = 2`, then `i_en_overflow` is 4 bits wide. The cell at row 0, column 0 gets bit `[0]`, row 0, column 1 gets bit `[1]`, row 1, column 0 gets bit `[2]`, and row 1, column 1 gets bit `[3]`.\n\n\n#### Output Logic:\n- After data has propagated through all rows, each column's final output is collected:\n - A `data_col_sel` signal is constructed by collecting the output data from each column in the last row of the array. For each column, the module takes the `data_out` of the `event_storage` cell at row `NS_ROWS - 1` and column `col`. These outputs are concatenated from **left to right** in **increasing column index order**, meaning **column 0 goes into the most significant bits**, and **column `NS_COLS - 1` goes into the least significant bits**. This signal is then connected to the input of the `column_selector` module.\n - For example, if `NS_COLS = 4` and `NBW_STR = 8`, then `data_col_sel` is 32 bits wide. The output from column 0 goes into bits `[31:24]`, column 1 into `[23:16]`, column 2 into `[15:8]`, and column 3 into `[7:0]`.\n\n- The `column_selector` submodule then selects one column based on `i_col_sel` to produce the module's final output `o_data`.", + "verilog_code": { + "code_block_1_11": "o_data = reg_bank[i_raddr]", + "code_block_1_46": "[NBW_COL-1:0] i_col_sel", + "code_block_1_48": "[NS_ROWS*NS_COLS-1:0] i_en_overflow", + "code_block_1_51": "[(NS_ROWS*NS_COLS*NS_EVT)-1:0] i_event", + "code_block_1_54": "[(NS_COLS*NBW_STR)-1:0] i_data", + "code_block_1_55": "[NS_ROWS-1:0] i_bypass", + "code_block_1_57": "[NBW_EVT-1:0] i_raddr", + "code_block_2_0": "module in rtl directory synchronously stores events from the input `i_event` in a register bank. Each `i_event` input has an equivalent register. If the interface signal `i_en_overflow` is asserted, the register bank may wrap around when it reaches its maximum value, and an event occurs. If not asserted, the data stored in the register bank must be saturated.\n\nThe signals `i_bypass`, `i_data`, `i_raddr` are used to set the `o_data` signal such as:\n- If `i_bypass == 1`, then `o_data = i_data`.\n- If `i_bypass == 0`, then `o_data = reg_bank[i_raddr]`.\n\n**Modify** the module `event_storage` so that it is fully parameterizable. The parameters for this block are:\n\n- `NBW_STR`: Defines the bit width of the input and output data, as well as the bit width of each register in the register bank.\n- `NS_EVT`: Defines the number of parallel events stored by the module.\n- `NBW_EVT`: Defines the bit width of the read address used to select one of the event counters in `reg_bank`.\n\n----------\n\nThe `event_array` module implements a **2D pipeline of event processors** (called `event_storage` units), structured as a grid of **NS_ROWS \u00d7 NS_COLS**. Each processor operates on a stream of input data and associated events, performing updates and passing data to the next row in the same column. **All of the top module connections are fully combinational**. A testbench for it is provided.\n\n**Create** an `event_array` module in the rtl directory, and make sure it is fully parameterizable.\n\n### Specifications\n\n- **Module Name**: `event_array`\n\n- **Parameters**:\n - `NS_ROWS`: Number of rows in the 2D processing array.\n - Default value: 4.\n - Related interface signals: `i_en_overflow`, `i_event`, `i_bypass`.\n - `NS_COLS`: Number of columns in the 2D processing array.\n - Default value: 4. Must always be $`2^{NBW\\_COL}`$\n - Related interface signals: `i_en_overflow`, `i_event`, `i_data`, `i_col_sel`.\n - `NBW_COL`: Bit width of the column selection signal.\n - Default value: 2.\n - Related interface signals: `i_col_sel`.\n - `NBW_STR`: Bit width of the data processed in each `event_storage`.\n - Default value: 8.\n - Related interface signals: `i_data`, `o_data`.\n - `NS_EVT`: Number of event bits handled by each `event_storage`.\n - Default value: 8. Must always be $`2^{NBW\\_EVT}`$\n - Related interface signals: `i_event`.\n - `NBW_EVT`: Bit width of the read address used for event selection inside each `event_storage`.\n - Default value: 3.\n - Related interface signals: `i_raddr`.\n\n### Interface Signals\n\n- **Clock** (`clk`): Synchronizes operation at the rising edge.\n- **Reset** (`rst_async_n`): Active-low asynchronous reset. Resets the internal storage elements.\n- **Column Select** (`[NBW_COL-1:0] i_col_sel`): Selects which column\u2019s output from the last row will be assigned to `o_data`.\n- **Overflow Enable** (`[NS_ROWS*NS_COLS-1:0] i_en_overflow`): One-bit flag per `event_storage`. When high, enables overflow in `event_storage`'s internal registers.\n- **Event Input** (`[(NS_ROWS*NS_COLS*NS_EVT)-1:0] i_event`): All events (flattened) to be applied across the array. Each `event_storage` receives `NS_EVT` bits.\n- **Input Data** (`[(NS_COLS*NBW_STR)-1:0] i_data`): Parallel input data for the **first row only**, one value per column.\n- **Bypass Control** (`[NS_ROWS-1:0] i_bypass`): One bit per row. When high, it bypasses the event logic in that row's `event_storage`.\n- **Read Address** (`[NBW_EVT-1:0] i_raddr`): Address input used to read specific event-mapped data from each `event_storage`.\n- **Output Data** (`[NBW_STR-1:0] o_data`): Output from the selected column in the **last row**.\n\n### Functional Description\n\nThe `event_array` module is structured as a **2D pipeline** of `event_storage` units. Each unit represents a processing cell that performs bit-based updates to its internal data register according to the received `i_event` bits and the `i_en_overflow` flag.\n\nThe array is organized as `NS_ROWS` rows and `NS_COLS` columns.\n\n#### Input Flow:\n- Input data (`i_data`) is injected only into the **first row** of the array.\n- Each subsequent row receives the processed output from the `event_storage` directly above it in the same column.\n- All `event_storage` receive a unique slice of the flattened `i_event` and `i_en_overflow` arrays:\n - In `event_array`, the `i_event` input is a flat vector that holds all event bits for every cell in the grid, with each `event_storage` requiring `NS_EVT` bits. The module slices this vector by assigning `NS_EVT` bits to each `event_storage` based on its row and column. The slicing starts from the most significant bit and moves left to right across columns, then top to bottom across rows \u2014 like reading a table row by row. This way, each cell gets exactly the bits intended for its position in the array.\n - For example, if `NS_ROWS = 2`, `NS_COLS = 2`, and `NS_EVT = 4`, then `i_event` is 16 bits wide. The cell at row 0, column 0 gets the top 4 bits `[15:12]`, row 0, column 1 gets `[11:8]`, row 1, column 0 gets `[7:4]`, and row 1, column 1 gets the lowest 4 bits `[3:0]`.\n\n - The `i_en_overflow` input is a flat bit vector with one bit per `event_storage` in the grid. The vector is sliced using a row-major order: starting from the least significant bit, it maps left to right across columns, then top to bottom across rows.\n - For example, if `NS_ROWS = 2` and `NS_COLS = 2`, then `i_en_overflow` is 4 bits wide. The cell at row 0, column 0 gets bit `[0]`, row 0, column 1 gets bit `[1]`, row 1, column 0 gets bit `[2]`, and row 1, column 1 gets bit `[3]`.\n\n\n#### Output Logic:\n- After data has propagated through all rows, each column's final output is collected:\n - A `data_col_sel` signal is constructed by collecting the output data from each column in the last row of the array. For each column, the module takes the `data_out` of the `event_storage` cell at row `NS_ROWS - 1` and column `col`. These outputs are concatenated from **left to right** in **increasing column index order**, meaning **column 0 goes into the most significant bits**, and **column `NS_COLS - 1` goes into the least significant bits**. This signal is then connected to the input of the `column_selector` module.\n - For example, if `NS_COLS = 4` and `NBW_STR = 8`, then `data_col_sel` is 32 bits wide. The output from column 0 goes into bits `[31:24]`, column 1 into `[23:16]`, column 2 into `[15:8]`, and column 3 into `[7:0]`.\n\n- The `column_selector` submodule then selects one column based on `i_col_sel` to produce the module's final output `o_data`.\n\n {'docs/specification.md': None, 'rtl/decoder_data_control_64b66b.sv': None, 'rtl/encoder_control_64b66b.sv': None, 'rtl/encoder_data_64b66b.sv': None, 'rtl/aes128_encrypt.sv': None, 'verif/tb_aes128_enc.sv': None, 'rtl/aes128_decrypt.sv': None, 'rtl/aes128_key_expansion.sv': None, 'rtl/inv_sbox.sv': None, 'rtl/sbox.sv': None, 'verif/tb_aes128_dec.sv': None, 'rtl/aes_encrypt.sv': None, 'verif/tb_aes_encrypt.sv': None, 'rtl/aes_decrypt.sv': None, 'rtl/aes_ke.sv': None, 'verif/tb_aes_decrypt.sv': None, 'rtl/aes_dec_top.sv': None, 'rtl/aes_enc_top.sv': None, 'verif/tb_padding_top.sv': None, 'verif/tb_des_enc.sv': None, 'docs/Key_schedule.md': None, 'docs/Permutations.md': None, 'docs/S_box_creation.md': None, 'rtl/S1.sv': None, 'rtl/S2.sv': None, 'rtl/S3.sv': None, 'rtl/S4.sv': None, 'rtl/S5.sv': None, 'rtl/S6.sv': None, 'rtl/S7.sv': None, 'rtl/S8.sv': None, 'rtl/des_enc.sv': None, 'verif/tb_des_dec.sv': None, 'docs/Encryption.md': None, 'rtl/des_dec.sv': None, 'verif/tb_3des_enc.sv': None, 'verif/tb_3des_dec.sv': None, 'docs/min_hamming_distance_finder_spec.md': None, 'rtl/Bit_Difference_Counter.sv': None, 'rtl/Bitwise_Reduction.sv': None, 'rtl/Data_Reduction.sv': None, 'verif/tb_Min_Hamming_Distance_Finder.sv': None, 'docs/specs.md': None, 'rtl/arithmetic_progression_generator.sv': None, 'docs/algorithms.md': None, 'docs/coeff_update_spec.md': None, 'docs/equalizer_spec.md': None, 'docs/error_calc_spec.md': None, 'rtl/coeff_update.sv': None, 'rtl/dynamic_equalizer.sv': None, 'rtl/error_calc.sv': None, 'docs/awgn_spec.md': None, 'docs/equalizer_top_spec.md': None, 'rtl/elevator_control_system.sv': None, 'docs/tx_specification.md': None, 'rtl/ethernet_fifo_cdc.sv': None, 'docs/tx_mac_specification.md': None, 'verif/event_scheduler_tb.sv': None, 'docs/modified_specs.md': None, 'rtl/event_scheduler.sv': None, 'verif/tb_event_scheduler.sv': None, 'rtl/column_selector.sv': \"module column_selector #(\\n parameter NBW_STR = 'd8,\\n parameter NBW_COL = 'd2,\\n parameter NS_COLS = 'd4\\n) (\\n input logic [NBW_COL-1:0] i_col_sel,\\n input logic [(NBW_STR*NS_COLS)-1:0] i_data,\\n output logic [NBW_STR-1:0] o_data\\n);\\n\\n// ----------------------------------------\\n// - Wires/Registers creation\\n// ----------------------------------------\\nlogic [NBW_STR-1:0] data [0:NS_COLS-1];\\n\\n// ----------------------------------------\\n// - Unpack input data\\n// ----------------------------------------\\ngenerate\\n for(genvar i = 0; i < NS_COLS; i++) begin : unpack_data\\n assign data[i] = i_data[(NBW_STR*NS_COLS)-i*NBW_STR-1-:NBW_STR];\\n end\\nendgenerate\\n\\n// ----------------------------------------\\n// - Output assignment\\n// ----------------------------------------\\nalways_comb begin : output_assignment\\n o_data = data[i_col_sel];\\nend\\n\\nendmodule : column_selector\", 'rtl/event_storage.sv': \"module event_storage #(\\n parameter NBW_STR = 'd4,\\n parameter NS_EVT = 'd4,\\n parameter NBW_EVT = 'd2\\n) (\\n input logic clk,\\n input logic rst_async_n,\\n input logic i_en_overflow,\\n input logic [3:0] i_event,\\n input logic [3:0] i_data,\\n input logic i_bypass,\\n input logic [1:0] i_raddr,\\n output logic [3:0] o_data\\n);\\n\\n// ----------------------------------------\\n// - Wires/Registers creation\\n// ----------------------------------------\\nlogic [3:0] reg_bank [0:3];\\n\\n// ----------------------------------------\\n// - Block logic\\n// ----------------------------------------\\ngenerate\\n for (genvar i = 0; i < 4; i++) begin : instantiate_regs\\n always_ff @ (posedge clk or negedge rst_async_n) begin\\n if(!rst_async_n) begin\\n reg_bank[i] <= 0;\\n end else begin\\n if(i_en_overflow) begin\\n reg_bank[i] <= reg_bank[i] + i_event[i];\\n end else begin\\n if(reg_bank[i] == 4'd15) begin\\n reg_bank[i] <= reg_bank[i];\\n end else begin\\n reg_bank[i] <= reg_bank[i] + i_event[i];\\n end\\n end\\n end\\n end\\n end\\nendgenerate\\n\\n// ----------------------------------------\\n// - Output assignment\\n// ----------------------------------------\\nalways_comb begin : output_assignment\\n if(i_bypass) begin\\n o_data = i_data;\\n end else begin\\n o_data = reg_bank[i_raddr];\\n end\\nend\\n\\nendmodule : event_storage\", 'verif/tb.sv': 'module tb;\\n\\nlocalparam NS_ROWS = \\'d4;\\nlocalparam NS_COLS = \\'d4;\\nlocalparam NBW_COL = \\'d2;\\nlocalparam NBW_STR = \\'d8;\\nlocalparam NS_EVT = \\'d8;\\nlocalparam NBW_EVT = \\'d3;\\n\\nlogic clk;\\nlogic rst_async_n;\\nlogic [NBW_COL-1:0] i_col_sel;\\nlogic [NS_ROWS*NS_COLS-1:0] i_en_overflow;\\nlogic [(NS_ROWS*NS_COLS*NS_EVT)-1:0] i_event;\\nlogic [(NS_ROWS*NBW_STR)-1:0] i_data;\\nlogic [NS_ROWS-1:0] i_bypass;\\nlogic [NBW_EVT-1:0] i_raddr;\\nlogic [NBW_STR-1:0] o_data;\\n\\nevent_array #(\\n .NS_ROWS(NS_ROWS),\\n .NS_COLS(NS_COLS),\\n .NBW_COL(NBW_COL),\\n .NBW_STR(NBW_STR),\\n .NS_EVT(NS_EVT),\\n .NBW_EVT(NBW_EVT)\\n) uu_event_array (\\n .clk (clk ),\\n .rst_async_n (rst_async_n ),\\n .i_col_sel (i_col_sel ),\\n .i_en_overflow(i_en_overflow),\\n .i_event (i_event ),\\n .i_data (i_data ),\\n .i_bypass (i_bypass ),\\n .i_raddr (i_raddr ),\\n .o_data (o_data )\\n);\\n\\ninitial begin\\n $dumpfile(\"test.vcd\");\\n $dumpvars(0,tb);\\nend\\n\\ntask SimpleTest(int line_to_read, int col_to_read, int r_addr);\\n $display(\"---------------\");\\n $display(\"Running test reading row %2d, column %2d, address %2d\", line_to_read, col_to_read, r_addr);\\n @(negedge clk);\\n i_en_overflow = 0;\\n i_bypass = {NS_ROWS{1\\'b1}};\\n i_bypass[line_to_read] = 1\\'b0;\\n i_raddr = r_addr;\\n i_col_sel = col_to_read;\\n i_event = 0;\\n\\n for(int i = 1; i <= NS_ROWS*NS_COLS*NS_EVT; i++) begin\\n for(int j = 0; j < i; j++) begin\\n i_event[NS_ROWS*NS_COLS*NS_EVT-i] = 1\\'b1;\\n @(negedge clk);\\n end\\n i_event = 0;\\n end\\n\\n @(negedge clk);\\n\\n if((NS_EVT - r_addr + line_to_read*NS_COLS*NS_EVT + col_to_read*NS_EVT) > 2**NBW_STR - 1) begin\\n if(o_data != 2**NBW_STR - 1) begin\\n $display(\"FAIL! Received o_data = %2d, when it should have been %2d\", o_data, 2**NBW_STR - 1);\\n end else begin\\n $display(\"PASS! Received o_data = %2d\", o_data);\\n end\\n end else begin\\n if(o_data != (NS_EVT - r_addr + line_to_read*NS_COLS*NS_EVT + col_to_read*NS_EVT)) begin\\n $display(\"FAIL! Received o_data = %d, when it should have been %2d\", o_data, (NS_EVT - r_addr + line_to_read*NS_COLS*NS_EVT + col_to_read*NS_EVT));\\n end else begin\\n $display(\"PASS! Received o_data = %d\", o_data);\\n end\\n end\\nendtask\\n\\ntask Reset();\\n i_col_sel = 0;\\n i_en_overflow = 0;\\n i_event = 0;\\n i_data = 0;\\n i_bypass = 0;\\n i_raddr = 0;\\n rst_async_n = 1;\\n #1;\\n rst_async_n = 0;\\n #2;\\n rst_async_n = 1;\\n @(negedge clk);\\nendtask\\n\\ntask TestOverflow(logic overflow);\\n $display(\"---------------\");\\n $display(\"Testing overflow in row 0, column 0, address 0\");\\n @(negedge clk);\\n i_en_overflow = overflow;\\n i_bypass = {NS_ROWS{1\\'b1}};\\n i_bypass[0] = 1\\'b0;\\n i_raddr = 0;\\n i_col_sel = 0;\\n i_event = 0;\\n\\n for(int i = 0; i <= 2**NBW_STR; i++) begin\\n i_event[NS_ROWS*NS_COLS*NS_EVT-NS_EVT] = 1\\'b1;\\n @(negedge clk);\\n end\\n i_event = 0;\\n\\n @(negedge clk);\\n\\n if(overflow == 0) begin\\n if(o_data != 2**NBW_STR - 1) begin\\n $display(\"FAIL! Received o_data = %2d, when it should have been %2d\", o_data, 2**NBW_STR - 1);\\n end else begin\\n $display(\"PASS! Received o_data = %2d\", o_data);\\n end\\n end else begin\\n if(o_data != 1) begin\\n $display(\"FAIL! Received o_data = %2d, when it should have been %2d\", o_data, 1);\\n end else begin\\n $display(\"PASS! Received o_data = %2d\", o_data);\\n end\\n end\\nendtask\\n\\nalways #5 clk = ~clk;\\n\\nint value;\\n\\ninitial begin\\n clk = 0;\\n value = 1;\\n Reset();\\n\\n $display(\"----------------------\");\\n $display(\"This testbench writes:\");\\n for(int row = 0; row < NS_ROWS; row++) begin\\n for(int col = 0; col < NS_COLS; col++) begin\\n for(int addr = NS_EVT-1; addr >= 0; addr--) begin\\n $display(\"%2d in row %2d, col %2d, address %2d\", value, row, col, addr);\\n value++;\\n end\\n end\\n end\\n\\n $display(\"----------------------\");\\n $display(\"Note that, if any of those values are bigger than %2d, it will saturate when i_en_overflow = 0, and wrap around when i_en_overflow = 1.\", 2**NBW_STR - 1);\\n $display(\"----------------------\");\\n\\n // Tasks go here\\n SimpleTest(0, 0, 0);\\n Reset();\\n SimpleTest(1, 0, 0);\\n Reset();\\n SimpleTest(0, 1, 0);\\n Reset();\\n SimpleTest(0, 0, 1);\\n Reset();\\n SimpleTest(2, 1, 0);\\n Reset();\\n SimpleTest(1, 2, 2);\\n Reset();\\n SimpleTest(1, 2, 7);\\n Reset();\\n TestOverflow(1\\'b0);\\n Reset();\\n TestOverflow(1\\'b1);\\n Reset();\\n\\n @(negedge clk);\\n @(negedge clk);\\n\\n $finish();\\nend\\n\\nendmodule', 'rtl/fixed_priority_arbiter.sv': None, 'verif/fixed_priority_arbiter_tb.sv': None, 'docs/Modified_specification.md': None, 'docs/GCD_specification.md': None, 'docs/crypto_accelerator_specification.md': None, 'docs/modular_exponentiation_specification.md': None, 'docs/modular_multiplier_specification.md': None, 'rtl/gcd_controlpath_3.sv': None, 'rtl/gcd_controlpath_4.sv': None, 'rtl/gcd_datapath_5.sv': None, 'rtl/gcd_datapath_6.sv': None, 'rtl/gcd_top_1.sv': None, 'rtl/gcd_top_2.sv': None, 'rtl/modular_exponentiation.sv': None, 'rtl/modular_multiplier.sv': None, 'rtl/lfsr_8bit.sv': None, 'verif/lfsr_8bit_tb.sv': None, 'rtl/bit16_lfsr.sv': None, 'rtl/low_power_ctrl.sv': None, 'rtl/sync_fifo.sv': None, 'verif/tb_low_power_channel.sv': None, 'rtl/cross_domain_sync.sv': None, 'rtl/dsp_input_stage.sv': None, 'rtl/dsp_output_stage.sv': None, 'rtl/lfsr_generator.sv': None, 'rtl/monte_carlo_dsp_monitor_top.sv': None, 'verif/monte_carlo_dsp_monitor_top_tb.sv': None, 'docs/multiplexer_specification.md': None, 'verif/multiplexer_tb.sv': None, 'docs/nbit_swizzling_spec.md': None, 'verif/nbit_swizzling_tb.sv': None, 'docs/nmea_decoder_spec.md': None, 'rtl/nmea_decoder.sv': None, 'verif/nmea_decoder_tb.sv': None, 'docs/fifo.md': None, 'rtl/fifo_memory.sv': None, 'rtl/read_to_write_pointer_sync.sv': None, 'rtl/rptr_empty.sv': None, 'rtl/wptr_full.sv': None, 'rtl/write_to_read_pointer_sync.sv': None, 'docs/spec.md': None, 'verif/async_filo_tb.sv': None, 'docs/axilite_to_pcie_config_module.md': None, 'rtl/axi4lite_to_pcie_cfg_bridge.sv': None, 'rtl/axis_broadcast.sv': None, 'verif/tb_axis_broadcast.sv': None, 'docs/axis_to_uart_tx_specs.md': None, 'docs/uart_rx_to_axis_specs.md': None, 'rtl/barrel_shifter.sv': None, 'verif/barrel_shifter_tb.sv': None, 'rtl/bcd_adder.sv': None, 'rtl/full_adder.sv': None, 'rtl/four_bit_adder.sv': None, 'rtl/search_binary_search_tree.sv': None, 'rtl/delete_node_binary_search_tree.sv': None, 'docs/bst_operations.md': None, 'rtl/binary_search_tree_sort_construct.sv': None, 'docs/Spec.md': None, 'verif/tb_binary_to_gray.sv': None, 'verif/tb_custom_byte_enable_ram.sv': None, 'verif/cache_controller_tb.sv': None, 'rtl/caesar_cipher.sv': None, 'verif/caesar_cipher_tb.sv': None, 'verif/tb_pseudoRandGenerator_ca.sv': None, 'docs/continuous_adder_specification.md': None, 'verif/continuous_adder_tb.sv': None, 'rtl/fifo_buffer.sv': None, 'verif/tb_fifo_buffer.sv': None, 'docs/direct_map_cache_spec.md': None, 'verif/tb_direct_map_cache.sv': None, 'rtl/direct_map_cache.sv': None, 'rtl/dual_port_memory.sv': None, 'rtl/gen_cos_sin_lut.sv': None, 'rtl/phase_lut.sv': None, 'rtl/phase_rotation.sv': None, 'rtl/power4.sv': None, 'rtl/saturation.sv': None, 'rtl/top_phase_rotation.sv': None, 'docs/spec_viterbi.md': None, 'docs/spec_slicer_top.md': None, 'docs/spec_top_phase_rotation.md': None, 'rtl/slicer.sv': None, 'rtl/slicer_top.sv': None, 'docs/swizzler_specification.md': None, 'verif/swizzler_tb.sv': None, 'rtl/swizzler.sv': None, 'docs/sync_serial_communication_tx_rx_spec.md': None, 'verif/sync_serial_communication_tb.sv': None, 'rtl/weight_stationary_pe.sv': None, 'verif/systolic_array_tb.sv': None, 'rtl/thermostat.v': None, 'docs/Traffic_controller.md': None, 'rtl/traffic_light_controller.sv': None, 'docs/Universal_Shift_Register_spec.md': None, 'verif/tb_universal_shift_register.sv': None, 'rtl/universal_shift_register.sv': None, 'docs/spec_conj.md': None, 'docs/spec_cross_correlation.md': None, 'docs/spec_detect_sequence.md': None, 'rtl/adder_2d_layers.sv': None, 'rtl/adder_tree_2d.sv': None, 'rtl/correlate.sv': None, 'rtl/cross_correlation.sv': None, 'docs/valid_modes.md': None, 'docs/words_counting.md': None, 'rtl/detect_sequence.sv': None, 'docs/proc_fsm_spec.md': None, 'docs/adder_tree.md': None, 'docs/coeff_ram.md': None, 'docs/poly_decimator.md': None, 'docs/poly_filter.md': None, 'docs/shift_register.md': None, 'rtl/adder_tree.sv': None, 'rtl/coeff_ram.sv': None, 'rtl/poly_filter.sv': None, 'rtl/shift_register.sv': None, 'docs/prbs_specification.md': None, 'rtl/prbs_gen_check.sv': None, 'rtl/fsm.sv': None, 'verif/fsm_tb.sv': None, 'rtl/CA_1.sv': None, 'rtl/CA_2.sv': None, 'rtl/CA_3.sv': None, 'rtl/CA_4.sv': None, 'rtl/rgb_color_space_conversion.sv': None, 'rtl/APBGlobalHistoryRegister.v': None, 'docs/signed_comparator_specification.md': None, 'verif/signed_comparator_tb.sv': None, 'rtl/sorting_engine.sv': None, 'rtl/brick_sort.sv': None, 'rtl/bubble_sort.sv': None, 'rtl/merge_sort.sv': None, 'rtl/selection_sort.sv': None}", + "rtl/column_selector.sv": "module column_selector #(\n parameter NBW_STR = 'd8,\n parameter NBW_COL = 'd2,\n parameter NS_COLS = 'd4\n) (\n input logic [NBW_COL-1:0] i_col_sel,\n input logic [(NBW_STR*NS_COLS)-1:0] i_data,\n output logic [NBW_STR-1:0] o_data\n);\n\n// ----------------------------------------\n// - Wires/Registers creation\n// ----------------------------------------\nlogic [NBW_STR-1:0] data [0:NS_COLS-1];\n\n// ----------------------------------------\n// - Unpack input data\n// ----------------------------------------\ngenerate\n for(genvar i = 0; i < NS_COLS; i++) begin : unpack_data\n assign data[i] = i_data[(NBW_STR*NS_COLS)-i*NBW_STR-1-:NBW_STR];\n end\nendgenerate\n\n// ----------------------------------------\n// - Output assignment\n// ----------------------------------------\nalways_comb begin : output_assignment\n o_data = data[i_col_sel];\nend\n\nendmodule : column_selector", + "rtl/event_storage.sv": "module event_storage #(\n parameter NBW_STR = 'd4,\n parameter NS_EVT = 'd4,\n parameter NBW_EVT = 'd2\n) (\n input logic clk,\n input logic rst_async_n,\n input logic i_en_overflow,\n input logic [3:0] i_event,\n input logic [3:0] i_data,\n input logic i_bypass,\n input logic [1:0] i_raddr,\n output logic [3:0] o_data\n);\n\n// ----------------------------------------\n// - Wires/Registers creation\n// ----------------------------------------\nlogic [3:0] reg_bank [0:3];\n\n// ----------------------------------------\n// - Block logic\n// ----------------------------------------\ngenerate\n for (genvar i = 0; i < 4; i++) begin : instantiate_regs\n always_ff @ (posedge clk or negedge rst_async_n) begin\n if(!rst_async_n) begin\n reg_bank[i] <= 0;\n end else begin\n if(i_en_overflow) begin\n reg_bank[i] <= reg_bank[i] + i_event[i];\n end else begin\n if(reg_bank[i] == 4'd15) begin\n reg_bank[i] <= reg_bank[i];\n end else begin\n reg_bank[i] <= reg_bank[i] + i_event[i];\n end\n end\n end\n end\n end\nendgenerate\n\n// ----------------------------------------\n// - Output assignment\n// ----------------------------------------\nalways_comb begin : output_assignment\n if(i_bypass) begin\n o_data = i_data;\n end else begin\n o_data = reg_bank[i_raddr];\n end\nend\n\nendmodule : event_storage", + "verif/tb.sv": "module tb;\n\nlocalparam NS_ROWS = 'd4;\nlocalparam NS_COLS = 'd4;\nlocalparam NBW_COL = 'd2;\nlocalparam NBW_STR = 'd8;\nlocalparam NS_EVT = 'd8;\nlocalparam NBW_EVT = 'd3;\n\nlogic clk;\nlogic rst_async_n;\nlogic [NBW_COL-1:0] i_col_sel;\nlogic [NS_ROWS*NS_COLS-1:0] i_en_overflow;\nlogic [(NS_ROWS*NS_COLS*NS_EVT)-1:0] i_event;\nlogic [(NS_ROWS*NBW_STR)-1:0] i_data;\nlogic [NS_ROWS-1:0] i_bypass;\nlogic [NBW_EVT-1:0] i_raddr;\nlogic [NBW_STR-1:0] o_data;\n\nevent_array #(\n .NS_ROWS(NS_ROWS),\n .NS_COLS(NS_COLS),\n .NBW_COL(NBW_COL),\n .NBW_STR(NBW_STR),\n .NS_EVT(NS_EVT),\n .NBW_EVT(NBW_EVT)\n) uu_event_array (\n .clk (clk ),\n .rst_async_n (rst_async_n ),\n .i_col_sel (i_col_sel ),\n .i_en_overflow(i_en_overflow),\n .i_event (i_event ),\n .i_data (i_data ),\n .i_bypass (i_bypass ),\n .i_raddr (i_raddr ),\n .o_data (o_data )\n);\n\ninitial begin\n $dumpfile(\"test.vcd\");\n $dumpvars(0,tb);\nend\n\ntask SimpleTest(int line_to_read, int col_to_read, int r_addr);\n $display(\"---------------\");\n $display(\"Running test reading row %2d, column %2d, address %2d\", line_to_read, col_to_read, r_addr);\n @(negedge clk);\n i_en_overflow = 0;\n i_bypass = {NS_ROWS{1'b1}};\n i_bypass[line_to_read] = 1'b0;\n i_raddr = r_addr;\n i_col_sel = col_to_read;\n i_event = 0;\n\n for(int i = 1; i <= NS_ROWS*NS_COLS*NS_EVT; i++) begin\n for(int j = 0; j < i; j++) begin\n i_event[NS_ROWS*NS_COLS*NS_EVT-i] = 1'b1;\n @(negedge clk);\n end\n i_event = 0;\n end\n\n @(negedge clk);\n\n if((NS_EVT - r_addr + line_to_read*NS_COLS*NS_EVT + col_to_read*NS_EVT) > 2**NBW_STR - 1) begin\n if(o_data != 2**NBW_STR - 1) begin\n $display(\"FAIL! Received o_data = %2d, when it should have been %2d\", o_data, 2**NBW_STR - 1);\n end else begin\n $display(\"PASS! Received o_data = %2d\", o_data);\n end\n end else begin\n if(o_data != (NS_EVT - r_addr + line_to_read*NS_COLS*NS_EVT + col_to_read*NS_EVT)) begin\n $display(\"FAIL! Received o_data = %d, when it should have been %2d\", o_data, (NS_EVT - r_addr + line_to_read*NS_COLS*NS_EVT + col_to_read*NS_EVT));\n end else begin\n $display(\"PASS! Received o_data = %d\", o_data);\n end\n end\nendtask\n\ntask Reset();\n i_col_sel = 0;\n i_en_overflow = 0;\n i_event = 0;\n i_data = 0;\n i_bypass = 0;\n i_raddr = 0;\n rst_async_n = 1;\n #1;\n rst_async_n = 0;\n #2;\n rst_async_n = 1;\n @(negedge clk);\nendtask\n\ntask TestOverflow(logic overflow);\n $display(\"---------------\");\n $display(\"Testing overflow in row 0, column 0, address 0\");\n @(negedge clk);\n i_en_overflow = overflow;\n i_bypass = {NS_ROWS{1'b1}};\n i_bypass[0] = 1'b0;\n i_raddr = 0;\n i_col_sel = 0;\n i_event = 0;\n\n for(int i = 0; i <= 2**NBW_STR; i++) begin\n i_event[NS_ROWS*NS_COLS*NS_EVT-NS_EVT] = 1'b1;\n @(negedge clk);\n end\n i_event = 0;\n\n @(negedge clk);\n\n if(overflow == 0) begin\n if(o_data != 2**NBW_STR - 1) begin\n $display(\"FAIL! Received o_data = %2d, when it should have been %2d\", o_data, 2**NBW_STR - 1);\n end else begin\n $display(\"PASS! Received o_data = %2d\", o_data);\n end\n end else begin\n if(o_data != 1) begin\n $display(\"FAIL! Received o_data = %2d, when it should have been %2d\", o_data, 1);\n end else begin\n $display(\"PASS! Received o_data = %2d\", o_data);\n end\n end\nendtask\n\nalways #5 clk = ~clk;\n\nint value;\n\ninitial begin\n clk = 0;\n value = 1;\n Reset();\n\n $display(\"----------------------\");\n $display(\"This testbench writes:\");\n for(int row = 0; row < NS_ROWS; row++) begin\n for(int col = 0; col < NS_COLS; col++) begin\n for(int addr = NS_EVT-1; addr >= 0; addr--) begin\n $display(\"%2d in row %2d, col %2d, address %2d\", value, row, col, addr);\n value++;\n end\n end\n end\n\n $display(\"----------------------\");\n $display(\"Note that, if any of those values are bigger than %2d, it will saturate when i_en_overflow = 0, and wrap around when i_en_overflow = 1.\", 2**NBW_STR - 1);\n $display(\"----------------------\");\n\n // Tasks go here\n SimpleTest(0, 0, 0);\n Reset();\n SimpleTest(1, 0, 0);\n Reset();\n SimpleTest(0, 1, 0);\n Reset();\n SimpleTest(0, 0, 1);\n Reset();\n SimpleTest(2, 1, 0);\n Reset();\n SimpleTest(1, 2, 2);\n Reset();\n SimpleTest(1, 2, 7);\n Reset();\n TestOverflow(1'b0);\n Reset();\n TestOverflow(1'b1);\n Reset();\n\n @(negedge clk);\n @(negedge clk);\n\n $finish();\nend\n\nendmodule" + }, + "test_info": { + "test_criteria_0": [ + "for it is provided." + ] + }, + "expected_behavior": [ + "be saturated", + "always be $`2^{NBW\\_COL}`$", + "always be $`2^{NBW\\_EVT}`$", + "be assigned to `o_data`" + ], + "metadata": { + "categories": [ + "cid005", + "hard" + ], + "domain": "processor", + "complexity": "expert", + "problem_type": "design", + "has_code": true, + "has_tests": true + }, + "full_prompt": "The `event_storage` module in rtl directory synchronously stores events from the input `i_event` in a register bank. Each `i_event` input has an equivalent register. If the interface signal `i_en_overflow` is asserted, the register bank may wrap around when it reaches its maximum value, and an event occurs. If not asserted, the data stored in the register bank must be saturated.\n\nThe signals `i_bypass`, `i_data`, `i_raddr` are used to set the `o_data` signal such as:\n- If `i_bypass == 1`, then `o_data = i_data`.\n- If `i_bypass == 0`, then `o_data = reg_bank[i_raddr]`.\n\n**Modify** the module `event_storage` so that it is fully parameterizable. The parameters for this block are:\n\n- `NBW_STR`: Defines the bit width of the input and output data, as well as the bit width of each register in the register bank.\n- `NS_EVT`: Defines the number of parallel events stored by the module.\n- `NBW_EVT`: Defines the bit width of the read address used to select one of the event counters in `reg_bank`.\n\n----------\n\nThe `event_array` module implements a **2D pipeline of event processors** (called `event_storage` units), structured as a grid of **NS_ROWS \u00d7 NS_COLS**. Each processor operates on a stream of input data and associated events, performing updates and passing data to the next row in the same column. **All of the top module connections are fully combinational**. A testbench for it is provided.\n\n**Create** an `event_array` module in the rtl directory, and make sure it is fully parameterizable.\n\n### Specifications\n\n- **Module Name**: `event_array`\n\n- **Parameters**:\n - `NS_ROWS`: Number of rows in the 2D processing array.\n - Default value: 4.\n - Related interface signals: `i_en_overflow`, `i_event`, `i_bypass`.\n - `NS_COLS`: Number of columns in the 2D processing array.\n - Default value: 4. Must always be $`2^{NBW\\_COL}`$\n - Related interface signals: `i_en_overflow`, `i_event`, `i_data`, `i_col_sel`.\n - `NBW_COL`: Bit width of the column selection signal.\n - Default value: 2.\n - Related interface signals: `i_col_sel`.\n - `NBW_STR`: Bit width of the data processed in each `event_storage`.\n - Default value: 8.\n - Related interface signals: `i_data`, `o_data`.\n - `NS_EVT`: Number of event bits handled by each `event_storage`.\n - Default value: 8. Must always be $`2^{NBW\\_EVT}`$\n - Related interface signals: `i_event`.\n - `NBW_EVT`: Bit width of the read address used for event selection inside each `event_storage`.\n - Default value: 3.\n - Related interface signals: `i_raddr`.\n\n### Interface Signals\n\n- **Clock** (`clk`): Synchronizes operation at the rising edge.\n- **Reset** (`rst_async_n`): Active-low asynchronous reset. Resets the internal storage elements.\n- **Column Select** (`[NBW_COL-1:0] i_col_sel`): Selects which column\u2019s output from the last row will be assigned to `o_data`.\n- **Overflow Enable** (`[NS_ROWS*NS_COLS-1:0] i_en_overflow`): One-bit flag per `event_storage`. When high, enables overflow in `event_storage`'s internal registers.\n- **Event Input** (`[(NS_ROWS*NS_COLS*NS_EVT)-1:0] i_event`): All events (flattened) to be applied across the array. Each `event_storage` receives `NS_EVT` bits.\n- **Input Data** (`[(NS_COLS*NBW_STR)-1:0] i_data`): Parallel input data for the **first row only**, one value per column.\n- **Bypass Control** (`[NS_ROWS-1:0] i_bypass`): One bit per row. When high, it bypasses the event logic in that row's `event_storage`.\n- **Read Address** (`[NBW_EVT-1:0] i_raddr`): Address input used to read specific event-mapped data from each `event_storage`.\n- **Output Data** (`[NBW_STR-1:0] o_data`): Output from the selected column in the **last row**.\n\n### Functional Description\n\nThe `event_array` module is structured as a **2D pipeline** of `event_storage` units. Each unit represents a processing cell that performs bit-based updates to its internal data register according to the received `i_event` bits and the `i_en_overflow` flag.\n\nThe array is organized as `NS_ROWS` rows and `NS_COLS` columns.\n\n#### Input Flow:\n- Input data (`i_data`) is injected only into the **first row** of the array.\n- Each subsequent row receives the processed output from the `event_storage` directly above it in the same column.\n- All `event_storage` receive a unique slice of the flattened `i_event` and `i_en_overflow` arrays:\n - In `event_array`, the `i_event` input is a flat vector that holds all event bits for every cell in the grid, with each `event_storage` requiring `NS_EVT` bits. The module slices this vector by assigning `NS_EVT` bits to each `event_storage` based on its row and column. The slicing starts from the most significant bit and moves left to right across columns, then top to bottom across rows \u2014 like reading a table row by row. This way, each cell gets exactly the bits intended for its position in the array.\n - For example, if `NS_ROWS = 2`, `NS_COLS = 2`, and `NS_EVT = 4`, then `i_event` is 16 bits wide. The cell at row 0, column 0 gets the top 4 bits `[15:12]`, row 0, column 1 gets `[11:8]`, row 1, column 0 gets `[7:4]`, and row 1, column 1 gets the lowest 4 bits `[3:0]`.\n\n - The `i_en_overflow` input is a flat bit vector with one bit per `event_storage` in the grid. The vector is sliced using a row-major order: starting from the least significant bit, it maps left to right across columns, then top to bottom across rows.\n - For example, if `NS_ROWS = 2` and `NS_COLS = 2`, then `i_en_overflow` is 4 bits wide. The cell at row 0, column 0 gets bit `[0]`, row 0, column 1 gets bit `[1]`, row 1, column 0 gets bit `[2]`, and row 1, column 1 gets bit `[3]`.\n\n\n#### Output Logic:\n- After data has propagated through all rows, each column's final output is collected:\n - A `data_col_sel` signal is constructed by collecting the output data from each column in the last row of the array. For each column, the module takes the `data_out` of the `event_storage` cell at row `NS_ROWS - 1` and column `col`. These outputs are concatenated from **left to right** in **increasing column index order**, meaning **column 0 goes into the most significant bits**, and **column `NS_COLS - 1` goes into the least significant bits**. This signal is then connected to the input of the `column_selector` module.\n - For example, if `NS_COLS = 4` and `NBW_STR = 8`, then `data_col_sel` is 32 bits wide. The output from column 0 goes into bits `[31:24]`, column 1 into `[23:16]`, column 2 into `[15:8]`, and column 3 into `[7:0]`.\n\n- The `column_selector` submodule then selects one column based on `i_col_sel` to produce the module's final output `o_data`.\n\n", + "system_message": "You are a language model that has the following file operations available at your disposal:\n - **List files in a directory** by running one of the following commands: \n - `ls`\n - `tree`\n - **Read files** by using:\n - `cat `\n - **Write files** by using:\n - `echo > `\n - **Compile Verilog** by using `iverilog` such as:\n - `iverilog -o .out -g2012 `\n - **Run Simulation** by using:\n - `vvp .out`\n - **Find current working directory** by using:\n - `pwd`\n - **Update the contents of a text file from a old content to new content**\n - `sed -i \"line_number s/old_statement/new_statement/\" file.sv`\n - **To access a specific line of the file**\n - `awk 'NR==line_number' file_name.sv`\n\nYou will be given a prompt and your task is to understand it and solve the given issue by using the above-mentioned commands as needed. In the final step, you should create a Linux patch to highlight the necessary file updates to achieve the targeted goal.\n\n You will solve the problem step by step using the following approach of \n - thought (thinking process of the step you're going to take)\n - action (the command you will be running to get more details/context that's helpful to solve the problem)\n - observation (the output from the action you will observe based on which you will take your next step)\n\n The last step will be the final output summary and the patch itself in the following format \n - thought (the summary of what you did and some introduction of the patch file itself)\n - patch (a Linux-based patch that needs to be applied to reach the relevant solution)", + "raw_context": { + "docs/specification.md": null, + "rtl/decoder_data_control_64b66b.sv": null, + "rtl/encoder_control_64b66b.sv": null, + "rtl/encoder_data_64b66b.sv": null, + "rtl/aes128_encrypt.sv": null, + "verif/tb_aes128_enc.sv": null, + "rtl/aes128_decrypt.sv": null, + "rtl/aes128_key_expansion.sv": null, + "rtl/inv_sbox.sv": null, + "rtl/sbox.sv": null, + "verif/tb_aes128_dec.sv": null, + "rtl/aes_encrypt.sv": null, + "verif/tb_aes_encrypt.sv": null, + "rtl/aes_decrypt.sv": null, + "rtl/aes_ke.sv": null, + "verif/tb_aes_decrypt.sv": null, + "rtl/aes_dec_top.sv": null, + "rtl/aes_enc_top.sv": null, + "verif/tb_padding_top.sv": null, + "verif/tb_des_enc.sv": null, + "docs/Key_schedule.md": null, + "docs/Permutations.md": null, + "docs/S_box_creation.md": null, + "rtl/S1.sv": null, + "rtl/S2.sv": null, + "rtl/S3.sv": null, + "rtl/S4.sv": null, + "rtl/S5.sv": null, + "rtl/S6.sv": null, + "rtl/S7.sv": null, + "rtl/S8.sv": null, + "rtl/des_enc.sv": null, + "verif/tb_des_dec.sv": null, + "docs/Encryption.md": null, + "rtl/des_dec.sv": null, + "verif/tb_3des_enc.sv": null, + "verif/tb_3des_dec.sv": null, + "docs/min_hamming_distance_finder_spec.md": null, + "rtl/Bit_Difference_Counter.sv": null, + "rtl/Bitwise_Reduction.sv": null, + "rtl/Data_Reduction.sv": null, + "verif/tb_Min_Hamming_Distance_Finder.sv": null, + "docs/specs.md": null, + "rtl/arithmetic_progression_generator.sv": null, + "docs/algorithms.md": null, + "docs/coeff_update_spec.md": null, + "docs/equalizer_spec.md": null, + "docs/error_calc_spec.md": null, + "rtl/coeff_update.sv": null, + "rtl/dynamic_equalizer.sv": null, + "rtl/error_calc.sv": null, + "docs/awgn_spec.md": null, + "docs/equalizer_top_spec.md": null, + "rtl/elevator_control_system.sv": null, + "docs/tx_specification.md": null, + "rtl/ethernet_fifo_cdc.sv": null, + "docs/tx_mac_specification.md": null, + "verif/event_scheduler_tb.sv": null, + "docs/modified_specs.md": null, + "rtl/event_scheduler.sv": null, + "verif/tb_event_scheduler.sv": null, + "rtl/column_selector.sv": "module column_selector #(\n parameter NBW_STR = 'd8,\n parameter NBW_COL = 'd2,\n parameter NS_COLS = 'd4\n) (\n input logic [NBW_COL-1:0] i_col_sel,\n input logic [(NBW_STR*NS_COLS)-1:0] i_data,\n output logic [NBW_STR-1:0] o_data\n);\n\n// ----------------------------------------\n// - Wires/Registers creation\n// ----------------------------------------\nlogic [NBW_STR-1:0] data [0:NS_COLS-1];\n\n// ----------------------------------------\n// - Unpack input data\n// ----------------------------------------\ngenerate\n for(genvar i = 0; i < NS_COLS; i++) begin : unpack_data\n assign data[i] = i_data[(NBW_STR*NS_COLS)-i*NBW_STR-1-:NBW_STR];\n end\nendgenerate\n\n// ----------------------------------------\n// - Output assignment\n// ----------------------------------------\nalways_comb begin : output_assignment\n o_data = data[i_col_sel];\nend\n\nendmodule : column_selector", + "rtl/event_storage.sv": "module event_storage #(\n parameter NBW_STR = 'd4,\n parameter NS_EVT = 'd4,\n parameter NBW_EVT = 'd2\n) (\n input logic clk,\n input logic rst_async_n,\n input logic i_en_overflow,\n input logic [3:0] i_event,\n input logic [3:0] i_data,\n input logic i_bypass,\n input logic [1:0] i_raddr,\n output logic [3:0] o_data\n);\n\n// ----------------------------------------\n// - Wires/Registers creation\n// ----------------------------------------\nlogic [3:0] reg_bank [0:3];\n\n// ----------------------------------------\n// - Block logic\n// ----------------------------------------\ngenerate\n for (genvar i = 0; i < 4; i++) begin : instantiate_regs\n always_ff @ (posedge clk or negedge rst_async_n) begin\n if(!rst_async_n) begin\n reg_bank[i] <= 0;\n end else begin\n if(i_en_overflow) begin\n reg_bank[i] <= reg_bank[i] + i_event[i];\n end else begin\n if(reg_bank[i] == 4'd15) begin\n reg_bank[i] <= reg_bank[i];\n end else begin\n reg_bank[i] <= reg_bank[i] + i_event[i];\n end\n end\n end\n end\n end\nendgenerate\n\n// ----------------------------------------\n// - Output assignment\n// ----------------------------------------\nalways_comb begin : output_assignment\n if(i_bypass) begin\n o_data = i_data;\n end else begin\n o_data = reg_bank[i_raddr];\n end\nend\n\nendmodule : event_storage", + "verif/tb.sv": "module tb;\n\nlocalparam NS_ROWS = 'd4;\nlocalparam NS_COLS = 'd4;\nlocalparam NBW_COL = 'd2;\nlocalparam NBW_STR = 'd8;\nlocalparam NS_EVT = 'd8;\nlocalparam NBW_EVT = 'd3;\n\nlogic clk;\nlogic rst_async_n;\nlogic [NBW_COL-1:0] i_col_sel;\nlogic [NS_ROWS*NS_COLS-1:0] i_en_overflow;\nlogic [(NS_ROWS*NS_COLS*NS_EVT)-1:0] i_event;\nlogic [(NS_ROWS*NBW_STR)-1:0] i_data;\nlogic [NS_ROWS-1:0] i_bypass;\nlogic [NBW_EVT-1:0] i_raddr;\nlogic [NBW_STR-1:0] o_data;\n\nevent_array #(\n .NS_ROWS(NS_ROWS),\n .NS_COLS(NS_COLS),\n .NBW_COL(NBW_COL),\n .NBW_STR(NBW_STR),\n .NS_EVT(NS_EVT),\n .NBW_EVT(NBW_EVT)\n) uu_event_array (\n .clk (clk ),\n .rst_async_n (rst_async_n ),\n .i_col_sel (i_col_sel ),\n .i_en_overflow(i_en_overflow),\n .i_event (i_event ),\n .i_data (i_data ),\n .i_bypass (i_bypass ),\n .i_raddr (i_raddr ),\n .o_data (o_data )\n);\n\ninitial begin\n $dumpfile(\"test.vcd\");\n $dumpvars(0,tb);\nend\n\ntask SimpleTest(int line_to_read, int col_to_read, int r_addr);\n $display(\"---------------\");\n $display(\"Running test reading row %2d, column %2d, address %2d\", line_to_read, col_to_read, r_addr);\n @(negedge clk);\n i_en_overflow = 0;\n i_bypass = {NS_ROWS{1'b1}};\n i_bypass[line_to_read] = 1'b0;\n i_raddr = r_addr;\n i_col_sel = col_to_read;\n i_event = 0;\n\n for(int i = 1; i <= NS_ROWS*NS_COLS*NS_EVT; i++) begin\n for(int j = 0; j < i; j++) begin\n i_event[NS_ROWS*NS_COLS*NS_EVT-i] = 1'b1;\n @(negedge clk);\n end\n i_event = 0;\n end\n\n @(negedge clk);\n\n if((NS_EVT - r_addr + line_to_read*NS_COLS*NS_EVT + col_to_read*NS_EVT) > 2**NBW_STR - 1) begin\n if(o_data != 2**NBW_STR - 1) begin\n $display(\"FAIL! Received o_data = %2d, when it should have been %2d\", o_data, 2**NBW_STR - 1);\n end else begin\n $display(\"PASS! Received o_data = %2d\", o_data);\n end\n end else begin\n if(o_data != (NS_EVT - r_addr + line_to_read*NS_COLS*NS_EVT + col_to_read*NS_EVT)) begin\n $display(\"FAIL! Received o_data = %d, when it should have been %2d\", o_data, (NS_EVT - r_addr + line_to_read*NS_COLS*NS_EVT + col_to_read*NS_EVT));\n end else begin\n $display(\"PASS! Received o_data = %d\", o_data);\n end\n end\nendtask\n\ntask Reset();\n i_col_sel = 0;\n i_en_overflow = 0;\n i_event = 0;\n i_data = 0;\n i_bypass = 0;\n i_raddr = 0;\n rst_async_n = 1;\n #1;\n rst_async_n = 0;\n #2;\n rst_async_n = 1;\n @(negedge clk);\nendtask\n\ntask TestOverflow(logic overflow);\n $display(\"---------------\");\n $display(\"Testing overflow in row 0, column 0, address 0\");\n @(negedge clk);\n i_en_overflow = overflow;\n i_bypass = {NS_ROWS{1'b1}};\n i_bypass[0] = 1'b0;\n i_raddr = 0;\n i_col_sel = 0;\n i_event = 0;\n\n for(int i = 0; i <= 2**NBW_STR; i++) begin\n i_event[NS_ROWS*NS_COLS*NS_EVT-NS_EVT] = 1'b1;\n @(negedge clk);\n end\n i_event = 0;\n\n @(negedge clk);\n\n if(overflow == 0) begin\n if(o_data != 2**NBW_STR - 1) begin\n $display(\"FAIL! Received o_data = %2d, when it should have been %2d\", o_data, 2**NBW_STR - 1);\n end else begin\n $display(\"PASS! Received o_data = %2d\", o_data);\n end\n end else begin\n if(o_data != 1) begin\n $display(\"FAIL! Received o_data = %2d, when it should have been %2d\", o_data, 1);\n end else begin\n $display(\"PASS! Received o_data = %2d\", o_data);\n end\n end\nendtask\n\nalways #5 clk = ~clk;\n\nint value;\n\ninitial begin\n clk = 0;\n value = 1;\n Reset();\n\n $display(\"----------------------\");\n $display(\"This testbench writes:\");\n for(int row = 0; row < NS_ROWS; row++) begin\n for(int col = 0; col < NS_COLS; col++) begin\n for(int addr = NS_EVT-1; addr >= 0; addr--) begin\n $display(\"%2d in row %2d, col %2d, address %2d\", value, row, col, addr);\n value++;\n end\n end\n end\n\n $display(\"----------------------\");\n $display(\"Note that, if any of those values are bigger than %2d, it will saturate when i_en_overflow = 0, and wrap around when i_en_overflow = 1.\", 2**NBW_STR - 1);\n $display(\"----------------------\");\n\n // Tasks go here\n SimpleTest(0, 0, 0);\n Reset();\n SimpleTest(1, 0, 0);\n Reset();\n SimpleTest(0, 1, 0);\n Reset();\n SimpleTest(0, 0, 1);\n Reset();\n SimpleTest(2, 1, 0);\n Reset();\n SimpleTest(1, 2, 2);\n Reset();\n SimpleTest(1, 2, 7);\n Reset();\n TestOverflow(1'b0);\n Reset();\n TestOverflow(1'b1);\n Reset();\n\n @(negedge clk);\n @(negedge clk);\n\n $finish();\nend\n\nendmodule", + "rtl/fixed_priority_arbiter.sv": null, + "verif/fixed_priority_arbiter_tb.sv": null, + "docs/Modified_specification.md": null, + "docs/GCD_specification.md": null, + "docs/crypto_accelerator_specification.md": null, + "docs/modular_exponentiation_specification.md": null, + "docs/modular_multiplier_specification.md": null, + "rtl/gcd_controlpath_3.sv": null, + "rtl/gcd_controlpath_4.sv": null, + "rtl/gcd_datapath_5.sv": null, + "rtl/gcd_datapath_6.sv": null, + "rtl/gcd_top_1.sv": null, + "rtl/gcd_top_2.sv": null, + "rtl/modular_exponentiation.sv": null, + "rtl/modular_multiplier.sv": null, + "rtl/lfsr_8bit.sv": null, + "verif/lfsr_8bit_tb.sv": null, + "rtl/bit16_lfsr.sv": null, + "rtl/low_power_ctrl.sv": null, + "rtl/sync_fifo.sv": null, + "verif/tb_low_power_channel.sv": null, + "rtl/cross_domain_sync.sv": null, + "rtl/dsp_input_stage.sv": null, + "rtl/dsp_output_stage.sv": null, + "rtl/lfsr_generator.sv": null, + "rtl/monte_carlo_dsp_monitor_top.sv": null, + "verif/monte_carlo_dsp_monitor_top_tb.sv": null, + "docs/multiplexer_specification.md": null, + "verif/multiplexer_tb.sv": null, + "docs/nbit_swizzling_spec.md": null, + "verif/nbit_swizzling_tb.sv": null, + "docs/nmea_decoder_spec.md": null, + "rtl/nmea_decoder.sv": null, + "verif/nmea_decoder_tb.sv": null, + "docs/fifo.md": null, + "rtl/fifo_memory.sv": null, + "rtl/read_to_write_pointer_sync.sv": null, + "rtl/rptr_empty.sv": null, + "rtl/wptr_full.sv": null, + "rtl/write_to_read_pointer_sync.sv": null, + "docs/spec.md": null, + "verif/async_filo_tb.sv": null, + "docs/axilite_to_pcie_config_module.md": null, + "rtl/axi4lite_to_pcie_cfg_bridge.sv": null, + "rtl/axis_broadcast.sv": null, + "verif/tb_axis_broadcast.sv": null, + "docs/axis_to_uart_tx_specs.md": null, + "docs/uart_rx_to_axis_specs.md": null, + "rtl/barrel_shifter.sv": null, + "verif/barrel_shifter_tb.sv": null, + "rtl/bcd_adder.sv": null, + "rtl/full_adder.sv": null, + "rtl/four_bit_adder.sv": null, + "rtl/search_binary_search_tree.sv": null, + "rtl/delete_node_binary_search_tree.sv": null, + "docs/bst_operations.md": null, + "rtl/binary_search_tree_sort_construct.sv": null, + "docs/Spec.md": null, + "verif/tb_binary_to_gray.sv": null, + "verif/tb_custom_byte_enable_ram.sv": null, + "verif/cache_controller_tb.sv": null, + "rtl/caesar_cipher.sv": null, + "verif/caesar_cipher_tb.sv": null, + "verif/tb_pseudoRandGenerator_ca.sv": null, + "docs/continuous_adder_specification.md": null, + "verif/continuous_adder_tb.sv": null, + "rtl/fifo_buffer.sv": null, + "verif/tb_fifo_buffer.sv": null, + "docs/direct_map_cache_spec.md": null, + "verif/tb_direct_map_cache.sv": null, + "rtl/direct_map_cache.sv": null, + "rtl/dual_port_memory.sv": null, + "rtl/gen_cos_sin_lut.sv": null, + "rtl/phase_lut.sv": null, + "rtl/phase_rotation.sv": null, + "rtl/power4.sv": null, + "rtl/saturation.sv": null, + "rtl/top_phase_rotation.sv": null, + "docs/spec_viterbi.md": null, + "docs/spec_slicer_top.md": null, + "docs/spec_top_phase_rotation.md": null, + "rtl/slicer.sv": null, + "rtl/slicer_top.sv": null, + "docs/swizzler_specification.md": null, + "verif/swizzler_tb.sv": null, + "rtl/swizzler.sv": null, + "docs/sync_serial_communication_tx_rx_spec.md": null, + "verif/sync_serial_communication_tb.sv": null, + "rtl/weight_stationary_pe.sv": null, + "verif/systolic_array_tb.sv": null, + "rtl/thermostat.v": null, + "docs/Traffic_controller.md": null, + "rtl/traffic_light_controller.sv": null, + "docs/Universal_Shift_Register_spec.md": null, + "verif/tb_universal_shift_register.sv": null, + "rtl/universal_shift_register.sv": null, + "docs/spec_conj.md": null, + "docs/spec_cross_correlation.md": null, + "docs/spec_detect_sequence.md": null, + "rtl/adder_2d_layers.sv": null, + "rtl/adder_tree_2d.sv": null, + "rtl/correlate.sv": null, + "rtl/cross_correlation.sv": null, + "docs/valid_modes.md": null, + "docs/words_counting.md": null, + "rtl/detect_sequence.sv": null, + "docs/proc_fsm_spec.md": null, + "docs/adder_tree.md": null, + "docs/coeff_ram.md": null, + "docs/poly_decimator.md": null, + "docs/poly_filter.md": null, + "docs/shift_register.md": null, + "rtl/adder_tree.sv": null, + "rtl/coeff_ram.sv": null, + "rtl/poly_filter.sv": null, + "rtl/shift_register.sv": null, + "docs/prbs_specification.md": null, + "rtl/prbs_gen_check.sv": null, + "rtl/fsm.sv": null, + "verif/fsm_tb.sv": null, + "rtl/CA_1.sv": null, + "rtl/CA_2.sv": null, + "rtl/CA_3.sv": null, + "rtl/CA_4.sv": null, + "rtl/rgb_color_space_conversion.sv": null, + "rtl/APBGlobalHistoryRegister.v": null, + "docs/signed_comparator_specification.md": null, + "verif/signed_comparator_tb.sv": null, + "rtl/sorting_engine.sv": null, + "rtl/brick_sort.sv": null, + "rtl/bubble_sort.sv": null, + "rtl/merge_sort.sv": null, + "rtl/selection_sort.sv": null + } + }, + { + "id": "cvdp_agentic_poly_decimator_0001", + "index": 558, + "source_config": "cvdp_agentic_code_generation_no_commercial", + "instruction": "Context: You are a language model that has the following file operations available at your disposal:\n - **List files in a directory** by running one of the following commands: \n - `ls`\n - `tree`\n - **Read files** by using:\n - `cat `\n - **Write files** by using:\n - `echo > `\n - **Edit files** by using:\n - `sed -i 's/old_text/new_text/g' `\n - **Compile Verilog** by using `iverilog` such as:\n - `iverilog -o .out -g2012 `\n - **Run Simulation** by using:\n - `vvp .out`\n - **Find current working directory** by using:\n - `pwd`\n\nYou will be given a prompt and your task is to understand it and solve the given issue by using the above-mentioned commands as needed. In the final step, you should create a Linux patch to highlight the necessary file updates to achieve the targeted goal.\n\n You will solve the problem step by step using the following approach of \n - thought (thinking process of the step you're going to take)\n - action (the command you will be running to get more details/context that's helpful to solve the problem)\n - observation (the output from the action you will observe based on which you will take your next step)\n\n The last step will be the final output summary and the patch itself in the following format \n - thought (the summary of what you did and some introduction of the patch file itself)\n - patch (a Linux-based patch that needs to be applied to reach the relevant solution)\n\n The patch file should only be applied to a single file to reach the required solution.\n\nTask: You are required to System Verilog module `poly_decimator`. The `poly_decimator` is a top-module and it must integrate a number of provided files. The detailed specification of `poly_decimator` is provided in the document `docs/poly_decimator.md`.\n\n## Integration Instructions\n- The **`poly_decimator`** module, that should be defined in `rtl/poly_decimator.sv`, must serve as the top-level design. It is responsible for handling the overall decimation operation of M samples.\n\nYou are also provided with a library of pre-designed modules that must be integrated into the target module. The library modules are:\n\n- **adder_tree** \n - **File:** `rtl/adder_tree.sv` \n - **Specifications:** `docs/adder_tree.md` \n - **Functionality:** Implements a pipelined adder tree for summing multiple data inputs.\n\n- **shift_register** \n - **File:** `rtl/shift_register.sv` \n - **Specifications:** `docs/shift_register.md` \n - **Functionality:** Implements a shift register that stores a history of input samples.\n\n- **coeff_ram** \n - **File:** `rtl/coeff_ram.sv` \n - **Specifications:** `docs/coeff_ram.md` \n - **Functionality:** Provides a synchronous memory block for storing filter coefficients.\n\n- **poly_filter** \n - **File:** `rtl/poly_filter.sv` \n - **Specifications:** `docs/poly_filter.md` \n - **Functionality:** Implements the filtering operation for each polyphase branch: it multiplies a subset of input samples by the proper coefficients, then sums the products.\n\nEnsure that you fully understand the functionality and interfaces of these modules as described in their specification documents. They must be integrated properly to achieve the desired polyphase decimation functionality", + "verilog_code": { + "code_block_0_0": "\\n stage_reg[s][j] = stage_reg[s-1][2*j] + stage_reg[s-1][2*j+1]\\n", + "code_block_0_1": "\\n addr = phase_reg * TAPS + tap_index\\n", + "code_block_0_2": "\\n addr = phase_reg * TAPS + j\\n", + "code_block_1_3": "docs/poly_decimator.md", + "code_block_1_5": "rtl/poly_decimator.sv", + "code_block_1_8": "rtl/shift_register.sv", + "code_block_1_9": "docs/shift_register.md", + "code_block_1_17": "NUM_STAGES = $clog2(NUM_INPUTS)", + "code_block_1_19": "DATA_WIDTH + $clog2(NUM_INPUTS)", + "code_block_1_27": "DATA_WIDTH + $clog2(NUM_INPUTS)", + "code_block_1_33": "DATA_WIDTH + $clog2(NUM_INPUTS)", + "code_block_1_40": "\\n stage_reg[s][j] = stage_reg[s-1][2*j] + stage_reg[s-1][2*j+1]\\n", + "code_block_1_41": "\\n- **Valid Propagation:** \\n The valid flag propagates from one stage to the next. If the previous stage's valid signal (", + "code_block_1_43": "is set high after the addition.\\n\\n### Final Output\\n- **Sum Output:** \\n The final sum is taken from", + "code_block_1_45": ".\\n- **Valid Output:** \\n The final valid signal is available on", + "code_block_1_46": ", which is assigned from", + "code_block_1_47": ".\", 'docs/coeff_ram.md': \"# Coefficient RAM\\n\\nThe", + "code_block_1_48": "module implements a simple synchronous read-only memory that stores a set of coefficients. It should be used in", + "code_block_1_49": "to fetch the filtering coefficients\\n\\nWhen an address is provided at the", + "code_block_1_50": "input, the module outputs the corresponding coefficient stored in its internal memory array (", + "code_block_1_51": ").\\n\\n---\\n\\n## Parameters\\n\\n- **NUM_COEFFS** \\n - **Type:** Integer \\n - **Description:** Specifies the total number of coefficients stored in the RAM. \\n - **Default Value:** 32\\n\\n- **DATA_WIDTH** \\n - **Type:** Integer \\n - **Description:** Specifies the bit width of each coefficient. \\n - **Default Value:** 16\\n\\n---\\n\\n## Interface Table\\n\\n| Signal Name | Direction | Width | Description |\\n|-------------|-----------|---------------------------|-------------------------------------------------------------|\\n|", + "code_block_1_52": "| Input | 1 | Clock signal. |\\n|", + "code_block_1_54": "bits | Address input used to index the coefficient memory array. |\\n|", + "code_block_1_56": "bits | Synchronously outputs the coefficient stored at the address |\\n\\n\\n---\\n\\n## How the Module Works\\n\\n1. **Memory Storage:** \\n The module contains an internal memory array", + "code_block_1_58": "coefficients. Each coefficient is", + "code_block_1_59": "bits wide.\\n\\n2. **Synchronous Read Operation:** \\n On every rising edge of the clock (", + "code_block_1_60": "), the module reads the coefficient at the address specified by", + "code_block_1_62": ".\\n\\n3. **No Write Capability:** \\n This module is designed as a read-only memory block. Coefficient values are typically preloaded. It should be populated with a testbench.\\n\\n---\\n\\n\\n## How to Use This Module in a Polyphase Filter (poly_filter) Design\\n\\nIn a polyphase filter design:\\n- **Coefficient Arrangement:** \\n Coefficients are usually organized into groups corresponding to the filter's phases and taps. For instance, if the polyphase filter has", + "code_block_1_64": "taps per phase, the total number of coefficients is", + "code_block_1_65": ".\\n \\n- **Address Calculation:** \\n The poly_filter computes an address to retrieve the proper coefficient for a given phase and tap index. For example, the address may be calculated as:\\n", + "code_block_1_66": "\\n addr = phase_reg * TAPS + tap_index\\n", + "code_block_1_67": "\\n \\n- **Integration:** \\n The poly_filter instantiates one or more", + "code_block_1_68": "modules (often within a generate loop) to supply coefficients for its multiply-accumulate operations. The coefficient retrieved from", + "code_block_1_69": "is then used to multiply against a sample from the shift register, contributing to the final filter output.\", 'docs/poly_decimator.md': \"# Polyphase Decimator Module\\n\\nThe", + "code_block_1_70": "module takes an input sample stream and produces one decimated output sample every *M* input samples. Instead of generating multiple outputs per input sample (as in interpolation), the decimator collects a full window of samples, decomposes the FIR filtering operation into *M* polyphase branches, and then sums the branch outputs to generate a single filtered, decimated sample. Each branch computes a partial product using a subset of the input window, and an adder tree combines the branch results to form the final output.\\n\\n---\\n\\n## Parameters\\n\\n- **M** \\n **Decimation factor.** \\n Specifies that one output sample is generated for every *M* input samples. \\n **Default Value:** 4\\n\\n- **TAPS** \\n Defines the length of each FIR sub-filter that computes one partial dot\u2013product in every branch. \\n **Default Value:** 8\\n\\n- **COEFF_WIDTH**\\n Width of the filter coefficients used in the multiplication with input samples. \\n **Default Value:** 16\\n\\n- **DATA_WIDTH** \\n Bit width of the input samples that are filtered. \\n **Default Value:** 16\\n\\n- **ACC_WIDTH** \\n The word width computed as:\\n \\n **ACC_WIDTH = DATA_WIDTH + COEFF_WIDTH + $clog2(TAPS)**\\n\\n- **TOTAL_TAPS** \\n Total number of stored samples. \\n Defined as: **TOTAL_TAPS = M * TAPS**\\n\\n---\\n\\n## Interface\\n\\n| **Signal Name** | **Direction** | **Width / Type** | **Description** |\\n|-----------------|---------------|------------------------------|------------------------------------------|\\n|", + "code_block_1_71": "| Input | 1 | Clock signal. |\\n|", + "code_block_1_72": "| Input | 1 | Active-low asynchronous reset. |\\n|", + "code_block_1_74": "bits | The input sample stream to be decimated. |\\n|", + "code_block_1_75": "| Input | 1 | Indicates that", + "code_block_1_77": "| Output | 1 | Ready to accept a new input sample. |\\n|", + "code_block_1_79": "bits | The decimated output sample. |\\n|", + "code_block_1_80": "| Output | 1 | Indicates that", + "code_block_1_81": "is valid. |\\n\\n\\n---\\n\\n## Internal Operation\\n\\nThe polyphase decimator should operate in the following steps:\\n\\n1. **Input Storage:** \\n - An input shift register (of depth **TOTAL_TAPS = M * TAPS**) captures the most recent input samples.\\n - As new samples are accepted (while", + "code_block_1_83": "are high), the register shifts its contents.\\n - A sample counter keeps track of the number of samples received. When the counter reaches *M* (indicating that a complete window has been collected), filtering is triggered.\\n\\n2. **Polyphase Filtering:** \\n - The shift register output is decomposed into *M* branches. Each branch extracts **TAPS** samples from the window using a stride of *M* (starting from a unique offset).\\n - Each branch instantiates a", + "code_block_1_84": "submodule. The branch's fixed phase (given by its index) is used to fetch the corresponding coefficients from coefficient RAM.\\n - In each branch, the", + "code_block_1_85": "multiplies its sample vector by the set of coefficients and computes a dot\u2013product, outputting a partial result along with a valid signal.\\n\\n3. **Result Summation and Output:** \\n - A reduction is performed to ensure that all the *M* branches have produced valid results.\\n - An adder tree will collect the *M* branch outputs, summing them to form the final decimated output sample.\\n - The final sample is registered and presented on the", + "code_block_1_87": "is asserted to indicate its validity.\\n - The FSM controlling the decimator will be operating in two primary states:\\n - **ACCUMULATE:** Continuously accepts input samples, incrementing the sample counter until *M* samples are collected.\\n - **OUTPUT:** Once a complete window is received and all branch outputs are valid, the filtered output is computed, and the decimated sample is released. The counter is reset afterwards.\\n\\n---\\n\\n## Submodule Integration\\n\\n### Shift Register\\n\\n- **Purpose:** \\nStores the most recent **TOTAL_TAPS** input samples so that each decimation window is complete.\\n- **Integration:** \\nThe instance", + "code_block_1_88": "should be implemented as a standard shift register whose depth is parameterized by **TOTAL_TAPS**. It provides an array output (", + "code_block_1_89": ") and a corresponding valid signal (", + "code_block_1_90": ").\\n\\n### Polyphase Filter\\n\\n- **Purpose:** \\nEach", + "code_block_1_91": "submodule instantiated performs filtering on one polyphase branch. It registers the branch's sample vector, fetches corresponding coefficients using a computed address (based on its phase), multiplies the samples by the coefficients, and sums the products.\\n- **Integration:** \\nA generate block should be used to instantiate *M* branches, each with:\\n- A dedicated sub-array (", + "code_block_1_92": ") of **TAPS** samples extracted from the shift register.\\n- A fixed phase number corresponding to its branch index (used to fetch the proper coefficient set).\\n- An output (", + "code_block_1_94": ").\\n\\n### Adder Tree\\n\\n- **Purpose:** \\nCombines the outputs from the *M* polyphase branches to produce a single decimated output sample.\\n- **Integration:** \\nThe", + "code_block_1_95": "module is shared across the design. It accepts the vector of branch outputs and performs a hierarchical sum (with the output width growing by", + "code_block_1_96": "bits) to produce the final filtered result.\\n\\n\", 'docs/poly_filter.md': '# Polyphase Filter Module\\n\\nThe", + "code_block_1_97": "module performs the multiply-accumulate (MAC) operations required in a polyphase filter structure. It takes as inputs:\\n- A **sample buffer** (from a shift register) containing the history of input samples.\\n- A **phase selection** signal that determines which group of filter coefficients to use.\\n- A **valid_in** flag indicating that new input data is available.\\n\\nThe module operates in four main stages:\\n\\n1. **Stage 0: Input Registration** \\n The incoming sample buffer and the phase signal are registered into internal registers (", + "code_block_1_100": ") is generated when the input data is valid.\\n\\n2. **Stage 1: Coefficient Fetch** \\n For each tap, a coefficient is fetched from an instance of the **coeff_ram** module.\\n\\n3. **Stage 2: Multiplication** \\n Each registered sample is multiplied by its corresponding coefficient to produce a set of products.\\n\\n4. **Stage 3: Summation** \\n The products are summed using a pipelined **adder_tree** module. The output of the adder tree is a single sum representing the filtered result.\\n\\n5. **Stage 4: Output Registration** \\n The final sum is registered and output along with a valid flag, indicating that the filter output is ready.\\n\\n---\\n\\n## Interface Table\\n\\n| Signal Name | Direction | Width | Description |\\n|-----------------|-----------|-------------------------------------------------------|---------------------------------------------------------------------|\\n|", + "code_block_1_101": "| Input | 1 | Clock signal |\\n|", + "code_block_1_102": "| Input | 1 | Active-low asynchronous reset |\\n|", + "code_block_1_103": "| Input | Array of", + "code_block_1_105": "bits wide | Input sample history, from a shift register |\\n|", + "code_block_1_106": "| Input | 1 | Valid flag for the sample_buffer. |\\n|", + "code_block_1_108": "bits | Phase selection signal used to choose the correct coefficient group |\\n|", + "code_block_1_110": "| Final filter output |\\n|", + "code_block_1_111": "| Output | 1 | Valid flag indicating that the output on", + "code_block_1_112": "|\\n\\n\\n---\\n\\n## Submodule Integration\\n\\n### Coefficient RAM (coeff_ram)\\n\\n- **Purpose:** \\n The **coeff_ram** module stores filter coefficients. In the poly_filter, a generate block named", + "code_block_1_114": "instance per tap.\\n \\n- **Operation:** \\n For each tap (index", + "code_block_1_115": "), the coefficient RAM is accessed with an address computed as:\\n", + "code_block_1_116": "\\n addr = phase_reg * TAPS + j\\n", + "code_block_1_117": "\\n This fetches the coefficient corresponding to the current phase and tap.\\n \\n- **Integration:** \\n The output of each coefficient RAM instance is assigned to an array (", + "code_block_1_118": "), which is later used in the multiplication stage.\\n\\n### Adder Tree (adder_tree)\\n\\n- **Purpose:** \\n The **adder_tree** module sums an array of products obtained from multiplying the registered samples and the fetched coefficients.\\n \\n- **Operation:** \\n The multiplication results are stored in the", + "code_block_1_119": "array. The adder_tree uses a pipelined structure where the number of values is halved at each stage until a single summed value is produced.\\n \\n- **Integration:** \\n The adder_tree is instantiated with the parameters:\\n -", + "code_block_1_121": "\\n \\n Its output is assigned to the final filter result (", + "code_block_1_122": "), and a valid flag (", + "code_block_1_123": ") indicates when the summed result is valid.\\n\\n---\\n\\n## Detailed Operation Flow\\n\\n1. **Stage 0 \u2013 Input Registration:** \\n - Registers each element of", + "code_block_1_125": ".\\n - Registers the", + "code_block_1_129": "is high.\\n\\n2. **Stage 1 \u2013 Coefficient Fetch:** \\n - For each tap", + "code_block_1_130": ", calculates the coefficient address:", + "code_block_1_132": "to retrieve the coefficient at the computed address.\\n - Outputs are stored in the", + "code_block_1_133": "array.\\n\\n3. **Stage 2 \u2013 Multiplication:** \\n - For each tap", + "code_block_1_137": ".\\n\\n4. **Stage 3 \u2013 Summation via Adder Tree:** \\n - The", + "code_block_1_138": "array is input to the adder_tree module.\\n - The adder_tree computes the sum of all products.\\n - The final sum is available at", + "code_block_1_139": "and is accompanied by a valid signal (", + "code_block_1_140": ").\\n\\n5. **Stage 4 \u2013 Output Registration:** \\n - The", + "code_block_1_141": "is registered and assigned to", + "code_block_1_142": ".\\n - The output valid flag", + "code_block_1_144": ".', 'docs/shift_register.md': '## Overview\\n\\nThe", + "code_block_1_145": "module captures a stream of data samples into an internal register array. When a new sample is loaded (when the", + "code_block_1_146": "signal is asserted), the module inserts the new sample at the beginning of the register array (index 0) and shifts the previous samples down the chain. The module also provides a valid flag (", + "code_block_1_147": ") that indicates when new data has been loaded into the register array.\\n\\n---\\n\\n## Parameters\\n\\n- **TAPS** \\n **Description:** Specifies the number of storage elements (or \"taps\") in the shift register. \\n **Default Value:** 32\\n\\n- **DATA_WIDTH** \\n **Description:** Specifies the bit width of each data sample stored in the shift register. \\n **Default Value:** 16\\n\\n---\\n\\n## Interface\\n\\n### Interface Table\\n\\n| Signal Name | Direction | Width | Description |\\n|----------------|-----------|-----------------------------------------|--------------------------------------------------------------------------------------------------------------------------|\\n|", + "code_block_1_148": "| Input | 1 | Clock signal. The module updates its registers on the rising edge of this clock. |\\n|", + "code_block_1_149": "| Input | 1 | Active-low asynchronous reset. When low, all stored samples are reset to 0. |\\n|", + "code_block_1_150": "| Input | 1 | Load enable signal. When high, the module loads a new sample and shifts the existing data. |\\n|", + "code_block_1_152": "bits | The new data sample to be inserted into the shift register at index 0 when", + "code_block_1_153": "is asserted. |\\n|", + "code_block_1_154": "| Output | Array of", + "code_block_1_156": "| Current content of the shift register;", + "code_block_1_157": "is the most recent sample,", + "code_block_1_158": "is the oldest sample. |\\n|", + "code_block_1_159": "| Output | 1 | Valid flag that is asserted for one clock cycle when new data is loaded into the shift register. |\\n\\n\\n---\\n\\n## Internal Operation\\n\\n1. **Asynchronous Reset:** \\n - When", + "code_block_1_160": "is deasserted (set to 0), all internal register elements are reset to 0 and the valid flag (", + "code_block_1_161": ") is cleared.\\n\\n2. **Loading a New Sample:** \\n - On the rising edge of the", + "code_block_1_163": "signal is asserted:\\n - The new sample from", + "code_block_1_164": "is loaded into the first register (", + "code_block_1_165": ").\\n - All previous samples in the register array are shifted down by one index.\\n - The valid flag (", + "code_block_1_167": "for one clock cycle to indicate that new data is available.\\n \\n3. **No Load Condition:** \\n - When", + "code_block_1_168": "is not asserted, the internal registers retain their current values, and the valid flag remains at 0.\\n\\n4. **Output Assignment:** \\n - The internal register array (", + "code_block_1_169": ") is continuously assigned to the output array (", + "code_block_2_0": "module `poly_decimator`. The `poly_decimator` is a top-module and it must integrate a number of provided files. The detailed specification of `poly_decimator` is provided in the document `docs/poly_decimator.md`.\n\n## Integration Instructions\n- The **`poly_decimator`** module, that should be defined in `rtl/poly_decimator.sv`, must serve as the top-level design. It is responsible for handling the overall decimation operation of M samples.\n\nYou are also provided with a library of pre-designed modules that must be integrated into the target module. The library modules are:\n\n- **adder_tree** \n - **Design File:** `rtl/adder_tree.sv` \n - **Specifications:** `docs/adder_tree.md` \n - **Functionality:** Implements a pipelined adder tree for summing multiple data inputs.\n\n- **shift_register** \n - **Design File:** `rtl/shift_register.sv` \n - **Specifications:** `docs/shift_register.md` \n - **Functionality:** Implements a shift register that stores a history of input samples.\n\n- **coeff_ram** \n - **Design File:** `rtl/coeff_ram.sv` \n - **Specifications:** `docs/coeff_ram.md` \n - **Functionality:** Provides a synchronous memory block for storing filter coefficients.\n\n- **poly_filter** \n - **Design File:** `rtl/poly_filter.sv` \n - **Specifications:** `docs/poly_filter.md` \n - **Functionality:** Implements the filtering operation for each polyphase branch: it multiplies a subset of input samples by the proper coefficients, then sums the products.\n\nEnsure that you fully understand the functionality and interfaces of these modules as described in their specification documents. They must be integrated properly to achieve the desired polyphase decimation functionality\n {'docs/specification.md': None, 'rtl/decoder_data_control_64b66b.sv': None, 'rtl/encoder_control_64b66b.sv': None, 'rtl/encoder_data_64b66b.sv': None, 'rtl/aes128_encrypt.sv': None, 'verif/tb_aes128_enc.sv': None, 'rtl/aes128_decrypt.sv': None, 'rtl/aes128_key_expansion.sv': None, 'rtl/inv_sbox.sv': None, 'rtl/sbox.sv': None, 'verif/tb_aes128_dec.sv': None, 'rtl/aes_encrypt.sv': None, 'verif/tb_aes_encrypt.sv': None, 'rtl/aes_decrypt.sv': None, 'rtl/aes_ke.sv': None, 'verif/tb_aes_decrypt.sv': None, 'rtl/aes_dec_top.sv': None, 'rtl/aes_enc_top.sv': None, 'verif/tb_padding_top.sv': None, 'verif/tb_des_enc.sv': None, 'docs/Key_schedule.md': None, 'docs/Permutations.md': None, 'docs/S_box_creation.md': None, 'rtl/S1.sv': None, 'rtl/S2.sv': None, 'rtl/S3.sv': None, 'rtl/S4.sv': None, 'rtl/S5.sv': None, 'rtl/S6.sv': None, 'rtl/S7.sv': None, 'rtl/S8.sv': None, 'rtl/des_enc.sv': None, 'verif/tb_des_dec.sv': None, 'docs/Encryption.md': None, 'rtl/des_dec.sv': None, 'verif/tb_3des_enc.sv': None, 'verif/tb_3des_dec.sv': None, 'docs/min_hamming_distance_finder_spec.md': None, 'rtl/Bit_Difference_Counter.sv': None, 'rtl/Bitwise_Reduction.sv': None, 'rtl/Data_Reduction.sv': None, 'verif/tb_Min_Hamming_Distance_Finder.sv': None, 'docs/specs.md': None, 'rtl/arithmetic_progression_generator.sv': None, 'docs/algorithms.md': None, 'docs/coeff_update_spec.md': None, 'docs/equalizer_spec.md': None, 'docs/error_calc_spec.md': None, 'rtl/coeff_update.sv': None, 'rtl/dynamic_equalizer.sv': None, 'rtl/error_calc.sv': None, 'docs/awgn_spec.md': None, 'docs/equalizer_top_spec.md': None, 'rtl/elevator_control_system.sv': None, 'docs/tx_specification.md': None, 'rtl/ethernet_fifo_cdc.sv': None, 'docs/tx_mac_specification.md': None, 'verif/event_scheduler_tb.sv': None, 'docs/modified_specs.md': None, 'rtl/event_scheduler.sv': None, 'verif/tb_event_scheduler.sv': None, 'rtl/column_selector.sv': None, 'rtl/event_storage.sv': None, 'verif/tb.sv': None, 'rtl/fixed_priority_arbiter.sv': None, 'verif/fixed_priority_arbiter_tb.sv': None, 'docs/Modified_specification.md': None, 'docs/GCD_specification.md': None, 'docs/crypto_accelerator_specification.md': None, 'docs/modular_exponentiation_specification.md': None, 'docs/modular_multiplier_specification.md': None, 'rtl/gcd_controlpath_3.sv': None, 'rtl/gcd_controlpath_4.sv': None, 'rtl/gcd_datapath_5.sv': None, 'rtl/gcd_datapath_6.sv': None, 'rtl/gcd_top_1.sv': None, 'rtl/gcd_top_2.sv': None, 'rtl/modular_exponentiation.sv': None, 'rtl/modular_multiplier.sv': None, 'rtl/lfsr_8bit.sv': None, 'verif/lfsr_8bit_tb.sv': None, 'rtl/bit16_lfsr.sv': None, 'rtl/low_power_ctrl.sv': None, 'rtl/sync_fifo.sv': None, 'verif/tb_low_power_channel.sv': None, 'rtl/cross_domain_sync.sv': None, 'rtl/dsp_input_stage.sv': None, 'rtl/dsp_output_stage.sv': None, 'rtl/lfsr_generator.sv': None, 'rtl/monte_carlo_dsp_monitor_top.sv': None, 'verif/monte_carlo_dsp_monitor_top_tb.sv': None, 'docs/multiplexer_specification.md': None, 'verif/multiplexer_tb.sv': None, 'docs/nbit_swizzling_spec.md': None, 'verif/nbit_swizzling_tb.sv': None, 'docs/nmea_decoder_spec.md': None, 'rtl/nmea_decoder.sv': None, 'verif/nmea_decoder_tb.sv': None, 'docs/fifo.md': None, 'rtl/fifo_memory.sv': None, 'rtl/read_to_write_pointer_sync.sv': None, 'rtl/rptr_empty.sv': None, 'rtl/wptr_full.sv': None, 'rtl/write_to_read_pointer_sync.sv': None, 'docs/spec.md': None, 'verif/async_filo_tb.sv': None, 'docs/axilite_to_pcie_config_module.md': None, 'rtl/axi4lite_to_pcie_cfg_bridge.sv': None, 'rtl/axis_broadcast.sv': None, 'verif/tb_axis_broadcast.sv': None, 'docs/axis_to_uart_tx_specs.md': None, 'docs/uart_rx_to_axis_specs.md': None, 'rtl/barrel_shifter.sv': None, 'verif/barrel_shifter_tb.sv': None, 'rtl/bcd_adder.sv': None, 'rtl/full_adder.sv': None, 'rtl/four_bit_adder.sv': None, 'rtl/search_binary_search_tree.sv': None, 'rtl/delete_node_binary_search_tree.sv': None, 'docs/bst_operations.md': None, 'rtl/binary_search_tree_sort_construct.sv': None, 'docs/Spec.md': None, 'verif/tb_binary_to_gray.sv': None, 'verif/tb_custom_byte_enable_ram.sv': None, 'verif/cache_controller_tb.sv': None, 'rtl/caesar_cipher.sv': None, 'verif/caesar_cipher_tb.sv': None, 'verif/tb_pseudoRandGenerator_ca.sv': None, 'docs/continuous_adder_specification.md': None, 'verif/continuous_adder_tb.sv': None, 'rtl/fifo_buffer.sv': None, 'verif/tb_fifo_buffer.sv': None, 'docs/direct_map_cache_spec.md': None, 'verif/tb_direct_map_cache.sv': None, 'rtl/direct_map_cache.sv': None, 'rtl/dual_port_memory.sv': None, 'rtl/gen_cos_sin_lut.sv': None, 'rtl/phase_lut.sv': None, 'rtl/phase_rotation.sv': None, 'rtl/power4.sv': None, 'rtl/saturation.sv': None, 'rtl/top_phase_rotation.sv': None, 'docs/spec_viterbi.md': None, 'docs/spec_slicer_top.md': None, 'docs/spec_top_phase_rotation.md': None, 'rtl/slicer.sv': None, 'rtl/slicer_top.sv': None, 'docs/swizzler_specification.md': None, 'verif/swizzler_tb.sv': None, 'rtl/swizzler.sv': None, 'docs/sync_serial_communication_tx_rx_spec.md': None, 'verif/sync_serial_communication_tb.sv': None, 'rtl/weight_stationary_pe.sv': None, 'verif/systolic_array_tb.sv': None, 'rtl/thermostat.v': None, 'docs/Traffic_controller.md': None, 'rtl/traffic_light_controller.sv': None, 'docs/Universal_Shift_Register_spec.md': None, 'verif/tb_universal_shift_register.sv': None, 'rtl/universal_shift_register.sv': None, 'docs/spec_conj.md': None, 'docs/spec_cross_correlation.md': None, 'docs/spec_detect_sequence.md': None, 'rtl/adder_2d_layers.sv': None, 'rtl/adder_tree_2d.sv': None, 'rtl/correlate.sv': None, 'rtl/cross_correlation.sv': None, 'docs/valid_modes.md': None, 'docs/words_counting.md': None, 'rtl/detect_sequence.sv': None, 'docs/proc_fsm_spec.md': None, 'docs/adder_tree.md': \"## Adder Tree Design\\n\\nThe `adder_tree` module takes an array of `NUM_INPUTS` data words (each of width `DATA_WIDTH`) and computes their sum using a pipelined adder tree structure. The design is fully pipelined, meaning that at each clock cycle a new sum can be produced after the pipeline is filled.\\n\\nThe addition process is divided into several stages:\\n- **Stage 0:** The input data is registered and sign-extended to ensure proper arithmetic addition.\\n- **Subsequent Stages:** Each stage halves the number of elements by summing adjacent pairs. The number of stages required is calculated as `NUM_STAGES = $clog2(NUM_INPUTS)`.\\n- **Final Stage:** The final sum is available at the output along with a valid flag (`valid_out`) that propagates through the pipeline.\\n\\n---\\n\\n## Parameters\\n\\n- **NUM_INPUTS** \\n **Type:** Integer \\n **Description:** Number of input data words to be summed. \\n **Default Value:** 8\\n\\n- **DATA_WIDTH** \\n **Type:** Integer \\n **Description:** Bit width of each input data word. \\n **Default Value:** 32\\n\\nThe output width is automatically computed as `DATA_WIDTH + $clog2(NUM_INPUTS)` to accommodate the growth in bit width due to the summation of multiple inputs.\\n\\n---\\n\\n## Interface Table\\n\\n| Signal Name | Direction | Width | Description |\\n|-------------|-----------|-------------------------------------------------------------|-----------------------------------------|\\n| `clk` | Input | 1 | Clock signal |\\n| `arst_n` | Input | 1 | Active-low asynchronous reset |\\n| `valid_in` | Input | 1 | Valid signal for the input data |\\n| `data_in` | Input | Array of `NUM_INPUTS` elements, each `DATA_WIDTH` bits wide | Array of input data words to be summed. |\\n| `sum_out` | Output | `DATA_WIDTH + $clog2(NUM_INPUTS)` bits | The computed sum of the data |\\n| `valid_out` | Output | 1 | Valid signal for the output sum |\\n\\n\\n---\\n\\n## Detailed Operation\\n\\n### Stage 0: Input Registration\\n- **Function:** \\n On the rising edge of `clk`, if `valid_in` is asserted, each input word from `data_in` is registered into the first stage of the pipeline (`stage_reg[0]`). \\n- **Sign Extension:** \\n Each input is sign-extended to a width of `DATA_WIDTH + $clog2(NUM_INPUTS)` bits. This ensures that when negative numbers are involved, the additions are computed correctly.\\n- **Valid Signal:** \\n If `valid_in` is high, `valid_stage[0]` is set to `1` to indicate that the first stage has valid data.\\n\\n### Subsequent Pipeline Stages\\n- **Function:** \\n A generate block creates `NUM_STAGES` pipeline stages. In each stage, the number of data words is halved by adding pairs from the previous stage. \\n- **Computation:** \\n For stage `s`, there are `NUM_INPUTS >> s` elements. Each element is computed as: \\n ```\\n stage_reg[s][j] = stage_reg[s-1][2*j] + stage_reg[s-1][2*j+1]\\n ```\\n- **Valid Propagation:** \\n The valid flag propagates from one stage to the next. If the previous stage's valid signal (`valid_stage[s-1]`) is high, then `valid_stage[s]` is set high after the addition.\\n\\n### Final Output\\n- **Sum Output:** \\n The final sum is taken from `stage_reg[NUM_STAGES][0]` and assigned to `sum_out`.\\n- **Valid Output:** \\n The final valid signal is available on `valid_out`, which is assigned from `valid_stage[NUM_STAGES]`.\", 'docs/coeff_ram.md': \"# Coefficient RAM\\n\\nThe `coeff_ram` module implements a simple synchronous read-only memory that stores a set of coefficients. It should be used in `polyphase filtering` to fetch the filtering coefficients\\n\\nWhen an address is provided at the `addr` input, the module outputs the corresponding coefficient stored in its internal memory array (`mem`).\\n\\n---\\n\\n## Parameters\\n\\n- **NUM_COEFFS** \\n - **Type:** Integer \\n - **Description:** Specifies the total number of coefficients stored in the RAM. \\n - **Default Value:** 32\\n\\n- **DATA_WIDTH** \\n - **Type:** Integer \\n - **Description:** Specifies the bit width of each coefficient. \\n - **Default Value:** 16\\n\\n---\\n\\n## Interface Table\\n\\n| Signal Name | Direction | Width | Description |\\n|-------------|-----------|---------------------------|-------------------------------------------------------------|\\n| `clk` | Input | 1 | Clock signal. |\\n| `addr` | Input | `$clog2(NUM_COEFFS)` bits | Address input used to index the coefficient memory array. |\\n| `data_out` | Output | `DATA_WIDTH` bits | Synchronously outputs the coefficient stored at the address |\\n\\n\\n---\\n\\n## How the Module Works\\n\\n1. **Memory Storage:** \\n The module contains an internal memory array `mem` that holds `NUM_COEFFS` coefficients. Each coefficient is `DATA_WIDTH` bits wide.\\n\\n2. **Synchronous Read Operation:** \\n On every rising edge of the clock (`clk`), the module reads the coefficient at the address specified by `addr` and outputs it on `data_out`.\\n\\n3. **No Write Capability:** \\n This module is designed as a read-only memory block. Coefficient values are typically preloaded. It should be populated with a testbench.\\n\\n---\\n\\n\\n## How to Use This Module in a Polyphase Filter (poly_filter) Design\\n\\nIn a polyphase filter design:\\n- **Coefficient Arrangement:** \\n Coefficients are usually organized into groups corresponding to the filter's phases and taps. For instance, if the polyphase filter has `N` phases and `TAPS` taps per phase, the total number of coefficients is `N * TAPS`.\\n \\n- **Address Calculation:** \\n The poly_filter computes an address to retrieve the proper coefficient for a given phase and tap index. For example, the address may be calculated as:\\n ```\\n addr = phase_reg * TAPS + tap_index\\n ```\\n \\n- **Integration:** \\n The poly_filter instantiates one or more `coeff_ram` modules (often within a generate loop) to supply coefficients for its multiply-accumulate operations. The coefficient retrieved from `coeff_ram` is then used to multiply against a sample from the shift register, contributing to the final filter output.\", 'docs/poly_decimator.md': \"# Polyphase Decimator Module\\n\\nThe `poly_decimator` module takes an input sample stream and produces one decimated output sample every *M* input samples. Instead of generating multiple outputs per input sample (as in interpolation), the decimator collects a full window of samples, decomposes the FIR filtering operation into *M* polyphase branches, and then sums the branch outputs to generate a single filtered, decimated sample. Each branch computes a partial product using a subset of the input window, and an adder tree combines the branch results to form the final output.\\n\\n---\\n\\n## Parameters\\n\\n- **M** \\n **Decimation factor.** \\n Specifies that one output sample is generated for every *M* input samples. \\n **Default Value:** 4\\n\\n- **TAPS** \\n Defines the length of each FIR sub-filter that computes one partial dot\u2013product in every branch. \\n **Default Value:** 8\\n\\n- **COEFF_WIDTH**\\n Width of the filter coefficients used in the multiplication with input samples. \\n **Default Value:** 16\\n\\n- **DATA_WIDTH** \\n Bit width of the input samples that are filtered. \\n **Default Value:** 16\\n\\n- **ACC_WIDTH** \\n The word width computed as:\\n \\n **ACC_WIDTH = DATA_WIDTH + COEFF_WIDTH + $clog2(TAPS)**\\n\\n- **TOTAL_TAPS** \\n Total number of stored samples. \\n Defined as: **TOTAL_TAPS = M * TAPS**\\n\\n---\\n\\n## Interface\\n\\n| **Signal Name** | **Direction** | **Width / Type** | **Description** |\\n|-----------------|---------------|------------------------------|------------------------------------------|\\n| `clk` | Input | 1 | Clock signal. |\\n| `arst_n` | Input | 1 | Active-low asynchronous reset. |\\n| `in_sample` | Input | `DATA_WIDTH` bits | The input sample stream to be decimated. |\\n| `in_valid` | Input | 1 | Indicates that `in_sample` is valid. |\\n| `in_ready` | Output | 1 | Ready to accept a new input sample. |\\n| `out_sample` | Output | `ACC_WIDTH + $clog2(M)` bits | The decimated output sample. |\\n| `out_valid` | Output | 1 | Indicates that `out_sample` is valid. |\\n\\n\\n---\\n\\n## Internal Operation\\n\\nThe polyphase decimator should operate in the following steps:\\n\\n1. **Input Storage:** \\n - An input shift register (of depth **TOTAL_TAPS = M * TAPS**) captures the most recent input samples.\\n - As new samples are accepted (while `in_valid` and `in_ready` are high), the register shifts its contents.\\n - A sample counter keeps track of the number of samples received. When the counter reaches *M* (indicating that a complete window has been collected), filtering is triggered.\\n\\n2. **Polyphase Filtering:** \\n - The shift register output is decomposed into *M* branches. Each branch extracts **TAPS** samples from the window using a stride of *M* (starting from a unique offset).\\n - Each branch instantiates a `poly_filter` submodule. The branch's fixed phase (given by its index) is used to fetch the corresponding coefficients from coefficient RAM.\\n - In each branch, the `poly_filter` multiplies its sample vector by the set of coefficients and computes a dot\u2013product, outputting a partial result along with a valid signal.\\n\\n3. **Result Summation and Output:** \\n - A reduction is performed to ensure that all the *M* branches have produced valid results.\\n - An adder tree will collect the *M* branch outputs, summing them to form the final decimated output sample.\\n - The final sample is registered and presented on the `out_sample` output, while `out_valid` is asserted to indicate its validity.\\n - The FSM controlling the decimator will be operating in two primary states:\\n - **ACCUMULATE:** Continuously accepts input samples, incrementing the sample counter until *M* samples are collected.\\n - **OUTPUT:** Once a complete window is received and all branch outputs are valid, the filtered output is computed, and the decimated sample is released. The counter is reset afterwards.\\n\\n---\\n\\n## Submodule Integration\\n\\n### Shift Register\\n\\n- **Purpose:** \\nStores the most recent **TOTAL_TAPS** input samples so that each decimation window is complete.\\n- **Integration:** \\nThe instance `u_shift_reg_decim` should be implemented as a standard shift register whose depth is parameterized by **TOTAL_TAPS**. It provides an array output (`shift_data`) and a corresponding valid signal (`shift_data_val`).\\n\\n### Polyphase Filter\\n\\n- **Purpose:** \\nEach `poly_filter` submodule instantiated performs filtering on one polyphase branch. It registers the branch's sample vector, fetches corresponding coefficients using a computed address (based on its phase), multiplies the samples by the coefficients, and sums the products.\\n- **Integration:** \\nA generate block should be used to instantiate *M* branches, each with:\\n- A dedicated sub-array (`branch_samples`) of **TAPS** samples extracted from the shift register.\\n- A fixed phase number corresponding to its branch index (used to fetch the proper coefficient set).\\n- An output (`branch_out`) and a valid flag (`branch_valid`).\\n\\n### Adder Tree\\n\\n- **Purpose:** \\nCombines the outputs from the *M* polyphase branches to produce a single decimated output sample.\\n- **Integration:** \\nThe `adder_tree` module is shared across the design. It accepts the vector of branch outputs and performs a hierarchical sum (with the output width growing by `$clog2(M)` bits) to produce the final filtered result.\\n\\n\", 'docs/poly_filter.md': '# Polyphase Filter Module\\n\\nThe `poly_filter` module performs the multiply-accumulate (MAC) operations required in a polyphase filter structure. It takes as inputs:\\n- A **sample buffer** (from a shift register) containing the history of input samples.\\n- A **phase selection** signal that determines which group of filter coefficients to use.\\n- A **valid_in** flag indicating that new input data is available.\\n\\nThe module operates in four main stages:\\n\\n1. **Stage 0: Input Registration** \\n The incoming sample buffer and the phase signal are registered into internal registers (`sample_reg` and `phase_reg`). A valid flag (`valid_stage0`) is generated when the input data is valid.\\n\\n2. **Stage 1: Coefficient Fetch** \\n For each tap, a coefficient is fetched from an instance of the **coeff_ram** module.\\n\\n3. **Stage 2: Multiplication** \\n Each registered sample is multiplied by its corresponding coefficient to produce a set of products.\\n\\n4. **Stage 3: Summation** \\n The products are summed using a pipelined **adder_tree** module. The output of the adder tree is a single sum representing the filtered result.\\n\\n5. **Stage 4: Output Registration** \\n The final sum is registered and output along with a valid flag, indicating that the filter output is ready.\\n\\n---\\n\\n## Interface Table\\n\\n| Signal Name | Direction | Width | Description |\\n|-----------------|-----------|-------------------------------------------------------|---------------------------------------------------------------------|\\n| `clk` | Input | 1 | Clock signal |\\n| `arst_n` | Input | 1 | Active-low asynchronous reset |\\n| `sample_buffer` | Input | Array of `TAPS` elements, each `DATA_WIDTH` bits wide | Input sample history, from a shift register |\\n| `valid_in` | Input | 1 | Valid flag for the sample_buffer. |\\n| `phase` | Input | `$clog2(N)` bits | Phase selection signal used to choose the correct coefficient group |\\n| `filter_out` | Output | `ACC_WIDTH` | Final filter output |\\n| `valid` | Output | 1 | Valid flag indicating that the output on `filter_out` |\\n\\n\\n---\\n\\n## Submodule Integration\\n\\n### Coefficient RAM (coeff_ram)\\n\\n- **Purpose:** \\n The **coeff_ram** module stores filter coefficients. In the poly_filter, a generate block named `coeff_fetch` instantiates one `coeff_ram` instance per tap.\\n \\n- **Operation:** \\n For each tap (index `j`), the coefficient RAM is accessed with an address computed as:\\n ```\\n addr = phase_reg * TAPS + j\\n ```\\n This fetches the coefficient corresponding to the current phase and tap.\\n \\n- **Integration:** \\n The output of each coefficient RAM instance is assigned to an array (`coeff[j]`), which is later used in the multiplication stage.\\n\\n### Adder Tree (adder_tree)\\n\\n- **Purpose:** \\n The **adder_tree** module sums an array of products obtained from multiplying the registered samples and the fetched coefficients.\\n \\n- **Operation:** \\n The multiplication results are stored in the `products` array. The adder_tree uses a pipelined structure where the number of values is halved at each stage until a single summed value is produced.\\n \\n- **Integration:** \\n The adder_tree is instantiated with the parameters:\\n - `NUM_INPUTS = TAPS`\\n - `DATA_WIDTH = DATA_WIDTH + COEFF_WIDTH`\\n \\n Its output is assigned to the final filter result (`sum_result`), and a valid flag (`valid_adder`) indicates when the summed result is valid.\\n\\n---\\n\\n## Detailed Operation Flow\\n\\n1. **Stage 0 \u2013 Input Registration:** \\n - Registers each element of `sample_buffer` into `sample_reg`.\\n - Registers the `phase` signal into `phase_reg`.\\n - Generates `valid_stage0` if `valid_in` is high.\\n\\n2. **Stage 1 \u2013 Coefficient Fetch:** \\n - For each tap `j`, calculates the coefficient address: `addr = phase_reg * TAPS + j`.\\n - Instantiates `coeff_ram` to retrieve the coefficient at the computed address.\\n - Outputs are stored in the `coeff` array.\\n\\n3. **Stage 2 \u2013 Multiplication:** \\n - For each tap `j`, multiplies `sample_reg[j]` with `coeff[j]` to obtain `products[j]`.\\n\\n4. **Stage 3 \u2013 Summation via Adder Tree:** \\n - The `products` array is input to the adder_tree module.\\n - The adder_tree computes the sum of all products.\\n - The final sum is available at `sum_result` and is accompanied by a valid signal (`valid_adder`).\\n\\n5. **Stage 4 \u2013 Output Registration:** \\n - The `sum_result` is registered and assigned to `filter_out`.\\n - The output valid flag `valid` is set based on `valid_adder`.', 'docs/shift_register.md': '## Overview\\n\\nThe `shift_register` module captures a stream of data samples into an internal register array. When a new sample is loaded (when the `load` signal is asserted), the module inserts the new sample at the beginning of the register array (index 0) and shifts the previous samples down the chain. The module also provides a valid flag (`data_out_val`) that indicates when new data has been loaded into the register array.\\n\\n---\\n\\n## Parameters\\n\\n- **TAPS** \\n **Description:** Specifies the number of storage elements (or \"taps\") in the shift register. \\n **Default Value:** 32\\n\\n- **DATA_WIDTH** \\n **Description:** Specifies the bit width of each data sample stored in the shift register. \\n **Default Value:** 16\\n\\n---\\n\\n## Interface\\n\\n### Interface Table\\n\\n| Signal Name | Direction | Width | Description |\\n|----------------|-----------|-----------------------------------------|--------------------------------------------------------------------------------------------------------------------------|\\n| `clk` | Input | 1 | Clock signal. The module updates its registers on the rising edge of this clock. |\\n| `arst_n` | Input | 1 | Active-low asynchronous reset. When low, all stored samples are reset to 0. |\\n| `load` | Input | 1 | Load enable signal. When high, the module loads a new sample and shifts the existing data. |\\n| `new_sample` | Input | `DATA_WIDTH` bits | The new data sample to be inserted into the shift register at index 0 when `load` is asserted. |\\n| `data_out` | Output | Array of `DATA_WIDTH` bits, size `TAPS` | Current content of the shift register; `data_out[0]` is the most recent sample, `data_out[TAPS-1]` is the oldest sample. |\\n| `data_out_val` | Output | 1 | Valid flag that is asserted for one clock cycle when new data is loaded into the shift register. |\\n\\n\\n---\\n\\n## Internal Operation\\n\\n1. **Asynchronous Reset:** \\n - When `arst_n` is deasserted (set to 0), all internal register elements are reset to 0 and the valid flag (`data_out_val`) is cleared.\\n\\n2. **Loading a New Sample:** \\n - On the rising edge of the `clk`, if the `load` signal is asserted:\\n - The new sample from `new_sample` is loaded into the first register (`reg_array[0]`).\\n - All previous samples in the register array are shifted down by one index.\\n - The valid flag (`data_out_val`) is set to `1` for one clock cycle to indicate that new data is available.\\n \\n3. **No Load Condition:** \\n - When `load` is not asserted, the internal registers retain their current values, and the valid flag remains at 0.\\n\\n4. **Output Assignment:** \\n - The internal register array (`reg_array`) is continuously assigned to the output array (`data_out`), so the latest sample history is always available at the module outputs.', 'rtl/adder_tree.sv': \"module adder_tree #(\\n parameter NUM_INPUTS = 8,\\n parameter DATA_WIDTH = 32\\n)\\n(\\n input logic clk,\\n input logic arst_n,\\n input logic valid_in,\\n input logic [DATA_WIDTH-1:0] data_in [NUM_INPUTS],\\n output logic [DATA_WIDTH+$clog2(NUM_INPUTS)-1:0] sum_out,\\n output logic valid_out\\n);\\n\\n // Calculate the number of pipeline stages:\\n localparam NUM_STAGES = $clog2(NUM_INPUTS);\\n\\n // Pipeline registers for data and valid signals.\\n logic [DATA_WIDTH+$clog2(NUM_INPUTS)-1:0] stage_reg [0:NUM_STAGES][0:NUM_INPUTS-1];\\n logic valid_stage [0:NUM_STAGES];\\n integer i, s, j;\\n\\n // Stage 0: Register the input data.\\n always_ff @(posedge clk or negedge arst_n) begin\\n if (!arst_n) begin\\n for (i = 0; i < NUM_INPUTS; i = i + 1)\\n stage_reg[0][i] <= '0;\\n valid_stage[0] <= 1'b0;\\n end\\n else if (valid_in) begin\\n for (i = 0; i < NUM_INPUTS; i = i + 1)\\n // Sign extend if needed.\\n stage_reg[0][i] <= {{($clog2(NUM_INPUTS)){data_in[i][DATA_WIDTH-1]}}, data_in[i]};\\n valid_stage[0] <= 1'b1;\\n end \\n else begin\\n valid_stage[0] <= 1'b0;\\n end\\n end\\n\\n // Subsequent stages: each stage halves the number of values.\\n generate\\n for (genvar s = 1; s <= NUM_STAGES; s = s + 1) begin : stage_pipeline\\n localparam int NUM_ELEMS = NUM_INPUTS >> s;\\n always_ff @(posedge clk or negedge arst_n) begin\\n if (!arst_n) begin\\n for (j = 0; j < NUM_ELEMS; j = j + 1)\\n stage_reg[s][j] <= '0;\\n valid_stage[s] <= 1'b0;\\n end\\n else if (valid_stage[s-1]) begin\\n for (j = 0; j < NUM_ELEMS; j = j + 1)\\n stage_reg[s][j] <= stage_reg[s-1][2*j] + stage_reg[s-1][2*j+1];\\n valid_stage[s] <= 1'b1;\\n end\\n else begin\\n valid_stage[s] <= 1'b0;\\n end\\n end\\n end\\n endgenerate\\n\\n assign sum_out = stage_reg[NUM_STAGES][0];\\n assign valid_out = valid_stage[NUM_STAGES];\\n\\nendmodule\", 'rtl/coeff_ram.sv': 'module coeff_ram #(\\n parameter NUM_COEFFS = 32,\\n parameter DATA_WIDTH = 16\\n)\\n(\\n input logic clk,\\n input logic [$clog2(NUM_COEFFS)-1:0] addr,\\n output logic [DATA_WIDTH-1:0] data_out\\n);\\n\\n // Memory array for coefficients.\\n logic [DATA_WIDTH-1:0] mem [0:NUM_COEFFS-1];\\n integer i;\\n\\n // Synchronous read.\\n always_ff @(posedge clk) begin\\n data_out <= mem[addr];\\n end\\n\\nendmodule', 'rtl/poly_filter.sv': \"module poly_filter #(\\n parameter M = 4, // decimation factor\\n parameter TAPS = 8, // Taps per phase\\n parameter COEFF_WIDTH = 16, // Coefficient bit width\\n parameter DATA_WIDTH = 16, // Sample data bit width\\n localparam ACC_WIDTH = DATA_WIDTH + COEFF_WIDTH + $clog2(TAPS)\\n)\\n(\\n input logic clk,\\n input logic arst_n,\\n input logic [DATA_WIDTH-1:0] sample_buffer [0:TAPS-1],\\n input logic valid_in,\\n // The branch's phase number\\n input logic [$clog2(M)-1:0] phase,\\n output logic [ACC_WIDTH-1:0] filter_out,\\n output logic valid\\n);\\n\\n // ---- Stage 0: Register the input sample vector and phase. ----\\n logic [DATA_WIDTH-1:0] sample_reg [0:TAPS-1];\\n logic [$clog2(M)-1:0] phase_reg;\\n logic valid_stage0;\\n integer i;\\n always_ff @(posedge clk or negedge arst_n) begin\\n if (!arst_n) begin\\n for (i = 0; i < TAPS; i = i + 1)\\n sample_reg[i] <= '0;\\n phase_reg <= '0;\\n valid_stage0 <= 1'b0;\\n end\\n else begin\\n if (valid_in) begin\\n for (i = 0; i < TAPS; i = i + 1)\\n sample_reg[i] <= sample_buffer[i];\\n phase_reg <= phase;\\n valid_stage0 <= 1'b1;\\n end\\n else begin\\n valid_stage0 <= 1'b0;\\n end\\n end\\n end\\n\\n // ---- Stage 1: Coefficient Fetch ----\\n logic [COEFF_WIDTH-1:0] coeff [0:TAPS-1];\\n genvar j;\\n generate\\n for (j = 0; j < TAPS; j = j + 1) begin : coeff_fetch\\n logic [$clog2(M*TAPS)-1:0] addr;\\n assign addr = phase_reg * TAPS + j;\\n coeff_ram #(\\n .NUM_COEFFS(M*TAPS),\\n .DATA_WIDTH(COEFF_WIDTH)\\n ) u_coeff_ram (\\n .clk (clk),\\n .addr (addr),\\n .data_out(coeff[j])\\n );\\n end\\n endgenerate\\n\\n logic valid_stage1;\\n always_ff @(posedge clk or negedge arst_n) begin\\n if (!arst_n)\\n valid_stage1 <= 1'b0;\\n else\\n valid_stage1 <= valid_stage0;\\n end\\n\\n // ---- Stage 2: Multiply the registered samples with coefficients ----\\n logic [DATA_WIDTH+COEFF_WIDTH-1:0] products [0:TAPS-1];\\n integer k;\\n always_comb begin\\n for (k = 0; k < TAPS; k = k + 1)\\n products[k] = sample_reg[k] * coeff[k];\\n end\\n\\n // ---- Stage 3: Sum the products using the adder_tree ----\\n logic [ACC_WIDTH-1:0] sum_result;\\n logic valid_adder;\\n adder_tree #(\\n .NUM_INPUTS(TAPS),\\n .DATA_WIDTH(DATA_WIDTH+COEFF_WIDTH)\\n ) u_adder_tree_filter (\\n .clk (clk),\\n .arst_n (arst_n),\\n .valid_in (valid_stage1),\\n .data_in (products),\\n .sum_out (sum_result),\\n .valid_out(valid_adder)\\n );\\n\\n // ---- Stage 4: Output Registration ----\\n always_ff @(posedge clk or negedge arst_n) begin\\n if (!arst_n) begin\\n filter_out <= '0;\\n valid <= 1'b0;\\n end\\n else begin\\n filter_out <= sum_result;\\n valid <= valid_adder;\\n end\\n end\\n\\nendmodule\", 'rtl/shift_register.sv': \"module shift_register #(\\n parameter TAPS = 32, // TOTAL_TAPS = N * TAPS\\n parameter DATA_WIDTH = 16\\n)\\n(\\n input logic clk,\\n input logic arst_n,\\n input logic load, // Asserted when a new sample is to be shifted in\\n input logic [DATA_WIDTH-1:0] new_sample,\\n output logic [DATA_WIDTH-1:0] data_out [0:TAPS-1],\\n output logic data_out_val // Indicates that data_out is updated.\\n);\\n\\n // Internal register array for storing samples.\\n logic [DATA_WIDTH-1:0] reg_array [0:TAPS-1];\\n integer i;\\n\\n always_ff @(posedge clk or negedge arst_n) begin\\n if (!arst_n) begin\\n for (i = 0; i < TAPS; i = i + 1)\\n reg_array[i] <= '0;\\n data_out_val <= 1'b0;\\n end\\n else if (load) begin\\n reg_array[0] <= new_sample;\\n for (i = TAPS-1; i > 0; i = i - 1)\\n reg_array[i] <= reg_array[i-1];\\n data_out_val <= 1'b1;\\n end\\n else begin\\n data_out_val <= 1'b0;\\n end\\n end\\n\\n // Continuous assignment of the stored register values to the outputs.\\n generate\\n for (genvar j = 0; j < TAPS; j = j + 1) begin : assign_output\\n assign data_out[j] = reg_array[j];\\n end\\n endgenerate\\n\\nendmodule\", 'docs/prbs_specification.md': None, 'rtl/prbs_gen_check.sv': None, 'rtl/fsm.sv': None, 'verif/fsm_tb.sv': None, 'rtl/CA_1.sv': None, 'rtl/CA_2.sv': None, 'rtl/CA_3.sv': None, 'rtl/CA_4.sv': None, 'rtl/rgb_color_space_conversion.sv': None, 'rtl/APBGlobalHistoryRegister.v': None, 'docs/signed_comparator_specification.md': None, 'verif/signed_comparator_tb.sv': None, 'rtl/sorting_engine.sv': None, 'rtl/brick_sort.sv': None, 'rtl/bubble_sort.sv': None, 'rtl/merge_sort.sv': None, 'rtl/selection_sort.sv': None}", + "rtl/adder_tree.sv": "module adder_tree #(\n parameter NUM_INPUTS = 8,\n parameter DATA_WIDTH = 32\n)\n(\n input logic clk,\n input logic arst_n,\n input logic valid_in,\n input logic [DATA_WIDTH-1:0] data_in [NUM_INPUTS],\n output logic [DATA_WIDTH+$clog2(NUM_INPUTS)-1:0] sum_out,\n output logic valid_out\n);\n\n // Calculate the number of pipeline stages:\n localparam NUM_STAGES = $clog2(NUM_INPUTS);\n\n // Pipeline registers for data and valid signals.\n logic [DATA_WIDTH+$clog2(NUM_INPUTS)-1:0] stage_reg [0:NUM_STAGES][0:NUM_INPUTS-1];\n logic valid_stage [0:NUM_STAGES];\n integer i, s, j;\n\n // Stage 0: Register the input data.\n always_ff @(posedge clk or negedge arst_n) begin\n if (!arst_n) begin\n for (i = 0; i < NUM_INPUTS; i = i + 1)\n stage_reg[0][i] <= '0;\n valid_stage[0] <= 1'b0;\n end\n else if (valid_in) begin\n for (i = 0; i < NUM_INPUTS; i = i + 1)\n // Sign extend if needed.\n stage_reg[0][i] <= {{($clog2(NUM_INPUTS)){data_in[i][DATA_WIDTH-1]}}, data_in[i]};\n valid_stage[0] <= 1'b1;\n end \n else begin\n valid_stage[0] <= 1'b0;\n end\n end\n\n // Subsequent stages: each stage halves the number of values.\n generate\n for (genvar s = 1; s <= NUM_STAGES; s = s + 1) begin : stage_pipeline\n localparam int NUM_ELEMS = NUM_INPUTS >> s;\n always_ff @(posedge clk or negedge arst_n) begin\n if (!arst_n) begin\n for (j = 0; j < NUM_ELEMS; j = j + 1)\n stage_reg[s][j] <= '0;\n valid_stage[s] <= 1'b0;\n end\n else if (valid_stage[s-1]) begin\n for (j = 0; j < NUM_ELEMS; j = j + 1)\n stage_reg[s][j] <= stage_reg[s-1][2*j] + stage_reg[s-1][2*j+1];\n valid_stage[s] <= 1'b1;\n end\n else begin\n valid_stage[s] <= 1'b0;\n end\n end\n end\n endgenerate\n\n assign sum_out = stage_reg[NUM_STAGES][0];\n assign valid_out = valid_stage[NUM_STAGES];\n\nendmodule", + "rtl/coeff_ram.sv": "module coeff_ram #(\n parameter NUM_COEFFS = 32,\n parameter DATA_WIDTH = 16\n)\n(\n input logic clk,\n input logic [$clog2(NUM_COEFFS)-1:0] addr,\n output logic [DATA_WIDTH-1:0] data_out\n);\n\n // Memory array for coefficients.\n logic [DATA_WIDTH-1:0] mem [0:NUM_COEFFS-1];\n integer i;\n\n // Synchronous read.\n always_ff @(posedge clk) begin\n data_out <= mem[addr];\n end\n\nendmodule", + "rtl/poly_filter.sv": "module poly_filter #(\n parameter M = 4, // decimation factor\n parameter TAPS = 8, // Taps per phase\n parameter COEFF_WIDTH = 16, // Coefficient bit width\n parameter DATA_WIDTH = 16, // Sample data bit width\n localparam ACC_WIDTH = DATA_WIDTH + COEFF_WIDTH + $clog2(TAPS)\n)\n(\n input logic clk,\n input logic arst_n,\n input logic [DATA_WIDTH-1:0] sample_buffer [0:TAPS-1],\n input logic valid_in,\n // The branch's phase number\n input logic [$clog2(M)-1:0] phase,\n output logic [ACC_WIDTH-1:0] filter_out,\n output logic valid\n);\n\n // ---- Stage 0: Register the input sample vector and phase. ----\n logic [DATA_WIDTH-1:0] sample_reg [0:TAPS-1];\n logic [$clog2(M)-1:0] phase_reg;\n logic valid_stage0;\n integer i;\n always_ff @(posedge clk or negedge arst_n) begin\n if (!arst_n) begin\n for (i = 0; i < TAPS; i = i + 1)\n sample_reg[i] <= '0;\n phase_reg <= '0;\n valid_stage0 <= 1'b0;\n end\n else begin\n if (valid_in) begin\n for (i = 0; i < TAPS; i = i + 1)\n sample_reg[i] <= sample_buffer[i];\n phase_reg <= phase;\n valid_stage0 <= 1'b1;\n end\n else begin\n valid_stage0 <= 1'b0;\n end\n end\n end\n\n // ---- Stage 1: Coefficient Fetch ----\n logic [COEFF_WIDTH-1:0] coeff [0:TAPS-1];\n genvar j;\n generate\n for (j = 0; j < TAPS; j = j + 1) begin : coeff_fetch\n logic [$clog2(M*TAPS)-1:0] addr;\n assign addr = phase_reg * TAPS + j;\n coeff_ram #(\n .NUM_COEFFS(M*TAPS),\n .DATA_WIDTH(COEFF_WIDTH)\n ) u_coeff_ram (\n .clk (clk),\n .addr (addr),\n .data_out(coeff[j])\n );\n end\n endgenerate\n\n logic valid_stage1;\n always_ff @(posedge clk or negedge arst_n) begin\n if (!arst_n)\n valid_stage1 <= 1'b0;\n else\n valid_stage1 <= valid_stage0;\n end\n\n // ---- Stage 2: Multiply the registered samples with coefficients ----\n logic [DATA_WIDTH+COEFF_WIDTH-1:0] products [0:TAPS-1];\n integer k;\n always_comb begin\n for (k = 0; k < TAPS; k = k + 1)\n products[k] = sample_reg[k] * coeff[k];\n end\n\n // ---- Stage 3: Sum the products using the adder_tree ----\n logic [ACC_WIDTH-1:0] sum_result;\n logic valid_adder;\n adder_tree #(\n .NUM_INPUTS(TAPS),\n .DATA_WIDTH(DATA_WIDTH+COEFF_WIDTH)\n ) u_adder_tree_filter (\n .clk (clk),\n .arst_n (arst_n),\n .valid_in (valid_stage1),\n .data_in (products),\n .sum_out (sum_result),\n .valid_out(valid_adder)\n );\n\n // ---- Stage 4: Output Registration ----\n always_ff @(posedge clk or negedge arst_n) begin\n if (!arst_n) begin\n filter_out <= '0;\n valid <= 1'b0;\n end\n else begin\n filter_out <= sum_result;\n valid <= valid_adder;\n end\n end\n\nendmodule", + "rtl/shift_register.sv": "module shift_register #(\n parameter TAPS = 32, // TOTAL_TAPS = N * TAPS\n parameter DATA_WIDTH = 16\n)\n(\n input logic clk,\n input logic arst_n,\n input logic load, // Asserted when a new sample is to be shifted in\n input logic [DATA_WIDTH-1:0] new_sample,\n output logic [DATA_WIDTH-1:0] data_out [0:TAPS-1],\n output logic data_out_val // Indicates that data_out is updated.\n);\n\n // Internal register array for storing samples.\n logic [DATA_WIDTH-1:0] reg_array [0:TAPS-1];\n integer i;\n\n always_ff @(posedge clk or negedge arst_n) begin\n if (!arst_n) begin\n for (i = 0; i < TAPS; i = i + 1)\n reg_array[i] <= '0;\n data_out_val <= 1'b0;\n end\n else if (load) begin\n reg_array[0] <= new_sample;\n for (i = TAPS-1; i > 0; i = i - 1)\n reg_array[i] <= reg_array[i-1];\n data_out_val <= 1'b1;\n end\n else begin\n data_out_val <= 1'b0;\n end\n end\n\n // Continuous assignment of the stored register values to the outputs.\n generate\n for (genvar j = 0; j < TAPS; j = j + 1) begin : assign_output\n assign data_out[j] = reg_array[j];\n end\n endgenerate\n\nendmodule" + }, + "test_info": { + "test_criteria_2": [ + "be defined in `rtl/poly_decimator.sv`, must serve as the top-level design. it is responsible for handling the overall decimation operation of m samples." + ] + }, + "expected_behavior": [ + "integrate a number of provided files", + "be defined in `rtl/poly_decimator", + "serve as the top-level design", + "be integrated into the target module", + "be integrated properly to achieve the desired polyphase decimation functionality", + "** Implements a pipelined adder tree for summing multiple data inputs.", + "** Implements a shift register that stores a history of input samples.", + "** Provides a synchronous memory block for storing filter coefficients.", + "** Implements the filtering operation for each polyphase branch: it multiplies a subset of input samples by the proper coefficients, then sums the products." + ], + "metadata": { + "categories": [ + "cid005", + "medium" + ], + "domain": "processor", + "complexity": "expert", + "problem_type": "design", + "has_code": true, + "has_tests": true + }, + "full_prompt": "You are required to design a System Verilog module `poly_decimator`. The `poly_decimator` is a top-module and it must integrate a number of provided files. The detailed specification of `poly_decimator` is provided in the document `docs/poly_decimator.md`.\n\n## Integration Instructions\n- The **`poly_decimator`** module, that should be defined in `rtl/poly_decimator.sv`, must serve as the top-level design. It is responsible for handling the overall decimation operation of M samples.\n\nYou are also provided with a library of pre-designed modules that must be integrated into the target module. The library modules are:\n\n- **adder_tree** \n - **Design File:** `rtl/adder_tree.sv` \n - **Specifications:** `docs/adder_tree.md` \n - **Functionality:** Implements a pipelined adder tree for summing multiple data inputs.\n\n- **shift_register** \n - **Design File:** `rtl/shift_register.sv` \n - **Specifications:** `docs/shift_register.md` \n - **Functionality:** Implements a shift register that stores a history of input samples.\n\n- **coeff_ram** \n - **Design File:** `rtl/coeff_ram.sv` \n - **Specifications:** `docs/coeff_ram.md` \n - **Functionality:** Provides a synchronous memory block for storing filter coefficients.\n\n- **poly_filter** \n - **Design File:** `rtl/poly_filter.sv` \n - **Specifications:** `docs/poly_filter.md` \n - **Functionality:** Implements the filtering operation for each polyphase branch: it multiplies a subset of input samples by the proper coefficients, then sums the products.\n\nEnsure that you fully understand the functionality and interfaces of these modules as described in their specification documents. They must be integrated properly to achieve the desired polyphase decimation functionality\n", + "system_message": "You are a language model that has the following file operations available at your disposal:\n - **List files in a directory** by running one of the following commands: \n - `ls`\n - `tree`\n - **Read files** by using:\n - `cat `\n - **Write files** by using:\n - `echo > `\n - **Edit files** by using:\n - `sed -i 's/old_text/new_text/g' `\n - **Compile Verilog** by using `iverilog` such as:\n - `iverilog -o .out -g2012 `\n - **Run Simulation** by using:\n - `vvp .out`\n - **Find current working directory** by using:\n - `pwd`\n\nYou will be given a prompt and your task is to understand it and solve the given issue by using the above-mentioned commands as needed. In the final step, you should create a Linux patch to highlight the necessary file updates to achieve the targeted goal.\n\n You will solve the problem step by step using the following approach of \n - thought (thinking process of the step you're going to take)\n - action (the command you will be running to get more details/context that's helpful to solve the problem)\n - observation (the output from the action you will observe based on which you will take your next step)\n\n The last step will be the final output summary and the patch itself in the following format \n - thought (the summary of what you did and some introduction of the patch file itself)\n - patch (a Linux-based patch that needs to be applied to reach the relevant solution)\n\n The patch file should only be applied to a single file to reach the required solution.", + "raw_context": { + "docs/specification.md": null, + "rtl/decoder_data_control_64b66b.sv": null, + "rtl/encoder_control_64b66b.sv": null, + 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+ "docs/adder_tree.md": "## Adder Tree Design\n\nThe `adder_tree` module takes an array of `NUM_INPUTS` data words (each of width `DATA_WIDTH`) and computes their sum using a pipelined adder tree structure. The design is fully pipelined, meaning that at each clock cycle a new sum can be produced after the pipeline is filled.\n\nThe addition process is divided into several stages:\n- **Stage 0:** The input data is registered and sign-extended to ensure proper arithmetic addition.\n- **Subsequent Stages:** Each stage halves the number of elements by summing adjacent pairs. The number of stages required is calculated as `NUM_STAGES = $clog2(NUM_INPUTS)`.\n- **Final Stage:** The final sum is available at the output along with a valid flag (`valid_out`) that propagates through the pipeline.\n\n---\n\n## Parameters\n\n- **NUM_INPUTS** \n **Type:** Integer \n **Description:** Number of input data words to be summed. \n **Default Value:** 8\n\n- **DATA_WIDTH** \n **Type:** Integer \n **Description:** Bit width of each input data word. \n **Default Value:** 32\n\nThe output width is automatically computed as `DATA_WIDTH + $clog2(NUM_INPUTS)` to accommodate the growth in bit width due to the summation of multiple inputs.\n\n---\n\n## Interface Table\n\n| Signal Name | Direction | Width | Description |\n|-------------|-----------|-------------------------------------------------------------|-----------------------------------------|\n| `clk` | Input | 1 | Clock signal |\n| `arst_n` | Input | 1 | Active-low asynchronous reset |\n| `valid_in` | Input | 1 | Valid signal for the input data |\n| `data_in` | Input | Array of `NUM_INPUTS` elements, each `DATA_WIDTH` bits wide | Array of input data words to be summed. |\n| `sum_out` | Output | `DATA_WIDTH + $clog2(NUM_INPUTS)` bits | The computed sum of the data |\n| `valid_out` | Output | 1 | Valid signal for the output sum |\n\n\n---\n\n## Detailed Operation\n\n### Stage 0: Input Registration\n- **Function:** \n On the rising edge of `clk`, if `valid_in` is asserted, each input word from `data_in` is registered into the first stage of the pipeline (`stage_reg[0]`). \n- **Sign Extension:** \n Each input is sign-extended to a width of `DATA_WIDTH + $clog2(NUM_INPUTS)` bits. This ensures that when negative numbers are involved, the additions are computed correctly.\n- **Valid Signal:** \n If `valid_in` is high, `valid_stage[0]` is set to `1` to indicate that the first stage has valid data.\n\n### Subsequent Pipeline Stages\n- **Function:** \n A generate block creates `NUM_STAGES` pipeline stages. In each stage, the number of data words is halved by adding pairs from the previous stage. \n- **Computation:** \n For stage `s`, there are `NUM_INPUTS >> s` elements. Each element is computed as: \n ```\n stage_reg[s][j] = stage_reg[s-1][2*j] + stage_reg[s-1][2*j+1]\n ```\n- **Valid Propagation:** \n The valid flag propagates from one stage to the next. If the previous stage's valid signal (`valid_stage[s-1]`) is high, then `valid_stage[s]` is set high after the addition.\n\n### Final Output\n- **Sum Output:** \n The final sum is taken from `stage_reg[NUM_STAGES][0]` and assigned to `sum_out`.\n- **Valid Output:** \n The final valid signal is available on `valid_out`, which is assigned from `valid_stage[NUM_STAGES]`.", + "docs/coeff_ram.md": "# Coefficient RAM\n\nThe `coeff_ram` module implements a simple synchronous read-only memory that stores a set of coefficients. It should be used in `polyphase filtering` to fetch the filtering coefficients\n\nWhen an address is provided at the `addr` input, the module outputs the corresponding coefficient stored in its internal memory array (`mem`).\n\n---\n\n## Parameters\n\n- **NUM_COEFFS** \n - **Type:** Integer \n - **Description:** Specifies the total number of coefficients stored in the RAM. \n - **Default Value:** 32\n\n- **DATA_WIDTH** \n - **Type:** Integer \n - **Description:** Specifies the bit width of each coefficient. \n - **Default Value:** 16\n\n---\n\n## Interface Table\n\n| Signal Name | Direction | Width | Description |\n|-------------|-----------|---------------------------|-------------------------------------------------------------|\n| `clk` | Input | 1 | Clock signal. |\n| `addr` | Input | `$clog2(NUM_COEFFS)` bits | Address input used to index the coefficient memory array. |\n| `data_out` | Output | `DATA_WIDTH` bits | Synchronously outputs the coefficient stored at the address |\n\n\n---\n\n## How the Module Works\n\n1. **Memory Storage:** \n The module contains an internal memory array `mem` that holds `NUM_COEFFS` coefficients. Each coefficient is `DATA_WIDTH` bits wide.\n\n2. **Synchronous Read Operation:** \n On every rising edge of the clock (`clk`), the module reads the coefficient at the address specified by `addr` and outputs it on `data_out`.\n\n3. **No Write Capability:** \n This module is designed as a read-only memory block. Coefficient values are typically preloaded. It should be populated with a testbench.\n\n---\n\n\n## How to Use This Module in a Polyphase Filter (poly_filter) Design\n\nIn a polyphase filter design:\n- **Coefficient Arrangement:** \n Coefficients are usually organized into groups corresponding to the filter's phases and taps. For instance, if the polyphase filter has `N` phases and `TAPS` taps per phase, the total number of coefficients is `N * TAPS`.\n \n- **Address Calculation:** \n The poly_filter computes an address to retrieve the proper coefficient for a given phase and tap index. For example, the address may be calculated as:\n ```\n addr = phase_reg * TAPS + tap_index\n ```\n \n- **Integration:** \n The poly_filter instantiates one or more `coeff_ram` modules (often within a generate loop) to supply coefficients for its multiply-accumulate operations. The coefficient retrieved from `coeff_ram` is then used to multiply against a sample from the shift register, contributing to the final filter output.", + "docs/poly_decimator.md": "# Polyphase Decimator Module\n\nThe `poly_decimator` module takes an input sample stream and produces one decimated output sample every *M* input samples. Instead of generating multiple outputs per input sample (as in interpolation), the decimator collects a full window of samples, decomposes the FIR filtering operation into *M* polyphase branches, and then sums the branch outputs to generate a single filtered, decimated sample. Each branch computes a partial product using a subset of the input window, and an adder tree combines the branch results to form the final output.\n\n---\n\n## Parameters\n\n- **M** \n **Decimation factor.** \n Specifies that one output sample is generated for every *M* input samples. \n **Default Value:** 4\n\n- **TAPS** \n Defines the length of each FIR sub-filter that computes one partial dot\u2013product in every branch. \n **Default Value:** 8\n\n- **COEFF_WIDTH**\n Width of the filter coefficients used in the multiplication with input samples. \n **Default Value:** 16\n\n- **DATA_WIDTH** \n Bit width of the input samples that are filtered. \n **Default Value:** 16\n\n- **ACC_WIDTH** \n The word width computed as:\n \n **ACC_WIDTH = DATA_WIDTH + COEFF_WIDTH + $clog2(TAPS)**\n\n- **TOTAL_TAPS** \n Total number of stored samples. \n Defined as: **TOTAL_TAPS = M * TAPS**\n\n---\n\n## Interface\n\n| **Signal Name** | **Direction** | **Width / Type** | **Description** |\n|-----------------|---------------|------------------------------|------------------------------------------|\n| `clk` | Input | 1 | Clock signal. |\n| `arst_n` | Input | 1 | Active-low asynchronous reset. |\n| `in_sample` | Input | `DATA_WIDTH` bits | The input sample stream to be decimated. |\n| `in_valid` | Input | 1 | Indicates that `in_sample` is valid. |\n| `in_ready` | Output | 1 | Ready to accept a new input sample. |\n| `out_sample` | Output | `ACC_WIDTH + $clog2(M)` bits | The decimated output sample. |\n| `out_valid` | Output | 1 | Indicates that `out_sample` is valid. |\n\n\n---\n\n## Internal Operation\n\nThe polyphase decimator should operate in the following steps:\n\n1. **Input Storage:** \n - An input shift register (of depth **TOTAL_TAPS = M * TAPS**) captures the most recent input samples.\n - As new samples are accepted (while `in_valid` and `in_ready` are high), the register shifts its contents.\n - A sample counter keeps track of the number of samples received. When the counter reaches *M* (indicating that a complete window has been collected), filtering is triggered.\n\n2. **Polyphase Filtering:** \n - The shift register output is decomposed into *M* branches. Each branch extracts **TAPS** samples from the window using a stride of *M* (starting from a unique offset).\n - Each branch instantiates a `poly_filter` submodule. The branch's fixed phase (given by its index) is used to fetch the corresponding coefficients from coefficient RAM.\n - In each branch, the `poly_filter` multiplies its sample vector by the set of coefficients and computes a dot\u2013product, outputting a partial result along with a valid signal.\n\n3. **Result Summation and Output:** \n - A reduction is performed to ensure that all the *M* branches have produced valid results.\n - An adder tree will collect the *M* branch outputs, summing them to form the final decimated output sample.\n - The final sample is registered and presented on the `out_sample` output, while `out_valid` is asserted to indicate its validity.\n - The FSM controlling the decimator will be operating in two primary states:\n - **ACCUMULATE:** Continuously accepts input samples, incrementing the sample counter until *M* samples are collected.\n - **OUTPUT:** Once a complete window is received and all branch outputs are valid, the filtered output is computed, and the decimated sample is released. The counter is reset afterwards.\n\n---\n\n## Submodule Integration\n\n### Shift Register\n\n- **Purpose:** \nStores the most recent **TOTAL_TAPS** input samples so that each decimation window is complete.\n- **Integration:** \nThe instance `u_shift_reg_decim` should be implemented as a standard shift register whose depth is parameterized by **TOTAL_TAPS**. It provides an array output (`shift_data`) and a corresponding valid signal (`shift_data_val`).\n\n### Polyphase Filter\n\n- **Purpose:** \nEach `poly_filter` submodule instantiated performs filtering on one polyphase branch. It registers the branch's sample vector, fetches corresponding coefficients using a computed address (based on its phase), multiplies the samples by the coefficients, and sums the products.\n- **Integration:** \nA generate block should be used to instantiate *M* branches, each with:\n- A dedicated sub-array (`branch_samples`) of **TAPS** samples extracted from the shift register.\n- A fixed phase number corresponding to its branch index (used to fetch the proper coefficient set).\n- An output (`branch_out`) and a valid flag (`branch_valid`).\n\n### Adder Tree\n\n- **Purpose:** \nCombines the outputs from the *M* polyphase branches to produce a single decimated output sample.\n- **Integration:** \nThe `adder_tree` module is shared across the design. It accepts the vector of branch outputs and performs a hierarchical sum (with the output width growing by `$clog2(M)` bits) to produce the final filtered result.\n\n", + "docs/poly_filter.md": "# Polyphase Filter Module\n\nThe `poly_filter` module performs the multiply-accumulate (MAC) operations required in a polyphase filter structure. It takes as inputs:\n- A **sample buffer** (from a shift register) containing the history of input samples.\n- A **phase selection** signal that determines which group of filter coefficients to use.\n- A **valid_in** flag indicating that new input data is available.\n\nThe module operates in four main stages:\n\n1. **Stage 0: Input Registration** \n The incoming sample buffer and the phase signal are registered into internal registers (`sample_reg` and `phase_reg`). A valid flag (`valid_stage0`) is generated when the input data is valid.\n\n2. **Stage 1: Coefficient Fetch** \n For each tap, a coefficient is fetched from an instance of the **coeff_ram** module.\n\n3. **Stage 2: Multiplication** \n Each registered sample is multiplied by its corresponding coefficient to produce a set of products.\n\n4. **Stage 3: Summation** \n The products are summed using a pipelined **adder_tree** module. The output of the adder tree is a single sum representing the filtered result.\n\n5. **Stage 4: Output Registration** \n The final sum is registered and output along with a valid flag, indicating that the filter output is ready.\n\n---\n\n## Interface Table\n\n| Signal Name | Direction | Width | Description |\n|-----------------|-----------|-------------------------------------------------------|---------------------------------------------------------------------|\n| `clk` | Input | 1 | Clock signal |\n| `arst_n` | Input | 1 | Active-low asynchronous reset |\n| `sample_buffer` | Input | Array of `TAPS` elements, each `DATA_WIDTH` bits wide | Input sample history, from a shift register |\n| `valid_in` | Input | 1 | Valid flag for the sample_buffer. |\n| `phase` | Input | `$clog2(N)` bits | Phase selection signal used to choose the correct coefficient group |\n| `filter_out` | Output | `ACC_WIDTH` | Final filter output |\n| `valid` | Output | 1 | Valid flag indicating that the output on `filter_out` |\n\n\n---\n\n## Submodule Integration\n\n### Coefficient RAM (coeff_ram)\n\n- **Purpose:** \n The **coeff_ram** module stores filter coefficients. In the poly_filter, a generate block named `coeff_fetch` instantiates one `coeff_ram` instance per tap.\n \n- **Operation:** \n For each tap (index `j`), the coefficient RAM is accessed with an address computed as:\n ```\n addr = phase_reg * TAPS + j\n ```\n This fetches the coefficient corresponding to the current phase and tap.\n \n- **Integration:** \n The output of each coefficient RAM instance is assigned to an array (`coeff[j]`), which is later used in the multiplication stage.\n\n### Adder Tree (adder_tree)\n\n- **Purpose:** \n The **adder_tree** module sums an array of products obtained from multiplying the registered samples and the fetched coefficients.\n \n- **Operation:** \n The multiplication results are stored in the `products` array. The adder_tree uses a pipelined structure where the number of values is halved at each stage until a single summed value is produced.\n \n- **Integration:** \n The adder_tree is instantiated with the parameters:\n - `NUM_INPUTS = TAPS`\n - `DATA_WIDTH = DATA_WIDTH + COEFF_WIDTH`\n \n Its output is assigned to the final filter result (`sum_result`), and a valid flag (`valid_adder`) indicates when the summed result is valid.\n\n---\n\n## Detailed Operation Flow\n\n1. **Stage 0 \u2013 Input Registration:** \n - Registers each element of `sample_buffer` into `sample_reg`.\n - Registers the `phase` signal into `phase_reg`.\n - Generates `valid_stage0` if `valid_in` is high.\n\n2. **Stage 1 \u2013 Coefficient Fetch:** \n - For each tap `j`, calculates the coefficient address: `addr = phase_reg * TAPS + j`.\n - Instantiates `coeff_ram` to retrieve the coefficient at the computed address.\n - Outputs are stored in the `coeff` array.\n\n3. **Stage 2 \u2013 Multiplication:** \n - For each tap `j`, multiplies `sample_reg[j]` with `coeff[j]` to obtain `products[j]`.\n\n4. **Stage 3 \u2013 Summation via Adder Tree:** \n - The `products` array is input to the adder_tree module.\n - The adder_tree computes the sum of all products.\n - The final sum is available at `sum_result` and is accompanied by a valid signal (`valid_adder`).\n\n5. **Stage 4 \u2013 Output Registration:** \n - The `sum_result` is registered and assigned to `filter_out`.\n - The output valid flag `valid` is set based on `valid_adder`.", + "docs/shift_register.md": "## Overview\n\nThe `shift_register` module captures a stream of data samples into an internal register array. When a new sample is loaded (when the `load` signal is asserted), the module inserts the new sample at the beginning of the register array (index 0) and shifts the previous samples down the chain. The module also provides a valid flag (`data_out_val`) that indicates when new data has been loaded into the register array.\n\n---\n\n## Parameters\n\n- **TAPS** \n **Description:** Specifies the number of storage elements (or \"taps\") in the shift register. \n **Default Value:** 32\n\n- **DATA_WIDTH** \n **Description:** Specifies the bit width of each data sample stored in the shift register. \n **Default Value:** 16\n\n---\n\n## Interface\n\n### Interface Table\n\n| Signal Name | Direction | Width | Description |\n|----------------|-----------|-----------------------------------------|--------------------------------------------------------------------------------------------------------------------------|\n| `clk` | Input | 1 | Clock signal. The module updates its registers on the rising edge of this clock. |\n| `arst_n` | Input | 1 | Active-low asynchronous reset. When low, all stored samples are reset to 0. |\n| `load` | Input | 1 | Load enable signal. When high, the module loads a new sample and shifts the existing data. |\n| `new_sample` | Input | `DATA_WIDTH` bits | The new data sample to be inserted into the shift register at index 0 when `load` is asserted. |\n| `data_out` | Output | Array of `DATA_WIDTH` bits, size `TAPS` | Current content of the shift register; `data_out[0]` is the most recent sample, `data_out[TAPS-1]` is the oldest sample. |\n| `data_out_val` | Output | 1 | Valid flag that is asserted for one clock cycle when new data is loaded into the shift register. |\n\n\n---\n\n## Internal Operation\n\n1. **Asynchronous Reset:** \n - When `arst_n` is deasserted (set to 0), all internal register elements are reset to 0 and the valid flag (`data_out_val`) is cleared.\n\n2. **Loading a New Sample:** \n - On the rising edge of the `clk`, if the `load` signal is asserted:\n - The new sample from `new_sample` is loaded into the first register (`reg_array[0]`).\n - All previous samples in the register array are shifted down by one index.\n - The valid flag (`data_out_val`) is set to `1` for one clock cycle to indicate that new data is available.\n \n3. **No Load Condition:** \n - When `load` is not asserted, the internal registers retain their current values, and the valid flag remains at 0.\n\n4. **Output Assignment:** \n - The internal register array (`reg_array`) is continuously assigned to the output array (`data_out`), so the latest sample history is always available at the module outputs.", + "rtl/adder_tree.sv": "module adder_tree #(\n parameter NUM_INPUTS = 8,\n parameter DATA_WIDTH = 32\n)\n(\n input logic clk,\n input logic arst_n,\n input logic valid_in,\n input logic [DATA_WIDTH-1:0] data_in [NUM_INPUTS],\n output logic [DATA_WIDTH+$clog2(NUM_INPUTS)-1:0] sum_out,\n output logic valid_out\n);\n\n // Calculate the number of pipeline stages:\n localparam NUM_STAGES = $clog2(NUM_INPUTS);\n\n // Pipeline registers for data and valid signals.\n logic [DATA_WIDTH+$clog2(NUM_INPUTS)-1:0] stage_reg [0:NUM_STAGES][0:NUM_INPUTS-1];\n logic valid_stage [0:NUM_STAGES];\n integer i, s, j;\n\n // Stage 0: Register the input data.\n always_ff @(posedge clk or negedge arst_n) begin\n if (!arst_n) begin\n for (i = 0; i < NUM_INPUTS; i = i + 1)\n stage_reg[0][i] <= '0;\n valid_stage[0] <= 1'b0;\n end\n else if (valid_in) begin\n for (i = 0; i < NUM_INPUTS; i = i + 1)\n // Sign extend if needed.\n stage_reg[0][i] <= {{($clog2(NUM_INPUTS)){data_in[i][DATA_WIDTH-1]}}, data_in[i]};\n valid_stage[0] <= 1'b1;\n end \n else begin\n valid_stage[0] <= 1'b0;\n end\n end\n\n // Subsequent stages: each stage halves the number of values.\n generate\n for (genvar s = 1; s <= NUM_STAGES; s = s + 1) begin : stage_pipeline\n localparam int NUM_ELEMS = NUM_INPUTS >> s;\n always_ff @(posedge clk or negedge arst_n) begin\n if (!arst_n) begin\n for (j = 0; j < NUM_ELEMS; j = j + 1)\n stage_reg[s][j] <= '0;\n valid_stage[s] <= 1'b0;\n end\n else if (valid_stage[s-1]) begin\n for (j = 0; j < NUM_ELEMS; j = j + 1)\n stage_reg[s][j] <= stage_reg[s-1][2*j] + stage_reg[s-1][2*j+1];\n valid_stage[s] <= 1'b1;\n end\n else begin\n valid_stage[s] <= 1'b0;\n end\n end\n end\n endgenerate\n\n assign sum_out = stage_reg[NUM_STAGES][0];\n assign valid_out = valid_stage[NUM_STAGES];\n\nendmodule", + "rtl/coeff_ram.sv": "module coeff_ram #(\n parameter NUM_COEFFS = 32,\n parameter DATA_WIDTH = 16\n)\n(\n input logic clk,\n input logic [$clog2(NUM_COEFFS)-1:0] addr,\n output logic [DATA_WIDTH-1:0] data_out\n);\n\n // Memory array for coefficients.\n logic [DATA_WIDTH-1:0] mem [0:NUM_COEFFS-1];\n integer i;\n\n // Synchronous read.\n always_ff @(posedge clk) begin\n data_out <= mem[addr];\n end\n\nendmodule", + "rtl/poly_filter.sv": "module poly_filter #(\n parameter M = 4, // decimation factor\n parameter TAPS = 8, // Taps per phase\n parameter COEFF_WIDTH = 16, // Coefficient bit width\n parameter DATA_WIDTH = 16, // Sample data bit width\n localparam ACC_WIDTH = DATA_WIDTH + COEFF_WIDTH + $clog2(TAPS)\n)\n(\n input logic clk,\n input logic arst_n,\n input logic [DATA_WIDTH-1:0] sample_buffer [0:TAPS-1],\n input logic valid_in,\n // The branch's phase number\n input logic [$clog2(M)-1:0] phase,\n output logic [ACC_WIDTH-1:0] filter_out,\n output logic valid\n);\n\n // ---- Stage 0: Register the input sample vector and phase. ----\n logic [DATA_WIDTH-1:0] sample_reg [0:TAPS-1];\n logic [$clog2(M)-1:0] phase_reg;\n logic valid_stage0;\n integer i;\n always_ff @(posedge clk or negedge arst_n) begin\n if (!arst_n) begin\n for (i = 0; i < TAPS; i = i + 1)\n sample_reg[i] <= '0;\n phase_reg <= '0;\n valid_stage0 <= 1'b0;\n end\n else begin\n if (valid_in) begin\n for (i = 0; i < TAPS; i = i + 1)\n sample_reg[i] <= sample_buffer[i];\n phase_reg <= phase;\n valid_stage0 <= 1'b1;\n end\n else begin\n valid_stage0 <= 1'b0;\n end\n end\n end\n\n // ---- Stage 1: Coefficient Fetch ----\n logic [COEFF_WIDTH-1:0] coeff [0:TAPS-1];\n genvar j;\n generate\n for (j = 0; j < TAPS; j = j + 1) begin : coeff_fetch\n logic [$clog2(M*TAPS)-1:0] addr;\n assign addr = phase_reg * TAPS + j;\n coeff_ram #(\n .NUM_COEFFS(M*TAPS),\n .DATA_WIDTH(COEFF_WIDTH)\n ) u_coeff_ram (\n .clk (clk),\n .addr (addr),\n .data_out(coeff[j])\n );\n end\n endgenerate\n\n logic valid_stage1;\n always_ff @(posedge clk or negedge arst_n) begin\n if (!arst_n)\n valid_stage1 <= 1'b0;\n else\n valid_stage1 <= valid_stage0;\n end\n\n // ---- Stage 2: Multiply the registered samples with coefficients ----\n logic [DATA_WIDTH+COEFF_WIDTH-1:0] products [0:TAPS-1];\n integer k;\n always_comb begin\n for (k = 0; k < TAPS; k = k + 1)\n products[k] = sample_reg[k] * coeff[k];\n end\n\n // ---- Stage 3: Sum the products using the adder_tree ----\n logic [ACC_WIDTH-1:0] sum_result;\n logic valid_adder;\n adder_tree #(\n .NUM_INPUTS(TAPS),\n .DATA_WIDTH(DATA_WIDTH+COEFF_WIDTH)\n ) u_adder_tree_filter (\n .clk (clk),\n .arst_n (arst_n),\n .valid_in (valid_stage1),\n .data_in (products),\n .sum_out (sum_result),\n .valid_out(valid_adder)\n );\n\n // ---- Stage 4: Output Registration ----\n always_ff @(posedge clk or negedge arst_n) begin\n if (!arst_n) begin\n filter_out <= '0;\n valid <= 1'b0;\n end\n else begin\n filter_out <= sum_result;\n valid <= valid_adder;\n end\n end\n\nendmodule", + "rtl/shift_register.sv": "module shift_register #(\n parameter TAPS = 32, // TOTAL_TAPS = N * TAPS\n parameter DATA_WIDTH = 16\n)\n(\n input logic clk,\n input logic arst_n,\n input logic load, // Asserted when a new sample is to be shifted in\n input logic [DATA_WIDTH-1:0] new_sample,\n output logic [DATA_WIDTH-1:0] data_out [0:TAPS-1],\n output logic data_out_val // Indicates that data_out is updated.\n);\n\n // Internal register array for storing samples.\n logic [DATA_WIDTH-1:0] reg_array [0:TAPS-1];\n integer i;\n\n always_ff @(posedge clk or negedge arst_n) begin\n if (!arst_n) begin\n for (i = 0; i < TAPS; i = i + 1)\n reg_array[i] <= '0;\n data_out_val <= 1'b0;\n end\n else if (load) begin\n reg_array[0] <= new_sample;\n for (i = TAPS-1; i > 0; i = i - 1)\n reg_array[i] <= reg_array[i-1];\n data_out_val <= 1'b1;\n end\n else begin\n data_out_val <= 1'b0;\n end\n end\n\n // Continuous assignment of the stored register values to the outputs.\n generate\n for (genvar j = 0; j < TAPS; j = j + 1) begin : assign_output\n assign data_out[j] = reg_array[j];\n end\n endgenerate\n\nendmodule", + "docs/prbs_specification.md": null, + "rtl/prbs_gen_check.sv": null, + "rtl/fsm.sv": null, + "verif/fsm_tb.sv": null, + "rtl/CA_1.sv": null, + "rtl/CA_2.sv": null, + "rtl/CA_3.sv": null, + "rtl/CA_4.sv": null, + "rtl/rgb_color_space_conversion.sv": null, + "rtl/APBGlobalHistoryRegister.v": null, + "docs/signed_comparator_specification.md": null, + "verif/signed_comparator_tb.sv": null, + "rtl/sorting_engine.sv": null, + "rtl/brick_sort.sv": null, + "rtl/bubble_sort.sv": null, + "rtl/merge_sort.sv": null, + "rtl/selection_sort.sv": null + } + }, + { + "id": "cvdp_agentic_programmable_fsm_dynamic_state_encoding_0001", + "index": 560, + "source_config": "cvdp_agentic_code_generation_no_commercial", + "instruction": "Context: You are a language model that has the following file operations available at your disposal:\n - **List files in a directory** by running one of the following commands: \n - `ls`\n - `tree`\n - **Read files** by using:\n - `cat `\n - **Write files** by using:\n - `echo > `\n - **Compile Verilog** by using `iverilog` such as:\n - `iverilog -o .out -g2012 `\n - **Run Simulation** by using:\n - `vvp .out`\n - **Find current working directory** by using:\n - `pwd`\n - **Update the contents of a text file from a old content to new content**\n - `sed -i \"problematic_line_number s/problematic_statement/non_problematic_statement/\" Buggy_RTL_code.sv`\n - **To access a specific line of the file**\n - `awk 'NR==line_number' file_name.sv`\n\nYou will be given a prompt and your task is to understand it and solve the given issue by using the above-mentioned commands as needed. In the final step, you should create a Linux patch to highlight the necessary file updates to achieve the targeted goal.\n\n You will solve the problem step by step using the following approach of \n - thought (thinking process of the step you're going to take\n - action (the command you will be running to get more details/context that's helpful to solve the problem)\n - observation (the output from the action you will observe based on which you will take your next step)\n\n The last step will be the final output summary and the patch itself in the following format \n - thought (the summary of what you did and some introduction of the patch file itself)\n - patch (a Linux-based patch that needs to be applied to reach the relevant solution)\n\n The patch file should only be applied to a single file to reach the required solution.\n\nTask: # Review and Improvement Request for FSM RTL\n\nI have a **Finite State Machine (FSM)** RTL module located at `rtl/fsm.sv` that currently implements **statically encoded** state logic. I would like to convert it to a **dynamically encoded** FSM. Below is a summary of the current design, a clear set of modifications to be made, and the evaluation criteria.\n\n---\n\n## Module Specifications\n\n### RTL (rtl/fsm.sv)\n\n**Inputs**:\n- **clk:** Posedge Clock signal.\n- **reset:** Active-high reset. When ACTIVE HIGH, the `state`, `current_state`, and `error_flag` are initialized to zero.\n- **input_signal:** A 4\u2011bit signal used to drive state transitions.\n- **config_state_map_flat:** A 64\u2011bit flattened state map that holds an 8\u2011bit configuration for each of the 8 states.\n- **config_transition_map_flat:** A 128\u2011bit flattened transition map for calculating the next state.\n\n**Outputs (Static FSM)**:\n- **current_state:** The current internal state (directly driven by the state register).\n- **error_flag:** Indicates if an invalid state transition (next state > 7) is detected.\n- **operation_result:** A result computed based on the current state and input signal using a user-defined operation.\n\n---\n\n## Proposed Modifications for Dynamic State Encoding\n\nThe current outputs the internal state directly, which is suitable for static state encoding. To improve flexibility and allow run-time reconfiguration for area and power optimizations, the following modifications are proposed:\n\n1. **Decouple Internal and External State Representation:**\n - **Current Behavior:** The internal state is directly output as `current_state`.\n - **Modification:** Remove the direct assignment and instead lookup mechanism using `config_state_map_flat` to n **encoded_state**. This separates the internal binary state from its external representation.\n\n2. **dditional Dynamic Transformation:**\n - **Current Behavior:** Operations are computed directly using the statically encoded state.\n - **Modification:** Introduce a second output called **dynamic_encoded_state** that is derived from the **encoded_state** using an additional transformation (for example, an XOR with the input signal). This extra transformation enables further flexibility in the external representation and can be tuned at run time.\n\n3. **Preserve Transition and Error Handling Logic:**\n - **Current Behavior:** The next state is computed from the transition map, and error detection is performed if the next state exceeds 7.\n - **Modification:** Retain this state transition logic, error detection, and the user-defined operations (e.g., addition, subtraction, bitwise operations) so that the functional behavior remains consistent.\n\n---\n\n## Evaluation Criteria\n\nTo evaluate the dynamic FSM against the current static design, consider the following criteria:\n\n- **Functional Correctness:**\n - The dynamic FSM must maintain the same state transitions and operation results as the static FSM for identical inputs.\n \n- **Reconfigurability:**\n - The external state outputs (**encoded_state** and **dynamic_encoded_state**) must accurately reflect the configuration provided by `config_state_map_flat` and adapt correctly based on the input signal.\n\n- **Error Detection:**\n - The error flag must be correctly set when the computed next state exceeds the valid range (i.e., greater than 7), and the state should be safely reset to 0 as in the original design.\n\n- **Flexibility:**\n - The modifications should allow for on-the-fly changes to the state encoding without impacting the underlying state machine functionality. \n\n----\n**Block Diagram for the Existing Architecture**:\n\n +---------------------------+\n | Internal State (reg) |\n | (state) |\n +------------+--------------+\n |\n | (state, input_signal)\n v\n +--------------------------------+\n | Config Transition Map |\n | (128-bit lookup) |\n +------------+-------------------+\n | (computes next_state)\n v\n +----------------------------------+\n | Next State Logic |\n | (generates next_state and |\n | error_flag based on next_state) |\n +------------+---------------------+\n | (error_flag output here)\n |\n | (next_state is passed on)\n v\n +----------------------------+\n | Internal State (reg) |\n | (updated state) |\n +----------------------------+\n |\n | (direct mapping)\n v\n +---------------------+\n | current_state |\n +---------------------+\n |\n | (state used to select slice)\n v\n +------------------------------+\n | Config State Map Lookup |\n | (64-bit lookup: 8-bit per |\n | state slice) |\n +------------+-----------------+\n | (provides operand for)\n v\n +------------------------------+\n | Operation Computation Logic |\n | (case: using config slice |\n | & input_signal for arithmetic)|\n +-------------+------------------+\n |\n v\n +---------------------+\n | operation_result |\n +---------------------+\n |\n v\n +---------------------+\n | error_flag |\n +---------------------+\n\n\n----\n\n---\n**Block Diagram of the Proposed Modification** :\n\n +---------------------------+\n | Internal State (reg) |\n | (state) |\n +------------+--------------+\n |\n | (state, input_signal)\n v\n +--------------------------------+\n | Config Transition Map |\n | (128-bit lookup) |\n +------------+-------------------+\n | (computes next_state)\n v\n +----------------------------------+\n | Next State Logic |\n | (generates next_state and |\n | error_flag based on next_state)|\n +------------+---------------------+\n | (error_flag output here)\n |\n | (next_state is passed on)\n v\n +----------------------------+\n | Internal State (reg) |\n | (updated state) |\n +----------------------------+\n |\n +---------------+--------------+\n | |\n v v\n +------------------------------+ +------------------------------+\n | Config State Map Lookup | | Operation Computation |\n | (64-bit lookup: 8-bit per state) | | Logic (using config slice |\n | | | & input_signal) |\n +-------------+----------------+ +-------------+----------------+\n | |\n v v\n +-------------------+ +---------------------+\n | encoded_state | | operation_result |\n +-------------------+ +---------------------+\n | \n | (Dynamic Transformation: \n | encoded_state ^ {4'b0, input_signal})\n v \n +----------------------------+\n | dynamic_encoded_state |\n +----------------------------+\n\n (error_flag is generated in Next State Logic\n and is output separately; it is not used in\n updating the internal state)\n\n\n-----\n\n\n## Summary\n\n**Static FSM (Current Implementation)**: \n- Directly outputs the internal state as `current_state`. \n- Uses fixed, unmodifiable state encoding.\n\n**Dynamic FSM (Proposed Improvement)**: \n- Separates the internal state from its external representation using a configurable state map to **encoded_state**. \n- Further refines the external state via a dynamic transformation (e.g., XOR with the input) to produce **dynamic_encoded_state**. \n- Retains the same state transition, operation, and error detection logic.\n\nPlease review the current FSM implementation at `rtl/fsm.sv` and make the above modifications to convert the statically encoded into a dynamically encoded FSM. The evaluation will be based on functional equivalence, improved flexibility in state representation, robust error handling, and the ability to adjust state encoding dynamically at runtime.", + "verilog_code": { + "code_block_1_5": "config_state_map_flat", + "code_block_1_6": "config_state_map_flat", + "code_block_2_0": "module located at `rtl/fsm.sv` that currently implements **statically encoded** state logic. I would like to convert it to a **dynamically encoded** FSM. Below is a summary of the current design, a clear set of modifications to be made, and the evaluation criteria.\n\n---\n\n## Module Specifications\n\n### RTL (rtl/fsm.sv)\n\n**Inputs**:\n- **clk:** Posedge Clock signal.\n- **reset:** Active-high reset. When ACTIVE HIGH, the `state`, `current_state`, and `error_flag` are initialized to zero.\n- **input_signal:** A 4\u2011bit signal used to drive state transitions.\n- **config_state_map_flat:** A 64\u2011bit flattened state map that holds an 8\u2011bit configuration for each of the 8 states.\n- **config_transition_map_flat:** A 128\u2011bit flattened transition map for calculating the next state.\n\n**Outputs (Static FSM)**:\n- **current_state:** The current internal state (directly driven by the state register).\n- **error_flag:** Indicates if an invalid state transition (next state > 7) is detected.\n- **operation_result:** A result computed based on the current state and input signal using a user-defined operation.\n\n---\n\n## Proposed Modifications for Dynamic State Encoding\n\nThe current design outputs the internal state directly, which is suitable for static state encoding. To improve flexibility and allow run-time reconfiguration for area and power optimizations, the following modifications are proposed:\n\n1. **Decouple Internal and External State Representation:**\n - **Current Behavior:** The internal state is directly output as `current_state`.\n - **Modification:** Remove the direct assignment and instead implement a lookup mechanism using `config_state_map_flat` to generate an **encoded_state**. This separates the internal binary state from its external representation.\n\n2. **Implement Additional Dynamic Transformation:**\n - **Current Behavior:** Operations are computed directly using the statically encoded state.\n - **Modification:** Introduce a second output called **dynamic_encoded_state** that is derived from the **encoded_state** using an additional transformation (for example, an XOR with the input signal). This extra transformation enables further flexibility in the external representation and can be tuned at run time.\n\n3. **Preserve Transition and Error Handling Logic:**\n - **Current Behavior:** The next state is computed from the transition map, and error detection is performed if the next state exceeds 7.\n - **Modification:** Retain this state transition logic, error detection, and the user-defined operations (e.g., addition, subtraction, bitwise operations) so that the functional behavior remains consistent.\n\n---\n\n## Evaluation Criteria\n\nTo evaluate the dynamic FSM against the current static design, consider the following criteria:\n\n- **Functional Correctness:**\n - The dynamic FSM must maintain the same state transitions and operation results as the static FSM for identical inputs.\n \n- **Reconfigurability:**\n - The external state outputs (**encoded_state** and **dynamic_encoded_state**) must accurately reflect the configuration provided by `config_state_map_flat` and adapt correctly based on the input signal.\n\n- **Error Detection:**\n - The error flag must be correctly set when the computed next state exceeds the valid range (i.e., greater than 7), and the state should be safely reset to 0 as in the original design.\n\n- **Flexibility:**\n - The modifications should allow for on-the-fly changes to the state encoding without impacting the underlying state machine functionality. \n\n----\n**Block Diagram for the Existing Architecture**:\n\n +---------------------------+\n | Internal State (reg) |\n | (state) |\n +------------+--------------+\n |\n | (state, input_signal)\n v\n +--------------------------------+\n | Config Transition Map |\n | (128-bit lookup) |\n +------------+-------------------+\n | (computes next_state)\n v\n +----------------------------------+\n | Next State Logic |\n | (generates next_state and |\n | error_flag based on next_state) |\n +------------+---------------------+\n | (error_flag output here)\n |\n | (next_state is passed on)\n v\n +----------------------------+\n | Internal State (reg) |\n | (updated state) |\n +----------------------------+\n |\n | (direct mapping)\n v\n +---------------------+\n | current_state |\n +---------------------+\n |\n | (state used to select slice)\n v\n +------------------------------+\n | Config State Map Lookup |\n | (64-bit lookup: 8-bit per |\n | state slice) |\n +------------+-----------------+\n | (provides operand for)\n v\n +------------------------------+\n | Operation Computation Logic |\n | (case: using config slice |\n | & input_signal for arithmetic)|\n +-------------+------------------+\n |\n v\n +---------------------+\n | operation_result |\n +---------------------+\n |\n v\n +---------------------+\n | error_flag |\n +---------------------+\n\n\n----\n\n---\n**Block Diagram of the Proposed Modification** :\n\n +---------------------------+\n | Internal State (reg) |\n | (state) |\n +------------+--------------+\n |\n | (state, input_signal)\n v\n +--------------------------------+\n | Config Transition Map |\n | (128-bit lookup) |\n +------------+-------------------+\n | (computes next_state)\n v\n +----------------------------------+\n | Next State Logic |\n | (generates next_state and |\n | error_flag based on next_state)|\n +------------+---------------------+\n | (error_flag output here)\n |\n | (next_state is passed on)\n v\n +----------------------------+\n | Internal State (reg) |\n | (updated state) |\n +----------------------------+\n |\n +---------------+--------------+\n | |\n v v\n +------------------------------+ +------------------------------+\n | Config State Map Lookup | | Operation Computation |\n | (64-bit lookup: 8-bit per state) | | Logic (using config slice |\n | | | & input_signal) |\n +-------------+----------------+ +-------------+----------------+\n | |\n v v\n +-------------------+ +---------------------+\n | encoded_state | | operation_result |\n +-------------------+ +---------------------+\n | \n | (Dynamic Transformation: \n | encoded_state ^ {4'b0, input_signal})\n v \n +----------------------------+\n | dynamic_encoded_state |\n +----------------------------+\n\n (error_flag is generated in Next State Logic\n and is output separately; it is not used in\n updating the internal state)", + "code_block_2_1": "module fsm (\\n input clk,\\n input reset,\\n input [3:0] input_signal,\\n input [63:0] config_state_map_flat,\\n input [127:0] config_transition_map_flat,\\n output reg [7:0] current_state,\\n output reg error_flag,\\n output reg [7:0] operation_result\\n);\\n\\n \\n reg [7:0] state;\\n reg [7:0] next_state;\\n \\n wire [7:0] config_state_map0 = config_state_map_flat[7:0];\\n wire [7:0] config_state_map1 = config_state_map_flat[15:8];\\n wire [7:0] config_state_map2 = config_state_map_flat[23:16];\\n wire [7:0] config_state_map3 = config_state_map_flat[31:24];\\n wire [7:0] config_state_map4 = config_state_map_flat[39:32];\\n wire [7:0] config_state_map5 = config_state_map_flat[47:40];\\n wire [7:0] config_state_map6 = config_state_map_flat[55:48];\\n wire [7:0] config_state_map7 = config_state_map_flat[63:56];\\n\\n always @(posedge clk or posedge reset) begin\\n if (reset) begin\\n state <= 0;\\n current_state <= 0;\\n error_flag <= 0;\\n end else begin\\n state <= next_state;\\n current_state <= next_state;\\n end\\n end\\n\\n always @(*) begin\\n integer idx;\\n idx = (state << 4) + input_signal; \\n next_state = config_transition_map_flat[(idx * 8) + 7 -: 8];\\n \\n if (next_state > 8'h7) begin\\n error_flag = 1;\\n next_state = 0; \\n end else begin\\n error_flag = 0;\\n end\\n\\n case (state)\\n 8'h0: operation_result = config_state_map0 + input_signal;\\n 8'h1: operation_result = config_state_map1 - input_signal;\\n 8'h2: operation_result = config_state_map2 & input_signal;\\n 8'h3: operation_result = config_state_map3 | input_signal;\\n default: operation_result = 8'hFF; \\n endcase\\n end\\n\\nendmodule\", 'verif/fsm_tb.sv': '`timescale 1ns/1ps\\nmodule fsm_tb;\\n\\n reg clk;\\n reg reset;\\n reg [3:0] input_signal;\\n reg [63:0] config_state_map_flat;\\n reg [127:0] config_transition_map_flat;\\n wire [7:0] encoded_state;\\n wire [7:0] dynamic_encoded_state;\\n wire error_flag;\\n wire [7:0] operation_result;\\n \\n \\n fsm dut (\\n .clk(clk),\\n .reset(reset),\\n .input_signal(input_signal),\\n .config_state_map_flat(config_state_map_flat),\\n .config_transition_map_flat(config_transition_map_flat),\\n .encoded_state(encoded_state),\\n .dynamic_encoded_state(dynamic_encoded_state),\\n .error_flag(error_flag),\\n .operation_result(operation_result)\\n );\\n \\n \\n initial begin\\n clk = 0;\\n forever #5 clk = ~clk;\\n end\\n \\n \\n initial begin\\n $dumpfile(\"fsm_tb.vcd\");\\n $dumpvars(0, fsm_tb);\\n \\n config_state_map_flat = {8\\'h80, 8\\'h70, 8\\'h60, 8\\'h50, 8\\'h40, 8\\'h30, 8\\'h20, 8\\'h10};\\n \\n config_transition_map_flat = { \\n 8\\'h0, \\n 8\\'h0, \\n 8\\'h0, \\n 8\\'h0, \\n 8\\'h0, \\n 8\\'h0, \\n 8\\'h0, \\n 8\\'h0, \\n 8\\'h0, \\n 8\\'h0, \\n 8\\'h0, \\n 8\\'h8, \\n 8\\'h0, \\n 8\\'h0, \\n 8\\'h0, \\n 8\\'h0 \\n };\\n \\n \\n reset = 1;\\n input_signal = 4\\'b0;\\n #12;\\n reset = 0;\\n #10;\\n \\n \\n input_signal = 4\\'h1;\\n #10;\\n $display(\"Test 1: encoded_state = %0h, dynamic_encoded_state = %0h, error_flag = %b, operation_result = %0d\", \\n encoded_state, dynamic_encoded_state, error_flag, operation_result);\\n \\n \\n input_signal = 4\\'h2;\\n #10;\\n $display(\"Test 2: encoded_state = %0h, dynamic_encoded_state = %0h, error_flag = %b, operation_result = %0d\", \\n encoded_state, dynamic_encoded_state, error_flag, operation_result);\\n \\n \\n input_signal = 4\\'h3;\\n #10;\\n $display(\"Test 3: encoded_state = %0h, dynamic_encoded_state = %0h, error_flag = %b, operation_result = %0d\", \\n encoded_state, dynamic_encoded_state, error_flag, operation_result);\\n \\n \\n input_signal = 4\\'h4;\\n #10;\\n $display(\"Test 4 (error): encoded_state = %0h, dynamic_encoded_state = %0h, error_flag = %b, operation_result = %0d\", \\n encoded_state, dynamic_encoded_state, error_flag, operation_result);\\n \\n \\n input_signal = 4\\'h0;\\n #10;\\n $display(\"Test 5: encoded_state = %0h, dynamic_encoded_state = %0h, error_flag = %b, operation_result = %0d\", \\n encoded_state, dynamic_encoded_state, error_flag, operation_result);\\n \\n $finish;\\n end\\n\\nendmodule', 'rtl/CA_1.sv': None, 'rtl/CA_2.sv': None, 'rtl/CA_3.sv': None, 'rtl/CA_4.sv': None, 'rtl/rgb_color_space_conversion.sv': None, 'rtl/APBGlobalHistoryRegister.v': None, 'docs/signed_comparator_specification.md': None, 'verif/signed_comparator_tb.sv': None, 'rtl/sorting_engine.sv': None, 'rtl/brick_sort.sv': None, 'rtl/bubble_sort.sv': None, 'rtl/merge_sort.sv': None, 'rtl/selection_sort.sv': None}", + "rtl/fsm.sv": "module fsm (\n input clk,\n input reset,\n input [3:0] input_signal,\n input [63:0] config_state_map_flat,\n input [127:0] config_transition_map_flat,\n output reg [7:0] current_state,\n output reg error_flag,\n output reg [7:0] operation_result\n);\n\n \n reg [7:0] state;\n reg [7:0] next_state;\n \n wire [7:0] config_state_map0 = config_state_map_flat[7:0];\n wire [7:0] config_state_map1 = config_state_map_flat[15:8];\n wire [7:0] config_state_map2 = config_state_map_flat[23:16];\n wire [7:0] config_state_map3 = config_state_map_flat[31:24];\n wire [7:0] config_state_map4 = config_state_map_flat[39:32];\n wire [7:0] config_state_map5 = config_state_map_flat[47:40];\n wire [7:0] config_state_map6 = config_state_map_flat[55:48];\n wire [7:0] config_state_map7 = config_state_map_flat[63:56];\n\n always @(posedge clk or posedge reset) begin\n if (reset) begin\n state <= 0;\n current_state <= 0;\n error_flag <= 0;\n end else begin\n state <= next_state;\n current_state <= next_state;\n end\n end\n\n always @(*) begin\n integer idx;\n idx = (state << 4) + input_signal; \n next_state = config_transition_map_flat[(idx * 8) + 7 -: 8];\n \n if (next_state > 8'h7) begin\n error_flag = 1;\n next_state = 0; \n end else begin\n error_flag = 0;\n end\n\n case (state)\n 8'h0: operation_result = config_state_map0 + input_signal;\n 8'h1: operation_result = config_state_map1 - input_signal;\n 8'h2: operation_result = config_state_map2 & input_signal;\n 8'h3: operation_result = config_state_map3 | input_signal;\n default: operation_result = 8'hFF; \n endcase\n end\n\nendmodule", + "verif/fsm_tb.sv": "`timescale 1ns/1ps\nmodule fsm_tb;\n\n reg clk;\n reg reset;\n reg [3:0] input_signal;\n reg [63:0] config_state_map_flat;\n reg [127:0] config_transition_map_flat;\n wire [7:0] encoded_state;\n wire [7:0] dynamic_encoded_state;\n wire error_flag;\n wire [7:0] operation_result;\n \n \n fsm dut (\n .clk(clk),\n .reset(reset),\n .input_signal(input_signal),\n .config_state_map_flat(config_state_map_flat),\n .config_transition_map_flat(config_transition_map_flat),\n .encoded_state(encoded_state),\n .dynamic_encoded_state(dynamic_encoded_state),\n .error_flag(error_flag),\n .operation_result(operation_result)\n );\n \n \n initial begin\n clk = 0;\n forever #5 clk = ~clk;\n end\n \n \n initial begin\n $dumpfile(\"fsm_tb.vcd\");\n $dumpvars(0, fsm_tb);\n \n config_state_map_flat = {8'h80, 8'h70, 8'h60, 8'h50, 8'h40, 8'h30, 8'h20, 8'h10};\n \n config_transition_map_flat = { \n 8'h0, \n 8'h0, \n 8'h0, \n 8'h0, \n 8'h0, \n 8'h0, \n 8'h0, \n 8'h0, \n 8'h0, \n 8'h0, \n 8'h0, \n 8'h8, \n 8'h0, \n 8'h0, \n 8'h0, \n 8'h0 \n };\n \n \n reset = 1;\n input_signal = 4'b0;\n #12;\n reset = 0;\n #10;\n \n \n input_signal = 4'h1;\n #10;\n $display(\"Test 1: encoded_state = %0h, dynamic_encoded_state = %0h, error_flag = %b, operation_result = %0d\", \n encoded_state, dynamic_encoded_state, error_flag, operation_result);\n \n \n input_signal = 4'h2;\n #10;\n $display(\"Test 2: encoded_state = %0h, dynamic_encoded_state = %0h, error_flag = %b, operation_result = %0d\", \n encoded_state, dynamic_encoded_state, error_flag, operation_result);\n \n \n input_signal = 4'h3;\n #10;\n $display(\"Test 3: encoded_state = %0h, dynamic_encoded_state = %0h, error_flag = %b, operation_result = %0d\", \n encoded_state, dynamic_encoded_state, error_flag, operation_result);\n \n \n input_signal = 4'h4;\n #10;\n $display(\"Test 4 (error): encoded_state = %0h, dynamic_encoded_state = %0h, error_flag = %b, operation_result = %0d\", \n encoded_state, dynamic_encoded_state, error_flag, operation_result);\n \n \n input_signal = 4'h0;\n #10;\n $display(\"Test 5: encoded_state = %0h, dynamic_encoded_state = %0h, error_flag = %b, operation_result = %0d\", \n encoded_state, dynamic_encoded_state, error_flag, operation_result);\n \n $finish;\n end\n\nendmodule" + }, + "test_info": { + "test_criteria_2": [ + "be safely reset to 0 as in the original design.", + "allow for on-the-fly changes to the state encoding without impacting the underlying state machine functionality." + ] + }, + "expected_behavior": [ + "maintain the same state transitions and operation results as the static FSM for identical inputs", + "accurately reflect the configuration provided by `config_state_map_flat` and adapt correctly based on the input signal", + "be correctly set when the computed next state exceeds the valid range (i", + "be safely reset to 0 as in the original design", + "allow for on-the-fly changes to the state encoding without impacting the underlying state machine functionality", + "be based on functional equivalence, improved flexibility in state representation, robust error handling, and the ability to adjust state encoding dynamically at runtime", + "remains consistent." + ], + "metadata": { + "categories": [ + "cid004", + "easy" + ], + "domain": "memory", + "complexity": "expert", + "problem_type": "design", + "has_code": true, + "has_tests": true + }, + "full_prompt": "# Review and Improvement Request for FSM RTL\n\nI have a **Finite State Machine (FSM)** RTL module located at `rtl/fsm.sv` that currently implements **statically encoded** state logic. I would like to convert it to a **dynamically encoded** FSM. Below is a summary of the current design, a clear set of modifications to be made, and the evaluation criteria.\n\n---\n\n## Module Specifications\n\n### RTL (rtl/fsm.sv)\n\n**Inputs**:\n- **clk:** Posedge Clock signal.\n- **reset:** Active-high reset. When ACTIVE HIGH, the `state`, `current_state`, and `error_flag` are initialized to zero.\n- **input_signal:** A 4\u2011bit signal used to drive state transitions.\n- **config_state_map_flat:** A 64\u2011bit flattened state map that holds an 8\u2011bit configuration for each of the 8 states.\n- **config_transition_map_flat:** A 128\u2011bit flattened transition map for calculating the next state.\n\n**Outputs (Static FSM)**:\n- **current_state:** The current internal state (directly driven by the state register).\n- **error_flag:** Indicates if an invalid state transition (next state > 7) is detected.\n- **operation_result:** A result computed based on the current state and input signal using a user-defined operation.\n\n---\n\n## Proposed Modifications for Dynamic State Encoding\n\nThe current design outputs the internal state directly, which is suitable for static state encoding. To improve flexibility and allow run-time reconfiguration for area and power optimizations, the following modifications are proposed:\n\n1. **Decouple Internal and External State Representation:**\n - **Current Behavior:** The internal state is directly output as `current_state`.\n - **Modification:** Remove the direct assignment and instead implement a lookup mechanism using `config_state_map_flat` to generate an **encoded_state**. This separates the internal binary state from its external representation.\n\n2. **Implement Additional Dynamic Transformation:**\n - **Current Behavior:** Operations are computed directly using the statically encoded state.\n - **Modification:** Introduce a second output called **dynamic_encoded_state** that is derived from the **encoded_state** using an additional transformation (for example, an XOR with the input signal). This extra transformation enables further flexibility in the external representation and can be tuned at run time.\n\n3. **Preserve Transition and Error Handling Logic:**\n - **Current Behavior:** The next state is computed from the transition map, and error detection is performed if the next state exceeds 7.\n - **Modification:** Retain this state transition logic, error detection, and the user-defined operations (e.g., addition, subtraction, bitwise operations) so that the functional behavior remains consistent.\n\n---\n\n## Evaluation Criteria\n\nTo evaluate the dynamic FSM against the current static design, consider the following criteria:\n\n- **Functional Correctness:**\n - The dynamic FSM must maintain the same state transitions and operation results as the static FSM for identical inputs.\n \n- **Reconfigurability:**\n - The external state outputs (**encoded_state** and **dynamic_encoded_state**) must accurately reflect the configuration provided by `config_state_map_flat` and adapt correctly based on the input signal.\n\n- **Error Detection:**\n - The error flag must be correctly set when the computed next state exceeds the valid range (i.e., greater than 7), and the state should be safely reset to 0 as in the original design.\n\n- **Flexibility:**\n - The modifications should allow for on-the-fly changes to the state encoding without impacting the underlying state machine functionality. \n\n----\n**Block Diagram for the Existing Architecture**:\n\n +---------------------------+\n | Internal State (reg) |\n | (state) |\n +------------+--------------+\n |\n | (state, input_signal)\n v\n +--------------------------------+\n | Config Transition Map |\n | (128-bit lookup) |\n +------------+-------------------+\n | (computes next_state)\n v\n +----------------------------------+\n | Next State Logic |\n | (generates next_state and |\n | error_flag based on next_state) |\n +------------+---------------------+\n | (error_flag output here)\n |\n | (next_state is passed on)\n v\n +----------------------------+\n | Internal State (reg) |\n | (updated state) |\n +----------------------------+\n |\n | (direct mapping)\n v\n +---------------------+\n | current_state |\n +---------------------+\n |\n | (state used to select slice)\n v\n +------------------------------+\n | Config State Map Lookup |\n | (64-bit lookup: 8-bit per |\n | state slice) |\n +------------+-----------------+\n | (provides operand for)\n v\n +------------------------------+\n | Operation Computation Logic |\n | (case: using config slice |\n | & input_signal for arithmetic)|\n +-------------+------------------+\n |\n v\n +---------------------+\n | operation_result |\n +---------------------+\n |\n v\n +---------------------+\n | error_flag |\n +---------------------+\n\n\n----\n\n---\n**Block Diagram of the Proposed Modification** :\n\n +---------------------------+\n | Internal State (reg) |\n | (state) |\n +------------+--------------+\n |\n | (state, input_signal)\n v\n +--------------------------------+\n | Config Transition Map |\n | (128-bit lookup) |\n +------------+-------------------+\n | (computes next_state)\n v\n +----------------------------------+\n | Next State Logic |\n | (generates next_state and |\n | error_flag based on next_state)|\n +------------+---------------------+\n | (error_flag output here)\n |\n | (next_state is passed on)\n v\n +----------------------------+\n | Internal State (reg) |\n | (updated state) |\n +----------------------------+\n |\n +---------------+--------------+\n | |\n v v\n +------------------------------+ +------------------------------+\n | Config State Map Lookup | | Operation Computation |\n | (64-bit lookup: 8-bit per state) | | Logic (using config slice |\n | | | & input_signal) |\n +-------------+----------------+ +-------------+----------------+\n | |\n v v\n +-------------------+ +---------------------+\n | encoded_state | | operation_result |\n +-------------------+ +---------------------+\n | \n | (Dynamic Transformation: \n | encoded_state ^ {4'b0, input_signal})\n v \n +----------------------------+\n | dynamic_encoded_state |\n +----------------------------+\n\n (error_flag is generated in Next State Logic\n and is output separately; it is not used in\n updating the internal state)\n\n\n-----\n\n\n## Summary\n\n**Static FSM (Current Implementation)**: \n- Directly outputs the internal state as `current_state`. \n- Uses fixed, unmodifiable state encoding.\n\n**Dynamic FSM (Proposed Improvement)**: \n- Separates the internal state from its external representation using a configurable state map to generate **encoded_state**. \n- Further refines the external state via a dynamic transformation (e.g., XOR with the input) to produce **dynamic_encoded_state**. \n- Retains the same state transition, operation, and error detection logic.\n\nPlease review the current FSM implementation at `rtl/fsm.sv` and make the above modifications to convert the statically encoded design into a dynamically encoded FSM. The evaluation will be based on functional equivalence, improved flexibility in state representation, robust error handling, and the ability to adjust state encoding dynamically at runtime.\n", + "system_message": "You are a language model that has the following file operations available at your disposal:\n - **List files in a directory** by running one of the following commands: \n - `ls`\n - `tree`\n - **Read files** by using:\n - `cat `\n - **Write files** by using:\n - `echo > `\n - **Compile Verilog** by using `iverilog` such as:\n - `iverilog -o .out -g2012 `\n - **Run Simulation** by using:\n - `vvp .out`\n - **Find current working directory** by using:\n - `pwd`\n - **Update the contents of a text file from a old content to new content**\n - `sed -i \"problematic_line_number s/problematic_statement/non_problematic_statement/\" Buggy_RTL_code.sv`\n - **To access a specific line of the file**\n - `awk 'NR==line_number' file_name.sv`\n\nYou will be given a prompt and your task is to understand it and solve the given issue by using the above-mentioned commands as needed. In the final step, you should create a Linux patch to highlight the necessary file updates to achieve the targeted goal.\n\n You will solve the problem step by step using the following approach of \n - thought (thinking process of the step you're going to take\n - action (the command you will be running to get more details/context that's helpful to solve the problem)\n - observation (the output from the action you will observe based on which you will take your next step)\n\n The last step will be the final output summary and the patch itself in the following format \n - thought (the summary of what you did and some introduction of the patch file itself)\n - patch (a Linux-based patch that needs to be applied to reach the relevant solution)\n\n The patch file should only be applied to a single file to reach the required solution.", + "raw_context": { + "docs/specification.md": null, + "rtl/decoder_data_control_64b66b.sv": null, + "rtl/encoder_control_64b66b.sv": null, + "rtl/encoder_data_64b66b.sv": null, + "rtl/aes128_encrypt.sv": null, + "verif/tb_aes128_enc.sv": null, + "rtl/aes128_decrypt.sv": null, + "rtl/aes128_key_expansion.sv": null, + "rtl/inv_sbox.sv": null, + "rtl/sbox.sv": null, + "verif/tb_aes128_dec.sv": null, + "rtl/aes_encrypt.sv": null, + "verif/tb_aes_encrypt.sv": null, + "rtl/aes_decrypt.sv": null, + "rtl/aes_ke.sv": null, + "verif/tb_aes_decrypt.sv": null, + "rtl/aes_dec_top.sv": null, + "rtl/aes_enc_top.sv": null, + "verif/tb_padding_top.sv": null, + "verif/tb_des_enc.sv": null, + "docs/Key_schedule.md": null, + "docs/Permutations.md": null, + "docs/S_box_creation.md": null, + "rtl/S1.sv": null, + "rtl/S2.sv": null, + "rtl/S3.sv": null, + "rtl/S4.sv": null, + "rtl/S5.sv": null, + "rtl/S6.sv": null, + "rtl/S7.sv": null, + "rtl/S8.sv": null, + "rtl/des_enc.sv": null, + "verif/tb_des_dec.sv": null, + "docs/Encryption.md": null, + "rtl/des_dec.sv": null, + "verif/tb_3des_enc.sv": null, + "verif/tb_3des_dec.sv": null, + "docs/min_hamming_distance_finder_spec.md": null, + "rtl/Bit_Difference_Counter.sv": null, + "rtl/Bitwise_Reduction.sv": null, + "rtl/Data_Reduction.sv": null, + "verif/tb_Min_Hamming_Distance_Finder.sv": null, + "docs/specs.md": null, + "rtl/arithmetic_progression_generator.sv": null, + "docs/algorithms.md": null, + "docs/coeff_update_spec.md": null, + "docs/equalizer_spec.md": null, + "docs/error_calc_spec.md": null, + "rtl/coeff_update.sv": null, + "rtl/dynamic_equalizer.sv": null, + "rtl/error_calc.sv": null, + "docs/awgn_spec.md": null, + "docs/equalizer_top_spec.md": null, + "rtl/elevator_control_system.sv": null, + "docs/tx_specification.md": null, + "rtl/ethernet_fifo_cdc.sv": null, + "docs/tx_mac_specification.md": null, + "verif/event_scheduler_tb.sv": null, + "docs/modified_specs.md": null, + "rtl/event_scheduler.sv": null, + "verif/tb_event_scheduler.sv": null, + "rtl/column_selector.sv": null, + "rtl/event_storage.sv": null, + "verif/tb.sv": null, + "rtl/fixed_priority_arbiter.sv": null, + "verif/fixed_priority_arbiter_tb.sv": null, + "docs/Modified_specification.md": null, + "docs/GCD_specification.md": null, + "docs/crypto_accelerator_specification.md": null, + "docs/modular_exponentiation_specification.md": null, + "docs/modular_multiplier_specification.md": null, + "rtl/gcd_controlpath_3.sv": null, + "rtl/gcd_controlpath_4.sv": null, + "rtl/gcd_datapath_5.sv": null, + "rtl/gcd_datapath_6.sv": null, + "rtl/gcd_top_1.sv": null, + "rtl/gcd_top_2.sv": null, + "rtl/modular_exponentiation.sv": null, + "rtl/modular_multiplier.sv": null, + "rtl/lfsr_8bit.sv": null, + "verif/lfsr_8bit_tb.sv": null, + "rtl/bit16_lfsr.sv": null, + "rtl/low_power_ctrl.sv": null, + "rtl/sync_fifo.sv": null, + "verif/tb_low_power_channel.sv": null, + "rtl/cross_domain_sync.sv": null, + "rtl/dsp_input_stage.sv": null, + "rtl/dsp_output_stage.sv": null, + "rtl/lfsr_generator.sv": null, + "rtl/monte_carlo_dsp_monitor_top.sv": null, + "verif/monte_carlo_dsp_monitor_top_tb.sv": null, + "docs/multiplexer_specification.md": null, + "verif/multiplexer_tb.sv": null, + "docs/nbit_swizzling_spec.md": null, + "verif/nbit_swizzling_tb.sv": null, + "docs/nmea_decoder_spec.md": null, + "rtl/nmea_decoder.sv": null, + "verif/nmea_decoder_tb.sv": null, + "docs/fifo.md": null, + "rtl/fifo_memory.sv": null, + "rtl/read_to_write_pointer_sync.sv": null, + "rtl/rptr_empty.sv": null, + "rtl/wptr_full.sv": null, + "rtl/write_to_read_pointer_sync.sv": null, + "docs/spec.md": null, + "verif/async_filo_tb.sv": null, + "docs/axilite_to_pcie_config_module.md": null, + "rtl/axi4lite_to_pcie_cfg_bridge.sv": null, + "rtl/axis_broadcast.sv": null, + "verif/tb_axis_broadcast.sv": null, + "docs/axis_to_uart_tx_specs.md": null, + "docs/uart_rx_to_axis_specs.md": null, + "rtl/barrel_shifter.sv": null, + "verif/barrel_shifter_tb.sv": null, + "rtl/bcd_adder.sv": null, + "rtl/full_adder.sv": null, + "rtl/four_bit_adder.sv": null, + "rtl/search_binary_search_tree.sv": null, + "rtl/delete_node_binary_search_tree.sv": null, + "docs/bst_operations.md": null, + "rtl/binary_search_tree_sort_construct.sv": null, + "docs/Spec.md": null, + "verif/tb_binary_to_gray.sv": null, + "verif/tb_custom_byte_enable_ram.sv": null, + "verif/cache_controller_tb.sv": null, + "rtl/caesar_cipher.sv": null, + "verif/caesar_cipher_tb.sv": null, + "verif/tb_pseudoRandGenerator_ca.sv": null, + "docs/continuous_adder_specification.md": null, + "verif/continuous_adder_tb.sv": null, + "rtl/fifo_buffer.sv": null, + "verif/tb_fifo_buffer.sv": null, + "docs/direct_map_cache_spec.md": null, + "verif/tb_direct_map_cache.sv": null, + "rtl/direct_map_cache.sv": null, + "rtl/dual_port_memory.sv": null, + "rtl/gen_cos_sin_lut.sv": null, + "rtl/phase_lut.sv": null, + "rtl/phase_rotation.sv": null, + "rtl/power4.sv": null, + "rtl/saturation.sv": null, + "rtl/top_phase_rotation.sv": null, + "docs/spec_viterbi.md": null, + "docs/spec_slicer_top.md": null, + "docs/spec_top_phase_rotation.md": null, + "rtl/slicer.sv": null, + "rtl/slicer_top.sv": null, + "docs/swizzler_specification.md": null, + "verif/swizzler_tb.sv": null, + "rtl/swizzler.sv": null, + "docs/sync_serial_communication_tx_rx_spec.md": null, + "verif/sync_serial_communication_tb.sv": null, + "rtl/weight_stationary_pe.sv": null, + "verif/systolic_array_tb.sv": null, + "rtl/thermostat.v": null, + "docs/Traffic_controller.md": null, + "rtl/traffic_light_controller.sv": null, + "docs/Universal_Shift_Register_spec.md": null, + "verif/tb_universal_shift_register.sv": null, + "rtl/universal_shift_register.sv": null, + "docs/spec_conj.md": null, + "docs/spec_cross_correlation.md": null, + "docs/spec_detect_sequence.md": null, + "rtl/adder_2d_layers.sv": null, + "rtl/adder_tree_2d.sv": null, + "rtl/correlate.sv": null, + "rtl/cross_correlation.sv": null, + "docs/valid_modes.md": null, + "docs/words_counting.md": null, + "rtl/detect_sequence.sv": null, + "docs/proc_fsm_spec.md": null, + "docs/adder_tree.md": null, + "docs/coeff_ram.md": null, + "docs/poly_decimator.md": null, + "docs/poly_filter.md": null, + "docs/shift_register.md": null, + "rtl/adder_tree.sv": null, + "rtl/coeff_ram.sv": null, + "rtl/poly_filter.sv": null, + "rtl/shift_register.sv": null, + "docs/prbs_specification.md": null, + "rtl/prbs_gen_check.sv": null, + "rtl/fsm.sv": "module fsm (\n input clk,\n input reset,\n input [3:0] input_signal,\n input [63:0] config_state_map_flat,\n input [127:0] config_transition_map_flat,\n output reg [7:0] current_state,\n output reg error_flag,\n output reg [7:0] operation_result\n);\n\n \n reg [7:0] state;\n reg [7:0] next_state;\n \n wire [7:0] config_state_map0 = config_state_map_flat[7:0];\n wire [7:0] config_state_map1 = config_state_map_flat[15:8];\n wire [7:0] config_state_map2 = config_state_map_flat[23:16];\n wire [7:0] config_state_map3 = config_state_map_flat[31:24];\n wire [7:0] config_state_map4 = config_state_map_flat[39:32];\n wire [7:0] config_state_map5 = config_state_map_flat[47:40];\n wire [7:0] config_state_map6 = config_state_map_flat[55:48];\n wire [7:0] config_state_map7 = config_state_map_flat[63:56];\n\n always @(posedge clk or posedge reset) begin\n if (reset) begin\n state <= 0;\n current_state <= 0;\n error_flag <= 0;\n end else begin\n state <= next_state;\n current_state <= next_state;\n end\n end\n\n always @(*) begin\n integer idx;\n idx = (state << 4) + input_signal; \n next_state = config_transition_map_flat[(idx * 8) + 7 -: 8];\n \n if (next_state > 8'h7) begin\n error_flag = 1;\n next_state = 0; \n end else begin\n error_flag = 0;\n end\n\n case (state)\n 8'h0: operation_result = config_state_map0 + input_signal;\n 8'h1: operation_result = config_state_map1 - input_signal;\n 8'h2: operation_result = config_state_map2 & input_signal;\n 8'h3: operation_result = config_state_map3 | input_signal;\n default: operation_result = 8'hFF; \n endcase\n end\n\nendmodule", + "verif/fsm_tb.sv": "`timescale 1ns/1ps\nmodule fsm_tb;\n\n reg clk;\n reg reset;\n reg [3:0] input_signal;\n reg [63:0] config_state_map_flat;\n reg [127:0] config_transition_map_flat;\n wire [7:0] encoded_state;\n wire [7:0] dynamic_encoded_state;\n wire error_flag;\n wire [7:0] operation_result;\n \n \n fsm dut (\n .clk(clk),\n .reset(reset),\n .input_signal(input_signal),\n .config_state_map_flat(config_state_map_flat),\n .config_transition_map_flat(config_transition_map_flat),\n .encoded_state(encoded_state),\n .dynamic_encoded_state(dynamic_encoded_state),\n .error_flag(error_flag),\n .operation_result(operation_result)\n );\n \n \n initial begin\n clk = 0;\n forever #5 clk = ~clk;\n end\n \n \n initial begin\n $dumpfile(\"fsm_tb.vcd\");\n $dumpvars(0, fsm_tb);\n \n config_state_map_flat = {8'h80, 8'h70, 8'h60, 8'h50, 8'h40, 8'h30, 8'h20, 8'h10};\n \n config_transition_map_flat = { \n 8'h0, \n 8'h0, \n 8'h0, \n 8'h0, \n 8'h0, \n 8'h0, \n 8'h0, \n 8'h0, \n 8'h0, \n 8'h0, \n 8'h0, \n 8'h8, \n 8'h0, \n 8'h0, \n 8'h0, \n 8'h0 \n };\n \n \n reset = 1;\n input_signal = 4'b0;\n #12;\n reset = 0;\n #10;\n \n \n input_signal = 4'h1;\n #10;\n $display(\"Test 1: encoded_state = %0h, dynamic_encoded_state = %0h, error_flag = %b, operation_result = %0d\", \n encoded_state, dynamic_encoded_state, error_flag, operation_result);\n \n \n input_signal = 4'h2;\n #10;\n $display(\"Test 2: encoded_state = %0h, dynamic_encoded_state = %0h, error_flag = %b, operation_result = %0d\", \n encoded_state, dynamic_encoded_state, error_flag, operation_result);\n \n \n input_signal = 4'h3;\n #10;\n $display(\"Test 3: encoded_state = %0h, dynamic_encoded_state = %0h, error_flag = %b, operation_result = %0d\", \n encoded_state, dynamic_encoded_state, error_flag, operation_result);\n \n \n input_signal = 4'h4;\n #10;\n $display(\"Test 4 (error): encoded_state = %0h, dynamic_encoded_state = %0h, error_flag = %b, operation_result = %0d\", \n encoded_state, dynamic_encoded_state, error_flag, operation_result);\n \n \n input_signal = 4'h0;\n #10;\n $display(\"Test 5: encoded_state = %0h, dynamic_encoded_state = %0h, error_flag = %b, operation_result = %0d\", \n encoded_state, dynamic_encoded_state, error_flag, operation_result);\n \n $finish;\n end\n\nendmodule", + "rtl/CA_1.sv": null, + "rtl/CA_2.sv": null, + "rtl/CA_3.sv": null, + "rtl/CA_4.sv": null, + "rtl/rgb_color_space_conversion.sv": null, + "rtl/APBGlobalHistoryRegister.v": null, + "docs/signed_comparator_specification.md": null, + "verif/signed_comparator_tb.sv": null, + "rtl/sorting_engine.sv": null, + "rtl/brick_sort.sv": null, + "rtl/bubble_sort.sv": null, + "rtl/merge_sort.sv": null, + "rtl/selection_sort.sv": null + } + }, + { + "id": "cvdp_agentic_rc5_0001", + "index": 562, + "source_config": "cvdp_agentic_code_generation_no_commercial", + "instruction": "Context: You are a language model that has the following file operations available at your disposal:\n - **List files in a directory** by running one of the following commands: \n - `ls`\n - `tree`\n - **Read files** by using:\n - `cat `\n - **Write files** by using:\n - `echo > `\n - **Compile Verilog** by using `iverilog` such as:\n - `iverilog -o .out -g2012 `\n - **Run Simulation** by using:\n - `vvp .out`\n - **Update the file content** by using:\n - `sed -i '3s/old/new/' file.txt`\n - **Find current working directory** by using:\n - `pwd`\n\n You will be given a prompt and your task is to understand it and solve the given issue by using the commands mentioned above as needed. In the final step, you should create a Linux patch highlighting the necessary file updates to achieve the targeted goal.\n\n You will solve the problem step by step using the following approach of \n - thought (thinking process of the step you're going to take)\n - action (the command you will be running to get more details/context that's helpful to solve the problem)\n - observation (the output from the action you will observe based on which you will take your next step)\n\n The last step will be the final output summary and the patch itself in the following format \n - thought (the summary of what you did and some introduction of the patch file itself)\n - patch (a Linux-based patch that needs to be applied to reach the relevant solution)\n\n The patch file should only be applied to a single file to reach the required solution.\n\nTask: RTL module `rc5_enc_16bit` in `rtl` directory for a RC5 symmetric block-cipher encryption process based on the following specification and functionality. The must support encryption of 16-bit plaintext input. The RTL may assume one round of operation for encryption. The number of S-box variables and their values to be incorporated for encryption can be chosen accordingly. Following interface details have to be used for RTL of RC5 encryption.\n\n## Interface details\n\n### Inputs:\n- **clock (1-bit)**: A single-bit input clock that drives the Finite State Machine executing the encryption algorithm at the positive edge. The clock typically has a 50:50 duty cycle.\n- **reset (1-bit)**: A control signal that resets the internal states of the encryption system. The reset can be configured as synchronous active low signal.\n- **enc_start (1-bit)**: After this signal becomes HIGH, the encryption process begins\n- **p (16-bit,[15:0])** : The 16-bit plaintext input of RC5 encryption \n\n### Output:\n- **c (16-bit,[15:0])** : The 16-bit ciphertext output of RC5 encryption \n- **enc_done (1-bit)**: A HIGH in this output signal indicates the end of RC5 encryption and stable output at `c`, the ciphertext output\n\n## Functionality\n\n### RC5 Encryption algorithm\n\n- The RC5 algorithm is a symmetric block cipher known for its simplicity and effectiveness in converting plaintext to ciphertext and vice versa. \n- It offers flexible options for adjusting block size, key size, and the number of encryption rounds. \n- The RC5 algorithm employs operations such as modulo addition, left rotation, modulo subtraction, right rotation, and XOR in its encryption and decryption processes.\n\nIn order to understand the RC5 block cipher encryption, the following parameters are needed:\n1. Plaintext (P)\n2. Plaintext as w-bit registers (A & B)\n2. Data width (2w)\n3. S-box key array (S)\n4. Rounds of operation (r)\n5. Ciphertext (C)\n\nThe RC5 encryption algorithm works as follows:\n\nA = A + S[0];\\\nB = B + S[1];\\\nfor i = 1 to r do\\\n    A = ((A XOR B) <<< B) + S[2×i];\\\n    B = ((B XOR A) <<< A) + S[(2×i)+1];\\\nC = {A,B}\n\nHere, <<< : Left rotation; + : Modulo 2w addition; A : MSB w-bits of plaintext P;\\\nB : LSB w-bits of plaintext P; S[0],S[1],S[2],....... : S-box keys ; {} : Concatenation\n\nAt the beginning of encryption, the MSB w-bits of plaintext are assumed as A, and the LSB w-bits of plaintext as B. Every step of this algorithm has to be carried out sequentially as the subsequent steps utilize the result of previous computations. Even though the encryption can be carried out on any data width, the recommended plaintext widths are 16,32 or 64. The number of S-box keys for the encryption is 2*(r+1), where 'r' represents the number of rounds. As the number of rounds increases, the algorithm requires more number of S-box keys. In general, S-box keys are assumed by the user during the encryption process which need to be shared for executing the decryption.\n\n## Considerations\n\n- The RTL specifically should encrypt 16-bit data using four 8-bit S-box constants to meet operational needs. \n- Encryption has to be performed by a Finite State Machine (FSM) that completes one round of the RC5 algorithm in four clock cycles. The FSM progresses through four states: initial addition, computation of the most significant 8-bits (MSB), computation of the least significant 8-bits (LSB), and finally, output of the ciphertext. The system has to operate on 2w bits, where w is 8, fitting the 16-bit encryption scheme.\n- The encryption process requires 2(r+1) S-box entries, where r represents the number of rounds. Since the RTL module for RC5 encryption has to operate with a single round, it can incorporate four 8-bit S-box entries. These S-box entries, based on ssumptions, are to be set as follows:\n - Cellular Automata for PRNG: Develop a Cellular Automata-based PRNG specifically designed to four 8-bit random values. These values will be used as S-box keys in the RC5 encryption process.\n - Ensure that the Cellular Automata configuration is capable of generating maximal length sequences. This is crucial for maintaining high entropy in the key stream and enhancing the cryptographic strength of the RC5 cipher.\n - combination of Rule 90 and Rule 150 in your Cellular Automata design. These rules are selected for their properties in producing complex, pseudorandom patterns, suitable for cryptographic applications.\n - Rule 90: A simple XOR of each cell with its two immediate neighbors (i.e., left and right cells).\n - Rule 150: Involves XORing each cell with its left and right neighbors and itself, resulting in a more complex pattern.\n - The CA based PRNG has to be constructed with a combination of rules R90-R90-R150-R90-R150-R90-R150-R90 with 8-bit seed of 8'hFF\n - This CA should be capable of generating (28 - 1) pseudorandom sequences.\n- The encryption shall employ arithmetic and logical operations such as modulo 256 addition, left rotation, and XOR. These operations have to be executed sequentially, as each step of the algorithm depends on the output from the previous step to the 16-bit ciphertext.\n\n## Working example \n\n### RC5 Encryption\n\nLet us consider the following parameters:\n\nP = 16'hFFFF ; w = 8 ; r = 1 ; S[0] = 8'h20;S[1] = 8'h10;S[2] = 8'hFF;S[3] = 8'hFF;\n\nSolution:\n\nA = 8'hFF; B = 8'hFF\n\nA = (8'hFF + 8'h20) mod 256 = 1F\\\nB = (8'hFF + 8'h10) mod 256 = 0F\n\n(Loop computation)\\\n    A = (((8'h1F XOR 8'h0F) <<< 8'h0F) + 8'hFF) mod 256 = (8'h08 + 8'hFF) mod 256 = 8'h07\\\n    B = (((8'h0F XOR 8'h07) <<< 8'h07) + 8'hFF) mod 256 = (8'h04 + 8'hFF) mod 256 = 8'h03\n\nThe ciphertext output is C = 16'h0703\n\nThe `rtl` directory has four different CA implementations namely `CA_1.sv`, `CA_2.sv`, `CA_3.sv`, and `CA_4.sv` and choose the appropriate CA S-box generation.", + "verilog_code": { + "code_block_2_0": "module `rc5_enc_16bit` in `rtl` directory for a RC5 symmetric block-cipher encryption process based on the following specification and functionality. The design must support encryption of 16-bit plaintext input. The RTL design may assume one round of operation for encryption. The number of S-box variables and their values to be incorporated for encryption can be chosen accordingly. Following interface details have to be used for RTL design of RC5 encryption.\n\n## Interface details\n\n### Inputs:\n- **clock (1-bit)**: A single-bit input clock that drives the Finite State Machine executing the encryption algorithm at the positive edge. The clock typically has a 50:50 duty cycle.\n- **reset (1-bit)**: A control signal that resets the internal states of the encryption system. The reset can be configured as synchronous active low signal.\n- **enc_start (1-bit)**: After this signal becomes HIGH, the encryption process begins\n- **p (16-bit,[15:0])** : The 16-bit plaintext input of RC5 encryption \n\n### Output:\n- **c (16-bit,[15:0])** : The 16-bit ciphertext output of RC5 encryption \n- **enc_done (1-bit)**: A HIGH in this output signal indicates the end of RC5 encryption and stable output at `c`, the ciphertext output\n\n## Functionality\n\n### RC5 Encryption algorithm\n\n- The RC5 algorithm is a symmetric block cipher known for its simplicity and effectiveness in converting plaintext to ciphertext and vice versa. \n- It offers flexible options for adjusting block size, key size, and the number of encryption rounds. \n- The RC5 algorithm employs operations such as modulo addition, left rotation, modulo subtraction, right rotation, and XOR in its encryption and decryption processes.\n\nIn order to understand the RC5 block cipher encryption, the following parameters are needed:\n1. Plaintext (P)\n2. Plaintext as w-bit registers (A & B)\n2. Data width (2w)\n3. S-box key array (S)\n4. Rounds of operation (r)\n5. Ciphertext (C)\n\nThe RC5 encryption algorithm works as follows:\n\nA = A + S[0];\\", + "code_block_2_1": "output of the ciphertext. The system has to operate on 2w bits, where w is 8, fitting the 16-bit encryption scheme.\n- The encryption process requires 2(r+1) S-box entries, where r represents the number of rounds. Since the RTL module for RC5 encryption has to operate with a single round, it can incorporate four 8-bit S-box entries. These S-box entries, based on design assumptions, are to be set as follows:\n - Implement Cellular Automata for PRNG: Develop a Cellular Automata-based PRNG specifically designed to generate four 8-bit random values. These values will be used as S-box keys in the RC5 encryption process.\n - Ensure that the Cellular Automata configuration is capable of generating maximal length sequences. This is crucial for maintaining high entropy in the key stream and enhancing the cryptographic strength of the RC5 cipher.\n - Implement a combination of Rule 90 and Rule 150 in your Cellular Automata design. These rules are selected for their properties in producing complex, pseudorandom patterns, suitable for cryptographic applications.\n - Rule 90: A simple XOR of each cell with its two immediate neighbors (i.e., left and right cells).\n - Rule 150: Involves XORing each cell with its left and right neighbors and itself, resulting in a more complex pattern.\n - The CA based PRNG has to be constructed with a combination of rules R90-R90-R150-R90-R150-R90-R150-R90 with 8-bit seed of 8'hFF\n - This CA should be capable of generating (28 - 1) pseudorandom sequences.\n- The encryption shall employ arithmetic and logical operations such as modulo 256 addition, left rotation, and XOR. These operations have to be executed sequentially, as each step of the algorithm depends on the output from the previous step to generate the 16-bit ciphertext.\n\n## Working example \n\n### RC5 Encryption\n\nLet us consider the following parameters:\n\nP = 16'hFFFF ; w = 8 ; r = 1 ; S[0] = 8'h20;S[1] = 8'h10;S[2] = 8'hFF;S[3] = 8'hFF;", + "code_block_2_2": "output is C = 16'h0703\n\nThe `rtl` directory has four different CA implementations namely `CA_1.sv`, `CA_2.sv`, `CA_3.sv`, and `CA_4.sv` and choose the appropriate CA design for S-box generation.\n {'docs/specification.md': None, 'rtl/decoder_data_control_64b66b.sv': None, 'rtl/encoder_control_64b66b.sv': None, 'rtl/encoder_data_64b66b.sv': None, 'rtl/aes128_encrypt.sv': None, 'verif/tb_aes128_enc.sv': None, 'rtl/aes128_decrypt.sv': None, 'rtl/aes128_key_expansion.sv': None, 'rtl/inv_sbox.sv': None, 'rtl/sbox.sv': None, 'verif/tb_aes128_dec.sv': None, 'rtl/aes_encrypt.sv': None, 'verif/tb_aes_encrypt.sv': None, 'rtl/aes_decrypt.sv': None, 'rtl/aes_ke.sv': None, 'verif/tb_aes_decrypt.sv': None, 'rtl/aes_dec_top.sv': None, 'rtl/aes_enc_top.sv': None, 'verif/tb_padding_top.sv': None, 'verif/tb_des_enc.sv': None, 'docs/Key_schedule.md': None, 'docs/Permutations.md': None, 'docs/S_box_creation.md': None, 'rtl/S1.sv': None, 'rtl/S2.sv': None, 'rtl/S3.sv': None, 'rtl/S4.sv': None, 'rtl/S5.sv': None, 'rtl/S6.sv': None, 'rtl/S7.sv': None, 'rtl/S8.sv': None, 'rtl/des_enc.sv': None, 'verif/tb_des_dec.sv': None, 'docs/Encryption.md': None, 'rtl/des_dec.sv': None, 'verif/tb_3des_enc.sv': None, 'verif/tb_3des_dec.sv': None, 'docs/min_hamming_distance_finder_spec.md': None, 'rtl/Bit_Difference_Counter.sv': None, 'rtl/Bitwise_Reduction.sv': None, 'rtl/Data_Reduction.sv': None, 'verif/tb_Min_Hamming_Distance_Finder.sv': None, 'docs/specs.md': None, 'rtl/arithmetic_progression_generator.sv': None, 'docs/algorithms.md': None, 'docs/coeff_update_spec.md': None, 'docs/equalizer_spec.md': None, 'docs/error_calc_spec.md': None, 'rtl/coeff_update.sv': None, 'rtl/dynamic_equalizer.sv': None, 'rtl/error_calc.sv': None, 'docs/awgn_spec.md': None, 'docs/equalizer_top_spec.md': None, 'rtl/elevator_control_system.sv': None, 'docs/tx_specification.md': None, 'rtl/ethernet_fifo_cdc.sv': None, 'docs/tx_mac_specification.md': None, 'verif/event_scheduler_tb.sv': None, 'docs/modified_specs.md': None, 'rtl/event_scheduler.sv': None, 'verif/tb_event_scheduler.sv': None, 'rtl/column_selector.sv': None, 'rtl/event_storage.sv': None, 'verif/tb.sv': None, 'rtl/fixed_priority_arbiter.sv': None, 'verif/fixed_priority_arbiter_tb.sv': None, 'docs/Modified_specification.md': None, 'docs/GCD_specification.md': None, 'docs/crypto_accelerator_specification.md': None, 'docs/modular_exponentiation_specification.md': None, 'docs/modular_multiplier_specification.md': None, 'rtl/gcd_controlpath_3.sv': None, 'rtl/gcd_controlpath_4.sv': None, 'rtl/gcd_datapath_5.sv': None, 'rtl/gcd_datapath_6.sv': None, 'rtl/gcd_top_1.sv': None, 'rtl/gcd_top_2.sv': None, 'rtl/modular_exponentiation.sv': None, 'rtl/modular_multiplier.sv': None, 'rtl/lfsr_8bit.sv': None, 'verif/lfsr_8bit_tb.sv': None, 'rtl/bit16_lfsr.sv': None, 'rtl/low_power_ctrl.sv': None, 'rtl/sync_fifo.sv': None, 'verif/tb_low_power_channel.sv': None, 'rtl/cross_domain_sync.sv': None, 'rtl/dsp_input_stage.sv': None, 'rtl/dsp_output_stage.sv': None, 'rtl/lfsr_generator.sv': None, 'rtl/monte_carlo_dsp_monitor_top.sv': None, 'verif/monte_carlo_dsp_monitor_top_tb.sv': None, 'docs/multiplexer_specification.md': None, 'verif/multiplexer_tb.sv': None, 'docs/nbit_swizzling_spec.md': None, 'verif/nbit_swizzling_tb.sv': None, 'docs/nmea_decoder_spec.md': None, 'rtl/nmea_decoder.sv': None, 'verif/nmea_decoder_tb.sv': None, 'docs/fifo.md': None, 'rtl/fifo_memory.sv': None, 'rtl/read_to_write_pointer_sync.sv': None, 'rtl/rptr_empty.sv': None, 'rtl/wptr_full.sv': None, 'rtl/write_to_read_pointer_sync.sv': None, 'docs/spec.md': None, 'verif/async_filo_tb.sv': None, 'docs/axilite_to_pcie_config_module.md': None, 'rtl/axi4lite_to_pcie_cfg_bridge.sv': None, 'rtl/axis_broadcast.sv': None, 'verif/tb_axis_broadcast.sv': None, 'docs/axis_to_uart_tx_specs.md': None, 'docs/uart_rx_to_axis_specs.md': None, 'rtl/barrel_shifter.sv': None, 'verif/barrel_shifter_tb.sv': None, 'rtl/bcd_adder.sv': None, 'rtl/full_adder.sv': None, 'rtl/four_bit_adder.sv': None, 'rtl/search_binary_search_tree.sv': None, 'rtl/delete_node_binary_search_tree.sv': None, 'docs/bst_operations.md': None, 'rtl/binary_search_tree_sort_construct.sv': None, 'docs/Spec.md': None, 'verif/tb_binary_to_gray.sv': None, 'verif/tb_custom_byte_enable_ram.sv': None, 'verif/cache_controller_tb.sv': None, 'rtl/caesar_cipher.sv': None, 'verif/caesar_cipher_tb.sv': None, 'verif/tb_pseudoRandGenerator_ca.sv': None, 'docs/continuous_adder_specification.md': None, 'verif/continuous_adder_tb.sv': None, 'rtl/fifo_buffer.sv': None, 'verif/tb_fifo_buffer.sv': None, 'docs/direct_map_cache_spec.md': None, 'verif/tb_direct_map_cache.sv': None, 'rtl/direct_map_cache.sv': None, 'rtl/dual_port_memory.sv': None, 'rtl/gen_cos_sin_lut.sv': None, 'rtl/phase_lut.sv': None, 'rtl/phase_rotation.sv': None, 'rtl/power4.sv': None, 'rtl/saturation.sv': None, 'rtl/top_phase_rotation.sv': None, 'docs/spec_viterbi.md': None, 'docs/spec_slicer_top.md': None, 'docs/spec_top_phase_rotation.md': None, 'rtl/slicer.sv': None, 'rtl/slicer_top.sv': None, 'docs/swizzler_specification.md': None, 'verif/swizzler_tb.sv': None, 'rtl/swizzler.sv': None, 'docs/sync_serial_communication_tx_rx_spec.md': None, 'verif/sync_serial_communication_tb.sv': None, 'rtl/weight_stationary_pe.sv': None, 'verif/systolic_array_tb.sv': None, 'rtl/thermostat.v': None, 'docs/Traffic_controller.md': None, 'rtl/traffic_light_controller.sv': None, 'docs/Universal_Shift_Register_spec.md': None, 'verif/tb_universal_shift_register.sv': None, 'rtl/universal_shift_register.sv': None, 'docs/spec_conj.md': None, 'docs/spec_cross_correlation.md': None, 'docs/spec_detect_sequence.md': None, 'rtl/adder_2d_layers.sv': None, 'rtl/adder_tree_2d.sv': None, 'rtl/correlate.sv': None, 'rtl/cross_correlation.sv': None, 'docs/valid_modes.md': None, 'docs/words_counting.md': None, 'rtl/detect_sequence.sv': None, 'docs/proc_fsm_spec.md': None, 'docs/adder_tree.md': None, 'docs/coeff_ram.md': None, 'docs/poly_decimator.md': None, 'docs/poly_filter.md': None, 'docs/shift_register.md': None, 'rtl/adder_tree.sv': None, 'rtl/coeff_ram.sv': None, 'rtl/poly_filter.sv': None, 'rtl/shift_register.sv': None, 'docs/prbs_specification.md': None, 'rtl/prbs_gen_check.sv': None, 'rtl/fsm.sv': None, 'verif/fsm_tb.sv': None, 'rtl/CA_1.sv': 'module CA_1(\\n\\tinput wire clock,\\t\\t//Clock input\\n\\tinput wire reset,\\t\\t//Reset input\\n\\tinput wire [7:0] CA_seed, \\t//8-bit Cellular Automata (CA) seed\\n\\toutput reg [7:0] CA_out); \\t//8-bit CA output\\n\\t\\n\\twire q1,q2,q3,q4,q5,q6,q7,q8;\\n\\t\\n\\t//Rule combination considered for 8-bit CA is R90-R90-R150-R90-R150-R90-R150-R90\\n\\t\\n\\t//Internal XORing based on rules 90 and 150 combination\\n\\tassign q1 = CA_out[6]; \\t\\t\\t\\t//R90\\n\\tassign q2 = CA_out[7] ^ CA_out[5]; \\t\\t//R90\\n\\tassign q3 = CA_out[6] ^ CA_out[5] ^ CA_out[4]; \\t//R150\\n\\tassign q4 = CA_out[5] ^ CA_out[3]; \\t\\t//R90\\n\\tassign q5 = CA_out[4] ^ CA_out[3] ^ CA_out[2]; \\t//R150\\n\\tassign q6 = CA_out[3] ^ CA_out[1]; \\t\\t//R90\\n\\tassign q7 = CA_out[2] ^ CA_out[1] ^ CA_out[0]; \\t//R150\\n\\tassign q8 = CA_out[1]; \\t\\t\\t\\t//R90\\n\\n\\talways_ff @(posedge clock)\\n\\tbegin\\n\\t\\tif (reset) //If reset is HIGH, 8-bit CA seed will be initialised at CA output\\n\\t\\t\\tCA_out <= CA_seed;\\n\\t\\telse\\n\\t\\t\\tCA_out <= {q1,q2,q3,q4,q5,q6,q7,q8}; //Shift register based on the CA rules\\n\\tend\\nendmodule', 'rtl/CA_2.sv': 'module CA_2(\\n\\tinput wire clock,\\t\\t//Clock input\\n\\tinput wire reset,\\t\\t//Reset input\\n\\tinput wire [7:0] CA_seed, \\t//8-bit Cellular Automata (CA) seed\\n\\toutput reg [7:0] CA_out); \\t//8-bit CA output\\n\\t\\n\\twire q1,q2,q3,q4,q5,q6,q7,q8;\\n\\t\\n\\t//Rule combination considered for 8-bit CA is R150-R90-R150-R90-R150-R90-R150-R150\\n\\t\\n\\t//Internal XORing based on rules 90 and 150 combination\\n\\tassign q1 = CA_out[7] ^ CA_out[6]; \\t\\t//R150\\n\\tassign q2 = CA_out[7] ^ CA_out[5]; \\t\\t//R90\\n\\tassign q3 = CA_out[6] ^ CA_out[5] ^ CA_out[4]; \\t//R150\\n\\tassign q4 = CA_out[5] ^ CA_out[3]; \\t\\t//R90\\n\\tassign q5 = CA_out[4] ^ CA_out[3] ^ CA_out[2]; \\t//R150\\n\\tassign q6 = CA_out[3] ^ CA_out[1]; \\t\\t//R90\\n\\tassign q7 = CA_out[2] ^ CA_out[1] ^ CA_out[0]; \\t//R150\\n\\tassign q8 = CA_out[1] ^ CA_out[0];; \\t//R150\\n\\n\\talways_ff @(posedge clock)\\n\\tbegin\\n\\t\\tif (reset) //If reset is HIGH, 8-bit CA seed will be initialised at CA output\\n\\t\\t\\tCA_out <= CA_seed;\\n\\t\\telse\\n\\t\\t\\tCA_out <= {q1,q2,q3,q4,q5,q6,q7,q8}; //Shift register based on the CA rules\\n\\tend\\nendmodule', 'rtl/CA_3.sv': 'module CA_3(\\n\\tinput wire clock,\\t\\t//Clock input\\n\\tinput wire reset,\\t\\t//Reset input\\n\\tinput wire [7:0] CA_seed, \\t//8-bit Cellular Automata (CA) seed\\n\\toutput reg [7:0] CA_out); \\t//8-bit CA output\\n\\t\\n\\twire q1,q2,q3,q4,q5,q6,q7,q8;\\n\\t\\n\\t//Rule combination considered for 8-bit CA is R150-R150-R90-R150-R90-R150-R90-R150\\n\\t\\n\\t//Internal XORing based on rules 90 and 150 combination\\n assign q1 = CA_out[7] ^ CA_out[6]; \\t\\t\\t\\t //R150\\n assign q2 = CA_out[7] ^ CA_out[6] ^ CA_out[5]; \\t\\t//R150\\n assign q3 = CA_out[6] ^ CA_out[4]; \\t //R90\\n assign q4 = CA_out[5] ^ CA_out[4] ^ CA_out[3]; \\t\\t//R150\\n assign q5 = CA_out[4] ^ CA_out[2]; \\t//R90\\n assign q6 = CA_out[3] ^ CA_out[2] ^ CA_out[1]; \\t\\t//R150\\n assign q7 = CA_out[2] ^ CA_out[0]; \\t //R90\\n assign q8 = CA_out[1] ^ CA_out[0]; \\t\\t\\t\\t //R150\\n\\n\\talways_ff @(posedge clock)\\n\\tbegin\\n\\t\\tif (reset) //If reset is HIGH, 8-bit CA seed will be initialised at CA output\\n\\t\\t\\tCA_out <= CA_seed;\\n\\t\\telse\\n\\t\\t\\tCA_out <= {q1,q2,q3,q4,q5,q6,q7,q8}; //Shift register based on the CA rules\\n\\tend\\nendmodule', 'rtl/CA_4.sv': 'module CA_4(\\n\\tinput wire clock,\\t\\t//Clock input\\n\\tinput wire reset,\\t\\t//Reset input\\n\\tinput wire [7:0] CA_seed, \\t//8-bit Cellular Automata (CA) seed\\n\\toutput reg [7:0] CA_out); \\t//8-bit CA output\\n\\t\\n\\twire q1,q2,q3,q4,q5,q6,q7,q8;\\n\\t\\n\\t//Rule combination considered for 8-bit CA is R90-R90-R90-R150-R90-R150-R90-R150\\n\\t\\n\\t//Internal XORing based on rules 90 and 150 combination\\n assign q1 = CA_out[6]; \\t\\t\\t\\t //R90\\n assign q2 = CA_out[7] ^ CA_out[5]; \\t\\t //R90\\n assign q3 = CA_out[6] ^ CA_out[4]; \\t //R90\\n assign q4 = CA_out[5] ^ CA_out[4] ^ CA_out[3]; \\t\\t//R150\\n assign q5 = CA_out[4] ^ CA_out[2]; \\t//R90\\n assign q6 = CA_out[3] ^ CA_out[2] ^ CA_out[1]; \\t\\t//R150\\n assign q7 = CA_out[2] ^ CA_out[0]; \\t //R90\\n assign q8 = CA_out[1] ^ CA_out[0]; \\t\\t\\t\\t //R150\\n\\n\\talways_ff @(posedge clock)\\n\\tbegin\\n\\t\\tif (reset) //If reset is HIGH, 8-bit CA seed will be initialised at CA output\\n\\t\\t\\tCA_out <= CA_seed;\\n\\t\\telse\\n\\t\\t\\tCA_out <= {q1,q2,q3,q4,q5,q6,q7,q8}; //Shift register based on the CA rules\\n\\tend\\nendmodule', 'rtl/rgb_color_space_conversion.sv': None, 'rtl/APBGlobalHistoryRegister.v': None, 'docs/signed_comparator_specification.md': None, 'verif/signed_comparator_tb.sv': None, 'rtl/sorting_engine.sv': None, 'rtl/brick_sort.sv': None, 'rtl/bubble_sort.sv': None, 'rtl/merge_sort.sv': None, 'rtl/selection_sort.sv': None}", + "rtl/CA_1.sv": "module CA_1(\n\tinput wire clock,\t\t//Clock input\n\tinput wire reset,\t\t//Reset input\n\tinput wire [7:0] CA_seed, \t//8-bit Cellular Automata (CA) seed\n\toutput reg [7:0] CA_out); \t//8-bit CA output\n\t\n\twire q1,q2,q3,q4,q5,q6,q7,q8;\n\t\n\t//Rule combination considered for 8-bit CA is R90-R90-R150-R90-R150-R90-R150-R90\n\t\n\t//Internal XORing based on rules 90 and 150 combination\n\tassign q1 = CA_out[6]; \t\t\t\t//R90\n\tassign q2 = CA_out[7] ^ CA_out[5]; \t\t//R90\n\tassign q3 = CA_out[6] ^ CA_out[5] ^ CA_out[4]; \t//R150\n\tassign q4 = CA_out[5] ^ CA_out[3]; \t\t//R90\n\tassign q5 = CA_out[4] ^ CA_out[3] ^ CA_out[2]; \t//R150\n\tassign q6 = CA_out[3] ^ CA_out[1]; \t\t//R90\n\tassign q7 = CA_out[2] ^ CA_out[1] ^ CA_out[0]; \t//R150\n\tassign q8 = CA_out[1]; \t\t\t\t//R90\n\n\talways_ff @(posedge clock)\n\tbegin\n\t\tif (reset) //If reset is HIGH, 8-bit CA seed will be initialised at CA output\n\t\t\tCA_out <= CA_seed;\n\t\telse\n\t\t\tCA_out <= {q1,q2,q3,q4,q5,q6,q7,q8}; //Shift register based on the CA rules\n\tend\nendmodule", + "rtl/CA_2.sv": "module CA_2(\n\tinput wire clock,\t\t//Clock input\n\tinput wire reset,\t\t//Reset input\n\tinput wire [7:0] CA_seed, \t//8-bit Cellular Automata (CA) seed\n\toutput reg [7:0] CA_out); \t//8-bit CA output\n\t\n\twire q1,q2,q3,q4,q5,q6,q7,q8;\n\t\n\t//Rule combination considered for 8-bit CA is R150-R90-R150-R90-R150-R90-R150-R150\n\t\n\t//Internal XORing based on rules 90 and 150 combination\n\tassign q1 = CA_out[7] ^ CA_out[6]; \t\t//R150\n\tassign q2 = CA_out[7] ^ CA_out[5]; \t\t//R90\n\tassign q3 = CA_out[6] ^ CA_out[5] ^ CA_out[4]; \t//R150\n\tassign q4 = CA_out[5] ^ CA_out[3]; \t\t//R90\n\tassign q5 = CA_out[4] ^ CA_out[3] ^ CA_out[2]; \t//R150\n\tassign q6 = CA_out[3] ^ CA_out[1]; \t\t//R90\n\tassign q7 = CA_out[2] ^ CA_out[1] ^ CA_out[0]; \t//R150\n\tassign q8 = CA_out[1] ^ CA_out[0];; \t//R150\n\n\talways_ff @(posedge clock)\n\tbegin\n\t\tif (reset) //If reset is HIGH, 8-bit CA seed will be initialised at CA output\n\t\t\tCA_out <= CA_seed;\n\t\telse\n\t\t\tCA_out <= {q1,q2,q3,q4,q5,q6,q7,q8}; //Shift register based on the CA rules\n\tend\nendmodule", + "rtl/CA_3.sv": "module CA_3(\n\tinput wire clock,\t\t//Clock input\n\tinput wire reset,\t\t//Reset input\n\tinput wire [7:0] CA_seed, \t//8-bit Cellular Automata (CA) seed\n\toutput reg [7:0] CA_out); \t//8-bit CA output\n\t\n\twire q1,q2,q3,q4,q5,q6,q7,q8;\n\t\n\t//Rule combination considered for 8-bit CA is R150-R150-R90-R150-R90-R150-R90-R150\n\t\n\t//Internal XORing based on rules 90 and 150 combination\n assign q1 = CA_out[7] ^ CA_out[6]; \t\t\t\t //R150\n assign q2 = CA_out[7] ^ CA_out[6] ^ CA_out[5]; \t\t//R150\n assign q3 = CA_out[6] ^ CA_out[4]; \t //R90\n assign q4 = CA_out[5] ^ CA_out[4] ^ CA_out[3]; \t\t//R150\n assign q5 = CA_out[4] ^ CA_out[2]; \t//R90\n assign q6 = CA_out[3] ^ CA_out[2] ^ CA_out[1]; \t\t//R150\n assign q7 = CA_out[2] ^ CA_out[0]; \t //R90\n assign q8 = CA_out[1] ^ CA_out[0]; \t\t\t\t //R150\n\n\talways_ff @(posedge clock)\n\tbegin\n\t\tif (reset) //If reset is HIGH, 8-bit CA seed will be initialised at CA output\n\t\t\tCA_out <= CA_seed;\n\t\telse\n\t\t\tCA_out <= {q1,q2,q3,q4,q5,q6,q7,q8}; //Shift register based on the CA rules\n\tend\nendmodule", + "rtl/CA_4.sv": "module CA_4(\n\tinput wire clock,\t\t//Clock input\n\tinput wire reset,\t\t//Reset input\n\tinput wire [7:0] CA_seed, \t//8-bit Cellular Automata (CA) seed\n\toutput reg [7:0] CA_out); \t//8-bit CA output\n\t\n\twire q1,q2,q3,q4,q5,q6,q7,q8;\n\t\n\t//Rule combination considered for 8-bit CA is R90-R90-R90-R150-R90-R150-R90-R150\n\t\n\t//Internal XORing based on rules 90 and 150 combination\n assign q1 = CA_out[6]; \t\t\t\t //R90\n assign q2 = CA_out[7] ^ CA_out[5]; \t\t //R90\n assign q3 = CA_out[6] ^ CA_out[4]; \t //R90\n assign q4 = CA_out[5] ^ CA_out[4] ^ CA_out[3]; \t\t//R150\n assign q5 = CA_out[4] ^ CA_out[2]; \t//R90\n assign q6 = CA_out[3] ^ CA_out[2] ^ CA_out[1]; \t\t//R150\n assign q7 = CA_out[2] ^ CA_out[0]; \t //R90\n assign q8 = CA_out[1] ^ CA_out[0]; \t\t\t\t //R150\n\n\talways_ff @(posedge clock)\n\tbegin\n\t\tif (reset) //If reset is HIGH, 8-bit CA seed will be initialised at CA output\n\t\t\tCA_out <= CA_seed;\n\t\telse\n\t\t\tCA_out <= {q1,q2,q3,q4,q5,q6,q7,q8}; //Shift register based on the CA rules\n\tend\nendmodule" + }, + "test_info": { + "test_criteria_2": [ + "encrypt 16-bit data using four 8-bit s-box constants to meet operational needs. \n- encryption has to be performed by a finite state machine (fsm) that completes one round of the rc5 algorithm in four clock cycles. the fsm progresses through four states: initial addition, computation of the most significant 8-bits (msb), computation of the least significant 8-bits (lsb), and finally, output of the ciphertext. the system has to operate on 2w bits, where w is 8, fitting the 16-bit encryption scheme.\n- the encryption process requires 2(r+1) s-box entries, where r represents the number of rounds. since the rtl module for rc5 encryption has to operate with a single round, it can incorporate four 8-bit s-box entries. these s-box entries, based on design assumptions, are to be set as follows:\n - implement cellular automata for prng: develop a cellular automata-based prng specifically designed to generate four 8-bit random values. these values will be used as s-box keys in the rc5 encryption process.\n - ensure that the cellular automata configuration is capable of generating maximal length sequences. this is crucial for maintaining high entropy in the key stream and enhancing the cryptographic strength of the rc5 cipher.\n - implement a combination of rule 90 and rule 150 in your cellular automata design. these rules are selected for their properties in producing complex, pseudorandom patterns, suitable for cryptographic applications.\n - rule 90: a simple xor of each cell with its two immediate neighbors (i.e., left and right cells).\n - rule 150: involves xoring each cell with its left and right neighbors and itself, resulting in a more complex pattern.\n - the ca based prng has to be constructed with a combination of rules r90-r90-r150-r90-r150-r90-r150-r90 with 8-bit seed of 8'hff\n - this ca should be capable of generating (28 - 1) pseudorandom sequences.\n- the encryption shall employ arithmetic and logical operations such as modulo 256 addition, left rotation, and xor. these operations have to be executed sequentially, as each step of the algorithm depends on the output from the previous step to generate the 16-bit ciphertext." + ] + }, + "expected_behavior": [ + "support encryption of 16-bit plaintext input", + "encrypt 16-bit data using four 8-bit S-box constants to meet operational needs", + "be used as S-box keys in the RC5 encryption process", + "be capable of generating (28 - 1) pseudorandom sequences", + ". The design must support encryption of 16-bit plaintext input. The RTL design may assume one round of operation for encryption. The number of S-box variables and their values to be incorporated for encryption can be chosen accordingly. Following interface details have to be used for RTL design of RC5 encryption.", + "### RC5 Encryption algorithm" + ], + "metadata": { + "categories": [ + "cid003", + "hard" + ], + "domain": "control", + "complexity": "expert", + "problem_type": "design", + "has_code": true, + "has_tests": true + }, + "full_prompt": "Design RTL module `rc5_enc_16bit` in `rtl` directory for a RC5 symmetric block-cipher encryption process based on the following specification and functionality. The design must support encryption of 16-bit plaintext input. The RTL design may assume one round of operation for encryption. The number of S-box variables and their values to be incorporated for encryption can be chosen accordingly. Following interface details have to be used for RTL design of RC5 encryption.\n\n## Interface details\n\n### Inputs:\n- **clock (1-bit)**: A single-bit input clock that drives the Finite State Machine executing the encryption algorithm at the positive edge. The clock typically has a 50:50 duty cycle.\n- **reset (1-bit)**: A control signal that resets the internal states of the encryption system. The reset can be configured as synchronous active low signal.\n- **enc_start (1-bit)**: After this signal becomes HIGH, the encryption process begins\n- **p (16-bit,[15:0])** : The 16-bit plaintext input of RC5 encryption \n\n### Output:\n- **c (16-bit,[15:0])** : The 16-bit ciphertext output of RC5 encryption \n- **enc_done (1-bit)**: A HIGH in this output signal indicates the end of RC5 encryption and stable output at `c`, the ciphertext output\n\n## Functionality\n\n### RC5 Encryption algorithm\n\n- The RC5 algorithm is a symmetric block cipher known for its simplicity and effectiveness in converting plaintext to ciphertext and vice versa. \n- It offers flexible options for adjusting block size, key size, and the number of encryption rounds. \n- The RC5 algorithm employs operations such as modulo addition, left rotation, modulo subtraction, right rotation, and XOR in its encryption and decryption processes.\n\nIn order to understand the RC5 block cipher encryption, the following parameters are needed:\n1. Plaintext (P)\n2. Plaintext as w-bit registers (A & B)\n2. Data width (2w)\n3. S-box key array (S)\n4. Rounds of operation (r)\n5. Ciphertext (C)\n\nThe RC5 encryption algorithm works as follows:\n\nA = A + S[0];\\\nB = B + S[1];\\\nfor i = 1 to r do\\\n    A = ((A XOR B) <<< B) + S[2×i];\\\n    B = ((B XOR A) <<< A) + S[(2×i)+1];\\\nC = {A,B}\n\nHere, <<< : Left rotation; + : Modulo 2w addition; A : MSB w-bits of plaintext P;\\\nB : LSB w-bits of plaintext P; S[0],S[1],S[2],....... : S-box keys ; {} : Concatenation\n\nAt the beginning of encryption, the MSB w-bits of plaintext are assumed as A, and the LSB w-bits of plaintext as B. Every step of this algorithm has to be carried out sequentially as the subsequent steps utilize the result of previous computations. Even though the encryption can be carried out on any data width, the recommended plaintext widths are 16,32 or 64. The number of S-box keys for the encryption is 2*(r+1), where 'r' represents the number of rounds. As the number of rounds increases, the algorithm requires more number of S-box keys. In general, S-box keys are assumed by the user during the encryption process which need to be shared for executing the decryption.\n\n## Considerations\n\n- The RTL design specifically should encrypt 16-bit data using four 8-bit S-box constants to meet operational needs. \n- Encryption has to be performed by a Finite State Machine (FSM) that completes one round of the RC5 algorithm in four clock cycles. The FSM progresses through four states: initial addition, computation of the most significant 8-bits (MSB), computation of the least significant 8-bits (LSB), and finally, output of the ciphertext. The system has to operate on 2w bits, where w is 8, fitting the 16-bit encryption scheme.\n- The encryption process requires 2(r+1) S-box entries, where r represents the number of rounds. Since the RTL module for RC5 encryption has to operate with a single round, it can incorporate four 8-bit S-box entries. These S-box entries, based on design assumptions, are to be set as follows:\n - Implement Cellular Automata for PRNG: Develop a Cellular Automata-based PRNG specifically designed to generate four 8-bit random values. These values will be used as S-box keys in the RC5 encryption process.\n - Ensure that the Cellular Automata configuration is capable of generating maximal length sequences. This is crucial for maintaining high entropy in the key stream and enhancing the cryptographic strength of the RC5 cipher.\n - Implement a combination of Rule 90 and Rule 150 in your Cellular Automata design. These rules are selected for their properties in producing complex, pseudorandom patterns, suitable for cryptographic applications.\n - Rule 90: A simple XOR of each cell with its two immediate neighbors (i.e., left and right cells).\n - Rule 150: Involves XORing each cell with its left and right neighbors and itself, resulting in a more complex pattern.\n - The CA based PRNG has to be constructed with a combination of rules R90-R90-R150-R90-R150-R90-R150-R90 with 8-bit seed of 8'hFF\n - This CA should be capable of generating (28 - 1) pseudorandom sequences.\n- The encryption shall employ arithmetic and logical operations such as modulo 256 addition, left rotation, and XOR. These operations have to be executed sequentially, as each step of the algorithm depends on the output from the previous step to generate the 16-bit ciphertext.\n\n## Working example \n\n### RC5 Encryption\n\nLet us consider the following parameters:\n\nP = 16'hFFFF ; w = 8 ; r = 1 ; S[0] = 8'h20;S[1] = 8'h10;S[2] = 8'hFF;S[3] = 8'hFF;\n\nSolution:\n\nA = 8'hFF; B = 8'hFF\n\nA = (8'hFF + 8'h20) mod 256 = 1F\\\nB = (8'hFF + 8'h10) mod 256 = 0F\n\n(Loop computation)\\\n    A = (((8'h1F XOR 8'h0F) <<< 8'h0F) + 8'hFF) mod 256 = (8'h08 + 8'hFF) mod 256 = 8'h07\\\n    B = (((8'h0F XOR 8'h07) <<< 8'h07) + 8'hFF) mod 256 = (8'h04 + 8'hFF) mod 256 = 8'h03\n\nThe ciphertext output is C = 16'h0703\n\nThe `rtl` directory has four different CA implementations namely `CA_1.sv`, `CA_2.sv`, `CA_3.sv`, and `CA_4.sv` and choose the appropriate CA design for S-box generation.\n", + "system_message": "You are a language model that has the following file operations available at your disposal:\n - **List files in a directory** by running one of the following commands: \n - `ls`\n - `tree`\n - **Read files** by using:\n - `cat `\n - **Write files** by using:\n - `echo > `\n - **Compile Verilog** by using `iverilog` such as:\n - `iverilog -o .out -g2012 `\n - **Run Simulation** by using:\n - `vvp .out`\n - **Update the file content** by using:\n - `sed -i '3s/old/new/' file.txt`\n - **Find current working directory** by using:\n - `pwd`\n\n You will be given a prompt and your task is to understand it and solve the given issue by using the commands mentioned above as needed. In the final step, you should create a Linux patch highlighting the necessary file updates to achieve the targeted goal.\n\n You will solve the problem step by step using the following approach of \n - thought (thinking process of the step you're going to take)\n - action (the command you will be running to get more details/context that's helpful to solve the problem)\n - observation (the output from the action you will observe based on which you will take your next step)\n\n The last step will be the final output summary and the patch itself in the following format \n - thought (the summary of what you did and some introduction of the patch file itself)\n - patch (a Linux-based patch that needs to be applied to reach the relevant solution)\n\n The patch file should only be applied to a single file to reach the required solution.", + "raw_context": { + "docs/specification.md": null, + "rtl/decoder_data_control_64b66b.sv": null, + "rtl/encoder_control_64b66b.sv": null, + "rtl/encoder_data_64b66b.sv": null, + "rtl/aes128_encrypt.sv": null, + "verif/tb_aes128_enc.sv": null, + "rtl/aes128_decrypt.sv": null, + "rtl/aes128_key_expansion.sv": null, + "rtl/inv_sbox.sv": null, + "rtl/sbox.sv": null, + "verif/tb_aes128_dec.sv": null, + "rtl/aes_encrypt.sv": null, + "verif/tb_aes_encrypt.sv": null, + "rtl/aes_decrypt.sv": null, + "rtl/aes_ke.sv": null, + "verif/tb_aes_decrypt.sv": null, + "rtl/aes_dec_top.sv": null, + "rtl/aes_enc_top.sv": null, + "verif/tb_padding_top.sv": null, + "verif/tb_des_enc.sv": null, + "docs/Key_schedule.md": null, + "docs/Permutations.md": null, + "docs/S_box_creation.md": null, + "rtl/S1.sv": null, + "rtl/S2.sv": null, + "rtl/S3.sv": null, + "rtl/S4.sv": null, + "rtl/S5.sv": null, + "rtl/S6.sv": null, + "rtl/S7.sv": null, + "rtl/S8.sv": null, + "rtl/des_enc.sv": null, + "verif/tb_des_dec.sv": null, + "docs/Encryption.md": null, + "rtl/des_dec.sv": null, + "verif/tb_3des_enc.sv": null, + "verif/tb_3des_dec.sv": null, + "docs/min_hamming_distance_finder_spec.md": null, + "rtl/Bit_Difference_Counter.sv": null, + "rtl/Bitwise_Reduction.sv": null, + "rtl/Data_Reduction.sv": null, + "verif/tb_Min_Hamming_Distance_Finder.sv": null, + "docs/specs.md": null, + "rtl/arithmetic_progression_generator.sv": null, + "docs/algorithms.md": null, + "docs/coeff_update_spec.md": null, + "docs/equalizer_spec.md": null, + "docs/error_calc_spec.md": null, + "rtl/coeff_update.sv": null, + "rtl/dynamic_equalizer.sv": null, + "rtl/error_calc.sv": null, + "docs/awgn_spec.md": null, + "docs/equalizer_top_spec.md": null, + "rtl/elevator_control_system.sv": null, + "docs/tx_specification.md": null, + "rtl/ethernet_fifo_cdc.sv": null, + "docs/tx_mac_specification.md": null, + "verif/event_scheduler_tb.sv": null, + "docs/modified_specs.md": null, + "rtl/event_scheduler.sv": null, + "verif/tb_event_scheduler.sv": null, + "rtl/column_selector.sv": null, + "rtl/event_storage.sv": null, + "verif/tb.sv": null, + "rtl/fixed_priority_arbiter.sv": null, + "verif/fixed_priority_arbiter_tb.sv": null, + "docs/Modified_specification.md": null, + "docs/GCD_specification.md": null, + "docs/crypto_accelerator_specification.md": null, + "docs/modular_exponentiation_specification.md": null, + "docs/modular_multiplier_specification.md": null, + "rtl/gcd_controlpath_3.sv": null, + "rtl/gcd_controlpath_4.sv": null, + "rtl/gcd_datapath_5.sv": null, + "rtl/gcd_datapath_6.sv": null, + "rtl/gcd_top_1.sv": null, + "rtl/gcd_top_2.sv": null, + "rtl/modular_exponentiation.sv": null, + "rtl/modular_multiplier.sv": null, + "rtl/lfsr_8bit.sv": null, + "verif/lfsr_8bit_tb.sv": null, + "rtl/bit16_lfsr.sv": null, + "rtl/low_power_ctrl.sv": null, + "rtl/sync_fifo.sv": null, + "verif/tb_low_power_channel.sv": null, + "rtl/cross_domain_sync.sv": null, + "rtl/dsp_input_stage.sv": null, + "rtl/dsp_output_stage.sv": null, + "rtl/lfsr_generator.sv": null, + "rtl/monte_carlo_dsp_monitor_top.sv": null, + "verif/monte_carlo_dsp_monitor_top_tb.sv": null, + "docs/multiplexer_specification.md": null, + "verif/multiplexer_tb.sv": null, + "docs/nbit_swizzling_spec.md": null, + "verif/nbit_swizzling_tb.sv": null, + "docs/nmea_decoder_spec.md": null, + "rtl/nmea_decoder.sv": null, + "verif/nmea_decoder_tb.sv": null, + "docs/fifo.md": null, + "rtl/fifo_memory.sv": null, + "rtl/read_to_write_pointer_sync.sv": null, + "rtl/rptr_empty.sv": null, + "rtl/wptr_full.sv": null, + "rtl/write_to_read_pointer_sync.sv": null, + "docs/spec.md": null, + "verif/async_filo_tb.sv": null, + "docs/axilite_to_pcie_config_module.md": null, + "rtl/axi4lite_to_pcie_cfg_bridge.sv": null, + "rtl/axis_broadcast.sv": null, + "verif/tb_axis_broadcast.sv": null, + "docs/axis_to_uart_tx_specs.md": null, + "docs/uart_rx_to_axis_specs.md": null, + "rtl/barrel_shifter.sv": null, + "verif/barrel_shifter_tb.sv": null, + "rtl/bcd_adder.sv": null, + "rtl/full_adder.sv": null, + "rtl/four_bit_adder.sv": null, + "rtl/search_binary_search_tree.sv": null, + "rtl/delete_node_binary_search_tree.sv": null, + "docs/bst_operations.md": null, + "rtl/binary_search_tree_sort_construct.sv": null, + "docs/Spec.md": null, + "verif/tb_binary_to_gray.sv": null, + "verif/tb_custom_byte_enable_ram.sv": null, + "verif/cache_controller_tb.sv": null, + "rtl/caesar_cipher.sv": null, + "verif/caesar_cipher_tb.sv": null, + "verif/tb_pseudoRandGenerator_ca.sv": null, + "docs/continuous_adder_specification.md": null, + "verif/continuous_adder_tb.sv": null, + "rtl/fifo_buffer.sv": null, + "verif/tb_fifo_buffer.sv": null, + "docs/direct_map_cache_spec.md": null, + "verif/tb_direct_map_cache.sv": null, + "rtl/direct_map_cache.sv": null, + "rtl/dual_port_memory.sv": null, + "rtl/gen_cos_sin_lut.sv": null, + "rtl/phase_lut.sv": null, + "rtl/phase_rotation.sv": null, + "rtl/power4.sv": null, + "rtl/saturation.sv": null, + "rtl/top_phase_rotation.sv": null, + "docs/spec_viterbi.md": null, + "docs/spec_slicer_top.md": null, + "docs/spec_top_phase_rotation.md": null, + "rtl/slicer.sv": null, + "rtl/slicer_top.sv": null, + "docs/swizzler_specification.md": null, + "verif/swizzler_tb.sv": null, + "rtl/swizzler.sv": null, + "docs/sync_serial_communication_tx_rx_spec.md": null, + "verif/sync_serial_communication_tb.sv": null, + "rtl/weight_stationary_pe.sv": null, + "verif/systolic_array_tb.sv": null, + "rtl/thermostat.v": null, + "docs/Traffic_controller.md": null, + "rtl/traffic_light_controller.sv": null, + "docs/Universal_Shift_Register_spec.md": null, + "verif/tb_universal_shift_register.sv": null, + "rtl/universal_shift_register.sv": null, + "docs/spec_conj.md": null, + "docs/spec_cross_correlation.md": null, + "docs/spec_detect_sequence.md": null, + "rtl/adder_2d_layers.sv": null, + "rtl/adder_tree_2d.sv": null, + "rtl/correlate.sv": null, + "rtl/cross_correlation.sv": null, + "docs/valid_modes.md": null, + "docs/words_counting.md": null, + "rtl/detect_sequence.sv": null, + "docs/proc_fsm_spec.md": null, + "docs/adder_tree.md": null, + "docs/coeff_ram.md": null, + "docs/poly_decimator.md": null, + "docs/poly_filter.md": null, + "docs/shift_register.md": null, + "rtl/adder_tree.sv": null, + "rtl/coeff_ram.sv": null, + "rtl/poly_filter.sv": null, + "rtl/shift_register.sv": null, + "docs/prbs_specification.md": null, + "rtl/prbs_gen_check.sv": null, + "rtl/fsm.sv": null, + "verif/fsm_tb.sv": null, + "rtl/CA_1.sv": "module CA_1(\n\tinput wire clock,\t\t//Clock input\n\tinput wire reset,\t\t//Reset input\n\tinput wire [7:0] CA_seed, \t//8-bit Cellular Automata (CA) seed\n\toutput reg [7:0] CA_out); \t//8-bit CA output\n\t\n\twire q1,q2,q3,q4,q5,q6,q7,q8;\n\t\n\t//Rule combination considered for 8-bit CA is R90-R90-R150-R90-R150-R90-R150-R90\n\t\n\t//Internal XORing based on rules 90 and 150 combination\n\tassign q1 = CA_out[6]; \t\t\t\t//R90\n\tassign q2 = CA_out[7] ^ CA_out[5]; \t\t//R90\n\tassign q3 = CA_out[6] ^ CA_out[5] ^ CA_out[4]; \t//R150\n\tassign q4 = CA_out[5] ^ CA_out[3]; \t\t//R90\n\tassign q5 = CA_out[4] ^ CA_out[3] ^ CA_out[2]; \t//R150\n\tassign q6 = CA_out[3] ^ CA_out[1]; \t\t//R90\n\tassign q7 = CA_out[2] ^ CA_out[1] ^ CA_out[0]; \t//R150\n\tassign q8 = CA_out[1]; \t\t\t\t//R90\n\n\talways_ff @(posedge clock)\n\tbegin\n\t\tif (reset) //If reset is HIGH, 8-bit CA seed will be initialised at CA output\n\t\t\tCA_out <= CA_seed;\n\t\telse\n\t\t\tCA_out <= {q1,q2,q3,q4,q5,q6,q7,q8}; //Shift register based on the CA rules\n\tend\nendmodule", + "rtl/CA_2.sv": "module CA_2(\n\tinput wire clock,\t\t//Clock input\n\tinput wire reset,\t\t//Reset input\n\tinput wire [7:0] CA_seed, \t//8-bit Cellular Automata (CA) seed\n\toutput reg [7:0] CA_out); \t//8-bit CA output\n\t\n\twire q1,q2,q3,q4,q5,q6,q7,q8;\n\t\n\t//Rule combination considered for 8-bit CA is R150-R90-R150-R90-R150-R90-R150-R150\n\t\n\t//Internal XORing based on rules 90 and 150 combination\n\tassign q1 = CA_out[7] ^ CA_out[6]; \t\t//R150\n\tassign q2 = CA_out[7] ^ CA_out[5]; \t\t//R90\n\tassign q3 = CA_out[6] ^ CA_out[5] ^ CA_out[4]; \t//R150\n\tassign q4 = CA_out[5] ^ CA_out[3]; \t\t//R90\n\tassign q5 = CA_out[4] ^ CA_out[3] ^ CA_out[2]; \t//R150\n\tassign q6 = CA_out[3] ^ CA_out[1]; \t\t//R90\n\tassign q7 = CA_out[2] ^ CA_out[1] ^ CA_out[0]; \t//R150\n\tassign q8 = CA_out[1] ^ CA_out[0];; \t//R150\n\n\talways_ff @(posedge clock)\n\tbegin\n\t\tif (reset) //If reset is HIGH, 8-bit CA seed will be initialised at CA output\n\t\t\tCA_out <= CA_seed;\n\t\telse\n\t\t\tCA_out <= {q1,q2,q3,q4,q5,q6,q7,q8}; //Shift register based on the CA rules\n\tend\nendmodule", + "rtl/CA_3.sv": "module CA_3(\n\tinput wire clock,\t\t//Clock input\n\tinput wire reset,\t\t//Reset input\n\tinput wire [7:0] CA_seed, \t//8-bit Cellular Automata (CA) seed\n\toutput reg [7:0] CA_out); \t//8-bit CA output\n\t\n\twire q1,q2,q3,q4,q5,q6,q7,q8;\n\t\n\t//Rule combination considered for 8-bit CA is R150-R150-R90-R150-R90-R150-R90-R150\n\t\n\t//Internal XORing based on rules 90 and 150 combination\n assign q1 = CA_out[7] ^ CA_out[6]; \t\t\t\t //R150\n assign q2 = CA_out[7] ^ CA_out[6] ^ CA_out[5]; \t\t//R150\n assign q3 = CA_out[6] ^ CA_out[4]; \t //R90\n assign q4 = CA_out[5] ^ CA_out[4] ^ CA_out[3]; \t\t//R150\n assign q5 = CA_out[4] ^ CA_out[2]; \t//R90\n assign q6 = CA_out[3] ^ CA_out[2] ^ CA_out[1]; \t\t//R150\n assign q7 = CA_out[2] ^ CA_out[0]; \t //R90\n assign q8 = CA_out[1] ^ CA_out[0]; \t\t\t\t //R150\n\n\talways_ff @(posedge clock)\n\tbegin\n\t\tif (reset) //If reset is HIGH, 8-bit CA seed will be initialised at CA output\n\t\t\tCA_out <= CA_seed;\n\t\telse\n\t\t\tCA_out <= {q1,q2,q3,q4,q5,q6,q7,q8}; //Shift register based on the CA rules\n\tend\nendmodule", + "rtl/CA_4.sv": "module CA_4(\n\tinput wire clock,\t\t//Clock input\n\tinput wire reset,\t\t//Reset input\n\tinput wire [7:0] CA_seed, \t//8-bit Cellular Automata (CA) seed\n\toutput reg [7:0] CA_out); \t//8-bit CA output\n\t\n\twire q1,q2,q3,q4,q5,q6,q7,q8;\n\t\n\t//Rule combination considered for 8-bit CA is R90-R90-R90-R150-R90-R150-R90-R150\n\t\n\t//Internal XORing based on rules 90 and 150 combination\n assign q1 = CA_out[6]; \t\t\t\t //R90\n assign q2 = CA_out[7] ^ CA_out[5]; \t\t //R90\n assign q3 = CA_out[6] ^ CA_out[4]; \t //R90\n assign q4 = CA_out[5] ^ CA_out[4] ^ CA_out[3]; \t\t//R150\n assign q5 = CA_out[4] ^ CA_out[2]; \t//R90\n assign q6 = CA_out[3] ^ CA_out[2] ^ CA_out[1]; \t\t//R150\n assign q7 = CA_out[2] ^ CA_out[0]; \t //R90\n assign q8 = CA_out[1] ^ CA_out[0]; \t\t\t\t //R150\n\n\talways_ff @(posedge clock)\n\tbegin\n\t\tif (reset) //If reset is HIGH, 8-bit CA seed will be initialised at CA output\n\t\t\tCA_out <= CA_seed;\n\t\telse\n\t\t\tCA_out <= {q1,q2,q3,q4,q5,q6,q7,q8}; //Shift register based on the CA rules\n\tend\nendmodule", + "rtl/rgb_color_space_conversion.sv": null, + "rtl/APBGlobalHistoryRegister.v": null, + "docs/signed_comparator_specification.md": null, + "verif/signed_comparator_tb.sv": null, + "rtl/sorting_engine.sv": null, + "rtl/brick_sort.sv": null, + "rtl/bubble_sort.sv": null, + "rtl/merge_sort.sv": null, + "rtl/selection_sort.sv": null + } + }, + { + "id": "cvdp_agentic_swizzler_0005", + "index": 573, + "source_config": "cvdp_agentic_code_generation_no_commercial", + "instruction": "Context: You are a language model that has the following file operations available at your disposal:\n - **List files in a directory** by running one of the following commands: \n - `ls`\n - `tree`\n - **Read files** by using:\n - `cat `\n - **Write files** by using:\n - `echo > `\n - **Compile Verilog** by using `iverilog` such as:\n - `iverilog -o .out -g2012 `\n - **Run Simulation** by using:\n - `vvp .out`\n - **Update the file content** by using:\n - `sed -i '3s/old/new/' file.txt`\n - **Find current working directory** by using:\n - `pwd`\n\nYou will be given a prompt and your task is to understand it and solve the given issue by using the above-mentioned commands as needed. In the final step, you should create a Linux patch to highlight the necessary file updates to achieve the targeted goal.\n\n You will solve the problem step by step using the following approach of \n - thought (thinking process of the step you're going to take)\n - action (the command you will be running to get more details/context that's helpful to solve the problem)\n - observation (the output from the action you will observe based on which you will take your next step)\n\n The last step will be the final output summary and the patch itself in the following format \n - thought (the summary of what you did and some introduction of the patch file itself)\n - patch (a Linux-based patch that needs to be applied to reach the relevant solution)\n\n The patch file should only be applied to a single file to reach the required solution.\n\nTask: I have a **swizzler** module that performs complex cross-correlation and energy computation over input I/Q data. This module handles the internal processing logic required for computing correlation with conjugate reference sequences. It unpacks the input data into individual lanes, applies a swizzle map for remapping the lanes, detects invalid mappings, computes parity errors (if enabled), and finally performs a bit reversal on each lane before packing the data back into a flat output vector. The **swizzler** module is available at `/rtl/swizzler.sv` and its detailed specification is provided in the `/docs` directory.\n\nCan you p-level module called **`swizzler_supervisor`** ? The supervisor should integrate the **swizzler** module and augment its functionality with additional glue logic as described below.\n\nThe **swizzler_supervisor** module is designed to enhance the raw functionality of the **swizzler** subcomponent by:\n \n- **Input Handling:** \n - Pre-processing the input I/Q data to ensure proper formatting and conditioning prior to processing by the swizzler.\n - Applying potential reordering or scaling operations to align with the swizzler\u2019s processing requirements.\n\n- **Processing the Swizzler's Output:** \n - Performing post-processing on the swizzler\u2019s output, which includes computing a checksum across all lanes.\n - Comparing the computed checksum with a pre-defined expected value.\n - Generating error flags if a parity error, invalid mapping, or checksum mismatch is detected.\n - Applying additional bit manipulations (such as inverting the least significant bit in each lane) to produce the final data output.\n\n- **Parameterization:** \n - The must be fully parameterizable to adapt to various configurations. Key parameters include:\n - **NUM_LANES**: Number of data lanes.\n - **DATA_WIDTH**: Bit-width of each lane.\n - **REGISTER_OUTPUT**: Option to pipeline outputs.\n - **ENABLE_PARITY_CHECK**: Toggle for parity error computation.\n - **OP_MODE_WIDTH**: Width of the operation mode signal.\n - **SWIZZLE_MAP_WIDTH**: Derived width for swizzle mapping.\n - **EXPECTED_CHECKSUM**: The checksum value against which the output is verified.\n\n- **Error Supervision:** \n - Integrate supervisory logic that validates the swizzler output by comparing the computed checksum with the expected value.\n - Assert a top-level error signal if any discrepancies arise (i.e., parity errors, invalid mapping errors, or checksum mismatches).\n\n```verilog\nmodule swizzler_supervisor #(\n parameter integer NUM_LANES = 4,\n parameter integer DATA_WIDTH = 8,\n parameter integer REGISTER_OUTPUT = 1,\n parameter integer ENABLE_PARITY_CHECK = 1,\n parameter integer OP_MODE_WIDTH = 2,\n parameter integer SWIZZLE_MAP_WIDTH = $clog2(NUM_LANES)+1,\n parameter [DATA_WIDTH-1:0] EXPECTED_CHECKSUM = 8'hA5\n)(\n input wire clk,\n input wire rst_n,\n input wire bypass,\n input wire [NUM_LANES*DATA_WIDTH-1:0] data_in,\n input wire [NUM_LANES*SWIZZLE_MAP_WIDTH-1:0] swizzle_map_flat,\n input wire [OP_MODE_WIDTH-1:0] operation_mode,\n output reg [NUM_LANES*DATA_WIDTH-1:0] final_data_out,\n output reg top_error\n);\n // [Internal implementation...]\nendmodule\n```\n\nPlease refer to `docs/swizzler_specification.md` for detailed requirements and specifications of the subcomponent swizzler.", + "verilog_code": { + "code_block_0_0": "module swizzler_supervisor #(\n parameter integer NUM_LANES = 4,\n parameter integer DATA_WIDTH = 8,\n parameter integer REGISTER_OUTPUT = 1,\n parameter integer ENABLE_PARITY_CHECK = 1,\n parameter integer OP_MODE_WIDTH = 2,\n parameter integer SWIZZLE_MAP_WIDTH = $clog2(NUM_LANES)+1,\n parameter [DATA_WIDTH-1:0] EXPECTED_CHECKSUM = 8'hA5\n)(\n input wire clk,\n input wire rst_n,\n input wire bypass,\n input wire [NUM_LANES*DATA_WIDTH-1:0] data_in,\n input wire [NUM_LANES*SWIZZLE_MAP_WIDTH-1:0] swizzle_map_flat,\n input wire [OP_MODE_WIDTH-1:0] operation_mode,\n output reg [NUM_LANES*DATA_WIDTH-1:0] final_data_out,\n output reg top_error\n);\n // [Internal implementation...]\nendmodule", + "code_block_1_3": "verilog\nmodule swizzler_supervisor #(\n parameter integer NUM_LANES = 4,\n parameter integer DATA_WIDTH = 8,\n parameter integer REGISTER_OUTPUT = 1,\n parameter integer ENABLE_PARITY_CHECK = 1,\n parameter integer OP_MODE_WIDTH = 2,\n parameter integer SWIZZLE_MAP_WIDTH = $clog2(NUM_LANES)+1,\n parameter [DATA_WIDTH-1:0] EXPECTED_CHECKSUM = 8'hA5\n)(\n input wire clk,\n input wire rst_n,\n input wire bypass,\n input wire [NUM_LANES*DATA_WIDTH-1:0] data_in,\n input wire [NUM_LANES*SWIZZLE_MAP_WIDTH-1:0] swizzle_map_flat,\n input wire [OP_MODE_WIDTH-1:0] operation_mode,\n output reg [NUM_LANES*DATA_WIDTH-1:0] final_data_out,\n output reg top_error\n);\n // [Internal implementation...]\nendmodule", + "code_block_1_5": "for detailed design requirements and specifications of the subcomponent swizzler. \n {'docs/specification.md': None, 'rtl/decoder_data_control_64b66b.sv': None, 'rtl/encoder_control_64b66b.sv': None, 'rtl/encoder_data_64b66b.sv': None, 'rtl/aes128_encrypt.sv': None, 'verif/tb_aes128_enc.sv': None, 'rtl/aes128_decrypt.sv': None, 'rtl/aes128_key_expansion.sv': None, 'rtl/inv_sbox.sv': None, 'rtl/sbox.sv': None, 'verif/tb_aes128_dec.sv': None, 'rtl/aes_encrypt.sv': None, 'verif/tb_aes_encrypt.sv': None, 'rtl/aes_decrypt.sv': None, 'rtl/aes_ke.sv': None, 'verif/tb_aes_decrypt.sv': None, 'rtl/aes_dec_top.sv': None, 'rtl/aes_enc_top.sv': None, 'verif/tb_padding_top.sv': None, 'verif/tb_des_enc.sv': None, 'docs/Key_schedule.md': None, 'docs/Permutations.md': None, 'docs/S_box_creation.md': None, 'rtl/S1.sv': None, 'rtl/S2.sv': None, 'rtl/S3.sv': None, 'rtl/S4.sv': None, 'rtl/S5.sv': None, 'rtl/S6.sv': None, 'rtl/S7.sv': None, 'rtl/S8.sv': None, 'rtl/des_enc.sv': None, 'verif/tb_des_dec.sv': None, 'docs/Encryption.md': None, 'rtl/des_dec.sv': None, 'verif/tb_3des_enc.sv': None, 'verif/tb_3des_dec.sv': None, 'docs/min_hamming_distance_finder_spec.md': None, 'rtl/Bit_Difference_Counter.sv': None, 'rtl/Bitwise_Reduction.sv': None, 'rtl/Data_Reduction.sv': None, 'verif/tb_Min_Hamming_Distance_Finder.sv': None, 'docs/specs.md': None, 'rtl/arithmetic_progression_generator.sv': None, 'docs/algorithms.md': None, 'docs/coeff_update_spec.md': None, 'docs/equalizer_spec.md': None, 'docs/error_calc_spec.md': None, 'rtl/coeff_update.sv': None, 'rtl/dynamic_equalizer.sv': None, 'rtl/error_calc.sv': None, 'docs/awgn_spec.md': None, 'docs/equalizer_top_spec.md': None, 'rtl/elevator_control_system.sv': None, 'docs/tx_specification.md': None, 'rtl/ethernet_fifo_cdc.sv': None, 'docs/tx_mac_specification.md': None, 'verif/event_scheduler_tb.sv': None, 'docs/modified_specs.md': None, 'rtl/event_scheduler.sv': None, 'verif/tb_event_scheduler.sv': None, 'rtl/column_selector.sv': None, 'rtl/event_storage.sv': None, 'verif/tb.sv': None, 'rtl/fixed_priority_arbiter.sv': None, 'verif/fixed_priority_arbiter_tb.sv': None, 'docs/Modified_specification.md': None, 'docs/GCD_specification.md': None, 'docs/crypto_accelerator_specification.md': None, 'docs/modular_exponentiation_specification.md': None, 'docs/modular_multiplier_specification.md': None, 'rtl/gcd_controlpath_3.sv': None, 'rtl/gcd_controlpath_4.sv': None, 'rtl/gcd_datapath_5.sv': None, 'rtl/gcd_datapath_6.sv': None, 'rtl/gcd_top_1.sv': None, 'rtl/gcd_top_2.sv': None, 'rtl/modular_exponentiation.sv': None, 'rtl/modular_multiplier.sv': None, 'rtl/lfsr_8bit.sv': None, 'verif/lfsr_8bit_tb.sv': None, 'rtl/bit16_lfsr.sv': None, 'rtl/low_power_ctrl.sv': None, 'rtl/sync_fifo.sv': None, 'verif/tb_low_power_channel.sv': None, 'rtl/cross_domain_sync.sv': None, 'rtl/dsp_input_stage.sv': None, 'rtl/dsp_output_stage.sv': None, 'rtl/lfsr_generator.sv': None, 'rtl/monte_carlo_dsp_monitor_top.sv': None, 'verif/monte_carlo_dsp_monitor_top_tb.sv': None, 'docs/multiplexer_specification.md': None, 'verif/multiplexer_tb.sv': None, 'docs/nbit_swizzling_spec.md': None, 'verif/nbit_swizzling_tb.sv': None, 'docs/nmea_decoder_spec.md': None, 'rtl/nmea_decoder.sv': None, 'verif/nmea_decoder_tb.sv': None, 'docs/fifo.md': None, 'rtl/fifo_memory.sv': None, 'rtl/read_to_write_pointer_sync.sv': None, 'rtl/rptr_empty.sv': None, 'rtl/wptr_full.sv': None, 'rtl/write_to_read_pointer_sync.sv': None, 'docs/spec.md': None, 'verif/async_filo_tb.sv': None, 'docs/axilite_to_pcie_config_module.md': None, 'rtl/axi4lite_to_pcie_cfg_bridge.sv': None, 'rtl/axis_broadcast.sv': None, 'verif/tb_axis_broadcast.sv': None, 'docs/axis_to_uart_tx_specs.md': None, 'docs/uart_rx_to_axis_specs.md': None, 'rtl/barrel_shifter.sv': None, 'verif/barrel_shifter_tb.sv': None, 'rtl/bcd_adder.sv': None, 'rtl/full_adder.sv': None, 'rtl/four_bit_adder.sv': None, 'rtl/search_binary_search_tree.sv': None, 'rtl/delete_node_binary_search_tree.sv': None, 'docs/bst_operations.md': None, 'rtl/binary_search_tree_sort_construct.sv': None, 'docs/Spec.md': None, 'verif/tb_binary_to_gray.sv': None, 'verif/tb_custom_byte_enable_ram.sv': None, 'verif/cache_controller_tb.sv': None, 'rtl/caesar_cipher.sv': None, 'verif/caesar_cipher_tb.sv': None, 'verif/tb_pseudoRandGenerator_ca.sv': None, 'docs/continuous_adder_specification.md': None, 'verif/continuous_adder_tb.sv': None, 'rtl/fifo_buffer.sv': None, 'verif/tb_fifo_buffer.sv': None, 'docs/direct_map_cache_spec.md': None, 'verif/tb_direct_map_cache.sv': None, 'rtl/direct_map_cache.sv': None, 'rtl/dual_port_memory.sv': None, 'rtl/gen_cos_sin_lut.sv': None, 'rtl/phase_lut.sv': None, 'rtl/phase_rotation.sv': None, 'rtl/power4.sv': None, 'rtl/saturation.sv': None, 'rtl/top_phase_rotation.sv': None, 'docs/spec_viterbi.md': None, 'docs/spec_slicer_top.md': None, 'docs/spec_top_phase_rotation.md': None, 'rtl/slicer.sv': None, 'rtl/slicer_top.sv': None, 'docs/swizzler_specification.md': '# Swizzler Specification Document\\n\\n## Introduction\\n\\nThe Swizzler module is a configurable hardware component designed to perform lane remapping (swizzling) on a multi-lane data bus. It allows for flexible data routing by rearranging the input data lanes according to an encoded swizzle map. This version of the Swizzler adds advanced features including an operation mode input for additional control, invalid mapping detection, a three-stage pipeline with bit reversal processing, and optional parity checking and output registering.\\n\\n## Functional Overview\\n\\n1. **Data Unpacking:** \\n The flat input bus (", + "code_block_1_6": ") is partitioned into individual data lanes. Each lane is extracted based on the defined data width.\\n\\n2. **Swizzle Map Unpacking:** \\n The encoded flat swizzle map (", + "code_block_1_7": ") is converted into an array of mapping values. The width of each element is defined as", + "code_block_1_8": ", which provides extra bits for error detection.\\n\\n3. **Invalid Mapping Detection:** \\n Each element of the swizzle map is compared against", + "code_block_1_9": "to detect invalid mapping values. If any element is out of the valid range, an invalid mapping flag is raised and later captured by the pipeline.\\n\\n4. **Lane Remapping:** \\n In normal operation, the module remaps the input lanes based on the swizzle map. When the", + "code_block_1_10": "signal is asserted, the input lanes pass through unchanged. The lower bits of each mapping element are used as the valid index for lane selection.\\n\\n5. **Pipeline Stage 1:** \\n The remapped (or bypassed) lanes are captured into a set of registers. This stage creates a buffered version of the swizzled lanes that can be further processed.\\n\\n6. **Pipeline Stage 2:** \\n The current", + "code_block_1_11": "is captured into a register along with the invalid mapping detection signal. This stage isolates control and error status information before final processing.\\n\\n7. **Bit Reversal:** \\n A bit reversal function processes each lane. In the final pipeline stage, the bits of each captured lane are reversed to produce the final output data.\\n\\n8. **Pipeline Stage 3:** \\n The bit-reversed lanes are stored in a final set of registers, which are then repacked into the flat output bus (", + "code_block_1_12": "). Depending on the configuration, the final output may be registered or directly passed through combinational logic.\\n\\n9. **Optional Parity Checking:** \\n When parity checking is enabled, the module calculates the parity for each final output lane. If any lane has nonzero parity, the", + "code_block_1_13": "output is asserted.\\n\\n10. **Invalid Mapping Error Output:** \\n The result of invalid mapping detection is propagated to the top level via the", + "code_block_1_14": "output, signaling if any swizzle map element is outside the allowed range.\\n\\n## Module Interface\\n\\n### Parameters\\n\\n- **NUM_LANES** \\n Number of data lanes in the module.\\n\\n- **DATA_WIDTH** \\n Width of each data lane in bits.\\n\\n- **REGISTER_OUTPUT** \\n Determines whether the final output data is registered. If set to 1, data is clocked out; if 0, data is passed combinationally.\\n\\n- **ENABLE_PARITY_CHECK** \\n Enables parity error detection across the output lanes when set to 1.\\n\\n- **OP_MODE_WIDTH** \\n Defines the width of the operation mode input, used for auxiliary control purposes.\\n\\n- **SWIZZLE_MAP_WIDTH** \\n Calculated as", + "code_block_1_15": ", this defines the width of each element in the swizzle map, allowing for error detection by providing an extra bit.\\n\\n### Ports\\n\\n- **clk (input):** \\n Clock signal for synchronizing operations.\\n\\n- **rst_n (input):** \\n Active-low reset that initializes internal registers.\\n\\n- **bypass (input):** \\n When asserted, the module bypasses the swizzling logic and forwards the input lanes directly to the output.\\n\\n- **data_in (input):** \\n Flat data input bus with a width of", + "code_block_1_16": ".\\n\\n- **swizzle_map_flat (input):** \\n Flat swizzle map with a width of", + "code_block_1_17": "which specifies the remapping of input lanes.\\n\\n- **operation_mode (input):** \\n Input specifying the operational mode. Captured and used in pipeline stage 2 for additional control.\\n\\n- **data_out (output):** \\n Flat data output bus with a width of", + "code_block_1_18": "that carries the processed (remapped and bit-reversed) data.\\n\\n- **parity_error (output):** \\n When parity checking is enabled, this output is asserted if any lane\u2019s computed parity is nonzero.\\n\\n- **invalid_mapping_error (output):** \\n Indicates that one or more elements in the swizzle map contained an invalid mapping (i.e., a mapping value not less than NUM_LANES).\\n\\n", + "code_block_1_19": "verilog\\nmodule swizzler #(\\n parameter integer NUM_LANES = 4,\\n parameter integer DATA_WIDTH = 8,\\n parameter integer REGISTER_OUTPUT = 0,\\n parameter integer ENABLE_PARITY_CHECK = 0,\\n parameter integer OP_MODE_WIDTH = 2,\\n parameter integer SWIZZLE_MAP_WIDTH = $clog2(NUM_LANES)+1\\n)(\\n input wire clk,\\n input wire rst_n,\\n input wire bypass,\\n input wire [NUM_LANES*DATA_WIDTH-1:0] data_in,\\n input wire [NUM_LANES*SWIZZLE_MAP_WIDTH-1:0] swizzle_map_flat,\\n input wire [OP_MODE_WIDTH-1:0] operation_mode,\\n output reg [NUM_LANES*DATA_WIDTH-1:0] data_out,\\n output reg parity_error,\\n output reg invalid_mapping_error\\n);\\n // Internal RTL implementation as described in the functional overview.\\nendmodule', 'verif/swizzler_tb.sv': '", + "code_block_2_0": "module that performs complex cross-correlation and energy computation over input I/Q data. This module handles the internal processing logic required for computing correlation with conjugate reference sequences. It unpacks the input data into individual lanes, applies a swizzle map for remapping the lanes, detects invalid mappings, computes parity errors (if enabled), and finally performs a bit reversal on each lane before packing the data back into a flat output vector. The **swizzler** module is available at `/rtl/swizzler.sv` and its detailed specification is provided in the `/docs` directory.\n\nCan you implement a top-level module called **`swizzler_supervisor`** ? The supervisor should integrate the **swizzler** module and augment its functionality with additional glue logic as described below.\n\nThe **swizzler_supervisor** module is designed to enhance the raw functionality of the **swizzler** subcomponent by:\n \n- **Input Handling:** \n - Pre-processing the input I/Q data to ensure proper formatting and conditioning prior to processing by the swizzler.\n - Applying potential reordering or scaling operations to align with the swizzler\u2019s processing requirements.\n\n- **Processing the Swizzler's Output:** \n - Performing post-processing on the swizzler\u2019s output, which includes computing a checksum across all lanes.\n - Comparing the computed checksum with a pre-defined expected value.\n - Generating error flags if a parity error, invalid mapping, or checksum mismatch is detected.\n - Applying additional bit manipulations (such as inverting the least significant bit in each lane) to produce the final data output.\n\n- **Parameterization:** \n - The design must be fully parameterizable to adapt to various configurations. Key parameters include:\n - **NUM_LANES**: Number of data lanes.\n - **DATA_WIDTH**: Bit-width of each lane.\n - **REGISTER_OUTPUT**: Option to pipeline outputs.\n - **ENABLE_PARITY_CHECK**: Toggle for parity error computation.\n - **OP_MODE_WIDTH**: Width of the operation mode signal.\n - **SWIZZLE_MAP_WIDTH**: Derived width for swizzle mapping.\n - **EXPECTED_CHECKSUM**: The checksum value against which the output is verified.\n\n- **Error Supervision:** \n - Integrate supervisory logic that validates the swizzler output by comparing the computed checksum with the expected value.\n - Assert a top-level error signal if any discrepancies arise (i.e., parity errors, invalid mapping errors, or checksum mismatches).\n\n```verilog\nmodule swizzler_supervisor #(\n parameter integer NUM_LANES = 4,\n parameter integer DATA_WIDTH = 8,\n parameter integer REGISTER_OUTPUT = 1,\n parameter integer ENABLE_PARITY_CHECK = 1,\n parameter integer OP_MODE_WIDTH = 2,\n parameter integer SWIZZLE_MAP_WIDTH = $clog2(NUM_LANES)+1,\n parameter [DATA_WIDTH-1:0] EXPECTED_CHECKSUM = 8'hA5\n)(\n input wire clk,\n input wire rst_n,\n input wire bypass,\n input wire [NUM_LANES*DATA_WIDTH-1:0] data_in,\n input wire [NUM_LANES*SWIZZLE_MAP_WIDTH-1:0] swizzle_map_flat,\n input wire [OP_MODE_WIDTH-1:0] operation_mode,\n output reg [NUM_LANES*DATA_WIDTH-1:0] final_data_out,\n output reg top_error\n);\n // [Internal implementation...]", + "code_block_2_1": "module\n```\n\nPlease refer to `docs/swizzler_specification.md` for detailed design requirements and specifications of the subcomponent swizzler. \n {'docs/specification.md': None, 'rtl/decoder_data_control_64b66b.sv': None, 'rtl/encoder_control_64b66b.sv': None, 'rtl/encoder_data_64b66b.sv': None, 'rtl/aes128_encrypt.sv': None, 'verif/tb_aes128_enc.sv': None, 'rtl/aes128_decrypt.sv': None, 'rtl/aes128_key_expansion.sv': None, 'rtl/inv_sbox.sv': None, 'rtl/sbox.sv': None, 'verif/tb_aes128_dec.sv': None, 'rtl/aes_encrypt.sv': None, 'verif/tb_aes_encrypt.sv': None, 'rtl/aes_decrypt.sv': None, 'rtl/aes_ke.sv': None, 'verif/tb_aes_decrypt.sv': None, 'rtl/aes_dec_top.sv': None, 'rtl/aes_enc_top.sv': None, 'verif/tb_padding_top.sv': None, 'verif/tb_des_enc.sv': None, 'docs/Key_schedule.md': None, 'docs/Permutations.md': None, 'docs/S_box_creation.md': None, 'rtl/S1.sv': None, 'rtl/S2.sv': None, 'rtl/S3.sv': None, 'rtl/S4.sv': None, 'rtl/S5.sv': None, 'rtl/S6.sv': None, 'rtl/S7.sv': None, 'rtl/S8.sv': None, 'rtl/des_enc.sv': None, 'verif/tb_des_dec.sv': None, 'docs/Encryption.md': None, 'rtl/des_dec.sv': None, 'verif/tb_3des_enc.sv': None, 'verif/tb_3des_dec.sv': None, 'docs/min_hamming_distance_finder_spec.md': None, 'rtl/Bit_Difference_Counter.sv': None, 'rtl/Bitwise_Reduction.sv': None, 'rtl/Data_Reduction.sv': None, 'verif/tb_Min_Hamming_Distance_Finder.sv': None, 'docs/specs.md': None, 'rtl/arithmetic_progression_generator.sv': None, 'docs/algorithms.md': None, 'docs/coeff_update_spec.md': None, 'docs/equalizer_spec.md': None, 'docs/error_calc_spec.md': None, 'rtl/coeff_update.sv': None, 'rtl/dynamic_equalizer.sv': None, 'rtl/error_calc.sv': None, 'docs/awgn_spec.md': None, 'docs/equalizer_top_spec.md': None, 'rtl/elevator_control_system.sv': None, 'docs/tx_specification.md': None, 'rtl/ethernet_fifo_cdc.sv': None, 'docs/tx_mac_specification.md': None, 'verif/event_scheduler_tb.sv': None, 'docs/modified_specs.md': None, 'rtl/event_scheduler.sv': None, 'verif/tb_event_scheduler.sv': None, 'rtl/column_selector.sv': None, 'rtl/event_storage.sv': None, 'verif/tb.sv': None, 'rtl/fixed_priority_arbiter.sv': None, 'verif/fixed_priority_arbiter_tb.sv': None, 'docs/Modified_specification.md': None, 'docs/GCD_specification.md': None, 'docs/crypto_accelerator_specification.md': None, 'docs/modular_exponentiation_specification.md': None, 'docs/modular_multiplier_specification.md': None, 'rtl/gcd_controlpath_3.sv': None, 'rtl/gcd_controlpath_4.sv': None, 'rtl/gcd_datapath_5.sv': None, 'rtl/gcd_datapath_6.sv': None, 'rtl/gcd_top_1.sv': None, 'rtl/gcd_top_2.sv': None, 'rtl/modular_exponentiation.sv': None, 'rtl/modular_multiplier.sv': None, 'rtl/lfsr_8bit.sv': None, 'verif/lfsr_8bit_tb.sv': None, 'rtl/bit16_lfsr.sv': None, 'rtl/low_power_ctrl.sv': None, 'rtl/sync_fifo.sv': None, 'verif/tb_low_power_channel.sv': None, 'rtl/cross_domain_sync.sv': None, 'rtl/dsp_input_stage.sv': None, 'rtl/dsp_output_stage.sv': None, 'rtl/lfsr_generator.sv': None, 'rtl/monte_carlo_dsp_monitor_top.sv': None, 'verif/monte_carlo_dsp_monitor_top_tb.sv': None, 'docs/multiplexer_specification.md': None, 'verif/multiplexer_tb.sv': None, 'docs/nbit_swizzling_spec.md': None, 'verif/nbit_swizzling_tb.sv': None, 'docs/nmea_decoder_spec.md': None, 'rtl/nmea_decoder.sv': None, 'verif/nmea_decoder_tb.sv': None, 'docs/fifo.md': None, 'rtl/fifo_memory.sv': None, 'rtl/read_to_write_pointer_sync.sv': None, 'rtl/rptr_empty.sv': None, 'rtl/wptr_full.sv': None, 'rtl/write_to_read_pointer_sync.sv': None, 'docs/spec.md': None, 'verif/async_filo_tb.sv': None, 'docs/axilite_to_pcie_config_module.md': None, 'rtl/axi4lite_to_pcie_cfg_bridge.sv': None, 'rtl/axis_broadcast.sv': None, 'verif/tb_axis_broadcast.sv': None, 'docs/axis_to_uart_tx_specs.md': None, 'docs/uart_rx_to_axis_specs.md': None, 'rtl/barrel_shifter.sv': None, 'verif/barrel_shifter_tb.sv': None, 'rtl/bcd_adder.sv': None, 'rtl/full_adder.sv': None, 'rtl/four_bit_adder.sv': None, 'rtl/search_binary_search_tree.sv': None, 'rtl/delete_node_binary_search_tree.sv': None, 'docs/bst_operations.md': None, 'rtl/binary_search_tree_sort_construct.sv': None, 'docs/Spec.md': None, 'verif/tb_binary_to_gray.sv': None, 'verif/tb_custom_byte_enable_ram.sv': None, 'verif/cache_controller_tb.sv': None, 'rtl/caesar_cipher.sv': None, 'verif/caesar_cipher_tb.sv': None, 'verif/tb_pseudoRandGenerator_ca.sv': None, 'docs/continuous_adder_specification.md': None, 'verif/continuous_adder_tb.sv': None, 'rtl/fifo_buffer.sv': None, 'verif/tb_fifo_buffer.sv': None, 'docs/direct_map_cache_spec.md': None, 'verif/tb_direct_map_cache.sv': None, 'rtl/direct_map_cache.sv': None, 'rtl/dual_port_memory.sv': None, 'rtl/gen_cos_sin_lut.sv': None, 'rtl/phase_lut.sv': None, 'rtl/phase_rotation.sv': None, 'rtl/power4.sv': None, 'rtl/saturation.sv': None, 'rtl/top_phase_rotation.sv': None, 'docs/spec_viterbi.md': None, 'docs/spec_slicer_top.md': None, 'docs/spec_top_phase_rotation.md': None, 'rtl/slicer.sv': None, 'rtl/slicer_top.sv': None, 'docs/swizzler_specification.md': '# Swizzler Specification Document\\n\\n## Introduction\\n\\nThe Swizzler module is a configurable hardware component designed to perform lane remapping (swizzling) on a multi-lane data bus. It allows for flexible data routing by rearranging the input data lanes according to an encoded swizzle map. This version of the Swizzler adds advanced features including an operation mode input for additional control, invalid mapping detection, a three-stage pipeline with bit reversal processing, and optional parity checking and output registering.\\n\\n## Functional Overview\\n\\n1. **Data Unpacking:** \\n The flat input bus (`data_in`) is partitioned into individual data lanes. Each lane is extracted based on the defined data width.\\n\\n2. **Swizzle Map Unpacking:** \\n The encoded flat swizzle map (`swizzle_map_flat`) is converted into an array of mapping values. The width of each element is defined as `$clog2(NUM_LANES)+1`, which provides extra bits for error detection.\\n\\n3. **Invalid Mapping Detection:** \\n Each element of the swizzle map is compared against `NUM_LANES` to detect invalid mapping values. If any element is out of the valid range, an invalid mapping flag is raised and later captured by the pipeline.\\n\\n4. **Lane Remapping:** \\n In normal operation, the module remaps the input lanes based on the swizzle map. When the `bypass` signal is asserted, the input lanes pass through unchanged. The lower bits of each mapping element are used as the valid index for lane selection.\\n\\n5. **Pipeline Stage 1:** \\n The remapped (or bypassed) lanes are captured into a set of registers. This stage creates a buffered version of the swizzled lanes that can be further processed.\\n\\n6. **Pipeline Stage 2:** \\n The current `operation_mode` is captured into a register along with the invalid mapping detection signal. This stage isolates control and error status information before final processing.\\n\\n7. **Bit Reversal:** \\n A bit reversal function processes each lane. In the final pipeline stage, the bits of each captured lane are reversed to produce the final output data.\\n\\n8. **Pipeline Stage 3:** \\n The bit-reversed lanes are stored in a final set of registers, which are then repacked into the flat output bus (`data_out`). Depending on the configuration, the final output may be registered or directly passed through combinational logic.\\n\\n9. **Optional Parity Checking:** \\n When parity checking is enabled, the module calculates the parity for each final output lane. If any lane has nonzero parity, the `parity_error` output is asserted.\\n\\n10. **Invalid Mapping Error Output:** \\n The result of invalid mapping detection is propagated to the top level via the `invalid_mapping_error` output, signaling if any swizzle map element is outside the allowed range.\\n\\n## Module Interface\\n\\n### Parameters\\n\\n- **NUM_LANES** \\n Number of data lanes in the module.\\n\\n- **DATA_WIDTH** \\n Width of each data lane in bits.\\n\\n- **REGISTER_OUTPUT** \\n Determines whether the final output data is registered. If set to 1, data is clocked out; if 0, data is passed combinationally.\\n\\n- **ENABLE_PARITY_CHECK** \\n Enables parity error detection across the output lanes when set to 1.\\n\\n- **OP_MODE_WIDTH** \\n Defines the width of the operation mode input, used for auxiliary control purposes.\\n\\n- **SWIZZLE_MAP_WIDTH** \\n Calculated as `$clog2(NUM_LANES)+1`, this defines the width of each element in the swizzle map, allowing for error detection by providing an extra bit.\\n\\n### Ports\\n\\n- **clk (input):** \\n Clock signal for synchronizing operations.\\n\\n- **rst_n (input):** \\n Active-low reset that initializes internal registers.\\n\\n- **bypass (input):** \\n When asserted, the module bypasses the swizzling logic and forwards the input lanes directly to the output.\\n\\n- **data_in (input):** \\n Flat data input bus with a width of `NUM_LANES * DATA_WIDTH`.\\n\\n- **swizzle_map_flat (input):** \\n Flat swizzle map with a width of `NUM_LANES * SWIZZLE_MAP_WIDTH` which specifies the remapping of input lanes.\\n\\n- **operation_mode (input):** \\n Input specifying the operational mode. Captured and used in pipeline stage 2 for additional control.\\n\\n- **data_out (output):** \\n Flat data output bus with a width of `NUM_LANES * DATA_WIDTH` that carries the processed (remapped and bit-reversed) data.\\n\\n- **parity_error (output):** \\n When parity checking is enabled, this output is asserted if any lane\u2019s computed parity is nonzero.\\n\\n- **invalid_mapping_error (output):** \\n Indicates that one or more elements in the swizzle map contained an invalid mapping (i.e., a mapping value not less than NUM_LANES).\\n\\n```verilog\\nmodule swizzler #(\\n parameter integer NUM_LANES = 4,\\n parameter integer DATA_WIDTH = 8,\\n parameter integer REGISTER_OUTPUT = 0,\\n parameter integer ENABLE_PARITY_CHECK = 0,\\n parameter integer OP_MODE_WIDTH = 2,\\n parameter integer SWIZZLE_MAP_WIDTH = $clog2(NUM_LANES)+1\\n)(\\n input wire clk,\\n input wire rst_n,\\n input wire bypass,\\n input wire [NUM_LANES*DATA_WIDTH-1:0] data_in,\\n input wire [NUM_LANES*SWIZZLE_MAP_WIDTH-1:0] swizzle_map_flat,\\n input wire [OP_MODE_WIDTH-1:0] operation_mode,\\n output reg [NUM_LANES*DATA_WIDTH-1:0] data_out,\\n output reg parity_error,\\n output reg invalid_mapping_error\\n);\\n // Internal RTL implementation as described in the functional overview.\\nendmodule', 'verif/swizzler_tb.sv': '`timescale 1ns/1ps\\n\\nmodule tb_swizzler;\\n parameter NUM_LANES = 4;\\n parameter DATA_WIDTH = 8;\\n parameter REGISTER_OUTPUT = 1;\\n parameter ENABLE_PARITY_CHECK = 0;\\n parameter OP_MODE_WIDTH = 2;\\n parameter SWIZZLE_MAP_WIDTH = 3;\\n\\n reg clk;\\n reg rst_n;\\n reg bypass;\\n reg [NUM_LANES*DATA_WIDTH-1:0] data_in;\\n reg [NUM_LANES*SWIZZLE_MAP_WIDTH-1:0] swizzle_map_flat;\\n reg [OP_MODE_WIDTH-1:0] operation_mode;\\n wire [NUM_LANES*DATA_WIDTH-1:0] data_out;\\n wire parity_error;\\n wire invalid_mapping_error;\\n\\n swizzler #(\\n .NUM_LANES(NUM_LANES),\\n .DATA_WIDTH(DATA_WIDTH),\\n .REGISTER_OUTPUT(REGISTER_OUTPUT),\\n .ENABLE_PARITY_CHECK(ENABLE_PARITY_CHECK),\\n .OP_MODE_WIDTH(OP_MODE_WIDTH),\\n .SWIZZLE_MAP_WIDTH(SWIZZLE_MAP_WIDTH)\\n ) dut (\\n .clk(clk),\\n .rst_n(rst_n),\\n .bypass(bypass),\\n .data_in(data_in),\\n .swizzle_map_flat(swizzle_map_flat),\\n .operation_mode(operation_mode),\\n .data_out(data_out),\\n .parity_error(parity_error),\\n .invalid_mapping_error(invalid_mapping_error)\\n );\\n\\n reg [DATA_WIDTH-1:0] expected [0:NUM_LANES-1];\\n reg [DATA_WIDTH-1:0] out_lane [0:NUM_LANES-1];\\n integer i;\\n\\n function [DATA_WIDTH-1:0] bit_reverse;\\n input [DATA_WIDTH-1:0] in;\\n integer j;\\n reg [DATA_WIDTH-1:0] out;\\n begin\\n out = 0;\\n for(j = 0; j < DATA_WIDTH; j = j + 1)\\n out[j] = in[DATA_WIDTH-1-j];\\n bit_reverse = out;\\n end\\n endfunction\\n\\n function [DATA_WIDTH-1:0] get_lane;\\n input integer index;\\n begin\\n get_lane = data_out[DATA_WIDTH*(index+1)-1 -: DATA_WIDTH];\\n end\\n endfunction\\n\\n initial begin\\n clk = 0;\\n forever #5 clk = ~clk;\\n end\\n\\n initial begin\\n rst_n = 0;\\n bypass = 0;\\n data_in = 0;\\n swizzle_map_flat = 0;\\n operation_mode = 0;\\n #12;\\n rst_n = 1;\\n repeat (5) @(posedge clk);\\n // TEST 1: Bypass disabled, identity mapping with bit reversal.\\n data_in = {8\\'h04, 8\\'h03, 8\\'h02, 8\\'h01};\\n swizzle_map_flat = {3\\'b011, 3\\'b010, 3\\'b001, 3\\'b000};\\n bypass = 0;\\n operation_mode = 0;\\n repeat (5) @(posedge clk);\\n for(i = 0; i < NUM_LANES; i = i + 1)\\n out_lane[i] = get_lane(i);\\n expected[0] = bit_reverse(8\\'h01);\\n expected[1] = bit_reverse(8\\'h02);\\n expected[2] = bit_reverse(8\\'h03);\\n expected[3] = bit_reverse(8\\'h04);\\n if(out_lane[0]==expected[0] && out_lane[1]==expected[1] &&\\n out_lane[2]==expected[2] && out_lane[3]==expected[3])\\n $display(\"TEST 1 PASS\");\\n else\\n $display(\"TEST 1 FAIL: Expected %h %h %h %h, Got %h %h %h %h\",\\n expected[0], expected[1], expected[2], expected[3],\\n out_lane[0], out_lane[1], out_lane[2], out_lane[3]);\\n if(invalid_mapping_error==0)\\n $display(\"TEST 1 INVALID MAPPING PASS\");\\n else\\n $display(\"TEST 1 INVALID MAPPING FAIL\");\\n\\n // TEST 2: Reverse mapping.\\n data_in = {8\\'hAA, 8\\'hBB, 8\\'hCC, 8\\'hDD};\\n swizzle_map_flat = {3\\'b000, 3\\'b001, 3\\'b010, 3\\'b011};\\n bypass = 0;\\n operation_mode = 0;\\n repeat (5) @(posedge clk);\\n for(i = 0; i < NUM_LANES; i = i + 1)\\n out_lane[i] = get_lane(i);\\n // Expected output is reversed compared to input lane order.\\n expected[0] = bit_reverse(8\\'hAA);\\n expected[1] = bit_reverse(8\\'hBB);\\n expected[2] = bit_reverse(8\\'hCC);\\n expected[3] = bit_reverse(8\\'hDD);\\n if(out_lane[0]==expected[0] && out_lane[1]==expected[1] &&\\n out_lane[2]==expected[2] && out_lane[3]==expected[3])\\n $display(\"TEST 2 PASS\");\\n else\\n $display(\"TEST 2 FAIL: Expected %h %h %h %h, Got %h %h %h %h\",\\n expected[0], expected[1], expected[2], expected[3],\\n out_lane[0], out_lane[1], out_lane[2], out_lane[3]);\\n\\n // TEST 3: Bypass mode active.\\n data_in = {8\\'h11, 8\\'h22, 8\\'h33, 8\\'h44};\\n swizzle_map_flat = {3\\'b001, 3\\'b000, 3\\'b011, 3\\'b010};\\n bypass = 1;\\n operation_mode = 0;\\n repeat (5) @(posedge clk);\\n for(i = 0; i < NUM_LANES; i = i + 1)\\n out_lane[i] = get_lane(i);\\n expected[0] = bit_reverse(8\\'h44);\\n expected[1] = bit_reverse(8\\'h33);\\n expected[2] = bit_reverse(8\\'h22);\\n expected[3] = bit_reverse(8\\'h11);\\n if(out_lane[0]==expected[0] && out_lane[1]==expected[1] &&\\n out_lane[2]==expected[2] && out_lane[3]==expected[3])\\n $display(\"TEST 3 PASS\");\\n else\\n $display(\"TEST 3 FAIL: Expected %h %h %h %h, Got %h %h %h %h\",\\n expected[0], expected[1], expected[2], expected[3],\\n out_lane[0], out_lane[1], out_lane[2], out_lane[3]);\\n\\n // TEST 4: Invalid mapping detection.\\n data_in = {8\\'h55, 8\\'h66, 8\\'h77, 8\\'h88};\\n swizzle_map_flat = {3\\'b011, 3\\'b010, 3\\'b001, 3\\'b100};\\n bypass = 0;\\n operation_mode = 0;\\n repeat (5) @(posedge clk);\\n if(invalid_mapping_error==1)\\n $display(\"TEST 4 PASS: Invalid mapping detected\");\\n else\\n $display(\"TEST 4 FAIL: Invalid mapping not detected\");\\n $finish;\\n end\\n\\nendmodule', 'rtl/swizzler.sv': \"`timescale 1ns/1ps\\n\\nmodule swizzler #(\\n parameter integer NUM_LANES = 4,\\n parameter integer DATA_WIDTH = 8,\\n parameter integer REGISTER_OUTPUT = 0,\\n parameter integer ENABLE_PARITY_CHECK = 0,\\n parameter integer OP_MODE_WIDTH = 2,\\n parameter integer SWIZZLE_MAP_WIDTH = $clog2(NUM_LANES)+1\\n)(\\n input wire clk,\\n input wire rst_n,\\n input wire bypass,\\n input wire [NUM_LANES*DATA_WIDTH-1:0] data_in,\\n input wire [NUM_LANES*SWIZZLE_MAP_WIDTH-1:0] swizzle_map_flat,\\n input wire [OP_MODE_WIDTH-1:0] operation_mode,\\n output reg [NUM_LANES*DATA_WIDTH-1:0] data_out,\\n output reg parity_error,\\n output reg invalid_mapping_error\\n);\\n\\n // Unpack data_in into lanes\\n wire [DATA_WIDTH-1:0] lane_in [0:NUM_LANES-1];\\n genvar gi;\\n generate\\n for (gi = 0; gi < NUM_LANES; gi = gi + 1) begin : UNPACK_INPUT\\n assign lane_in[gi] = data_in[DATA_WIDTH*(gi+1)-1 : DATA_WIDTH*gi];\\n end\\n endgenerate\\n\\n // Unpack swizzle_map_flat into swizzle_map array\\n wire [SWIZZLE_MAP_WIDTH-1:0] swizzle_map [0:NUM_LANES-1];\\n generate\\n for (gi = 0; gi < NUM_LANES; gi = gi + 1) begin : UNPACK_SWIZZLE\\n assign swizzle_map[gi] = swizzle_map_flat[SWIZZLE_MAP_WIDTH*(gi+1)-1 : SWIZZLE_MAP_WIDTH*gi];\\n end\\n endgenerate\\n\\n // Invalid mapping detection\\n wire [NUM_LANES-1:0] invalid_map_flag;\\n generate\\n for (gi = 0; gi < NUM_LANES; gi = gi + 1) begin : INVALID_CHECK\\n assign invalid_map_flag[gi] = (swizzle_map[gi] >= NUM_LANES) ? 1'b1 : 1'b0;\\n end\\n endgenerate\\n wire invalid_mapping_detected = |invalid_map_flag;\\n\\n // Remap lanes according to swizzle_map or bypass\\n wire [DATA_WIDTH-1:0] swizzled [0:NUM_LANES-1];\\n generate\\n for (gi = 0; gi < NUM_LANES; gi = gi + 1) begin : REMAP\\n // Use lower bits of swizzle_map to index valid lanes.\\n assign swizzled[gi] = bypass ? lane_in[gi] : lane_in[ swizzle_map[gi][$clog2(NUM_LANES)-1:0] ];\\n end\\n endgenerate\\n\\n // Pipeline Stage 1: Capture swizzled lanes\\n reg [DATA_WIDTH-1:0] swizzle_reg [0:NUM_LANES-1];\\n integer i;\\n always @(posedge clk or negedge rst_n) begin\\n if (!rst_n)\\n for (i = 0; i < NUM_LANES; i = i + 1)\\n swizzle_reg[i] <= {DATA_WIDTH{1'b0}};\\n else\\n for (i = 0; i < NUM_LANES; i = i + 1)\\n swizzle_reg[i] <= swizzled[i];\\n end\\n\\n // Pipeline Stage 2: Capture operation mode and invalid mapping status\\n reg [OP_MODE_WIDTH-1:0] op_reg;\\n reg op_invalid_reg;\\n always @(posedge clk or negedge rst_n) begin\\n if (!rst_n) begin\\n op_reg <= {OP_MODE_WIDTH{1'b0}};\\n op_invalid_reg <= 1'b0;\\n end else begin\\n op_reg <= operation_mode;\\n op_invalid_reg <= invalid_mapping_detected;\\n end\\n end\\n\\n // Bit reversal function\\n function automatic [DATA_WIDTH-1:0] bit_reverse;\\n input [DATA_WIDTH-1:0] in;\\n integer k;\\n begin\\n bit_reverse = {DATA_WIDTH{1'b0}};\\n for (k = 0; k < DATA_WIDTH; k = k + 1)\\n bit_reverse[k] = in[DATA_WIDTH-1-k];\\n end\\n endfunction\\n\\n // Pipeline Stage 3: Final output stage with bit reversal\\n reg [DATA_WIDTH-1:0] final_reg [0:NUM_LANES-1];\\n integer m;\\n always @(posedge clk or negedge rst_n) begin\\n if (!rst_n)\\n for (m = 0; m < NUM_LANES; m = m + 1)\\n final_reg[m] <= {DATA_WIDTH{1'b0}};\\n else\\n for (m = 0; m < NUM_LANES; m = m + 1)\\n final_reg[m] <= bit_reverse(swizzle_reg[m]);\\n end\\n\\n // Pack final_reg into a flat output vector\\n wire [NUM_LANES*DATA_WIDTH-1:0] final_packed;\\n genvar q;\\n generate\\n for (q = 0; q < NUM_LANES; q = q + 1) begin : PACK_FINAL\\n assign final_packed[DATA_WIDTH*(q+1)-1 : DATA_WIDTH*q] = final_reg[q];\\n end\\n endgenerate\\n\\n generate\\n if (REGISTER_OUTPUT) begin : REG_FINAL\\n always @(posedge clk or negedge rst_n) begin\\n if (!rst_n)\\n data_out <= {NUM_LANES*DATA_WIDTH{1'b0}};\\n else\\n data_out <= final_packed;\\n end\\n end else begin : COMB_FINAL\\n always @* begin\\n data_out = final_packed;\\n end\\n end\\n endgenerate\\n\\n // Updated parity error calculation using a generate block\\n generate\\n if (ENABLE_PARITY_CHECK) begin : GEN_PARITY\\n // Calculate parity from final_reg if parity check is enabled.\\n wire [NUM_LANES-1:0] final_parity;\\n genvar p;\\n for (p = 0; p < NUM_LANES; p = p + 1) begin : PARITY_CALC\\n assign final_parity[p] = ^final_reg[p];\\n end\\n wire computed_parity = |final_parity;\\n always @* begin\\n parity_error = computed_parity;\\n end\\n end else begin : NO_PARITY\\n // Drive parity_error to 0 when parity check is disabled.\\n always @* begin\\n parity_error = 1'b0;\\n end\\n end\\n endgenerate\\n\\n // Pass the invalid mapping flag\\n always @* begin\\n invalid_mapping_error = op_invalid_reg;\\n end\\n\\nendmodule\", 'docs/sync_serial_communication_tx_rx_spec.md': None, 'verif/sync_serial_communication_tb.sv': None, 'rtl/weight_stationary_pe.sv': None, 'verif/systolic_array_tb.sv': None, 'rtl/thermostat.v': None, 'docs/Traffic_controller.md': None, 'rtl/traffic_light_controller.sv': None, 'docs/Universal_Shift_Register_spec.md': None, 'verif/tb_universal_shift_register.sv': None, 'rtl/universal_shift_register.sv': None, 'docs/spec_conj.md': None, 'docs/spec_cross_correlation.md': None, 'docs/spec_detect_sequence.md': None, 'rtl/adder_2d_layers.sv': None, 'rtl/adder_tree_2d.sv': None, 'rtl/correlate.sv': None, 'rtl/cross_correlation.sv': None, 'docs/valid_modes.md': None, 'docs/words_counting.md': None, 'rtl/detect_sequence.sv': None, 'docs/proc_fsm_spec.md': None, 'docs/adder_tree.md': None, 'docs/coeff_ram.md': None, 'docs/poly_decimator.md': None, 'docs/poly_filter.md': None, 'docs/shift_register.md': None, 'rtl/adder_tree.sv': None, 'rtl/coeff_ram.sv': None, 'rtl/poly_filter.sv': None, 'rtl/shift_register.sv': None, 'docs/prbs_specification.md': None, 'rtl/prbs_gen_check.sv': None, 'rtl/fsm.sv': None, 'verif/fsm_tb.sv': None, 'rtl/CA_1.sv': None, 'rtl/CA_2.sv': None, 'rtl/CA_3.sv': None, 'rtl/CA_4.sv': None, 'rtl/rgb_color_space_conversion.sv': None, 'rtl/APBGlobalHistoryRegister.v': None, 'docs/signed_comparator_specification.md': None, 'verif/signed_comparator_tb.sv': None, 'rtl/sorting_engine.sv': None, 'rtl/brick_sort.sv': None, 'rtl/bubble_sort.sv': None, 'rtl/merge_sort.sv': None, 'rtl/selection_sort.sv': None}", + "verif/swizzler_tb.sv": "`timescale 1ns/1ps\n\nmodule tb_swizzler;\n parameter NUM_LANES = 4;\n parameter DATA_WIDTH = 8;\n parameter REGISTER_OUTPUT = 1;\n parameter ENABLE_PARITY_CHECK = 0;\n parameter OP_MODE_WIDTH = 2;\n parameter SWIZZLE_MAP_WIDTH = 3;\n\n reg clk;\n reg rst_n;\n reg bypass;\n reg [NUM_LANES*DATA_WIDTH-1:0] data_in;\n reg [NUM_LANES*SWIZZLE_MAP_WIDTH-1:0] swizzle_map_flat;\n reg [OP_MODE_WIDTH-1:0] operation_mode;\n wire [NUM_LANES*DATA_WIDTH-1:0] data_out;\n wire parity_error;\n wire invalid_mapping_error;\n\n swizzler #(\n .NUM_LANES(NUM_LANES),\n .DATA_WIDTH(DATA_WIDTH),\n .REGISTER_OUTPUT(REGISTER_OUTPUT),\n .ENABLE_PARITY_CHECK(ENABLE_PARITY_CHECK),\n .OP_MODE_WIDTH(OP_MODE_WIDTH),\n .SWIZZLE_MAP_WIDTH(SWIZZLE_MAP_WIDTH)\n ) dut (\n .clk(clk),\n .rst_n(rst_n),\n .bypass(bypass),\n .data_in(data_in),\n .swizzle_map_flat(swizzle_map_flat),\n .operation_mode(operation_mode),\n .data_out(data_out),\n .parity_error(parity_error),\n .invalid_mapping_error(invalid_mapping_error)\n );\n\n reg [DATA_WIDTH-1:0] expected [0:NUM_LANES-1];\n reg [DATA_WIDTH-1:0] out_lane [0:NUM_LANES-1];\n integer i;\n\n function [DATA_WIDTH-1:0] bit_reverse;\n input [DATA_WIDTH-1:0] in;\n integer j;\n reg [DATA_WIDTH-1:0] out;\n begin\n out = 0;\n for(j = 0; j < DATA_WIDTH; j = j + 1)\n out[j] = in[DATA_WIDTH-1-j];\n bit_reverse = out;\n end\n endfunction\n\n function [DATA_WIDTH-1:0] get_lane;\n input integer index;\n begin\n get_lane = data_out[DATA_WIDTH*(index+1)-1 -: DATA_WIDTH];\n end\n endfunction\n\n initial begin\n clk = 0;\n forever #5 clk = ~clk;\n end\n\n initial begin\n rst_n = 0;\n bypass = 0;\n data_in = 0;\n swizzle_map_flat = 0;\n operation_mode = 0;\n #12;\n rst_n = 1;\n repeat (5) @(posedge clk);\n // TEST 1: Bypass disabled, identity mapping with bit reversal.\n data_in = {8'h04, 8'h03, 8'h02, 8'h01};\n swizzle_map_flat = {3'b011, 3'b010, 3'b001, 3'b000};\n bypass = 0;\n operation_mode = 0;\n repeat (5) @(posedge clk);\n for(i = 0; i < NUM_LANES; i = i + 1)\n out_lane[i] = get_lane(i);\n expected[0] = bit_reverse(8'h01);\n expected[1] = bit_reverse(8'h02);\n expected[2] = bit_reverse(8'h03);\n expected[3] = bit_reverse(8'h04);\n if(out_lane[0]==expected[0] && out_lane[1]==expected[1] &&\n out_lane[2]==expected[2] && out_lane[3]==expected[3])\n $display(\"TEST 1 PASS\");\n else\n $display(\"TEST 1 FAIL: Expected %h %h %h %h, Got %h %h %h %h\",\n expected[0], expected[1], expected[2], expected[3],\n out_lane[0], out_lane[1], out_lane[2], out_lane[3]);\n if(invalid_mapping_error==0)\n $display(\"TEST 1 INVALID MAPPING PASS\");\n else\n $display(\"TEST 1 INVALID MAPPING FAIL\");\n\n // TEST 2: Reverse mapping.\n data_in = {8'hAA, 8'hBB, 8'hCC, 8'hDD};\n swizzle_map_flat = {3'b000, 3'b001, 3'b010, 3'b011};\n bypass = 0;\n operation_mode = 0;\n repeat (5) @(posedge clk);\n for(i = 0; i < NUM_LANES; i = i + 1)\n out_lane[i] = get_lane(i);\n // Expected output is reversed compared to input lane order.\n expected[0] = bit_reverse(8'hAA);\n expected[1] = bit_reverse(8'hBB);\n expected[2] = bit_reverse(8'hCC);\n expected[3] = bit_reverse(8'hDD);\n if(out_lane[0]==expected[0] && out_lane[1]==expected[1] &&\n out_lane[2]==expected[2] && out_lane[3]==expected[3])\n $display(\"TEST 2 PASS\");\n else\n $display(\"TEST 2 FAIL: Expected %h %h %h %h, Got %h %h %h %h\",\n expected[0], expected[1], expected[2], expected[3],\n out_lane[0], out_lane[1], out_lane[2], out_lane[3]);\n\n // TEST 3: Bypass mode active.\n data_in = {8'h11, 8'h22, 8'h33, 8'h44};\n swizzle_map_flat = {3'b001, 3'b000, 3'b011, 3'b010};\n bypass = 1;\n operation_mode = 0;\n repeat (5) @(posedge clk);\n for(i = 0; i < NUM_LANES; i = i + 1)\n out_lane[i] = get_lane(i);\n expected[0] = bit_reverse(8'h44);\n expected[1] = bit_reverse(8'h33);\n expected[2] = bit_reverse(8'h22);\n expected[3] = bit_reverse(8'h11);\n if(out_lane[0]==expected[0] && out_lane[1]==expected[1] &&\n out_lane[2]==expected[2] && out_lane[3]==expected[3])\n $display(\"TEST 3 PASS\");\n else\n $display(\"TEST 3 FAIL: Expected %h %h %h %h, Got %h %h %h %h\",\n expected[0], expected[1], expected[2], expected[3],\n out_lane[0], out_lane[1], out_lane[2], out_lane[3]);\n\n // TEST 4: Invalid mapping detection.\n data_in = {8'h55, 8'h66, 8'h77, 8'h88};\n swizzle_map_flat = {3'b011, 3'b010, 3'b001, 3'b100};\n bypass = 0;\n operation_mode = 0;\n repeat (5) @(posedge clk);\n if(invalid_mapping_error==1)\n $display(\"TEST 4 PASS: Invalid mapping detected\");\n else\n $display(\"TEST 4 FAIL: Invalid mapping not detected\");\n $finish;\n end\n\nendmodule", + "rtl/swizzler.sv": "`timescale 1ns/1ps\n\nmodule swizzler #(\n parameter integer NUM_LANES = 4,\n parameter integer DATA_WIDTH = 8,\n parameter integer REGISTER_OUTPUT = 0,\n parameter integer ENABLE_PARITY_CHECK = 0,\n parameter integer OP_MODE_WIDTH = 2,\n parameter integer SWIZZLE_MAP_WIDTH = $clog2(NUM_LANES)+1\n)(\n input wire clk,\n input wire rst_n,\n input wire bypass,\n input wire [NUM_LANES*DATA_WIDTH-1:0] data_in,\n input wire [NUM_LANES*SWIZZLE_MAP_WIDTH-1:0] swizzle_map_flat,\n input wire [OP_MODE_WIDTH-1:0] operation_mode,\n output reg [NUM_LANES*DATA_WIDTH-1:0] data_out,\n output reg parity_error,\n output reg invalid_mapping_error\n);\n\n // Unpack data_in into lanes\n wire [DATA_WIDTH-1:0] lane_in [0:NUM_LANES-1];\n genvar gi;\n generate\n for (gi = 0; gi < NUM_LANES; gi = gi + 1) begin : UNPACK_INPUT\n assign lane_in[gi] = data_in[DATA_WIDTH*(gi+1)-1 : DATA_WIDTH*gi];\n end\n endgenerate\n\n // Unpack swizzle_map_flat into swizzle_map array\n wire [SWIZZLE_MAP_WIDTH-1:0] swizzle_map [0:NUM_LANES-1];\n generate\n for (gi = 0; gi < NUM_LANES; gi = gi + 1) begin : UNPACK_SWIZZLE\n assign swizzle_map[gi] = swizzle_map_flat[SWIZZLE_MAP_WIDTH*(gi+1)-1 : SWIZZLE_MAP_WIDTH*gi];\n end\n endgenerate\n\n // Invalid mapping detection\n wire [NUM_LANES-1:0] invalid_map_flag;\n generate\n for (gi = 0; gi < NUM_LANES; gi = gi + 1) begin : INVALID_CHECK\n assign invalid_map_flag[gi] = (swizzle_map[gi] >= NUM_LANES) ? 1'b1 : 1'b0;\n end\n endgenerate\n wire invalid_mapping_detected = |invalid_map_flag;\n\n // Remap lanes according to swizzle_map or bypass\n wire [DATA_WIDTH-1:0] swizzled [0:NUM_LANES-1];\n generate\n for (gi = 0; gi < NUM_LANES; gi = gi + 1) begin : REMAP\n // Use lower bits of swizzle_map to index valid lanes.\n assign swizzled[gi] = bypass ? lane_in[gi] : lane_in[ swizzle_map[gi][$clog2(NUM_LANES)-1:0] ];\n end\n endgenerate\n\n // Pipeline Stage 1: Capture swizzled lanes\n reg [DATA_WIDTH-1:0] swizzle_reg [0:NUM_LANES-1];\n integer i;\n always @(posedge clk or negedge rst_n) begin\n if (!rst_n)\n for (i = 0; i < NUM_LANES; i = i + 1)\n swizzle_reg[i] <= {DATA_WIDTH{1'b0}};\n else\n for (i = 0; i < NUM_LANES; i = i + 1)\n swizzle_reg[i] <= swizzled[i];\n end\n\n // Pipeline Stage 2: Capture operation mode and invalid mapping status\n reg [OP_MODE_WIDTH-1:0] op_reg;\n reg op_invalid_reg;\n always @(posedge clk or negedge rst_n) begin\n if (!rst_n) begin\n op_reg <= {OP_MODE_WIDTH{1'b0}};\n op_invalid_reg <= 1'b0;\n end else begin\n op_reg <= operation_mode;\n op_invalid_reg <= invalid_mapping_detected;\n end\n end\n\n // Bit reversal function\n function automatic [DATA_WIDTH-1:0] bit_reverse;\n input [DATA_WIDTH-1:0] in;\n integer k;\n begin\n bit_reverse = {DATA_WIDTH{1'b0}};\n for (k = 0; k < DATA_WIDTH; k = k + 1)\n bit_reverse[k] = in[DATA_WIDTH-1-k];\n end\n endfunction\n\n // Pipeline Stage 3: Final output stage with bit reversal\n reg [DATA_WIDTH-1:0] final_reg [0:NUM_LANES-1];\n integer m;\n always @(posedge clk or negedge rst_n) begin\n if (!rst_n)\n for (m = 0; m < NUM_LANES; m = m + 1)\n final_reg[m] <= {DATA_WIDTH{1'b0}};\n else\n for (m = 0; m < NUM_LANES; m = m + 1)\n final_reg[m] <= bit_reverse(swizzle_reg[m]);\n end\n\n // Pack final_reg into a flat output vector\n wire [NUM_LANES*DATA_WIDTH-1:0] final_packed;\n genvar q;\n generate\n for (q = 0; q < NUM_LANES; q = q + 1) begin : PACK_FINAL\n assign final_packed[DATA_WIDTH*(q+1)-1 : DATA_WIDTH*q] = final_reg[q];\n end\n endgenerate\n\n generate\n if (REGISTER_OUTPUT) begin : REG_FINAL\n always @(posedge clk or negedge rst_n) begin\n if (!rst_n)\n data_out <= {NUM_LANES*DATA_WIDTH{1'b0}};\n else\n data_out <= final_packed;\n end\n end else begin : COMB_FINAL\n always @* begin\n data_out = final_packed;\n end\n end\n endgenerate\n\n // Updated parity error calculation using a generate block\n generate\n if (ENABLE_PARITY_CHECK) begin : GEN_PARITY\n // Calculate parity from final_reg if parity check is enabled.\n wire [NUM_LANES-1:0] final_parity;\n genvar p;\n for (p = 0; p < NUM_LANES; p = p + 1) begin : PARITY_CALC\n assign final_parity[p] = ^final_reg[p];\n end\n wire computed_parity = |final_parity;\n always @* begin\n parity_error = computed_parity;\n end\n end else begin : NO_PARITY\n // Drive parity_error to 0 when parity check is disabled.\n always @* begin\n parity_error = 1'b0;\n end\n end\n endgenerate\n\n // Pass the invalid mapping flag\n always @* begin\n invalid_mapping_error = op_invalid_reg;\n end\n\nendmodule" + }, + "test_info": { + "test_criteria_2": [ + "integrate the **swizzler** module and augment its functionality with additional glue logic as described below." + ] + }, + "expected_behavior": [ + "integrate the **swizzler** module and augment its functionality with additional glue logic as described below", + "be fully parameterizable to adapt to various configurations", + "with additional glue logic as described below." + ], + "metadata": { + "categories": [ + "cid005", + "medium" + ], + "domain": "processor", + "complexity": "expert", + "problem_type": "design", + "has_code": true, + "has_tests": true + }, + "full_prompt": "I have a **swizzler** module that performs complex cross-correlation and energy computation over input I/Q data. This module handles the internal processing logic required for computing correlation with conjugate reference sequences. It unpacks the input data into individual lanes, applies a swizzle map for remapping the lanes, detects invalid mappings, computes parity errors (if enabled), and finally performs a bit reversal on each lane before packing the data back into a flat output vector. The **swizzler** module is available at `/rtl/swizzler.sv` and its detailed specification is provided in the `/docs` directory.\n\nCan you implement a top-level module called **`swizzler_supervisor`** ? The supervisor should integrate the **swizzler** module and augment its functionality with additional glue logic as described below.\n\nThe **swizzler_supervisor** module is designed to enhance the raw functionality of the **swizzler** subcomponent by:\n \n- **Input Handling:** \n - Pre-processing the input I/Q data to ensure proper formatting and conditioning prior to processing by the swizzler.\n - Applying potential reordering or scaling operations to align with the swizzler\u2019s processing requirements.\n\n- **Processing the Swizzler's Output:** \n - Performing post-processing on the swizzler\u2019s output, which includes computing a checksum across all lanes.\n - Comparing the computed checksum with a pre-defined expected value.\n - Generating error flags if a parity error, invalid mapping, or checksum mismatch is detected.\n - Applying additional bit manipulations (such as inverting the least significant bit in each lane) to produce the final data output.\n\n- **Parameterization:** \n - The design must be fully parameterizable to adapt to various configurations. Key parameters include:\n - **NUM_LANES**: Number of data lanes.\n - **DATA_WIDTH**: Bit-width of each lane.\n - **REGISTER_OUTPUT**: Option to pipeline outputs.\n - **ENABLE_PARITY_CHECK**: Toggle for parity error computation.\n - **OP_MODE_WIDTH**: Width of the operation mode signal.\n - **SWIZZLE_MAP_WIDTH**: Derived width for swizzle mapping.\n - **EXPECTED_CHECKSUM**: The checksum value against which the output is verified.\n\n- **Error Supervision:** \n - Integrate supervisory logic that validates the swizzler output by comparing the computed checksum with the expected value.\n - Assert a top-level error signal if any discrepancies arise (i.e., parity errors, invalid mapping errors, or checksum mismatches).\n\n```verilog\nmodule swizzler_supervisor #(\n parameter integer NUM_LANES = 4,\n parameter integer DATA_WIDTH = 8,\n parameter integer REGISTER_OUTPUT = 1,\n parameter integer ENABLE_PARITY_CHECK = 1,\n parameter integer OP_MODE_WIDTH = 2,\n parameter integer SWIZZLE_MAP_WIDTH = $clog2(NUM_LANES)+1,\n parameter [DATA_WIDTH-1:0] EXPECTED_CHECKSUM = 8'hA5\n)(\n input wire clk,\n input wire rst_n,\n input wire bypass,\n input wire [NUM_LANES*DATA_WIDTH-1:0] data_in,\n input wire [NUM_LANES*SWIZZLE_MAP_WIDTH-1:0] swizzle_map_flat,\n input wire [OP_MODE_WIDTH-1:0] operation_mode,\n output reg [NUM_LANES*DATA_WIDTH-1:0] final_data_out,\n output reg top_error\n);\n // [Internal implementation...]\nendmodule\n```\n\nPlease refer to `docs/swizzler_specification.md` for detailed design requirements and specifications of the subcomponent swizzler. \n", + "system_message": " You are a language model that has the following file operations available at your disposal:\n - **List files in a directory** by running one of the following commands: \n - `ls`\n - `tree`\n - **Read files** by using:\n - `cat `\n - **Write files** by using:\n - `echo > `\n - **Compile Verilog** by using `iverilog` such as:\n - `iverilog -o .out -g2012 `\n - **Run Simulation** by using:\n - `vvp .out`\n - **Update the file content** by using:\n - `sed -i '3s/old/new/' file.txt`\n - **Find current working directory** by using:\n - `pwd`\n\nYou will be given a prompt and your task is to understand it and solve the given issue by using the above-mentioned commands as needed. In the final step, you should create a Linux patch to highlight the necessary file updates to achieve the targeted goal.\n\n You will solve the problem step by step using the following approach of \n - thought (thinking process of the step you're going to take)\n - action (the command you will be running to get more details/context that's helpful to solve the problem)\n - observation (the output from the action you will observe based on which you will take your next step)\n\n The last step will be the final output summary and the patch itself in the following format \n - thought (the summary of what you did and some introduction of the patch file itself)\n - patch (a Linux-based patch that needs to be applied to reach the relevant solution)\n\n The patch file should only be applied to a single file to reach the required solution.", + "raw_context": { + "docs/specification.md": null, + "rtl/decoder_data_control_64b66b.sv": null, + "rtl/encoder_control_64b66b.sv": null, + "rtl/encoder_data_64b66b.sv": null, + "rtl/aes128_encrypt.sv": null, + "verif/tb_aes128_enc.sv": null, + "rtl/aes128_decrypt.sv": null, + "rtl/aes128_key_expansion.sv": null, + "rtl/inv_sbox.sv": null, + "rtl/sbox.sv": null, + "verif/tb_aes128_dec.sv": null, + "rtl/aes_encrypt.sv": null, + "verif/tb_aes_encrypt.sv": null, + "rtl/aes_decrypt.sv": null, + "rtl/aes_ke.sv": null, + "verif/tb_aes_decrypt.sv": null, + "rtl/aes_dec_top.sv": null, + "rtl/aes_enc_top.sv": null, + "verif/tb_padding_top.sv": null, + "verif/tb_des_enc.sv": null, + "docs/Key_schedule.md": null, + "docs/Permutations.md": null, + "docs/S_box_creation.md": null, + "rtl/S1.sv": null, + "rtl/S2.sv": null, + "rtl/S3.sv": null, + "rtl/S4.sv": null, + "rtl/S5.sv": null, + "rtl/S6.sv": null, + "rtl/S7.sv": null, + "rtl/S8.sv": null, + "rtl/des_enc.sv": null, + "verif/tb_des_dec.sv": null, + "docs/Encryption.md": null, + "rtl/des_dec.sv": null, + "verif/tb_3des_enc.sv": null, + "verif/tb_3des_dec.sv": null, + "docs/min_hamming_distance_finder_spec.md": null, + "rtl/Bit_Difference_Counter.sv": null, + "rtl/Bitwise_Reduction.sv": null, + "rtl/Data_Reduction.sv": null, + "verif/tb_Min_Hamming_Distance_Finder.sv": null, + "docs/specs.md": null, + "rtl/arithmetic_progression_generator.sv": null, + "docs/algorithms.md": null, + "docs/coeff_update_spec.md": null, + "docs/equalizer_spec.md": null, + "docs/error_calc_spec.md": null, + "rtl/coeff_update.sv": null, + "rtl/dynamic_equalizer.sv": null, + "rtl/error_calc.sv": null, + "docs/awgn_spec.md": null, + "docs/equalizer_top_spec.md": null, + "rtl/elevator_control_system.sv": null, + "docs/tx_specification.md": null, + "rtl/ethernet_fifo_cdc.sv": null, + "docs/tx_mac_specification.md": null, + "verif/event_scheduler_tb.sv": null, + "docs/modified_specs.md": null, + "rtl/event_scheduler.sv": null, + "verif/tb_event_scheduler.sv": null, + "rtl/column_selector.sv": null, + "rtl/event_storage.sv": null, + "verif/tb.sv": null, + "rtl/fixed_priority_arbiter.sv": null, + "verif/fixed_priority_arbiter_tb.sv": null, + "docs/Modified_specification.md": null, + "docs/GCD_specification.md": null, + "docs/crypto_accelerator_specification.md": null, + "docs/modular_exponentiation_specification.md": null, + "docs/modular_multiplier_specification.md": null, + "rtl/gcd_controlpath_3.sv": null, + "rtl/gcd_controlpath_4.sv": null, + "rtl/gcd_datapath_5.sv": null, + "rtl/gcd_datapath_6.sv": null, + "rtl/gcd_top_1.sv": null, + "rtl/gcd_top_2.sv": null, + "rtl/modular_exponentiation.sv": null, + "rtl/modular_multiplier.sv": null, + "rtl/lfsr_8bit.sv": null, + "verif/lfsr_8bit_tb.sv": null, + "rtl/bit16_lfsr.sv": null, + "rtl/low_power_ctrl.sv": null, + "rtl/sync_fifo.sv": null, + "verif/tb_low_power_channel.sv": null, + "rtl/cross_domain_sync.sv": null, + "rtl/dsp_input_stage.sv": null, + "rtl/dsp_output_stage.sv": null, + "rtl/lfsr_generator.sv": null, + "rtl/monte_carlo_dsp_monitor_top.sv": null, + "verif/monte_carlo_dsp_monitor_top_tb.sv": null, + "docs/multiplexer_specification.md": null, + "verif/multiplexer_tb.sv": null, + "docs/nbit_swizzling_spec.md": null, + "verif/nbit_swizzling_tb.sv": null, + "docs/nmea_decoder_spec.md": null, + "rtl/nmea_decoder.sv": null, + "verif/nmea_decoder_tb.sv": null, + "docs/fifo.md": null, + "rtl/fifo_memory.sv": null, + "rtl/read_to_write_pointer_sync.sv": null, + "rtl/rptr_empty.sv": null, + "rtl/wptr_full.sv": null, + "rtl/write_to_read_pointer_sync.sv": null, + "docs/spec.md": null, + "verif/async_filo_tb.sv": null, + "docs/axilite_to_pcie_config_module.md": null, + "rtl/axi4lite_to_pcie_cfg_bridge.sv": null, + "rtl/axis_broadcast.sv": null, + "verif/tb_axis_broadcast.sv": null, + "docs/axis_to_uart_tx_specs.md": null, + "docs/uart_rx_to_axis_specs.md": null, + "rtl/barrel_shifter.sv": null, + "verif/barrel_shifter_tb.sv": null, + "rtl/bcd_adder.sv": null, + "rtl/full_adder.sv": null, + "rtl/four_bit_adder.sv": null, + "rtl/search_binary_search_tree.sv": null, + "rtl/delete_node_binary_search_tree.sv": null, + "docs/bst_operations.md": null, + "rtl/binary_search_tree_sort_construct.sv": null, + "docs/Spec.md": null, + "verif/tb_binary_to_gray.sv": null, + "verif/tb_custom_byte_enable_ram.sv": null, + "verif/cache_controller_tb.sv": null, + "rtl/caesar_cipher.sv": null, + "verif/caesar_cipher_tb.sv": null, + "verif/tb_pseudoRandGenerator_ca.sv": null, + "docs/continuous_adder_specification.md": null, + "verif/continuous_adder_tb.sv": null, + "rtl/fifo_buffer.sv": null, + "verif/tb_fifo_buffer.sv": null, + "docs/direct_map_cache_spec.md": null, + "verif/tb_direct_map_cache.sv": null, + "rtl/direct_map_cache.sv": null, + "rtl/dual_port_memory.sv": null, + "rtl/gen_cos_sin_lut.sv": null, + "rtl/phase_lut.sv": null, + "rtl/phase_rotation.sv": null, + "rtl/power4.sv": null, + "rtl/saturation.sv": null, + "rtl/top_phase_rotation.sv": null, + "docs/spec_viterbi.md": null, + "docs/spec_slicer_top.md": null, + "docs/spec_top_phase_rotation.md": null, + "rtl/slicer.sv": null, + "rtl/slicer_top.sv": null, + "docs/swizzler_specification.md": "# Swizzler Specification Document\n\n## Introduction\n\nThe Swizzler module is a configurable hardware component designed to perform lane remapping (swizzling) on a multi-lane data bus. It allows for flexible data routing by rearranging the input data lanes according to an encoded swizzle map. This version of the Swizzler adds advanced features including an operation mode input for additional control, invalid mapping detection, a three-stage pipeline with bit reversal processing, and optional parity checking and output registering.\n\n## Functional Overview\n\n1. **Data Unpacking:** \n The flat input bus (`data_in`) is partitioned into individual data lanes. Each lane is extracted based on the defined data width.\n\n2. **Swizzle Map Unpacking:** \n The encoded flat swizzle map (`swizzle_map_flat`) is converted into an array of mapping values. The width of each element is defined as `$clog2(NUM_LANES)+1`, which provides extra bits for error detection.\n\n3. **Invalid Mapping Detection:** \n Each element of the swizzle map is compared against `NUM_LANES` to detect invalid mapping values. If any element is out of the valid range, an invalid mapping flag is raised and later captured by the pipeline.\n\n4. **Lane Remapping:** \n In normal operation, the module remaps the input lanes based on the swizzle map. When the `bypass` signal is asserted, the input lanes pass through unchanged. The lower bits of each mapping element are used as the valid index for lane selection.\n\n5. **Pipeline Stage 1:** \n The remapped (or bypassed) lanes are captured into a set of registers. This stage creates a buffered version of the swizzled lanes that can be further processed.\n\n6. **Pipeline Stage 2:** \n The current `operation_mode` is captured into a register along with the invalid mapping detection signal. This stage isolates control and error status information before final processing.\n\n7. **Bit Reversal:** \n A bit reversal function processes each lane. In the final pipeline stage, the bits of each captured lane are reversed to produce the final output data.\n\n8. **Pipeline Stage 3:** \n The bit-reversed lanes are stored in a final set of registers, which are then repacked into the flat output bus (`data_out`). Depending on the configuration, the final output may be registered or directly passed through combinational logic.\n\n9. **Optional Parity Checking:** \n When parity checking is enabled, the module calculates the parity for each final output lane. If any lane has nonzero parity, the `parity_error` output is asserted.\n\n10. **Invalid Mapping Error Output:** \n The result of invalid mapping detection is propagated to the top level via the `invalid_mapping_error` output, signaling if any swizzle map element is outside the allowed range.\n\n## Module Interface\n\n### Parameters\n\n- **NUM_LANES** \n Number of data lanes in the module.\n\n- **DATA_WIDTH** \n Width of each data lane in bits.\n\n- **REGISTER_OUTPUT** \n Determines whether the final output data is registered. If set to 1, data is clocked out; if 0, data is passed combinationally.\n\n- **ENABLE_PARITY_CHECK** \n Enables parity error detection across the output lanes when set to 1.\n\n- **OP_MODE_WIDTH** \n Defines the width of the operation mode input, used for auxiliary control purposes.\n\n- **SWIZZLE_MAP_WIDTH** \n Calculated as `$clog2(NUM_LANES)+1`, this defines the width of each element in the swizzle map, allowing for error detection by providing an extra bit.\n\n### Ports\n\n- **clk (input):** \n Clock signal for synchronizing operations.\n\n- **rst_n (input):** \n Active-low reset that initializes internal registers.\n\n- **bypass (input):** \n When asserted, the module bypasses the swizzling logic and forwards the input lanes directly to the output.\n\n- **data_in (input):** \n Flat data input bus with a width of `NUM_LANES * DATA_WIDTH`.\n\n- **swizzle_map_flat (input):** \n Flat swizzle map with a width of `NUM_LANES * SWIZZLE_MAP_WIDTH` which specifies the remapping of input lanes.\n\n- **operation_mode (input):** \n Input specifying the operational mode. Captured and used in pipeline stage 2 for additional control.\n\n- **data_out (output):** \n Flat data output bus with a width of `NUM_LANES * DATA_WIDTH` that carries the processed (remapped and bit-reversed) data.\n\n- **parity_error (output):** \n When parity checking is enabled, this output is asserted if any lane\u2019s computed parity is nonzero.\n\n- **invalid_mapping_error (output):** \n Indicates that one or more elements in the swizzle map contained an invalid mapping (i.e., a mapping value not less than NUM_LANES).\n\n```verilog\nmodule swizzler #(\n parameter integer NUM_LANES = 4,\n parameter integer DATA_WIDTH = 8,\n parameter integer REGISTER_OUTPUT = 0,\n parameter integer ENABLE_PARITY_CHECK = 0,\n parameter integer OP_MODE_WIDTH = 2,\n parameter integer SWIZZLE_MAP_WIDTH = $clog2(NUM_LANES)+1\n)(\n input wire clk,\n input wire rst_n,\n input wire bypass,\n input wire [NUM_LANES*DATA_WIDTH-1:0] data_in,\n input wire [NUM_LANES*SWIZZLE_MAP_WIDTH-1:0] swizzle_map_flat,\n input wire [OP_MODE_WIDTH-1:0] operation_mode,\n output reg [NUM_LANES*DATA_WIDTH-1:0] data_out,\n output reg parity_error,\n output reg invalid_mapping_error\n);\n // Internal RTL implementation as described in the functional overview.\nendmodule", + "verif/swizzler_tb.sv": "`timescale 1ns/1ps\n\nmodule tb_swizzler;\n parameter NUM_LANES = 4;\n parameter DATA_WIDTH = 8;\n parameter REGISTER_OUTPUT = 1;\n parameter ENABLE_PARITY_CHECK = 0;\n parameter OP_MODE_WIDTH = 2;\n parameter SWIZZLE_MAP_WIDTH = 3;\n\n reg clk;\n reg rst_n;\n reg bypass;\n reg [NUM_LANES*DATA_WIDTH-1:0] data_in;\n reg [NUM_LANES*SWIZZLE_MAP_WIDTH-1:0] swizzle_map_flat;\n reg [OP_MODE_WIDTH-1:0] operation_mode;\n wire [NUM_LANES*DATA_WIDTH-1:0] data_out;\n wire parity_error;\n wire invalid_mapping_error;\n\n swizzler #(\n .NUM_LANES(NUM_LANES),\n .DATA_WIDTH(DATA_WIDTH),\n .REGISTER_OUTPUT(REGISTER_OUTPUT),\n .ENABLE_PARITY_CHECK(ENABLE_PARITY_CHECK),\n .OP_MODE_WIDTH(OP_MODE_WIDTH),\n .SWIZZLE_MAP_WIDTH(SWIZZLE_MAP_WIDTH)\n ) dut (\n .clk(clk),\n .rst_n(rst_n),\n .bypass(bypass),\n .data_in(data_in),\n .swizzle_map_flat(swizzle_map_flat),\n .operation_mode(operation_mode),\n .data_out(data_out),\n .parity_error(parity_error),\n .invalid_mapping_error(invalid_mapping_error)\n );\n\n reg [DATA_WIDTH-1:0] expected [0:NUM_LANES-1];\n reg [DATA_WIDTH-1:0] out_lane [0:NUM_LANES-1];\n integer i;\n\n function [DATA_WIDTH-1:0] bit_reverse;\n input [DATA_WIDTH-1:0] in;\n integer j;\n reg [DATA_WIDTH-1:0] out;\n begin\n out = 0;\n for(j = 0; j < DATA_WIDTH; j = j + 1)\n out[j] = in[DATA_WIDTH-1-j];\n bit_reverse = out;\n end\n endfunction\n\n function [DATA_WIDTH-1:0] get_lane;\n input integer index;\n begin\n get_lane = data_out[DATA_WIDTH*(index+1)-1 -: DATA_WIDTH];\n end\n endfunction\n\n initial begin\n clk = 0;\n forever #5 clk = ~clk;\n end\n\n initial begin\n rst_n = 0;\n bypass = 0;\n data_in = 0;\n swizzle_map_flat = 0;\n operation_mode = 0;\n #12;\n rst_n = 1;\n repeat (5) @(posedge clk);\n // TEST 1: Bypass disabled, identity mapping with bit reversal.\n data_in = {8'h04, 8'h03, 8'h02, 8'h01};\n swizzle_map_flat = {3'b011, 3'b010, 3'b001, 3'b000};\n bypass = 0;\n operation_mode = 0;\n repeat (5) @(posedge clk);\n for(i = 0; i < NUM_LANES; i = i + 1)\n out_lane[i] = get_lane(i);\n expected[0] = bit_reverse(8'h01);\n expected[1] = bit_reverse(8'h02);\n expected[2] = bit_reverse(8'h03);\n expected[3] = bit_reverse(8'h04);\n if(out_lane[0]==expected[0] && out_lane[1]==expected[1] &&\n out_lane[2]==expected[2] && out_lane[3]==expected[3])\n $display(\"TEST 1 PASS\");\n else\n $display(\"TEST 1 FAIL: Expected %h %h %h %h, Got %h %h %h %h\",\n expected[0], expected[1], expected[2], expected[3],\n out_lane[0], out_lane[1], out_lane[2], out_lane[3]);\n if(invalid_mapping_error==0)\n $display(\"TEST 1 INVALID MAPPING PASS\");\n else\n $display(\"TEST 1 INVALID MAPPING FAIL\");\n\n // TEST 2: Reverse mapping.\n data_in = {8'hAA, 8'hBB, 8'hCC, 8'hDD};\n swizzle_map_flat = {3'b000, 3'b001, 3'b010, 3'b011};\n bypass = 0;\n operation_mode = 0;\n repeat (5) @(posedge clk);\n for(i = 0; i < NUM_LANES; i = i + 1)\n out_lane[i] = get_lane(i);\n // Expected output is reversed compared to input lane order.\n expected[0] = bit_reverse(8'hAA);\n expected[1] = bit_reverse(8'hBB);\n expected[2] = bit_reverse(8'hCC);\n expected[3] = bit_reverse(8'hDD);\n if(out_lane[0]==expected[0] && out_lane[1]==expected[1] &&\n out_lane[2]==expected[2] && out_lane[3]==expected[3])\n $display(\"TEST 2 PASS\");\n else\n $display(\"TEST 2 FAIL: Expected %h %h %h %h, Got %h %h %h %h\",\n expected[0], expected[1], expected[2], expected[3],\n out_lane[0], out_lane[1], out_lane[2], out_lane[3]);\n\n // TEST 3: Bypass mode active.\n data_in = {8'h11, 8'h22, 8'h33, 8'h44};\n swizzle_map_flat = {3'b001, 3'b000, 3'b011, 3'b010};\n bypass = 1;\n operation_mode = 0;\n repeat (5) @(posedge clk);\n for(i = 0; i < NUM_LANES; i = i + 1)\n out_lane[i] = get_lane(i);\n expected[0] = bit_reverse(8'h44);\n expected[1] = bit_reverse(8'h33);\n expected[2] = bit_reverse(8'h22);\n expected[3] = bit_reverse(8'h11);\n if(out_lane[0]==expected[0] && out_lane[1]==expected[1] &&\n out_lane[2]==expected[2] && out_lane[3]==expected[3])\n $display(\"TEST 3 PASS\");\n else\n $display(\"TEST 3 FAIL: Expected %h %h %h %h, Got %h %h %h %h\",\n expected[0], expected[1], expected[2], expected[3],\n out_lane[0], out_lane[1], out_lane[2], out_lane[3]);\n\n // TEST 4: Invalid mapping detection.\n data_in = {8'h55, 8'h66, 8'h77, 8'h88};\n swizzle_map_flat = {3'b011, 3'b010, 3'b001, 3'b100};\n bypass = 0;\n operation_mode = 0;\n repeat (5) @(posedge clk);\n if(invalid_mapping_error==1)\n $display(\"TEST 4 PASS: Invalid mapping detected\");\n else\n $display(\"TEST 4 FAIL: Invalid mapping not detected\");\n $finish;\n end\n\nendmodule", + "rtl/swizzler.sv": "`timescale 1ns/1ps\n\nmodule swizzler #(\n parameter integer NUM_LANES = 4,\n parameter integer DATA_WIDTH = 8,\n parameter integer REGISTER_OUTPUT = 0,\n parameter integer ENABLE_PARITY_CHECK = 0,\n parameter integer OP_MODE_WIDTH = 2,\n parameter integer SWIZZLE_MAP_WIDTH = $clog2(NUM_LANES)+1\n)(\n input wire clk,\n input wire rst_n,\n input wire bypass,\n input wire [NUM_LANES*DATA_WIDTH-1:0] data_in,\n input wire [NUM_LANES*SWIZZLE_MAP_WIDTH-1:0] swizzle_map_flat,\n input wire [OP_MODE_WIDTH-1:0] operation_mode,\n output reg [NUM_LANES*DATA_WIDTH-1:0] data_out,\n output reg parity_error,\n output reg invalid_mapping_error\n);\n\n // Unpack data_in into lanes\n wire [DATA_WIDTH-1:0] lane_in [0:NUM_LANES-1];\n genvar gi;\n generate\n for (gi = 0; gi < NUM_LANES; gi = gi + 1) begin : UNPACK_INPUT\n assign lane_in[gi] = data_in[DATA_WIDTH*(gi+1)-1 : DATA_WIDTH*gi];\n end\n endgenerate\n\n // Unpack swizzle_map_flat into swizzle_map array\n wire [SWIZZLE_MAP_WIDTH-1:0] swizzle_map [0:NUM_LANES-1];\n generate\n for (gi = 0; gi < NUM_LANES; gi = gi + 1) begin : UNPACK_SWIZZLE\n assign swizzle_map[gi] = swizzle_map_flat[SWIZZLE_MAP_WIDTH*(gi+1)-1 : SWIZZLE_MAP_WIDTH*gi];\n end\n endgenerate\n\n // Invalid mapping detection\n wire [NUM_LANES-1:0] invalid_map_flag;\n generate\n for (gi = 0; gi < NUM_LANES; gi = gi + 1) begin : INVALID_CHECK\n assign invalid_map_flag[gi] = (swizzle_map[gi] >= NUM_LANES) ? 1'b1 : 1'b0;\n end\n endgenerate\n wire invalid_mapping_detected = |invalid_map_flag;\n\n // Remap lanes according to swizzle_map or bypass\n wire [DATA_WIDTH-1:0] swizzled [0:NUM_LANES-1];\n generate\n for (gi = 0; gi < NUM_LANES; gi = gi + 1) begin : REMAP\n // Use lower bits of swizzle_map to index valid lanes.\n assign swizzled[gi] = bypass ? lane_in[gi] : lane_in[ swizzle_map[gi][$clog2(NUM_LANES)-1:0] ];\n end\n endgenerate\n\n // Pipeline Stage 1: Capture swizzled lanes\n reg [DATA_WIDTH-1:0] swizzle_reg [0:NUM_LANES-1];\n integer i;\n always @(posedge clk or negedge rst_n) begin\n if (!rst_n)\n for (i = 0; i < NUM_LANES; i = i + 1)\n swizzle_reg[i] <= {DATA_WIDTH{1'b0}};\n else\n for (i = 0; i < NUM_LANES; i = i + 1)\n swizzle_reg[i] <= swizzled[i];\n end\n\n // Pipeline Stage 2: Capture operation mode and invalid mapping status\n reg [OP_MODE_WIDTH-1:0] op_reg;\n reg op_invalid_reg;\n always @(posedge clk or negedge rst_n) begin\n if (!rst_n) begin\n op_reg <= {OP_MODE_WIDTH{1'b0}};\n op_invalid_reg <= 1'b0;\n end else begin\n op_reg <= operation_mode;\n op_invalid_reg <= invalid_mapping_detected;\n end\n end\n\n // Bit reversal function\n function automatic [DATA_WIDTH-1:0] bit_reverse;\n input [DATA_WIDTH-1:0] in;\n integer k;\n begin\n bit_reverse = {DATA_WIDTH{1'b0}};\n for (k = 0; k < DATA_WIDTH; k = k + 1)\n bit_reverse[k] = in[DATA_WIDTH-1-k];\n end\n endfunction\n\n // Pipeline Stage 3: Final output stage with bit reversal\n reg [DATA_WIDTH-1:0] final_reg [0:NUM_LANES-1];\n integer m;\n always @(posedge clk or negedge rst_n) begin\n if (!rst_n)\n for (m = 0; m < NUM_LANES; m = m + 1)\n final_reg[m] <= {DATA_WIDTH{1'b0}};\n else\n for (m = 0; m < NUM_LANES; m = m + 1)\n final_reg[m] <= bit_reverse(swizzle_reg[m]);\n end\n\n // Pack final_reg into a flat output vector\n wire [NUM_LANES*DATA_WIDTH-1:0] final_packed;\n genvar q;\n generate\n for (q = 0; q < NUM_LANES; q = q + 1) begin : PACK_FINAL\n assign final_packed[DATA_WIDTH*(q+1)-1 : DATA_WIDTH*q] = final_reg[q];\n end\n endgenerate\n\n generate\n if (REGISTER_OUTPUT) begin : REG_FINAL\n always @(posedge clk or negedge rst_n) begin\n if (!rst_n)\n data_out <= {NUM_LANES*DATA_WIDTH{1'b0}};\n else\n data_out <= final_packed;\n end\n end else begin : COMB_FINAL\n always @* begin\n data_out = final_packed;\n end\n end\n endgenerate\n\n // Updated parity error calculation using a generate block\n generate\n if (ENABLE_PARITY_CHECK) begin : GEN_PARITY\n // Calculate parity from final_reg if parity check is enabled.\n wire [NUM_LANES-1:0] final_parity;\n genvar p;\n for (p = 0; p < NUM_LANES; p = p + 1) begin : PARITY_CALC\n assign final_parity[p] = ^final_reg[p];\n end\n wire computed_parity = |final_parity;\n always @* begin\n parity_error = computed_parity;\n end\n end else begin : NO_PARITY\n // Drive parity_error to 0 when parity check is disabled.\n always @* begin\n parity_error = 1'b0;\n end\n end\n endgenerate\n\n // Pass the invalid mapping flag\n always @* begin\n invalid_mapping_error = op_invalid_reg;\n end\n\nendmodule", + "docs/sync_serial_communication_tx_rx_spec.md": null, + "verif/sync_serial_communication_tb.sv": null, + "rtl/weight_stationary_pe.sv": null, + "verif/systolic_array_tb.sv": null, + "rtl/thermostat.v": null, + "docs/Traffic_controller.md": null, + "rtl/traffic_light_controller.sv": null, + "docs/Universal_Shift_Register_spec.md": null, + "verif/tb_universal_shift_register.sv": null, + "rtl/universal_shift_register.sv": null, + "docs/spec_conj.md": null, + "docs/spec_cross_correlation.md": null, + "docs/spec_detect_sequence.md": null, + "rtl/adder_2d_layers.sv": null, + "rtl/adder_tree_2d.sv": null, + "rtl/correlate.sv": null, + "rtl/cross_correlation.sv": null, + "docs/valid_modes.md": null, + "docs/words_counting.md": null, + "rtl/detect_sequence.sv": null, + "docs/proc_fsm_spec.md": null, + "docs/adder_tree.md": null, + "docs/coeff_ram.md": null, + "docs/poly_decimator.md": null, + "docs/poly_filter.md": null, + "docs/shift_register.md": null, + "rtl/adder_tree.sv": null, + "rtl/coeff_ram.sv": null, + "rtl/poly_filter.sv": null, + "rtl/shift_register.sv": null, + "docs/prbs_specification.md": null, + "rtl/prbs_gen_check.sv": null, + "rtl/fsm.sv": null, + "verif/fsm_tb.sv": null, + "rtl/CA_1.sv": null, + "rtl/CA_2.sv": null, + "rtl/CA_3.sv": null, + "rtl/CA_4.sv": null, + "rtl/rgb_color_space_conversion.sv": null, + "rtl/APBGlobalHistoryRegister.v": null, + "docs/signed_comparator_specification.md": null, + "verif/signed_comparator_tb.sv": null, + "rtl/sorting_engine.sv": null, + "rtl/brick_sort.sv": null, + "rtl/bubble_sort.sv": null, + "rtl/merge_sort.sv": null, + "rtl/selection_sort.sv": null + } + }, + { + "id": "cvdp_agentic_binary_search_tree_algorithms_0009", + "index": 597, + "source_config": "cvdp_agentic_code_generation_commercial", + "instruction": "Context: You are a language model that has the following file operations available at your disposal:\n - **List files in a directory** by running one of the following commands: \n - `ls`\n - `tree`\n - **Read files** by using:\n - `cat `\n - **Write files** by using:\n - `echo > `\n - **Compile Verilog** by using `iverilog` such as:\n - `iverilog -o .out -g2012 `\n - **Run Simulation** by using:\n - `vvp .out`\n - **Update the file content** by using:\n - `sed -i '3s/old/new/' file.txt`\n - **Find current working directory** by using:\n - `pwd`\n\n You will be given a prompt, and your task is to understand it and solve the given issue by using the commands mentioned above as needed. In the final step, you should create a Linux patch highlighting the necessary file updates to achieve the targeted goal.\n\n You will solve the problem step by step using the following approach of \n - thought (thinking process of the step you're going to take)\n - action (the command you will be running to get more details/context that's helpful to solve the problem)\n - observation (the output from the action you will observe based on which you will take your next step)\n\n The last step will be the final output summary and the patch itself in the following format \n - thought (the summary of what you did and some introduction of the patch file itself)\n - patch (a Linux-based patch that needs to be applied to reach the relevant solution)\n\n The patch file should only be applied to a single file to reach the required solution.\n\nTask: System Verilog testbench named `delete_node_binary_search_tree_tb.sv` in `verif` directory to stimuli and a checker that validates output for a `delete_node_binary_search_tree` module that deletes a node for a given `delete_key` in a binary search tree (BST). The task is to provide the required stimuli and add checker logic to validate the correctness of the output from the the given stimulus. The specification is located in the `docs` directory for the `delete_node_binary_search_tree` module.\n\n### Testbench Requirements: The testbench should stimuli and then checker logic.\n\n**Instantiation**\n\n- **Module Instance**: The module `delete_node_binary_search_tree` should be instantiated as `dut`, with all input and output signals connected for testing.\n\n**Input Generation**\n\n- **BST Generation**: \n - The testbench must multiple test cases with possible combinations for `keys`, `left_child`, and `right_child` which abides by the structure of the BST to achieve maximum coverage. \n - To accurately construct a BST including `keys`, `left_child`, and `right_child`, separate submodule `BST_SUB_TREE` in a file named `bst_sub_tree.sv` in the `verif` directory that generates different BSTs based on the input array provided from the testbench. To BST, different input arrays can be provided as input to the new submodule responsible for constructing the BST. Make sure that the keys are not duplicated. The module, key outputs should be the same as the key inputs, but it should left and right child pointers to make the array a BST.\n\n- Interface of `BST_SUB_TREE` : \n \n - Inputs:\n - `[ARRAY_SIZE*DATA_WIDTH-1:0] data_in`: A packed array for which the BST is to be constructed. \n - `start`: Active high signal to initiate the BST generation.\n - `clk` and `reset`: Clock and reset signals. Submodule should be triggered on the posedge of the clk, and reset should be active high asynchronous\n\n - Outputs:\n - `done`: Active high signal to show that the BST is generated.\n - `[ARRAY_SIZE*DATA_WIDTH-1:0] keys`: A packed array containing the node values of the BST.\n - `[ARRAY_SIZE*($clog2(ARRAY_SIZE)+1)-1:0] left_child`: A packed array containing the left child pointers for each node in the BST.\n - `[ARRAY_SIZE*($clog2(ARRAY_SIZE)+1)-1:0] right_child`: A packed array containing the right child pointers for each node in the BST.\n \n\n- **Delete Key (`delete_key`) Generation**: \n - The testbench must different random values of `delete_key` to achieve different scenarios of possible keys to be deleted to achieve maximum coverage\n \n- **Control Signal Handling**:\n\n - The `start` signal should be asserted to trigger the deletion process, and the testbench must wait until the `complete_deletion` signal is asserted (to wait for the deletion to be completed) when the delete is valid or wait until the `delete_invalid` is asserted when the `delete_key` is not found within the tree or when the tree is empty. \n - The new inputs `keys`, `left_child`, `right_child`, and `delete_key` along with the `start` signal must only be asserted after the `complete_deletion` or `delete_invalid` signal for the previous input array is asserted to high. This process must be repeated to cover different sequences of the input array, which means different BSTs will be generated. \n\n### Output Validation: \n\nThe testbench should be implemented to include the following checker logic:\n\n - **Validating assertion of Control signals**: The assertion of the control signals `complete_deletion` and `delete_invalid` should be validated. \n \n - **Reference Model**: Use a reference model `delete_bst_key` that deletes a given node. If the `delete_key` node doesn\u2019t exist in the BST, it does nothing. If the node has 0 or 1 child, it directly replaces the node\u2019s key/pointers with its child (or invalidate if leaf). If the node has 2 children, it finds the inorder successor in the right subtree, copies that key up, and then removes or replaces the successor node with its immediate right node if it exists. \n\n\n### Latency Validation:\n\n- The testbench should verify the latency until either the `complete_deletion` signal or the `delete_invalid` signal is asserted. The number of clock cycles between the `start` and `complete_deletion` or `delete_invalid` signals should be checked against the expected latency. Due to the complex nature of the `delete_node_binary_search_tree` design, it is difficult to calculate latency for different input scenarios. The testbench must, therefore, restrict the expected latency calculation to only some simple and worst-case scenarios in skewed trees and latency for searching an empty tree, as described in the RTL specification.\n-----\n\n### Simulation Control\n- Execute the test cases using procedural blocks, monitoring the process with appropriate delays and synchronization methods.\n- Use `$display` for logging results and `$error` for mismatches to facilitate debugging.\n\n### Test Procedure\n\n1. Initialization and Reset: An initial reset to the dut before starting the test sequence should be applied.\n2. the input stimuli for different cases as mentioned in **BST Generation** and **Delete Key Generation**\n3. Provide the set of test cases as inputs to the design.\n4. Use the reference deletion implementation on the provided `delete_key` and the **BST** to find out if the `delete_key` is present and to the modified BST with the `delete_key` replaced or deleted according to the different deletion scenarios. \n5. Validate the output for the generated stimuli as explained in Output Validation.\n6. Validate the latency calculated against the expected latency only for the above-mentioned scenarios. \n\n\n## Deliverables\nProvide a **complete SystemVerilog testbench** that effectively generates the test cases and includes checker logic that verifies the `delete_node_binary_search_tree` module's functionality to ensure it correctly performs the deletion of the given input key.", + "verilog_code": { + "code_block_1_0": "delete_node_binary_search_tree_tb.sv", + "code_block_1_2": "delete_node_binary_search_tree", + "code_block_1_5": "delete_node_binary_search_tree", + "code_block_1_6": "delete_node_binary_search_tree", + "code_block_1_18": "[ARRAY_SIZE*DATA_WIDTH-1:0] data_in", + "code_block_1_23": "[ARRAY_SIZE*DATA_WIDTH-1:0] keys", + "code_block_1_24": "[ARRAY_SIZE*($clog2(ARRAY_SIZE)+1)-1:0] left_child", + "code_block_1_25": "[ARRAY_SIZE*($clog2(ARRAY_SIZE)+1)-1:0] right_child", + "code_block_1_48": "delete_node_binary_search_tree", + "code_block_1_54": "delete_node_binary_search_tree", + "code_block_1_62": "(2^(clog2(ARRAY_SIZE) + 1) - 1", + "code_block_1_63": "[ARRAY_SIZE*DATA_WIDTH-1:0] keys", + "code_block_1_64": "[ARRAY_SIZE*($clog2(ARRAY_SIZE)+1)-1:0] left_child", + "code_block_1_65": "[ARRAY_SIZE*($clog2(ARRAY_SIZE)+1)-1:0] right_child", + "code_block_1_66": "[$clog2(ARRAY_SIZE):0] root", + "code_block_1_68": "[DATA_WIDTH-1:0] delete_key", + "code_block_1_80": "[ARRAY_SIZE*DATA_WIDTH-1:0] modified_keys", + "code_block_1_81": "[ARRAY_SIZE*($clog2(ARRAY_SIZE)+1)-1:0] modified_left_child", + "code_block_1_82": "[ARRAY_SIZE*($clog2(ARRAY_SIZE)+1)-1:0] modified_right_child", + "code_block_1_91": "S_FIND_INORDER_SUCCESSOR", + "code_block_1_122": "keys = [10, 5, 15, 3, 12, 20]", + "code_block_1_123": "left_child = [1, 3, 4, 15, 15, 15]", + "code_block_1_124": "right_child = [2, 15, 5, 15, 15, 15]", + "code_block_1_130": "S_FIND_INORDER_SUCCESSOR", + "code_block_2_0": "output for a `delete_node_binary_search_tree` module that deletes a node for a given `delete_key` in a binary search tree (BST). The task is to provide the required stimuli and add checker logic to validate the correctness of the output from the design for the given stimulus. The specification is located in the `docs` directory for the `delete_node_binary_search_tree` module.\n\n### Testbench Requirements: The testbench should generate stimuli and then implement checker logic.\n\n**Instantiation**\n\n- **Module Instance**: The module `delete_node_binary_search_tree` should be instantiated as `dut`, with all input and output signals connected for testing.\n\n**Input Generation**\n\n- **BST Generation**: \n - The testbench must generate multiple test cases with possible combinations for `keys`, `left_child`, and `right_child` which abides by the structure of the BST to achieve maximum coverage. \n - To accurately construct a BST including `keys`, `left_child`, and `right_child`, create a separate submodule `BST_SUB_TREE` in a file named `bst_sub_tree.sv` in the `verif` directory that generates different BSTs based on the input array provided from the testbench. To generate a BST, different input arrays can be provided as input to the new submodule responsible for constructing the BST. Make sure that the keys are not duplicated. The module, key outputs should be the same as the key inputs, but it should generate left and right child pointers to make the array a BST.\n\n- Interface of `BST_SUB_TREE` : \n \n - Inputs:\n - `[ARRAY_SIZE*DATA_WIDTH-1:0] data_in`: A packed array for which the BST is to be constructed. \n - `start`: Active high signal to initiate the BST generation.\n - `clk` and `reset`: Clock and reset signals. Submodule should be triggered on the posedge of the clk, and reset should be active high asynchronous\n\n - Outputs:\n - `done`: Active high signal to show that the BST is generated.\n - `[ARRAY_SIZE*DATA_WIDTH-1:0] keys`: A packed array containing the node values of the BST.\n - `[ARRAY_SIZE*($clog2(ARRAY_SIZE)+1)-1:0] left_child`: A packed array containing the left child pointers for each node in the BST.\n - `[ARRAY_SIZE*($clog2(ARRAY_SIZE)+1)-1:0] right_child`: A packed array containing the right child pointers for each node in the BST.\n \n\n- **Delete Key (`delete_key`) Generation**: \n - The testbench must generate different random values of `delete_key` to achieve different scenarios of possible keys to be deleted to achieve maximum coverage\n \n- **Control Signal Handling**:\n\n - The `start` signal should be asserted to trigger the deletion process, and the testbench must wait until the `complete_deletion` signal is asserted (to wait for the deletion to be completed) when the delete is valid or wait until the `delete_invalid` is asserted when the `delete_key` is not found within the tree or when the tree is empty. \n - The new inputs `keys`, `left_child`, `right_child`, and `delete_key` along with the `start` signal must only be asserted after the `complete_deletion` or `delete_invalid` signal for the previous input array is asserted to high. This process must be repeated to cover different sequences of the input array, which means different BSTs will be generated. \n\n### Output Validation: \n\nThe testbench should be implemented to include the following checker logic:\n\n - **Validating assertion of Control signals**: The assertion of the control signals `complete_deletion` and `delete_invalid` should be validated. \n \n - **Reference Model**: Use a reference model `delete_bst_key` that deletes a given node. If the `delete_key` node doesn\u2019t exist in the BST, it does nothing. If the node has 0 or 1 child, it directly replaces the node\u2019s key/pointers with its child (or invalidate if leaf). If the node has 2 children, it finds the inorder successor in the right subtree, copies that key up, and then removes or replaces the successor node with its immediate right node if it exists. \n\n\n### Latency Validation:\n\n- The testbench should verify the latency until either the `complete_deletion` signal or the `delete_invalid` signal is asserted. The number of clock cycles between the `start` and `complete_deletion` or `delete_invalid` signals should be checked against the expected latency. Due to the complex nature of the `delete_node_binary_search_tree` design, it is difficult to calculate latency for different input scenarios. The testbench must, therefore, restrict the expected latency calculation to only some simple and worst-case scenarios in skewed trees and latency for searching an empty tree, as described in the RTL specification.\n-----\n\n### Simulation Control\n- Execute the test cases using procedural blocks, monitoring the process with appropriate delays and synchronization methods.\n- Use `$display` for logging results and `$error` for mismatches to facilitate debugging.\n\n### Test Procedure\n\n1. Initialization and Reset: An initial reset to the dut before starting the test sequence should be applied.\n2. Generate the input stimuli for different cases as mentioned in **BST Generation** and **Delete Key Generation**\n3. Provide the set of test cases as inputs to the design.\n4. Use the reference deletion implementation on the provided `delete_key` and the **BST** to find out if the `delete_key` is present and to generate the modified BST with the `delete_key` replaced or deleted according to the different deletion scenarios. \n5. Validate the output for the generated stimuli as explained in Output Validation.\n6. Validate the latency calculated against the expected latency only for the above-mentioned scenarios. \n\n\n## Deliverables\nProvide a **complete SystemVerilog testbench** that effectively generates the test cases and includes checker logic that verifies the `delete_node_binary_search_tree` module's functionality to ensure it correctly performs the deletion of the given input key. \n {'docs/specification.md': None, 'verif/tb_top_64b66b_codec.sv': None, 'docs/decoder_specification.md': None, 'rtl/aes_enc_top.sv': None, 'rtl/aes_encrypt.sv': None, 'rtl/sbox.sv': None, 'rtl/Bit_Difference_Counter.sv': None, 'rtl/Bitwise_Reduction.sv': None, 'rtl/Data_Reduction.sv': None, 'rtl/Min_Hamming_Distance_Finder.sv': None, 'verif/tb_Min_Hamming_Distance_Finder.sv': None, 'docs/alu_core_specification.md': None, 'rtl/alu_core.sv': None, 'verif/alu_core_tb.sv': None, 'docs/fifo.md': None, 'rtl/async_fifo.sv': None, 'rtl/fifo_memory.sv': None, 'rtl/load_memory.sv': None, 'rtl/read_to_write_pointer_sync.sv': None, 'rtl/rptr_empty.sv': None, 'rtl/wptr_full.sv': None, 'rtl/spi_complex_mult.sv': None, 'rtl/spi_master.sv': None, 'rtl/spi_top.sv': None, 'verif/spi_complex_mult_tb.sv': None, 'rtl/ttc_counter_lite.sv': None, 'verif/ttc_counter_lite_tb.sv': None, 'docs/UART_Specifications.md': None, 'rtl/areset_sync.sv': None, 'rtl/baud_gen.sv': None, 'rtl/cdc_sync.sv': None, 'rtl/uart_rx.sv': None, 'rtl/uart_tx.sv': None, 'rtl/blake2s_G.v': None, 'rtl/blake2s_core.v': None, 'rtl/blake2s_m_select.v': None, 'verif/blake2s_core_finish_and_update_sanity_check.sv': None, 'rtl/blake2s.v': None, 'verif/blake2s_not_readable_addresses_check.sv': None, 'rtl/csr_apb_interface.sv': None, 'rtl/direct_map_cache.sv': None, 'verif/tb_direct_map_cache.sv': None, 'rtl/door_lock.sv': None, 'docs/specs.md': None, 'verif/tb_branch_control_unit.sv': None, 'verif/tb_custom_byte_enable_ram.sv': None, 'rtl/custom_byte_enable_ram.sv': None, 'rtl/caesar_cipher.sv': None, 'rtl/cic_decimator.sv': None, 'verif/coffee_machine_testbench.sv': None, 'docs/continuous_adder_specification.md': None, 'rtl/continuous_adder.sv': None, 'verif/continuous_adder_tb.sv': None, 'verif/blake2s_core_state_liveness_check.sv': None, 'verif/blake2s_core_reset_and_ready_sanity_check.sv': None, 'rtl/adder_tree.sv': None, 'rtl/coeff_ram.sv': None, 'rtl/poly_filter.sv': None, 'rtl/poly_interpolator.sv': None, 'rtl/shift_register.sv': None, 'docs/poly_filter.md': None, 'rtl/rgb_color_space_hsv.sv': None, 'verif/tb_linear_search.sv': None, 'docs/simd_datapath_specs.md': None, 'docs/simd_lane_specs.md': None, 'rtl/sorting_engine.sv': None, 'verif/sorting_engine_testbench.sv': None, 'docs/order_matching_engine_specification.md': None, 'verif/order_matching_engine_testbench.sv': None, 'rtl/fixed_priority_arbiter.sv': None, 'verif/fixed_priority_arbiter_tb.sv': None, 'docs/Helmholtz_Audio_Spec.md': None, 'rtl/helmholtz_resonator.sv': None, 'rtl/modulator.sv': None, 'rtl/resonator_bank.sv': None, 'rtl/soft_clipper.sv': None, 'docs/specs_tb.md': None, 'docs/image_stego_specification.md': None, 'verif/image_stego_tb.sv': None, 'rtl/top_inv_manchester_codec.sv': None, 'rtl/jpeg_runlength_enc.sv': None, 'rtl/jpeg_runlength_rzs.sv': None, 'rtl/jpeg_runlength_stage1.sv': None, 'docs/8Bit_lfsr_spec.md': None, 'rtl/memory_scheduler.sv': None, 'docs/multiplexer_specification.md': None, 'rtl/multiplexer.sv': None, 'verif/multiplexer_tb.sv': None, 'docs/nbit_swizzling_spec.md': None, 'verif/nbit_swizzling_tb.sv': None, 'docs/nmea_decoder_spec.md': None, 'verif/nmea_decoder_tb.sv': None, 'rtl/axi4lite_to_pcie_cfg_bridge.sv': None, 'rtl/axis_to_uart_tx.sv': None, 'rtl/uart_rx_to_axis.sv': None, 'rtl/axis_to_uart.sv': None, 'rtl/barrel_shifter.sv': None, 'verif/barrel_shifter_tb.sv': None, 'docs/bcd_adder_spec.md': None, 'verif/tb_bcd_adder.sv': None, 'rtl/bcd_adder.sv': None, 'rtl/bcd_top.sv': None, 'rtl/multi_digit_bcd_add_sub.sv': None, 'rtl/full_adder.sv': None, 'rtl/four_bit_adder.sv': None, 'verif/bcd_to_excess_3_tb.sv': None, 'docs/deletion_specification.md': \"## Specification\\n\\nThe BST is a structure formed where each node contains a key, with its `left_child` containing `keys` less than the node, and its `right_child` containing `keys` greater than the node. The module deletes the `delete_key` in the input BST. The BST is constructed in a way that traversing to the nodes results in a sorted array. The module doesn't wait for the complete BST to be traversed. As soon as the `delete_key` is found, the module stops its search and transitions to the stage where the key is deleted based on the number of possible children (no, one or two children). Additionally, it is expected that the keys are not duplicated.\\n\\n---\\n\\n### Invalid Key and Pointer Values\\n- **Invalid key value:** `(2^DATA_WIDTH) - 1`\\n- **Invalid pointer value for left_child and right_child:** `(2^(clog2(ARRAY_SIZE) + 1) - 1`\\n\\n---\\n### Parameters:\\n- DATA_WIDTH (default 31): Width of a single element, greater than 0.\\n- ARRAY_SIZE (default 16): Number of elements in the array, will be greater than 0 \\n\\n### Inputs:\\n- `[ARRAY_SIZE*DATA_WIDTH-1:0] keys`: A packed array containing the node values of the BST. \\n- `[ARRAY_SIZE*($clog2(ARRAY_SIZE)+1)-1:0] left_child`: A packed array containing the left child pointers for each node in the BST.\\n- `[ARRAY_SIZE*($clog2(ARRAY_SIZE)+1)-1:0] right_child`: A packed array containing the right child pointers for each node in the BST.\\n- `[$clog2(ARRAY_SIZE):0] root`: The index of the root node (always 0 except for an empty BST, assuming the BST is constructed such that the first element in the arrays corresponds to the root node). For an empty BST, `root` is assigned an invalid index where all bits are set to 1; Eg, 15 (for ARRAY_SIZE = 7).\\n- `[DATA_WIDTH-1:0] delete_key`: The key to delete in the BST.\\n- `start`: 1-bit active high signal to initiate the deletion (1 clock cycle in duration).\\n- `clk`: Clock Signal. The design is synchronized to the positive edge of this clock.\\n- `reset`: Asynchronous active high reset to reset all control signal outputs to zero and `modified_keys`, `modified_left_child`, and `modified_right_child` to null (invalid) values.\\n\\n### Outputs:\\n- `complete_deletion`: 1-bit active high signal that is asserted once the deletion is complete, indicating that the key was deleted successfully (1 clock cycle in duration). If the `delete_key` is not found and could not be deleted in the constructed BST, or if the tree is empty, `complete_deletion` remains at 0.\\n- `delete_invalid`: 1-bit Active high signal that is asserted when the BST is empty or when the `delete_key` doesn't exist in the given BST (1 clock cycle in duration). \\n- `[ARRAY_SIZE*DATA_WIDTH-1:0] modified_keys`: Updated array of node keys after deletion. The values are valid for one clock cycle following the completion of the deletion, after which they are reset to an invalid pointer value.\\n- `[ARRAY_SIZE*($clog2(ARRAY_SIZE)+1)-1:0] modified_left_child`: Updated array of left child pointers after deletion. The values are valid for one clock cycle following the completion of the deletion, after which they are reset to an invalid pointer value.\\n- `[ARRAY_SIZE*($clog2(ARRAY_SIZE)+1)-1:0] modified_right_child`: Updated array of right child pointers after deletion. The values are valid for one clock cycle following the completion of the deletion, after which they are reset to an invalid pointer value.\\n\\n---\\n\\n### Deletion Scenarios\\n1. **Node with Both Left and Right Children:**\\n - Find the inorder successor (the leftmost node in the right subtree).\\n - Replace the node's key with the in-order successor's key.\\n - Delete or replace the inorder successor node with its immediate right node if it exists.\\n\\n2. **Node with Only Left Child:**\\n - Replace the node's key and pointers with those of its left child.\\n - Mark the left child's original position as invalid.\\n\\n3. **Node with Only Right Child:**\\n - Replace the node's key and pointers with those of its right child.\\n - Mark the right child's original position as invalid.\\n\\n4. **Node with No Children**\\n - Mark the node's key and pointers as invalid.\\n\\n---\\n\\n### Implementation details \\n\\n**FSM (Finite State Machine) Design**:\\nThe delete processes must be controlled by an FSM. \\n\\n- **S_IDLE**: The system resets intermediate variables and the outputs and waits for the `start` signal.\\n- **S_INIT**: The search begins by comparing the `delete_key` with the root node and decides the direction of traversal (left or right).\\n- **S_SEARCH_LEFT**: The FSM traverses the left subtree if the `delete_key` is less than the `root` node.\\n- **S_SEARCH_RIGHT**: The FSM traverses the right subtree if the `delete_key` is greater than the `root` node.\\n- **S_DELETE**: The FSM deletes the key based on the number of children and different combinations. It traverses to `S_DELETE_COMPLETE` for completion. But when the `delete_key` has both children, it first traverses to `S_FIND_INORDER_SUCCESSOR`.\\n- **S_DELETE_COMPLETE**: The FSM outputs the signals `complete_deletion`, `delete_invalid`, and the keys and pointer of the modified tree.\\n- **S_FIND_INORDER_SUCCESSOR**: The FSM finds the in-order successor of the `delete_key`. It traverses to the right child and stays in the same state until it encounters a left child with no key, then traverses to `S_DELETE_COMPLETE`.\\n\\n---\\n**Latency Analysis**:\\n\\n- **Example 1**: The worst-case scenario is to delete the largest node in a right-skewed tree (a BST where every node only consists of a right child and no left child).\\n - **Process**:\\n - The FSM traverses the entire depth of the tree (`ARRAY_SIZE-1`) to locate the largest key.\\n - Except for the target node (largest node), the FSM traverses twice before moving to the next node. Hence it takes **`(ARRAY_SIZE-2) * 2` clock cycles**.\\n - The largest node will take **1 clock cycle**\\n - After finding the node, the deletion process `S_DELETE` takes **1 clock cycle**.\\n - The `S_INIT` and `S_DELETE_COMPLETE` states each take **1 clock cycle**.\\n - To transition from `S_IDLE` to `S_INIT` when `start` is asserted, it takes **1 clock cycle**\\n - **Total Latency**: `1` (Start) + `1` (Initialization) + {`(ARRAY_SIZE-2) * 2`} (Traversal except the largest node)+ `1` (Traversal of largest node) + `1` (Delete) + `1` (Completion).\\n\\n \\n- **Example 2**: The best case scenario is to delete the largest node in a left-skewed BST (a BST where every node only consists of a left child and no right child) and the smallest node in a right-skewed tree (a BST where every node only consists of a right child and no left child)\\n - **Process**:\\n - The FSM finds the `delete_key` at the root (largest node in a left-skewed BST or smallest node in right-skewed tree) in **1 clock cycle**, and since the position of the `delete_key` is not to be found, there is no need to traverse further to the left tree or right tree, reducing the latency significantly. \\n - The deletion process takes **1 clock cycle**.\\n - The `S_INIT` and `S_DELETE_COMPLETE` states each take **1 clock cycle**.\\n - To transition from `S_IDLE` to `S_INIT` when `start` is asserted, it takes **1 clock cycle**\\n - **Total latency** = `1` (Start) + `1` (Initialization) + `1` (Deletion) + `1` (Completion) = `4 clock cycles`.\\n\\n\\n- **Example 3**: To delete a node (15) in the given Binary Search Tree (BST) below that has both left and right children, consider the following example: \\n\\n - **BST Structure**: \\n - `keys = [10, 5, 15, 3, 12, 20]` \\n - `left_child = [1, 3, 4, 15, 15, 15]` \\n - `right_child = [2, 15, 5, 15, 15, 15]` \\n\\n - **Delete Operation**: \\n - The node to delete has the key `delete_key = 15`, which has a right child at index 6 (key = 20) and a left child at index 5 (key = 12). \\n\\n - **Process**:\\n - **Traversal Process**: \\n - Searching for the node with `key = 15` takes **1 clock cycle**. \\n\\n - **Deletion Process**: \\n - Deleting the node involves finding its in-order successor (the leftmost node in the right subtree). This process takes **2 clock cycles**: \\n 1. **1 clock cycle** to assign the right child of `delete_key` in the `S_DELETE` state. \\n 2. **1 clock cycle** to traverse to the leftmost child of the right child of `delete_key` in the `S_FIND_INORDER_SUCCESSOR` state and replace the node with its in-order successor. \\n\\n - **State Transitions**: \\n - Similar to other cases, the `S_INIT` and `S_DELETE_COMPLETE` states each take **2 clock cycles**. \\n - An additional 1 clock cycle is needed to transition from `S_IDLE` to `S_INIT` when the start is asserted.\\n \\n - **Total latency** = `1` (Start) + `1` (Initialization) + `1` (Traversal) + `2` (Deletion) + `1` (Completion) = `6 clock cycles`.\\n \\n- **Other Latency Scenarios**: \\n - Latency to delete the smallest node in a left-skewed tree: (ARRAY_SIZE - 1) + 4;\\n - Latency for an empty tree (key, left_child, right_child are invalid): 2\"}" + }, + "test_info": { + "test_criteria_0": [ + "named `delete_node_binary_search_tree_tb.sv` in `verif` directory to generate stimuli and a checker that validates output for a `delete_node_binary_search_tree` module that deletes a node for a given `delete_key` in a binary search tree (bst). the task is to provide the required stimuli and add checker logic to validate the correctness of the output from the design for the given stimulus. the specification is located in the `docs` directory for the `delete_node_binary_search_tree` module.", + "requirements: the testbench should generate stimuli and then implement checker logic.", + "ing.", + "must generate multiple test cases with possible combinations for `keys`, `left_child`, and `right_child` which abides by the structure of the bst to achieve maximum coverage. \n - to accurately construct a bst including `keys`, `left_child`, and `right_child`, create a separate submodule `bst_sub_tree` in a file named `bst_sub_tree.sv` in the `verif` directory that generates different bsts based on the input array provided from the testbench. to generate a bst, different input arrays can be provided as input to the new submodule responsible for constructing the bst. make sure that the keys are not duplicated. the module, key outputs should be the same as the key inputs, but it should generate left and right child pointers to make the array a bst.", + "must generate different random values of `delete_key` to achieve different scenarios of possible keys to be deleted to achieve maximum coverage\n \n- **control signal handling**:", + "must wait until the `complete_deletion` signal is asserted (to wait for the deletion to be completed) when the delete is valid or wait until the `delete_invalid` is asserted when the `delete_key` is not found within the tree or when the tree is empty. \n - the new inputs `keys`, `left_child`, `right_child`, and `delete_key` along with the `start` signal must only be asserted after the `complete_deletion` or `delete_invalid` signal for the previous input array is asserted to high. this process must be repeated to cover different sequences of the input array, which means different bsts will be generated.", + "should be implemented to include the following checker logic:", + "should verify the latency until either the `complete_deletion` signal or the `delete_invalid` signal is asserted. the number of clock cycles between the `start` and `complete_deletion` or `delete_invalid` signals should be checked against the expected latency. due to the complex nature of the `delete_node_binary_search_tree` design, it is difficult to calculate latency for different input scenarios. the testbench must, therefore, restrict the expected latency calculation to only some simple and worst-case scenarios in skewed trees and latency for searching an empty tree, as described in the rtl specification.\n-----", + "cases using procedural blocks, monitoring the process with appropriate delays and synchronization methods.\n- use `$display` for logging results and `$error` for mismatches to facilitate debugging.", + "procedure", + "sequence should be applied.\n2. generate the input stimuli for different cases as mentioned in **bst generation** and **delete key generation**\n3. provide the set of test cases as inputs to the design.\n4. use the reference deletion implementation on the provided `delete_key` and the **bst** to find out if the `delete_key` is present and to generate the modified bst with the `delete_key` replaced or deleted according to the different deletion scenarios. \n5. validate the output for the generated stimuli as explained in output validation.\n6. validate the latency calculated against the expected latency only for the above-mentioned scenarios.", + "** that effectively generates the test cases and includes checker logic that verifies the `delete_node_binary_search_tree` module's functionality to ensure it correctly performs the deletion of the given input key." + ], + "test_criteria_2": [ + "generate stimuli and then implement checker logic.", + "be instantiated as `dut`, with all input and output signals connected for testing.", + "be the same as the key inputs, but it should generate left and right child pointers to make the array a bst.", + "be triggered on the posedge of the clk, and reset should be active high asynchronous", + "be asserted to trigger the deletion process, and the testbench must wait until the `complete_deletion` signal is asserted (to wait for the deletion to be completed) when the delete is valid or wait until the `delete_invalid` is asserted when the `delete_key` is not found within the tree or when the tree is empty. \n - the new inputs `keys`, `left_child`, `right_child`, and `delete_key` along with the `start` signal must only be asserted after the `complete_deletion` or `delete_invalid` signal for the previous input array is asserted to high. this process must be repeated to cover different sequences of the input array, which means different bsts will be generated.", + "be implemented to include the following checker logic:", + "be validated. \n \n - **reference model**: use a reference model `delete_bst_key` that deletes a given node. if the `delete_key` node doesn\u2019t exist in the bst, it does nothing. if the node has 0 or 1 child, it directly replaces the node\u2019s key/pointers with its child (or invalidate if leaf). if the node has 2 children, it finds the inorder successor in the right subtree, copies that key up, and then removes or replaces the successor node with its immediate right node if it exists.", + "verify the latency until either the `complete_deletion` signal or the `delete_invalid` signal is asserted. the number of clock cycles between the `start` and `complete_deletion` or `delete_invalid` signals should be checked against the expected latency. due to the complex nature of the `delete_node_binary_search_tree` design, it is difficult to calculate latency for different input scenarios. the testbench must, therefore, restrict the expected latency calculation to only some simple and worst-case scenarios in skewed trees and latency for searching an empty tree, as described in the rtl specification.\n-----", + "be applied.\n2. generate the input stimuli for different cases as mentioned in **bst generation** and **delete key generation**\n3. provide the set of test cases as inputs to the design.\n4. use the reference deletion implementation on the provided `delete_key` and the **bst** to find out if the `delete_key` is present and to generate the modified bst with the `delete_key` replaced or deleted according to the different deletion scenarios. \n5. validate the output for the generated stimuli as explained in output validation.\n6. validate the latency calculated against the expected latency only for the above-mentioned scenarios." + ] + }, + "expected_behavior": [ + "generate stimuli and then implement checker logic", + "be instantiated as `dut`, with all input and output signals connected for testing", + "generate multiple test cases with possible combinations for `keys`, `left_child`, and `right_child` which abides by the structure of the BST to achieve maximum coverage", + "be the same as the key inputs, but it should generate left and right child pointers to make the array a BST", + "be triggered on the posedge of the clk, and reset should be active high asynchronous", + "generate different random values of `delete_key` to achieve different scenarios of possible keys to be deleted to achieve maximum coverage", + "be asserted to trigger the deletion process, and the testbench must wait until the `complete_deletion` signal is asserted (to wait for the deletion to be completed) when the delete is valid or wait until the `delete_invalid` is asserted when the `delete_key` is not found within the tree or when the tree is empty", + "only be asserted after the `complete_deletion` or `delete_invalid` signal for the previous input array is asserted to high", + "be repeated to cover different sequences of the input array, which means different BSTs will be generated", + "be implemented to include the following checker logic:", + "be validated", + "verify the latency until either the `complete_deletion` signal or the `delete_invalid` signal is asserted", + "be checked against the expected latency" + ], + "metadata": { + "categories": [ + "cid013", + "hard" + ], + "domain": "processor", + "complexity": "expert", + "problem_type": "design", + "has_code": true, + "has_tests": true + }, + "full_prompt": "Implement a System Verilog testbench named `delete_node_binary_search_tree_tb.sv` in `verif` directory to generate stimuli and a checker that validates output for a `delete_node_binary_search_tree` module that deletes a node for a given `delete_key` in a binary search tree (BST). The task is to provide the required stimuli and add checker logic to validate the correctness of the output from the design for the given stimulus. The specification is located in the `docs` directory for the `delete_node_binary_search_tree` module.\n\n### Testbench Requirements: The testbench should generate stimuli and then implement checker logic.\n\n**Instantiation**\n\n- **Module Instance**: The module `delete_node_binary_search_tree` should be instantiated as `dut`, with all input and output signals connected for testing.\n\n**Input Generation**\n\n- **BST Generation**: \n - The testbench must generate multiple test cases with possible combinations for `keys`, `left_child`, and `right_child` which abides by the structure of the BST to achieve maximum coverage. \n - To accurately construct a BST including `keys`, `left_child`, and `right_child`, create a separate submodule `BST_SUB_TREE` in a file named `bst_sub_tree.sv` in the `verif` directory that generates different BSTs based on the input array provided from the testbench. To generate a BST, different input arrays can be provided as input to the new submodule responsible for constructing the BST. Make sure that the keys are not duplicated. The module, key outputs should be the same as the key inputs, but it should generate left and right child pointers to make the array a BST.\n\n- Interface of `BST_SUB_TREE` : \n \n - Inputs:\n - `[ARRAY_SIZE*DATA_WIDTH-1:0] data_in`: A packed array for which the BST is to be constructed. \n - `start`: Active high signal to initiate the BST generation.\n - `clk` and `reset`: Clock and reset signals. Submodule should be triggered on the posedge of the clk, and reset should be active high asynchronous\n\n - Outputs:\n - `done`: Active high signal to show that the BST is generated.\n - `[ARRAY_SIZE*DATA_WIDTH-1:0] keys`: A packed array containing the node values of the BST.\n - `[ARRAY_SIZE*($clog2(ARRAY_SIZE)+1)-1:0] left_child`: A packed array containing the left child pointers for each node in the BST.\n - `[ARRAY_SIZE*($clog2(ARRAY_SIZE)+1)-1:0] right_child`: A packed array containing the right child pointers for each node in the BST.\n \n\n- **Delete Key (`delete_key`) Generation**: \n - The testbench must generate different random values of `delete_key` to achieve different scenarios of possible keys to be deleted to achieve maximum coverage\n \n- **Control Signal Handling**:\n\n - The `start` signal should be asserted to trigger the deletion process, and the testbench must wait until the `complete_deletion` signal is asserted (to wait for the deletion to be completed) when the delete is valid or wait until the `delete_invalid` is asserted when the `delete_key` is not found within the tree or when the tree is empty. \n - The new inputs `keys`, `left_child`, `right_child`, and `delete_key` along with the `start` signal must only be asserted after the `complete_deletion` or `delete_invalid` signal for the previous input array is asserted to high. This process must be repeated to cover different sequences of the input array, which means different BSTs will be generated. \n\n### Output Validation: \n\nThe testbench should be implemented to include the following checker logic:\n\n - **Validating assertion of Control signals**: The assertion of the control signals `complete_deletion` and `delete_invalid` should be validated. \n \n - **Reference Model**: Use a reference model `delete_bst_key` that deletes a given node. If the `delete_key` node doesn\u2019t exist in the BST, it does nothing. If the node has 0 or 1 child, it directly replaces the node\u2019s key/pointers with its child (or invalidate if leaf). If the node has 2 children, it finds the inorder successor in the right subtree, copies that key up, and then removes or replaces the successor node with its immediate right node if it exists. \n\n\n### Latency Validation:\n\n- The testbench should verify the latency until either the `complete_deletion` signal or the `delete_invalid` signal is asserted. The number of clock cycles between the `start` and `complete_deletion` or `delete_invalid` signals should be checked against the expected latency. Due to the complex nature of the `delete_node_binary_search_tree` design, it is difficult to calculate latency for different input scenarios. The testbench must, therefore, restrict the expected latency calculation to only some simple and worst-case scenarios in skewed trees and latency for searching an empty tree, as described in the RTL specification.\n-----\n\n### Simulation Control\n- Execute the test cases using procedural blocks, monitoring the process with appropriate delays and synchronization methods.\n- Use `$display` for logging results and `$error` for mismatches to facilitate debugging.\n\n### Test Procedure\n\n1. Initialization and Reset: An initial reset to the dut before starting the test sequence should be applied.\n2. Generate the input stimuli for different cases as mentioned in **BST Generation** and **Delete Key Generation**\n3. Provide the set of test cases as inputs to the design.\n4. Use the reference deletion implementation on the provided `delete_key` and the **BST** to find out if the `delete_key` is present and to generate the modified BST with the `delete_key` replaced or deleted according to the different deletion scenarios. \n5. Validate the output for the generated stimuli as explained in Output Validation.\n6. Validate the latency calculated against the expected latency only for the above-mentioned scenarios. \n\n\n## Deliverables\nProvide a **complete SystemVerilog testbench** that effectively generates the test cases and includes checker logic that verifies the `delete_node_binary_search_tree` module's functionality to ensure it correctly performs the deletion of the given input key. \n", + "system_message": "You are a language model that has the following file operations available at your disposal:\n - **List files in a directory** by running one of the following commands: \n - `ls`\n - `tree`\n - **Read files** by using:\n - `cat `\n - **Write files** by using:\n - `echo > `\n - **Compile Verilog** by using `iverilog` such as:\n - `iverilog -o .out -g2012 `\n - **Run Simulation** by using:\n - `vvp .out`\n - **Update the file content** by using:\n - `sed -i '3s/old/new/' file.txt`\n - **Find current working directory** by using:\n - `pwd`\n\n You will be given a prompt, and your task is to understand it and solve the given issue by using the commands mentioned above as needed. In the final step, you should create a Linux patch highlighting the necessary file updates to achieve the targeted goal.\n\n You will solve the problem step by step using the following approach of \n - thought (thinking process of the step you're going to take)\n - action (the command you will be running to get more details/context that's helpful to solve the problem)\n - observation (the output from the action you will observe based on which you will take your next step)\n\n The last step will be the final output summary and the patch itself in the following format \n - thought (the summary of what you did and some introduction of the patch file itself)\n - patch (a Linux-based patch that needs to be applied to reach the relevant solution)\n\n The patch file should only be applied to a single file to reach the required solution.", + "raw_context": { + "docs/specification.md": null, + "verif/tb_top_64b66b_codec.sv": null, + "docs/decoder_specification.md": null, + "rtl/aes_enc_top.sv": null, + "rtl/aes_encrypt.sv": null, + "rtl/sbox.sv": null, + "rtl/Bit_Difference_Counter.sv": null, + "rtl/Bitwise_Reduction.sv": null, + "rtl/Data_Reduction.sv": null, + "rtl/Min_Hamming_Distance_Finder.sv": null, + "verif/tb_Min_Hamming_Distance_Finder.sv": null, + "docs/alu_core_specification.md": null, + "rtl/alu_core.sv": null, + "verif/alu_core_tb.sv": null, + "docs/fifo.md": null, + "rtl/async_fifo.sv": null, + "rtl/fifo_memory.sv": null, + "rtl/load_memory.sv": null, + "rtl/read_to_write_pointer_sync.sv": null, + "rtl/rptr_empty.sv": null, + "rtl/wptr_full.sv": null, + "rtl/spi_complex_mult.sv": null, + "rtl/spi_master.sv": null, + "rtl/spi_top.sv": null, + "verif/spi_complex_mult_tb.sv": null, + "rtl/ttc_counter_lite.sv": null, + "verif/ttc_counter_lite_tb.sv": null, + "docs/UART_Specifications.md": null, + "rtl/areset_sync.sv": null, + "rtl/baud_gen.sv": null, + "rtl/cdc_sync.sv": null, + "rtl/uart_rx.sv": null, + "rtl/uart_tx.sv": null, + "rtl/blake2s_G.v": null, + "rtl/blake2s_core.v": null, + "rtl/blake2s_m_select.v": null, + "verif/blake2s_core_finish_and_update_sanity_check.sv": null, + "rtl/blake2s.v": null, + "verif/blake2s_not_readable_addresses_check.sv": null, + "rtl/csr_apb_interface.sv": null, + "rtl/direct_map_cache.sv": null, + "verif/tb_direct_map_cache.sv": null, + "rtl/door_lock.sv": null, + "docs/specs.md": null, + "verif/tb_branch_control_unit.sv": null, + "verif/tb_custom_byte_enable_ram.sv": null, + "rtl/custom_byte_enable_ram.sv": null, + "rtl/caesar_cipher.sv": null, + "rtl/cic_decimator.sv": null, + "verif/coffee_machine_testbench.sv": null, + "docs/continuous_adder_specification.md": null, + "rtl/continuous_adder.sv": null, + "verif/continuous_adder_tb.sv": null, + "verif/blake2s_core_state_liveness_check.sv": null, + "verif/blake2s_core_reset_and_ready_sanity_check.sv": null, + "rtl/adder_tree.sv": null, + "rtl/coeff_ram.sv": null, + "rtl/poly_filter.sv": null, + "rtl/poly_interpolator.sv": null, + "rtl/shift_register.sv": null, + "docs/poly_filter.md": null, + "rtl/rgb_color_space_hsv.sv": null, + "verif/tb_linear_search.sv": null, + "docs/simd_datapath_specs.md": null, + "docs/simd_lane_specs.md": null, + "rtl/sorting_engine.sv": null, + "verif/sorting_engine_testbench.sv": null, + "docs/order_matching_engine_specification.md": null, + "verif/order_matching_engine_testbench.sv": null, + "rtl/fixed_priority_arbiter.sv": null, + "verif/fixed_priority_arbiter_tb.sv": null, + "docs/Helmholtz_Audio_Spec.md": null, + "rtl/helmholtz_resonator.sv": null, + "rtl/modulator.sv": null, + "rtl/resonator_bank.sv": null, + "rtl/soft_clipper.sv": null, + "docs/specs_tb.md": null, + "docs/image_stego_specification.md": null, + "verif/image_stego_tb.sv": null, + "rtl/top_inv_manchester_codec.sv": null, + "rtl/jpeg_runlength_enc.sv": null, + "rtl/jpeg_runlength_rzs.sv": null, + "rtl/jpeg_runlength_stage1.sv": null, + "docs/8Bit_lfsr_spec.md": null, + "rtl/memory_scheduler.sv": null, + "docs/multiplexer_specification.md": null, + "rtl/multiplexer.sv": null, + "verif/multiplexer_tb.sv": null, + "docs/nbit_swizzling_spec.md": null, + "verif/nbit_swizzling_tb.sv": null, + "docs/nmea_decoder_spec.md": null, + "verif/nmea_decoder_tb.sv": null, + "rtl/axi4lite_to_pcie_cfg_bridge.sv": null, + "rtl/axis_to_uart_tx.sv": null, + "rtl/uart_rx_to_axis.sv": null, + "rtl/axis_to_uart.sv": null, + "rtl/barrel_shifter.sv": null, + "verif/barrel_shifter_tb.sv": null, + "docs/bcd_adder_spec.md": null, + "verif/tb_bcd_adder.sv": null, + "rtl/bcd_adder.sv": null, + "rtl/bcd_top.sv": null, + "rtl/multi_digit_bcd_add_sub.sv": null, + "rtl/full_adder.sv": null, + "rtl/four_bit_adder.sv": null, + "verif/bcd_to_excess_3_tb.sv": null, + "docs/deletion_specification.md": "## Specification\n\nThe BST is a structure formed where each node contains a key, with its `left_child` containing `keys` less than the node, and its `right_child` containing `keys` greater than the node. The module deletes the `delete_key` in the input BST. The BST is constructed in a way that traversing to the nodes results in a sorted array. The module doesn't wait for the complete BST to be traversed. As soon as the `delete_key` is found, the module stops its search and transitions to the stage where the key is deleted based on the number of possible children (no, one or two children). Additionally, it is expected that the keys are not duplicated.\n\n---\n\n### Invalid Key and Pointer Values\n- **Invalid key value:** `(2^DATA_WIDTH) - 1`\n- **Invalid pointer value for left_child and right_child:** `(2^(clog2(ARRAY_SIZE) + 1) - 1`\n\n---\n### Parameters:\n- DATA_WIDTH (default 31): Width of a single element, greater than 0.\n- ARRAY_SIZE (default 16): Number of elements in the array, will be greater than 0 \n\n### Inputs:\n- `[ARRAY_SIZE*DATA_WIDTH-1:0] keys`: A packed array containing the node values of the BST. \n- `[ARRAY_SIZE*($clog2(ARRAY_SIZE)+1)-1:0] left_child`: A packed array containing the left child pointers for each node in the BST.\n- `[ARRAY_SIZE*($clog2(ARRAY_SIZE)+1)-1:0] right_child`: A packed array containing the right child pointers for each node in the BST.\n- `[$clog2(ARRAY_SIZE):0] root`: The index of the root node (always 0 except for an empty BST, assuming the BST is constructed such that the first element in the arrays corresponds to the root node). For an empty BST, `root` is assigned an invalid index where all bits are set to 1; Eg, 15 (for ARRAY_SIZE = 7).\n- `[DATA_WIDTH-1:0] delete_key`: The key to delete in the BST.\n- `start`: 1-bit active high signal to initiate the deletion (1 clock cycle in duration).\n- `clk`: Clock Signal. The design is synchronized to the positive edge of this clock.\n- `reset`: Asynchronous active high reset to reset all control signal outputs to zero and `modified_keys`, `modified_left_child`, and `modified_right_child` to null (invalid) values.\n\n### Outputs:\n- `complete_deletion`: 1-bit active high signal that is asserted once the deletion is complete, indicating that the key was deleted successfully (1 clock cycle in duration). If the `delete_key` is not found and could not be deleted in the constructed BST, or if the tree is empty, `complete_deletion` remains at 0.\n- `delete_invalid`: 1-bit Active high signal that is asserted when the BST is empty or when the `delete_key` doesn't exist in the given BST (1 clock cycle in duration). \n- `[ARRAY_SIZE*DATA_WIDTH-1:0] modified_keys`: Updated array of node keys after deletion. The values are valid for one clock cycle following the completion of the deletion, after which they are reset to an invalid pointer value.\n- `[ARRAY_SIZE*($clog2(ARRAY_SIZE)+1)-1:0] modified_left_child`: Updated array of left child pointers after deletion. The values are valid for one clock cycle following the completion of the deletion, after which they are reset to an invalid pointer value.\n- `[ARRAY_SIZE*($clog2(ARRAY_SIZE)+1)-1:0] modified_right_child`: Updated array of right child pointers after deletion. The values are valid for one clock cycle following the completion of the deletion, after which they are reset to an invalid pointer value.\n\n---\n\n### Deletion Scenarios\n1. **Node with Both Left and Right Children:**\n - Find the inorder successor (the leftmost node in the right subtree).\n - Replace the node's key with the in-order successor's key.\n - Delete or replace the inorder successor node with its immediate right node if it exists.\n\n2. **Node with Only Left Child:**\n - Replace the node's key and pointers with those of its left child.\n - Mark the left child's original position as invalid.\n\n3. **Node with Only Right Child:**\n - Replace the node's key and pointers with those of its right child.\n - Mark the right child's original position as invalid.\n\n4. **Node with No Children**\n - Mark the node's key and pointers as invalid.\n\n---\n\n### Implementation details \n\n**FSM (Finite State Machine) Design**:\nThe delete processes must be controlled by an FSM. \n\n- **S_IDLE**: The system resets intermediate variables and the outputs and waits for the `start` signal.\n- **S_INIT**: The search begins by comparing the `delete_key` with the root node and decides the direction of traversal (left or right).\n- **S_SEARCH_LEFT**: The FSM traverses the left subtree if the `delete_key` is less than the `root` node.\n- **S_SEARCH_RIGHT**: The FSM traverses the right subtree if the `delete_key` is greater than the `root` node.\n- **S_DELETE**: The FSM deletes the key based on the number of children and different combinations. It traverses to `S_DELETE_COMPLETE` for completion. But when the `delete_key` has both children, it first traverses to `S_FIND_INORDER_SUCCESSOR`.\n- **S_DELETE_COMPLETE**: The FSM outputs the signals `complete_deletion`, `delete_invalid`, and the keys and pointer of the modified tree.\n- **S_FIND_INORDER_SUCCESSOR**: The FSM finds the in-order successor of the `delete_key`. It traverses to the right child and stays in the same state until it encounters a left child with no key, then traverses to `S_DELETE_COMPLETE`.\n\n---\n**Latency Analysis**:\n\n- **Example 1**: The worst-case scenario is to delete the largest node in a right-skewed tree (a BST where every node only consists of a right child and no left child).\n - **Process**:\n - The FSM traverses the entire depth of the tree (`ARRAY_SIZE-1`) to locate the largest key.\n - Except for the target node (largest node), the FSM traverses twice before moving to the next node. Hence it takes **`(ARRAY_SIZE-2) * 2` clock cycles**.\n - The largest node will take **1 clock cycle**\n - After finding the node, the deletion process `S_DELETE` takes **1 clock cycle**.\n - The `S_INIT` and `S_DELETE_COMPLETE` states each take **1 clock cycle**.\n - To transition from `S_IDLE` to `S_INIT` when `start` is asserted, it takes **1 clock cycle**\n - **Total Latency**: `1` (Start) + `1` (Initialization) + {`(ARRAY_SIZE-2) * 2`} (Traversal except the largest node)+ `1` (Traversal of largest node) + `1` (Delete) + `1` (Completion).\n\n \n- **Example 2**: The best case scenario is to delete the largest node in a left-skewed BST (a BST where every node only consists of a left child and no right child) and the smallest node in a right-skewed tree (a BST where every node only consists of a right child and no left child)\n - **Process**:\n - The FSM finds the `delete_key` at the root (largest node in a left-skewed BST or smallest node in right-skewed tree) in **1 clock cycle**, and since the position of the `delete_key` is not to be found, there is no need to traverse further to the left tree or right tree, reducing the latency significantly. \n - The deletion process takes **1 clock cycle**.\n - The `S_INIT` and `S_DELETE_COMPLETE` states each take **1 clock cycle**.\n - To transition from `S_IDLE` to `S_INIT` when `start` is asserted, it takes **1 clock cycle**\n - **Total latency** = `1` (Start) + `1` (Initialization) + `1` (Deletion) + `1` (Completion) = `4 clock cycles`.\n\n\n- **Example 3**: To delete a node (15) in the given Binary Search Tree (BST) below that has both left and right children, consider the following example: \n\n - **BST Structure**: \n - `keys = [10, 5, 15, 3, 12, 20]` \n - `left_child = [1, 3, 4, 15, 15, 15]` \n - `right_child = [2, 15, 5, 15, 15, 15]` \n\n - **Delete Operation**: \n - The node to delete has the key `delete_key = 15`, which has a right child at index 6 (key = 20) and a left child at index 5 (key = 12). \n\n - **Process**:\n - **Traversal Process**: \n - Searching for the node with `key = 15` takes **1 clock cycle**. \n\n - **Deletion Process**: \n - Deleting the node involves finding its in-order successor (the leftmost node in the right subtree). This process takes **2 clock cycles**: \n 1. **1 clock cycle** to assign the right child of `delete_key` in the `S_DELETE` state. \n 2. **1 clock cycle** to traverse to the leftmost child of the right child of `delete_key` in the `S_FIND_INORDER_SUCCESSOR` state and replace the node with its in-order successor. \n\n - **State Transitions**: \n - Similar to other cases, the `S_INIT` and `S_DELETE_COMPLETE` states each take **2 clock cycles**. \n - An additional 1 clock cycle is needed to transition from `S_IDLE` to `S_INIT` when the start is asserted.\n \n - **Total latency** = `1` (Start) + `1` (Initialization) + `1` (Traversal) + `2` (Deletion) + `1` (Completion) = `6 clock cycles`.\n \n- **Other Latency Scenarios**: \n - Latency to delete the smallest node in a left-skewed tree: (ARRAY_SIZE - 1) + 4;\n - Latency for an empty tree (key, left_child, right_child are invalid): 2" + } + }, + { + "id": "cvdp_agentic_jpeg_runlength_enc_0003", + "index": 626, + "source_config": "cvdp_agentic_code_generation_commercial", + "instruction": "Context: You are a language model that has the following file operations available at your disposal:\n - **List files in a directory** by running one of the following commands: \n - `ls`\n - `tree`\n - **Read files** by using:\n - `cat `\n - **Write files** by using:\n - `echo > `\n - **Compile Verilog** by using `iverilog` such as:\n - `iverilog -o .out -g2012 `\n - **Run Simulation** by using:\n - `vvp .out`\n - **Update the file content** by using:\n - `sed -i '3s/old/new/' file.txt`\n - **Find current working directory** by using:\n - `pwd`\n\n You will be given a prompt and your task is to understand it and solve the given issue by using the commands mentioned above as needed. In the final step, you should create a Linux patch highlighting the necessary file updates to achieve the targeted goal.\n\n You will solve the problem step by step using the following approach of \n - thought (thinking process of the step you're going to take)\n - action (the command you will be running to get more details/context that's helpful to solve the problem)\n - observation (the output from the action you will observe based on which you will take your next step)\n\n The last step will be the final output summary and the patch itself in the following format \n - thought (the summary of what you did and some introduction of the patch file itself)\n - patch (a Linux-based patch that needs to be applied to reach the relevant solution)\n\n The patch file should only be applied to a single file to reach the required solution.\n\nTask: Enhance the by incorporating SystemVerilog Assertions (SVA) to ensure robust verification of internal control, functional behavior in the `jpeg_runlength_enc` module. The project, located in the **rtl** directory, implements a hierarchical JPEG Run-Length Encoding scheme consisting of three interrelated modules:\n\n- **jpeg_runlength_enc** (Top\u2011Level Interface & Pipeline Integration) \n This module is the central integration block that connects the processing pipeline stages. It instantiates:\n - **jpeg_runlength_stage1** \u2013 the encoding stage responsible for:\n - Separating DC from AC coefficients.\n - Calculating run\u2011length for AC coefficients.\n - Determining coefficient size (category) and adjusting amplitude.\n - Generating the control flag (`dcterm_out`) when processing the DC term.\n - **jpeg_runlength_rzs** \u2013 the zero\u2011run suppression stage used in multiple instances (stages 2\u20135) to:\n - Detect complete zero\u2011blocks from the input signals.\n - Suppress the output enable (`den_out`) when required.\n - Propagate data through pipeline registers while ensuring signal timing and integrity.\n - Manage state transitions between zero\u2011suppression and normal operation via an internal state machine.\n \n### Assertion Requirements\n\nSVA to check that the `jpeg_runlength_enc` satisfies the following functional and safety properties:\n\n1. **Pipeline Delay Consistency** \n - In **jpeg_runlength_enc**, the `douten_out` signal must follow the assertion of `dstrb_in` after a defined pipeline delay. \n\n2. **Block Start Validity** \n - When `bstart_out` is high, the output valid signal (`douten_out`) must also be asserted, and the run\u2011length output (`rlen_out`) must equal 0, indicating a proper block start.\n\n3. **DC Marker Uniqueness** \n - Ensure that the DC marker (originating from `stage1_dc` in **jpeg_runlength_enc**) is asserted only once per block. Once the DC term is issued, it must not be repeated until a new block begins.\n\n4. **Valid Data Output Integrity** \n - Whenever `douten_out` is high, the corresponding encoded outputs (`rlen_out`, `size_out`, and `amp_out`) must carry valid data. At least one bit of `amp_out` should be set for non-DC data, and for DC terms, `rlen_out` must be 0.\n\n### Expected Behavior\n\n- The assertion properties must be placed in a separate module named `jpeg_run_length_assertion_check` in the `verif` directory, which instantiates the `jpeg_runlength_enc` module as the Device Under Test (DUT).\n- The properties must reference internal DUT signals directly for verification purposes.\n\n### Notes\n\n- All assertions must use **SystemVerilog Assertions (SVA)** syntax.\n- the new **verif** directory file (`jpeg_run_length_assertion_check.sv`) that should have these assertions implemented.", + "verilog_code": { + "code_block_1_16": "jpeg_run_length_assertion_check", + "code_block_1_19": "jpeg_run_length_assertion_check.sv", + "code_block_2_0": "module is the central integration block that connects the processing pipeline stages. It instantiates:\n - **jpeg_runlength_stage1** \u2013 the encoding stage responsible for:\n - Separating DC from AC coefficients.\n - Calculating run\u2011length for AC coefficients.\n - Determining coefficient size (category) and adjusting amplitude.\n - Generating the control flag (`dcterm_out`) when processing the DC term.\n - **jpeg_runlength_rzs** \u2013 the zero\u2011run suppression stage used in multiple instances (stages 2\u20135) to:\n - Detect complete zero\u2011blocks from the input signals.\n - Suppress the output enable (`den_out`) when required.\n - Propagate data through pipeline registers while ensuring signal timing and integrity.\n - Manage state transitions between zero\u2011suppression and normal operation via an internal state machine.\n \n### Assertion Requirements\n\nPlease implement SVA to check that the design module `jpeg_runlength_enc` satisfies the following functional and safety properties:\n\n1. **Pipeline Delay Consistency** \n - In **jpeg_runlength_enc**, the `douten_out` signal must follow the assertion of `dstrb_in` after a defined pipeline delay. \n\n2. **Block Start Validity** \n - When `bstart_out` is high, the output valid signal (`douten_out`) must also be asserted, and the run\u2011length output (`rlen_out`) must equal 0, indicating a proper block start.\n\n3. **DC Marker Uniqueness** \n - Ensure that the DC marker (originating from `stage1_dc` in **jpeg_runlength_enc**) is asserted only once per block. Once the DC term is issued, it must not be repeated until a new block begins.\n\n4. **Valid Data Output Integrity** \n - Whenever `douten_out` is high, the corresponding encoded outputs (`rlen_out`, `size_out`, and `amp_out`) must carry valid data. At least one bit of `amp_out` should be set for non-DC data, and for DC terms, `rlen_out` must be 0.\n\n### Expected Behavior\n\n- The assertion properties must be placed in a separate module named `jpeg_run_length_assertion_check` in the `verif` directory, which instantiates the `jpeg_runlength_enc` module as the Device Under Test (DUT).\n- The properties must reference internal DUT signals directly for verification purposes.\n\n### Notes\n\n- All assertions must use **SystemVerilog Assertions (SVA)** syntax.\n- Create the new **verif** directory file (`jpeg_run_length_assertion_check.sv`) that should have these assertions implemented.\n {'docs/specification.md': None, 'verif/tb_top_64b66b_codec.sv': None, 'docs/decoder_specification.md': None, 'rtl/aes_enc_top.sv': None, 'rtl/aes_encrypt.sv': None, 'rtl/sbox.sv': None, 'rtl/Bit_Difference_Counter.sv': None, 'rtl/Bitwise_Reduction.sv': None, 'rtl/Data_Reduction.sv': None, 'rtl/Min_Hamming_Distance_Finder.sv': None, 'verif/tb_Min_Hamming_Distance_Finder.sv': None, 'docs/alu_core_specification.md': None, 'rtl/alu_core.sv': None, 'verif/alu_core_tb.sv': None, 'docs/fifo.md': None, 'rtl/async_fifo.sv': None, 'rtl/fifo_memory.sv': None, 'rtl/load_memory.sv': None, 'rtl/read_to_write_pointer_sync.sv': None, 'rtl/rptr_empty.sv': None, 'rtl/wptr_full.sv': None, 'rtl/spi_complex_mult.sv': None, 'rtl/spi_master.sv': None, 'rtl/spi_top.sv': None, 'verif/spi_complex_mult_tb.sv': None, 'rtl/ttc_counter_lite.sv': None, 'verif/ttc_counter_lite_tb.sv': None, 'docs/UART_Specifications.md': None, 'rtl/areset_sync.sv': None, 'rtl/baud_gen.sv': None, 'rtl/cdc_sync.sv': None, 'rtl/uart_rx.sv': None, 'rtl/uart_tx.sv': None, 'rtl/blake2s_G.v': None, 'rtl/blake2s_core.v': None, 'rtl/blake2s_m_select.v': None, 'verif/blake2s_core_finish_and_update_sanity_check.sv': None, 'rtl/blake2s.v': None, 'verif/blake2s_not_readable_addresses_check.sv': None, 'rtl/csr_apb_interface.sv': None, 'rtl/direct_map_cache.sv': None, 'verif/tb_direct_map_cache.sv': None, 'rtl/door_lock.sv': None, 'docs/specs.md': None, 'verif/tb_branch_control_unit.sv': None, 'verif/tb_custom_byte_enable_ram.sv': None, 'rtl/custom_byte_enable_ram.sv': None, 'rtl/caesar_cipher.sv': None, 'rtl/cic_decimator.sv': None, 'verif/coffee_machine_testbench.sv': None, 'docs/continuous_adder_specification.md': None, 'rtl/continuous_adder.sv': None, 'verif/continuous_adder_tb.sv': None, 'verif/blake2s_core_state_liveness_check.sv': None, 'verif/blake2s_core_reset_and_ready_sanity_check.sv': None, 'rtl/adder_tree.sv': None, 'rtl/coeff_ram.sv': None, 'rtl/poly_filter.sv': None, 'rtl/poly_interpolator.sv': None, 'rtl/shift_register.sv': None, 'docs/poly_filter.md': None, 'rtl/rgb_color_space_hsv.sv': None, 'verif/tb_linear_search.sv': None, 'docs/simd_datapath_specs.md': None, 'docs/simd_lane_specs.md': None, 'rtl/sorting_engine.sv': None, 'verif/sorting_engine_testbench.sv': None, 'docs/order_matching_engine_specification.md': None, 'verif/order_matching_engine_testbench.sv': None, 'rtl/fixed_priority_arbiter.sv': None, 'verif/fixed_priority_arbiter_tb.sv': None, 'docs/Helmholtz_Audio_Spec.md': None, 'rtl/helmholtz_resonator.sv': None, 'rtl/modulator.sv': None, 'rtl/resonator_bank.sv': None, 'rtl/soft_clipper.sv': None, 'docs/specs_tb.md': None, 'docs/image_stego_specification.md': None, 'verif/image_stego_tb.sv': None, 'rtl/top_inv_manchester_codec.sv': None, 'rtl/jpeg_runlength_enc.sv': 'module jpeg_runlength_enc (\\n // Clock and Control Signals\\n input clk_in, // System clock (positive edge)\\n input reset_in, // Synchronous active-high reset\\n input enable_in, // Clock enable (active high)\\n input dstrb_in, // Data strobe (start of block)\\n \\n // Data Input\\n input [11:0] din_in, // 12-bit signed DCT coefficient input\\n \\n // Encoded Outputs\\n output [ 3:0] rlen_out, // Run-length (0-15 zeros)\\n output [ 3:0] size_out, // Coefficient size/category\\n output [11:0] amp_out, // Coefficient amplitude\\n output douten_out, // Data output valid\\n output bstart_out // Block start indicator\\n);\\n\\n // =========================================================================\\n // Internal Signal Declarations\\n // =========================================================================\\n \\n // Inter-stage signals (renamed with stage suffixes)\\n wire [ 3:0] stage1_rlen, stage2_rlen, stage3_rlen, stage4_rlen, stage5_rlen;\\n wire [ 3:0] stage1_size, stage2_size, stage3_size, stage4_size, stage5_size;\\n wire [11:0] stage1_amp, stage2_amp, stage3_amp, stage4_amp, stage5_amp;\\n wire stage1_den, stage2_den, stage3_den, stage4_den, stage5_den;\\n wire stage1_dc, stage2_dc, stage3_dc, stage4_dc, stage5_dc;\\n\\n // =========================================================================\\n // Processing Pipeline Stages\\n // =========================================================================\\n \\n // Stage 1: Initial Run-Length Encoding\\n jpeg_runlength_stage1 stage1_inst (\\n .clk_in (clk_in),\\n .reset_in (reset_in),\\n .enable_in (enable_in),\\n .go_in (dstrb_in),\\n .din_in (din_in),\\n .rlen_out (stage1_rlen),\\n .size_out (stage1_size),\\n .amp_out (stage1_amp),\\n .den_out (stage1_den),\\n .dcterm_out (stage1_dc)\\n );\\n\\n // Stage 2: First Zero-Run Suppression\\n jpeg_runlength_rzs stage2_inst (\\n .clk_in (clk_in),\\n .reset_in (reset_in),\\n .enable_in (enable_in),\\n .rlen_in (stage1_rlen),\\n .size_in (stage1_size),\\n .amp_in (stage1_amp),\\n .den_in (stage1_den),\\n .dc_in (stage1_dc),\\n .rlen_out (stage2_rlen),\\n .size_out (stage2_size),\\n .amp_out (stage2_amp),\\n .den_out (stage2_den),\\n .dc_out (stage2_dc)\\n );\\n\\n // Stage 3: Second Zero-Run Suppression\\n jpeg_runlength_rzs stage3_inst (\\n .clk_in (clk_in),\\n .reset_in (reset_in),\\n .enable_in (enable_in),\\n .rlen_in (stage2_rlen),\\n .size_in (stage2_size),\\n .amp_in (stage2_amp),\\n .den_in (stage2_den),\\n .dc_in (stage2_dc),\\n .rlen_out (stage3_rlen),\\n .size_out (stage3_size),\\n .amp_out (stage3_amp),\\n .den_out (stage3_den),\\n .dc_out (stage3_dc)\\n );\\n\\n // Stage 4: Third Zero-Run Suppression\\n jpeg_runlength_rzs stage4_inst (\\n .clk_in (clk_in),\\n .reset_in (reset_in),\\n .enable_in (enable_in),\\n .rlen_in (stage3_rlen),\\n .size_in (stage3_size),\\n .amp_in (stage3_amp),\\n .den_in (stage3_den),\\n .dc_in (stage3_dc),\\n .rlen_out (stage4_rlen),\\n .size_out (stage4_size),\\n .amp_out (stage4_amp),\\n .den_out (stage4_den),\\n .dc_out (stage4_dc)\\n );\\n\\n // Stage 5: Fourth Zero-Run Suppression (Final Stage)\\n jpeg_runlength_rzs stage5_inst (\\n .clk_in (clk_in),\\n .reset_in (reset_in),\\n .enable_in (enable_in),\\n .rlen_in (stage4_rlen),\\n .size_in (stage4_size),\\n .amp_in (stage4_amp),\\n .den_in (stage4_den),\\n .dc_in (stage4_dc),\\n .rlen_out (stage5_rlen),\\n .size_out (stage5_size),\\n .amp_out (stage5_amp),\\n .den_out (stage5_den),\\n .dc_out (stage5_dc)\\n );\\n\\n // =========================================================================\\n // Output Assignments\\n // =========================================================================\\n assign rlen_out = stage5_rlen;\\n assign size_out = stage5_size;\\n assign amp_out = stage5_amp;\\n assign douten_out = stage5_den;\\n assign bstart_out = stage5_dc;\\n\\nendmodule', 'rtl/jpeg_runlength_rzs.sv': \"module jpeg_runlength_rzs (\\n // Clock and Control Signals\\n input clk_in, // System clock (positive edge)\\n input enable_in, // Clock enable (active high)\\n input reset_in, // Synchronous active-high reset\\n \\n // Input Data Bus\\n input den_in, // Data input valid\\n input dc_in, // DC coefficient indicator\\n input [ 3:0] rlen_in, // Run-length input (0-15)\\n input [ 3:0] size_in, // Coefficient size/category\\n input [11:0] amp_in, // Coefficient amplitude\\n \\n // Output Data Bus\\n output reg den_out, // Data output valid\\n output reg dc_out, // DC coefficient output indicator\\n output reg [ 3:0] rlen_out, // Run-length output\\n output reg [ 3:0] size_out, // Size/category output\\n output reg [11:0] amp_out // Amplitude output\\n);\\n\\n // =========================================================================\\n // Internal Registers and Signals\\n // =========================================================================\\n \\n // Pipeline registers for output data\\n reg [ 3:0] size;\\n reg [ 3:0] rlen;\\n reg [11:0] amp;\\n reg den;\\n reg dc;\\n \\n // Control signals\\n wire eob; // End-of-Block detection\\n wire zerobl; // Zero-block detection\\n reg state; // State machine state (0=normal, 1=zero-block)\\n\\n // =========================================================================\\n // Data Pipeline Registers\\n // =========================================================================\\n \\n // Input data pipeline stage\\n always @(posedge clk_in or posedge reset_in)\\n if (reset_in) begin\\n size <= 4'b0;\\n rlen <= 4'b0;\\n amp <= 12'b0;\\n end else if (enable_in & den_in) begin\\n size <= size_in;\\n rlen <= rlen_in;\\n amp <= amp_in;\\n end\\n \\n // Output data pipeline stage\\n always @(posedge clk_in or posedge reset_in)\\n if (reset_in) begin\\n size_out <= 4'b0;\\n rlen_out <= 4'b0;\\n amp_out <= 12'b0;\\n dc <= 1'b0;\\n dc_out <= 1'b0;\\n end else if (enable_in) begin\\n size_out <= size;\\n rlen_out <= rlen;\\n amp_out <= amp;\\n dc <= dc_in;\\n dc_out <= dc;\\n end\\n\\n // =========================================================================\\n // Control Signal Generation\\n // =========================================================================\\n \\n // Zero-block detection: run-length=15 and size=0 with valid data\\n assign zerobl = &rlen_in & ~|size_in & den_in;\\n \\n // End-of-Block detection: run-length=0 and size=0 with valid AC data\\n assign eob = ~|{rlen_in, size_in} & den_in & ~dc_in;\\n\\n // =========================================================================\\n // Zero-Suppression State Machine\\n // =========================================================================\\n always @(posedge clk_in or posedge reset_in)\\n if (reset_in) begin\\n state <= 1'b0; // Start in normal state\\n den <= 1'b0;\\n den_out <= 1'b0;\\n end else if (enable_in)\\n case (state)\\n // Normal Processing State\\n 1'b0: begin\\n if (zerobl) begin\\n // Detected zero-block, transition to suppression state\\n state <= 1'b1;\\n den <= 1'b0; // Suppress output\\n den_out <= den; // Output previous data\\n end else begin\\n // Continue normal processing\\n state <= 1'b0;\\n den <= den_in; // Pass through data enable\\n den_out <= den; // Output previous data\\n end\\n end\\n \\n // Zero-Block Suppression State\\n 1'b1: begin\\n den_out <= 1'b0; // Default to suppressed output\\n \\n if (den_in) begin // Only act when input valid\\n if (zerobl) begin\\n // Another zero-block detected\\n state <= 1'b1; // Stay in suppression state\\n den <= 1'b0; // Continue suppression\\n den_out <= 1'b1; // Output previous zero-block\\n end else if (eob) begin\\n // EOB marker detected\\n state <= 1'b0; // Return to normal state\\n den <= 1'b1; // Enable EOB output\\n den_out <= 1'b0; // Explicitly zero\\n end else begin\\n // Non-zero data detected\\n state <= 1'b0; // Return to normal state\\n den <= 1'b1; // Enable data output\\n den_out <= 1'b1; // Output zero-block\\n end\\n end\\n end\\n endcase\\n\\nendmodule\", 'rtl/jpeg_runlength_stage1.sv': \"module jpeg_runlength_stage1 (\\n // Clock and reset\\n input clk_in, // System clock (positive edge triggered)\\n input reset_in, // Synchronous active-high reset\\n \\n // Control signals\\n input enable_in, // Clock enable (active high)\\n input go_in, // Start new block (pulse high for 1 cycle)\\n \\n // Data input\\n input [11:0] din_in, // 12-bit DCT coefficient input\\n \\n // Encoded outputs\\n output reg [ 3:0] rlen_out, // Run-length (0-15 zeros before this coefficient)\\n output reg [ 3:0] size_out, // Category (bit size needed for coefficient)\\n output reg [11:0] amp_out, // Amplitude (modified coefficient value)\\n output reg den_out, // Data valid output (active high)\\n output reg dcterm_out // Indicates DC term output (active high)\\n);\\n\\n // =========================================================================\\n // Internal Signals and State\\n // =========================================================================\\n \\n // Sample counter (0-63 for 8x8 block)\\n reg [5:0] sample_cnt;\\n \\n // Zero run-length counter (counts consecutive zeros)\\n reg [3:0] zero_cnt;\\n \\n // Zero detection signal (high when input is zero)\\n wire is_zero = ~|din_in;\\n \\n // State machine states\\n reg state;\\n parameter dc = 1'b0; // Processing DC coefficient (first in block)\\n parameter ac = 1'b1; // Processing AC coefficients\\n\\n // =========================================================================\\n // Helper Functions\\n // =========================================================================\\n \\n /**\\n * Absolute Value Function\\n * Returns absolute value of 12-bit signed input\\n */\\n function [10:0] abs;\\n input [11:0] a;\\n begin\\n abs = a[11] ? (~a[10:0] + 11'h1) : a[10:0]; // 2's complement conversion\\n end\\n endfunction\\n\\n /**\\n * Category (Bit Size) Calculation\\n * Determines the number of bits needed to represent the coefficient\\n * Returns value 0-11 (0 means zero coefficient, special case for DC)\\n */\\n function [3:0] cat;\\n input [11:0] a;\\n reg [10:0] tmp;\\n begin\\n tmp = abs(a); // Get absolute value first\\n \\n // Priority encoder style category detection\\n casex(tmp) // synopsys full_case parallel_case\\n 11'b1??_????_???? : cat = 4'hb; // 1024..2047 (11 bits)\\n 11'b01?_????_???? : cat = 4'ha; // 512..1023 (10 bits)\\n 11'b001_????_???? : cat = 4'h9; // 256.. 511 (9 bits)\\n 11'b000_1???_???? : cat = 4'h8; // 128.. 255 (8 bits)\\n 11'b000_01??_???? : cat = 4'h7; // 64.. 127 (7 bits)\\n 11'b000_001?_???? : cat = 4'h6; // 32.. 63 (6 bits)\\n 11'b000_0001_???? : cat = 4'h5; // 16.. 31 (5 bits)\\n 11'b000_0000_1??? : cat = 4'h4; // 8.. 15 (4 bits)\\n 11'b000_0000_01?? : cat = 4'h3; // 4.. 7 (3 bits)\\n 11'b000_0000_001? : cat = 4'h2; // 2.. 3 (2 bits)\\n 11'b000_0000_0001 : cat = 4'h1; // 1 (1 bit)\\n 11'b000_0000_0000 : cat = 4'h0; // 0 (special case)\\n endcase\\n end\\n endfunction\\n\\n /**\\n * Amplitude Modification Function\\n * Adjusts coefficient value for more efficient encoding\\n */\\n function [10:0] rem;\\n input [11:0] a;\\n reg [10:0] tmp_rem;\\n begin\\n // For negative numbers: rem = -a - 1\\n // For positive numbers: rem = a\\n tmp_rem = a[11] ? (a[10:0] - 10'h1) : a[10:0];\\n rem = tmp_rem;\\n end\\n endfunction\\n\\n // =========================================================================\\n // Main Processing Logic\\n // =========================================================================\\n\\n // Amplitude output register\\n always @(posedge clk_in or posedge reset_in)\\n if (reset_in)\\n amp_out <= 12'b0;\\n else if (enable_in)\\n amp_out <= {din_in[11], rem(din_in)}; // Preserve sign bit\\n\\n // Sample counter (0-63 for 8x8 block)\\n always @(posedge clk_in or posedge reset_in)\\n if (reset_in)\\n sample_cnt <= 6'b0;\\n else if (enable_in)\\n if (go_in) // Start new block\\n sample_cnt <= 1; // Skip DC position (handled separately)\\n else if (|sample_cnt) // Only increment if not zero\\n sample_cnt <= sample_cnt + 1;\\n\\n // Zero run-length counter\\n always @(posedge clk_in or posedge reset_in)\\n if (reset_in)\\n zero_cnt <= 4'b0;\\n else if (enable_in)\\n if (is_zero)\\n zero_cnt <= zero_cnt + 1; // Increment for zero coefficients\\n else\\n zero_cnt <= 0; // Reset for non-zero coefficients\\n\\n // =========================================================================\\n // State Machine - Controls Output Encoding\\n // =========================================================================\\n always @(posedge clk_in or posedge reset_in)\\n if (reset_in) begin\\n state <= dc;\\n rlen_out <= 0;\\n size_out <= 0;\\n den_out <= 1'b0;\\n dcterm_out <= 1'b0;\\n end else if (enable_in)\\n case (state)\\n // DC Coefficient Processing State\\n dc: begin\\n rlen_out <= 0; // DC has no run-length\\n size_out <= cat(din_in); // Get DC coefficient size\\n \\n if (go_in) begin\\n // Start processing AC coefficients\\n state <= ac;\\n den_out <= 1'b1; // Output valid\\n dcterm_out <= 1'b1; // Mark as DC term\\n end else begin\\n // Stay in DC state\\n state <= dc;\\n den_out <= 1'b0; // No output\\n dcterm_out <= 1'b0;\\n end\\n end\\n \\n // AC Coefficient Processing State\\n ac: begin\\n if (&sample_cnt) begin\\n // End of block processing\\n state <= dc; // Return to DC state\\n \\n if (is_zero) begin\\n // End-of-block marker\\n rlen_out <= 0;\\n size_out <= 0;\\n den_out <= 1'b1;\\n dcterm_out <= 1'b0;\\n end else begin\\n // Last coefficient in block\\n rlen_out <= zero_cnt;\\n size_out <= cat(din_in);\\n den_out <= 1'b1;\\n dcterm_out <= 1'b0;\\n end\\n end else begin\\n // Normal AC coefficient processing\\n state <= ac;\\n rlen_out <= zero_cnt;\\n dcterm_out <= 1'b0;\\n \\n // Handle zero vs non-zero coefficients\\n size_out <= is_zero ? 0 : cat(din_in);\\n den_out <= is_zero ? &zero_cnt : 1'b1; // Only output after 15 zeros\\n end\\n end\\n endcase\\nendmodule\", 'docs/8Bit_lfsr_spec.md': None, 'rtl/memory_scheduler.sv': None, 'docs/multiplexer_specification.md': None, 'rtl/multiplexer.sv': None, 'verif/multiplexer_tb.sv': None, 'docs/nbit_swizzling_spec.md': None, 'verif/nbit_swizzling_tb.sv': None, 'docs/nmea_decoder_spec.md': None, 'verif/nmea_decoder_tb.sv': None, 'rtl/axi4lite_to_pcie_cfg_bridge.sv': None, 'rtl/axis_to_uart_tx.sv': None, 'rtl/uart_rx_to_axis.sv': None, 'rtl/axis_to_uart.sv': None, 'rtl/barrel_shifter.sv': None, 'verif/barrel_shifter_tb.sv': None, 'docs/bcd_adder_spec.md': None, 'verif/tb_bcd_adder.sv': None, 'rtl/bcd_adder.sv': None, 'rtl/bcd_top.sv': None, 'rtl/multi_digit_bcd_add_sub.sv': None, 'rtl/full_adder.sv': None, 'rtl/four_bit_adder.sv': None, 'verif/bcd_to_excess_3_tb.sv': None, 'docs/deletion_specification.md': None}", + "rtl/jpeg_runlength_enc.sv": "module jpeg_runlength_enc (\n // Clock and Control Signals\n input clk_in, // System clock (positive edge)\n input reset_in, // Synchronous active-high reset\n input enable_in, // Clock enable (active high)\n input dstrb_in, // Data strobe (start of block)\n \n // Data Input\n input [11:0] din_in, // 12-bit signed DCT coefficient input\n \n // Encoded Outputs\n output [ 3:0] rlen_out, // Run-length (0-15 zeros)\n output [ 3:0] size_out, // Coefficient size/category\n output [11:0] amp_out, // Coefficient amplitude\n output douten_out, // Data output valid\n output bstart_out // Block start indicator\n);\n\n // =========================================================================\n // Internal Signal Declarations\n // =========================================================================\n \n // Inter-stage signals (renamed with stage suffixes)\n wire [ 3:0] stage1_rlen, stage2_rlen, stage3_rlen, stage4_rlen, stage5_rlen;\n wire [ 3:0] stage1_size, stage2_size, stage3_size, stage4_size, stage5_size;\n wire [11:0] stage1_amp, stage2_amp, stage3_amp, stage4_amp, stage5_amp;\n wire stage1_den, stage2_den, stage3_den, stage4_den, stage5_den;\n wire stage1_dc, stage2_dc, stage3_dc, stage4_dc, stage5_dc;\n\n // =========================================================================\n // Processing Pipeline Stages\n // =========================================================================\n \n // Stage 1: Initial Run-Length Encoding\n jpeg_runlength_stage1 stage1_inst (\n .clk_in (clk_in),\n .reset_in (reset_in),\n .enable_in (enable_in),\n .go_in (dstrb_in),\n .din_in (din_in),\n .rlen_out (stage1_rlen),\n .size_out (stage1_size),\n .amp_out (stage1_amp),\n .den_out (stage1_den),\n .dcterm_out (stage1_dc)\n );\n\n // Stage 2: First Zero-Run Suppression\n jpeg_runlength_rzs stage2_inst (\n .clk_in (clk_in),\n .reset_in (reset_in),\n .enable_in (enable_in),\n .rlen_in (stage1_rlen),\n .size_in (stage1_size),\n .amp_in (stage1_amp),\n .den_in (stage1_den),\n .dc_in (stage1_dc),\n .rlen_out (stage2_rlen),\n .size_out (stage2_size),\n .amp_out (stage2_amp),\n .den_out (stage2_den),\n .dc_out (stage2_dc)\n );\n\n // Stage 3: Second Zero-Run Suppression\n jpeg_runlength_rzs stage3_inst (\n .clk_in (clk_in),\n .reset_in (reset_in),\n .enable_in (enable_in),\n .rlen_in (stage2_rlen),\n .size_in (stage2_size),\n .amp_in (stage2_amp),\n .den_in (stage2_den),\n .dc_in (stage2_dc),\n .rlen_out (stage3_rlen),\n .size_out (stage3_size),\n .amp_out (stage3_amp),\n .den_out (stage3_den),\n .dc_out (stage3_dc)\n );\n\n // Stage 4: Third Zero-Run Suppression\n jpeg_runlength_rzs stage4_inst (\n .clk_in (clk_in),\n .reset_in (reset_in),\n .enable_in (enable_in),\n .rlen_in (stage3_rlen),\n .size_in (stage3_size),\n .amp_in (stage3_amp),\n .den_in (stage3_den),\n .dc_in (stage3_dc),\n .rlen_out (stage4_rlen),\n .size_out (stage4_size),\n .amp_out (stage4_amp),\n .den_out (stage4_den),\n .dc_out (stage4_dc)\n );\n\n // Stage 5: Fourth Zero-Run Suppression (Final Stage)\n jpeg_runlength_rzs stage5_inst (\n .clk_in (clk_in),\n .reset_in (reset_in),\n .enable_in (enable_in),\n .rlen_in (stage4_rlen),\n .size_in (stage4_size),\n .amp_in (stage4_amp),\n .den_in (stage4_den),\n .dc_in (stage4_dc),\n .rlen_out (stage5_rlen),\n .size_out (stage5_size),\n .amp_out (stage5_amp),\n .den_out (stage5_den),\n .dc_out (stage5_dc)\n );\n\n // =========================================================================\n // Output Assignments\n // =========================================================================\n assign rlen_out = stage5_rlen;\n assign size_out = stage5_size;\n assign amp_out = stage5_amp;\n assign douten_out = stage5_den;\n assign bstart_out = stage5_dc;\n\nendmodule", + "rtl/jpeg_runlength_rzs.sv": "module jpeg_runlength_rzs (\n // Clock and Control Signals\n input clk_in, // System clock (positive edge)\n input enable_in, // Clock enable (active high)\n input reset_in, // Synchronous active-high reset\n \n // Input Data Bus\n input den_in, // Data input valid\n input dc_in, // DC coefficient indicator\n input [ 3:0] rlen_in, // Run-length input (0-15)\n input [ 3:0] size_in, // Coefficient size/category\n input [11:0] amp_in, // Coefficient amplitude\n \n // Output Data Bus\n output reg den_out, // Data output valid\n output reg dc_out, // DC coefficient output indicator\n output reg [ 3:0] rlen_out, // Run-length output\n output reg [ 3:0] size_out, // Size/category output\n output reg [11:0] amp_out // Amplitude output\n);\n\n // =========================================================================\n // Internal Registers and Signals\n // =========================================================================\n \n // Pipeline registers for output data\n reg [ 3:0] size;\n reg [ 3:0] rlen;\n reg [11:0] amp;\n reg den;\n reg dc;\n \n // Control signals\n wire eob; // End-of-Block detection\n wire zerobl; // Zero-block detection\n reg state; // State machine state (0=normal, 1=zero-block)\n\n // =========================================================================\n // Data Pipeline Registers\n // =========================================================================\n \n // Input data pipeline stage\n always @(posedge clk_in or posedge reset_in)\n if (reset_in) begin\n size <= 4'b0;\n rlen <= 4'b0;\n amp <= 12'b0;\n end else if (enable_in & den_in) begin\n size <= size_in;\n rlen <= rlen_in;\n amp <= amp_in;\n end\n \n // Output data pipeline stage\n always @(posedge clk_in or posedge reset_in)\n if (reset_in) begin\n size_out <= 4'b0;\n rlen_out <= 4'b0;\n amp_out <= 12'b0;\n dc <= 1'b0;\n dc_out <= 1'b0;\n end else if (enable_in) begin\n size_out <= size;\n rlen_out <= rlen;\n amp_out <= amp;\n dc <= dc_in;\n dc_out <= dc;\n end\n\n // =========================================================================\n // Control Signal Generation\n // =========================================================================\n \n // Zero-block detection: run-length=15 and size=0 with valid data\n assign zerobl = &rlen_in & ~|size_in & den_in;\n \n // End-of-Block detection: run-length=0 and size=0 with valid AC data\n assign eob = ~|{rlen_in, size_in} & den_in & ~dc_in;\n\n // =========================================================================\n // Zero-Suppression State Machine\n // =========================================================================\n always @(posedge clk_in or posedge reset_in)\n if (reset_in) begin\n state <= 1'b0; // Start in normal state\n den <= 1'b0;\n den_out <= 1'b0;\n end else if (enable_in)\n case (state)\n // Normal Processing State\n 1'b0: begin\n if (zerobl) begin\n // Detected zero-block, transition to suppression state\n state <= 1'b1;\n den <= 1'b0; // Suppress output\n den_out <= den; // Output previous data\n end else begin\n // Continue normal processing\n state <= 1'b0;\n den <= den_in; // Pass through data enable\n den_out <= den; // Output previous data\n end\n end\n \n // Zero-Block Suppression State\n 1'b1: begin\n den_out <= 1'b0; // Default to suppressed output\n \n if (den_in) begin // Only act when input valid\n if (zerobl) begin\n // Another zero-block detected\n state <= 1'b1; // Stay in suppression state\n den <= 1'b0; // Continue suppression\n den_out <= 1'b1; // Output previous zero-block\n end else if (eob) begin\n // EOB marker detected\n state <= 1'b0; // Return to normal state\n den <= 1'b1; // Enable EOB output\n den_out <= 1'b0; // Explicitly zero\n end else begin\n // Non-zero data detected\n state <= 1'b0; // Return to normal state\n den <= 1'b1; // Enable data output\n den_out <= 1'b1; // Output zero-block\n end\n end\n end\n endcase\n\nendmodule", + "rtl/jpeg_runlength_stage1.sv": "module jpeg_runlength_stage1 (\n // Clock and reset\n input clk_in, // System clock (positive edge triggered)\n input reset_in, // Synchronous active-high reset\n \n // Control signals\n input enable_in, // Clock enable (active high)\n input go_in, // Start new block (pulse high for 1 cycle)\n \n // Data input\n input [11:0] din_in, // 12-bit DCT coefficient input\n \n // Encoded outputs\n output reg [ 3:0] rlen_out, // Run-length (0-15 zeros before this coefficient)\n output reg [ 3:0] size_out, // Category (bit size needed for coefficient)\n output reg [11:0] amp_out, // Amplitude (modified coefficient value)\n output reg den_out, // Data valid output (active high)\n output reg dcterm_out // Indicates DC term output (active high)\n);\n\n // =========================================================================\n // Internal Signals and State\n // =========================================================================\n \n // Sample counter (0-63 for 8x8 block)\n reg [5:0] sample_cnt;\n \n // Zero run-length counter (counts consecutive zeros)\n reg [3:0] zero_cnt;\n \n // Zero detection signal (high when input is zero)\n wire is_zero = ~|din_in;\n \n // State machine states\n reg state;\n parameter dc = 1'b0; // Processing DC coefficient (first in block)\n parameter ac = 1'b1; // Processing AC coefficients\n\n // =========================================================================\n // Helper Functions\n // =========================================================================\n \n /**\n * Absolute Value Function\n * Returns absolute value of 12-bit signed input\n */\n function [10:0] abs;\n input [11:0] a;\n begin\n abs = a[11] ? (~a[10:0] + 11'h1) : a[10:0]; // 2's complement conversion\n end\n endfunction\n\n /**\n * Category (Bit Size) Calculation\n * Determines the number of bits needed to represent the coefficient\n * Returns value 0-11 (0 means zero coefficient, special case for DC)\n */\n function [3:0] cat;\n input [11:0] a;\n reg [10:0] tmp;\n begin\n tmp = abs(a); // Get absolute value first\n \n // Priority encoder style category detection\n casex(tmp) // synopsys full_case parallel_case\n 11'b1??_????_???? : cat = 4'hb; // 1024..2047 (11 bits)\n 11'b01?_????_???? : cat = 4'ha; // 512..1023 (10 bits)\n 11'b001_????_???? : cat = 4'h9; // 256.. 511 (9 bits)\n 11'b000_1???_???? : cat = 4'h8; // 128.. 255 (8 bits)\n 11'b000_01??_???? : cat = 4'h7; // 64.. 127 (7 bits)\n 11'b000_001?_???? : cat = 4'h6; // 32.. 63 (6 bits)\n 11'b000_0001_???? : cat = 4'h5; // 16.. 31 (5 bits)\n 11'b000_0000_1??? : cat = 4'h4; // 8.. 15 (4 bits)\n 11'b000_0000_01?? : cat = 4'h3; // 4.. 7 (3 bits)\n 11'b000_0000_001? : cat = 4'h2; // 2.. 3 (2 bits)\n 11'b000_0000_0001 : cat = 4'h1; // 1 (1 bit)\n 11'b000_0000_0000 : cat = 4'h0; // 0 (special case)\n endcase\n end\n endfunction\n\n /**\n * Amplitude Modification Function\n * Adjusts coefficient value for more efficient encoding\n */\n function [10:0] rem;\n input [11:0] a;\n reg [10:0] tmp_rem;\n begin\n // For negative numbers: rem = -a - 1\n // For positive numbers: rem = a\n tmp_rem = a[11] ? (a[10:0] - 10'h1) : a[10:0];\n rem = tmp_rem;\n end\n endfunction\n\n // =========================================================================\n // Main Processing Logic\n // =========================================================================\n\n // Amplitude output register\n always @(posedge clk_in or posedge reset_in)\n if (reset_in)\n amp_out <= 12'b0;\n else if (enable_in)\n amp_out <= {din_in[11], rem(din_in)}; // Preserve sign bit\n\n // Sample counter (0-63 for 8x8 block)\n always @(posedge clk_in or posedge reset_in)\n if (reset_in)\n sample_cnt <= 6'b0;\n else if (enable_in)\n if (go_in) // Start new block\n sample_cnt <= 1; // Skip DC position (handled separately)\n else if (|sample_cnt) // Only increment if not zero\n sample_cnt <= sample_cnt + 1;\n\n // Zero run-length counter\n always @(posedge clk_in or posedge reset_in)\n if (reset_in)\n zero_cnt <= 4'b0;\n else if (enable_in)\n if (is_zero)\n zero_cnt <= zero_cnt + 1; // Increment for zero coefficients\n else\n zero_cnt <= 0; // Reset for non-zero coefficients\n\n // =========================================================================\n // State Machine - Controls Output Encoding\n // =========================================================================\n always @(posedge clk_in or posedge reset_in)\n if (reset_in) begin\n state <= dc;\n rlen_out <= 0;\n size_out <= 0;\n den_out <= 1'b0;\n dcterm_out <= 1'b0;\n end else if (enable_in)\n case (state)\n // DC Coefficient Processing State\n dc: begin\n rlen_out <= 0; // DC has no run-length\n size_out <= cat(din_in); // Get DC coefficient size\n \n if (go_in) begin\n // Start processing AC coefficients\n state <= ac;\n den_out <= 1'b1; // Output valid\n dcterm_out <= 1'b1; // Mark as DC term\n end else begin\n // Stay in DC state\n state <= dc;\n den_out <= 1'b0; // No output\n dcterm_out <= 1'b0;\n end\n end\n \n // AC Coefficient Processing State\n ac: begin\n if (&sample_cnt) begin\n // End of block processing\n state <= dc; // Return to DC state\n \n if (is_zero) begin\n // End-of-block marker\n rlen_out <= 0;\n size_out <= 0;\n den_out <= 1'b1;\n dcterm_out <= 1'b0;\n end else begin\n // Last coefficient in block\n rlen_out <= zero_cnt;\n size_out <= cat(din_in);\n den_out <= 1'b1;\n dcterm_out <= 1'b0;\n end\n end else begin\n // Normal AC coefficient processing\n state <= ac;\n rlen_out <= zero_cnt;\n dcterm_out <= 1'b0;\n \n // Handle zero vs non-zero coefficients\n size_out <= is_zero ? 0 : cat(din_in);\n den_out <= is_zero ? &zero_cnt : 1'b1; // Only output after 15 zeros\n end\n end\n endcase\nendmodule" + }, + "test_info": { + "test_criteria_0": [ + "(dut).\n- the properties must reference internal dut signals directly for verification purposes." + ], + "test_criteria_2": [ + "be set for non-dc data, and for dc terms, `rlen_out` must be 0.", + "have these assertions implemented." + ], + "test_criteria_3": [ + "- the assertion properties must be placed in a separate module named `jpeg_run_length_assertion_check` in the `verif` directory, which instantiates the `jpeg_runlength_enc` module as the device under test (dut).\n- the properties must reference internal dut signals directly for verification purposes." + ] + }, + "expected_behavior": [ + "follow the assertion of `dstrb_in` after a defined pipeline delay", + "also be asserted, and the run\u2011length output (`rlen_out`) must equal 0, indicating a proper block start", + "not be repeated until a new block begins", + "carry valid data", + "be set for non-DC data, and for DC terms, `rlen_out` must be 0", + "be placed in a separate module named `jpeg_run_length_assertion_check` in the `verif` directory, which instantiates the `jpeg_runlength_enc` module as the Device Under Test (DUT)", + "reference internal DUT signals directly for verification purposes", + "use **SystemVerilog Assertions (SVA)** syntax", + "have these assertions implemented", + "in the `jpeg_runlength_enc` module. The project, located in the **rtl** directory, implements a hierarchical JPEG Run-Length Encoding scheme consisting of three interrelated modules:" + ], + "metadata": { + "categories": [ + "cid014", + "hard" + ], + "domain": "control", + "complexity": "expert", + "problem_type": "design", + "has_code": true, + "has_tests": true + }, + "full_prompt": "Enhance the design by incorporating SystemVerilog Assertions (SVA) to ensure robust verification of internal control, functional behavior in the `jpeg_runlength_enc` module. The project, located in the **rtl** directory, implements a hierarchical JPEG Run-Length Encoding scheme consisting of three interrelated modules:\n\n- **jpeg_runlength_enc** (Top\u2011Level Interface & Pipeline Integration) \n This module is the central integration block that connects the processing pipeline stages. It instantiates:\n - **jpeg_runlength_stage1** \u2013 the encoding stage responsible for:\n - Separating DC from AC coefficients.\n - Calculating run\u2011length for AC coefficients.\n - Determining coefficient size (category) and adjusting amplitude.\n - Generating the control flag (`dcterm_out`) when processing the DC term.\n - **jpeg_runlength_rzs** \u2013 the zero\u2011run suppression stage used in multiple instances (stages 2\u20135) to:\n - Detect complete zero\u2011blocks from the input signals.\n - Suppress the output enable (`den_out`) when required.\n - Propagate data through pipeline registers while ensuring signal timing and integrity.\n - Manage state transitions between zero\u2011suppression and normal operation via an internal state machine.\n \n### Assertion Requirements\n\nPlease implement SVA to check that the design module `jpeg_runlength_enc` satisfies the following functional and safety properties:\n\n1. **Pipeline Delay Consistency** \n - In **jpeg_runlength_enc**, the `douten_out` signal must follow the assertion of `dstrb_in` after a defined pipeline delay. \n\n2. **Block Start Validity** \n - When `bstart_out` is high, the output valid signal (`douten_out`) must also be asserted, and the run\u2011length output (`rlen_out`) must equal 0, indicating a proper block start.\n\n3. **DC Marker Uniqueness** \n - Ensure that the DC marker (originating from `stage1_dc` in **jpeg_runlength_enc**) is asserted only once per block. Once the DC term is issued, it must not be repeated until a new block begins.\n\n4. **Valid Data Output Integrity** \n - Whenever `douten_out` is high, the corresponding encoded outputs (`rlen_out`, `size_out`, and `amp_out`) must carry valid data. At least one bit of `amp_out` should be set for non-DC data, and for DC terms, `rlen_out` must be 0.\n\n### Expected Behavior\n\n- The assertion properties must be placed in a separate module named `jpeg_run_length_assertion_check` in the `verif` directory, which instantiates the `jpeg_runlength_enc` module as the Device Under Test (DUT).\n- The properties must reference internal DUT signals directly for verification purposes.\n\n### Notes\n\n- All assertions must use **SystemVerilog Assertions (SVA)** syntax.\n- Create the new **verif** directory file (`jpeg_run_length_assertion_check.sv`) that should have these assertions implemented.\n", + "system_message": "You are a language model that has the following file operations available at your disposal:\n - **List files in a directory** by running one of the following commands: \n - `ls`\n - `tree`\n - **Read files** by using:\n - `cat `\n - **Write files** by using:\n - `echo > `\n - **Compile Verilog** by using `iverilog` such as:\n - `iverilog -o .out -g2012 `\n - **Run Simulation** by using:\n - `vvp .out`\n - **Update the file content** by using:\n - `sed -i '3s/old/new/' file.txt`\n - **Find current working directory** by using:\n - `pwd`\n\n You will be given a prompt and your task is to understand it and solve the given issue by using the commands mentioned above as needed. In the final step, you should create a Linux patch highlighting the necessary file updates to achieve the targeted goal.\n\n You will solve the problem step by step using the following approach of \n - thought (thinking process of the step you're going to take)\n - action (the command you will be running to get more details/context that's helpful to solve the problem)\n - observation (the output from the action you will observe based on which you will take your next step)\n\n The last step will be the final output summary and the patch itself in the following format \n - thought (the summary of what you did and some introduction of the patch file itself)\n - patch (a Linux-based patch that needs to be applied to reach the relevant solution)\n\n The patch file should only be applied to a single file to reach the required solution.", + "raw_context": { + "docs/specification.md": null, + "verif/tb_top_64b66b_codec.sv": null, + "docs/decoder_specification.md": null, + "rtl/aes_enc_top.sv": null, + "rtl/aes_encrypt.sv": null, + "rtl/sbox.sv": null, + "rtl/Bit_Difference_Counter.sv": null, + "rtl/Bitwise_Reduction.sv": null, + "rtl/Data_Reduction.sv": null, + "rtl/Min_Hamming_Distance_Finder.sv": null, + "verif/tb_Min_Hamming_Distance_Finder.sv": null, + "docs/alu_core_specification.md": null, + "rtl/alu_core.sv": null, + "verif/alu_core_tb.sv": null, + "docs/fifo.md": null, + "rtl/async_fifo.sv": null, + "rtl/fifo_memory.sv": null, + "rtl/load_memory.sv": null, + "rtl/read_to_write_pointer_sync.sv": null, + "rtl/rptr_empty.sv": null, + "rtl/wptr_full.sv": null, + "rtl/spi_complex_mult.sv": null, + "rtl/spi_master.sv": null, + "rtl/spi_top.sv": null, + "verif/spi_complex_mult_tb.sv": null, + "rtl/ttc_counter_lite.sv": null, + "verif/ttc_counter_lite_tb.sv": null, + "docs/UART_Specifications.md": null, + "rtl/areset_sync.sv": null, + "rtl/baud_gen.sv": null, + "rtl/cdc_sync.sv": null, + "rtl/uart_rx.sv": null, + "rtl/uart_tx.sv": null, + "rtl/blake2s_G.v": null, + "rtl/blake2s_core.v": null, + "rtl/blake2s_m_select.v": null, + "verif/blake2s_core_finish_and_update_sanity_check.sv": null, + "rtl/blake2s.v": null, + "verif/blake2s_not_readable_addresses_check.sv": null, + "rtl/csr_apb_interface.sv": null, + "rtl/direct_map_cache.sv": null, + "verif/tb_direct_map_cache.sv": null, + "rtl/door_lock.sv": null, + "docs/specs.md": null, + "verif/tb_branch_control_unit.sv": null, + "verif/tb_custom_byte_enable_ram.sv": null, + "rtl/custom_byte_enable_ram.sv": null, + "rtl/caesar_cipher.sv": null, + "rtl/cic_decimator.sv": null, + "verif/coffee_machine_testbench.sv": null, + "docs/continuous_adder_specification.md": null, + "rtl/continuous_adder.sv": null, + "verif/continuous_adder_tb.sv": null, + "verif/blake2s_core_state_liveness_check.sv": null, + "verif/blake2s_core_reset_and_ready_sanity_check.sv": null, + "rtl/adder_tree.sv": null, + "rtl/coeff_ram.sv": null, + "rtl/poly_filter.sv": null, + "rtl/poly_interpolator.sv": null, + "rtl/shift_register.sv": null, + "docs/poly_filter.md": null, + "rtl/rgb_color_space_hsv.sv": null, + "verif/tb_linear_search.sv": null, + "docs/simd_datapath_specs.md": null, + "docs/simd_lane_specs.md": null, + "rtl/sorting_engine.sv": null, + "verif/sorting_engine_testbench.sv": null, + "docs/order_matching_engine_specification.md": null, + "verif/order_matching_engine_testbench.sv": null, + "rtl/fixed_priority_arbiter.sv": null, + "verif/fixed_priority_arbiter_tb.sv": null, + "docs/Helmholtz_Audio_Spec.md": null, + "rtl/helmholtz_resonator.sv": null, + "rtl/modulator.sv": null, + "rtl/resonator_bank.sv": null, + "rtl/soft_clipper.sv": null, + "docs/specs_tb.md": null, + "docs/image_stego_specification.md": null, + "verif/image_stego_tb.sv": null, + "rtl/top_inv_manchester_codec.sv": null, + "rtl/jpeg_runlength_enc.sv": "module jpeg_runlength_enc (\n // Clock and Control Signals\n input clk_in, // System clock (positive edge)\n input reset_in, // Synchronous active-high reset\n input enable_in, // Clock enable (active high)\n input dstrb_in, // Data strobe (start of block)\n \n // Data Input\n input [11:0] din_in, // 12-bit signed DCT coefficient input\n \n // Encoded Outputs\n output [ 3:0] rlen_out, // Run-length (0-15 zeros)\n output [ 3:0] size_out, // Coefficient size/category\n output [11:0] amp_out, // Coefficient amplitude\n output douten_out, // Data output valid\n output bstart_out // Block start indicator\n);\n\n // =========================================================================\n // Internal Signal Declarations\n // =========================================================================\n \n // Inter-stage signals (renamed with stage suffixes)\n wire [ 3:0] stage1_rlen, stage2_rlen, stage3_rlen, stage4_rlen, stage5_rlen;\n wire [ 3:0] stage1_size, stage2_size, stage3_size, stage4_size, stage5_size;\n wire [11:0] stage1_amp, stage2_amp, stage3_amp, stage4_amp, stage5_amp;\n wire stage1_den, stage2_den, stage3_den, stage4_den, stage5_den;\n wire stage1_dc, stage2_dc, stage3_dc, stage4_dc, stage5_dc;\n\n // =========================================================================\n // Processing Pipeline Stages\n // =========================================================================\n \n // Stage 1: Initial Run-Length Encoding\n jpeg_runlength_stage1 stage1_inst (\n .clk_in (clk_in),\n .reset_in (reset_in),\n .enable_in (enable_in),\n .go_in (dstrb_in),\n .din_in (din_in),\n .rlen_out (stage1_rlen),\n .size_out (stage1_size),\n .amp_out (stage1_amp),\n .den_out (stage1_den),\n .dcterm_out (stage1_dc)\n );\n\n // Stage 2: First Zero-Run Suppression\n jpeg_runlength_rzs stage2_inst (\n .clk_in (clk_in),\n .reset_in (reset_in),\n .enable_in (enable_in),\n .rlen_in (stage1_rlen),\n .size_in (stage1_size),\n .amp_in (stage1_amp),\n .den_in (stage1_den),\n .dc_in (stage1_dc),\n .rlen_out (stage2_rlen),\n .size_out (stage2_size),\n .amp_out (stage2_amp),\n .den_out (stage2_den),\n .dc_out (stage2_dc)\n );\n\n // Stage 3: Second Zero-Run Suppression\n jpeg_runlength_rzs stage3_inst (\n .clk_in (clk_in),\n .reset_in (reset_in),\n .enable_in (enable_in),\n .rlen_in (stage2_rlen),\n .size_in (stage2_size),\n .amp_in (stage2_amp),\n .den_in (stage2_den),\n .dc_in (stage2_dc),\n .rlen_out (stage3_rlen),\n .size_out (stage3_size),\n .amp_out (stage3_amp),\n .den_out (stage3_den),\n .dc_out (stage3_dc)\n );\n\n // Stage 4: Third Zero-Run Suppression\n jpeg_runlength_rzs stage4_inst (\n .clk_in (clk_in),\n .reset_in (reset_in),\n .enable_in (enable_in),\n .rlen_in (stage3_rlen),\n .size_in (stage3_size),\n .amp_in (stage3_amp),\n .den_in (stage3_den),\n .dc_in (stage3_dc),\n .rlen_out (stage4_rlen),\n .size_out (stage4_size),\n .amp_out (stage4_amp),\n .den_out (stage4_den),\n .dc_out (stage4_dc)\n );\n\n // Stage 5: Fourth Zero-Run Suppression (Final Stage)\n jpeg_runlength_rzs stage5_inst (\n .clk_in (clk_in),\n .reset_in (reset_in),\n .enable_in (enable_in),\n .rlen_in (stage4_rlen),\n .size_in (stage4_size),\n .amp_in (stage4_amp),\n .den_in (stage4_den),\n .dc_in (stage4_dc),\n .rlen_out (stage5_rlen),\n .size_out (stage5_size),\n .amp_out (stage5_amp),\n .den_out (stage5_den),\n .dc_out (stage5_dc)\n );\n\n // =========================================================================\n // Output Assignments\n // =========================================================================\n assign rlen_out = stage5_rlen;\n assign size_out = stage5_size;\n assign amp_out = stage5_amp;\n assign douten_out = stage5_den;\n assign bstart_out = stage5_dc;\n\nendmodule", + "rtl/jpeg_runlength_rzs.sv": "module jpeg_runlength_rzs (\n // Clock and Control Signals\n input clk_in, // System clock (positive edge)\n input enable_in, // Clock enable (active high)\n input reset_in, // Synchronous active-high reset\n \n // Input Data Bus\n input den_in, // Data input valid\n input dc_in, // DC coefficient indicator\n input [ 3:0] rlen_in, // Run-length input (0-15)\n input [ 3:0] size_in, // Coefficient size/category\n input [11:0] amp_in, // Coefficient amplitude\n \n // Output Data Bus\n output reg den_out, // Data output valid\n output reg dc_out, // DC coefficient output indicator\n output reg [ 3:0] rlen_out, // Run-length output\n output reg [ 3:0] size_out, // Size/category output\n output reg [11:0] amp_out // Amplitude output\n);\n\n // =========================================================================\n // Internal Registers and Signals\n // =========================================================================\n \n // Pipeline registers for output data\n reg [ 3:0] size;\n reg [ 3:0] rlen;\n reg [11:0] amp;\n reg den;\n reg dc;\n \n // Control signals\n wire eob; // End-of-Block detection\n wire zerobl; // Zero-block detection\n reg state; // State machine state (0=normal, 1=zero-block)\n\n // =========================================================================\n // Data Pipeline Registers\n // =========================================================================\n \n // Input data pipeline stage\n always @(posedge clk_in or posedge reset_in)\n if (reset_in) begin\n size <= 4'b0;\n rlen <= 4'b0;\n amp <= 12'b0;\n end else if (enable_in & den_in) begin\n size <= size_in;\n rlen <= rlen_in;\n amp <= amp_in;\n end\n \n // Output data pipeline stage\n always @(posedge clk_in or posedge reset_in)\n if (reset_in) begin\n size_out <= 4'b0;\n rlen_out <= 4'b0;\n amp_out <= 12'b0;\n dc <= 1'b0;\n dc_out <= 1'b0;\n end else if (enable_in) begin\n size_out <= size;\n rlen_out <= rlen;\n amp_out <= amp;\n dc <= dc_in;\n dc_out <= dc;\n end\n\n // =========================================================================\n // Control Signal Generation\n // =========================================================================\n \n // Zero-block detection: run-length=15 and size=0 with valid data\n assign zerobl = &rlen_in & ~|size_in & den_in;\n \n // End-of-Block detection: run-length=0 and size=0 with valid AC data\n assign eob = ~|{rlen_in, size_in} & den_in & ~dc_in;\n\n // =========================================================================\n // Zero-Suppression State Machine\n // =========================================================================\n always @(posedge clk_in or posedge reset_in)\n if (reset_in) begin\n state <= 1'b0; // Start in normal state\n den <= 1'b0;\n den_out <= 1'b0;\n end else if (enable_in)\n case (state)\n // Normal Processing State\n 1'b0: begin\n if (zerobl) begin\n // Detected zero-block, transition to suppression state\n state <= 1'b1;\n den <= 1'b0; // Suppress output\n den_out <= den; // Output previous data\n end else begin\n // Continue normal processing\n state <= 1'b0;\n den <= den_in; // Pass through data enable\n den_out <= den; // Output previous data\n end\n end\n \n // Zero-Block Suppression State\n 1'b1: begin\n den_out <= 1'b0; // Default to suppressed output\n \n if (den_in) begin // Only act when input valid\n if (zerobl) begin\n // Another zero-block detected\n state <= 1'b1; // Stay in suppression state\n den <= 1'b0; // Continue suppression\n den_out <= 1'b1; // Output previous zero-block\n end else if (eob) begin\n // EOB marker detected\n state <= 1'b0; // Return to normal state\n den <= 1'b1; // Enable EOB output\n den_out <= 1'b0; // Explicitly zero\n end else begin\n // Non-zero data detected\n state <= 1'b0; // Return to normal state\n den <= 1'b1; // Enable data output\n den_out <= 1'b1; // Output zero-block\n end\n end\n end\n endcase\n\nendmodule", + "rtl/jpeg_runlength_stage1.sv": "module jpeg_runlength_stage1 (\n // Clock and reset\n input clk_in, // System clock (positive edge triggered)\n input reset_in, // Synchronous active-high reset\n \n // Control signals\n input enable_in, // Clock enable (active high)\n input go_in, // Start new block (pulse high for 1 cycle)\n \n // Data input\n input [11:0] din_in, // 12-bit DCT coefficient input\n \n // Encoded outputs\n output reg [ 3:0] rlen_out, // Run-length (0-15 zeros before this coefficient)\n output reg [ 3:0] size_out, // Category (bit size needed for coefficient)\n output reg [11:0] amp_out, // Amplitude (modified coefficient value)\n output reg den_out, // Data valid output (active high)\n output reg dcterm_out // Indicates DC term output (active high)\n);\n\n // =========================================================================\n // Internal Signals and State\n // =========================================================================\n \n // Sample counter (0-63 for 8x8 block)\n reg [5:0] sample_cnt;\n \n // Zero run-length counter (counts consecutive zeros)\n reg [3:0] zero_cnt;\n \n // Zero detection signal (high when input is zero)\n wire is_zero = ~|din_in;\n \n // State machine states\n reg state;\n parameter dc = 1'b0; // Processing DC coefficient (first in block)\n parameter ac = 1'b1; // Processing AC coefficients\n\n // =========================================================================\n // Helper Functions\n // =========================================================================\n \n /**\n * Absolute Value Function\n * Returns absolute value of 12-bit signed input\n */\n function [10:0] abs;\n input [11:0] a;\n begin\n abs = a[11] ? (~a[10:0] + 11'h1) : a[10:0]; // 2's complement conversion\n end\n endfunction\n\n /**\n * Category (Bit Size) Calculation\n * Determines the number of bits needed to represent the coefficient\n * Returns value 0-11 (0 means zero coefficient, special case for DC)\n */\n function [3:0] cat;\n input [11:0] a;\n reg [10:0] tmp;\n begin\n tmp = abs(a); // Get absolute value first\n \n // Priority encoder style category detection\n casex(tmp) // synopsys full_case parallel_case\n 11'b1??_????_???? : cat = 4'hb; // 1024..2047 (11 bits)\n 11'b01?_????_???? : cat = 4'ha; // 512..1023 (10 bits)\n 11'b001_????_???? : cat = 4'h9; // 256.. 511 (9 bits)\n 11'b000_1???_???? : cat = 4'h8; // 128.. 255 (8 bits)\n 11'b000_01??_???? : cat = 4'h7; // 64.. 127 (7 bits)\n 11'b000_001?_???? : cat = 4'h6; // 32.. 63 (6 bits)\n 11'b000_0001_???? : cat = 4'h5; // 16.. 31 (5 bits)\n 11'b000_0000_1??? : cat = 4'h4; // 8.. 15 (4 bits)\n 11'b000_0000_01?? : cat = 4'h3; // 4.. 7 (3 bits)\n 11'b000_0000_001? : cat = 4'h2; // 2.. 3 (2 bits)\n 11'b000_0000_0001 : cat = 4'h1; // 1 (1 bit)\n 11'b000_0000_0000 : cat = 4'h0; // 0 (special case)\n endcase\n end\n endfunction\n\n /**\n * Amplitude Modification Function\n * Adjusts coefficient value for more efficient encoding\n */\n function [10:0] rem;\n input [11:0] a;\n reg [10:0] tmp_rem;\n begin\n // For negative numbers: rem = -a - 1\n // For positive numbers: rem = a\n tmp_rem = a[11] ? (a[10:0] - 10'h1) : a[10:0];\n rem = tmp_rem;\n end\n endfunction\n\n // =========================================================================\n // Main Processing Logic\n // =========================================================================\n\n // Amplitude output register\n always @(posedge clk_in or posedge reset_in)\n if (reset_in)\n amp_out <= 12'b0;\n else if (enable_in)\n amp_out <= {din_in[11], rem(din_in)}; // Preserve sign bit\n\n // Sample counter (0-63 for 8x8 block)\n always @(posedge clk_in or posedge reset_in)\n if (reset_in)\n sample_cnt <= 6'b0;\n else if (enable_in)\n if (go_in) // Start new block\n sample_cnt <= 1; // Skip DC position (handled separately)\n else if (|sample_cnt) // Only increment if not zero\n sample_cnt <= sample_cnt + 1;\n\n // Zero run-length counter\n always @(posedge clk_in or posedge reset_in)\n if (reset_in)\n zero_cnt <= 4'b0;\n else if (enable_in)\n if (is_zero)\n zero_cnt <= zero_cnt + 1; // Increment for zero coefficients\n else\n zero_cnt <= 0; // Reset for non-zero coefficients\n\n // =========================================================================\n // State Machine - Controls Output Encoding\n // =========================================================================\n always @(posedge clk_in or posedge reset_in)\n if (reset_in) begin\n state <= dc;\n rlen_out <= 0;\n size_out <= 0;\n den_out <= 1'b0;\n dcterm_out <= 1'b0;\n end else if (enable_in)\n case (state)\n // DC Coefficient Processing State\n dc: begin\n rlen_out <= 0; // DC has no run-length\n size_out <= cat(din_in); // Get DC coefficient size\n \n if (go_in) begin\n // Start processing AC coefficients\n state <= ac;\n den_out <= 1'b1; // Output valid\n dcterm_out <= 1'b1; // Mark as DC term\n end else begin\n // Stay in DC state\n state <= dc;\n den_out <= 1'b0; // No output\n dcterm_out <= 1'b0;\n end\n end\n \n // AC Coefficient Processing State\n ac: begin\n if (&sample_cnt) begin\n // End of block processing\n state <= dc; // Return to DC state\n \n if (is_zero) begin\n // End-of-block marker\n rlen_out <= 0;\n size_out <= 0;\n den_out <= 1'b1;\n dcterm_out <= 1'b0;\n end else begin\n // Last coefficient in block\n rlen_out <= zero_cnt;\n size_out <= cat(din_in);\n den_out <= 1'b1;\n dcterm_out <= 1'b0;\n end\n end else begin\n // Normal AC coefficient processing\n state <= ac;\n rlen_out <= zero_cnt;\n dcterm_out <= 1'b0;\n \n // Handle zero vs non-zero coefficients\n size_out <= is_zero ? 0 : cat(din_in);\n den_out <= is_zero ? &zero_cnt : 1'b1; // Only output after 15 zeros\n end\n end\n endcase\nendmodule", + "docs/8Bit_lfsr_spec.md": null, + "rtl/memory_scheduler.sv": null, + "docs/multiplexer_specification.md": null, + "rtl/multiplexer.sv": null, + "verif/multiplexer_tb.sv": null, + "docs/nbit_swizzling_spec.md": null, + "verif/nbit_swizzling_tb.sv": null, + "docs/nmea_decoder_spec.md": null, + "verif/nmea_decoder_tb.sv": null, + "rtl/axi4lite_to_pcie_cfg_bridge.sv": null, + "rtl/axis_to_uart_tx.sv": null, + "rtl/uart_rx_to_axis.sv": null, + "rtl/axis_to_uart.sv": null, + "rtl/barrel_shifter.sv": null, + "verif/barrel_shifter_tb.sv": null, + "docs/bcd_adder_spec.md": null, + "verif/tb_bcd_adder.sv": null, + "rtl/bcd_adder.sv": null, + "rtl/bcd_top.sv": null, + "rtl/multi_digit_bcd_add_sub.sv": null, + "rtl/full_adder.sv": null, + "rtl/four_bit_adder.sv": null, + "verif/bcd_to_excess_3_tb.sv": null, + "docs/deletion_specification.md": null + } + } +] \ No newline at end of file