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Datasets:
AbiralArch
/
verilog-training-data

Tasks:
Text Generation
Languages:
English
Size:
1K<n<10K
Tags:
verilog
hardware-design
hdl
fpga
asic
Dataset card Files
xet
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verilog-training-data

Commit History

Upload README.md with huggingface_hub
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Upload cvdp_processor_problems.json with huggingface_hub
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Upload cvdp_memory_problems.json with huggingface_hub
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Upload cvdp_expert_problems.json with huggingface_hub
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initial commit
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