Xingquan-Li commited on
Commit
095591b
·
verified ·
1 Parent(s): e218c61

Update README.md

Browse files
Files changed (1) hide show
  1. README.md +2 -2
README.md CHANGED
@@ -62,7 +62,7 @@ The `vectors/` directory contains feature data for each strategy design.
62
  The source data is collected from oscc-ip, iscas89, OpenRoad, and OpenLane.
63
 
64
  ### Data processing
65
- The data processing uses the [AiEDA](https://gitee.com/oscc-project/AiEDA.git) toolkit.The following steps show how to use the toolkit to process the data:
66
 
67
  - SDC preprocessing: run `python AiEDA/test/process_sdc_files.py --dataset-dir <dataset_dir>` to automatically generate placement and routing SDC files with/without `set_propagated_clock [all_clocks]` (written to `place/` and `route/`, respectively).
68
  - Batch placement runs: execute `python AiEDA/test/test_sky130_place.py --design-list <json>` (add `--summary-out`, `--first-class-only`, etc. if needed). The script drives iEDA according to the workspace, Verilog, SDC, and SPEF entries in the design list to perform floorplan→route; outputs are saved in each workspace under `output/iEDA/`. The design list is an array where each item must include at least `design`, `workspace`, `verilog`, and `sdc`, and may optionally include `spef`, `clk_port_name`, etc. Example:
@@ -1069,7 +1069,7 @@ gcd/iEDA_route_process_data/gcd_a_place/
1069
  ```
1070
 
1071
  ## Data Owner
1072
- iEDA Team
1073
 
1074
  ## License
1075
  GPL
 
62
  The source data is collected from oscc-ip, iscas89, OpenRoad, and OpenLane.
63
 
64
  ### Data processing
65
+ The data processing uses the [AiEDA](https://github.com/OSCC-Project/AiEDA) toolkit.The following steps show how to use the toolkit to process the data:
66
 
67
  - SDC preprocessing: run `python AiEDA/test/process_sdc_files.py --dataset-dir <dataset_dir>` to automatically generate placement and routing SDC files with/without `set_propagated_clock [all_clocks]` (written to `place/` and `route/`, respectively).
68
  - Batch placement runs: execute `python AiEDA/test/test_sky130_place.py --design-list <json>` (add `--summary-out`, `--first-class-only`, etc. if needed). The script drives iEDA according to the workspace, Verilog, SDC, and SPEF entries in the design list to perform floorplan→route; outputs are saved in each workspace under `output/iEDA/`. The design list is an array where each item must include at least `design`, `workspace`, `verilog`, and `sdc`, and may optionally include `spef`, `clk_port_name`, etc. Example:
 
1069
  ```
1070
 
1071
  ## Data Owner
1072
+ [iEDA Team](https://github.com/OSCC-Project)
1073
 
1074
  ## License
1075
  GPL