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LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY floating_point_v7_1_2; USE floating_point_v7_1_2.floating_point_v7_1_2; ENTITY fmul IS PORT ( aclk : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_b_tvalid : IN STD_LOGIC; s_axis_b_tda... |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 11; -- bitwidth of local memory address for a single PE constant N_AXI_W ... |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use work.CONSTANTS.all; use work.CONFIG_MANDELBROT.all; entity cpt_iter is Port ( clock : in STD_LOGIC; reset : in STD_LOGIC; inib : in std_logic; endcalcul : in STD_LOGIC; maxiter : in STD_LOGIC; iter : out STD_LOGIC_VECTOR(ITER_RANGE-1 downto 0)); ... |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W ... |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; entity CU_instruction_dispatcher is --{{{ port( clk, nrst : in std_logic; cram_rqst : out std_logic := '0'; cram_rdAddr : out unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0'); cram_rdAddr_con... |
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; USE IEEE.NUMERIC_STD.all; LIBRARY UniSim; USE UniSim.vComponents.ALL; entity xil_SystemMonitor_Virtex6 is port ( Reset : in STD_LOGIC; -- Reset signal for the System Monitor control logic Alarm_UserTemp : out STD_LOGIC; -- Temperature-sensor alarm output Alarm_OverTemp : out ... |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W ... |
library ieee; use ieee.std_logic_1164.ALL; use ieee.std_logic_unsigned.all; use ieee.numeric_std.ALL; package mips_defs is subtype mips_opcode_type is std_logic_vector(5 downto 0); subtype mips_func_type is std_logic_vector(5 downto 0); constant OP_SPECIAL : std_logic_vector(5 downto 0) := "000000"; constant OP_J : std... |
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.nf_pkg.all; entity nf_transmitter is port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high reset rst_syn_i : ... |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W ... |
LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY echo_tb IS END echo_tb; ARCHITECTURE behavior OF echo_tb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT echo PORT( rx : IN std_logic; tx : OUT std_logic; clk : IN std_logic ); END COMPONENT; component uart is generic ( CLK_FREQ : integer := 32; -- M... |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; package FGPU_definitions is constant N_CU_W : natural := 0; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W ... |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity uart is generic ( CLK_FREQ : integer := 32; -- Main frequency (MHz) SER_FREQ : integer := 9600; -- Baud rate (bps) PARITY_BIT : boolean := true -- Parity bit enable/disable ); port ( -- Control clk : in std_... |
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY Decoder_Decoder_sch_tb IS END Decoder_Decoder_sch_tb; ARCHITECTURE behavioral OF Decoder_Decoder_sch_tb IS COMPONENT Decoder PORT ( RF : OUT STD_LOGIC; RR : OUT STD_LOGIC; LF : OUT STD_LOGIC; LR : OUT STD_LOGIC; SCLK : IN STD_LOGIC; I : IN STD_... |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W ... |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; package FGPU_definitions is constant N_CU_W : natural := 0; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W ... |
library ieee; use ieee.std_logic_1164.ALL; use ieee.std_logic_unsigned.all; use ieee.numeric_std.ALL; entity register_file is port (clk : in std_logic; rst : in std_logic; a1 : in std_logic_vector(4 downto 0); a2 : in std_logic_vector(4 downto 0); a3 : in std_logic_vector(4 downto 0); wd3 : in std_logic_vector(31 downt... |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; library PoC; use PoC.my_config.all; use PoC.utils.all; entity io_TimingCounter is generic ( TIMING_TABLE : T_NATVEC -- timing table ); port ( Clock : in STD_LOGIC; -- clock Enable : in STD_LOGIC; -- enable counter Load : in STD_LOGIC; -- load Timing ... |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; entity gmem_cntrl_tag is -- {{{ port( -- axi signals wr_fifo_free : in std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); --free ports have to respond to go ports immediately (in one cl... |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W ... |
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY floating_point_v7_1_2; USE floating_point_v7_1_2.floating_point_v7_1_2; ENTITY fsqrt IS PORT ( aclk : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_result_tvalid : OUT STD_LOGIC; m_axi... |
library IEEE; use IEEE.std_logic_1164.all; library PoC; use PoC.utils.all; entity msg_tap is generic ( D : positive -- Message Buffer Depth (Size) ); port ( -- Global Control clk : in std_logic; rst : in std_logic; -- Tap Input iful : out std_logic; idat : in byte; ieof : in std_logic; iput : in std_logic; -- Tap Forwa... |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W ... |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W ... |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity DataMemory is Port ( enableMem : in STD_LOGIC; reset : in STD_LOGIC; cRD : in STD_LOGIC_VECTOR (31 downto 0); address : in STD_LOGIC_VECTOR (31 downto 0); wrEnMem : in STD_LOGIC; datoToWr : out STD_LOGIC_VECTOR (31 downto 0) ); end DataM... |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant ... |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Sparcv8Monocicle is Port ( CLK : in STD_LOGIC; RST: in STD_LOGIC; R : out STD_LOGIC_VECTOR(31 downto 0) ); end Sparcv8Monocicle; architecture Behavioral of Sparcv8Monocicle is COMPONENT windows_manager PORT( cwp : IN std_logic; rs1 : IN std_logic_vector(4 downto 0); rs2... |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; library xil_defaultlib; use xil_defaultlib.all; entity FGPU_v2_1 is -- generics {{{ generic ( -- Users to add parameters here -- User parameters ends -- Do not modify the parameters beyond thi... |
entity queens_slice0_tb is generic ( N : positive := 16 -- Choose your board size ); end queens_slice0_tb; library IEEE; use IEEE.std_logic_1164.all; architecture tb of queens_slice0_tb is component queens_slice generic ( N : positive; -- size of field L : natural -- number of preplaced columns ); port ( clk : in std_... |
library ieee; use ieee.std_logic_1164.ALL; use ieee.std_logic_unsigned.all; use ieee.numeric_std.ALL; library work; use work.mips_defs.ALL; entity cpu_execute is port (rt : in std_logic_vector(4 downto 0); rd : in std_logic_vector(4 downto 0); shamt : in std_logic_vector(4 downto 0); imm : in std_logic_vector(31 downto... |
library IEEE; use IEEE.std_logic_1164.all; library PoC; use PoC.physical.all; entity dnk7_queens0 is generic ( -- Design Parameters N : positive := 27; L : positive := 2; SOLVERS : positive := 240; COUNT_CYCLES : boolean := false; SENTINEL : std_logic_vector(7 downto 0) := x"FA"; -- Start Byte -- Local Clock Parameters... |
LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_unsigned.ALL; ENTITY debouncer IS PORT ( rst: IN std_logic; clk: IN std_logic; x: IN std_logic; xDeb: OUT std_logic; xDebFallingEdge: OUT std_logic; xDebRisingEdge: OUT std_logic ); END debouncer; ARCHITECTURE debouncerArch of debouncer is SIGNAL xSync: std_... |
library IEEE; use IEEE.std_logic_1164.all; entity xupv5_queens_uart is generic ( N : positive := 27; L : positive := 2; SOLVERS : positive := 52; COUNT_CYCLES : boolean := false; CLK_FREQ : positive := 100000000; CLK_MUL : positive := 25; CLK_DIV : positive := 14; BAUDRATE : positive := 115200; SENTINEL : std_logic_vec... |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W ... |
library IEEE; use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.NUMERIC_STD.all; -- conversion functions library work; use work.WF_PACKAGE.all; -- definitions of types, constants, entities entity wf_tx_osc is port ( -- INPUTS -- nanoFIP User Interface, General signals uclk_i : in std_logic; -- 40 MHz cloc... |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W ... |
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library dyplo_hdl_node_lib; use dyplo_hdl_node_lib.hdl_node_package.all; use dyplo_hdl_node_lib.hdl_node_user_params.all; entity dyplo_user_logic_adder is generic( INPUT_STREAMS : integer := 4; OUTPUT_STREAMS : integer := 4 ); port( -- Processor bus ... |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W ... |
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.nf_pkg.all; entity nf_tx_registers is port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high reset rst_syn_i :... |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; entity CU_scheduler is --- {{{ port( clk, nrst : in std_logic; -- output status signals wf_active : out std_logic_vector(N_WF_CU-1 downto 0) := (others => '0'); -- for Work-Group Dispatcher sc... |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library WORK; use WORK.CONSTANTS.ALL; use WORK.FUNCTIONS.ALL; entity Colorgen is Port ( iters : in STD_LOGIC_VECTOR (ITER_RANGE-1 downto 0); itermax : in STD_LOGIC_VECTOR (ITER_RANGE-1 downto 0); color : out STD_LOGIC_VECTOR (bit_per_pixel-1 downto 0)... |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W ... |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 11; -- bitwidth of local memory address for a single PE constant N_AXI_W ... |
library IEEE; use IEEE.std_logic_1164.all; library PoC; use PoC.physical.all; entity sdrc_queens_master is generic ( -- Design Parameters N : positive := 27; L : positive := 2; SOLVERS : positive := 90; COUNT_CYCLES : boolean := false; -- Local Clock Parameters CLK_FREQ : FREQ := 16 MHz; -- external clock CLK_MUL : pos... |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; library tb_lib; use tb_lib.tb_env_pkg.all; library std; use std.env.all; use std.textio.all; library dyplo_hdl_node_lib; use dyplo_hdl_node_lib.hdl_node_package.all; use dyplo_hdl_node_lib.hdl_node_user_params.all; li... |
library ieee; use ieee.std_logic_1164.ALL; use ieee.std_logic_unsigned.all; use ieee.numeric_std.ALL; library work; use work.mips_defs.ALL; entity alu is port (op : in alucontrol_type; a : in std_logic_vector(31 downto 0); b : in std_logic_vector(31 downto 0); shift : in std_logic_vector(4 downto 0); result : out std_l... |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; entity CU_mem_cntrl is --{{{ port( clk : in std_logic; -- from the CV cv_wrData : in SLV32_ARRAY(CV_SIZE-1 downto 0); -- level 17. cv_addr : in GMEM_ADDR_ARRAY; -- level 17. cv_gmem_we : in st... |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W ... |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity register_file is Port( Wren : in STD_LOGIC; rst : in STD_LOGIC; rs1 : in STD_LOGIC_VECTOR (5 downto 0); rs2 : in STD_LOGIC_VECTOR (5 downto 0); rd : in STD_LOGIC_VECTOR (5 downto 0); data : in STD_LOGIC_VECTOR (31 downto 0); crs1 : out S... |
library IEEE; use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.NUMERIC_STD.all; -- conversion functions library work; use work.WF_PACKAGE.all; -- definitions of types, constants, entities entity wf_model_constr_decoder is port( -- INPUTS -- nanoFIP User Interface general signal uclk_i : in std_logic; -- ... |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; entity gmem_atomics is port( -- {{{ rcv_atomic_type : in be_array(N_RECEIVERS-1 downto 0); rcv_atomic_rqst : in std_logic_vector(N_RECEIVERS-1 downto 0); rcv_gmem_addr : in gmem_word_addr_arra... |
library IEEE; use IEEE.std_logic_1164.all; entity fifo_glue is generic ( D_BITS : positive -- Data Width ); port ( -- Control clk : in std_logic; -- Clock rst : in std_logic; -- Synchronous Reset -- Input put : in std_logic; -- Put Value di : in std_logic_vector(D_BITS-1 downto 0); -- Data Input ful : out std_logic; -... |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W ... |
library IEEE; use IEEE.std_logic_1164.all; library PoC; use PoC.physical.all; entity sdrc_queens_slave is generic ( -- Design Parameters N : positive := 27; L : positive := 2; SOLVERS : positive := 90; COUNT_CYCLES : boolean := false; -- Local Clock Parameters CLK_FREQ : FREQ := 16 MHz; -- external clock CLK_MUL : posi... |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W ... |
library ieee; use ieee.std_logic_1164.ALL; use ieee.std_logic_unsigned.all; use ieee.numeric_std.ALL; entity cpu_fetch is port (pc : in std_logic_vector(31 downto 0); pcbranch : in std_logic_vector(31 downto 0); pcsrc : in std_logic; instr_n : out std_logic_vector(31 downto 0); pcplus4_n : out std_logic_vector(31 downt... |
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; entity fetch_page_ow is port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high reset rst_syn_i : in std_ulogic; --! @} ... |
library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use IEEE.math_real.all; library PoC; use PoC.config.all; use PoC.utils.all; package strings is -- default fill and string termination character for fixed size strings -- =========================================================================== -- W... |
library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library poc; use poc.config.all; USE poc.utils.all; use poc.ocram.ocram_sdp; entity fifo_cc_got_tempput is generic ( D_BITS : positive; -- Data Width MIN_DEPTH : positive; -- Minimum FIFO Depth DATA_REG : boolean := false; -- Store Data Content in Re... |
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY AsyncTxTest IS END AsyncTxTest; ARCHITECTURE behavioral OF AsyncTxTest IS COMPONENT AsyncTx PORT ( TX : OUT STD_LOGIC; ACTIVE : OUT STD_LOGIC; SEND : IN STD_LOGIC; CLR : IN STD_LOGIC; CLK : IN STD_LOGIC; DATA : IN STD_LOGIC_VECTOR (5 DOWNTO 0))... |
library IEEE; use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.NUMERIC_STD.all; -- conversion functions library PROASIC3; -- ProASIC3 library use PROASIC3.all; entity dualram_512x8 is port( -- INPUTS -- Inputs concerning port A CLKA : in std_logic; -- clock A for synchronous read/ write operations ADDRA ... |
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; entity fetch_page_sram_adc is port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high reset rst_syn_i : in std_ulogic; -... |
library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library PoC; use PoC.utils.all; package config_private is -- TODO: -- =========================================================================== subtype T_BOARD_STRING is string(1 to 16); subtype T_BOARD_CONFIG_STRING is string(1 to 64); subtype T_D... |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; package FGPU_definitions is constant N_CU_W : natural := 1; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 11; -- bitwidth of local memory address for a single PE constant N_AXI_W ... |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W ... |
library IEEE; use IEEE.std_logic_1164.all; entity s3sk_queens_uart is generic ( N : positive := 27; L : positive := 2; SOLVERS : positive := 9; COUNT_CYCLES : boolean := false; CLK_FREQ : positive := 50000000; CLK_MUL : positive := 22; CLK_DIV : positive := 13; BAUDRATE : positive := 115200; SENTINEL : std_logic_vector... |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; entity ALU is -- {{{ port( rs_addr : in unsigned(REG_FILE_BLOCK_W-1 downto 0); -- level 1. rt_addr : in unsigned(REG_FILE_BLOCK_W-1 downto 0); -- level 1. rd_addr : in unsigned(REG_FILE_BLOCK_... |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use std.textio.all; entity instructionMemory is Port ( --clk : in STD_LOGIC; address : in STD_LOGIC_VECTOR (31 downto 0); reset : in STD_LOGIC; outInstruction : out STD_LOGIC_VECTOR (31 downto 0)); end instructionMemory; architecture arqInstruc... |
library IEEE; use IEEE.std_logic_1164.all; entity sdrc4_queens_uart is generic ( N : positive := 27; L : positive := 2; SOLVERS : positive := 79; COUNT_CYCLES : boolean := false; CLK_FREQ : positive := 16000000; CLK_MUL : positive := 23; CLK_DIV : positive := 3; BAUDRATE : positive := 115200; SENTINEL : std_logic_vecto... |
library ieee; use ieee.std_logic_1164.all; library work; entity fetch_page is port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high reset rst_syn_i : in std_ulogic; --! @} --! @name Commands --! @{ --!... |
library ieee; use ieee.std_logic_1164.ALL; use ieee.std_logic_unsigned.all; use ieee.numeric_std.ALL; entity cpu_tb is generic (FIRMWARE : string); end entity cpu_tb; architecture behav of cpu_tb is component cpu is port (clk : in std_logic; rst : in std_logic; mem_halt : in std_logic; pc : out std_logic_vector(31 down... |
library ieee; use ieee.std_logic_1164.ALL; use ieee.std_logic_unsigned.all; use ieee.numeric_std.ALL; library work; use work.mips_defs.ALL; entity cpu is port (clk : in std_logic; rst : in std_logic; mem_halt : in std_logic; pc : out std_logic_vector(31 downto 0); instr : in std_logic_vector(31 downto 0); data_addr : o... |
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY blk_mem_gen_v8_2; USE blk_mem_gen_v8_2.blk_mem_gen_v8_2; ENTITY LIST IS PORT ( clka : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); clkb : IN STD_LOGIC; a... |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W ... |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W ... |
component nios_system is port ( switches_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export leds_export : out std_logic_vector(3 downto 0); -- export clk_clk : in std_logic := 'X'; -- clk reset_reset_n : in std_logic := 'X' -- reset_n ); end component nios_system; u0 : component nios_system port ma... |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W ... |
library IEEE; library UNISIM; use UNISIM.vcomponents.all; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity tron is port ( ps2Clk: IN std_logic; ps2Data: IN std_logic; clk: IN std_logic; reset: IN std_logic; --reset activo a baja! hSync: OUT std_logic; Vsync: OUT std_logic; colisionOUT: OUT std_logi... |
library ieee; use ieee.std_logic_1164.all; library work; entity debug_serial is port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high reset rst_syn_i : in std_ulogic; --! @} --! @name Debugging interfa... |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W ... |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; library PoC; use PoC.utils.all; PACKAGE components IS -- FlipFlop functions function ffdre(q : STD_LOGIC; d : STD_LOGIC; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC; -- D-FlipFlop with reset and enable function ffdre(q : STD_LOGIC... |
library IEEE; use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.NUMERIC_STD.all; -- conversion functions library work; use work.WF_PACKAGE.all; -- definitions of types, constants, entities entity wf_rx_deglitcher is port( -- INPUTS -- nanoFIP User Interface general signal uclk_i : in std_logic; -- 40 MHz ... |
library ieee; use ieee.std_logic_1164.all; library work; use work.ab_pkg.all; use work.nf_pkg.all; use work.ads1281_filter_pkg.all; entity ab is port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high re... |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 11; -- bitwidth of local memory address for a single PE constant N_AXI_W ... |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W ... |
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY blk_mem_gen_v8_2; USE blk_mem_gen_v8_2.blk_mem_gen_v8_2; ENTITY VOICE_ROM_INIT IS PORT ( clka : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(5 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0); clkb : IN S... |
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_misc.all; use ieee.std_logic_unsigned.all; entity VOICE_DELAY is port ( clk:in std_logic; start:in std_logic:='0'; total:in std_logic_vector(7 downto 0); finish:out std_logic:='1' ); end entity; architecture delayx of VOICE_DELA... |
library IEEE; use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.NUMERIC_STD.all; -- conversion functions library work; use work.WF_PACKAGE.all; -- definitions of types, constants, entities entity wf_prod_data_lgth_calc is port( -- INPUTS -- nanoFIP User Interface, General signals uclk_i : in std_logic; --... |
library IEEE; use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.NUMERIC_STD.all; -- conversion functions library work; use work.WF_PACKAGE.all; -- definitions of types, constants, entities entity wf_crc is port( -- INPUTS -- nanoFIP User Interface, General signals uclk_i : in std_logic; -- 40 MHz clock --... |
library IEEE; use IEEE.std_logic_1164.all; library PoC; use PoC.physical.all; entity dnk7_queens1 is generic ( -- Design Parameters N : positive := 27; L : positive := 2; SOLVERS : positive := 240; COUNT_CYCLES : boolean := false; -- Local Clock Parameters CLK_FREQ : FREQ := 50 MHz; CLK_DIV : positive := 1; -- CLK_FREQ... |
library IEEE; use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.NUMERIC_STD.all; -- conversion functions library work; use work.WF_PACKAGE.all; -- definitions of types, constants, entities entity wf_incr_counter is generic(g_counter_lgth : natural := 4); -- default length port( -- INPUTS -- nanoFIP User I... |
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY floating_point_v7_1_2; USE floating_point_v7_1_2.floating_point_v7_1_2; ENTITY fadd_fsub IS PORT ( aclk : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_b_tvalid : IN STD_LOGIC; s_axis_... |
library IEEE; use IEEE.std_logic_1164.all; library PoC; use PoC.utils.all; entity expand_blocking is generic( N : positive; L : positive ); port( pre : in std_logic_vector(4*L*log2ceil(N)-2 downto 0); bh : out std_logic_vector(L to N-L-1); bv : out std_logic_vector(L to N-L-1); bu : out std_logic_vector(0 to 2*N-4*L-2)... |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W ... |
library IEEE; use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.NUMERIC_STD.all; -- conversion functions library work; use work.WF_PACKAGE.all; -- definitions of types, constants, entities entity wf_wb_controller is port( -- INPUTS -- nanoFIP User Interface, WISHBONE Slave wb_clk_i : in std_logic; -- WISH... |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity control_unit is Port ( op : in STD_LOGIC_VECTOR (1 downto 0); op2 : in STD_LOGIC_VECTOR (2 downto 0); op3 : in STD_LOGIC_VECTOR (5 downto 0); icc : in STD_LOGIC_VECTOR (3 downto 0); cond: in STD_LOGIC_VECTOR (3 downto 0); Aluop: out STD_LOGIC_VECTOR (5 downto 0); wrenDM... |
case expression is when choiceList1 => target := expr1; when choiceList2 => target := expr2; ... when choiceListN => target := exprN; end case; |
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library dyplo_hdl_node_lib; use dyplo_hdl_node_lib.hdl_node_package.all; use dyplo_hdl_node_lib.hdl_node_user_params.all; entity dyplo_user_logic_adder_2_to_1 is generic( INPUT_STREAMS : integer := 4; OUTPUT_STREA... |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W ... |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W ... |
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