level: Easy

type: Sensing

task: Design a resistor divider to scale a high-voltage input to a low-voltage sense node for single-end ADC measurement, you don't need to provide other functions.

input_nodes: VIN

output_nodes: VSENSE

components: Resistors


task: Design an isolated voltage sensing front-end using a resistor divider with an isolated amplifier to measure a high-voltage bus and output an isolated differential low-voltage sense signal. Use only AMC1350 and passive components; you do not need to model or provide the isolated VDD1/GND1 supply rails (assume they are provided externally).

output_nodes: OUTP, OUTN


task: Design a differential-to-single-ended amplifier using one op-amp with a VREF offset. Assume VREF=1.65 V and differential input VINP-VINN = +/-2.0 V. Use a standard differential amplifier with matched pairs R1=R3 and R2=R4, and choose the gain so that VOUT stays within 0 to 3.0 V.

input_nodes: VINP, VINN, VREF

output_nodes: VOUT


task: Design a Hall-effect isolated current sensing circuit that measures line current through an integrated isolated current path and outputs an isolated analog signal, the isolation barrier and amplifier are already provided within the chip.


type: AuxPower

task: Design an LDO-based supply that converts a DC input into a regulated low-voltage rail.


task: Design a low voltage auxilary buck regulator using chip that converts a DC input into a regulated low-voltage rail. if EN is left floating it defaults to enabled,please connect EN to NC.


level: Medium

task: Design an isolated DC-DC module that generates isolated positive and negative gate-drive supply rails for isolated gate drivers or sensors.

output_nodes: VISO+, VISO-


type: PowerStage

task: Implement a TO-247-3 MOSFET half-bridge power stage with a switching phase output. Note that at least 8 decoupling caps for high dv/dt loop is needed, gate driver is NOT needed for this task.

input_nodes: VBUS+, GATE_H, GATE_L

output_nodes: VSW


task: Implement a TO-247-4 SiC MOSFET half-bridge stage with Kelvin source connection. Note that at least 8 decoupling caps for high dv/dt loop is needed , gate driver is NOT needed for this task.


task: Implement a TOLL MOSFET half-bridge stage with Kelvin source connection. Note that at least 8 decoupling caps for high dv/dt loop is needed, gate driver is NOT needed for this task.


task: Implement a TOLT top-side-cooled MOSFET half-bridge stage with Kelvin source connection. Note that at least 8 decoupling caps for high dv/dt loop is needed, gate driver is NOT needed for this task.


task: Implement a QFN-8*8 integrated half-bridge power stage. Note that at least 8 decoupling caps for high dv/dt loop is needed, gate driver is NOT needed for this task.


type: Driver

task: Design a low-side gate driver that drives a MOSFET gate from a logic-level PWM signal, do not include power MOSFET,please include gate resistor.

input_nodes: PWM, VCC

output_nodes: GATE


task: Design a bootstrap high-side/low-side half-bridge gate driver that generates HO/LO outputs from logic PWM inputs, noted that the bootstrap freewheeling diode is integrated in the driver, do not add bootstrap diode again, do not include power MOSFET,please include gate resistor

input_nodes: PWM_H, PWM_L, VCC

output_nodes: HO, LO, VB, VS


task: Design an isolated gate driver that transfers PWM across an isolation barrier to drive a MOSFET gate, the secondary side of the gate driver is driven by isolated bipolar +15/-9V power supply, do not include power MOSFET, please include gate resistor

input_nodes: PWM, VCC1, VCC2, VEE2

output_nodes: OUT


task: Design a protected isolated gate driver with DESAT detection, Miller clamp, fault reporting, and enable control, the secondary side of the gate driver is driven by isolated bipolar +15/-9V power supply, do not include power MOSFET. OUTH and OUTL must each use a series turn-on/off resistor.

input_nodes: PWM, VCC, EN/FLT, VDD, VEE

output_nodes: OUT, FLT, DESAT, CLAMP


level: Hard

type: DC-DC

task: Design a synchronous buck converter using a half-bridge power stage. Include appropriate gate drivers and gate resistor structures that can individually control the turn-on and turn-off speed. Include appropriate power supply for gate drivers.

input_nodes: VIN, PWM_H, PWM_L


task: Design a synchronous boost converter using a half-bridge power stage. Include appropriate gate drivers and gate resistor structures that can individually control the turn-on and turn-off speed. Include appropriate power supply for gate drivers.


task: Design a 4-switch buck-boost converter using two half-bridges. Include appropriate gate drivers and gate resistor structures that can individually control the turn-on and turn-off speed. Include appropriate power supply for gate drivers.

input_nodes: VIN, PWM_1_H, PWM_1_L, PWM_2_H, PWM_2_L


task: Design a dual active bridge converter with one full bridge on primary side, one full bridge on secondary side. On the primary side, place one DC blocking capacitor and one external series inductor between one leg midpoint and the transformer primary terminal; the other leg midpoint connects directly to the other transformer primary terminal. Leave the port for transformers. Include appropriate gate drivers and gate resistor structures that can individually control the turn-on and turn-off speed. Include appropriate power supply for gate drivers.

input_nodes: VIN, PWM_PRI_H, PWM_PRI_L, PWM_SEC_H, PWM_SEC_L

output_nodes: VSW_1, VSW_2


task: Design an LLC resonant converter with a half-bridge on the primary side and an isolated transformer output. On the primary side, place one DC blocking capacitor and one resonant inductor in series between the half-bridge switch node and the transformer primary terminal; the other transformer primary terminal connects to the half-bridge DC bus midpoint. Leave the port for transformers. Include appropriate gate drivers and gate resistor structures that can individually control the turn-on and turn-off speed. Include appropriate power supply for gate drivers.


type: DC-AC

task: Design a 3-phase motor drive using three half-bridges. Include appropriate gate drivers and gate resistor structures that can individually control the turn-on and turn-off speed. Include appropriate power supply for gate drivers.

input_nodes: VIN, PWM_1_H, PWM_1_L, PWM_2_H, PWM_2_L, PWM_3_H, PWM_3_L

output_nodes: VSW_1, VSW_2, VSW_3


task: Design a single-phase grid-tied inverter from a DC link input. Include appropriate gate drivers and gate resistor structures that can individually control the turn-on and turn-off speed. Include appropriate power supply for gate drivers.

input_nodes: VIN, GRID_L, GRID_N, PWM_1_H, PWM_1_L, PWM_2_H, PWM_2_L


type: Comm

task: Design a non-isolated CAN bus transceiver circuit using SN65HVD230. Include a 120 ohm termination resistor between CANH and CANL, and a 100nF decoupling capacitor on VCC. The RS pin should be connected to GND for high-speed mode. Connect TXD and RXD to the MCU side.

input_nodes: TXD, RXD

output_nodes: CANH, CANL


type: Filter

task: Design a 400V DC-link pi filter (C-L-C with damping resistor) for high-voltage bus filtering using film capacitors and a power inductor.

input_nodes: VBUS_IN, PGND

components: C_film, Inductor_power


task: Design a second-order Sallen-Key antialiasing low-pass filter for ADC front-end using OPA328. Include VREF biasing for single-supply operation.

input_nodes: VIN, VDD, GND, VREF


task: Design an NTC thermistor temperature sensing circuit with pull-up voltage divider and RC filtering for ADC input.

input_nodes: VDD, GND

components: NTC, R, C


task: Design a bidirectional shunt current sense amplifier using INA240A1. Include input filtering and VREF biasing.

input_nodes: IP+, IP-, VDD, GND, VREF

output_nodes: ISENSE


task: Design a bridge signal instrumentation amplifier using INA333 for strain gauge or load cell measurement. Include gain-setting resistor and VREF biasing.

input_nodes: VINP, VINN, VREF, VDD, GND


task: Design a PT100 RTD digital temperature converter using MAX31865 with SPI output interface. Include reference resistor and filtering.

input_nodes: RTDIN+, RTDIN-, VDD, GND, SCLK, MOSI, CS

output_nodes: MISO


task: Design a K-type thermocouple analog amplifier using AD8495 with built-in cold junction compensation.

input_nodes: TC+, TC-, VDD, GND


type: DataConv

task: Design a 12-bit SPI ADC circuit using ADS7042 with input RC antialiasing filter and reference decoupling.

input_nodes: AIN, VDD, GND, SCLK, CS


task: Design a 12-bit SPI DAC with output buffer using MCP4921 and OPA328. Include RC output filtering.

input_nodes: VDD, GND, SCLK, MOSI, CS, VREF


task: Design a precision 3.3V voltage reference using REF3033 with input and output decoupling filtering.

input_nodes: VIN, GND

output_nodes: VREF


type: MCU

task: Design an STM32F103C8T6 minimum system with power supply decoupling, reset circuit, SWD debug interface, BOOT configuration, and CAN peripheral connections.

input_nodes: VDD3V3, GND, NRST

output_nodes: TIM, CAN, SPI, GPIO


task: Design an STM32F103C8T6 minimum system with power supply decoupling, reset circuit, SWD debug interface, crystal oscillator, and UART connections.

input_nodes: VDD3V3, GND

output_nodes: SPI, UART, GPIO


task: Design a crystal oscillator network (8MHz Pierce oscillator) with load capacitors and series damping resistor for MCU clock input.

input_nodes: XIN, XOUT, GND

output_nodes: XIN, XOUT

components: Crystal, C_load


task: Design an RS485 half-duplex transceiver circuit using SP3485. Include termination resistor, bus biasing resistors, and ESD protection.

input_nodes: VDD3V3, GND, TXD, RXD, DE_RE

output_nodes: A, B


task: Design a USB to UART bridge circuit using CP2102N with USB ESD protection using TPD4E05U06. Include decoupling and crystal.

input_nodes: VBUS, D+, D-, GND

output_nodes: TXD, RXD


type: Isolation

task: Design a 4-channel SPI digital isolator using ISO7741 with 3 forward channels and 1 reverse channel. Include decoupling on both sides.

input_nodes: VDD1, GND1, VDD2, GND2, MOSI_IN, SCLK_IN, CS_IN, MISO_IN

output_nodes: MOSI_ISO, SCLK_ISO, CS_ISO, MISO_ISO


task: Design a bidirectional I2C digital isolator using ADUM1250. Include decoupling and pull-up resistors on both sides.

input_nodes: VDD1, GND1, VDD2, GND2, SDA1, SCL1

output_nodes: SDA2, SCL2


type: Storage

task: Design a SPI NOR Flash circuit using W25Q64JV. Include decoupling, CS pull-up, and HOLD/WP pin handling.

input_nodes: VDD, GND, SCLK, MOSI, CS


task: Design an I2C EEPROM circuit using AT24C256. Include address configuration, write protect, and I2C pull-up resistors.

input_nodes: VDD, GND, SDA, SCL, WP

output_nodes: SDA, SCL


type: PowerMgmt

task: Design an I2C power monitor circuit using INA226 with high-side shunt resistor and bus voltage filtering.

input_nodes: VDD, GND, VBUS+, VBUS-, SDA, SCL

output_nodes: ALERT


task: Design a power tree with Buck regulator (TPS54302) for 3.3V digital rail followed by LDO (TLV1117-33) for 3.3V low-noise analog rail from 12V input.

input_nodes: VIN12, GND

output_nodes: V3P3_DIG, V3P3_ANA


task: Design a fully isolated CAN interface using ISO7741 digital isolator, SN65HVD230 CAN transceiver, and NXE1S0303MC isolated DC-DC power supply.

input_nodes: VDD, GND, TXD, RXD


type: BMS

task: Design a 5-series battery cell AFE using BQ76920 with RC cell sampling network, cell balancing resistors, I2C interface, and NTC temperature sensing.

input_nodes: CELL0, CELL1, CELL2, CELL3, CELL4, CELL5, PACK+, PACK-, SDA, SCL

output_nodes: ALERT, CHG, DSG


type: BMS-System

task: Design a complete 5S BMS system with BQ76920 AFE, BQ76200 high-side charge/discharge FET driver, and SN65HVD230 CAN bus communication interface.

input_nodes: CELL0, CELL1, CELL2, CELL3, CELL4, CELL5, PACK+, PACK-, CAN_TXD, CAN_RXD

output_nodes: CANH, CANL, CHG, DSG


type: Motor-System

task: Design a complete BLDC FOC controller with STM32F103C8T6 MCU, three isolated gate drivers (UCC5390E), six SiC MOSFETs (IMZA65R015M2H) forming three half-bridges, and two current sense amplifiers (INA240A1).

input_nodes: VIN, PWM, GND

output_nodes: VSW_A, VSW_B, VSW_C


type: DAQ-System

task: Design a 4-channel isolated data acquisition system with four ADS7042 ADCs, ISO7741 SPI isolator, NXE1S0303MC isolated DC-DC power, and REF3033 precision reference.

input_nodes: AIN1, AIN2, AIN3, AIN4, VDD, GND, SCLK, MOSI, CS


type: IoT-System

task: Design an IoT sensor node with STM32F103C8T6 MCU, SN65HVD230 CAN transceiver, TPS54302 Buck regulator, and TLV1117-33 LDO for power management.

output_nodes: CANH, CANL, TEMP_ADC


type: Charger-System

task: Design a Li-ion battery charger system with BQ25895 charge controller, INA226 power monitor, and TPD4E05U06 USB ESD protection.

output_nodes: BAT, SYS


type: Converter-System

task: Design a DAB converter with MCU control using the P20 DAB base topology plus STM32F103C8T6 MCU, SN65HVD230 CAN transceiver, and INA240A1 current sense amplifier.

input_nodes: VIN, PWM, GND, CAN_TXD, CAN_RXD

output_nodes: VOUT, CANH, CANL


task: Design a SPI Ethernet controller circuit using W5500. Include RJ45 magnetic interface connections, decoupling, and ESD protection.

input_nodes: VDD, GND, SCLK, MOSI, CS, MISO

output_nodes: TXP, TXN, RXP, RXN


task: Design a stepper motor driver system using DRV8825 with TPS54302 for motor power supply. Include current limiting configuration and MCU control interface.

input_nodes: VDD, GND, STEP, DIR, VMOT


task: Design a voltage supervisor and watchdog reset circuit using TPS3808 with adjustable threshold and delay.

input_nodes: VDD, GND, SENSE

output_nodes: RESET


type: Memory

task: Design an SDRAM interface circuit using W9825G6KH with 16-bit data bus, address bus, control signals, and power supply decoupling.

input_nodes: VDD, GND, CLK, CKE, CS, RAS, CAS, WE, DQM, ADDR, DATA

output_nodes: DATA


type: HighSpeed

task: Design a PCIe x1 endpoint connector interface with differential TX/RX pairs, 100MHz reference clock, PERST# reset, and power rail connections with ESD protection.

input_nodes: REFCLK+, REFCLK-, PERST, 3V3, 12V, GND

output_nodes: PETp0, PETn0, PERp0, PERn0

components: Connector


task: Design a P-MOSFET reverse polarity protection circuit with gate voltage divider, TVS protection, and indicator LED.

input_nodes: VIN, GND

output_nodes: VOUT

components: PMOS, R, C


type: DigitalPower

task: Design a complete MCU digital synchronous buck system with STM32F103C8T6 MCU, two UCC5390E isolated gate drivers, two IMZA65R015M2H SiC MOSFETs, INA240A1 current sense, and SN65HVD230 CAN transceiver.


type: DigitalMotor

task: Design a complete MCU 3-phase inverter system with STM32F103C8T6 MCU, six UCC5390E isolated gate drivers, six IMZA65R015M2H SiC MOSFETs, three INA240A1 current sense amplifiers, three MGJ2D121505SC isolated gate supplies, SN65HVD230 CAN transceiver, and TPS54302 auxiliary supply.

output_nodes: VSW_A, VSW_B, VSW_C, CANH, CANL


type: Memory-System

task: Design an MCU SDRAM system with STM32F103C8T6 MCU, W9825G6KH SDRAM, and TLV1117-33 LDO for power supply with bus termination resistors.

input_nodes: VDD5, GND

output_nodes: GPIO, ADDR, DATA