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#include <bits/stdc++.h> using namespace std; const int mxn = 2e5 + 10; int sp[mxn], arr[mxn]; vector<int> required[mxn], bit[mxn]; int ask(int p, int x) { int idx = lower_bound(required[p].begin(), required[p].end(), x) - required[p].begin(); int ret = 0; while (idx > 0) ret = max(ret, bit[p][idx]), idx -= idx & -idx; return ret; } void update(int p, int x, int v) { int idx = lower_bound(required[p].begin(), required[p].end(), x) - required[p].begin() + 1; while (idx <= required[p].size()) bit[p][idx] = max(v, bit[p][idx]), idx += idx & -idx; } int main() { sp[1] = 1; for (int i = 2; i < mxn; i++) { if (sp[i]) continue; for (int j = i; j < mxn; j += i) sp[j] = sp[j] == 0 ? i : sp[j]; } int n, x, ret = 1; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &arr[i]), x = arr[i]; while (x != 1) { int p = sp[x]; while (p == sp[x]) x /= p; required[p].push_back(arr[i]); } } for (int i = 1; i < mxn; i++) { sort(required[i].begin(), required[i].end()); required[i].erase(unique(required[i].begin(), required[i].end()), required[i].end()); bit[i] = vector<int>(required[i].size() + 1, 0); } for (int i = 1; i <= n; i++) { x = arr[i]; int curr = 0; while (x != 1) { int p = sp[x]; while (p == sp[x]) x /= p; curr = max(curr, 1 + ask(p, arr[i])); } ret = max(ret, curr); x = arr[i]; while (x != 1) { int p = sp[x]; while (p == sp[x]) x /= p; update(p, arr[i], curr); } } printf( %d n , ret); }
|
#include <bits/stdc++.h> using namespace std; bool deb_mode = 0; class debugger { vector<string> vars; public: template <typename T> debugger &operator,(const T v) { stringstream ss; ss << v, vars.push_back(ss.str()); return *this; } void printall() { int j = 0, l = vars.size(); for (int i = 0; i < (l - 1); i++) { if (i) cout << , ; for (; j < vars[l - 1].size(); j++) { if (vars[l - 1][j] == , ) { j++; break; } cout << vars[l - 1][j]; } cout << = << vars[i]; } vars.clear(); } } Dbug; template <typename T1, typename T2> inline ostream &operator<<(ostream &os, const pair<T1, T2> &p) { return os << ( << p.first << , << p.second << ) ; } template <typename T> inline ostream &operator<<(ostream &os, const vector<T> &v) { bool first = true; os << { ; for (unsigned int i = 0; i < v.size(); i++) { if (!first) os << , ; os << v[i]; first = false; } return os << } ; } template <typename T> inline ostream &operator<<(ostream &os, const set<T> &v) { bool first = true; os << { ; for (typename set<T>::const_iterator ii = v.begin(); ii != v.end(); ++ii) { if (!first) os << , ; os << *ii; first = false; } return os << } ; } template <typename T1, typename T2> inline ostream &operator<<(ostream &os, const map<T1, T2> &v) { bool first = true; os << { ; for (typename map<T1, T2>::const_iterator ii = v.begin(); ii != v.end(); ++ii) { if (!first) os << , ; os << *ii; first = false; } return os << } ; } template <typename T> void getarray(T a[], int b, int e) { for (int i = b; i < e + b; i++) cin >> a[i]; } template <typename T> void printarray(T a[], int b, int e) { for (int i = b; i < e - 1 + b; i++) cout << a[i] << ; if (e - 1 + b >= 0) cout << a[e - 1 + b] << n ; } template <typename T> void printV(vector<T> v) { int sz = v.size(); if (sz) cout << v[0]; for (int i = 1; i < sz; i++) cout << << v[i]; printf( n ); } template <typename T> T gcd(T a, T b) { if (b == 0) return a; return gcd(b, a % b); } template <typename T> T BigMod(T b, T p, T m) { if (p == 0) return 1; if (p % 2 == 0) { T s = BigMod(b, p / 2, m); return ((s % m) * (s % m)) % m; } return ((b % m) * (BigMod(b, p - 1, m) % m)) % m; } template <typename T> T ModInv(T b, T m) { return BigMod(b, m - 2, m); } pair<long long int, pair<long long int, long long int> > ext_gcd( long long int a, long long int b) { if (b == 0) return make_pair(a, make_pair(1LL, 0LL)); pair<long long int, pair<long long int, long long int> > t = ext_gcd(b, a % b); return make_pair( t.first, make_pair(t.second.second, t.second.first - a / b * t.second.second)); } long long int ModInvNonPrimeM(long long int N, long long int M) { pair<long long int, pair<long long int, long long int> > r = ext_gcd(N, M); r.second.first %= M; if (r.second.first < 0) r.second.first += M; return r.second.first; } template <class T> inline void read(T &x) { bool Minus = 0; char c; for (c = getchar(); c <= 32; c = getchar()) ; if (c == - ) Minus = 1, c = getchar(); for (x = 0; c > 32; c = getchar()) x = x * 10 + c - 0 ; if (Minus) x = -x; } char getc() { char c; for (c = getchar(); c <= 32; c = getchar()) ; return c; } int CI(int &_x) { return scanf( %d , &_x); } int CI(int &_x, int &_y) { return scanf( %d %d , &_x, &_y); } int CI(int &_x, int &_y, int &_z) { return scanf( %d %d %d , &_x, &_y, &_z); } int CI(int &_a, int &_b, int &_c, int &_d) { return scanf( %d %d %d %d , &_a, &_b, &_c, &_d); } template <class T1, class T2> inline T1 UMAX(T1 &m, T2 other) { if (m < other) m = other; return m; } template <class T1, class T2> inline T1 UMIN(T1 &m, T2 other) { if (m > other) m = other; return m; } template <class T> string toString(T n) { ostringstream oss; oss << n; return oss.str(); } int toInt(string s) { int r = 0; istringstream sin(s); sin >> r; return r; } long long int toLong(string s) { long long int r = 0; istringstream sin(s); sin >> r; return r; } bool isVowel(char ch) { ch = tolower(ch); if (ch == a || ch == e || ch == i || ch == o || ch == u ) return true; return false; } bool isUpper(char c) { return c >= A && c <= Z ; } bool isLower(char c) { return c >= a && c <= z ; } int dr8[8] = {+1, -1, +0, +0, +1, -1, -1, +1}; int dc8[8] = {+0, +0, -1, +1, +1, +1, -1, -1}; int dr4[4] = {+0, +0, +1, -1}; int dc4[4] = {-1, +1, +0, +0}; int kn8r[8] = {+1, +2, +2, +1, -1, -2, -2, -1}; int kn8c[8] = {+2, +1, -1, -2, -2, -1, +1, +2}; const double EPS = 1e-9; const int INF = (1 << 30) - 1; const long long int LINF = (1ll << 62) - 1; const int mod = (int)1e9 + 7; const int MAX = (int)1e5; int N, M, X; int main() { if (deb_mode) srand(int(time(NULL))); int i, j, k, l, n, m, q, a, b, c; cin >> N >> M >> X; X--; if (N > M) { cout << 0 n ; return 0; } int DP[2][N + 5][N + 5]; memset(DP, 0, sizeof(DP)); DP[M & 1][N][0] = 1; int posNow, posPrev; for (int pos = M; pos >= 0; pos--) { posNow = pos & 1; posPrev = (pos - 1) & 1; for (i = 0; i < N + 1; i++) for (j = 0; j < N + 1; j++) DP[posPrev][i][j] = 0; for (int seg = 0; seg <= N; seg++) { for (int open = 0; open <= N; open++) { if (open) DP[posPrev][seg][open - 1] = (DP[posPrev][seg][open - 1] + DP[posNow][seg][open]) % mod; if (pos - 1 != X && seg) DP[posPrev][seg - 1][open + 1] = (DP[posPrev][seg - 1][open + 1] + DP[posNow][seg][open]) % mod; if (seg) DP[posPrev][seg - 1][open] = (DP[posPrev][seg - 1][open] + DP[posNow][seg][open]) % mod; if (pos - 1 != X) DP[posPrev][seg][open] = (DP[posPrev][seg][open] + DP[posNow][seg][open]) % mod; } } } long long int ANS = DP[posNow][0][0]; for (i = 1; i <= N; i++) ANS = (ANS * i) % mod; cout << ANS << n ; if (deb_mode) cerr << EXECUTION TIME = << (1.0 * clock()) / CLOCKS_PER_SEC << SECONDS n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__XNOR2_BLACKBOX_V
`define SKY130_FD_SC_HD__XNOR2_BLACKBOX_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__xnor2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__XNOR2_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, t; cin >> n >> t; long long arr[n]; for (int i = 0; i < n; i++) { cin >> arr[i]; } sort(arr, arr + n); float mxdif = INT_MIN; for (int i = 1; i < n; i++) { if (arr[i] - arr[i - 1] > mxdif) { mxdif = arr[i] - arr[i - 1]; } } double z = (mxdif + 0.000) / 2; double maxcnr = max(arr[0] - 0, t - arr[n - 1]); printf( %.9lf , max(z, maxcnr)); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long calc(int n, int k) { int c = n / k; long long ans = c; ans += (long long)(n - k) * c / 2; return ans; } int main() { int n; cin >> n; vector<long long> a; for (int i = 1; i * i <= n; i++) if (n % i == 0) { a.push_back(calc(n, i)); if (i * i != n) a.push_back(calc(n, n / i)); } sort(a.begin(), a.end()); a.erase(unique(a.begin(), a.end()), a.end()); for (long long first : a) printf( %I64d , first); return 0; }
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#include <bits/stdc++.h> #pragma comment(linker, /STACK:66777216 ) using namespace std; int inf = 1e9 + 7; long long INF = 1e18; int gcd(int a, int b) { return b ? gcd(b, a % b) : a; } int main() { ios_base::sync_with_stdio(false); int k; cin >> k; vector<long long> a; map<long long, pair<int, int> > sums; for (int i = 0; i < k; i++) { int n; long long sum = 0; cin >> n; a.resize(n); for (int j = 0; j < n; j++) { cin >> a[j]; sum += a[j]; } for (int j = 0; j < n; j++) { if (sums[sum - a[j]] != make_pair(0, 0) && sums[sum - a[j]].first != i + 1) { cout << YES << n ; cout << sums[sum - a[j]].first << << sums[sum - a[j]].second << n ; cout << i + 1 << << j + 1; return 0; } sums[sum - a[j]] = make_pair(i + 1, j + 1); } } cout << NO ; return 0; }
|
/*
* PicoSoC - A simple example SoC using PicoRV32
*
* Copyright (C) 2017 Clifford Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module top (
input clk,
output tx,
input rx,
input [15:0] sw,
output [15:0] led
);
wire clk_bufg;
BUFG bufg (
.I(clk),
.O(clk_bufg)
);
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
always @(posedge clk_bufg) begin
reset_cnt <= reset_cnt + !resetn;
end
wire iomem_valid;
reg iomem_ready;
wire [ 3:0] iomem_wstrb;
wire [31:0] iomem_addr;
wire [31:0] iomem_wdata;
reg [31:0] iomem_rdata;
reg [31:0] gpio;
assign led = gpio[15:0];
always @(posedge clk_bufg) begin
if (!resetn) begin
gpio <= 0;
end else begin
iomem_ready <= 0;
if (iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h03) begin
iomem_ready <= 1;
iomem_rdata <= {sw, gpio[15:0]};
if (iomem_wstrb[0]) gpio[7:0] <= iomem_wdata[7:0];
if (iomem_wstrb[1]) gpio[15:8] <= iomem_wdata[15:8];
if (iomem_wstrb[2]) gpio[23:16] <= iomem_wdata[23:16];
if (iomem_wstrb[3]) gpio[31:24] <= iomem_wdata[31:24];
end
end
end
picosoc_noflash soc (
.clk (clk_bufg),
.resetn(resetn),
.ser_tx(tx),
.ser_rx(rx),
.irq_5(1'b0),
.irq_6(1'b0),
.irq_7(1'b0),
.iomem_valid(iomem_valid),
.iomem_ready(iomem_ready),
.iomem_wstrb(iomem_wstrb),
.iomem_addr (iomem_addr),
.iomem_wdata(iomem_wdata),
.iomem_rdata(iomem_rdata)
);
endmodule
|
//-----------------------------------------------------------------------------
//-- Baudrate generator
//-- It generates a square signal, with a frequency for communicating at the given
//-- given baudrate
//-- The output is set to 1 only during one clock cycle. The rest of the time is 0
//-- Once enabled, the pulse is generated just in the middle of the period
//-- This is necessary for the implementation of the receptor
//--------------------------------------------------------------------------------
//-- (c) BQ. December 2015. written by Juan Gonzalez (obijuan)
//-----------------------------------------------------------------------------
//-- GPL license
//-----------------------------------------------------------------------------
`default_nettype none
`include "src/baudgen.vh"
//----------------------------------------------------------------------------------------
//-- baudgen module
//--
//-- INPUTS:
//-- -clk: System clock (12 MHZ in the iceStick board)
//-- -clk_ena: clock enable:
//-- 1. Normal working: The squeare signal is generated
//-- 0: stoped. Output always 0
//-- OUTPUTS:
//-- - clk_out: Output signal. Pulse width: 1 clock cycle. Output not registered
//-- It tells the uart_rx when to sample the next bit
//-- __ __
//-- ____________________| |________________________________________| |_____________________
//-- | -> <- 1 clock cycle |
//-- <------- Period ------------------------->
//--
//---------------------------------------------------------------------------------------
module baudgen_rx #(
parameter BAUDRATE = `B115200 //-- Default baudrate
)(
input wire rstn, //-- Reset (active low)
input wire clk, //-- System clock
input wire clk_ena, //-- Clock enable
output wire clk_out //-- Bitrate Clock output
);
//-- Number of bits needed for storing the baudrate divisor
`include "src/functions.vh"
localparam N = clog2(BAUDRATE);
//-- Value for generating the pulse in the middle of the period
localparam M2 = (BAUDRATE >> 1);
//-- Counter for implementing the divisor (it is a BAUDRATE module counter)
//-- (when BAUDRATE is reached, it start again from 0)
reg [N-1:0] divcounter = 0;
//-- Contador módulo M
always @(posedge clk or negedge rstn)
if (!rstn)
divcounter <= 0;
else if (clk_ena)
//-- Normal working: counting. When the maximum count is reached, it starts from 0
divcounter <= (divcounter == BAUDRATE - 1) ? 0 : divcounter + 1;
else
//-- Counter fixed to its maximum value
//-- When it is resumed it start from 0
divcounter <= BAUDRATE - 1;
//-- The output is 1 when the counter is in the middle of the period, if clk_ena is active
//-- It is 1 only for one system clock cycle
assign clk_out = (divcounter == M2) ? clk_ena : 0;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t = 1; cin >> t; while (t--) { int n; cin >> n; if (n == 2) { cout << 2 n1 2 n ; continue; } vector<pair<int, int>> ans; int cur = n; for (int i = n - 1; i >= 1; --i) { ans.push_back(make_pair(i, cur)); cur = (cur + i + 1) / 2; } cout << cur << n ; for (auto i : ans) cout << i.first << << i.second << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 105; vector<int> adj[N]; int a[N], d[N], din[N]; int main() { int n; scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d %d , a + i, d + i); for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (i == j) continue; if (d[i] < 0) { if (make_pair(a[i], -i) > make_pair(a[j], -j) && make_pair(a[j], -j) > make_pair(a[i] + d[i], -i) && make_pair(a[i] + d[i], -i) > make_pair(a[j] + d[j], -j)) adj[i].push_back(j); } else { if (make_pair(a[i], -i) < make_pair(a[j], -j) && make_pair(a[j], -j) < make_pair(a[i] + d[i], -i) && make_pair(a[i] + d[i], -i) < make_pair(a[j] + d[j], -j)) adj[i].push_back(j); } } } memset(din, 0, sizeof din); for (int i = 0; i < n; i++) { for (int u : adj[i]) din[u]++; } stack<int> st; for (int i = 0; i < n; i++) if (din[i] == 0) { st.push(i); } vector<int> order; while (!st.empty()) { int u = st.top(); st.pop(); order.push_back(u); for (int v : adj[u]) { din[v]--; if (din[v] == 0) st.push(v); } } int ans = 0; for (int i = 0; i < n; i++) { int cnt1, cnt2; cnt1 = cnt2 = 0; for (int j = 0; j < n; j++) { if (j == order[i]) continue; cnt1 += (make_pair(a[j], -j) < make_pair(a[order[i]], -order[i])); cnt2 += (make_pair(a[j], -j) < make_pair(a[order[i]] + d[order[i]], -order[i])); } ans += abs(cnt1 - cnt2); a[order[i]] += d[order[i]]; } printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, k; bool check(int x) { int s[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; int t; while (x > 0) { t = x % 10; if (t <= k) s[t]++; x /= 10; } for (int i = 0; i <= k; i++) { if (s[i] == 0) return false; } return true; } int main() { cin >> n >> k; int res = 0; int t; for (int i = 0; i < n; i++) { cin >> t; if (check(t)) res++; } cout << res; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR4_2_V
`define SKY130_FD_SC_LS__NOR4_2_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog wrapper for nor4 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nor4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nor4_2 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nor4_2 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR4_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2BB2O_1_V
`define SKY130_FD_SC_MS__A2BB2O_1_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog wrapper for a2bb2o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a2bb2o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a2bb2o_1 (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a2bb2o_1 (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2BB2O_1_V
|
#include <bits/stdc++.h> using namespace std; int fact(int a) { int res = 1; while (a > 0) { res *= a--; } return res; } int main() { int a, b; cin >> a >> b; cout << fact(min(a, b)); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDLCLKP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__SDLCLKP_FUNCTIONAL_PP_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hd__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__sdlclkp (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire m0 ;
wire m0n ;
wire clkn ;
wire SCE_GATE;
// Name Output Other arguments
not not0 (m0n , m0 );
not not1 (clkn , CLK );
nor nor0 (SCE_GATE, GATE, SCE );
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , SCE_GATE, clkn, , VPWR, VGND);
and and0 (GCLK , m0n, CLK );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDLCLKP_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> static const int MAXN = 50004; static const int MAXE = 100004 * 2; static const int MAXL = 20; static const int MAXT = 1000005; int n, e; int head[MAXN], dest[MAXE], next[MAXE]; int l[MAXN], t[MAXN][MAXL]; int T = 0; int p[MAXN]; int conf[MAXN], team[MAXN]; int team_conf[MAXT]; inline void add_edge(int u, int v) { static int w = 0; dest[w] = v; next[w] = head[u]; head[u] = w++; } int main() { scanf( %d%d , &n, &e); for (int i = 0; i < n; ++i) head[i] = -1; int u, v; for (int i = 0; i < e; ++i) { scanf( %d%d , &u, &v); --u, --v; add_edge(u, v); add_edge(v, u); } for (int i = 0; i < n; ++i) { scanf( %d , &l[i]); for (int j = 0; j < l[i]; ++j) { scanf( %d , &t[i][j]); --t[i][j]; T = std::max(T, t[i][j]); } } ++T; srand(87665544); for (int i = 0; i < n; ++i) p[i] = i; for (int attempts = 0;; ++attempts) { if (attempts % 16 == 0) { std::random_shuffle(p, p + n); std::fill(conf, conf + n, -1); int ct[2]; for (int i = 0; i < n; ++i) { ct[0] = ct[1] = 0; for (int w = head[p[i]]; w != -1; w = next[w]) { if (conf[dest[w]] != -1) ++ct[conf[dest[w]]]; } conf[p[i]] = (ct[0] > ct[1] ? 1 : 0); } } for (int i = 0; i < T; ++i) team_conf[i] = rand() % 2; bool valid = true; for (int i = 0; i < n; ++i) { team[i] = -1; for (int j = 0; j < l[i]; ++j) if (conf[i] == team_conf[t[i][j]]) { team[i] = t[i][j]; break; } if (team[i] == -1) { valid = false; break; } } if (!valid) continue; for (int i = 0; i < n; ++i) printf( %d%c , team[i] + 1, i == n - 1 ? n : ); for (int i = 0; i < T; ++i) printf( %d%c , team_conf[i] + 1, i == T - 1 ? n : ); break; } return 0; }
|
//
// Copyright (c) 1999 Thomas Coonan ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
module idec (
inst,
aluasel,
alubsel,
aluop,
wwe,
fwe,
zwe,
cwe,
bdpol,
option,
tris
);
input [11:0] inst;
output [1:0] aluasel;
output [1:0] alubsel;
output [3:0] aluop;
output wwe;
output fwe;
output zwe;
output cwe;
output bdpol;
output option;
output tris;
reg [14:0] decodes;
// For reference, the ALU Op codes are:
//
// ADD 0000
// SUB 1000
// AND 0001
// OR 0010
// XOR 0011
// COM 0100
// ROR 0101
// ROL 0110
// SWAP 0111
assign { aluasel, // Select source for ALU A input. 00=W, 01=SBUS, 10=K, 11=BD
alubsel, // Select source for ALU B input. 00=W, 01=SBUS, 10=K, 11="1"
aluop, // ALU Operation (see comments above for these codes)
wwe, // W register Write Enable
fwe, // File Register Write Enable
zwe, // Status register Z bit update
cwe, // Status register Z bit update
bdpol, // Polarity on bit decode vector (0=no inversion, 1=invert)
tris, // Instruction is an TRIS instruction
option // Instruction is an OPTION instruction
} = decodes;
// This is a large combinatorial decoder.
// I use the casex statement.
always @(inst) begin
casex (inst) // synopsys parallel_case
// *** Byte-Oriented File Register Operations
//
// A A ALU W F Z C B T O
// L L O W W W W D R P
// U U P E E E E P I T
// A B O S
// L
12'b0000_0000_0000: decodes = 15'b00_00_0000_0_0_0_0_0_0_0; // NOP
12'b0000_001X_XXXX: decodes = 15'b00_00_0010_0_1_0_0_0_0_0; // MOVWF
12'b0000_0100_0000: decodes = 15'b00_00_0011_1_0_1_0_0_0_0; // CLRW
12'b0000_011X_XXXX: decodes = 15'b00_00_0011_0_1_1_0_0_0_0; // CLRF
12'b0000_100X_XXXX: decodes = 15'b01_00_1000_1_0_1_1_0_0_0; // SUBWF (d=0)
12'b0000_101X_XXXX: decodes = 15'b01_00_1000_0_1_1_1_0_0_0; // SUBWF (d=1)
12'b0000_110X_XXXX: decodes = 15'b01_11_1000_1_0_1_0_0_0_0; // DECF (d=0)
12'b0000_111X_XXXX: decodes = 15'b01_11_1000_0_1_1_0_0_0_0; // DECF (d=1)
12'b0001_000X_XXXX: decodes = 15'b00_01_0010_1_0_1_0_0_0_0; // IORWF (d=0)
12'b0001_001X_XXXX: decodes = 15'b00_01_0010_0_1_1_0_0_0_0; // IORWF (d=1)
12'b0001_010X_XXXX: decodes = 15'b00_01_0001_1_0_1_0_0_0_0; // ANDWF (d=0)
12'b0001_011X_XXXX: decodes = 15'b00_01_0001_0_1_1_0_0_0_0; // ANDWF (d=1)
12'b0001_100X_XXXX: decodes = 15'b00_01_0011_1_0_1_0_0_0_0; // XORWF (d=0)
12'b0001_101X_XXXX: decodes = 15'b00_01_0011_0_1_1_0_0_0_0; // XORWF (d=1)
12'b0001_110X_XXXX: decodes = 15'b00_01_0000_1_0_1_1_0_0_0; // ADDWF (d=0)
12'b0001_111X_XXXX: decodes = 15'b00_01_0000_0_1_1_1_0_0_0; // ADDWF (d=1)
12'b0010_000X_XXXX: decodes = 15'b01_01_0010_1_0_1_0_0_0_0; // MOVF (d=0)
12'b0010_001X_XXXX: decodes = 15'b01_01_0010_0_1_1_0_0_0_0; // MOVF (d=1)
12'b0010_010X_XXXX: decodes = 15'b01_01_0100_1_0_1_0_0_0_0; // COMF (d=0)
12'b0010_011X_XXXX: decodes = 15'b01_01_0100_0_1_1_0_0_0_0; // COMF (d=1)
12'b0010_100X_XXXX: decodes = 15'b01_11_0000_1_0_1_0_0_0_0; // INCF (d=0)
12'b0010_101X_XXXX: decodes = 15'b01_11_0000_0_1_1_0_0_0_0; // INCF (d=1)
12'b0010_110X_XXXX: decodes = 15'b01_11_1000_1_0_0_0_0_0_0; // DECFSZ(d=0)
12'b0010_111X_XXXX: decodes = 15'b01_11_1000_0_1_0_0_0_0_0; // DECFSZ(d=1)
12'b0011_000X_XXXX: decodes = 15'b01_01_0101_1_0_0_1_0_0_0; // RRF (d=0)
12'b0011_001X_XXXX: decodes = 15'b01_01_0101_0_1_0_1_0_0_0; // RRF (d=1)
12'b0011_010X_XXXX: decodes = 15'b01_01_0110_1_0_0_1_0_0_0; // RLF (d=0)
12'b0011_011X_XXXX: decodes = 15'b01_01_0110_0_1_0_1_0_0_0; // RLF (d=1)
12'b0011_100X_XXXX: decodes = 15'b01_01_0111_1_0_0_0_0_0_0; // SWAPF (d=0)
12'b0011_101X_XXXX: decodes = 15'b01_01_0111_0_1_0_0_0_0_0; // SWAPF (d=1)
12'b0011_110X_XXXX: decodes = 15'b01_11_0000_1_0_0_0_0_0_0; // INCFSZ(d=0)
12'b0011_111X_XXXX: decodes = 15'b01_11_0000_0_1_0_0_0_0_0; // INCFSZ(d=1)
// *** Bit-Oriented File Register Operations
//
// A A ALU W F Z C B T O
// L L O W W W W D R P
// U U P E E E E P I T
// A B O S
// L
12'b0100_XXXX_XXXX: decodes = 15'b11_01_0001_0_1_0_0_1_0_0; // BCF
12'b0101_XXXX_XXXX: decodes = 15'b11_01_0010_0_1_0_0_0_0_0; // BSF
12'b0110_XXXX_XXXX: decodes = 15'b11_01_0001_0_0_0_0_0_0_0; // BTFSC
12'b0111_XXXX_XXXX: decodes = 15'b11_01_0001_0_0_0_0_0_0_0; // BTFSS
// *** Literal and Control Operations
//
// A A ALU W F Z C B T O
// L L O W W W W D R P
// U U P E E E E P I T
// A B O S
// L
12'b0000_0000_0010: decodes = 15'b00_00_0010_0_1_0_0_0_0_1; // OPTION
12'b0000_0000_0011: decodes = 15'b00_00_0000_0_0_0_0_0_0_0; // SLEEP
12'b0000_0000_0100: decodes = 15'b00_00_0000_0_0_0_0_0_0_0; // CLRWDT
12'b0000_0000_0101: decodes = 15'b00_00_0000_0_1_0_0_0_1_0; // TRIS 5
12'b0000_0000_0110: decodes = 15'b00_00_0010_0_1_0_0_0_1_0; // TRIS 6
12'b0000_0000_0111: decodes = 15'b00_00_0010_0_1_0_0_0_1_0; // TRIS 7
//
// A A ALU W F Z C B T O
// L L O W W W W D R P
// U U P E E E E P I T
// A B O S
// L
12'b1000_XXXX_XXXX: decodes = 15'b10_10_0010_1_0_0_0_0_0_0; // RETLW
12'b1001_XXXX_XXXX: decodes = 15'b10_10_0010_0_0_0_0_0_0_0; // CALL
12'b101X_XXXX_XXXX: decodes = 15'b10_10_0010_0_0_0_0_0_0_0; // GOTO
12'b1100_XXXX_XXXX: decodes = 15'b10_10_0010_1_0_0_0_0_0_0; // MOVLW
12'b1101_XXXX_XXXX: decodes = 15'b00_10_0010_1_0_1_0_0_0_0; // IORLW
12'b1110_XXXX_XXXX: decodes = 15'b00_10_0001_1_0_1_0_0_0_0; // ANDLW
12'b1111_XXXX_XXXX: decodes = 15'b00_10_0011_1_0_1_0_0_0_0; // XORLW
default:
decodes = 15'b00_00_0000_0_0_0_0_0_0_0;
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLXTN_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__DLXTN_PP_BLACKBOX_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlxtn (
Q ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLXTN_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAP_1_V
`define SKY130_FD_SC_HS__TAP_1_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog wrapper for tap with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__tap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__tap_1 (
VPWR,
VGND
);
input VPWR;
input VGND;
sky130_fd_sc_hs__tap base (
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__tap_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__tap base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAP_1_V
|
#include <bits/stdc++.h> using namespace std; int main() { int k, n; scanf( %d%d , &n, &k); vector<int> a(n), b(n), distributed(n), p(n); vector<vector<int> > cart(k); for (int i = 0; i < n; ++i) { scanf( %d%d , &a[i], &b[i]); distributed[i] = 0; p[i] = i; } for (int i = 0; i < n; ++i) { for (int j = i + 1; j < n; ++j) { if (a[p[i]] < a[p[j]]) { swap(p[i], p[j]); } } } int cart_ptr = 0; for (int i = 0; i < n && cart_ptr < k; ++i) { if (b[p[i]] == 1) { distributed[p[i]] = 1; cart[cart_ptr].push_back(p[i]); ++cart_ptr; } } deque<int> available; for (int i = 0; i < n; ++i) { if (!distributed[p[i]]) { available.push_back(p[i]); } } while (cart_ptr < k) { cart[cart_ptr].push_back(available.front()); available.pop_front(); ++cart_ptr; } while (!available.empty()) { cart[k - 1].push_back(available.front()); available.pop_front(); } long long ans = 0; for (int i = 0; i < k; ++i) { int min_cost = 2000000000; for (int j = 0; j < (int)cart[i].size(); ++j) { ans += a[cart[i][j]] * 2; min_cost = min(min_cost, a[cart[i][j]]); } if (b[cart[i][0]] == 1) { ans -= min_cost; } } cout << ans / 2; if (ans % 2 == 0) { cout << .0 << endl; } else { cout << .5 << endl; } for (int i = 0; i < k; ++i) { cout << cart[i].size(); for (int j = 0; j < (int)cart[i].size(); ++j) { cout << << cart[i][j] + 1; } cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int pow_mod(long long int a, long long int b) { long long int res = 1; while (b != 0) { if (b & 1) { res = (res * a) % 1000000007; } a = (a * a) % 1000000007; b /= 2; } return res; } void solve() { long long int n, m, k; cin >> n >> m >> k; long long int a[n + 1][m]; for (long long int i = 0; i < n; i++) { for (long long int j = 0; j < m; j++) cin >> a[i][j]; } for (long long int j = 0; j < m; j++) a[n][j] = 0; long long int dp[n + 1][m]; memset(dp, 0, sizeof(dp)); long long int sum[n + 1][m], mx_p[n + 1][m], mx_s[n + 1][m]; memset(sum, 0, sizeof(sum)); memset(mx_s, 0, sizeof(mx_s)); memset(mx_p, 0, sizeof(mx_p)); for (long long int i = 0; i <= n; i++) { for (long long int j = 0; j < m; j++) { if (j == 0) sum[i][j] = a[i][j]; else sum[i][j] = a[i][j] + sum[i][j - 1]; } } for (long long int i = 1; i <= n; i++) { for (long long int j = 0; j < m; j++) { if (j - k + 1 >= 0) { if (i == 0) { dp[i][j] = sum[i][j] - (j - k >= 0 ? sum[i][j - k] : 0LL); } else { dp[i][j] = sum[i][j] - (j - k >= 0 ? sum[i][j - k] : 0LL); dp[i][j] += sum[i - 1][j] - (j - k >= 0 ? sum[i - 1][j - k] : 0LL); if (i != 1) { long long int res = 0; if (j + k < m) res = mx_s[i - 1][j + k]; if (j - k >= 0) res = max(res, mx_p[i - 1][j - k]); for (long long int xx = j; xx > max(-1LL, j - k); xx--) res = max(res, dp[i - 1][xx] - sum[i - 1][xx] + (j - k >= 0 ? sum[i - 1][j - k] : 0LL)); for (long long int xx = j + 1; xx < min(m, j + k); xx++) res = max(res, dp[i - 1][xx] - sum[i - 1][j] + (xx - k >= 0 ? sum[i - 1][xx - k] : 0LL)); dp[i][j] += res; } } mx_p[i][j] = dp[i][j]; if (j - 1 >= 0) mx_p[i][j] = max(mx_p[i][j], mx_p[i][j - 1]); } } for (long long int j = m - 1; j >= 0; j--) { if (j == m - 1) mx_s[i][j] = dp[i][j]; else mx_s[i][j] = max(mx_s[i][j + 1], dp[i][j]); } } long long int ans = 0; for (long long int j = 0; j < m; j++) { ans = max(ans, dp[n][j]); } cout << ans << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int t; t = 1; while (t--) solve(); return 0; }
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
// Designer : Bob Hu
//
// Description:
// This module to implement the CSR instructions
//
//
// ====================================================================
`include "e203_defines.v"
module e203_exu_alu_csrctrl(
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The Handshake Interface
//
input csr_i_valid, // Handshake valid
output csr_i_ready, // Handshake ready
input [`E203_XLEN-1:0] csr_i_rs1,
input [`E203_DECINFO_CSR_WIDTH-1:0] csr_i_info,
input csr_i_rdwen,
output csr_ena,
output csr_wr_en,
output csr_rd_en,
output [12-1:0] csr_idx,
input csr_access_ilgl,
input [`E203_XLEN-1:0] read_csr_dat,
output [`E203_XLEN-1:0] wbck_csr_dat,
`ifdef E203_HAS_CSR_EAI//{
output csr_sel_eai,
input eai_xs_off,
output eai_csr_valid,
input eai_csr_ready,
output [31:0] eai_csr_addr,
output eai_csr_wr,
output [31:0] eai_csr_wdata,
input [31:0] eai_csr_rdata,
`endif//}
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The CSR Write-back/Commit Interface
output csr_o_valid, // Handshake valid
input csr_o_ready, // Handshake ready
// The Write-Back Interface for Special (unaligned ldst and AMO instructions)
output [`E203_XLEN-1:0] csr_o_wbck_wdat,
output csr_o_wbck_err,
input clk,
input rst_n
);
`ifdef E203_HAS_CSR_EAI//{
// If accessed the EAI CSR range then we need to check if the EAI CSR is ready
assign csr_sel_eai = (csr_idx[11:8] == 4'hE);
wire sel_eai = csr_sel_eai & (~eai_xs_off);
wire addi_condi = sel_eai ? eai_csr_ready : 1'b1;
assign csr_o_valid = csr_i_valid
& addi_condi; // Need to make sure the eai_csr-ready is ready to make sure
// it can be sent to EAI and O interface same cycle
assign eai_csr_valid = sel_eai & csr_i_valid &
csr_o_ready;// Need to make sure the o-ready is ready to make sure
// it can be sent to EAI and O interface same cycle
assign csr_i_ready = sel_eai ? (eai_csr_ready & csr_o_ready) : csr_o_ready;
assign csr_o_wbck_err = csr_access_ilgl;
assign csr_o_wbck_wdat = sel_eai ? eai_csr_rdata : read_csr_dat;
assign eai_csr_addr = csr_idx;
assign eai_csr_wr = csr_wr_en;
assign eai_csr_wdata = wbck_csr_dat;
`else//}{
assign sel_eai = 1'b0;
assign csr_o_valid = csr_i_valid;
assign csr_i_ready = csr_o_ready;
assign csr_o_wbck_err = csr_access_ilgl;
assign csr_o_wbck_wdat = read_csr_dat;
`endif//}
wire csrrw = csr_i_info[`E203_DECINFO_CSR_CSRRW ];
wire csrrs = csr_i_info[`E203_DECINFO_CSR_CSRRS ];
wire csrrc = csr_i_info[`E203_DECINFO_CSR_CSRRC ];
wire rs1imm = csr_i_info[`E203_DECINFO_CSR_RS1IMM];
wire rs1is0 = csr_i_info[`E203_DECINFO_CSR_RS1IS0];
wire [4:0] zimm = csr_i_info[`E203_DECINFO_CSR_ZIMMM ];
wire [11:0] csridx = csr_i_info[`E203_DECINFO_CSR_CSRIDX];
wire [`E203_XLEN-1:0] csr_op1 = rs1imm ? {27'b0,zimm} : csr_i_rs1;
assign csr_rd_en = csr_i_valid &
(
(csrrw ? csr_i_rdwen : 1'b0) // the CSRRW only read when the destination reg need to be writen
| csrrs | csrrc // The set and clear operation always need to read CSR
);
assign csr_wr_en = csr_i_valid & (
csrrw // CSRRW always write the original RS1 value into the CSR
| ((csrrs | csrrc) & (~rs1is0)) // for CSRRS/RC, if the RS is x0, then should not really write
);
assign csr_idx = csridx;
assign csr_ena = csr_o_valid & csr_o_ready & (~sel_eai);
assign wbck_csr_dat =
({`E203_XLEN{csrrw}} & csr_op1)
| ({`E203_XLEN{csrrs}} & ( csr_op1 | read_csr_dat))
| ({`E203_XLEN{csrrc}} & ((~csr_op1) & read_csr_dat));
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n; struct mat { long long** val; mat() { val = new long long*[6]; for (int i = 0; i < 6; i++) { val[i] = new long long[6]; for (int j = 0; j < 6; j++) val[i][j] = 0; val[i][i] = 1; } } mat(long long v[6][6]) { val = new long long*[6]; for (int i = 0; i < 6; i++) { val[i] = new long long[6]; for (int j = 0; j < 6; j++) val[i][j] = v[i][j]; } } mat operator*(const mat& b) { mat ans; for (int i = 0; i < 6; i++) { for (int j = 0; j < 6; j++) { ans.val[i][j] = 0; for (int k = 0; k < 6; k++) { ans.val[i][j] += (val[i][k] * b.val[k][j]) % n; ans.val[i][j] %= n; } } } return ans; } mat& operator=(const mat& b) { for (int i = 0; i < 6; i++) { for (int j = 0; j < 6; j++) val[i][j] = b.val[i][j]; } return *this; } }; long long rec[6][6] = {{2, 1, 1, 0, 1, 2}, {1, 2, 0, 1, 1, 2}, {1, 1, 1, 0, 1, 2}, {1, 1, 0, 1, 1, 2}, {0, 0, 0, 0, 1, 1}, {0, 0, 0, 0, 0, 1}}; mat matrec; mat matexp(long long e) { if (e == 0ll) return mat(); mat tmp = matexp(e / 2ll); tmp = (tmp * tmp); if (e & 1) return tmp * matrec; return tmp; } int main() { ios::sync_with_stdio(0); matrec = mat(rec); long long sx, sy, dx, dy, t; cin >> n >> sx >> sy >> dx >> dy >> t; if (t == 0ll) { cout << sx << << sy << n ; return 0; } sx--; sy--; dx %= n; dy %= n; while (dx < 0) dx += n; while (dy < 0) dy += n; long long vec[] = {sx, sy, dx, dy, 0, 1}; mat ans = matexp(t); long long ansx = 0, ansy = 0; for (int i = 0; i < 6; i++) { ansx += (vec[i] * ans.val[0][i]) % n; ansy += (vec[i] * ans.val[1][i]) % n; ansx %= n; ansy %= n; } cout << ansx + 1 << << ansy + 1 << n ; return 0; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_sysref_gen (
input core_clk,
input sysref_en,
output reg sysref_out
);
// SYSREF period is multiple of core_clk, and has a duty cycle of 50%
// NOTE: if SYSREF always on (this is a JESD204 IP configuration),
// the period must be a correct multiple of the multiframe period
parameter SYSREF_PERIOD = 128;
localparam SYSREF_HALFPERIOD = SYSREF_PERIOD/2 - 1;
reg [ 7:0] counter;
reg sysref_en_m1;
reg sysref_en_m2;
reg sysref_en_int;
// bring the enable signal to JESD core clock domain
always @(posedge core_clk) begin
sysref_en_m1 <= sysref_en;
sysref_en_m2 <= sysref_en_m1;
sysref_en_int <= sysref_en_m2;
end
// free running counter for periodic SYSREF generation
always @(posedge core_clk) begin
if (sysref_en_int) begin
counter <= (counter < SYSREF_HALFPERIOD) ? counter + 1'b1 : 8'h0;
end else begin
counter <= 8'h0;
end
end
// generate SYSREF
always @(posedge core_clk) begin
if (sysref_en_int) begin
if (counter == SYSREF_HALFPERIOD) begin
sysref_out <= ~sysref_out;
end
end else begin
sysref_out <= 1'b0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; string a, ans; int b; string c; int main() { while (cin >> a >> b) { for (int i = 0; i < a.size(); i++) if (a[i] >= A && a[i] <= Z ) a[i] = a[i] - A + a ; for (int i = 0; i < a.size(); i++) { if ((int)a[i] < b + 97) { a[i] = a[i] - a + A ; } } cout << a << endl; } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 28.06.2017 17:24:09
// Design Name:
// Module Name: dmem
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module dmem(
output [31:0] RD,
input [31:0] A, WD,
input WE, clk
);
reg [31:0] RAM [0:255];
assign RD = (A != 0) ? RAM[A[7:0]] : 0;
always @ (posedge clk)
if (WE)
RAM[A[7:0]] <= WD;
// when a 32 bit number is sent to the address field, this is the calculated
// address from the ALU. Meaning that the instruction is for "lw" or "sw".
// Another indicator for this is when the signal "MemWrite" is 1.
// All other times, "MemWrite" is 0, and the ALUResult that is sent to A
// is ignored.
endmodule
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010, 2011 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`define AUTO_ON
module standby(
input clk50,
input btn1,
input btn2,
input btn3,
output led1,
output led2,
output flash_ce_n,
output flash_oe_n,
output flash_we_n,
output flash_rst_n,
output sdram_clk_p,
output sdram_clk_n,
output vga_psave_n,
output vga_clk,
output mc_clk,
output ac97_rst_n,
output usba_oe_n,
output usbb_oe_n,
output phy_rst_n,
output videoin_rst_n,
output midi_tx,
output dmxa_de,
output dmxb_de
);
wire clk;
wire clk_dcm;
wire locked;
DCM_SP #(
.CLKDV_DIVIDE(2.0), // 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
.CLKFX_DIVIDE(8), // 1 to 32
.CLKFX_MULTIPLY(2), // 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(20.0),
.CLKOUT_PHASE_SHIFT("NONE"),
.CLK_FEEDBACK("NONE"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
.DUTY_CYCLE_CORRECTION("TRUE"),
.PHASE_SHIFT(0),
.STARTUP_WAIT("FALSE")
) clkgen (
.CLK0(),
.CLK90(),
.CLK180(),
.CLK270(),
.CLK2X(),
.CLK2X180(),
.CLKDV(),
.CLKFX(clk_dcm),
.CLKFX180(),
.LOCKED(locked),
.CLKFB(),
.CLKIN(clk50),
.RST(1'b0),
.PSEN(1'b0)
);
BUFG b1(
.I(clk_dcm),
.O(clk)
);
`ifndef AUTO_ON
reg btn1_r0;
reg btn1_r;
reg btn2_r0;
reg btn2_r;
reg btn2_r2;
wire debounce;
always @(posedge clk) begin
if(debounce) begin
btn1_r0 <= btn1;
btn1_r <= btn1_r0;
btn2_r0 <= btn2;
btn2_r <= btn2_r0;
btn2_r2 <= btn2_r;
end
end
initial begin
btn2_r0 <= 1'b1;
btn2_r <= 1'b1;
btn2_r2 <= 1'b1;
end
reg [19:0] debounce_r;
always @(posedge clk) debounce_r <= debounce_r + 20'd1;
assign debounce = &debounce_r;
`endif
reg ce_r;
reg [15:0] d_r;
reg write_r;
ICAP_SPARTAN6 icap(
.BUSY(),
.O(),
.CE(ce_r),
.CLK(clk),
.I(d_r),
.WRITE(write_r)
);
reg [15:0] d;
reg icap_en_n;
always @(posedge clk, negedge locked) begin
if(~locked) begin
d_r <= 16'hffff;
ce_r <= 1'b1;
write_r <= 1'b1;
end else begin
d_r[0] <= d[7];
d_r[1] <= d[6];
d_r[2] <= d[5];
d_r[3] <= d[4];
d_r[4] <= d[3];
d_r[5] <= d[2];
d_r[6] <= d[1];
d_r[7] <= d[0];
d_r[8] <= d[15];
d_r[9] <= d[14];
d_r[10] <= d[13];
d_r[11] <= d[12];
d_r[12] <= d[11];
d_r[13] <= d[10];
d_r[14] <= d[9];
d_r[15] <= d[8];
ce_r <= icap_en_n;
write_r <= icap_en_n;
end
end
parameter IDLE = 4'd0;
parameter DUMMY = 4'd1;
parameter SYNC1 = 4'd2;
parameter SYNC2 = 4'd3;
parameter GENERAL1_C = 4'd4;
parameter GENERAL1_D = 4'd5;
parameter GENERAL2_C = 4'd6;
parameter GENERAL2_D_RESCUE = 4'd7;
parameter GENERAL2_D_REGULAR = 4'd8;
parameter CMD = 4'd9;
parameter IPROG = 4'd10;
parameter NOP = 4'd11;
parameter LOOP = 4'd12;
reg [3:0] state;
reg [3:0] next_state;
initial state <= IDLE;
always @(posedge clk, negedge locked)
if(~locked)
state <= IDLE;
else
state <= next_state;
`ifndef AUTO_ON
reg rescue;
reg next_rescue;
always @(posedge clk, negedge locked)
if(~locked)
rescue <= 1'b0;
else
rescue <= next_rescue;
`endif
`ifdef AUTO_ON
/* HACK: for some reason, reconfiguring right away fails intermittently.
* Work around this with a timer.
*/
reg [19:0] timer;
always @(posedge clk, negedge locked)
if(~locked)
timer <= 20'd0;
else
timer <= timer + 20'd1;
`endif
always @(*) begin
d = 16'hxxxx;
icap_en_n = 1'b1;
`ifndef AUTO_ON
next_rescue = rescue;
`endif
next_state = state;
case(state)
IDLE: begin
`ifdef AUTO_ON
if(timer[19])
next_state = DUMMY;
`else
next_rescue = btn1_r;
if(btn2_r & ~btn2_r2)
next_state = DUMMY;
`endif
end
DUMMY: begin
d = 16'hffff;
icap_en_n = 1'b0;
next_state = SYNC1;
end
SYNC1: begin
d = 16'haa99;
icap_en_n = 1'b0;
next_state = SYNC2;
end
SYNC2: begin
d = 16'h5566;
icap_en_n = 1'b0;
next_state = GENERAL1_C;
end
GENERAL1_C: begin
d = 16'h3261;
icap_en_n = 1'b0;
next_state = GENERAL1_D;
end
GENERAL1_D: begin
d = 16'h0000;
icap_en_n = 1'b0;
next_state = GENERAL2_C;
end
GENERAL2_C: begin
d = 16'h3281;
icap_en_n = 1'b0;
`ifdef AUTO_ON
if(btn1)
`else
if(rescue)
`endif
next_state = GENERAL2_D_RESCUE;
else
next_state = GENERAL2_D_REGULAR;
end
GENERAL2_D_RESCUE: begin
d = 16'h0005;
icap_en_n = 1'b0;
next_state = CMD;
end
GENERAL2_D_REGULAR: begin
d = 16'h0037;
icap_en_n = 1'b0;
next_state = CMD;
end
CMD: begin
d = 16'h30A1;
icap_en_n = 1'b0;
next_state = IPROG;
end
IPROG: begin
d = 16'h000E;
icap_en_n = 1'b0;
next_state = NOP;
end
NOP: begin
d = 16'h2000;
icap_en_n = 1'b0;
next_state = LOOP;
end
LOOP: next_state = LOOP;
endcase
end
assign led1 = 1'b0;
assign led2 = 1'b0;
assign flash_ce_n = 1'b1;
assign flash_oe_n = 1'b1;
assign flash_we_n = 1'b1;
assign flash_rst_n = 1'b1;
assign sdram_clk_p = 1'b0;
assign sdram_clk_n = 1'b1;
assign vga_psave_n = 1'b0;
assign vga_clk = 1'b0;
assign mc_clk = 1'b0;
assign ac97_rst_n = 1'b0;
assign usba_oe_n = 1'b1;
assign usbb_oe_n = 1'b1;
assign phy_rst_n = 1'b0;
assign videoin_rst_n = 1'b0;
assign midi_tx = 1'b1;
assign dmxa_de = 1'b0;
assign dmxb_de = 1'b0;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long a[101000]; long long pre[101000]; map<long long, long long> Hash; int main() { int n, k; scanf( %d%d , &n, &k); for (int i = 1; i <= n; i++) scanf( %I64d , &a[i]); for (int i = 1; i <= n; i++) pre[i] = pre[i - 1] + a[i]; Hash[0] = 1; long long count = 0; for (int i = 1; i <= n; i++) { if (abs(k) > 1) { for (long long p = 1; (p > 0 ? p : -p) <= 1e15; p *= k) { if (Hash[pre[i] - p]) count += Hash[pre[i] - p]; } } else { if (k == 1 || k == -1) { if (Hash[pre[i] - 1]) count += Hash[pre[i] - 1]; if (k == -1) { if (Hash[pre[i] + 1]) count += Hash[pre[i] + 1]; } } else { if (Hash[pre[i]]) count += Hash[pre[i]]; } } Hash[pre[i]] += 1; } cout << count << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__BUF_PP_SYMBOL_V
`define SKY130_FD_SC_HS__BUF_PP_SYMBOL_V
/**
* buf: Buffer.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__buf (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__BUF_PP_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////////////
// Company: Digilent Inc.
// Engineer: Andrew Skreen
//
// Create Date: 07/11/2012
// Module Name: two_bit_counter
// Project Name: PmodGYRO_Demo
// Target Devices: Nexys3
// Tool versions: ISE 14.1
// Description: Produces the select/control signals used to display data.
//
// Revision History:
// Revision 0.01 - File Created (Andrew Skreen)
// Revision 1.00 - Added Comments and Converted to Verilog (Josh Sackos)
//////////////////////////////////////////////////////////////////////////////////////////
// ==============================================================================
// Define Module
// ==============================================================================
module two_bit_counter(
dclk,
rst,
control
);
// ==============================================================================
// Port Declarations
// ==============================================================================
input dclk;
input rst;
output [1:0] control;
// ==============================================================================
// Parameters, Registers, and Wires
// ==============================================================================
reg [1:0] count;
// ==============================================================================
// Implementation
// ==============================================================================
// Counting process
always @(posedge dclk or posedge rst)
begin
if (rst == 1'b1)
count <= {2{1'b0}};
else
count <= count + 1'b1;
end
// Assign output control bus
assign control = count;
endmodule
|
#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0, f = 1; char ch; while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return f * x; } inline void chmax(int &x, int y) { x = max(x, y); } inline void chmin(int &x, int y) { x = min(x, y); } inline void pls(int &x, int y, int Mod) { x = (x + y >= Mod) ? (x + y - Mod) : (x + y); } inline void red(int &x, int y, int Mod) { x = (x - y < 0) ? (x - y + Mod) : (x - y); } const int MAXN = 200005; int n, m; vector<int> G[MAXN]; int fa[MAXN]; inline int find(int x) { if (fa[x] == x) return x; return fa[x] = find(fa[x]); } pair<int, int> lk[MAXN]; inline void del(int x) { lk[lk[x].first].second = lk[x].second; lk[lk[x].second].first = lk[x].first; } bool vis1[MAXN], vis2[MAXN]; int cnt[MAXN]; signed main() { n = read(), m = read(); for (int i = 1; i <= m; i++) { int x = read(), y = read(); G[x].push_back(y); G[y].push_back(x); } for (int i = 1; i <= n; i++) { fa[i] = i; lk[i - 1].second = i; lk[i].first = i - 1; } queue<int> q; while (lk[0].second) { int now = lk[0].second; del(now); q.push(now); while (!q.empty()) { int p = q.front(); q.pop(); vis1[p] = true; for (int i : G[p]) if (!vis1[i]) vis2[i] = true; int cur = lk[0].second; while (cur) { if (!vis2[cur]) { fa[find(cur)] = find(p); del(cur); q.push(cur); } cur = lk[cur].second; } for (int i : G[p]) vis2[i] = false; } } vector<int> ans; memset(vis1, false, sizeof(vis1)); for (int i = 1; i <= n; i++) cnt[find(i)]++; for (int i = 1; i <= n; i++) if (cnt[i]) ans.push_back(cnt[i]); sort(ans.begin(), ans.end()); cout << (int)ans.size() << endl; for (int i : ans) cout << i << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; inline int read() { register int x = 0, t = 1; register char ch = getchar(); while ((ch < 0 || ch > 9 ) && ch != - ) ch = getchar(); if (ch == - ) t = -1, ch = getchar(); while (ch <= 9 && ch >= 0 ) x = x * 10 + ch - 48, ch = getchar(); return x * t; } struct Line { int v, next; }; struct Link { Line e[444444 << 1]; int h[444444], cnt; void Add(int u, int v) { e[++cnt] = (Line){v, h[u]}; h[u] = cnt++; e[++cnt] = (Line){u, h[v]}; h[v] = cnt++; } } Gr, Tr; multiset<int> MS[444444]; int W[444444]; int n, m, Q, Tot; struct Graph { int dfn[444444], low[444444], S[444444], tim, top; void Tarjan(int u) { dfn[u] = low[u] = ++tim; S[++top] = u; for (int i = Gr.h[u]; i; i = Gr.e[i].next) { int v = Gr.e[i].v; if (!dfn[v]) { Tarjan(v); low[u] = min(low[u], low[v]); if (low[v] >= dfn[u]) { Tr.Add(++Tot, u); int x; do { x = S[top--]; Tr.Add(Tot, x); } while (v != x); } } else low[u] = min(low[u], dfn[v]); } } } G; struct SegMentTree { int t[444444 << 2]; void Modify(int now, int l, int r, int p, int w) { if (l == r) { t[now] = w; return; } int mid = (l + r) >> 1; if (p <= mid) Modify((now << 1), l, mid, p, w); else Modify((now << 1 | 1), mid + 1, r, p, w); t[now] = min(t[(now << 1)], t[(now << 1 | 1)]); } int Query(int now, int l, int r, int L, int R) { if (L <= l && r <= R) return t[now]; int ret = 1e9, mid = (l + r) >> 1; if (L <= mid) ret = min(ret, Query((now << 1), l, mid, L, R)); if (R > mid) ret = min(ret, Query((now << 1 | 1), mid + 1, r, L, R)); return ret; } } SMT; int fa[444444], tim, dfn[444444], low[444444]; int size[444444], hson[444444], top[444444], dep[444444]; void dfs1(int u, int ff) { fa[u] = ff; dep[u] = dep[ff] + 1; size[u] = 1; if (u <= n && ff) MS[ff].insert(W[u]); for (int i = Tr.h[u]; i; i = Tr.e[i].next) { int v = Tr.e[i].v; if (v == ff) continue; dfs1(v, u); size[u] += size[v]; if (size[v] > size[hson[u]]) hson[u] = v; } } void dfs2(int u, int tp) { top[u] = tp; dfn[u] = ++tim; low[tim] = u; if (hson[u]) dfs2(hson[u], tp); for (int i = Tr.h[u]; i; i = Tr.e[i].next) if (Tr.e[i].v != fa[u] && Tr.e[i].v != hson[u]) dfs2(Tr.e[i].v, Tr.e[i].v); } int Query(int u, int v) { int ret = 1e9; while (top[u] ^ top[v]) { if (dep[top[u]] < dep[top[v]]) swap(u, v); ret = min(ret, SMT.Query(1, 1, Tot, dfn[top[u]], dfn[u])); u = fa[top[u]]; } if (dep[u] > dep[v]) swap(u, v); ret = min(ret, SMT.Query(1, 1, Tot, dfn[u], dfn[v])); if (u <= n) return ret; else return min(ret, W[fa[u]]); } void Modify(int u, int w) { if (fa[u]) { MS[fa[u]].erase(MS[fa[u]].find(W[u])); MS[fa[u]].insert(w); SMT.Modify(1, 1, Tot, dfn[fa[u]], *MS[fa[u]].begin()); } W[u] = w; SMT.Modify(1, 1, Tot, dfn[u], w); } int main() { Tot = n = read(); m = read(); Q = read(); W[0] = 1e9; for (int i = 1; i <= n; ++i) W[i] = read(); for (int i = 1; i <= m; ++i) Gr.Add(read(), read()); G.Tarjan(1); dfs1(1, 0); dfs2(1, 1); for (int i = 1; i <= n; ++i) SMT.Modify(1, 1, Tot, dfn[i], W[i]); for (int i = n + 1; i <= Tot; ++i) SMT.Modify(1, 1, Tot, dfn[i], *MS[i].begin()); char ch[2]; while (Q--) { scanf( %s , ch); int a = read(), b = read(); if (ch[0] == C ) Modify(a, b); else printf( %d n , Query(a, b)); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND4B_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__NAND4B_PP_BLACKBOX_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nand4b (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND4B_PP_BLACKBOX_V
|
/*
read_eeprom.v
High Level module to read data from an i2c eeprom device.
inputs are:
- eeprom chip i2c slave address [7 bit]
- memory address to read from [16 bit]
- number of bytes to read [8 bit]
- start flag to begin the read operation [1-bit]
outputs are:
- data_out [8-bits]
- byte-ready [1-bit]
The new byte is placed in data_out as it is read and the byte-ready
flag is set
There are then a number of lines which communicate with the i1c_master
module which handles the actual communication with the eeprom chip.
This module handles the sending and receiving of bytes through the i2c module
This includes sending the slave address and memory address, the repeated start
signal and then reading the requested number of bytes.
The i2c_master module handles the lower level sending/receiving bytes with the actual chip.
IDLE
|
| start signal high
| Latch in slave addr, mem addr and nbytes
V
START
|
| set i2c control lines (addr, rw, etc) ready for address write
| set nbytes=2 (16bit address)
V
WRITE_ADDR
|
| For both memory address bytes:
| Wait for tx_data_req to go high (i1c requesting data) and then set it to the mem addr
V
READ_ADDR
|
| Send repeat start
| While nbytes>0, wait for rx_data_ready, set data_out and byte ready
V
IDLE
*/
module read_eeprom(
//inputs
input wire clk,
input wire reset,
input wire [6:0] slave_addr_w,
input wire [15:0] mem_addr_w,
input wire [7:0] read_nbytes_w,
input wire start,
//outputs
output reg [7:0] data_out,
output reg byte_ready,
//i2c master comms lines
output reg [6:0] i2c_slave_addr,
output reg i2c_rw,
output reg [7:0] i2c_write_data,
output reg [7:0] i2c_nbytes,
input wire [7:0] i2c_read_data,
input wire i2c_tx_data_req,
input wire i2c_rx_data_ready,
output reg i2c_start,
output reg busy
);
//state params
localparam STATE_IDLE = 0;
localparam STATE_START = 1;
localparam STATE_WRITE_ADDR = 2;
localparam STATE_REP_START = 3;
localparam STATE_READ_DATA = 4;
localparam READ = 1;
localparam WRITE = 0;
//local buffers to save the transfer information (device slave addr,
// memory addr, etc) when the transfer is started
reg [3:0] state;
reg [6:0] slave_addr;
reg [15:0] mem_addr;
reg [7:0] read_nbytes;
//output register definitions
reg waiting_for_tx;
reg read_prev_data;
reg [7:0] byte_count;
always @(posedge clk) begin
if (reset == 1) begin
i2c_slave_addr <= 0;
i2c_rw <= 0;
i2c_write_data <= 0;
i2c_start <= 0;
i2c_nbytes <= 0;
data_out <= 0;
byte_ready <= 0;
mem_addr <= 0;
slave_addr <= 0;
read_nbytes <= 0;
byte_count <= 0;
waiting_for_tx <= 0;
busy <= 0;
state <= STATE_IDLE;
end else begin
case(state)
STATE_IDLE: begin //idle
busy <= 0;
if (start) begin
state <= STATE_START;
//buffer all the control data
slave_addr <= slave_addr_w;
mem_addr <= mem_addr_w;
read_nbytes <= read_nbytes_w;
end
end //state_idle
STATE_START: begin
state <= STATE_WRITE_ADDR;
//set all the i2c control lines
i2c_slave_addr <= slave_addr;
i2c_rw <= WRITE;
i2c_nbytes <= 2; //2 memory addr bytes
byte_count <= 2;
waiting_for_tx <= 0;
i2c_start <= 1;
busy <= 1;
end //state_start
STATE_WRITE_ADDR: begin
if (waiting_for_tx == 0) begin
if (i2c_tx_data_req == 1) begin
waiting_for_tx <= 1;
case (byte_count)
2: begin
i2c_write_data <= mem_addr[15:8];
byte_count <= byte_count - 1'b1;
end //case 2
1: begin
i2c_write_data <= mem_addr[7:0];
byte_count <= byte_count - 1'b1;
state <= STATE_REP_START;
end //case 1
endcase
end//if i2x_tx_data_req
end else begin
if (i2c_tx_data_req == 0) begin
waiting_for_tx <= 0;
end //if i2x_tx_data_req
end //if waiting_for_tx
end //state WRITE_ADDR
STATE_REP_START: begin
state <= STATE_READ_DATA;
//set conditions for repeated start and change to read mode
i2c_start <= 1;
i2c_rw <= READ;
i2c_nbytes <= read_nbytes;
read_prev_data <= 0;
byte_count <= 0;
end //state_rep_start
STATE_READ_DATA: begin
if (read_prev_data == 0) begin
if (i2c_rx_data_ready) begin
data_out <= i2c_read_data;
byte_ready <= 1;
if (byte_count < (read_nbytes-1)) begin
byte_count <= byte_count + 1'b1;
read_prev_data <= 1;
end else begin
//we are done
i2c_start <= 0;
state <= STATE_IDLE;
end // if byte_count < read_nbytes
end //if i2c_rx_data_ready
end else begin
if (i2c_rx_data_ready == 0) begin
read_prev_data <= 0;
byte_ready <= 0;
end //if i2c_rx_data_ready
end // if read_prev_data
end //state_read_data
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { vector<long long int> v; long long int n, num, max_ind = 0, max_num = -1; cin >> n; for (long long int i = 0; i < n; i++) { cin >> num; v.push_back(num); if (num > max_num) { max_num = num; max_ind = i; } } if (max_num != 1) v[max_ind] = 1; else v[max_ind] = 2; sort(v.begin(), v.end()); for (long long int i = 0; i < n; i++) { cout << v[i] << ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long mod = 1000000007; const int INF = 1e9; const long long LINF = 1e18; long long mod_sum() { return 0LL; } template <typename T, typename... Args> T mod_sum(T a, Args... args) { return ((a + mod_sum(args...)) % mod + mod) % mod; } long long mod_prod() { return 1LL; } template <typename T, typename... Args> T mod_prod(T a, Args... args) { return (a * mod_prod(args...)) % mod; } struct ast { long long u, v, len; }; vector<ast> ans; long long solve() { long long n; cin >> n; priority_queue<pair<long long, long long>, vector<pair<long long, long long> >, greater<pair<long long, long long> > > pq0; priority_queue<pair<long long, long long>, vector<pair<long long, long long> >, greater<pair<long long, long long> > > pq1; for (long long i = 0; i < n; i++) { long long which, s; cin >> which >> s; if (which == 0) pq0.push({s, i}); else pq1.push({s, i}); } long long atlast0 = pq0.top().second, atlast1 = pq1.top().second; while (!pq0.empty() && !pq1.empty()) { if (pq0.top().first < pq1.top().first) { long long v = pq0.top().second; long long u = pq1.top().second; long long len = pq0.top().first; ans.push_back({u, v, len}); long long temp = pq1.top().first - len; pq0.pop(), pq1.pop(); pq1.push({temp, u}); } else { long long v = pq1.top().second; long long u = pq0.top().second; long long len = pq1.top().first; ans.push_back({u, v, len}); long long temp = pq0.top().first - len; pq0.pop(), pq1.pop(); pq0.push({temp, u}); } } if ((long long)ans.size() < n - 1 && !pq0.empty()) { pq0.pop(); while (!pq0.empty()) ans.push_back({atlast1, pq0.top().second, 0}), pq0.pop(); } else if ((long long)ans.size() < n - 1 && !pq1.empty()) { pq1.pop(); while (!pq1.empty()) ans.push_back({atlast0, pq1.top().second, 0}), pq1.pop(); } for (auto xxx : ans) cout << xxx.u + 1 << << xxx.v + 1 << << xxx.len << n ; return 0; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t = 1; while (t--) solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5; const int B = 350; int a[N]; int b[N]; int tot = 0; mt19937 rng(4112003); struct Node { Node *l, *r; Node *p; int key, pri; int nCh, cnt[B]; Node(int x = 0) : key(x), pri(rng() << 16 | rng()), nCh(1) { l = r = 0; for (int i = 0; i < tot; ++i) cnt[i] = 0; if (b[x] >= 0) cnt[b[x]] = 1; }; } * p[N]; int Siz(Node *x) { if (x) return x->nCh; else return 0; } void pull(Node *x) { Node *u = x->l; Node *v = x->r; x->nCh = 1; x->nCh += Siz(u); x->nCh += Siz(v); for (int i = 0; i < tot; ++i) { x->cnt[i] = 0; if (u) x->cnt[i] += u->cnt[i]; if (v) x->cnt[i] += v->cnt[i]; } if (b[x->key] >= 0) x->cnt[b[x->key]]++; if (u) u->p = x; if (v) v->p = x; } Node *join(Node *x, Node *y) { if (!x) return y; if (!y) return x; if (x->pri > y->pri) { x->r = join(x->r, y); pull(x); return x; } else { y->l = join(x, y->l); pull(y); return y; } } void split(Node *x, Node *&l, Node *&r, int p) { if (!x) { l = r = 0; return; } if (p >= Siz(x->l) + 1) { p -= Siz(x->l) + 1; split(x->r, x->r, r, p); pull(l = x); } else split(x->l, l, x->l, p), pull(r = x); } vector<int> pos[N]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); srand(time(NULL)); int n; cin >> n; for (int i = 0; i < n; ++i) { int x; cin >> x; --x; pos[x].emplace_back(i); a[i] = x; } for (int i = 0; i < n; ++i) { if (pos[i].size() > B) b[i] = tot++; else b[i] = -1; } Node *R = 0; for (int i = 0; i < n; ++i) R = join(R, p[i] = new Node(a[i])); int q; cin >> q; int lst = 0; for (int i = 0; i < q; ++i) { int t; cin >> t; int l; cin >> l; l = (l + lst - 1) % n; int r; cin >> r; r = (r + lst - 1) % n; if (l > r) swap(l, r); if (t == 1) { Node *x, *y, *z; split(R, R, x, l); split(x, x, y, r - l + 1); split(x, x, z, r - l); x = join(z, x); x = join(x, y); R = join(R, x); } if (t == 2) { int x; cin >> x; x = (x + lst - 1) % n; lst = 0; if (b[x] >= 0) { Node *p, *q; split(R, R, p, l); split(p, p, q, r - l + 1); lst = p->cnt[b[x]]; p = join(p, q); R = join(R, p); } else { for (int a : pos[x]) { Node *T = p[a]; int cur = Siz(T->l); while (T != R) { if (T->p->r == T) cur += Siz(T->p->l) + 1; T = T->p; } if (cur < l) continue; if (cur > r) continue; lst++; } } cout << lst << n ; } } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INVKAPWR_8_V
`define SKY130_FD_SC_LP__INVKAPWR_8_V
/**
* invkapwr: Inverter on keep-alive power rail.
*
* Verilog wrapper for invkapwr with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__invkapwr.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__invkapwr_8 (
Y ,
A ,
VPWR ,
VGND ,
KAPWR,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR ;
input VGND ;
input KAPWR;
input VPB ;
input VNB ;
sky130_fd_sc_lp__invkapwr base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.KAPWR(KAPWR),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__invkapwr_8 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 KAPWR;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__invkapwr base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__INVKAPWR_8_V
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; void io() {} long long fast_exp(long long base, int exp, int m) { long long res = 1; while (exp > 0) { if (exp % 2 == 1) { res = (res * base) % m; } base = (base * base) % m; exp /= 2; } return res % m; } vector<pair<long long, string> > v[10001]; long long dp[2001][4]; int main() { io(); ios ::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n, m; cin >> n >> m; while (n--) { string s; long long r, p; cin >> s >> r >> p; v[r].push_back(make_pair(p, s)); } for (int i = 1; i <= int(m); ++i) { sort(v[i].begin(), v[i].end()); int siz = v[i].size(); if (siz == 2) { cout << v[i][siz - 1].second << << v[i][siz - 2].second << n ; } else if ((v[i][siz - 2].first == v[i][siz - 3].first)) { cout << ? << n ; } else { cout << v[i][siz - 1].second << << v[i][siz - 2].second << n ; } } }
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#include <bits/stdc++.h> #pragma comment(linker, /STACK:64000000 ) using namespace std; const int inf32 = 1e9 + 9; const long long inf64 = 1e18 + 18; const int N = 6e5 + 5; const long long mod = 1e9 + 7; map<int, int> mp; vector<int> primes = {2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31}; int n, mx; void go(int &f, int a, int b, int mn) { if (a * b > mx) { if (a % b) return; mp[a] += mn; f -= mn; return; } go(f, a * b, b, (mn + 1) / 2); if (a % b) return; int t = min(f, mn); mp[a] += t; f -= t; } bool show() { int rez = 0; for (auto &x : mp) rez += x.second; return rez == n; } bool check(int j) { mp.clear(); mp[1] = n; int half = (n + 1) / 2; half += n / 100; for (int i = 0; i < j; ++i) { int x = primes[i]; int cnt = 0; bool flag = true; while (flag) { flag = false; for (auto &y : mp) { if (!y.second || !(y.first % x)) continue; int t = cnt; cnt += y.second; go(y.second, y.first, x, (y.second + 1) / 2); cnt -= y.second; flag |= t != cnt; if (cnt >= half) break; } if (cnt >= (n + 1) / 2) break; } if (!flag) { for (auto &y : mp) { if (y.second > 1 && y.first * x < mx) { mp[y.first * x] += 1; --y.second; ++cnt; } if (cnt >= (n + 1) / 2) break; } if (cnt < (n + 1) / 2) return false; } } for (auto &y : mp) { if (y.second > 1) { for (int i = 0; i < j; ++i) { int x = primes[i]; for (int i = x; y.second && i * y.first < mx; i *= x) { if (!mp[y.first * i]) { mp[y.first * i] = 1; --y.second; } } } } } if (n > 1000) { queue<int> lil; for (int i = 0; i < j; ++i) { for (int k = i + 1; k < j; ++k) { int x = primes[i], y = primes[k]; if (!mp[x * y]) lil.push(x * y); if (!mp[x]) lil.push(x); if (!mp[y]) lil.push(y); if (!mp[y * y]) lil.push(y * y); if (!mp[x * x]) lil.push(x * x); if (!mp[x * x * y]) lil.push(x * x * y); if (!mp[x * y * y]) lil.push(x * y * y); if (!mp[x * x * y * y]) lil.push(x * x * y * y); } } for (auto &x : mp) { while (x.second > 1) { while (!lil.empty() && mp[lil.front()]) lil.pop(); if (lil.empty()) return false; --x.second; mp[lil.front()] = 1; lil.pop(); } } } for (auto &x : mp) { if (x.second > 1) return false; } return true; } void solve() { cin >> n; mx = 2 * n * n; for (int j = 1; !check(j); ++j) ; int cnt = 0; for (auto &x : mp) { if (x.second) cout << x.first << ; } } int main() { solve(); return 0; }
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#include <bits/stdc++.h> using namespace std; int N[10]; string shirt[5] = { S , M , L , XL , XXL }; map<string, int> mp; int main() { int K, i, d; for ((i) = 0; (i) < (int)(5); (i)++) cin >> N[i]; cin >> K; for ((i) = 0; (i) < (int)(5); (i)++) mp[shirt[i]] = i; for ((i) = 0; (i) < (int)(K); (i)++) { string s; cin >> s; int x = mp[s]; int ans = -1; for (d = 0;; d++) { if (x + d >= 0 && x + d < 5 && N[x + d] > 0) { ans = x + d; break; } if (x - d >= 0 && x - d < 5 && N[x - d] > 0) { ans = x - d; break; } } N[ans]--; cout << shirt[ans] << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; long long int n, p, k; long long int cost[200010]; long long int price() { long long int dp[200010] = {0}; sort(cost, cost + n); long long int ans = 0; for (long long int i = 0; i < n; i++) { if (i < k - 1) { dp[i] = cost[i] + (i == 0 ? 0 : dp[i - 1]); } else if (i == k - 1) { dp[i] = cost[i]; } else { dp[i] = dp[i - k] + cost[i]; } if (dp[i] <= p) ans = i + 1; } return ans; } int main() { int t; cin >> t; while (t--) { cin >> n >> p >> k; for (int i = 0; i < n; i++) { cin >> cost[i]; }; cout << price() << endl; } }
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#include <bits/stdc++.h> using namespace std; pair<long double, int> v[100005]; int n; long double minn = 2 * 3.14159265358979323846264338327950288419716939937510 + 1; int minPos; int main() { cin >> n; for (int i = 1; i <= n; i++) { int x, y; cin >> x >> y; long double angle = atan2l(y, x); v[i] = { angle >= 0 ? angle : angle + 2 * 3.14159265358979323846264338327950288419716939937510, i}; } sort(v + 1, v + n + 1); for (int i = 1; i < n; i++) { if (v[i + 1].first - v[i].first < minn) { minn = v[i + 1].first - v[i].first; minPos = i; } } if (2 * 3.14159265358979323846264338327950288419716939937510 - v[n].first + v[1].first < minn) { minn = 2 * 3.14159265358979323846264338327950288419716939937510 - v[n].first + v[1].first; minPos = n; } cout << v[minPos].second << << v[(minPos == n) ? 1 : (minPos + 1)].second; }
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#include <bits/stdc++.h> using namespace std; int x[1000], y[1000], k, n, m; bool chck(int xx) { vector<int> v; v.push_back(1); v.push_back(m); for (int i = 0; i < k; ++i) { v.push_back(max(1, x[i] - xx)); v.push_back(max(1, x[i] - xx - 1)); v.push_back(min(m, x[i] + xx)); v.push_back(min(m, x[i] + xx + 1)); } sort(v.begin(), v.end()); int mn = 1e9, mx = -1, tmp, nm, c; bool l; vector<pair<int, int> > f; for (int i = 0; i < v.size(); ++i) { tmp = v[i]; f.clear(); for (int j = 0; j < k; ++j) { if (x[j] - xx <= tmp && x[j] + xx >= tmp) { f.push_back(make_pair(max(1, y[j] - xx), 0)); f.push_back(make_pair(min(n, y[j] + xx), 1)); } } sort(f.begin(), f.end()); c = 0; nm = 0; l = 0; for (int j = 0; j < f.size(); ++j) { if (nm == 0) { if (f[j].first != c + 1) { break; } } c = f[j].first; if (f[j].second == 0) ++nm; else --nm; if (c == n) { l = 1; break; } } if (!l) { mn = min(mn, tmp); mx = max(mx, tmp); } } mx = min(mx, m); mn = max(1, mn); if (mx - mn + 1 > xx + xx + 1) { return 0; } v.clear(); v.push_back(1); v.push_back(n); for (int i = 0; i < k; ++i) { v.push_back(max(1, y[i] - xx)); v.push_back(max(1, y[i] - xx - 1)); v.push_back(min(n, y[i] + xx)); v.push_back(min(n, y[i] + xx + 1)); } sort(v.begin(), v.end()); mn = 1e9, mx = -1; for (int i = 0; i < v.size(); ++i) { tmp = v[i]; f.clear(); for (int j = 0; j < k; ++j) { if (y[j] - xx <= tmp && y[j] + xx >= tmp) { f.push_back(make_pair(max(1, x[j] - xx), 0)); f.push_back(make_pair(min(m, x[j] + xx), 1)); } } sort(f.begin(), f.end()); c = 0; nm = 0; l = 0; for (int j = 0; j < f.size(); ++j) { if (nm == 0) { if (f[j].first != c + 1) { break; } } c = f[j].first; if (f[j].second == 0) ++nm; else --nm; if (c == m) { l = 1; break; } } if (!l) { mn = min(mn, tmp); mx = max(mx, tmp); } } mx = min(mx, n); mn = max(1, mn); if (mx - mn + 1 > xx + xx + 1) { return 0; } return 1; } int main() { while (cin >> m >> n >> k) { for (int i = 0; i < k; ++i) { scanf( %d%d , &x[i], &y[i]); } int st = 0, nd = 1e9, md; while (st < nd) { md = (st + nd) / 2; if (chck(md)) { nd = md; } else { st = md + 1; } } printf( %d n , nd); } return 0; }
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//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
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// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// (individually and collectively, "Critical
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//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.91
// \ \ Application : MIG
// / / Filename : bank_compare.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : Virtex-6
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// This block stores the request for this bank machine.
//
// All possible new requests are compared against the request stored
// here. The compare results are shared with the bank machines and
// is used to determine where to enqueue a new request.
`timescale 1ps/1ps
module bank_compare #
(parameter BANK_WIDTH = 3,
parameter TCQ = 100,
parameter BURST_MODE = "8",
parameter COL_WIDTH = 12,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter ECC = "OFF",
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter ROW_WIDTH = 16)
(/*AUTOARG*/
// Outputs
req_data_buf_addr_r, req_periodic_rd_r, req_size_r, rd_wr_r,
req_rank_r, req_bank_r, req_row_r, req_wr_r, req_priority_r,
rb_hit_busy_r, rb_hit_busy_ns, row_hit_r, maint_hit, col_addr,
req_ras, req_cas, row_cmd_wr, row_addr, rank_busy_r,
// Inputs
clk, idle_ns, idle_r, data_buf_addr, periodic_rd_insert, size, cmd,
sending_col, rank, periodic_rd_rank_r, bank, row, col, hi_priority,
maint_rank_r, maint_zq_r, auto_pre_r, rd_half_rmw, act_wait_r
);
input clk;
input idle_ns;
input idle_r;
input [DATA_BUF_ADDR_WIDTH-1:0]data_buf_addr;
output reg [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_r;
wire [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_ns =
idle_r
? data_buf_addr
: req_data_buf_addr_r;
always @(posedge clk) req_data_buf_addr_r <= #TCQ req_data_buf_addr_ns;
input periodic_rd_insert;
reg req_periodic_rd_r_lcl;
wire req_periodic_rd_ns = idle_ns
? periodic_rd_insert
: req_periodic_rd_r_lcl;
always @(posedge clk) req_periodic_rd_r_lcl <= #TCQ req_periodic_rd_ns;
output wire req_periodic_rd_r;
assign req_periodic_rd_r = req_periodic_rd_r_lcl;
input size;
wire req_size_r_lcl;
generate
if (BURST_MODE == "4") begin : burst_mode_4
assign req_size_r_lcl = 1'b0;
end
else
if (BURST_MODE == "8") begin : burst_mode_8
assign req_size_r_lcl = 1'b1;
end
else
if (BURST_MODE == "OTF") begin : burst_mode_otf
reg req_size;
wire req_size_ns = idle_ns
? (periodic_rd_insert || size)
: req_size;
always @(posedge clk) req_size <= #TCQ req_size_ns;
assign req_size_r_lcl = req_size;
end
endgenerate
output wire req_size_r;
assign req_size_r = req_size_r_lcl;
input [2:0] cmd;
reg [2:0] req_cmd_r;
wire [2:0] req_cmd_ns = idle_ns
? (periodic_rd_insert ? 3'b001 : cmd)
: req_cmd_r;
always @(posedge clk) req_cmd_r <= #TCQ req_cmd_ns;
`ifdef MC_SVA
rd_wr_only_wo_ecc: assert property
(@(posedge clk) ((ECC != "OFF") || idle_ns || ~|req_cmd_ns[2:1]));
`endif
input sending_col;
reg rd_wr_r_lcl;
wire rd_wr_ns = idle_ns
? ((req_cmd_ns[1:0] == 2'b11) || req_cmd_ns[0])
: ~sending_col && rd_wr_r_lcl;
always @(posedge clk) rd_wr_r_lcl <= #TCQ rd_wr_ns;
output wire rd_wr_r;
assign rd_wr_r = rd_wr_r_lcl;
input [RANK_WIDTH-1:0] rank;
input [RANK_WIDTH-1:0] periodic_rd_rank_r;
reg [RANK_WIDTH-1:0] req_rank_r_lcl = {RANK_WIDTH{1'b0}};
reg [RANK_WIDTH-1:0] req_rank_ns = {RANK_WIDTH{1'b0}};
generate
if (RANKS != 1) begin
always @(/*AS*/idle_ns or periodic_rd_insert
or periodic_rd_rank_r or rank or req_rank_r_lcl) req_rank_ns = idle_ns
? periodic_rd_insert
? periodic_rd_rank_r
: rank
: req_rank_r_lcl;
always @(posedge clk) req_rank_r_lcl <= #TCQ req_rank_ns;
end
endgenerate
output wire [RANK_WIDTH-1:0] req_rank_r;
assign req_rank_r = req_rank_r_lcl;
input [BANK_WIDTH-1:0] bank;
reg [BANK_WIDTH-1:0] req_bank_r_lcl;
wire [BANK_WIDTH-1:0] req_bank_ns = idle_ns ? bank : req_bank_r_lcl;
always @(posedge clk) req_bank_r_lcl <= #TCQ req_bank_ns;
output wire[BANK_WIDTH-1:0] req_bank_r;
assign req_bank_r = req_bank_r_lcl;
input [ROW_WIDTH-1:0] row;
reg [ROW_WIDTH-1:0] req_row_r_lcl;
wire [ROW_WIDTH-1:0] req_row_ns = idle_ns ? row : req_row_r_lcl;
always @(posedge clk) req_row_r_lcl <= #TCQ req_row_ns;
output wire [ROW_WIDTH-1:0] req_row_r;
assign req_row_r = req_row_r_lcl;
// Make req_col_r as wide as the max row address. This
// makes it easier to deal with indexing different column widths.
input [COL_WIDTH-1:0] col;
reg [15:0] req_col_r = 16'b0;
wire [COL_WIDTH-1:0] req_col_ns = idle_ns ? col : req_col_r[COL_WIDTH-1:0];
always @(posedge clk) req_col_r[COL_WIDTH-1:0] <= #TCQ req_col_ns;
reg req_wr_r_lcl;
wire req_wr_ns = idle_ns
? ((req_cmd_ns[1:0] == 2'b11) || ~req_cmd_ns[0])
: req_wr_r_lcl;
always @(posedge clk) req_wr_r_lcl <= #TCQ req_wr_ns;
output wire req_wr_r;
assign req_wr_r = req_wr_r_lcl;
input hi_priority;
output reg req_priority_r;
wire req_priority_ns = idle_ns ? hi_priority : req_priority_r;
always @(posedge clk) req_priority_r <= #TCQ req_priority_ns;
wire rank_hit = (req_rank_r_lcl == (periodic_rd_insert
? periodic_rd_rank_r
: rank));
wire bank_hit = (req_bank_r_lcl == bank);
wire rank_bank_hit = rank_hit && bank_hit;
output reg rb_hit_busy_r; // rank-bank hit on non idle row machine
wire rb_hit_busy_ns_lcl;
assign rb_hit_busy_ns_lcl = rank_bank_hit && ~idle_ns;
output wire rb_hit_busy_ns;
assign rb_hit_busy_ns = rb_hit_busy_ns_lcl;
wire row_hit_ns = (req_row_r_lcl == row);
output reg row_hit_r;
always @(posedge clk) rb_hit_busy_r <= #TCQ rb_hit_busy_ns_lcl;
always @(posedge clk) row_hit_r <= #TCQ row_hit_ns;
input [RANK_WIDTH-1:0] maint_rank_r;
input maint_zq_r;
output wire maint_hit;
assign maint_hit = (req_rank_r_lcl == maint_rank_r) || maint_zq_r;
// Assemble column address. Structure to be the same
// width as the row address. This makes it easier
// for the downstream muxing. Depending on the sizes
// of the row and column addresses, fill in as appropriate.
input auto_pre_r;
input rd_half_rmw;
reg [15:0] col_addr_template = 16'b0;
always @(/*AS*/auto_pre_r or rd_half_rmw or req_col_r
or req_size_r_lcl) begin
col_addr_template = req_col_r;
col_addr_template[10] = auto_pre_r && ~rd_half_rmw;
col_addr_template[11] = req_col_r[10];
col_addr_template[12] = req_size_r_lcl;
col_addr_template[13] = req_col_r[11];
end
output wire [ROW_WIDTH-1:0] col_addr;
assign col_addr = col_addr_template[ROW_WIDTH-1:0];
output wire req_ras;
output wire req_cas;
output wire row_cmd_wr;
input act_wait_r;
assign req_ras = 1'b0;
assign req_cas = 1'b1;
assign row_cmd_wr = act_wait_r;
output reg [ROW_WIDTH-1:0] row_addr;
always @(/*AS*/act_wait_r or req_row_r_lcl) begin
row_addr = req_row_r_lcl;
// This causes all precharges to be precharge single bank command.
if (~act_wait_r) row_addr[10] = 1'b0;
end
// Indicate which, if any, rank this bank machine is busy with.
// Not registering the result would probably be more accurate, but
// would create timing issues. This is used for refresh banking, perfect
// accuracy is not required.
localparam ONE = 1;
output reg [RANKS-1:0] rank_busy_r;
wire [RANKS-1:0] rank_busy_ns = {RANKS{~idle_ns}} & (ONE[RANKS-1:0] << req_rank_ns);
always @(posedge clk) rank_busy_r <= #TCQ rank_busy_ns;
endmodule // bank_compare
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#include <bits/stdc++.h> using namespace std; const unsigned long long x = 31; unsigned long long X[60000]; int Ql[20], Qr[20]; char str[60000], s[60000]; int N; map<unsigned long long, int> T[20]; map<unsigned long long, bool> A; void add(int index, unsigned long long H) { T[index][H] = T[index][H] + 1; } void CalcHashes(char s[], int index) { unsigned long long H; int i, j, L = strlen(s); for (i = 1; i <= L; i++) { H = 0; for (j = 0; j < i; j++) H += X[i - j - 1] * (s[j] - a + 1); add(index, H); for (j = i; j < L; j++) { H = (H - X[i - 1] * (s[j - i] - a + 1)) * x + (s[j] - a + 1); add(index, H); } } } int answer; void check(unsigned long long H) { if (A[H]) return; A[H] = true; int i, t; bool v = true; for (i = 0; i < N && v; i++) { t = T[i][H]; if (t < Ql[i] || Qr[i] < t) v = false; } if (v) answer++; } int main() { unsigned long long H; int i, j, L; for (X[0] = 1, i = 1; i <= 60000; i++) X[i] = X[i - 1] * x; scanf( %s , str); scanf( %d , &N); for (i = 0; i < N; i++) { scanf( %s%d%d , &s, &Ql[i], &Qr[i]); CalcHashes(s, i); } L = strlen(str); for (i = 1; i <= L; i++) { H = 0; for (j = 0; j < i; j++) H += X[i - j - 1] * (str[j] - a + 1); check(H); for (j = i; j < L; j++) { H = (H - X[i - 1] * (str[j - i] - a + 1)) * x + (str[j] - a + 1); check(H); } } printf( %d , answer); return 0; }
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/*
ORSoC GFX accelerator core
Copyright 2012, ORSoC, Per Lenander, Anton Fosselius.
PER-PIXEL COLORING MODULE, alpha blending
This file is part of orgfx.
orgfx is free software: you can redistribute it and/or modify
it under the terms of the GNU Lesser General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
orgfx is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public License
along with orgfx. If not, see <http://www.gnu.org/licenses/>.
*/
/*
This module performs alpha blending by fetching the pixel from the target and mixing it with the texel based on the current alpha value.
The exact formula is:
alpha = global_alpha_i * alpha_i
color_out = color_in * alpha + color_target * (1-alpha) , where alpha is defined from 0 to 1
alpha_i[7:0] is used, so the actual span is 0 (transparent) to 255 (opaque)
If alpha blending is disabled (blending_enable_i == 1'b0) the module just passes on the input pixel.
*/
module gfx_blender(clk_i, rst_i,
blending_enable_i, target_base_i, target_size_x_i, target_size_y_i, color_depth_i,
x_counter_i, y_counter_i, z_i, alpha_i, global_alpha_i, write_i, ack_o, // from fragment
target_ack_i, target_addr_o, target_data_i, target_sel_o, target_request_o, wbm_busy_i, // from/to wbm reader
pixel_x_o, pixel_y_o, pixel_z_o, pixel_color_i, pixel_color_o, write_o, ack_i // to render
);
parameter point_width = 16;
input clk_i;
input rst_i;
input blending_enable_i;
input [31:2] target_base_i;
input [point_width-1:0] target_size_x_i;
input [point_width-1:0] target_size_y_i;
input [1:0] color_depth_i;
// from fragment
input [point_width-1:0] x_counter_i;
input [point_width-1:0] y_counter_i;
input signed [point_width-1:0] z_i;
input [7:0] alpha_i;
input [7:0] global_alpha_i;
input [31:0] pixel_color_i;
input write_i;
output reg ack_o;
// Interface against wishbone master (reader)
input target_ack_i;
output [31:2] target_addr_o;
input [31:0] target_data_i;
output reg [3:0] target_sel_o;
output reg target_request_o;
input wbm_busy_i;
//to render
output reg [point_width-1:0] pixel_x_o;
output reg [point_width-1:0] pixel_y_o;
output reg signed [point_width-1:0] pixel_z_o;
output reg [31:0] pixel_color_o;
output reg write_o;
input ack_i;
// State machine
reg [1:0] state;
parameter wait_state = 2'b00,
target_read_state = 2'b01,
write_pixel_state = 2'b10;
// Calculate alpha
reg [15:0] combined_alpha_reg;
wire [7:0] alpha = combined_alpha_reg[15:8];
// Calculate address of target pixel
// Addr[31:2] = Base + (Y*width + X) * ppb
wire [31:0] pixel_offset;
assign pixel_offset = (color_depth_i == 2'b00) ? (target_size_x_i*y_counter_i + {16'h0, x_counter_i}) : // 8 bit
(color_depth_i == 2'b01) ? (target_size_x_i*y_counter_i + {16'h0, x_counter_i}) << 1 : // 16 bit
(target_size_x_i*y_counter_i + {16'h0, x_counter_i}) << 2 ; // 32 bit
assign target_addr_o = target_base_i + pixel_offset[31:2];
// Split colors for alpha blending (render color)
wire [7:0] blend_color_r = (color_depth_i == 2'b00) ? pixel_color_i[7:0] :
(color_depth_i == 2'b01) ? pixel_color_i[15:11] :
pixel_color_i[23:16];
wire [7:0] blend_color_g = (color_depth_i == 2'b00) ? pixel_color_i[7:0] :
(color_depth_i == 2'b01) ? pixel_color_i[10:5] :
pixel_color_i[15:8];
wire [7:0] blend_color_b = (color_depth_i == 2'b00) ? pixel_color_i[7:0] :
(color_depth_i == 2'b01) ? pixel_color_i[4:0] :
pixel_color_i[7:0];
// Split colors for alpha blending (from target surface)
wire [7:0] target_color_r = (color_depth_i == 2'b00) ? dest_color[7:0] :
(color_depth_i == 2'b01) ? dest_color[15:11] :
target_data_i[23:16];
wire [7:0] target_color_g = (color_depth_i == 2'b00) ? dest_color[7:0] :
(color_depth_i == 2'b01) ? dest_color[10:5] :
target_data_i[15:8];
wire [7:0] target_color_b = (color_depth_i == 2'b00) ? dest_color[7:0] :
(color_depth_i == 2'b01) ? dest_color[4:0] :
target_data_i[7:0];
// Alpha blending (per color channel):
// rgb = (alpha1)(rgb1) + (1-alpha1)(rgb2)
wire [15:0] alpha_color_r = blend_color_r * alpha + target_color_r * (8'hff - alpha);
wire [15:0] alpha_color_g = blend_color_g * alpha + target_color_g * (8'hff - alpha);
wire [15:0] alpha_color_b = blend_color_b * alpha + target_color_b * (8'hff - alpha);
wire [31:0] dest_color;
// Memory to color converter
memory_to_color memory_proc(
.color_depth_i (color_depth_i),
.mem_i (target_data_i),
.mem_lsb_i (x_counter_i[1:0]),
.color_o (dest_color),
.sel_o ()
);
// Acknowledge when a command has completed
always @(posedge clk_i or posedge rst_i)
begin
// reset, init component
if(rst_i)
begin
ack_o <= 1'b0;
write_o <= 1'b0;
pixel_x_o <= 1'b0;
pixel_y_o <= 1'b0;
pixel_z_o <= 1'b0;
pixel_color_o <= 1'b0;
target_request_o <= 1'b0;
target_sel_o <= 4'b1111;
end
// Else, set outputs for next cycle
else
begin
case (state)
wait_state:
begin
ack_o <= 1'b0;
if(write_i)
begin
if(!blending_enable_i)
begin
pixel_x_o <= x_counter_i;
pixel_y_o <= y_counter_i;
pixel_z_o <= z_i;
pixel_color_o <= pixel_color_i;
write_o <= 1'b1;
end
else
begin
target_request_o <= !wbm_busy_i;
combined_alpha_reg <= alpha_i * global_alpha_i;
end
end
end
// Read pixel color at target (request is sent through the wbm reader arbiter).
target_read_state:
if(target_ack_i)
begin
// When we receive an ack from memory, calculate the combined color and send the pixel forward in the pipeline (go to write state)
write_o <= 1'b1;
pixel_x_o <= x_counter_i;
pixel_y_o <= y_counter_i;
pixel_z_o <= z_i;
target_request_o <= 1'b0;
// Recombine colors
pixel_color_o <= (color_depth_i == 2'b00) ? {alpha_color_r[15:8]} : // 8 bit grayscale
(color_depth_i == 2'b01) ? {alpha_color_r[12:8], alpha_color_g[13:8], alpha_color_b[12:8]} : // 16 bit
{alpha_color_r[15:8], alpha_color_g[15:8], alpha_color_b[15:8]}; // 32 bit
end
else
target_request_o <= !wbm_busy_i | target_request_o;
// Ack and return to wait state
write_pixel_state:
begin
write_o <= 1'b0;
if(ack_i)
ack_o <= 1'b1;
end
endcase
end
end
// State machine
always @(posedge clk_i or posedge rst_i)
begin
// reset, init component
if(rst_i)
state <= wait_state;
// Move in statemachine
else
case (state)
wait_state:
if(write_i & blending_enable_i)
state <= target_read_state;
else if(write_i)
state <= write_pixel_state;
target_read_state:
if(target_ack_i)
state <= write_pixel_state;
write_pixel_state:
if(ack_i)
state <= wait_state;
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFXTP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__SDFXTP_FUNCTIONAL_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p/sky130_fd_sc_hvl__udp_dff_p.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_hvl__sdfxtp (
Q ,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFXTP_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-5; const int p = 131; const int inf = 0x3f3f3f3f; const long long mod = 1e9 + 7; const int N = 1e6 + 10; long long Hash[N], fac[N]; char s[N], ss[N]; long long get(int l, int r) { return (Hash[r] - Hash[l - 1] * fac[r - l + 1] % mod + mod) % mod; } void run() { scanf( %s %s , s + 1, ss + 1); int len1 = strlen(s + 1); int len2 = strlen(ss + 1); fac[0] = 1; int n0 = 0, n1 = 0; for (int i = 1; i <= len1; i++) { n0 += (s[i] == 0 ); n1 += (s[i] == 1 ); } for (int i = 1; i <= len2; i++) { Hash[i] = (Hash[i - 1] * p % mod + ss[i] - a + 1) % mod; fac[i] = fac[i - 1] * p % mod; } int res = 0; for (int l0 = 1, l1; l0 < len2; l0++) { if (l0 * n0 >= len2) break; if ((len2 - l0 * n0) % n1) continue; l1 = (len2 - l0 * n0) / n1; long long hash0 = -1, hash1 = -1; int idx = 1; int flag = 1; for (int j = 1; j <= len1; j++) { if (s[j] == 1 ) { if (hash1 == -1) { hash1 = get(idx, idx + l1 - 1); } else if (hash1 != get(idx, idx + l1 - 1)) { flag = 0; break; } idx += l1; } else { if (hash0 == -1) { hash0 = get(idx, idx + l0 - 1); } else if (hash0 != get(idx, idx + l0 - 1)) { flag = 0; break; } idx += l0; } if (~hash0 && ~hash1 && hash0 == hash1) { flag = 0; break; } } if (flag) res++; } printf( %d n , res); } int main() { run(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O311A_4_V
`define SKY130_FD_SC_LS__O311A_4_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog wrapper for o311a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o311a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o311a_4 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o311a_4 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O311A_4_V
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:136777216 ) using namespace std; int bits(int x) { return x == 0 ? 0 : 1 + bits(x & (x - 1)); } int v[30][30]; int dp[2][26][111]; int main() { const int ninf = -1000000; for (int(i) = 0; (i) < (30); (i)++) for (int(j) = 0; (j) < (30); (j)++) v[i][j] = 0; string s; int K, m; cin >> s >> K >> m; int n = (int)(s).size(); K = min(K, n); char a, b; int c; for (int(i) = 0; (i) < (m); (i)++) { cin >> a >> b >> c; v[a - a ][b - a ] = c; } for (int(j) = 0; (j) < (26); (j)++) for (int(k) = 0; (k) < (K + 1); (k)++) dp[0][j][k] = ninf; for (int(j) = 0; (j) < (26); (j)++) if (j == s[0] - a ) dp[0][j][0] = 0; else dp[0][j][1] = 0; int add; for (int i = 1; i < n; i++) { int now = i % 2, bef = 1 - now; for (int(j) = 0; (j) < (26); (j)++) for (int(k) = 0; (k) < (K + 1); (k)++) dp[now][j][k] = ninf; for (int(prev) = 0; (prev) < (26); (prev)++) for (int(cur) = 0; (cur) < (26); (cur)++) { if (cur == s[i] - a ) add = 0; else add = 1; if (add == 0) dp[now][cur][0] = max(dp[now][cur][0], dp[bef][prev][0] + v[prev][cur]); for (int(ch) = (1); (ch) < (K + 1); (ch)++) { dp[now][cur][ch] = max(dp[now][cur][ch], dp[bef][prev][ch - add] + v[prev][cur]); } } } int r = ninf, t = (n - 1) % 2; for (int(j) = 0; (j) < (26); (j)++) for (int(k) = 0; (k) < (K + 1); (k)++) r = max(r, dp[t][j][k]); cout << r; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Xilinx
// Engineer: Parimal Patel
// Create Date: 04/13/2017
// Module Name: fsm_controller
// Project Name: PYNQ
//////////////////////////////////////////////////////////////////////////////////
module fsm_controller (
input clk,
// controls_input are multiple clocks wide as they are generated by GPIO write
// [0] = start, [1] = stop, [2] = PG, [3] = FSM, [4] = Trace only, [5] = Step
input [5:0] controls_input,
input reset_n,
output reg fsm_enb,
output fsm_rst
);
reg step_executed, step_executed_1;
reg fsm_enb_1d=0;
reg stopped=0;
reg step_executed_after_stopped;
wire start;
wire stop;
wire step;
assign fsm_rst = (fsm_enb ^ fsm_enb_1d) & ~step_executed_1 & ~step_executed | step_executed_after_stopped;
// pulsed output generation
pulse_gen sync_start(.async_in(controls_input[0]&controls_input[3]), .sync_clk(clk), .pulsed_out(start));
pulse_gen sync_stop(.async_in(controls_input[1]&controls_input[3]), .sync_clk(clk), .pulsed_out(stop));
pulse_gen sync_step(.async_in(controls_input[5]&controls_input[3]), .sync_clk(clk), .pulsed_out(step));
always @(posedge clk)
if (!reset_n)
fsm_enb_1d <= 0;
else
fsm_enb_1d <= fsm_enb;
always @(posedge clk)
if (!reset_n)
begin
fsm_enb <= 0;
step_executed <= 0;
step_executed_1 <= 0;
end
else
begin
if(start) // start asserted
begin
fsm_enb <= 1;
step_executed <= 0;
end
else if(stop) // stop asserted
begin
fsm_enb <= 0;
step_executed <= 0;
end
else if(step)
begin
fsm_enb <= 1;
step_executed <= 1;
step_executed_1 <= 0;
end
else if(step_executed)
begin
step_executed <= 0;
step_executed_1 <= 1;
fsm_enb <=0;
end
else if(step_executed_1)
begin
step_executed_1 <= 0;
fsm_enb <=0;
end
else
begin
fsm_enb <= fsm_enb;
step_executed <= step_executed;
end
end
always @(posedge clk)
if (!reset_n)
begin
step_executed_after_stopped <= 0;
stopped <= 0;
end
else
begin
if(stop) // stop asserted
begin
step_executed_after_stopped <= 0;
stopped <= 1;
end
else if(stopped & step)
begin
step_executed_after_stopped <= 1;
stopped <= 0;
end
else if(step_executed_after_stopped)
begin
step_executed_after_stopped <= 0;
end
else
begin
step_executed_after_stopped <= step_executed_after_stopped;
end
end
endmodule
|
module tb;
reg clk = 0;
reg rst = 1;
wire mm_we;
wire [0:11] mm_adr;
wire [0:17] mm_din;
wire [0:17] mm_dout;
wire [0:3] mm_unit;
reg [0:5] sw_sn = 6'b0;
reg [0:17] sw_tw = 18'o777777;
reg cntrl_stop = 0;
reg cntrl_halt = 0;
wire cntrl_paused;
wire [0:1] cntrl_reason;
reg cntrl_resume = 0;
wire intr_disarm;
wire bs_stb;
wire [0:10] bs_adr;
wire bs_wait;
wire [0:17] bs_din;
wire [0:17] bs_dout;
wire bs_inh;
always #10 clk = ~clk;
pdp1_memory mem(clk, rst,
mm_we, mm_adr, mm_din, mm_dout);
pdp1_cpu cpu(clk, rst,
mm_we, mm_adr, mm_unit, mm_din, mm_dout,
bs_stb, bs_adr, bs_wait, bs_din, bs_dout, bs_inh,
sw_sn, sw_tw,
cntrl_stop, cntrl_halt, cntrl_paused,
cntrl_resume, cntrl_reason, 4'b0000, intr_grant);
always @(posedge clk)
if(cntrl_paused)
$finish();
initial begin
$dumpfile("pdp1.vcd");
$dumpvars(0, cpu);
$dumpvars(0, mem);
#100 rst = 0;
# $finish();
end
endmodule // tb
|
#include <bits/stdc++.h> using namespace std; int main() { int boxes; cin >> boxes; int arr[boxes]; for (int i = 0; i < boxes; i++) cin >> arr[i]; int shots; cin >> shots; int x, y; for (int i = 0; i < shots; i++) { cin >> x >> y; if (x == 1) { arr[x] += (arr[x - 1] - y); arr[0] = 0; } else if (x == boxes) { arr[boxes - 1] = 0; arr[x - 2] += (y - 1); } else { arr[x] += (arr[x - 1] - y); arr[x - 2] += (y - 1); arr[x - 1] = 0; } } for (int i = 0; i < boxes; i++) cout << arr[i] << endl; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:43:45 02/20/2015
// Design Name:
// Module Name: Fetch
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Fetch_FSL(
input [107:0] InstructionPacket,
input [107:0] InstructionPacket_Processed,
input ProcessInputReady,
input reset,
input clock,
input stall,
output reg [31:0] x_input = 32'h00000000,
output reg [31:0] y_input = 32'h00000000,
output reg [31:0] z_input = 32'h00000000,
output reg [1:0] mode,
output reg operation,
output reg [7:0] InsTagFetchOut,
output reg load = 1'b0,
output reg NatLogFlag = 1'b0
);
wire [3:0] Opcode;
wire [31:0] x_processor;
wire [31:0] y_processor;
wire [31:0] z_processor;
wire [7:0] InstructionTag;
wire [3:0] Opcode_processed;
wire [31:0] x_processor_processed;
wire [31:0] y_processor_processed;
wire [31:0] z_processor_processed;
wire [7:0] InstructionTag_processed;
assign InstructionTag = InstructionPacket[107:100];
assign Opcode = InstructionPacket[99:96];
assign x_processor = InstructionPacket[31:0];
assign y_processor = InstructionPacket[63:32];
assign z_processor = InstructionPacket[95:64];
assign InstructionTag_processed = InstructionPacket_Processed[107:100];
assign Opcode_processed = InstructionPacket_Processed[99:96];
assign x_processor_processed = InstructionPacket_Processed[31:0];
assign y_processor_processed = InstructionPacket_Processed[63:32];
assign z_processor_processed = InstructionPacket_Processed[95:64];
parameter sin_cos = 4'd0,
sinh_cosh = 4'd1,
arctan = 4'd2,
arctanh = 4'd3,
exp = 4'd4,
sqr_root = 4'd5, // Pre processed input is given 4'd11
// This requires pre processing. x = (a+1)/2 and y = (a-1)/2
division = 4'd6,
tan = 4'd7, // This is iterative. sin_cos followed by division.
tanh = 4'd8, // This is iterative. sinh_cosh followed by division.
nat_log = 4'd9, // This requires pre processing. x = (a+1) and y = (a-1)
hypotenuse = 4'd10;
parameter vectoring = 1'b0,
rotation = 1'b1;
parameter circular = 2'b01,
linear = 2'b00,
hyperbolic = 2'b11;
always @ (posedge clock)
begin
if (reset == 1'b1) begin
x_input <= 32'h00000000;
y_input <= 32'h00000000;
z_input <= 32'h00000000;
load <= 1'b0;
NatLogFlag <= 1'b0;
end
else begin
if (ProcessInputReady == 1'b0) begin
InsTagFetchOut <= InstructionTag;
case(Opcode)
sin_cos:
begin
mode <= circular;
operation <= rotation;
x_input <= 32'h3F800000;
y_input <= 32'h00000000;
z_input <= z_processor;
load <= 1'b1;
end
sinh_cosh:
begin
mode <= hyperbolic;
operation <= rotation;
x_input <= 32'h3F800000;
y_input <= 32'h00000000;
z_input <= z_processor;
load <= 1'b1;
end
arctan:
begin
mode <= circular;
operation <= vectoring;
x_input <= 32'h3F800000;
y_input <= y_processor;
z_input <= 32'h00000000;
load <= 1'b1;
end
arctanh:
begin
mode <= hyperbolic;
operation <= vectoring;
x_input <= 32'h3F800000;
y_input <= y_processor;
z_input <= 32'h00000000;
load <= 1'b1;
end
exp:
begin
mode <= hyperbolic;
operation <= rotation;
x_input <= 32'h3F800000;
y_input <= 32'h3F800000;
z_input <= z_processor;
load <= 1'b1;
end
division:
begin
mode <= linear;
operation <= vectoring;
x_input <= x_processor;
y_input <= y_processor;
z_input <= 32'h00000000;
load <= 1'b1;
end
hypotenuse:
begin
mode <= circular;
operation <= vectoring;
x_input <= x_processor;
y_input <= y_processor;
z_input <= 32'h00000000;
load <= 1'b1;
end
endcase
end
else begin
InsTagFetchOut <= InstructionTag_processed;
case(Opcode_processed)
sqr_root:
begin
mode <= hyperbolic;
operation <= vectoring;
x_input[31] <= x_processor_processed[31];
x_input[30:23] <= x_processor_processed[30:23] - 8'h01;
x_input[22:0] <= x_processor_processed[22:0];
y_input[31] <= 1'b0;
y_input[30:23] <= y_processor_processed[30:23] - 8'h01;
y_input[22:0] <= y_processor_processed[22:0];
z_input <= 32'h00000000;
load <= 1'b1;
end
nat_log:
begin
mode <= hyperbolic;
operation <= vectoring;
x_input <= x_processor_processed;
y_input[30:0] <= y_processor_processed[30:0];
y_input[31] <= 1'b0;
z_input <= 32'h00000000;
load <= 1'b1;
NatLogFlag <= 1'b1;
end
endcase
end
if (stall == 1'b1) begin
load <= 1'b0;
end
end
end
endmodule
|
/*
* RS-232 asynchronous TX module
* Copyright (C) 2010 Donna Polehn <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module serial_atx (
input clk,
input txd_start,
input baud1tick, // Desired baud rate
input [7:0] txd_data,
output reg txd, // Put together the start, data and stop bits
output txd_busy
);
// Transmitter state machine
parameter RegisterInputData = 1; // in RegisterInputData mode, the input doesn't have to stay valid while the character is been transmitted
reg [3:0] state;
wire BaudTick = txd_busy ? baud1tick : 1'b0;
wire txd_ready;
reg [7:0] txd_dataReg;
// Continuous assignments
assign txd_ready = (state==0);
assign txd_busy = ~txd_ready;
always @(posedge clk) if(txd_ready & txd_start) txd_dataReg <= txd_data;
wire [7:0] txd_dataD = RegisterInputData ? txd_dataReg : txd_data;
always @(posedge clk)
case(state)
4'b0000: if(txd_start) state <= 4'b0001;
4'b0001: if(BaudTick) state <= 4'b0100;
4'b0100: if(BaudTick) state <= 4'b1000; // start
4'b1000: if(BaudTick) state <= 4'b1001; // bit 0
4'b1001: if(BaudTick) state <= 4'b1010; // bit 1
4'b1010: if(BaudTick) state <= 4'b1011; // bit 2
4'b1011: if(BaudTick) state <= 4'b1100; // bit 3
4'b1100: if(BaudTick) state <= 4'b1101; // bit 4
4'b1101: if(BaudTick) state <= 4'b1110; // bit 5
4'b1110: if(BaudTick) state <= 4'b1111; // bit 6
4'b1111: if(BaudTick) state <= 4'b0010; // bit 7
4'b0010: if(BaudTick) state <= 4'b0011; // stop1
4'b0011: if(BaudTick) state <= 4'b0000; // stop2
default: if(BaudTick) state <= 4'b0000;
endcase
reg muxbit; // Output mux
always @( * )
case(state[2:0])
3'd0: muxbit <= txd_dataD[0];
3'd1: muxbit <= txd_dataD[1];
3'd2: muxbit <= txd_dataD[2];
3'd3: muxbit <= txd_dataD[3];
3'd4: muxbit <= txd_dataD[4];
3'd5: muxbit <= txd_dataD[5];
3'd6: muxbit <= txd_dataD[6];
3'd7: muxbit <= txd_dataD[7];
endcase
always @(posedge clk) txd <= (state<4) | (state[3] & muxbit); // register the output to make it glitch free
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S15_TB_V
`define SKY130_FD_SC_HD__CLKDLYBUF4S15_TB_V
/**
* clkdlybuf4s15: Clock Delay Buffer 4-stage 0.15um length inner stage
* gates.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__clkdlybuf4s15.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hd__clkdlybuf4s15 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S15_TB_V
|
// file: Clock48MHZ_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge LOCKED)
module Clock48MHZ_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 10.000*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bits of the sampling counters
wire [4:1] COUNT;
// Status and control signals
wire LOCKED;
reg COUNTER_RESET = 0;
wire [4:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
real period1;
real ref_period1;
localparam ref_period1_clkin1 = (10.000*1*31.750*1000/15.250);
time prev_rise1;
real period2;
real ref_period2;
localparam ref_period2_clkin1 = (10.000*1*8*1000/15.250);
time prev_rise2;
real period3;
real ref_period3;
localparam ref_period3_clkin1 = (10.000*1*15*1000/15.250);
time prev_rise3;
real period4;
real ref_period4;
localparam ref_period4_clkin1 = (10.000*1*103*1000/15.250);
time prev_rise4;
reg [13:0] timeout_counter = 14'b00000000000000;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
$display ("Timing checks are not valid");
COUNTER_RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*19.5)
COUNTER_RESET = 0;
#(PER1*1)
$display ("Timing checks are valid");
test_phase = "counting";
#(PER1*COUNT_PHASE);
if ((period1 -ref_period1_clkin1) <= 100 && (period1 -ref_period1_clkin1) >= -100) begin
$display("Freq of CLK_OUT[1] ( in MHz ) : %0f\n", /period1);
end else
$display("ERROR: Freq of CLK_OUT[1] is not correct");
if ((period2 -ref_period2_clkin1) <= 100 && (period2 -ref_period2_clkin1) >= -100) begin
$display("Freq of CLK_OUT[2] ( in MHz ) : %0f\n", /period2);
end else
$display("ERROR: Freq of CLK_OUT[2] is not correct");
if ((period3 -ref_period3_clkin1) <= 100 && (period3 -ref_period3_clkin1) >= -100) begin
$display("Freq of CLK_OUT[3] ( in MHz ) : %0f\n", /period3);
end else
$display("ERROR: Freq of CLK_OUT[3] is not correct");
if ((period4 -ref_period4_clkin1) <= 100 && (period4 -ref_period4_clkin1) >= -100) begin
$display("Freq of CLK_OUT[4] ( in MHz ) : %0f\n", /period4);
end else
$display("ERROR: Freq of CLK_OUT[4] is not correct");
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
always@(posedge CLK_IN1) begin
timeout_counter <= timeout_counter + 1'b1;
if (timeout_counter == 14'b10000000000000) begin
if (LOCKED != 1'b1) begin
$display("ERROR : NO LOCK signal");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
end
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
Clock48MHZ_exdes
dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.LOCKED (LOCKED));
// Freq Check
initial
prev_rise1 = 0;
always @(posedge CLK_OUT[1])
begin
if (prev_rise1 != 0)
period1 = $time - prev_rise1;
prev_rise1 = $time;
end
initial
prev_rise2 = 0;
always @(posedge CLK_OUT[2])
begin
if (prev_rise2 != 0)
period2 = $time - prev_rise2;
prev_rise2 = $time;
end
initial
prev_rise3 = 0;
always @(posedge CLK_OUT[3])
begin
if (prev_rise3 != 0)
period3 = $time - prev_rise3;
prev_rise3 = $time;
end
initial
prev_rise4 = 0;
always @(posedge CLK_OUT[4])
begin
if (prev_rise4 != 0)
period4 = $time - prev_rise4;
prev_rise4 = $time;
end
endmodule
|
/*
* The MIT License (MIT)
*
* Copyright (c) 2015 Stefan Wendler
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
/**
* Simple UART TX module to send bytes via UART.
*
* inputs:
* clk clock maintaining the correct slots for the desired baudrate
* send enable sending with 1, disable with 0
* data data byte to transmit
*
* outputs:
* tx bits to send to the UART line
* ready set to 1 if data byte is transmitted, 0 otherwise
*/
module uart_tx(
input clk,
input send,
input [7:0] data,
output tx,
output ready
);
reg [7:0] bit_count;
reg [10:0] msg;
reg r_tx;
reg r_ready;
initial begin
bit_count <= 0;
msg <= 0;
r_tx <= 0;
r_ready <= 0;
end
always @(posedge clk) begin
if(send && !msg) begin
// add start bit and stop bit + pause
msg <= {2'b11, data, 1'b0};
end
if(msg) begin
r_tx <= msg[0];
msg <= msg >> 1;
end
end
assign tx = r_tx;
assign ready = !msg;
endmodule
/**
* Top module receiving commands from remote control. Each channel (A..D) of
* the remote switches a LED (0..3). For each received state, the following
* character is send to the UART:
*
* A - channel A, ON
* a - channel A, OFF
* B - channel B, ON
* b - channel B, OFF
* C - channel C, ON
* c - channel C, OFF
* D - channel D, ON
* d - channel D, OFF
*
* Each state is reportet only once. Repeated presses regarding the same state
* are not send.
*
* inputs:
* clk_12M 12MHz input clock
* in input from radio
*
* outputs:
* LED all the 7 LEDs from the MachXO2 eval board
* ready the ready state from the rcswitch_receive module
*/
module top(
input clk_12M,
input in,
output [7:0] LED,
output tx,
output ready
);
reg [7:0] r_led;
reg [1:0] chan_id;
reg [7:0] tx_data;
reg [7:0] tx_data_prev;
initial begin
r_led[7:0] = 0;
chan_id = 0;
tx_data = 8'd78;
tx_data_prev = 8'd78;
end
wire clk_rcswitch;
clockdiv #(1000) clockdiv_inst1 (
.clk_i(clk_12M),
.clk_o(clk_rcswitch)
);
wire [39:0] addr;
wire [39:0] chan;
wire [15:0] stat;
// the receive instance
rcswitch_receive rcswitch_receive_inst1 (
.clk(clk_rcswitch),
.in(in),
.rst(1'b0), // no reset
.addr(addr),
.chan(chan),
.stat(stat),
.ready(ready)
);
wire clk_uart;
// we need a clock with a cycle of 104us for 9600Baud (1/ 9600 * )
// we need a clock with a cycle of 8.7us for 115200Baud (1/115200 * )
// 12MHz ~ 12us, the devider is then <baud-us>*12/2
// - for 9600: 104 * 12 / 2 = 624
// - for 115200: 8.68 * 12 / 2 = 52
// clockdiv #(624) clockdiv_inst2 (
clockdiv #(52) clockdiv_inst2 (
.clk_i(clk_12M),
.clk_o(clk_uart)
);
wire send;
wire uart_ready;
uart_tx uart_tx_inst(
.clk(clk_uart),
.send(send),
.data(tx_data),
.tx(tx),
.ready(uart_ready)
);
always @(posedge uart_ready) begin
// send each received state only once
tx_data_prev <= tx_data;
end
assign send = (tx_data != tx_data_prev);
// ready indicates a new message was received
always @(posedge ready) begin
// check if the message matches our addresss
if(addr == 40'h8888888888) begin
// see which channel is addressed (A, B, C or D)
if(chan == 40'h888E8E8E8E) begin
chan_id = 0;
tx_data = 8'd65; // ASCII A
end
else if(chan == 40'h8E888E8E8E) begin
chan_id = 1;
tx_data = 8'd66; // ASCII B
end
else if(chan == 40'h8E8E888E8E) begin
chan_id = 2;
tx_data = 8'd67; // ASCII C
end
else if(chan == 40'h8E8E8E888E) begin
chan_id = 3;
tx_data = 8'd68; // ASCII D
end
// see what state is requested (ON or OFF)
if(stat == 16'h8E88) begin
r_led[chan_id] = 1'b0;
tx_data = tx_data + 32; // a, b, c or d
end
else if(stat == 16'h888E) begin
r_led[chan_id] = 1'b1;
end
end
end
assign LED = ~r_led;
endmodule
|
//код модуля на verilog
module ay_note_ram(addr, data);
input wire [6:0] addr;
output wire [11:0] data; //12 бит - максимум
reg [11:0] note_ram [0:127];
initial begin
note_ram[0] <= 12'd03977;
note_ram[1] <= 12'd03977;
note_ram[2] <= 12'd03977;
note_ram[3] <= 12'd03977;
note_ram[4] <= 12'd03977;
note_ram[5] <= 12'd03977;
note_ram[6] <= 12'd03977;
note_ram[7] <= 12'd03977;
note_ram[8] <= 12'd03977;
note_ram[9] <= 12'd03977;
note_ram[10] <= 12'd03977;
note_ram[11] <= 12'd03977;
note_ram[12] <= 12'd03977;
note_ram[13] <= 12'd03977;
note_ram[14] <= 12'd03977;
note_ram[15] <= 12'd03977;
note_ram[16] <= 12'd03977;
note_ram[17] <= 12'd03977;
note_ram[18] <= 12'd03977;
note_ram[19] <= 12'd03977;
note_ram[20] <= 12'd03977;
note_ram[21] <= 12'd03977;
note_ram[22] <= 12'd03754;
note_ram[23] <= 12'd03543;
note_ram[24] <= 12'd03344;
note_ram[25] <= 12'd03157;
note_ram[26] <= 12'd02980;
note_ram[27] <= 12'd02812;
note_ram[28] <= 12'd02655;
note_ram[29] <= 12'd02506;
note_ram[30] <= 12'd02365;
note_ram[31] <= 12'd02232;
note_ram[32] <= 12'd02107;
note_ram[33] <= 12'd01989;
note_ram[34] <= 12'd01877;
note_ram[35] <= 12'd01772;
note_ram[36] <= 12'd01672;
note_ram[37] <= 12'd01578;
note_ram[38] <= 12'd01490;
note_ram[39] <= 12'd01406;
note_ram[40] <= 12'd01327;
note_ram[41] <= 12'd01253;
note_ram[42] <= 12'd01182;
note_ram[43] <= 12'd01116;
note_ram[44] <= 12'd01053;
note_ram[45] <= 12'd0994;
note_ram[46] <= 12'd0939;
note_ram[47] <= 12'd0886;
note_ram[48] <= 12'd0836;
note_ram[49] <= 12'd0789;
note_ram[50] <= 12'd0745;
note_ram[51] <= 12'd0703;
note_ram[52] <= 12'd0664;
note_ram[53] <= 12'd0626;
note_ram[54] <= 12'd0591;
note_ram[55] <= 12'd0558;
note_ram[56] <= 12'd0527;
note_ram[57] <= 12'd0497;
note_ram[58] <= 12'd0469;
note_ram[59] <= 12'd0443;
note_ram[60] <= 12'd0418;
note_ram[61] <= 12'd0395;
note_ram[62] <= 12'd0372;
note_ram[63] <= 12'd0352;
note_ram[64] <= 12'd0332;
note_ram[65] <= 12'd0313;
note_ram[66] <= 12'd0296;
note_ram[67] <= 12'd0279;
note_ram[68] <= 12'd0263;
note_ram[69] <= 12'd0249;
note_ram[70] <= 12'd0235;
note_ram[71] <= 12'd0221;
note_ram[72] <= 12'd0209;
note_ram[73] <= 12'd0197;
note_ram[74] <= 12'd0186;
note_ram[75] <= 12'd0176;
note_ram[76] <= 12'd0166;
note_ram[77] <= 12'd0157;
note_ram[78] <= 12'd0148;
note_ram[79] <= 12'd0140;
note_ram[80] <= 12'd0132;
note_ram[81] <= 12'd0124;
note_ram[82] <= 12'd0117;
note_ram[83] <= 12'd0111;
note_ram[84] <= 12'd0105;
note_ram[85] <= 12'd099;
note_ram[86] <= 12'd093;
note_ram[87] <= 12'd088;
note_ram[88] <= 12'd083;
note_ram[89] <= 12'd078;
note_ram[90] <= 12'd074;
note_ram[91] <= 12'd070;
note_ram[92] <= 12'd066;
note_ram[93] <= 12'd062;
note_ram[94] <= 12'd059;
note_ram[95] <= 12'd055;
note_ram[96] <= 12'd052;
note_ram[97] <= 12'd049;
note_ram[98] <= 12'd047;
note_ram[99] <= 12'd044;
note_ram[100] <= 12'd041;
note_ram[101] <= 12'd039;
note_ram[102] <= 12'd037;
note_ram[103] <= 12'd035;
note_ram[104] <= 12'd033;
note_ram[105] <= 12'd031;
note_ram[106] <= 12'd029;
note_ram[107] <= 12'd028;
note_ram[108] <= 12'd026;
note_ram[109] <= 12'd025;
note_ram[110] <= 12'd023;
note_ram[111] <= 12'd022;
note_ram[112] <= 12'd021;
note_ram[113] <= 12'd020;
note_ram[114] <= 12'd018;
note_ram[115] <= 12'd017;
note_ram[116] <= 12'd016;
note_ram[117] <= 12'd016;
note_ram[118] <= 12'd015;
note_ram[119] <= 12'd014;
note_ram[120] <= 12'd013;
note_ram[121] <= 12'd012;
note_ram[122] <= 12'd012;
note_ram[123] <= 12'd011;
note_ram[124] <= 12'd010;
note_ram[125] <= 12'd010;
note_ram[126] <= 12'd09;
note_ram[127] <= 12'd09;
end
assign data = note_ram[addr];
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<long long> translate; long long get(long long x) { return lower_bound(translate.begin(), translate.end(), x) - translate.begin(); } int main() { ios_base::sync_with_stdio(0); long long n; cin >> n; if (n == 1) { cout << 1 << endl; return 0; } long long a[n]; for (long long i = 0; i < n; i++) { cin >> a[i]; translate.push_back(a[i]); } translate.push_back(0); sort(translate.begin(), translate.end()); translate.resize(unique(translate.begin(), translate.end()) - translate.begin()); long long b[n]; for (long long i = 0; i < n; i++) { b[i] = get(a[i]); } long long d[n][translate.size()]; fill(d[0], d[n - 1] + translate.size(), INT_MAX); for (long long i = 0; i < n - 1; i++) { long long benefit = 0; for (long long j = 0; j <= b[i]; j++) { if (i == 0) { d[i][j] = translate[j] + (int)(j < b[i]); } if (d[i][benefit] + translate[j] - translate[benefit] >= d[i][j]) { benefit = j; } long long temp = j; if (j > b[i + 1]) temp = b[i + 1]; d[i + 1][temp] = min(d[i + 1][temp], d[i][benefit] + max(translate[temp] - translate[benefit], 0ll) + (int)(temp != b[i + 1])); } if (b[i + 1] > b[i]) { for (long long j = b[i] + 1; j <= b[i + 1]; j++) { long long znach = d[i][benefit] + translate[j] - translate[benefit] + (int)(j != b[i + 1]); d[i + 1][j] = min(d[i + 1][j], znach); } } } cout << *min_element(d[n - 1], d[n - 1] + translate.size()); }
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/spartan4/ODDR2.v,v 1.1 2004/06/21 21:45:36 wloo Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Dual Data Rate Output D Flip-Flop
// /___/ /\ Filename : ODDR2.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:52 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
`timescale 1 ps / 1 ps
module ODDR2 (Q, C0, C1, CE, D0, D1, R, S);
output Q;
input C0;
input C1;
input CE;
input D0;
input D1;
tri0 GSR = glbl.GSR;
input R;
input S;
parameter DDR_ALIGNMENT = "NONE";
parameter INIT = 1'b0;
parameter SRTYPE = "SYNC";
reg q_out, q_d0_c1_out_int, q_d1_c0_out_int;
buf buf_q (Q, q_out);
initial begin
if ((INIT != 1'b0) && (INIT != 1'b1)) begin
$display("Attribute Syntax Error : The attribute INIT on ODDR2 instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT);
$finish;
end
if ((DDR_ALIGNMENT != "NONE") && (DDR_ALIGNMENT != "C0") && (DDR_ALIGNMENT != "C1")) begin
$display("Attribute Syntax Error : The attribute DDR_ALIGNMENT on ODDR2 instance %m is set to %s. Legal values for this attribute are NONE, C0 or C1.", DDR_ALIGNMENT);
$finish;
end
if ((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin
$display("Attribute Syntax Error : The attribute SRTYPE on ODDR2 instance %m is set to %s. Legal values for this attribute are ASYNC or SYNC.", SRTYPE);
$finish;
end
end // initial begin
always @(GSR or R or S) begin
if (GSR == 1) begin
assign q_out = INIT;
assign q_d0_c1_out_int = INIT;
assign q_d1_c0_out_int = INIT;
end
else begin
deassign q_out;
deassign q_d0_c1_out_int;
deassign q_d1_c0_out_int;
if (SRTYPE == "ASYNC") begin
if (R == 1) begin
assign q_out = 0;
assign q_d0_c1_out_int = 0;
assign q_d1_c0_out_int = 0;
end
else if (R == 0 && S == 1) begin
assign q_out = 1;
assign q_d0_c1_out_int = 1;
assign q_d1_c0_out_int = 1;
end
end // if (SRTYPE == "ASYNC")
end // if (GSR == 1'b0)
end // always @ (GSR or R or S)
always @(posedge C0) begin
if (R == 1 && SRTYPE == "SYNC") begin
q_out <= 0;
q_d1_c0_out_int <= 0;
end
else if (R == 0 && S == 1 && SRTYPE == "SYNC") begin
q_out <= 1;
q_d1_c0_out_int <= 1;
end
else if (CE == 1 && R == 0 && S == 0) begin
if (DDR_ALIGNMENT == "C1")
q_out <= q_d0_c1_out_int;
else begin
q_out <= D0;
if (DDR_ALIGNMENT == "C0")
q_d1_c0_out_int <= D1;
end
end // if (CE == 1 && R == 0 && S == 0)
end // always @ (posedge C0)
always @(posedge C1) begin
if (R == 1 && SRTYPE == "SYNC") begin
q_out <= 0;
q_d0_c1_out_int <= 0;
end
else if (R == 0 && S == 1 && SRTYPE == "SYNC") begin
q_out <= 1;
q_d0_c1_out_int <= 1;
end
else if (CE == 1 && R == 0 && S == 0) begin
if (DDR_ALIGNMENT == "C0")
q_out <= q_d1_c0_out_int;
else begin
q_out <= D1;
if (DDR_ALIGNMENT == "C1")
q_d0_c1_out_int <= D0;
end
end // if (CE == 1 && R == 0 && S == 0)
end // always @ (negedge c_in)
specify
if (C0) (C0 => Q) = (100, 100);
if (C1) (C1 => Q) = (100, 100);
specparam PATHPULSE$ = 0;
endspecify
endmodule // ODDR2
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#include <bits/stdc++.h> using namespace std; int main() { long long t; cin >> t; while (t-- > 0) { int n; string s; cin >> n >> s; vector<int> a(n, 0), b(n, 0), c; int flag1 = 1, flag2 = 1; for (int i = 0; i < n - 1; i++) { if (s[i] == < ) { b[i] = flag1++; } } for (int i = n - 2; i >= 0; i--) { if (s[i] == < ) { while (i > 0 && s[i - 1] == < ) { i--; } int x = i; while (s[x] == < ) { a[x] = flag2++; x++; } } } for (int i = n - 1; i >= 0; i--) { if (b[i] == 0) { b[i] = flag1++; } if (a[i] == 0) { a[i] = flag2++; } } for (int i = 0; i < n; i++) { cout << a[i] << ; } cout << n ; for (int i = 0; i < n; i++) { cout << b[i] << ; } cout << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); struct Aho { enum { ALPHA = 30 }; struct Node { int p = -1, link = -1, superLink = -1; int next[ALPHA], go[ALPHA]; bool leaf = false; vector<int> leaves; char ch; Node(int p = -1, char c = $ ) : p(p), ch(c) { fill(begin(next), end(next), -1); fill(begin(go), end(go), -1); } }; vector<Node> nodes; void insert(string &s, int id) { int v = 0; for (char ch : s) { int c = ch - a ; if (nodes[v].next[c] == -1) { Node aux = Node(v, ch); nodes[v].next[c] = (int)nodes.size(); nodes.push_back(aux); } v = nodes[v].next[c]; } nodes[v].leaf = true; nodes[v].leaves.push_back(id); } int go(int v, char ch) { int c = ch - a ; if (nodes[v].go[c] == -1) { if (nodes[v].next[c] != -1) { nodes[v].go[c] = nodes[v].next[c]; } else { if (v == 0) nodes[v].go[c] = 0; else nodes[v].go[c] = go(nodes[v].link, ch); } } return nodes[v].go[c]; } Aho(vector<string> &vs) { Node root = Node(); nodes.push_back(root); int id = 0; for (auto s : vs) insert(s, id++); queue<int> fila; nodes[0].link = 0; for (int &v : nodes[0].next) { if (v != -1) { fila.push(v); nodes[v].link = 0; } else v = 0; } while (!fila.empty()) { int v = fila.front(); fila.pop(); for (int u : nodes[v].next) { if (u != -1) { int c = nodes[u].ch - a ; int fail = nodes[v].link; while (nodes[fail].next[c] == -1) { fail = nodes[fail].link; } fail = nodes[fail].next[c]; for (int id : nodes[fail].leaves) { nodes[u].leaves.push_back(id); } nodes[u].link = fail; fila.push(u); } } } } int find(int idx, int p) { if (idx != p and (nodes[idx].leaf or idx == 0)) return idx; if (nodes[idx].superLink == -1) { nodes[idx].superLink = find(nodes[idx].link, p); } return nodes[idx].superLink; } vector<vector<int> > findAll(string s, int n) { vector<vector<int> > res(n + 5); int idx = 0; for (int i = 0; i < (int)s.size(); i++) { char ch = s[i]; idx = go(idx, ch); for (int id : nodes[idx].leaves) res[i].push_back(id); } return res; } }; string s; string ss[100005]; int n; int k[100005]; int32_t main() { cin.tie(NULL); cout.tie(NULL); ios_base::sync_with_stdio(0); cin >> s >> n; vector<string> vs; for (int i = 0; i < n; i++) { cin >> k[i] >> ss[i]; vs.push_back(ss[i]); } Aho ac = Aho(vs); auto res = ac.findAll(s, (int)s.size()); vector<vector<int> > pos(n + 5); for (int i = 0; i < (int)res.size(); i++) { for (int idx : res[i]) { pos[idx].push_back(i); } } for (int i = 0; i < n; i++) { int res = 0x3f3f3f3f; if ((int)pos[i].size() < k[i]) { cout << -1 << n ; continue; } for (int j = 0; j + k[i] <= (int)pos[i].size(); j++) { res = min(res, pos[i][k[i] + j - 1] - pos[i][j] + (int)ss[i].size()); } cout << res << n ; } return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 11; const int Inf = 1e9; vector<int> dx[3] = { {-1, 0, 0, 1}, {-1, -1, 1, 1}, {-1, 1, 2, 2, 1, -1, -2, -2}}; vector<int> dy[3] = { {0, -1, 1, 0}, {-1, 1, -1, 1}, {-2, -2, -1, 1, 2, 2, -1, 1}}; int n; pair<int, int> g[3][3][N][N][N][N]; int a[N][N]; bool ok(int x, int y) { return 0 <= x && x < n && 0 <= y && y < n; } void build() { for (int x = 0; x < n; ++x) { for (int y = 0; y < n; ++y) { for (int t = 0; t < 3; ++t) { for (int i = 0; i < dx[t].size(); ++i) { if (t == 2) { int cx = x + dx[t][i]; int cy = y + dy[t][i]; if (ok(cx, cy)) { g[t][t][x][y][cx][cy] = {1, 0}; } } else { for (int k = 1; k <= n; ++k) { int cx = x + dx[t][i] * k; int cy = y + dy[t][i] * k; if (ok(cx, cy)) { g[t][t][x][y][cx][cy] = {1, 0}; } } } } } } } } pair<int, int> sm(pair<int, int> a, pair<int, int> b) { return {a.first + b.first, a.second + b.second}; } void count(int x, int y, vector<pair<int, int>> &t) { if (a[x][y] == n * n) { return; } int ix = -1, jx = -1; for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { if (a[x][y] + 1 == a[i][j]) { ix = i; jx = j; } } } vector<pair<int, int>> nt(3, {Inf, Inf}); for (int t1 = 0; t1 < 3; ++t1) { for (int t2 = 0; t2 < 3; ++t2) { nt[t2] = min(nt[t2], sm(t[t1], g[t1][t2][x][y][ix][jx])); } } t = nt; count(ix, jx, t); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.setf(ios::fixed); cout.precision(20); cin >> n; for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { cin >> a[i][j]; } } for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { for (int k = 0; k < n; ++k) { for (int t = 0; t < n; ++t) { for (int t1 = 0; t1 < 3; ++t1) { for (int t2 = 0; t2 < 3; ++t2) { g[t1][t2][i][j][k][t] = {Inf, Inf}; } } } } } } for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { for (int t1 = 0; t1 < 3; ++t1) { for (int t2 = 0; t2 < 3; ++t2) { if (t1 == t2) { g[t1][t2][i][j][i][j] = {0, 0}; } else { g[t1][t2][i][j][i][j] = {1, 1}; } } } } } build(); for (int t3 = 0; t3 < 3; ++t3) { for (int kx = 0; kx < n; ++kx) { for (int ky = 0; ky < n; ++ky) { for (int t1 = 0; t1 < 3; ++t1) { for (int ix = 0; ix < n; ++ix) { for (int iy = 0; iy < n; ++iy) { for (int t2 = 0; t2 < 3; ++t2) { for (int jx = 0; jx < n; ++jx) { for (int jy = 0; jy < n; ++jy) { g[t1][t2][ix][iy][jx][jy] = min(g[t1][t2][ix][iy][jx][jy], sm(g[t1][t3][ix][iy][kx][ky], g[t3][t2][kx][ky][jx][jy])); } } } } } } } } } int ix = -1, jx = -1; for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { if (a[i][j] == 1) { ix = i; jx = j; } } } vector<pair<int, int>> t(3); count(ix, jx, t); pair<int, int> ans = {Inf, Inf}; for (int i = 0; i < 3; ++i) { ans = min(ans, t[i]); } cout << ans.first << << ans.second << n ; }
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#include <bits/stdc++.h> using namespace std; #define ll long long int const int N=1000005; //vector<int>prime; bool prime[N]; void sieve() { int k=sqrt(N-2); for(int i=1;i<=N-2;++i) prime[i]=true; for(int i=2;i<=k;++i) { if(prime[i]) { for(int k=i*i;k<=N-2;k+=i) { prime[k]=false; //pf[k]=i; } } } } void solve() { int d; cin>>d; int x; int y; for(int i=d+1;;i++) { if(prime[i]) { x=i; break; } } for(int i=x+d;;i++) { if(prime[i]) { y=i; break; } } cout<<x*y<< n ; } int main() { // your code goes here ios_base::sync_with_stdio(false); cin.tie(NULL); sieve(); int t; cin>>t; while(t--) { solve(); } return 0; }
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#include <bits/stdc++.h> using namespace std; int n, m, l, r, q; map<pair<int, int>, int> vi; int V[100005 << 2], ly[100005 << 2]; void push_down(int o) { if (ly[o]) { ly[o << 1] |= ly[o]; ly[o << 1 | 1] |= ly[o]; V[o << 1] |= ly[o]; V[o << 1 | 1] |= ly[o]; ly[o] = 0; } } void push_up(int o) { V[o] = V[o << 1] & V[o << 1 | 1]; } void ud(int o, int l, int r, int L, int R, int x) { int mid = (l + r) / 2; if (L <= l && r <= R) { V[o] |= x; ly[o] |= x; return; } push_down(o); if (L <= mid) ud(o << 1, l, mid, L, R, x); if (R > mid) ud(o << 1 | 1, mid + 1, r, L, R, x); push_up(o); } int qy(int o, int l, int r, int L, int R) { int mid = (l + r) / 2; if (L <= l && r <= R) return V[o]; push_down(o); int ans = (1 << 30) - 1; if (L <= mid) ans &= qy(o << 1, l, mid, L, R); if (R > mid) ans &= qy(o << 1 | 1, mid + 1, r, L, R); push_up(o); return ans; } int main() { cin >> n >> m; int ok = 1; for (int i = 0; i < m; i++) { scanf( %d%d%d , &l, &r, &q); int tp = qy(1, 1, n, l, r); if (vi[make_pair(l, r)]) { if (tp != q) { ok = 0; } } if (!ok) continue; vi[make_pair(l, r)] = 1; if ((tp & q) == tp) ud(1, 1, n, l, r, q); else ok = 0; } if (!ok) { puts( NO ); return 0; } printf( YES n ); for (int i = 1; i <= n; i++) printf( %d , qy(1, 1, n, i, i)); }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// UART RX Module
// Paul Mumby 2012
// Originally derived from code examples at:
// http://www.fpga4fun.com
//////////////////////////////////////////////////////////////////////////////////
module uart_rx(
clk, //Communications Clock
rx, //Tx IO Pin
rx_byte, //Byte to Transmit
data_ready, //Start Transmitting Byte
busy, //Tx Busy Flag
error
);
//Parameters:
//================================================
parameter CLOCK = 25000000; //Overridden by parent UART core
parameter BAUD = 9600; //Overridden by parent UART core
parameter SAMPLE_POINT = 8; //Overridden by parent
//IO Definitions:
//================================================
input clk;
wire baudtick;
input rx;
output reg [7:0] rx_byte;
output reg data_ready;
output busy;
output reg error;
//Register/Wire Definitions:
//================================================
reg [1:0] rx_sync;
reg [1:0] rx_counter;
reg rx_bit;
reg [3:0] state;
reg [3:0] bit_spacing;
reg [4:0] data_gap;
reg rx_buf1, rx_buf2;
wire next_bit;
wire rx_n;
//BUFG Instatiation:
//================================================
//Module Instantiation:
//================================================
uart_baudgenerator #(
.CLOCK(CLOCK),
.BAUD(BAUD*8), //Oversampled
.ROUNDBITS(8) //Higher frequency requires more rounding
) BAUDGEN (
.clk(clk),
.baudtick(baudtick)
);
//Assignments:
//================================================
//Inverted rx for stability:
assign rx_n = ~rx_buf2;
//Note: value below for bit_spacing check, defines where data sampling occurs
assign next_bit = (bit_spacing==SAMPLE_POINT);
//Gap Detection:
assign busy = ~data_gap[4];
//Toplevel Logic:
//================================================
//Double Buffering
always @(posedge clk)
begin
rx_buf1 <= rx;
rx_buf2 <= rx_buf1;
end
//Oversampling & Sync of RX Input to clock
always @(posedge clk)
if(baudtick)
rx_sync <= {rx_sync[0], rx_n};
//RX Line Noise Filter
always @(posedge clk)
if(baudtick)
begin
if(rx_sync[1] && rx_counter!=2'b11)
rx_counter <= rx_counter + 2'h1;
if(~rx_sync[1] && rx_counter!=2'b00)
rx_counter <= rx_counter - 2'h1;
if(rx_counter==2'b00)
rx_bit <= 1'b0;
else if(rx_counter==2'b11)
rx_bit <= 1'b1;
end
//RX State Machine
always @(posedge clk)
if(baudtick)
case(state)
4'b0000: if(rx_bit) state <= 4'b1000; // start bit found?
4'b1000: if(next_bit) state <= 4'b1001; // bit 0
4'b1001: if(next_bit) state <= 4'b1010; // bit 1
4'b1010: if(next_bit) state <= 4'b1011; // bit 2
4'b1011: if(next_bit) state <= 4'b1100; // bit 3
4'b1100: if(next_bit) state <= 4'b1101; // bit 4
4'b1101: if(next_bit) state <= 4'b1110; // bit 5
4'b1110: if(next_bit) state <= 4'b1111; // bit 6
4'b1111: if(next_bit) state <= 4'b0001; // bit 7
4'b0001: if(next_bit) state <= 4'b0000; // stop bit
default: state <= 4'b0000;
endcase
//Bit Spacing Detection
always @(posedge clk)
if(state==0)
bit_spacing <= 4'b0000;
else if(baudtick)
bit_spacing <= {bit_spacing[2:0] + 4'b0001} | {bit_spacing[3], 3'b000};
//Shift Register
always @(posedge clk)
if(baudtick && next_bit && state[3])
rx_byte <= {~rx_bit, rx_byte[7:1]};
//Data Ready & Error Detection
always @(posedge clk)
begin
data_ready <= (baudtick && next_bit && state==4'b0001 && ~rx_bit); // ready only if the stop bit is received
error <= (baudtick && next_bit && state==4'b0001 && rx_bit); // error if no stop bit received
end
//Idle Detection
always @(posedge clk)
if(state!=0)
data_gap <= 5'h00;
else if(baudtick & ~data_gap[4])
data_gap <= data_gap + 5'h01;
endmodule
|
/*
* Copyright (c) 2002 Richard M. Myers
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
`timescale 10 ns/ 10 ns
module top ;
reg clk ;
reg [11:0] x_os_integ, y_os_integ;
reg [5:0] x_os, y_os;
initial
begin
//$dumpfile("show_math.vcd");
//$dumpvars(1, top);
clk = 1'h0 ;
x_os = 6'h01;
y_os = 6'h3f;
x_os_integ = 12'h000;
y_os_integ = 12'h000;
end
initial
begin
#60;
forever #3 clk = ~clk ; // 16Mhz
end
always @( posedge clk )
begin
// Integration period set above depending on configured modem speed.
x_os_integ <= x_os_integ + {{6{x_os[5]}}, {x_os[5:0]}};
y_os_integ <= y_os_integ + {{6{y_os[5]}}, {y_os[5:0]}};
$display ("%x %x", x_os_integ, y_os_integ);
end
initial
begin
#200 $finish(0);
end
endmodule
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#include <bits/stdc++.h> using namespace std; struct edge { int t, f, w; bool operator<(const edge& e) const { return w > e.w; } edge(int from, int to, int weight) { t = to; f = from; w = weight; } }; const double EPS = (1e-9); class UnionFind { public: vector<int> p, rank, setSize; int numSets; UnionFind(int N) { setSize.assign(N, 1); numSets = N; rank.assign(N, 0); p.assign(N, 0); for (int i = 0; i < N; i++) p[i] = i; } int findSet(int i) { return (p[i] == i) ? i : (p[i] = findSet(p[i])); } bool isSameSet(int i, int j) { return findSet(i) == findSet(j); } void unionSet(int i, int j) { if (!isSameSet(i, j)) { numSets--; int x = findSet(i), y = findSet(j); if (rank[x] > rank[y]) { p[y] = x; setSize[x] += setSize[y]; } else { p[x] = y; setSize[y] += setSize[x]; if (rank[x] == rank[y]) rank[y]++; } } } int numDisjointSets() { return numSets; } int sizeOfSet(int i) { return setSize[findSet(i)]; } }; long long root(long long x) { long long l = 0, r = 1e9 + 1; while (l < r - 1) { long long m = (l + r) / 2; if (m * m > x) r = m; else l = m; } return l; } struct line { double a, b, c; }; bool areParallel(line l1, line l2) { return (fabs(l1.a - l2.a) < EPS) && (fabs(l1.b - l2.b) < EPS); } bool areSame(line l1, line l2) { return areParallel(l1, l2) && (fabs(l1.c - l2.c) < EPS); } struct point { double x, y; point() { x = y = 0.0; } point(double _x, double _y) : x(_x), y(_y) {} bool operator<(point other) const { if (fabs(x - other.x) > EPS) return x < other.x; return y < other.y; } }; void pointsToLine(point p1, point p2, line& l) { if (fabs(p1.x - p2.x) < EPS) { l.a = 1.0; l.b = 0.0; l.c = -p1.x; } else { l.a = -(double)(p1.y - p2.y) / (p1.x - p2.x); l.b = 1.0; l.c = -(double)(l.a * p1.x) - p1.y; } } bool areIntersect(line l1, line l2, point& p) { if (areParallel(l1, l2)) return false; p.x = (l2.b * l1.c - l1.b * l2.c) / (l2.a * l1.b - l1.a * l2.b); if (fabs(l1.b) > EPS) p.y = -(l1.a * p.x + l1.c); else p.y = -(l2.a * p.x + l2.c); return true; } long long binpowmod(long long a, long long b, long long m) { a %= m; long long res = 1; while (b > 0) { if (b & 1) res = res * a % m; a = a * a % m; b >>= 1; } return res; } long long binpow(long long a, long long b) { long long res = 1; while (b > 0) { if (b & 1) res = res * a; a = a * a; b >>= 1; } return res; } int findXOR(int n) { switch (n % 4) { case 0: return n; case 1: return 1; case 2: return n + 1; case 3: return 0; } } int rangeXOR(int l, int r) { return (findXOR(l - 1) ^ findXOR(r)); } int getbit(int mask, int bit) { return (mask & (1 << bit)); } void setbit(int& mask, int bit, int val) { if (val) mask |= (1 << bit); else mask &= ~(1 << bit); } const int N = 1e5 + 1; const long long INF = 1e7 + 100; const int MOD = 1e9 + 7; class SegmentTree { private: vector<pair<int, int>> st; vector<int> lp; vector<int> A; int n; int left(int p) { return p << 1; } int right(int p) { return (p << 1) + 1; } pair<int, int> merge(pair<int, int> p1, pair<int, int> p2) { if (p1.first == p2.first) return {p1.first, p1.second + p2.second}; if (p1.first < p2.first) return p1; return p2; } void build(int p, int L, int R) { if (L == R) { st[p] = {A[L], 1}; } else { build(left(p), L, (L + R) / 2); build(right(p), (L + R) / 2 + 1, R); pair<int, int> p1 = st[left(p)], p2 = st[right(p)]; st[p] = merge(p1, p2); } } pair<int, int> rmq(int p, int L, int R, int i, int j) { if (i > R || j < L) return {-1, -1}; if (L >= i && R <= j) return st[p]; pair<int, int> p1 = rmq(left(p), L, (L + R) / 2, i, j); pair<int, int> p2 = rmq(right(p), (L + R) / 2 + 1, R, i, j); if (p1.first == -1) return p2; if (p2.first == -1) return p1; return merge(p1, p2); } void update_point(int p, int L, int R, int idx, int v) { int i = idx, j = idx; if (i > R || j < L) return; if (L == i && R == j) { A[L] = v; st[p] = {v, 1}; return; } pair<int, int> p1, p2; update_point(left(p), L, (L + R) / 2, idx, v); update_point(right(p), (L + R) / 2 + 1, R, idx, v); p1 = st[left(p)]; p2 = st[right(p)]; st[p] = merge(p1, p2); } public: SegmentTree(const vector<int>& _A) { A = _A; n = (int)A.size(); st.assign(4 * n, {0, 0}); lp.assign(4 * n, 0); build(1, 0, n - 1); } pair<int, int> rmq(int i, int j) { return rmq(1, 0, n - 1, i, j); } void update_point(int idx, int new_value) { update_point(1, 0, n - 1, idx, new_value); } }; vector<int> freq; int n; bool can(int x) { set<pair<int, int>, greater<pair<int, int>>> s; vector<int> cnt(n + 1); for (int i = 1; i <= n; ++i) { if (freq[i]) { cnt[i] = freq[i]; s.insert({cnt[i], i}); } } vector<int> b; for (int i = 0; i < n; ++i) { if (i >= x && cnt[b[i - x]] > 0) { s.insert({cnt[b[i - x]], b[i - x]}); } if (s.empty()) return false; b.push_back(s.begin()->second); s.erase(s.begin()); cnt[b.back()]--; } return true; } void solve() { cin >> n; freq.assign(n + 1, 0); for (int i = 0; i < n; ++i) { int x; cin >> x; freq[x]++; } int lo = 0, hi = n; while (hi - lo > 1) { int mid = (hi + lo) / 2; if (can(mid)) { lo = mid; } else hi = mid; } cout << lo - 1 << n ; } int main(void) { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int tc = 1; cin >> tc; while (tc--) { solve(); } }
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module top;
reg pass = 1'b1;
wire [3:0] part_idx_up, part_idx_down, part_sel;
wire [3:0] ps_array [1:0];
// Check the positive indexed part select.
// assign part_idx_up[-1+:2] = 2'b01; // We do not currently support this!
assign part_idx_up[1+:2] = 2'b01;
assign part_idx_up[3+:2] = 2'b01;
assign part_idx_up[5+:2] = 2'b01; // This should be skipped
assign part_idx_up[7+:3] = 3'b001; // This should be skipped
// Check the negative indexed part select.
// assign part_idx_down[0-:2] = 2'b10; // We do not currently support this!
assign part_idx_down[2-:2] = 2'b10;
assign part_idx_down[4-:2] = 2'b10;
assign part_idx_down[6-:2] = 2'b10; // This should be skipped
assign part_idx_down[9-:3] = 3'b100; // This should be skipped
// Check a normal constant part select.
// assign part_sel[1:-1] = 2'b01; // We do not currently support this!
assign part_sel[2:1] = 2'b01;
assign part_sel[4:3] = 2'b01;
assign part_sel[6:5] = 2'b01; // This should be skipped
assign part_sel[9:7] = 3'b001; // This should be skipped
// Check a normal constant part select on an array.
// assign ps_array[0][1:-1] = 2'b01; // We do not currently support this!
assign ps_array[0][2:1] = 2'b01;
assign ps_array[0][4:3] = 2'b01;
assign ps_array[0][6:5] = 2'b01; // This should be skipped
assign ps_array[0][9:7] = 3'b001; // This should be skipped
initial begin
#1;
if (part_idx_up !== 4'b101z) begin
$display("Failed +: select, expected 4'b101z, got %b", part_idx_up);
pass = 1'b0;
end
if (part_idx_down !== 4'b010z) begin
$display("Failed -: select, expected 4'b010z, got %b", part_idx_down);
pass = 1'b0;
end
if (part_sel !== 4'b101z) begin
$display("Failed const. part select, expected 4'b101z, got %b", part_sel);
pass = 1'b0;
end
if (ps_array[0] !== 4'b101z) begin
$display("Failed array part select, expected 4'b101z, got %b",
ps_array[0]);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
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module wb_mux_tb
(input wb_clk_i,
input wb_rst_i,
output done);
localparam NUM_SLAVES = 4;
localparam aw = 32;
localparam dw = 32;
localparam MEMORY_SIZE_WORDS = 32'h100;
localparam MEMORY_SIZE_BITS = 8;
/*TODO: Find a way to generate MATCH_ADDR and MATCH_MASK based on memory
size and number of slaves. Missing support for constant
user functions in Icarus Verilog is the blocker for this*/
localparam [dw*NUM_SLAVES-1:0] MATCH_ADDR = {32'h00000300,
32'h00000200,
32'h00000100,
32'h00000000};
localparam [dw*NUM_SLAVES-1:0] MATCH_MASK = {NUM_SLAVES{32'hffffff00}};
wire [NUM_SLAVES*aw-1:0] wbs_m2s_adr;
wire [NUM_SLAVES*dw-1:0] wbs_m2s_dat;
wire [NUM_SLAVES*4-1:0] wbs_m2s_sel;
wire [NUM_SLAVES-1:0] wbs_m2s_we ;
wire [NUM_SLAVES-1:0] wbs_m2s_cyc;
wire [NUM_SLAVES-1:0] wbs_m2s_stb;
wire [NUM_SLAVES*3-1:0] wbs_m2s_cti;
wire [NUM_SLAVES*2-1:0] wbs_m2s_bte;
wire [NUM_SLAVES*dw-1:0] wbs_s2m_dat;
wire [NUM_SLAVES-1:0] wbs_s2m_ack;
wire [NUM_SLAVES-1:0] wbs_s2m_err;
wire [NUM_SLAVES-1:0] wbs_s2m_rty;
wire [aw-1:0] wb_m2s_adr;
wire [dw-1:0] wb_m2s_dat;
wire [3:0] wb_m2s_sel;
wire wb_m2s_we ;
wire wb_m2s_cyc;
wire wb_m2s_stb;
wire [2:0] wb_m2s_cti;
wire [1:0] wb_m2s_bte;
wire [dw-1:0] wb_s2m_dat;
wire wb_s2m_ack;
wire wb_s2m_err;
wire wb_s2m_rty;
wire [31:0] slave_writes [0:NUM_SLAVES-1];
wire [31:0] slave_reads [0:NUM_SLAVES-1];
genvar i;
wb_bfm_transactor
#(.MEM_HIGH (MEMORY_SIZE_WORDS*NUM_SLAVES-1))
wb_bfm_transactor0
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_adr_o (wb_m2s_adr),
.wb_dat_o (wb_m2s_dat),
.wb_sel_o (wb_m2s_sel),
.wb_we_o (wb_m2s_we ),
.wb_cyc_o (wb_m2s_cyc),
.wb_stb_o (wb_m2s_stb),
.wb_cti_o (wb_m2s_cti),
.wb_bte_o (wb_m2s_bte),
.wb_dat_i (wb_s2m_dat),
.wb_ack_i (wb_s2m_ack),
.wb_err_i (wb_s2m_err),
.wb_rty_i (wb_s2m_rty),
//Test Control
.done(done));
integer idx;
always @(done) begin
if(done === 1'b1) begin
for(idx=0;idx<NUM_SLAVES;idx=idx+1) begin
$display("%0d writes to slave %0d", slave_writes[idx], idx);
end
$display("All tests passed!");
end
end
wb_mux
#(.num_slaves(NUM_SLAVES),
.MATCH_ADDR (MATCH_ADDR),
.MATCH_MASK (MATCH_MASK))
wb_mux0
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
// Master Interface
.wbm_adr_i (wb_m2s_adr),
.wbm_dat_i (wb_m2s_dat),
.wbm_sel_i (wb_m2s_sel),
.wbm_we_i (wb_m2s_we ),
.wbm_cyc_i (wb_m2s_cyc),
.wbm_stb_i (wb_m2s_stb),
.wbm_cti_i (wb_m2s_cti),
.wbm_bte_i (wb_m2s_bte),
.wbm_dat_o (wb_s2m_dat),
.wbm_ack_o (wb_s2m_ack),
.wbm_err_o (wb_s2m_err),
.wbm_rty_o (wb_s2m_rty),
// Wishbone Slave interface
.wbs_adr_o (wbs_m2s_adr),
.wbs_dat_o (wbs_m2s_dat),
.wbs_sel_o (wbs_m2s_sel),
.wbs_we_o (wbs_m2s_we),
.wbs_cyc_o (wbs_m2s_cyc),
.wbs_stb_o (wbs_m2s_stb),
.wbs_cti_o (wbs_m2s_cti),
.wbs_bte_o (wbs_m2s_bte),
.wbs_dat_i (wbs_s2m_dat),
.wbs_ack_i (wbs_s2m_ack),
.wbs_err_i (wbs_s2m_err),
.wbs_rty_i (wbs_s2m_rty));
generate
for(i=0;i<NUM_SLAVES;i=i+1) begin : slaves
assign slave_writes[i] = wb_mem_model0.writes;
assign slave_reads[i] = wb_mem_model0.reads;
wb_bfm_memory #(.DEBUG (0),
.mem_size_bytes(MEMORY_SIZE_WORDS*(dw/8)))
wb_mem_model0
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_adr_i (wbs_m2s_adr[i*aw+:aw] & (2**MEMORY_SIZE_BITS-1)),
.wb_dat_i (wbs_m2s_dat[i*dw+:dw]),
.wb_sel_i (wbs_m2s_sel[i*4+:4]),
.wb_we_i (wbs_m2s_we[i]),
.wb_cyc_i (wbs_m2s_cyc[i]),
.wb_stb_i (wbs_m2s_stb[i]),
.wb_cti_i (wbs_m2s_cti[i*3+:3]),
.wb_bte_i (wbs_m2s_bte[i*2+:2]),
.wb_dat_o (wbs_s2m_dat[i*dw+:dw]),
.wb_ack_o (wbs_s2m_ack[i]),
.wb_err_o (wbs_s2m_err[i]),
.wb_rty_o (wbs_s2m_rty[i]));
end // block: slaves
endgenerate
endmodule // orpsoc_tb
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#include <bits/stdc++.h> using namespace std; bool check_lucky(long long num) { while (num) { if ((num % 10) == 8) return 1; num /= 10; } return 0; } int main() { long long num; cin >> num; int flag = 0, ans = 1, f2 = 0; if (num < 0) { flag = 1; num *= (-1); } if (flag) { num--; while (1) { if (num == 0) { f2 = 1; } if (f2) { ans++; if (!num) { num++; continue; } if (check_lucky(num)) { cout << ans - 1 << endl; return 0; } num++; } else { ans++; if (check_lucky(num)) { cout << ans - 1 << endl; return 0; } num--; } } } else { num++; while (1) { ans++; if (!num) continue; if (check_lucky(num)) { cout << ans - 1 << endl; return 0; } num++; } } cout << ans << endl; }
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#include <bits/stdc++.h> using namespace std; int n, cnt = 0; map<int, int> mp; int main() { cin >> n; mp[n]++; cnt++; while (n) { n++; while (!(n % 10)) n /= 10; if (mp[n]) break; mp[n]++; cnt++; } cout << cnt << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long a; cin >> a; long long m = 0; vector<long long> c; long long b[a]; for (int i = 0; i < a; i++) { cin >> b[i]; } for (int y = 0; y < a; y++) { m = 0; for (int i = 0; i < a; i++) { long long x = abs(i - y) + i + y; x = x * b[i] * 2; m = m + x; } c.push_back(m); } sort(c.begin(), c.end()); cout << c[0]; return 0; }
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//faux_sata_hd_phy.v
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
`include "sata_defines.v"
module faux_sata_hd_phy (
//Inputs/Outputs
input rst, //reset
input clk,
//Data Interface
output reg [31:0] tx_dout,
output reg tx_is_k,
output reg tx_set_elec_idle,
output reg rx_byte_is_aligned,
input [31:0] rx_din,
input [3:0] rx_is_k,
input rx_is_elec_idle,
input comm_reset_detect,
input comm_wake_detect,
output reg tx_comm_reset,
output reg tx_comm_wake,
output [3:0] lax_state,
output reg hd_ready,
output phy_ready
);
//Parameters
parameter IDLE = 4'h0;
parameter WAIT_FOR_NO_RESET = 4'h1;
parameter SEND_INIT = 4'h2;
parameter WAIT_FOR_WAKE = 4'h3;
parameter WAIT_FOR_NO_WAKE = 4'h4;
parameter SEND_WAKE = 4'h5;
parameter STOP_SEND_WAKE = 4'h6;
parameter SEND_CONFIGURE_END = 4'h7;
parameter WAIT_FOR_DIALTONE = 4'h8;
parameter SEND_ALIGN = 4'h9;
parameter WAIT_FOR_ALIGN = 4'hA;
parameter READY = 4'hB;
parameter SEND_FIRST_ALIGNMENT = 4'hC;
parameter SEND_SECOND_ALIGNMENT = 4'hD;
parameter INITIALIZE_TIMEOUT = 100;
//Registers/Wires
reg [3:0] state = IDLE;
reg [31:0] timer;
reg [7:0] align_count;
wire align_detected;
wire dialtone_detected;
wire timeout;
//Sub Modules
//Asynchronous Logic
assign lax_state = state;
assign align_detected = ((rx_is_k > 0) && (rx_din == `PRIM_ALIGN));
assign dialtone_detected = ((rx_is_k == 0) && (rx_din == `DIALTONE));
assign timeout = (timer == 0);
assign phy_ready = (state == READY);
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
state <= IDLE;
tx_dout <= 0;
tx_is_k <= 0;
tx_set_elec_idle <= 1;
timer <= 0;
hd_ready <= 0;
rx_byte_is_aligned <= 0;
align_count <= 0;
end
else begin
tx_comm_reset <= 0;
tx_comm_wake <= 0;
rx_byte_is_aligned <= 0;
if (state == READY) begin
align_count <= align_count + 1;
end
if (timer > 0) begin
timer <= timer - 1;
end
if ((comm_reset_detect) && (state > WAIT_FOR_NO_RESET)) begin
$display("faux_sata_hd: Asynchronous RESET detected");
align_count <= 0;
hd_ready <= 0;
state <= WAIT_FOR_NO_RESET;
end
case (state)
IDLE: begin
align_count <= 0;
hd_ready <= 0;
tx_set_elec_idle <= 1;
if (comm_reset_detect) begin
//detected a reset from the host
$display("faux_sata_hd: RESET detected");
state <= WAIT_FOR_NO_RESET;
end
end
WAIT_FOR_NO_RESET: begin
if (!comm_reset_detect) begin
//host stopped sending reset
$display("faux_sata_hd: RESET deasserted");
hd_ready <= 0;
state <= SEND_INIT;
end
end
SEND_INIT: begin
//XXX: I may need to send more than one of these
$display("faux_sata_hd: send INIT");
tx_comm_reset <= 1;
state <= WAIT_FOR_WAKE;
end
WAIT_FOR_WAKE: begin
if (comm_wake_detect) begin
$display ("faux_sata_hd: WAKE detected");
state <= WAIT_FOR_NO_WAKE;
end
end
WAIT_FOR_NO_WAKE: begin
if (!comm_wake_detect) begin
$display ("faux_sata_hd: WAKE deasserted");
state <= SEND_WAKE;
end
end
SEND_WAKE: begin
$display ("faux_sata_hd: send WAKE");
tx_comm_wake <= 1;
state <= STOP_SEND_WAKE;
end
STOP_SEND_WAKE: begin
$display ("faux_sata_hd: stop sending WAKE");
state <= WAIT_FOR_DIALTONE;
end
WAIT_FOR_DIALTONE: begin
if (dialtone_detected) begin
$display ("faux_sata_hd: detected dialtone");
state <= SEND_ALIGN;
end
end
SEND_ALIGN: begin
$display ("faux_sata_hd: send aligns");
tx_set_elec_idle <= 0;
tx_dout <= `PRIM_ALIGN;
tx_is_k <= 1;
state <= WAIT_FOR_ALIGN;
timer <= 32'h`INITIALIZE_TIMEOUT;
rx_byte_is_aligned <= 1;
end
WAIT_FOR_ALIGN: begin
tx_is_k <= 1;
tx_dout <= `PRIM_ALIGN;
rx_byte_is_aligned <= 1;
//$display ("faux_sata_hd: waiting for aligns...");
//$display ("rx din: %h, k: %h", rx_din, rx_is_k);
if (align_detected) begin
$display ("faux_sata_hd: detected ALIGN primitive from host");
$display ("faux_sata_hd: Ready");
tx_dout <= `PRIM_ALIGN;
tx_is_k <= 1;
timer <= 0;
state <= READY;
end
else if (timeout) begin
$display ("faux_sata_hd: Timeout while waiting for an alignment from the host");
state <= IDLE;
end
end
READY: begin
hd_ready <= 1;
rx_byte_is_aligned <= 1;
tx_is_k <= 1;
tx_dout <= `PRIM_SYNC;
if (align_count == 255) begin
tx_dout <= `PRIM_ALIGN;
state <= SEND_FIRST_ALIGNMENT;
end
end
SEND_FIRST_ALIGNMENT: begin
rx_byte_is_aligned <= 1;
tx_is_k <= 1;
tx_dout <= `PRIM_ALIGN;
state <= SEND_SECOND_ALIGNMENT;
end
SEND_SECOND_ALIGNMENT: begin
rx_byte_is_aligned <= 1;
tx_is_k <= 1;
tx_dout <= `PRIM_ALIGN;
state <= READY;
end
default: begin
$display ("faux_sata_hd: In undefined state!");
state <= IDLE;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct circle { long double x, y, r; }; struct mod { long double theta, op; }; struct node { long double x, y, theta; }; int n, d, i, j, tot, S, ans, gg; circle c[20005]; mod l[2000005]; node A, B; long double D, k, t, L, R, dis1, dis2, dis3; void getAB() { long double x = c[i].x, y = c[i].y, r = c[i].r, delta; if (x == 0) { t = (r * r - x * x - y * y - D * D) / (-2 * y); k = -x / y; delta = (2 * t * k) * (2 * t * k) - 4 * (k * k + 1) * (t * t - D * D); if (delta < 0) { A.x = A.y = 0; return; } A.x = (-(2 * t * k) + sqrt(delta)) / (2 * (k * k + 1)); B.x = (-(2 * t * k) - sqrt(delta)) / (2 * (k * k + 1)); A.y = (r * r - x * x - y * y - D * D + 2 * x * A.x) / (-2 * y); B.y = (r * r - x * x - y * y - D * D + 2 * x * B.x) / (-2 * y); } else { t = (r * r - x * x - y * y - D * D) / (-2 * x); k = -y / x; delta = (2 * t * k) * (2 * t * k) - 4 * (k * k + 1) * (t * t - D * D); if (delta < 0) { A.x = A.y = 0; return; } A.y = (-(2 * t * k) + sqrt(delta)) / (2 * (k * k + 1)); B.y = (-(2 * t * k) - sqrt(delta)) / (2 * (k * k + 1)); A.x = (r * r - x * x - y * y - D * D + 2 * y * A.y) / (-2 * x); B.x = (r * r - x * x - y * y - D * D + 2 * y * B.y) / (-2 * x); } } void insert(long double L, long double R) { tot++; l[tot].theta = L; l[tot].op = 1; tot++; l[tot].theta = R + 0.0000000001; l[tot].op = -1; } int comp(mod A, mod B) { return ((A.theta < B.theta) || ((A.theta == B.theta) && (A.op < B.op))); } int main() { scanf( %d%d , &n, &d); for (i = 1; i <= n; i++) { scanf( %Lf%Lf%Lf , &c[i].x, &c[i].y, &c[i].r); } for (i = 1; i <= n; i++) { gg = sqrt(c[i].x * c[i].x + c[i].y * c[i].y) / d; for (D = (long double)max(gg - 100, 1) * (long double)d; D <= (long double)(gg + 100) * (long double)d; D += (long double)d) { getAB(); if ((A.x == 0) && (A.y == 0)) continue; A.theta = atan2(A.x, A.y); B.theta = atan2(B.x, B.y); if (A.theta > B.theta) swap(A, B); L = A.theta; R = B.theta; if (R - L > 3.1415926535) swap(L, R); if (L <= R) insert(L, R); else insert(-3.1415926535, R), insert(L, 3.1415926535); } } sort(l + 1, l + 1 + tot, comp); for (i = 1; i <= tot; i++) { S += l[i].op; ans = max(ans, S); } printf( %d , ans); }
|
// file: pll_exdes.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard example design
//----------------------------------------------------------------------------
// This example design instantiates the created clocking network, where each
// output clock drives a counter. The high bit of each counter is ported.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
module pll_exdes
#(
parameter TCQ = 100
)
(// Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [4:1] CLK_OUT,
// High bits of counters driven by clocks
output [4:1] COUNT,
// Status and control signals
input RESET,
output LOCKED
);
// Parameters for the counters
//-------------------------------
// Counter width
localparam C_W = 16;
// Number of counters
localparam NUM_C = 4;
genvar count_gen;
// When the clock goes out of lock, reset the counters
wire reset_int = !LOCKED || RESET || COUNTER_RESET;
reg [NUM_C:1] rst_sync;
reg [NUM_C:1] rst_sync_int;
reg [NUM_C:1] rst_sync_int1;
reg [NUM_C:1] rst_sync_int2;
// Declare the clocks and counters
wire [NUM_C:1] clk_int;
wire [NUM_C:1] clk;
reg [C_W-1:0] counter [NUM_C:1];
// Instantiation of the clocking network
//--------------------------------------
pll clknetwork
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Clock out ports
.CLK_OUT1 (clk_int[1]),
.CLK_OUT2 (clk_int[2]),
.CLK_OUT3 (clk_int[3]),
.CLK_OUT4 (clk_int[4]),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED));
genvar clk_out_pins;
generate
for (clk_out_pins = 1; clk_out_pins <= NUM_C; clk_out_pins = clk_out_pins + 1)
begin: gen_outclk_oddr
ODDR clkout_oddr
(.Q (CLK_OUT[clk_out_pins]),
.C (clk[clk_out_pins]),
.CE (1'b1),
.D1 (1'b1),
.D2 (1'b0),
.R (1'b0),
.S (1'b0));
end
endgenerate
// Connect the output clocks to the design
//-----------------------------------------
assign clk[1] = clk_int[1];
assign clk[2] = clk_int[2];
assign clk[3] = clk_int[3];
assign clk[4] = clk_int[4];
// Reset synchronizer
//-----------------------------------
generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters_1
always @(posedge reset_int or posedge clk[count_gen]) begin
if (reset_int) begin
rst_sync[count_gen] <= 1'b1;
rst_sync_int[count_gen]<= 1'b1;
rst_sync_int1[count_gen]<= 1'b1;
rst_sync_int2[count_gen]<= 1'b1;
end
else begin
rst_sync[count_gen] <= 1'b0;
rst_sync_int[count_gen] <= rst_sync[count_gen];
rst_sync_int1[count_gen] <= rst_sync_int[count_gen];
rst_sync_int2[count_gen] <= rst_sync_int1[count_gen];
end
end
end
endgenerate
// Output clock sampling
//-----------------------------------
generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters
always @(posedge clk[count_gen] or posedge rst_sync_int2[count_gen]) begin
if (rst_sync_int2[count_gen]) begin
counter[count_gen] <= #TCQ { C_W { 1'b 0 } };
end else begin
counter[count_gen] <= #TCQ counter[count_gen] + 1'b 1;
end
end
// alias the high bit of each counter to the corresponding
// bit in the output bus
assign COUNT[count_gen] = counter[count_gen][C_W-1];
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5, maxm = 1e5 + 5; int first[maxn], n, k; struct edge { int to; int next; } E[maxm]; int vis[maxn]; int order[maxn], p; int a[maxn]; bool dfs(int u) { vis[u] = -1; for (int e = first[u]; e != -1; e = E[e].next) { int v = E[e].to; if (vis[v] == -1) return false; else if (!vis[v] && !dfs(v)) return false; } vis[u] = 1; order[p++] = u; return true; } bool topo() { p = 0; memset(vis, 0, sizeof(vis)); for (int i = 0; i < k; i++) if (!vis[a[i]] && !dfs(a[i])) return false; return true; } int main() { while (scanf( %d%d , &n, &k) != EOF) { memset(first, -1, sizeof(first)); for (int i = 0; i < k; i++) scanf( %d , &a[i]); int t, x, ecnt = 0; for (int i = 1; i <= n; i++) { scanf( %d , &t); for (int j = 0; j < t; j++) { scanf( %d , &x); E[ecnt].to = x; E[ecnt].next = first[i]; first[i] = ecnt++; } } if (!topo()) cout << -1 n ; else { cout << p << n ; for (int i = 0; i < p; i++) cout << order[i] << n [i == p - 1]; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; bool const TO_FILE = false; string const FILENAME = ; void prepare() { if (TO_FILE) { freopen((FILENAME + .in ).c_str(), r , stdin); freopen((FILENAME + .out ).c_str(), w , stdout); } } void solve() { int n, m, k; cin >> n >> m >> k; map<int, pair<int, int>> apps; map<pair<int, int>, int> apps2; int curScr = 0; int curPos = 0; for (int i = 0; i < n; i++) { int app; cin >> app; apps[app] = make_pair(curScr, curPos); apps2[make_pair(curScr, curPos)] = app; if (++curPos == k) { curPos = 0; curScr++; } } long long res = m; for (int i = 0; i < m; i++) { int curApp, prevApp; cin >> curApp; int curScr = apps[curApp].first; int curPos = apps[curApp].second; int prevScr, prevPos; if (curScr == 0 && curPos == 0) continue; else if (curPos == 0) { prevScr = curScr - 1; prevPos = k - 1; prevApp = apps2[make_pair(prevScr, prevPos)]; } else { prevScr = curScr; prevPos = curPos - 1; prevApp = apps2[make_pair(prevScr, prevPos)]; } apps[curApp] = make_pair(prevScr, prevPos); apps2[make_pair(prevScr, prevPos)] = curApp; apps[prevApp] = make_pair(curScr, curPos); apps2[make_pair(curScr, curPos)] = prevApp; res += curScr; } cout << res; } int main() { prepare(); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, k, sum; string a; int main() { cin >> n >> k; for (int i = (0); i < (n); i++) { int l, r; cin >> l >> r; sum += (r - l + 1); } if (sum % k == 0) cout << 0 << endl; else { int u = sum; while (u % k) u++; cout << u - sum << endl; } return 0; }
|
`timescale 1ns/10ps
`include "pipeconnect.h"
/*
Notation:
_ low, 0
~ high, 1
/ posedge
\ negedge
. unknown,undetermined,unimportant
# valid data (held stable)
< changing
> --
*/
/*
Fasttarget presents the request address as the result data after one
cycle. Wait is never asserted.
WISHBONE - no wait states
clock _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
addr ........<#### A1 ####><#### A2 ####>.........................
read ________/~~~~~~~~~~~~~~~~~~~~~~~~~~\_________________________
wait _____________________________________________________________
readdata _____________<#### D1 ####><#### D2 ####>____________________
PIPECONNECT - no wait states
Request noticed by target
| Response captured by initiator
v v
clock _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
addr ........<#### A1 ####><#### A2 ####>.........................
read ________/~~~~~~~~~~~~~~~~~~~~~~~~~~\_________________________
wait _____________________________________________________________
readdata ___________________________<#### D1 ####><#### D2 ####>______
PIPECONNECT - some wait states
Request noticed by target
| Response captured by initiator
v v
clock _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
addr ........<#### A1 ##################><#### A2 ####>.........................
read ________/~~~~~~~~~~~~~~~~~~~~~~~~~~\_______________________________________
wait _____________/~~~~~~~~~~~~\________________________________________________
readdata _________________________________________<#### D1 ####><#### D2 ####>______
*/
module fasttarget // PIPECONNECT, no wait
(input wire clk,
input wire rst,
input wire `REQ req,
output reg `RES res);
always @(posedge clk) begin
res`WAIT <= 0;
res`RD <= ~rst && req`R ? req`A : 0;
end
endmodule
/*
PIPECONNECT - 1 wait state
Request noticed by target
| Response captured by initiator
v v
clock _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
addr ........<#### A1 ##################><#### A2 ##################>...........
read ________/~~~~~~~~~~~~~~~~~~~~~~~~~~\/~~~~~~~~~~~~~~~~~~~~~~~~~~\___________
wait _____________/~~~~~~~~~~~~\______________/~~~~~~~~~~~~\____________________
readdata _________________________________________<#### D1 ####>______________<#### D2 ####>______
_~_~_~_~_~_
.AAAABBBB..
_~~~~~~~~__
_~~__~~____
_____aa__bb
*/
module slowtarget // PIPECONNECT, 1 wait
(input wire clk,
input wire rst,
input wire `REQ req,
output wire `RES res);
reg [31:0] readData;
reg ready;
assign res`RD = readData;
assign res`WAIT = req`R & ~ready;
always @(posedge clk)
if (rst) begin
readData <= 0;
ready <= 0;
//$display("target in reset");
end else begin
readData <= ready ? req`A : 0;
ready <= req`R & ~ready;
//$display("target %d %d", ready, res`WAIT);
end
endmodule
/*
Simple master waits for a result before issuing new request
PIPECONNECT - no wait states
Request noticed by target
| Response captured by initiator
v v
clock /~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
addr ...<#####req 1###>...........................<#####req 2
read ___/~~~~~~~~~~~~~\___________________________/~~~~~~~~~~
wait ________________________________________________________
readdata ______________________<#############>___________________
*/
/*
Streaming master keeps one outstanding command
PIPECONNECT - no wait states
Request noticed by target
| Response captured by initiator
v v
clock _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
addr ........<#####req 1###>.............<#####req 2
read ________/~~~~~~~~~~~~~\___________________________/~~~~~~~~~~
wait _____________________________________________________________
readdata ___________________________<#############>___________________
*/
module initiator
(input wire clk,
input wire rst,
output reg `REQ req,
input wire `RES res);
parameter name = 1;
reg [31:0] counter, data;
reg [31:0] dataExpect;
reg dataValid;
wire pause = ^counter[1:0];
always @(posedge clk)
if (rst) begin
counter <= name << 16;
req <= 0;
dataValid <= 0;
dataExpect <= 0;
end else begin
dataExpect <= data;
dataValid <= req`R & ~res`WAIT;
if (dataValid) begin
if (dataExpect != res`RD)
$display("%6d init%d got %x, expected %x !!! BAD!",
$time, name, res`RD, dataExpect);
else
$display("%6d init%d got %x as expected", $time, name, res`RD);
end
if (~res`WAIT) begin
counter <= counter + 1;
if (pause) begin
req`R <= 0;
end else begin
req`R <= 1;
req`A <= counter;
data <= counter;
$display("%6d init%d requests %x", $time, name, counter);
end
end
end
endmodule
module main();
reg rst, clk;
wire `REQ req, req1, req2;
wire `RES res, res1, res2;
wire [31:0] addr = req`A;
wire read = req`R;
wire wai = res`WAIT;
wire [31:0] data = res`RD;
initiator #(1) initiator1(clk, rst, req1, res1);
initiator #(2) initiator2(clk, rst, req2, res2);
mux2 mux_init(clk, req1, res1, req2, res2, req, res);
slowtarget target(clk, rst, req, res);
always # 5 clk = ~clk;
initial begin
$monitor("%d%d %4d %x %d %d %x", rst, clk, $time, addr, read, wai, data);
clk = 1;
rst = 1;
#15 rst = 0;
#200 $finish;
end
endmodule
|
#include <bits/stdc++.h> char s[1005]; int a[25], mark[6071], dp[1005][6071], ch[6071][12], link[6071], tl, ans = 1e9, x, n; void insert(int len) { int rt = 0; for (int i = 1; i <= len; ++i) { if (!ch[rt][a[i]]) ch[rt][a[i]] = ++tl; rt = ch[rt][a[i]]; } mark[rt] = 1; } void build() { std::queue<int> q; std::memset(link, -1, sizeof(link)); link[0] = 0; for (int i = 0; i < 10; ++i) if (ch[0][i]) { q.push(ch[0][i]); link[ch[0][i]] = 0; } while (!q.empty()) { int u = q.front(); q.pop(); mark[u] |= mark[link[u]]; for (int i = 0; i < 10; ++i) { if (ch[u][i]) { mark[ch[u][i]] |= mark[u]; link[ch[u][i]] = ch[link[u]][i]; q.push(ch[u][i]); } else ch[u][i] = ch[link[u]][i]; } } } void dfs(int u, int sum) { if (sum == x) { for (int l = 1; l < u; ++l) { int s = 0; for (int r = l; r < u; ++r) { s += a[r]; if (s != x && x % s == 0) return; } } insert(u - 1); return; } for (int j = 1; sum + j <= x && j < 10; ++j) { a[u] = j; dfs(u + 1, sum + j); } } void generate() { dfs(1, 0); build(); } int main() { scanf( %s%d , s + 1, &x); n = std::strlen(s + 1); generate(); std::memset(dp, 63, sizeof(dp)); dp[1][0] = 0; for (int i = 1; i <= n; ++i) { for (int j = 0; j <= tl; ++j) { if (!mark[ch[j][s[i] - 0 ]]) dp[i + 1][ch[j][s[i] - 0 ]] = std::min(dp[i + 1][ch[j][s[i] - 0 ]], dp[i][j]); dp[i + 1][j] = std::min(dp[i + 1][j], dp[i][j] + 1); } } for (int j = 0; j <= tl; ++j) ans = std::min(ans, dp[n + 1][j]); printf( %d , ans); return 0; }
|
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
/*
* rcn bus buffered bridge.
*
*/
module rcn_bridge_buf
(
input rst,
input clk,
input [68:0] main_rcn_in,
output [68:0] main_rcn_out,
input [68:0] sub_rcn_in,
output [68:0] sub_rcn_out
);
parameter ID_MASK = 0;
parameter ID_BASE = 1;
parameter ADDR_MASK = 0;
parameter ADDR_BASE = 1;
wire [5:0] my_id_mask = ID_MASK;
wire [5:0] my_id_base = ID_BASE;
wire [23:0] my_addr_mask = ADDR_MASK;
wire [23:0] my_addr_base = ADDR_BASE;
reg [68:0] main_rin;
reg [68:0] main_rout;
reg [68:0] sub_rin;
reg [68:0] sub_rout;
assign main_rcn_out = main_rout;
assign sub_rcn_out = sub_rout;
wire [68:0] sub_fifo_in;
wire sub_fifo_push;
wire sub_fifo_full;
wire [68:0] sub_fifo_out;
wire sub_fifo_pop;
wire sub_fifo_empty;
wire [68:0] main_fifo_in;
wire main_fifo_push;
wire main_fifo_full;
wire [68:0] main_fifo_out;
wire main_fifo_pop;
wire main_fifo_empty;
always @ (posedge clk or posedge rst)
if (rst)
begin
main_rin <= 69'd0;
main_rout <= 69'd0;
sub_rin <= 69'd0;
sub_rout <= 69'd0;
end
else
begin
main_rin <= main_rcn_in;
main_rout <= (sub_fifo_pop) ? sub_fifo_out :
(main_fifo_push) ? 69'd0 : main_rin;
sub_rin <= sub_rcn_in;
sub_rout <= (main_fifo_pop) ? main_fifo_out :
(sub_fifo_push) ? 69'd0 : sub_rin;
end
wire main_id_match = ((main_rin[65:60] & my_id_mask) == my_id_base);
wire main_addr_match = ((main_rin[55:34] & my_addr_mask[23:2]) == my_addr_base[23:2]);
assign main_fifo_push = !main_fifo_full && main_rin[68] &&
((main_rin[67] && main_addr_match) ||
(!main_rin[67] && main_id_match));
assign main_fifo_pop = !main_fifo_empty && (!sub_rin[68] || sub_fifo_push);
rcn_fifo main_fifo
(
.rst(rst),
.clk(clk),
.rcn_in(main_rin),
.push(main_fifo_push),
.full(main_fifo_full),
.rcn_out(main_fifo_out),
.pop(main_fifo_pop),
.empty(main_fifo_empty)
);
wire sub_id_match = ((sub_rin[65:60] & my_id_mask) == my_id_base);
wire sub_addr_match = ((sub_rin[55:34] & my_addr_mask[23:2]) == my_addr_base[23:2]);
assign sub_fifo_push = !sub_fifo_full && sub_rin[68] &&
((sub_rin[67] && !sub_addr_match) ||
(!sub_rin[67] && !sub_id_match));
assign sub_fifo_pop = !sub_fifo_empty && (!main_rin[68] || main_fifo_push);
rcn_fifo sub_fifo
(
.rst(rst),
.clk(clk),
.rcn_in(sub_rin),
.push(sub_fifo_push),
.full(sub_fifo_full),
.rcn_out(sub_fifo_out),
.pop(sub_fifo_pop),
.empty(sub_fifo_empty)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { (i + j) % 2 ? cout << B : cout << W ; } cout << endl; } }
|
#include <bits/stdc++.h> using namespace std; int n, d; int a[200]; int x[200], y[200]; int dis[200]; vector<pair<int, int> > edge[200]; int bellman_ford() { for (int i = 0; i < n; ++i) dis[i] = 1000000000; dis[0] = 0; for (int i = 1; i < n; ++i) { for (int j = 0; j < n; ++j) { for (int k = 0, len = edge[j].size(); k < len; ++k) dis[edge[j][k].first] = min(dis[edge[j][k].first], dis[j] + edge[j][k].second); } } return max(0, dis[n - 1]); } int D(int i, int j) { return abs(x[i] - x[j]) + abs(y[i] - y[j]); } int main() { while (cin >> n >> d) { a[0] = 0; a[n - 1] = 0; for (int i = 1; i < n - 1; ++i) cin >> a[i]; for (int i = 0; i < n; ++i) { cin >> x[i] >> y[i]; } for (int i = 0; i < n; ++i) for (int j = 0; j < n; ++j) if (i != j) { edge[i].push_back(make_pair(j, D(i, j) * d - a[i])); } cout << bellman_ford() << endl; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND3_SYMBOL_V
`define SKY130_FD_SC_LP__AND3_SYMBOL_V
/**
* and3: 3-input AND.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__and3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND3_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND3B_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__AND3B_FUNCTIONAL_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__and3b (
X ,
A_N,
B ,
C
);
// Module ports
output X ;
input A_N;
input B ;
input C ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X, C, not0_out, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND3B_FUNCTIONAL_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:39:25 01/29/2016
// Design Name: control_unit
// Module Name: /home/poche002/Desktop/ArqComp/Trabajo_final/arquitectura_tpf/control_unit_tb.v
// Project Name: arquitectura_tpf
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: control_unit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module control_unit_tb;
// Inputs
reg clk;
reg [31:0] instruction;
// Outputs
wire [3:0] ex_ctrl_sgnl;
wire [2:0] mem_ctrl_sgnl;
wire [1:0] wb_ctrl_sgnl;
// Instantiate the Unit Under Test (UUT)
control_unit uut (
.clk(clk),
.instruction(instruction),
.ex_ctrl_sgnl(ex_ctrl_sgnl),
.mem_ctrl_sgnl(mem_ctrl_sgnl),
.wb_ctrl_sgnl(wb_ctrl_sgnl)
);
initial begin
// Initialize Inputs
clk = 0;
instruction = 0;
// Wait 100 ns for global reset to finish
#10;
// Add stimulus here
#10 instruction = 32'b00000000_00000000_00000000_00000000; //r-type
#10 instruction = 32'b10001100_00000000_00000000_00000000; //lw
#10 instruction = 32'b10101100_00000000_00000000_00000000; //sw
#10 instruction = 32'b00010000_00000000_00000000_00000000; //beq
end
always
#1 clk=~clk;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long a, n, b, x, y, s; int q; cin >> q; while (q--) { cin >> a >> b >> n >> s; long long ts = a * n + b; if (ts < s) { cout << NO n ; continue; } if (s % n > b) { cout << NO n ; continue; } cout << YES n ; } }
|
`include "../RF/reg_32bits.v"
`include "../lib/mux32bits_32to1.v"
`include "../lib/dec_5to32.v"
module reg_file (
input [4:0] readReg1, readReg2, writeReg,
input [31:0] writeData,
input regWrite, clk,
output [31:0] readData1, readData2);
wire [31:0] regOutput0, regOutput1, regOutput2, regOutput3, regOutput4, regOutput5, regOutput6, regOutput7, regOutput8, regOutput9, regOutput10, regOutput11, regOutput12, regOutput13, regOutput14, regOutput15, regOutput16, regOutput17, regOutput18, regOutput19, regOutput20, regOutput21, regOutput22, regOutput23, regOutput24, regOutput25, regOutput26, regOutput27, regOutput28, regOutput29, regOutput30, regOutput31;
wire [31:0] regInput0, regInput1, regInput2, regInput3, regInput4, regInput5, regInput6, regInput7, regInput8, regInput9, regInput10, regInput11, regInput12, regInput13, regInput14, regInput15, regInput16, regInput17, regInput18, regInput19, regInput20, regInput21, regInput22, regInput23, regInput24, regInput25, regInput26, regInput27, regInput28, regInput29, regInput30, regInput31;
wire [31:0] we, int;
wire [31:0] regOutput [31:0];
dec_5to32 dec (.b(int), .a(writeReg));
and (we[0 ], regWrite, int[0 ]);
and (we[1 ], regWrite, int[1 ]);
and (we[2 ], regWrite, int[2 ]);
and (we[3 ], regWrite, int[3 ]);
and (we[4 ], regWrite, int[4 ]);
and (we[5 ], regWrite, int[5 ]);
and (we[6 ], regWrite, int[6 ]);
and (we[7 ], regWrite, int[7 ]);
and (we[8 ], regWrite, int[8 ]);
and (we[9 ], regWrite, int[9 ]);
and (we[10], regWrite, int[10]);
and (we[11], regWrite, int[11]);
and (we[12], regWrite, int[12]);
and (we[13], regWrite, int[13]);
and (we[14], regWrite, int[14]);
and (we[15], regWrite, int[15]);
and (we[16], regWrite, int[16]);
and (we[17], regWrite, int[17]);
and (we[18], regWrite, int[18]);
and (we[19], regWrite, int[19]);
and (we[20], regWrite, int[20]);
and (we[21], regWrite, int[21]);
and (we[22], regWrite, int[22]);
and (we[23], regWrite, int[23]);
and (we[24], regWrite, int[24]);
and (we[25], regWrite, int[25]);
and (we[26], regWrite, int[26]);
and (we[27], regWrite, int[27]);
and (we[28], regWrite, int[28]);
and (we[29], regWrite, int[29]);
and (we[30], regWrite, int[30]);
and (we[31], regWrite, int[31]);
reg_32bits reg0 (.d(1'b0 ), .q(regOutput0 ), .we(1'b1 ), .clk(clk));
reg_32bits reg1 (.d(writeData), .q(regOutput1 ), .we(we[1 ]), .clk(clk));
reg_32bits reg2 (.d(writeData), .q(regOutput2 ), .we(we[2 ]), .clk(clk));
reg_32bits reg3 (.d(writeData), .q(regOutput3 ), .we(we[3 ]), .clk(clk));
reg_32bits reg4 (.d(writeData), .q(regOutput4 ), .we(we[4 ]), .clk(clk));
reg_32bits reg5 (.d(writeData), .q(regOutput5 ), .we(we[5 ]), .clk(clk));
reg_32bits reg6 (.d(writeData), .q(regOutput6 ), .we(we[6 ]), .clk(clk));
reg_32bits reg7 (.d(writeData), .q(regOutput7 ), .we(we[7 ]), .clk(clk));
reg_32bits reg8 (.d(writeData), .q(regOutput8 ), .we(we[8 ]), .clk(clk));
reg_32bits reg9 (.d(writeData), .q(regOutput9 ), .we(we[9 ]), .clk(clk));
reg_32bits reg10(.d(writeData), .q(regOutput10), .we(we[10]), .clk(clk));
reg_32bits reg11(.d(writeData), .q(regOutput11), .we(we[11]), .clk(clk));
reg_32bits reg12(.d(writeData), .q(regOutput12), .we(we[12]), .clk(clk));
reg_32bits reg13(.d(writeData), .q(regOutput13), .we(we[13]), .clk(clk));
reg_32bits reg14(.d(writeData), .q(regOutput14), .we(we[14]), .clk(clk));
reg_32bits reg15(.d(writeData), .q(regOutput15), .we(we[15]), .clk(clk));
reg_32bits reg16(.d(writeData), .q(regOutput16), .we(we[16]), .clk(clk));
reg_32bits reg17(.d(writeData), .q(regOutput17), .we(we[17]), .clk(clk));
reg_32bits reg18(.d(writeData), .q(regOutput18), .we(we[18]), .clk(clk));
reg_32bits reg19(.d(writeData), .q(regOutput19), .we(we[19]), .clk(clk));
reg_32bits reg20(.d(writeData), .q(regOutput20), .we(we[20]), .clk(clk));
reg_32bits reg21(.d(writeData), .q(regOutput21), .we(we[21]), .clk(clk));
reg_32bits reg22(.d(writeData), .q(regOutput22), .we(we[22]), .clk(clk));
reg_32bits reg23(.d(writeData), .q(regOutput23), .we(we[23]), .clk(clk));
reg_32bits reg24(.d(writeData), .q(regOutput24), .we(we[24]), .clk(clk));
reg_32bits reg25(.d(writeData), .q(regOutput25), .we(we[25]), .clk(clk));
reg_32bits reg26(.d(writeData), .q(regOutput26), .we(we[26]), .clk(clk));
reg_32bits reg27(.d(writeData), .q(regOutput27), .we(we[27]), .clk(clk));
reg_32bits reg28(.d(writeData), .q(regOutput28), .we(we[28]), .clk(clk));
reg_32bits reg29(.d(writeData), .q(regOutput29), .we(we[29]), .clk(clk));
reg_32bits reg30(.d(writeData), .q(regOutput30), .we(we[30]), .clk(clk));
reg_32bits reg31(.d(writeData), .q(regOutput31), .we(we[31]), .clk(clk));
mux32bits_32to1 rd1(.z(readData1), .s(readReg1), .i0(regOutput0), .i1(regOutput1), .i2(regOutput2), .i3(regOutput3), .i4(regOutput4), .i5(regOutput5), .i6(regOutput6), .i7(regOutput7), .i8(regOutput8), .i9(regOutput9), .i10(regOutput10), .i11(regOutput11), .i12(regOutput12), .i13(regOutput13), .i14(regOutput14), .i15(regOutput15), .i16(regOutput16), .i17(regOutput17), .i18(regOutput18), .i19(regOutput19), .i20(regOutput20), .i21(regOutput21), .i22(regOutput22), .i23(regOutput23), .i24(regOutput24), .i25(regOutput25), .i26(regOutput26), .i27(regOutput27), .i28(regOutput28), .i29(regOutput29), .i30(regOutput30), .i31(regOutput31));
mux32bits_32to1 rd2(.z(readData2), .s(readReg2), .i0(regOutput0), .i1(regOutput1), .i2(regOutput2), .i3(regOutput3), .i4(regOutput4), .i5(regOutput5), .i6(regOutput6), .i7(regOutput7), .i8(regOutput8), .i9(regOutput9), .i10(regOutput10), .i11(regOutput11), .i12(regOutput12), .i13(regOutput13), .i14(regOutput14), .i15(regOutput15), .i16(regOutput16), .i17(regOutput17), .i18(regOutput18), .i19(regOutput19), .i20(regOutput20), .i21(regOutput21), .i22(regOutput22), .i23(regOutput23), .i24(regOutput24), .i25(regOutput25), .i26(regOutput26), .i27(regOutput27), .i28(regOutput28), .i29(regOutput29), .i30(regOutput30), .i31(regOutput31));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND3B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__AND3B_BEHAVIORAL_PP_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__and3b (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , C, not0_out, B );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND3B_BEHAVIORAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XNOR3_FUNCTIONAL_V
`define SKY130_FD_SC_HS__XNOR3_FUNCTIONAL_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__xnor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
// Local signals
wire xnor0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
xnor xnor0 (xnor0_out_X , A, B, C );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, xnor0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__XNOR3_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; assert(n >= 1 && n <= 10000 && m >= 1 && m <= 10); if (n == m && (n == 1 || n == 2)) cout << n << endl; else { if (n == m) cout << n << endl; else { int t2 = 0, t1 = 0; if (n & 1) { n--; t1++; } t2 = n / 2; while ((t2 + t1) % m != 0 && n > 0) { n = n - 2; t1 = t1 + 2; t2 = n / 2; } if (n == 0) cout << -1 << endl; else cout << t1 + t2 << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; double dist(double x1, double y1, double x2, double y2) { double dx = x1 - x2; double dy = y1 - y2; return sqrt(dx * dx + dy * dy); } double catet(double a, int b) { double z = a * a - b * b; if (z < 1e-12) z = 0; return sqrt(z); } int main() { int xp, yp, vp; cin >> xp >> yp >> vp; int x, y, v, r; cin >> x >> y >> v >> r; const double eps = 1e-10; const double R = sqrt(1.0 * xp * xp + 1.0 * yp * yp); double lo = 0; double hi = 1e7; double T; while ((hi - lo) / hi > eps) { T = (lo + hi) / 2; const double alpha = T / (R / vp); double nx = xp * cos(alpha) - yp * sin(alpha); double ny = xp * sin(alpha) + yp * cos(alpha); double a = ny - y; double b = x - nx; double c = -(a * x + b * y); double z = sqrt(a * a + b * b); a /= z; b /= z; c /= z; double need; if (fabs(c) < r - 1e-8) { double mx = a * (-c); double my = b * (-c); if (dist(x, y, mx, my) + dist(mx, my, nx, ny) > dist(x, y, nx, ny) + 1e-8) { need = dist(x, y, nx, ny); } else { need = catet(dist(x, y, 0, 0), r) + catet(dist(nx, ny, 0, 0), r); double alp = fabs(atan2(y, x) - atan2(ny, nx)); if (alp > M_PI) alp = 2 * M_PI - alp; alp -= acos(r / dist(x, y, 0, 0)); alp -= acos(r / dist(nx, ny, 0, 0)); need += alp * r; } } else { need = dist(x, y, nx, ny); } if (need <= v * T) { hi = T; } else { lo = T; } } printf( %.6f n , T); return 0; }
|
/*
* c4puter northbridge - simple two-register Wishbone GPIO
* Copyright (C) 2017 Chris Pavlina
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
// Address 0: in
// Address 1: out
module wb_simple_gpio (
input [31:0] wb_dat_i,
output reg [31:0] wb_dat_o,
input [35:0] wb_adr_i,
input wb_we_i,
input [3:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output reg wb_ack_o,
input [31:0] gpio_in,
output [31:0] gpio_out,
input clk
);
reg [31:0] gpio_in_reg = 32'h00000000;
reg [31:0] gpio_out_reg = 32'h00000000;
wire gpio_write;
assign gpio_out = gpio_out_reg;
assign gpio_write = wb_stb_i && wb_we_i && wb_adr_i[0];
always @(posedge clk) begin
gpio_in_reg <= gpio_in;
if (gpio_write)
gpio_out_reg <= wb_dat_i;
if (wb_stb_i) begin
//wb_dat_o <= (wb_adr_i[0] == 1'b0 ? gpio_in_reg : gpio_out_reg);
wb_dat_o <= wb_adr_i[31:0];
wb_ack_o <= 1'b1;
end else begin
wb_ack_o <= 1'b0;
end
end
endmodule
|
#include <bits/stdc++.h> #define ll long long int #define vi vector<ll> #define vvi vector<vector<ll>> #define pii pair<ll, ll> #define pb push_back #define rep0(i, n) for(ll i = 0;i<n;i++) #define rep1(i, n) for(ll i = 1;i<n;i++) #define all(v) v.begin(),v.end() #define fast ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); using namespace std; const int N = 1e5 + 5; void solve(){ ll n; cin >> n; vector<ll> arr(n); for(ll i=0; i<n; i++){ cin >> arr[i]; arr[i] = arr[i]-i-1; } map<ll, ll> mp; ll res = 0; for(ll i=0; i<n; i++){ if(mp[arr[i]]>0){ res += mp[arr[i]]; } mp[arr[i]]++; } cout << res << n ; } int main() { fast; int t; cin >> t; while(t--){ solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; bool viz[105][105]; int dx[4] = {0, 1, 0, -1}; int dy[4] = {1, 0, -1, 0}; int main() { cin.tie(0)->sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); int T = 1; while (T--) { int n, m, x, y; cin >> n >> m >> x >> y; vector<pair<int, int> > sol; viz[x][y] = 1; cout << x << << y << n ; int cnt = 1; for (int j = 1; j <= m; j++) { if (j != y) { cout << x << << j << n ; } } for (int i = x + 1; i <= n; i++) { if (cnt % 2 == 1) { for (int j = m; j >= 1; j--) { cout << i << << j << n ; } } else { for (int j = 1; j <= m; j++) { cout << i << << j << n ; } } cnt++; } for (int i = x - 1; i >= 1; i--) { if (cnt % 2 == 1) { for (int j = m; j >= 1; j--) { cout << i << << j << n ; } } else { for (int j = 1; j <= m; j++) { cout << i << << j << n ; } } cnt++; } } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKINV_2_V
`define SKY130_FD_SC_LP__CLKINV_2_V
/**
* clkinv: Clock tree inverter.
*
* Verilog wrapper for clkinv with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__clkinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkinv_2 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkinv_2 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__clkinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKINV_2_V
|
`default_nettype none
module comparator_counter(
input wire iCLOCK,
input wire inRESET,
//Main Counter
input wire iMTIMER_WORKING,
input wire [63:0] iMTIMER_COUNT,
//Timmer Settings
input wire iCONF_WRITE,
input wire iCONF_ENA,
input wire iCONF_IRQENA,
input wire iCONF_64MODE,
input wire iCONF_PERIODIC, //Non Periodic mode = 0 | Periodic mode = 1
//Counter
input wire iCOUNT_WRITE,
input wire [1:0] inCOUNT_DQM,
input wire [63:0] iCOUNT_COUNTER,
//Interrupt
output wire oIRQ
);
reg enable;
reg irqena;
reg [63:0] ini_counter;
reg [63:0] counter;
reg bitmode;
reg periodic;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
enable <= 1'b0;
irqena <= 1'b0;
ini_counter <= 64'h0;
counter <= 64'h0;
bitmode <= 1'b0;
periodic <= 1'b0;
end
else begin
///Counter Setting
if(iCONF_WRITE)begin
enable <= iCONF_ENA;
irqena <= iCONF_IRQENA;
bitmode <= iCONF_64MODE;
periodic <= iCONF_PERIODIC;
//Counter Write
if(iCOUNT_WRITE)begin
ini_counter[31:0] <= (!inCOUNT_DQM[0])? iCOUNT_COUNTER[31:0] : ini_counter[31:0];
ini_counter[63:32] <= (!inCOUNT_DQM[1])? iCOUNT_COUNTER[63:32] : ini_counter[63:32];
counter[31:0] <= (!inCOUNT_DQM[0])? iCOUNT_COUNTER[31:0] : ini_counter[31:0];
counter[63:32] <= (!inCOUNT_DQM[1])? iCOUNT_COUNTER[63:32] : ini_counter[63:32];
end
end
else begin
//Counter Write
if(iCOUNT_WRITE)begin
ini_counter[31:0] <= (!inCOUNT_DQM[0])? iCOUNT_COUNTER[31:0] : ini_counter[31:0];
ini_counter[63:32] <= (!inCOUNT_DQM[1])? iCOUNT_COUNTER[63:32] : ini_counter[63:32];
counter[31:0] <= (!inCOUNT_DQM[0])? iCOUNT_COUNTER[31:0] : ini_counter[31:0];
counter[63:32] <= (!inCOUNT_DQM[1])? iCOUNT_COUNTER[63:32] : ini_counter[63:32];
end
else if(enable)begin
if(periodic)begin
if(bitmode)begin
//64bit Mode
if(counter == iMTIMER_COUNT)begin
counter <= counter + ini_counter;
end
end
else begin
//32bit Mode
if(counter[31:0] == iMTIMER_COUNT[31:0])begin
counter <= counter + ini_counter;
end
end
end
end
end
end
end
assign oIRQ = irqena && iMTIMER_WORKING && (bitmode)? (counter == iMTIMER_COUNT && ini_counter != 64'h0) : (counter[31:0] == iMTIMER_COUNT[31:0] && ini_counter[31:0] != 32'h0);
endmodule
`default_nettype wire
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