text
stringlengths 59
71.4k
|
|---|
#include <bits/stdc++.h> using namespace std; template <class T> void pp(T v) { for (__typeof((v).begin()) it = (v).begin(); it != (v).end(); ++it) cout << *it << ; cout << endl; } template <class T> void pp(T v, int n) { for (int i = 0; i < (int)n; i++) cout << v[i] << ; cout << endl; } const int INF = 1 << 28; const double EPS = 1.0e-9; bool solve(const vector<pair<int, string> > &data) { const int n = data.size(); for (int i = 0; i < (int)n; i++) { if (data[i].first > i) return false; } vector<int> height(n); vector<int> ans; for (int i = 0, h = n; i < n; i++, h--) { ans.insert(ans.begin() + data[i].first, i); height[i] = h; } for (int i = 0; i < (int)n; i++) { cout << data[ans[i]].second << << height[ans[i]] << endl; } return true; } int main(void) { int n; cin >> n; vector<pair<int, string> > data(n); for (int i = 0; i < (int)n; i++) { string name; int a; cin >> name >> a; data[i] = make_pair(a, name); } sort((data).begin(), (data).end()); bool ans = solve(data); if (ans == false) cout << -1 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; void Solve() { long long int n, q; cin >> n >> q; long long int a[n + 1], cnt[n + 1]; for (auto i = 1; i < n + 1; i++) cin >> a[i], cnt[i] = 0; while (q--) { long long int l, r; cin >> l >> r; cnt[l]++; if (r != n) cnt[r + 1]--; } for (auto i = 2; i < n + 1; i++) cnt[i] += cnt[i - 1]; sort(cnt + 1, cnt + n + 1); sort(a + 1, a + n + 1); long long int ans = 0; for (auto i = 1; i < n + 1; i++) ans += cnt[i] * a[i]; cout << ans << n ; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long int T = 1; while (T--) Solve(); return 0; }
|
/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.8.0.115.3 */
/* Module Version: 5.7 */
/* C:\lscc\diamond\3.8_x64\ispfpga\bin\nt64\scuba.exe -w -n system_pll -lang verilog -synth synplify -arch xo2c00 -type pll -fin 50 -fclkop 100 -fclkop_tol 0.0 -fclkos 100 -fclkos_tol 0.0 -trimp 0 -phasep 0 -trimp_r -trims 0 -phases 315 -trims_r -phase_cntl STATIC -fb_mode 1 */
/* Sun Oct 30 10:29:56 2016 */
`timescale 1 ns / 1 ps
module system_pll (CLKI, CLKOP, CLKOS)/* synthesis NGD_DRC_MASK=1 */;
input wire CLKI;
output wire CLKOP;
output wire CLKOS;
wire LOCK;
wire CLKOS_t;
wire CLKOP_t;
wire scuba_vlo;
VLO scuba_vlo_inst (.Z(scuba_vlo));
defparam PLLInst_0.DDRST_ENA = "DISABLED" ;
defparam PLLInst_0.DCRST_ENA = "DISABLED" ;
defparam PLLInst_0.MRST_ENA = "DISABLED" ;
defparam PLLInst_0.PLLRST_ENA = "DISABLED" ;
defparam PLLInst_0.INTFB_WAKE = "DISABLED" ;
defparam PLLInst_0.STDBY_ENABLE = "DISABLED" ;
defparam PLLInst_0.DPHASE_SOURCE = "DISABLED" ;
defparam PLLInst_0.PLL_USE_WB = "DISABLED" ;
defparam PLLInst_0.CLKOS3_FPHASE = 0 ;
defparam PLLInst_0.CLKOS3_CPHASE = 0 ;
defparam PLLInst_0.CLKOS2_FPHASE = 0 ;
defparam PLLInst_0.CLKOS2_CPHASE = 0 ;
defparam PLLInst_0.CLKOS_FPHASE = 3 ;
defparam PLLInst_0.CLKOS_CPHASE = 8 ;
defparam PLLInst_0.CLKOP_FPHASE = 0 ;
defparam PLLInst_0.CLKOP_CPHASE = 4 ;
defparam PLLInst_0.PLL_LOCK_MODE = 0 ;
defparam PLLInst_0.CLKOS_TRIM_DELAY = 0 ;
defparam PLLInst_0.CLKOS_TRIM_POL = "RISING" ;
defparam PLLInst_0.CLKOP_TRIM_DELAY = 0 ;
defparam PLLInst_0.CLKOP_TRIM_POL = "RISING" ;
defparam PLLInst_0.FRACN_DIV = 0 ;
defparam PLLInst_0.FRACN_ENABLE = "DISABLED" ;
defparam PLLInst_0.OUTDIVIDER_MUXD2 = "DIVD" ;
defparam PLLInst_0.PREDIVIDER_MUXD1 = 0 ;
defparam PLLInst_0.VCO_BYPASS_D0 = "DISABLED" ;
defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED" ;
defparam PLLInst_0.OUTDIVIDER_MUXC2 = "DIVC" ;
defparam PLLInst_0.PREDIVIDER_MUXC1 = 0 ;
defparam PLLInst_0.VCO_BYPASS_C0 = "DISABLED" ;
defparam PLLInst_0.CLKOS2_ENABLE = "DISABLED" ;
defparam PLLInst_0.OUTDIVIDER_MUXB2 = "DIVB" ;
defparam PLLInst_0.PREDIVIDER_MUXB1 = 0 ;
defparam PLLInst_0.VCO_BYPASS_B0 = "DISABLED" ;
defparam PLLInst_0.CLKOS_ENABLE = "ENABLED" ;
defparam PLLInst_0.OUTDIVIDER_MUXA2 = "DIVA" ;
defparam PLLInst_0.PREDIVIDER_MUXA1 = 0 ;
defparam PLLInst_0.VCO_BYPASS_A0 = "DISABLED" ;
defparam PLLInst_0.CLKOP_ENABLE = "ENABLED" ;
defparam PLLInst_0.CLKOS3_DIV = 1 ;
defparam PLLInst_0.CLKOS2_DIV = 1 ;
defparam PLLInst_0.CLKOS_DIV = 5 ;
defparam PLLInst_0.CLKOP_DIV = 5 ;
defparam PLLInst_0.CLKFB_DIV = 2 ;
defparam PLLInst_0.CLKI_DIV = 1 ;
defparam PLLInst_0.FEEDBK_PATH = "CLKOP" ;
EHXPLLJ PLLInst_0 (.CLKI(CLKI), .CLKFB(CLKOP_t), .PHASESEL1(scuba_vlo),
.PHASESEL0(scuba_vlo), .PHASEDIR(scuba_vlo), .PHASESTEP(scuba_vlo),
.LOADREG(scuba_vlo), .STDBY(scuba_vlo), .PLLWAKESYNC(scuba_vlo),
.RST(scuba_vlo), .RESETM(scuba_vlo), .RESETC(scuba_vlo), .RESETD(scuba_vlo),
.ENCLKOP(scuba_vlo), .ENCLKOS(scuba_vlo), .ENCLKOS2(scuba_vlo),
.ENCLKOS3(scuba_vlo), .PLLCLK(scuba_vlo), .PLLRST(scuba_vlo), .PLLSTB(scuba_vlo),
.PLLWE(scuba_vlo), .PLLADDR4(scuba_vlo), .PLLADDR3(scuba_vlo), .PLLADDR2(scuba_vlo),
.PLLADDR1(scuba_vlo), .PLLADDR0(scuba_vlo), .PLLDATI7(scuba_vlo),
.PLLDATI6(scuba_vlo), .PLLDATI5(scuba_vlo), .PLLDATI4(scuba_vlo),
.PLLDATI3(scuba_vlo), .PLLDATI2(scuba_vlo), .PLLDATI1(scuba_vlo),
.PLLDATI0(scuba_vlo), .CLKOP(CLKOP_t), .CLKOS(CLKOS_t), .CLKOS2(),
.CLKOS3(), .LOCK(LOCK), .INTLOCK(), .REFCLK(), .CLKINTFB(), .DPHSRC(),
.PLLACK(), .PLLDATO7(), .PLLDATO6(), .PLLDATO5(), .PLLDATO4(), .PLLDATO3(),
.PLLDATO2(), .PLLDATO1(), .PLLDATO0())
/* synthesis FREQUENCY_PIN_CLKOS="100.000000" */
/* synthesis FREQUENCY_PIN_CLKOP="100.000000" */
/* synthesis FREQUENCY_PIN_CLKI="50.000000" */
/* synthesis ICP_CURRENT="9" */
/* synthesis LPF_RESISTOR="72" */;
assign CLKOS = CLKOS_t;
assign CLKOP = CLKOP_t;
// exemplar begin
// exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOS 100.000000
// exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOP 100.000000
// exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKI 50.000000
// exemplar attribute PLLInst_0 ICP_CURRENT 9
// exemplar attribute PLLInst_0 LPF_RESISTOR 72
// exemplar end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long a[200005], b[200005]; int x[200005]; int main() { int n; long long t; scanf( %d%I64d , &n, &t); for (int i = 1; i <= n; i++) scanf( %I64d , a + i); for (int i = 1; i <= n; i++) { scanf( %d , x + i); if (x[i] < x[i - 1] || x[i] < i) { puts( No ); return 0; } } for (int i = 1; i <= n; i++) b[x[i]] = -1; for (int i = 1; i <= n; i++) b[i] += b[i - 1]; for (int i = 1; i <= n; i++) if (b[x[i] - 1] - b[i - 1]) { puts( No ); return 0; } for (int i = n; i; i--) b[i] -= b[i - 1]; for (int i = 1; i < n; i++) b[i] += a[i + 1] + t; b[n] = a[n] + t + 1; for (int i = 1; i <= n; i++) if (b[i] < a[i] + t || b[i] <= b[i - 1]) { puts( No ); return 0; } puts( Yes ); for (int i = 1; i <= n; i++) printf( %I64d , b[i]); return 0; }
|
#include <bits/stdc++.h> const int nmax = 500000; int ans[nmax + 5]; int main() { int n, i, j, x1, y1, x2, y2; scanf( %d , &n); for (i = 1; i <= n; i++) { scanf( %d%d%d%d , &x1, &y1, &x2, &y2); ans[i] = (((x2 % 2) + 2) % 2) * 2 + ((y2 % 2) + 2) % 2 + 1; } printf( YES n ); for (i = 1; i <= n; i++) printf( %d n , ans[i]); return 0; }
|
// This tests system functions operationg on packed arrays
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
module test ();
// parameters for array sizes
localparam WA = 4;
localparam WB = 6;
localparam WC = 8;
function int wdt (input int i);
wdt = 2 + 2*i;
endfunction
// 2D packed arrays
logic [WA-1:0] [WB-1:0] [WC-1:0] abg; // big endian array
logic [0:WA-1] [0:WB-1] [0:WC-1] alt; // little endian array
// error counter
bit err = 0;
// indexing variable
int i;
initial begin
// big endian
// full array
if ($dimensions(abg) != 3) begin $display("FAILED -- $dimensions(abg) = %0d", $dimensions(abg)); err=1; end;
if ($bits (abg) != WA*WB*WC) begin $display("FAILED -- $bits (abg) = %0d", $bits (abg)); err=1; end;
for (i=1; i<=3; i=i+1) begin
if ($left (abg , i) != wdt(i )-1) begin $display("FAILED -- $left (abg , %0d) = %0d", i, $left (abg , i)); err=1; end;
if ($right (abg , i) != 0 ) begin $display("FAILED -- $right (abg , %0d) = %0d", i, $right (abg , i)); err=1; end;
if ($low (abg , i) != 0 ) begin $display("FAILED -- $low (abg , %0d) = %0d", i, $low (abg , i)); err=1; end;
if ($high (abg , i) != wdt(i )-1) begin $display("FAILED -- $high (abg , %0d) = %0d", i, $high (abg , i)); err=1; end;
if ($increment(abg , i) != 1 ) begin $display("FAILED -- $increment(abg , %0d) = %0d", i, $increment(abg , i)); err=1; end;
if ($size (abg , i) != wdt(i ) ) begin $display("FAILED -- $size (abg , %0d) = %0d", i, $size (abg , i)); err=1; end;
end
// half array
if ($dimensions(abg[1:0]) != 3) begin $display("FAILED -- $dimensions(abg[1:0]) = %0d", $dimensions(abg[1:0])); err=1; end;
if ($bits (abg[1:0]) != 2*WB*WC) begin $display("FAILED -- $bits (abg[1:0]) = %0d", $bits (abg[1:0])); err=1; end;
for (i=1; i<=3; i=i+1) begin
if ($left (abg[1:0], i) != wdt(i )-1) begin $display("FAILED -- $left (abg[1:0], %0d) = %0d", i, $left (abg[1:0], i)); err=1; end;
if ($right (abg[1:0], i) != 0 ) begin $display("FAILED -- $right (abg[1:0], %0d) = %0d", i, $right (abg[1:0], i)); err=1; end;
if ($low (abg[1:0], i) != 0 ) begin $display("FAILED -- $low (abg[1:0], %0d) = %0d", i, $low (abg[1:0], i)); err=1; end;
if ($high (abg[1:0], i) != wdt(i )-1) begin $display("FAILED -- $high (abg[1:0], %0d) = %0d", i, $high (abg[1:0], i)); err=1; end;
if ($increment(abg[1:0], i) != 1 ) begin $display("FAILED -- $increment(abg[1:0], %0d) = %0d", i, $increment(abg[1:0], i)); err=1; end;
if ($size (abg[1:0], i) != wdt(i ) ) begin $display("FAILED -- $size (abg[1:0], %0d) = %0d", i, $size (abg[1:0], i)); err=1; end;
end
// single array element
if ($dimensions(abg[0]) != 2) begin $display("FAILED -- $dimensions(abg[0]) = %0d", $dimensions(abg[0])); err=1; end;
if ($bits (abg[0]) != WB*WC) begin $display("FAILED -- $bits (abg[0]) = %0d", $bits (abg[0])); err=1; end;
for (i=1; i<=2; i=i+1) begin
if ($left (abg[0] , i) != wdt(i+1)-1) begin $display("FAILED -- $left (abg[0] , %0d) = %0d", i, $left (abg[0] , i)); err=1; end;
if ($right (abg[0] , i) != 0 ) begin $display("FAILED -- $right (abg[0] , %0d) = %0d", i, $right (abg[0] , i)); err=1; end;
if ($low (abg[0] , i) != 0 ) begin $display("FAILED -- $low (abg[0] , %0d) = %0d", i, $low (abg[0] , i)); err=1; end;
if ($high (abg[0] , i) != wdt(i+1)-1) begin $display("FAILED -- $high (abg[0] , %0d) = %0d", i, $high (abg[0] , i)); err=1; end;
if ($increment(abg[0] , i) != 1 ) begin $display("FAILED -- $increment(abg[0] , %0d) = %0d", i, $increment(abg[0] , i)); err=1; end;
if ($size (abg[0] , i) != wdt(i+1) ) begin $display("FAILED -- $size (abg[0] , %0d) = %0d", i, $size (abg[0] , i)); err=1; end;
end
// little endian
// full array
if ($dimensions(alt) != 3) begin $display("FAILED -- $dimensions(alt) = %0d", $dimensions(alt)); err=1; end;
if ($bits (alt) != WA*WB*WC) begin $display("FAILED -- $bits (alt) = %0d", $bits (alt)); err=1; end;
for (i=1; i<=3; i=i+1) begin
if ($left (alt , i) != 0 ) begin $display("FAILED -- $left (alt , %0d) = %0d", i, $left (alt , i)); err=1; end;
if ($right (alt , i) != wdt(i )-1) begin $display("FAILED -- $right (alt , %0d) = %0d", i, $right (alt , i)); err=1; end;
if ($low (alt , i) != 0 ) begin $display("FAILED -- $low (alt , %0d) = %0d", i, $low (alt , i)); err=1; end;
if ($high (alt , i) != wdt(i )-1) begin $display("FAILED -- $high (alt , %0d) = %0d", i, $high (alt , i)); err=1; end;
if ($increment(alt , i) != -1 ) begin $display("FAILED -- $increment(alt , %0d) = %0d", i, $increment(alt , i)); err=1; end;
if ($size (alt , i) != wdt(i ) ) begin $display("FAILED -- $size (alt , %0d) = %0d", i, $size (alt , i)); err=1; end;
end
// half array
if ($dimensions(alt[0:1]) != 3) begin $display("FAILED -- $dimensions(alt[0:1]) = %0d", $dimensions(alt[0:1])); err=1; end;
if ($bits (alt[0:1]) != 2*WB*WC) begin $display("FAILED -- $bits (alt[0:1]) = %0d", $bits (alt[0:1])); err=1; end;
for (i=1; i<=3; i=i+1) begin
if ($left (alt[0:1], i) != 0 ) begin $display("FAILED -- $left (alt[0:1], %0d) = %0d", i, $left (alt[0:1], i)); err=1; end;
if ($right (alt[0:1], i) != wdt(i )-1) begin $display("FAILED -- $right (alt[0:1], %0d) = %0d", i, $right (alt[0:1], i)); err=1; end;
if ($low (alt[0:1], i) != 0 ) begin $display("FAILED -- $low (alt[0:1], %0d) = %0d", i, $low (alt[0:1], i)); err=1; end;
if ($high (alt[0:1], i) != wdt(i )-1) begin $display("FAILED -- $high (alt[0:1], %0d) = %0d", i, $high (alt[0:1], i)); err=1; end;
if ($increment(alt[0:1], i) != -1 ) begin $display("FAILED -- $increment(alt[0:1], %0d) = %0d", i, $increment(alt[0:1], i)); err=1; end;
if ($size (alt[0:1], i) != wdt(i ) ) begin $display("FAILED -- $size (alt[0:1], %0d) = %0d", i, $size (alt[0:1], i)); err=1; end;
end
// single array element
if ($dimensions(alt[0]) != 2) begin $display("FAILED -- $dimensions(alt) = %0d", $dimensions(alt)); err=1; end;
if ($bits (alt[0]) != WB*WC) begin $display("FAILED -- $bits (alt) = %0d", $bits (alt)); err=1; end;
for (i=1; i<=2; i=i+1) begin
if ($left (alt[0] , i) != 0 ) begin $display("FAILED -- $left (alt[0] , %0d) = %0d", i, $left (alt[0] , i)); err=1; end;
if ($right (alt[0] , i) != wdt(i+1)-1) begin $display("FAILED -- $right (alt[0] , %0d) = %0d", i, $right (alt[0] , i)); err=1; end;
if ($low (alt[0] , i) != 0 ) begin $display("FAILED -- $low (alt[0] , %0d) = %0d", i, $low (alt[0] , i)); err=1; end;
if ($high (alt[0] , i) != wdt(i+1)-1) begin $display("FAILED -- $high (alt[0] , %0d) = %0d", i, $high (alt[0] , i)); err=1; end;
if ($increment(alt[0] , i) != -1 ) begin $display("FAILED -- $increment(alt[0] , %0d) = %0d", i, $increment(alt[0] , i)); err=1; end;
if ($size (alt[0] , i) != wdt(i+1) ) begin $display("FAILED -- $size (alt[0] , %0d) = %0d", i, $size (alt[0] , i)); err=1; end;
end
if (!err) $display("PASSED");
end
endmodule // test
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFSBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__SDFSBP_FUNCTIONAL_PP_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_lp__udp_dff_ps_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_lp__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_lp__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFSBP_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5; int from[N], to[N]; int main() { cin.tie(NULL); ios_base::sync_with_stdio(0); int n, m; cin >> n >> m; vector<pair<int, int> > mst; set<pair<int, int> > freeEdges; for (int i = 0; i < (int)(m); ++i) { int w, isMST; cin >> w >> isMST; if (isMST) { mst.push_back(make_pair(w, i)); } else { freeEdges.insert(make_pair(w, i)); } } sort(mst.begin(), mst.end()); for (int i = 0; i < (int)(n - 1); ++i) { int id = mst[i].second; from[id] = i; to[id] = i + 1; } int u = 0, v = 2; for (int i = 0; i < (int)(m - n + 1); ++i) { int cur = mst[v - 1].first; auto it = freeEdges.lower_bound(make_pair(cur, -1)); if (freeEdges.empty() || it == freeEdges.end()) { cout << -1; return 0; } int id = it->second; from[id] = u; to[id] = v; --u; if (u == -1) { u = v - 1; ++v; } freeEdges.erase(it); } for (int i = 0; i < (int)(m); ++i) { cout << 1 + from[i] << << 1 + to[i] << endl; } return 0; }
|
// $Revision: #70 $$Date: 2002/10/19 $$Author: wsnyder $ -*- Verilog -*-
//====================================================================
module CmpEng (/*AUTOARG*/
// Inputs
clk, reset_l
);
input clk;
input reset_l;
// ****************************************************************
/*AUTOREG*/
/*AUTOWIRE*/
// ********* Prefetch FSM definitions ****************************
reg [3:0] m_cac_state_r;
reg [2:0] m_cac_sel_r, m_dat_sel_r, m_cac_rw_sel_r;
reg m_wid1_r;
reg [2:0] m_wid3_r;
reg [5:2] m_wid4_r_l;
logic [4:1] logic_four;
logic [PARAM-1:0] paramed;
`define M 2
`define L 1
parameter MS = 2;
parameter LS = 1;
reg [MS:LS] m_param_r;
reg [`M:`L] m_def2_r;
always @ (posedge clk) begin
if (~reset_l) begin
m_cac_state_r <= CAC_IDLE;
m_cac_sel_r <= CSEL_PF;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
logic_four <= '0;
m_def2_r <= '0;
m_param_r <= '0;
m_wid1_r <= '0;
m_wid3_r <= '0;
m_wid4_r_l <= ~'0;
paramed <= '0;
// End of automatics
end
else begin
m_wid1_r <= 0;
m_wid3_r <= 0;
m_wid4_r_l <= 0;
m_param_r <= 0;
m_def2_r <= 0;
logic_four <= 4;
paramed <= 1;
end
end
endmodule
// Local Variables:
// verilog-auto-read-includes:t
// verilog-auto-sense-defines-constant: t
// verilog-auto-reset-widths: unbased
// verilog-active-low-regexp: "_l$"
// End:
|
#include <bits/stdc++.h> using namespace std; template <typename T> T sqr(T x) { return x * x; } template <typename T> T abs(T x) { return x < 0 ? -x : x; } template <typename T> T gcd(T a, T b) { return b ? gcd(b, a % b) : a; } const int MAXN = 8009; const int MAXX = (int)1e+6 + 7; struct triple { int x, l, r; triple(int x = 0, int l = 0, int r = 0) : x(x), l(l), r(r) {} }; int s[MAXN]; vector<triple> v[MAXN]; int lg[MAXX]; int upd[MAXX], cnt; int n, m; int cpwr[MAXX]; int count_power(int l, int r) { return lg[r] - lg[l - 1]; } int main(int argc, char **argv) { ios_base::sync_with_stdio(false); lg[0] = -1; lg[1] = 0; for (int i = 2; i < MAXX; ++i) { lg[i] = lg[i >> 1] + 1; } cin >> n >> m; s[1] = 1; for (int i = 2; i <= n; ++i) { s[i] = s[i - 1] + lg[s[i - 1]] + 1; } while (m--) { int t; cin >> t; if (t == 1) { int l, r, x; cin >> t >> l >> r >> x; v[t].push_back(triple(x, l, r)); } else { int l, r, ans = 0; cin >> t >> l; r = l; ++cnt; for (; t <= n; ++t) { for (size_t i = 0; i < v[t].size(); ++i) { if (l <= v[t][i].r && v[t][i].l <= r && upd[v[t][i].x] != cnt) { upd[v[t][i].x] = cnt; ++ans; } } int len = r - l + 1; int k = count_power(l, r); l += count_power(1, l - 1); r = l + len - 1 + k; } cout << ans << n ; } } return 0; }
|
// file: clock_divider.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1___100.000______0.000______50.0______144.719____114.212
// CLK_OUT2_____7.143______0.000______50.0______244.806____114.212
// CLK_OUT3____25.000______0.000______50.0______191.696____114.212
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "clock_divider,clk_wiz_v5_1,{component_name=clock_divider,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=PLL,num_out_clk=3,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module clock_divider
(
// Clock in ports
input CLOCK_PLL,
// Clock out ports
output CLOCK_100,
output CLOCK_7_143,
output CLOCK_25,
// Status and control signals
input reset,
output locked
);
clock_divider_clk_wiz inst
(
// Clock in ports
.CLOCK_PLL(CLOCK_PLL),
// Clock out ports
.CLOCK_100(CLOCK_100),
.CLOCK_7_143(CLOCK_7_143),
.CLOCK_25(CLOCK_25),
// Status and control signals
.reset(reset),
.locked(locked)
);
endmodule
|
// DEFINES
`define BITS 8 // Bit width of the operands
`define B2TS 16 // Bit width of the operands
`define USEAND 0 // No available documentation provides for macros without values so we use 0
module bm_base_multiply(clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
e_in,
f_in,
out0,
out2,
out3,
out4,
out1);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input [`BITS-1:0] c_in;
input [`BITS-1:0] d_in;
input [`BITS-1:0] e_in;
input [`BITS-2:0] f_in;
output [`B2TS-1:0] out0;
output [`B2TS-1:0] out1;
output [`B2TS-1:0] out2;
output [14:0] out3;
output [14:0] out4;
reg [`B2TS-1:0] out0;
wire [`B2TS-1:0] out1;
reg [`B2TS-1:0] out2;
reg [14:0] out3;
wire [14:0] out4;
wire [`BITS-1:0] temp_a;
wire [`BITS-1:0] temp_b;
wire temp_c;
wire temp_d;
a top_a(clock, a_in, b_in, temp_a);
b top_b(clock, a_in, b_in, temp_b);
always @(posedge clock)
begin
out0 <= a_in * b_in;
out2 <= temp_a & temp_b;
out3 <= e_in * f_in;
end
assign out1 = c_in * d_in;
assign out4 = f_in * e_in;
endmodule
`ifdef USEAND
`include "ifdef_else_module_a_and.v"
`else
`include "ifdef_else_module_a_or.v"
`endif
`include "ifdef_else_module_b.v"
|
#include <bits/stdc++.h> int main() { std::ios::sync_with_stdio(false); std::cin.tie(0); std::cout.tie(0); int32_t n; std::cin >> n; std::set<std::pair<int32_t, int32_t> > segments; for (int32_t i = 0; i < n; i++) { int32_t left, right; std::cin >> left >> right; auto it = segments.lower_bound({left, 0}); if (it != segments.begin()) { it--; if (it->second < left) it++; } int32_t min_left = left, max_right = right; while (it != segments.end() && ((it->second >= left && it->second <= right) || (it->first >= left && it->first <= right) || (it->first <= left && it->second >= right))) { min_left = std::min(min_left, it->first); max_right = std::max(max_right, it->second); auto next = it; next++; segments.erase(it); it = next; } segments.emplace(min_left, max_right); std::cout << segments.size() << ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; struct node { int id, v; } tree[4 * 100005]; int in[100005]; void build(int nod, int s, int e) { if (s == e) { tree[nod].id = s; tree[nod].v = in[s]; return; } int mid = (s + e) / 2, l = 2 * nod, r = l + 1; build(l, s, mid); build(r, mid + 1, e); if (tree[l].v > tree[r].v) { tree[nod].v = tree[l].v; tree[nod].id = tree[l].id; } else { tree[nod].v = tree[r].v; tree[nod].id = tree[r].id; } } pair<int, int> query(int nod, int s, int e, int i, int j) { if (s > j || e < i) return {-1, -1}; if (s >= i && e <= j) return {tree[nod].v, tree[nod].id}; int mid = (s + e) / 2, l = 2 * nod, r = l + 1; pair<int, int> a = query(l, s, mid, i, j); pair<int, int> b = query(r, mid + 1, e, i, j); if (a.first > b.first) return a; else return b; } long long save[100005]; long long ans[100005]; int main() { int n, i; scanf( %d , &n); for (i = 1; i < n; i++) { scanf( %d , &in[i]); } build(1, 1, n); save[n - 1] = 1; ans[n - 1] = 1; pair<int, int> a = query(1, 1, n, 6, 8); for (i = n - 2; i >= 1; i--) { pair<int, int> pp = query(1, 1, n, i + 1, in[i]); save[i] = pp.second - i + save[pp.second] + n - in[i]; ans[i] = ans[i + 1] + save[i]; } printf( %I64d n , ans[1]); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND2_4_V
`define SKY130_FD_SC_LS__NAND2_4_V
/**
* nand2: 2-input NAND.
*
* Verilog wrapper for nand2 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nand2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand2_4 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nand2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand2_4 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nand2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND2_4_V
|
`timescale 1ns / 1ps
module quick_spi_soft_testbench;
reg clk;
reg rst_n;
wire end_of_transaction;
wire[7:0] incoming_data;
reg[15:0] outgoing_data;
wire mosi;
reg miso;
wire sclk;
wire[1:0] ss_n;
reg start_transaction;
reg operation;
integer sclk_toggle_count;
reg[8:0] incoming_data_buffer;
reg spi_clock_phase;
initial begin
clk <= 1'b0;
rst_n <= 1'b0;
rst_n <= #50 1'b1;
end
always @ (posedge clk) begin
if(!rst_n) begin
outgoing_data <= {8'b00011010, 8'b01101010};
operation <= 1'b0;
miso <= 1'b0;
sclk_toggle_count <= 0;
incoming_data_buffer <= {8'b10010101, 1'b1};
spi_clock_phase <= 1'b1;
end
else begin
if(sclk_toggle_count > 36 && operation == 1'b0) begin
if(!spi_clock_phase) begin
miso <= incoming_data_buffer[0];
incoming_data_buffer <= incoming_data_buffer >> 1;
end
end
sclk_toggle_count <= sclk_toggle_count + 1;
spi_clock_phase <= ~spi_clock_phase;
end
end
quick_spi_soft spi(
.s_axi_aclk(clk),
.s_axi_aresetn(rst_n),
.mosi(mosi),
.miso(miso),
.sclk(sclk),
.ss_n(ss_n));
always #25 clk <= ~clk;
endmodule
|
#include <bits/stdc++.h> using namespace std; struct node { bool flag = 0; long long sum1 = 0, sum2 = 0; void operator+=(const node& rhs) { flag |= rhs.flag; sum1 += rhs.sum1; sum2 = max(sum2, rhs.sum2); } }; const int N = 200200; int n, m, s, T; int par[N], siz[N]; int tin[N], low[N]; long long a[N]; vector<int> edges[N], tree[N]; vector<pair<int, int>> bridges; int findSetId(int u) { return (par[u] == u ? u : par[u] = findSetId(par[u])); } void findBridges(int u = 1, int p = -1) { tin[u] = low[u] = ++T; for (int v : edges[u]) { if (v == p) { continue; } if (tin[v] == 0) { findBridges(v, u); if (low[v] > tin[u]) { bridges.push_back({u, v}); } else { int x = findSetId(u); int y = findSetId(v); if (x != y) { par[y] = x; siz[x] += siz[y]; a[x] += a[y]; } } } low[u] = min(low[u], low[v]); } } void buildBridgeTree() { for (int i = 1; i <= n; ++i) { par[i] = i, siz[i] = 1; } findBridges(); for (auto& b : bridges) { int u = findSetId(b.first); int v = findSetId(b.second); tree[u].push_back(v); tree[v].push_back(u); } } node solve(int u = s, int p = -1) { node ret; for (int v : tree[u]) { if (v == p) { continue; } ret += solve(v, u); } if (siz[u] > 1 || ret.flag) { ret.sum1 += a[u], ret.flag = 1; } else { ret.sum2 += a[u]; } return ret; } int main() { cin >> n >> m; for (int i = 1; i <= n; ++i) { scanf( %lld , a + i); } while (m--) { int u, v; scanf( %d %d , &u, &v); edges[u].push_back(v); edges[v].push_back(u); } cin >> s; buildBridgeTree(); auto out = solve(findSetId(s)); cout << out.sum1 + out.sum2; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XNOR3_TB_V
`define SKY130_FD_SC_HDLL__XNOR3_TB_V
/**
* xnor3: 3-input exclusive NOR.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__xnor3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_hdll__xnor3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XNOR3_TB_V
|
#include <bits/stdc++.h> using namespace std; const long long somod = 1e9 + 7; const long long maxn = 5e4 + 7; long long cntnode = 1, m, n, a[maxn]; vector<long long> vt[maxn * 31]; long long cac[32][2]; map<long long, vector<long long>> mp; long long Pow(long long a, long long b) { long long ans = 1; for (; b > 0; b >>= 1, a = a * a % somod) { if (b & 1) ans = ans * a % somod; } return ans; } void Update(long long x, long long delta) { for (long long i = 29; i >= 0; i--) { cac[i][(x >> i & 1)] += delta; } } long long Cal(long long x) { long long ans = 0; for (long long i = 29; i >= 0; i--) { ans += cac[i][(x >> i & 1) ^ 1] * (1 << i); ans %= somod; } return ans; } pair<long long, long long> Count(long long curval, long long lastbit) { mp.clear(); long long f = 0, s = 0; for (long long i = 1; i <= n; i++) { long long val = 0; for (long long j = 29; j >= lastbit; j--) { val ^= (a[i] & (1 << j)); } mp[val].push_back(a[i]); } for (auto i : mp) { long long yay = i.first ^ curval; if (mp.count(yay) == 0) continue; s += mp[yay].size() * i.second.size(); for (auto j : i.second) Update(j, 1); for (auto j : mp[yay]) f = f + Cal(j); f %= somod; for (auto j : i.second) Update(j, -1); } s /= 2; f = f * Pow(2, somod - 2) % somod; return {f, s}; } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); if (fopen( test.inp , r )) freopen( test.inp , r , stdin); cin >> n >> m; for (long long i = 1; i <= n; i++) { cin >> a[i]; } long long val = 0, ans = 0; for (long long i = 29; i >= 0; i--) { pair<long long, long long> cc = Count(val ^ (1 << i), i); if (cc.second <= m) { m -= cc.second, ans += cc.first; } else { val ^= (1 << i); } if (i == 0) { ans += (val)*m; } } cout << ans % somod << n ; }
|
#include <bits/stdc++.h> using namespace std; int n, m; vector<pair<char, long long> > s1; vector<pair<char, long long> > s2; vector<pair<char, long long> > p; int sl, pl; int lps[1000009]; vector<int> ii; void calclps() { lps[0] = 0; int j = 0, i = 1; while (i < pl) { if (p[j] == p[i]) { if (j == 0) { lps[i] = 1; } else { lps[i] = j + 1; } j++; i++; } else { if (j == 0) { lps[i] = 0; i++; } else { j = lps[j - 1]; } } } } void kmp() { ii.clear(); if (p.size() == 1) { for (int i = 0; i < (int)sl; i++) { if (s1[i] == p[0]) ii.push_back(i); } return; } calclps(); int i = 0, j = 0; while (i < sl) { if (s1[i] == p[j]) { if (j == pl - 1) { ii.push_back(i - pl + 1); j = lps[j - 1]; } else { i++; j++; } } else { if (j == 0) i++; else j = lps[j - 1]; } } } void print(vector<pair<char, long long> > v) { cout << printing : << endl; for (int i = 0; i < (int)v.size(); i++) { cout << v[i].first << << v[i].second << endl; } } int main() { scanf( %d , &n); scanf( %d , &m); for (int i = 0; i < n; i++) { long long a; cin >> a; getchar(); char c = getchar(); if (i != 0 && s1[s1.size() - 1].first == c) { s1[s1.size() - 1].second += a; } else { s1.push_back(make_pair(c, a)); } } for (int i = 0; i < m; i++) { long long a; cin >> a; getchar(); char c = getchar(); if (i != 0 && s2[s2.size() - 1].first == c) { s2[s2.size() - 1].second += a; } else { s2.push_back(make_pair(c, a)); } } long long ans = 0; if (s2.size() == 1) { char c = s2[0].first; long long v = s2[0].second; for (int i = 0; i < (int)s1.size(); i++) { if (c == s1[i].first && s1[i].second >= v) { ans += s1[i].second - v + 1; } } } else if (s2.size() == 2) { char c1 = s2[0].first; char c2 = s2[1].first; long long v1 = s2[0].second; long long v2 = s2[1].second; for (int i = 1; i < (int)s1.size(); i++) { if (s1[i - 1].first == c1 && s1[i].first == c2 && s1[i - 1].second >= v1 && s1[i].second >= v2) ans++; } } else { for (int i = 1; i < (int)s2.size() - 1; i++) { p.push_back(s2[i]); } sl = s1.size(); pl = p.size(); kmp(); for (int i = 0; i < (int)ii.size(); i++) { int x = ii[i]; if (x > 0 && x + pl < n && s1[x - 1].first == s2[0].first && s1[x - 1].second >= s2[0].second && s1[x + pl].first == s2[s2.size() - 1].first && s1[x + pl].second >= s2[s2.size() - 1].second) ans++; } } cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; template <typename T> void read(T &x) { x = 0; char c; for (c = getchar(); !isdigit(c); c = getchar()) ; for (; isdigit(c); c = getchar()) x = x * 10 + c - 0 ; } const int N = 255, P = 998244353, oo = 0x3f3f3f3f; int mul(int a, int b) { return 1ll * a * b % P; } int add(int a, int b) { a += b; return a >= P ? a - P : a; } int sub(int a, int b) { a -= b; return a < 0 ? a + P : a; } int gcd(int a, int b) { return !b ? a : gcd(b, a % b); } namespace Dinic { const int S = N * N; struct Edge { int d, cap, nxt; } es[S << 2]; int vn, g[S], lev[S], itr[S], q[S], h, t, en = 1; void add(int s, int d, int cap) { es[++en] = (Edge){d, cap, g[s]}, g[s] = en; es[++en] = (Edge){s, 0, g[d]}, g[d] = en; } void bfs(int s) { int v; memset(lev, -1, sizeof(lev)); h = t = 0; q[t++] = s; lev[s] = 0; while (h < t) { v = q[h++]; for (int i = g[v], d = es[i].d; i; i = es[i].nxt, d = es[i].d) { if (es[i].cap > 0 && lev[d] < 0) { lev[d] = lev[v] + 1; q[t++] = es[i].d; } } } } int dfs(int v, int t, int f) { if (v == t) return f; for (int &i = itr[v]; i; i = es[i].nxt) { if (es[i].cap <= 0 || lev[es[i].d] <= lev[v]) continue; int a = dfs(es[i].d, t, min(es[i].cap, f)); if (a <= 0) continue; es[i].cap -= a; es[i ^ 1].cap += a; return a; } return 0; } int sol(int s, int t) { int i, res = 0, a; while (true) { bfs(s); if (lev[t] < 0) break; for (i = 0; i <= vn; ++i) itr[i] = g[i]; for (a = dfs(s, t, oo); a > 0; a = dfs(s, t, oo)) { res += a; } } return res; } } // namespace Dinic using namespace Dinic; int n, m; vector<int> xx, yy; struct Rec { int x1, y1, x2, y2; } rec[N]; int f(vector<int> &a, int x) { return lower_bound(a.begin(), a.end(), x) - a.begin() + 1; } int main(int argc, char *argv[]) { scanf( %d%d , &n, &m); for (int i = 1; i <= (m); ++i) { int x1, y1, x2, y2; scanf( %d%d%d%d , &x1, &y1, &x2, &y2); --x1, --y1; xx.push_back(x1), xx.push_back(x2); yy.push_back(y1), yy.push_back(y2); rec[i] = (Rec){x1, y1, x2, y2}; } xx.push_back(0), yy.push_back(0); sort(xx.begin(), xx.end()), sort(yy.begin(), yy.end()); xx.erase(unique(xx.begin(), xx.end()), xx.end()); yy.erase(unique(yy.begin(), yy.end()), yy.end()); int sx = xx.size(), sxy = sx + yy.size(), src = sxy + m + 1, snk = src + 1; vn = snk; for (int i = 1; i < (xx.size()); ++i) { add(src, i + 1, xx[i] - xx[i - 1]); } for (int i = 1; i < (yy.size()); ++i) { add(sx + i + 1, snk, yy[i] - yy[i - 1]); } for (int i = 1; i <= (m); ++i) { int x1 = rec[i].x1, x2 = rec[i].x2, y1 = rec[i].y1, y2 = rec[i].y2; x1 = f(xx, x1); x2 = f(xx, x2); y1 = f(yy, y1); y2 = f(yy, y2); for (int j = x1 + 1; j <= x2; ++j) add(j, sxy + i, oo); for (int j = y1 + 1; j <= y2; ++j) add(sxy + i, sx + j, oo); } cout << sol(src, snk) << endl; }
|
#include <bits/stdc++.h> using std::cin; using std::cout; using std::endl; using std::pair; using std::string; using std::vector; using vi = vector<int>; using pii = pair<int, int>; using vii = vector<pii>; using ll = long long; int solve(); int main(int argc, char* argv[]) { ::std::ios::sync_with_stdio(false); ::std::cin.tie(0); ::std::cout.tie(0); int t = 1; for (int i = 1; i <= t; ++i) { solve(); } } constexpr int MAX_N = 505050; constexpr int MOD = 998244353; int t[4 * MAX_N][2][2]; int n, m; char s[MAX_N]; void pushup(int k) { memset(t[k], 0, sizeof(t[k])); for (int i = 0; i < 2; ++i) { for (int j = 0; j < 2; ++j) { t[k][i][j] = (t[k * 2][i][0] * 1LL * t[k * 2 + 1][0][j] + t[k * 2][i][1] * 1LL * t[k * 2 + 1][1][j]) % MOD; } } } void build(int k, int L, int R) { if (L == R) { memset(t[k], 0, sizeof(t[k])); t[k][1][0] = 1; t[k][0][0] = s[L] + 1; if (s[L] == 1) t[k][0][1] = 9 - s[L + 1]; return; } int mid = (L + R) / 2; build(k * 2, L, mid); build(k * 2 + 1, mid + 1, R); pushup(k); } void change(int k, int L, int R, int P) { if (L == R) { memset(t[k], 0, sizeof(t[k])); t[k][1][0] = 1; t[k][0][0] = s[L] + 1; if (s[L] == 1) t[k][0][1] = 9 - s[L + 1]; return; } int mid = (L + R) / 2; if (P <= mid) change(k * 2, L, mid, P); else change(k * 2 + 1, mid + 1, R, P); pushup(k); } int solve() { string str; cin >> n >> m; cin >> str; for (int i = 1; i <= n; ++i) s[i] = str[i - 1] - 0 ; build(1, 1, n); while (m--) { int x, y; cin >> x >> y; s[x] = y; if (x != 1) change(1, 1, n, x - 1); change(1, 1, n, x); cout << t[1][0][0] << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } int lcm(int a, int b) { return a / gcd(a, b) * b; } const int mod = 1e9 + 7; long long binpow(long long a, long long b) { long long res = 1; while (b > 0) if (b & 1) { res = (long long)(res * 1ll * a); --b; } else { a = (long long)(a * 1ll * a); b >>= 1; } return (long long)res; } vector<vector<int>> g; vector<bool> used; vector<long double> ver; void dfs(int v, int prev) { used[v] = true; double cnt = 0, sum = 0; for (int i = 0; i < g[v].size(); i++) { int to = g[v][i]; if (to == prev) continue; dfs(to, v); sum += ver[to]; cnt++; } if (cnt == 0) ver[v] = 0; else ver[v] = 1 + sum / cnt; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int q; cin >> q; while (q--) { int n; cin >> n; if (n % 4 == 0) { cout << YES << endl; } else cout << NO << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 1 << 29; const int MOD = 1000000007; bool isPowerOfTwo(long long int x) { return x && (!(x & (x - 1))); } void fastio() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); } const int dx[] = {1, 0, -1, 0, 1, 1, -1, -1}; const int dy[] = {0, -1, 0, 1, 1, -1, -1, 1}; int main() { fastio(); int t = 1; while (t--) { int n; cin >> n; string s; cin >> s; int ans = 0; for (int i = 0; i < (s.length()); i++) { int x = int(s[i]) - 48; if (x % 2 == 0) ans += (i + 1); } cout << ans << n ; } return 0; }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module ANN_ddiv_64ns_64ns_64_31
#(parameter
ID = 7,
NUM_STAGE = 31,
din0_WIDTH = 64,
din1_WIDTH = 64,
dout_WIDTH = 64
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [63:0] a_tdata;
wire b_tvalid;
wire [63:0] b_tdata;
wire r_tvalid;
wire [63:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
ANN_ap_ddiv_29_no_dsp_64 ANN_ap_ddiv_29_no_dsp_64_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1==='bx ? 'b0 : din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1==='bx ? 'b0 : din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const double eps(1e-8); char s[1000010]; int n, m, a, b; vector<int> vec[1000010]; vector<int> p[1000010]; int x[1000010], y[1000010], sum[1000010], ans[1000010]; int Lowbit(int x) { return x & (-x); } void Update(int pos, int val) { while (pos > 0) { sum[pos] += val; pos -= Lowbit(pos); } } int Query(int pos) { int ret = 0; while (pos <= n) { ret += sum[pos]; pos += Lowbit(pos); } return ret; } void Add(int l, int r, int val) { Update(r, val); Update(l - 1, -val); } int main() { scanf( %s , s + 1); for (n = 1; s[n]; n++) ; n--; scanf( %d , &m); for (int i = 1; i <= m; i++) { scanf( %d%d , &a, &b); vec[b].push_back(a); p[b].push_back(i); } int len = 0; for (int i = 1; i <= n; i++) { len++; if (s[i] == ( ) x[len] = 0; else x[len] = 1; y[len] = i; if (len >= 2 && x[len] == 1 && x[len - 1] == 0) { Add(1, y[len - 1], 2); len -= 2; } for (int j = 0; j < (int)vec[i].size(); j++) { int tmp = vec[i][j]; ans[p[i][j]] = Query(tmp); } } for (int i = 1; i <= m; i++) printf( %d n , ans[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; int dp[255][105][105]; int c[255][255]; int cc[1005]; int N; string s; int f(char l, int i, int k) { if (i == N) return 0; if (dp[l][i][k] != -1) return dp[l][i][k]; int r = f(s[i], i + 1, k) + c[l][s[i]]; if (k) { for (char x = a ; x <= z ; x++) r = max(r, f(x, i + 1, k - 1) + c[l][x]); } return dp[l][i][k] = r; } int main() { int k, m; char x, y; int z; cin >> s >> k >> m; N = s.size(); for (int i = 0; i < m; i++) { cin >> x >> y >> z; c[x][y] = z; } memset(dp, -1, sizeof(dp)); cout << f( # , 0, k) << endl; return 0; }
|
#include <bits/stdc++.h> int main() { int n; scanf( %d , &n); for (int i = 1; i <= n - n / 3; i++) printf( 1 %d n , i); for (int i = 1; i <= n / 3; i++) printf( 4 %d n , 2 * i); return 0; }
|
#include <bits/stdc++.h> const int maxn = 1025; const int maxm = 10; using namespace std; int main() { int n; string s; cin >> n; cin >> s; int ans1 = 0, ans2 = 0; int cnt1 = 0; int f = 0; for (int i = 0; i < s.length(); i++) { if (s[i] == ( ) { f = 1; ans1 = max(ans1, cnt1); cnt1 = 0; continue; } if (s[i] == ) ) { f = 0; continue; } if (!f) { if (s[i] != _ ) { cnt1++; } else { ans1 = max(ans1, cnt1); cnt1 = 0; } } if (f) { if ((s[i - 1] == ( || s[i - 1] == _ ) && s[i] != _ ) { ans2++; } } } ans1 = max(ans1, cnt1); cnt1 = 0; cout << ans1 << << ans2 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[103], n, x, y, m, ans; int main() { cin >> x >> y >> n; m = x * y; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < m; i++) { int x, j; cin >> x; for (j = 0; j < n; j++) { if (a[j] == x) break; } ans = ans + j + 1; for (int k = j - 1; k >= 0; k--) a[k + 1] = a[k]; a[0] = x; } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; struct tree { int maxv[650001]; void set(int x, int d, int o, int l, int r) { if (l == r) { maxv[o] = d; return; } int m = (l + r) / 2; if (x <= m) set(x, d, o * 2, l, m); else set(x, d, o * 2 + 1, m + 1, r); maxv[o] = max(maxv[o * 2], maxv[o * 2 + 1]); } int query(int x, int y, int o, int l, int r) { if (x <= l && r <= y) return maxv[o]; int m = (l + r) / 2, ans = 0; if (x <= m) ans = max(ans, query(x, y, o * 2, l, m)); if (y > m) ans = max(ans, query(x, y, o * 2 + 1, m + 1, r)); return ans; } } Tx, Ty; int n, m; map<int, int> h, pos; void modify(int x, int y, int val) { Tx.set(x, val, 1, 1, n); Ty.set(y, val, 1, 1, m + 20); } void remove_all(map<int, int>::iterator del) { modify(del->first, del->second, 0); pos.erase(pos.lower_bound(del->second)); h.erase(del); } int main() { scanf( %d%d , &n, &m); for (int T = 1; T <= m; T++) { int op, p, v; scanf( %d%d , &op, &p); if (op == 1) { scanf( %d , &v); v += m - T; h[p] = v; pos[v] = p; auto it = pos.lower_bound(v), it2 = it; for (;; it2--) { modify(it2->second, it2->first, 0); if (it2 == pos.begin()) break; } for (;; it--) { int x = it->second, y = it->first, val = Tx.query(x, n, 1, 1, n) + 1; modify(x, y, val); if (it == pos.begin()) break; } } else { auto del = h.begin(); for (int i = 1; i < p; i++) del++; if (del == h.begin()) remove_all(del); else { auto it = del, it2 = --it; remove_all(del); for (;; it2--) { modify(it2->first, it2->second, 0); if (it2 == h.begin()) break; } for (;; it--) { int x = it->first, y = it->second, val = Ty.query(y + 1, m + 20, 1, 1, m + 20) + 1; modify(x, y, val); if (it == h.begin()) break; } } } printf( %d n , Tx.query(1, n, 1, 1, n)); } }
|
//-------------------------------------------------------------------
//-- rxleds_tb.v
//-- Testbench for the simulation of the rxleds.v
//-------------------------------------------------------------------
//-- (c) BQ December 2015. Written by Juan Gonzalez (Obijuan)
//-------------------------------------------------------------------
//-- GPL License
//-------------------------------------------------------------------
`timescale 100 ns / 10 ns
`include "baudgen.vh"
module rxleds_tb();
//-- Baudrate for the simulation
localparam BAUDRATE = `B115200;
//-- clock tics needed for sending one serial package
localparam SERIAL_PACK = (BAUDRATE * 10);
//-- Time between two characters
localparam WAIT = (BAUDRATE * 4);
//----------------------------------------
//-- Task for sending a character in serial
//----------------------------------------
task send_char;
input [7:0] char;
begin
rx <= 0; //-- Send the Start bit
#BAUDRATE rx <= char[0]; //-- Bit 0
#BAUDRATE rx <= char[1]; //-- Bit 1
#BAUDRATE rx <= char[2]; //-- Bit 2
#BAUDRATE rx <= char[3]; //-- Bit 3
#BAUDRATE rx <= char[4]; //-- Bit 4
#BAUDRATE rx <= char[5]; //-- Bit 5
#BAUDRATE rx <= char[6]; //-- Bit 6
#BAUDRATE rx <= char[7]; //-- Bit 7
#BAUDRATE rx <= 1; //-- stop bit
#BAUDRATE rx <= 1; //-- Wait until the bits stop is sent
end
endtask
//-- System clock
reg clk = 0;
//-- Wire connected to the rx port for transmiting to the receiver
reg rx = 1;
//-- For connecting the leds
wire [3:0] leds;
//-- Instantiate the entity to test
rxleds #(.BAUDRATE(BAUDRATE))
dut(
.clk(clk),
.rx(rx),
.leds(leds)
);
//-- Clock generator
always
# 0.5 clk <= ~clk;
initial begin
//-- File where to store the simulation
$dumpfile("rxleds_tb.vcd");
$dumpvars(0, rxleds_tb);
//-- Sent some data
#BAUDRATE send_char(8'h55);
#WAIT send_char("K");
#(WAIT * 4) $display("END of the simulation");
$finish;
end
endmodule
|
`timescale 1ns / 1ps
module hvsync_generator(clk, reset,vga_h_sync, vga_v_sync, inDisplayArea, CounterX, CounterY);
input clk;
input reset;
output vga_h_sync, vga_v_sync;
output inDisplayArea;
output [9:0] CounterX;
output [9:0] CounterY;
//////////////////////////////////////////////////
reg [9:0] CounterX;
reg [9:0] CounterY;
reg vga_HS, vga_VS;
reg inDisplayArea;
//increment column counter
always @(posedge clk)
begin
if(reset)
CounterX <= 0;
else if(CounterX==10'h320) //800
CounterX <= 0;
else
CounterX <= CounterX + 1'b1;
end
//increment row counter
always @(posedge clk)
begin
if(reset)
CounterY<=0;
else if(CounterY==10'h209) //521
CounterY<=0;
else if(CounterX==10'h320) //800
CounterY <= CounterY + 1'b1;
end
//generate synchronization signal for both vertical and horizontal
always @(posedge clk)
begin
vga_HS <= (CounterX > 655 && CounterX < 752); // change these values to move the display horizontally
vga_VS <= (CounterY == 490 || CounterY == 491); // change these values to move the display vertically
end
always @(posedge clk)
if(reset)
inDisplayArea<=0;
else
inDisplayArea <= (CounterX<640) && (CounterY<480);
assign vga_h_sync = ~vga_HS;
assign vga_v_sync = ~vga_VS;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title :
// File :
// Author : Jim MacLeod
// Created : 01-Dec-2011
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module flt_alu
(
input clk,
input rstn,
input [64:0] sum_0,
input [64:0] sum_1,
input [64:0] sum_2,
input [64:0] sum_3,
input [128:0] det,
input [63:0] div,
output [31:0] s0_s,
output [31:0] s1_s,
output [31:0] s2_s,
output [31:0] s3_s,
output [31:0] det_s,
output [31:0] div_result,
output [31:0] int0_s,
output [31:0] int1_s
);
/////////////////////////////////////////////////////////////////////
// FLOAT ALU
//
// Float Subtracts (Three Clock Cycles).
flt_add_sub u0_flt_add_sub(clk, sum_0[64], sum_0[63:32], sum_0[31:0], s0_s);
flt_add_sub u1_flt_add_sub(clk, sum_1[64], sum_1[63:32], sum_1[31:0], s1_s);
flt_add_sub u2_flt_add_sub(clk, sum_2[64], sum_2[63:32], sum_2[31:0], s2_s);
flt_add_sub u3_flt_add_sub(clk, sum_3[64], sum_3[63:32], sum_3[31:0], s3_s);
// Float Determinant(Six Clock Cycles).
flt_det u0_flt_det(clk, rstn, det, det_s);
// Float Divide (Seven Clock Cycles).
flt_div u0_flt_div(.clk(clk), .rstn(rstn), .numer_denom(div), .div_result(div_result));
// Float INT (Two Clock Cycles).
flt_int u0_flt_int(clk, s0_s, int0_s);
flt_int u1_flt_int(clk, s1_s, int1_s);
endmodule
|
`timescale 1ns / 1ps
module Registro_Juego(
clk,
reset_in,
c1_clear_in,
c2_clear_in,
c3_clear_in,
c4_clear_in,
c5_clear_in,
c6_clear_in,
c7_clear_in,
c8_clear_in,
c9_clear_in,
c1_in,
c2_in,
c3_in,
c4_in,
c5_in,
c6_in,
c7_in,
c8_in,
c9_in,
c1_out,
c2_out,
c3_out,
c4_out,
c5_out,
c6_out,
c7_out,
c8_out,
c9_out
);
input clk,reset_in;
input c1_clear_in, c2_clear_in, c3_clear_in, c4_clear_in, c5_clear_in, c6_clear_in, c7_clear_in, c8_clear_in, c9_clear_in;
input [1:0] c1_in, c2_in, c3_in, c4_in, c5_in, c6_in, c7_in, c8_in, c9_in;
output [1:0] c1_out, c2_out, c3_out, c4_out, c5_out, c6_out, c7_out, c8_out, c9_out;
reg clear_c1, clear_c2, clear_c3, clear_c4, clear_c5, clear_c6, clear_c7, clear_c8, clear_c9;
Registro2Bits espacio_1 (
.clk(clk),
.datos_i (c1_in),
.clear_i(c1_clear_in),
.salida_o(c1_out)
);
Registro2Bits espacio_2 (
.clk(clk),
.datos_i (c2_in),
.clear_i(c2_clear_in),
.salida_o(c2_out)
);
Registro2Bits espacio_3 (
.clk(clk),
.datos_i (c3_in),
.clear_i(c3_clear_in),
.salida_o(c3_out)
);
Registro2Bits espacio_4 (
.clk(clk),
.datos_i (c4_in),
.clear_i(c4_clear_in),
.salida_o(c4_out)
);
Registro2Bits espacio_5 (
.clk(clk),
.datos_i (c5_in),
.clear_i(c5_clear_in),
.salida_o(c5_out)
);
Registro2Bits espacio_6 (
.clk(clk),
.datos_i (c6_in),
.clear_i(c6_clear_in),
.salida_o(c6_out)
);
Registro2Bits espacio_7 (
.clk(clk),
.datos_i (c7_in),
.clear_i(c7_clear_in),
.salida_o(c7_out)
);
Registro2Bits espacio_8 (
.clk(clk),
.datos_i (c8_in),
.clear_i(c8_clear_in),
.salida_o(c8_out)
);
Registro2Bits espacio_9 (
.clk(clk),
.datos_i (c9_in),
.clear_i(c9_clear_in),
.salida_o(c9_out)
);
always @( posedge clk or posedge reset_in) begin
if(reset_in)
begin
clear_c1 <= 1;
clear_c2 <= 1;
clear_c3 <= 1;
clear_c4 <= 1;
clear_c5 <= 1;
clear_c6 <= 1;
clear_c7 <= 1;
clear_c8 <= 1;
clear_c9 <= 1;
end
else
begin
clear_c1 <= c1_clear_in;
clear_c2 <= c2_clear_in;
clear_c3 <= c3_clear_in;
clear_c4 <= c4_clear_in;
clear_c5 <= c5_clear_in;
clear_c6 <= c6_clear_in;
clear_c7 <= c7_clear_in;
clear_c8 <= c8_clear_in;
clear_c9 <= c9_clear_in;
end
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/*`include "sys.h"
`include "iop.h"
`include "ifu.h"
`include "tlu.h"
`include "lsu.h"
*/
`define PCX_WIDTH 124 //PCX payload packet width
`define CPX_WIDTH 145 //CPX payload packet width
module sparc (/*AUTOARG*/
// Outputs
spc_pcx_req_pq, spc_pcx_atom_pq, spc_pcx_data_pa, spc_sscan_so,
spc_scanout0, spc_scanout1, tst_ctu_mbist_done,
tst_ctu_mbist_fail, spc_efc_ifuse_data, spc_efc_dfuse_data,
// Inputs
pcx_spc_grant_px, cpx_spc_data_rdy_cx2, cpx_spc_data_cx2,
const_cpuid, const_maskid, ctu_tck, ctu_sscan_se, ctu_sscan_snap,
ctu_sscan_tid, ctu_tst_mbist_enable, efc_spc_fuse_clk1,
efc_spc_fuse_clk2, efc_spc_ifuse_ashift, efc_spc_ifuse_dshift,
efc_spc_ifuse_data, efc_spc_dfuse_ashift, efc_spc_dfuse_dshift,
efc_spc_dfuse_data, ctu_tst_macrotest, ctu_tst_scan_disable,
ctu_tst_short_chain, global_shift_enable, ctu_tst_scanmode,
spc_scanin0, spc_scanin1, cluster_cken, gclk, cmp_grst_l,
cmp_arst_l, ctu_tst_pre_grst_l, adbginit_l, gdbginit_l
);
// these are the only legal IOs
// pcx
output [4:0] spc_pcx_req_pq; // processor to pcx request
output spc_pcx_atom_pq; // processor to pcx atomic request
output [`PCX_WIDTH-1:0] spc_pcx_data_pa; // processor to pcx packet
// shadow scan
output spc_sscan_so; // From ifu of sparc_ifu.v
output spc_scanout0; // From test_stub of test_stub_bist.v
output spc_scanout1; // From test_stub of test_stub_bist.v
// bist
output tst_ctu_mbist_done; // From test_stub of test_stub_two_bist.v
output tst_ctu_mbist_fail; // From test_stub of test_stub_two_bist.v
// fuse
output spc_efc_ifuse_data; // From ifu of sparc_ifu.v
output spc_efc_dfuse_data; // From ifu of sparc_ifu.v
// cpx interface
input [4:0] pcx_spc_grant_px; // pcx to processor grant info
input cpx_spc_data_rdy_cx2; // cpx data inflight to sparc
input [`CPX_WIDTH-1:0] cpx_spc_data_cx2; // cpx to sparc data packet
input [3:0] const_cpuid;
input [7:0] const_maskid; // To ifu of sparc_ifu.v
// sscan
input ctu_tck; // To ifu of sparc_ifu.v
input ctu_sscan_se; // To ifu of sparc_ifu.v
input ctu_sscan_snap; // To ifu of sparc_ifu.v
input [3:0] ctu_sscan_tid; // To ifu of sparc_ifu.v
// bist
input ctu_tst_mbist_enable; // To test_stub of test_stub_bist.v
// efuse
input efc_spc_fuse_clk1;
input efc_spc_fuse_clk2;
input efc_spc_ifuse_ashift;
input efc_spc_ifuse_dshift;
input efc_spc_ifuse_data;
input efc_spc_dfuse_ashift;
input efc_spc_dfuse_dshift;
input efc_spc_dfuse_data;
// scan and macro test
input ctu_tst_macrotest; // To test_stub of test_stub_bist.v
input ctu_tst_scan_disable; // To test_stub of test_stub_bist.v
input ctu_tst_short_chain; // To test_stub of test_stub_bist.v
input global_shift_enable; // To test_stub of test_stub_two_bist.v
input ctu_tst_scanmode; // To test_stub of test_stub_two_bist.v
input spc_scanin0;
input spc_scanin1;
// clk
input cluster_cken; // To spc_hdr of cluster_header.v
input gclk; // To spc_hdr of cluster_header.v
// reset
input cmp_grst_l;
input cmp_arst_l;
input ctu_tst_pre_grst_l; // To test_stub of test_stub_bist.v
input adbginit_l; // To spc_hdr of cluster_header.v
input gdbginit_l; // To spc_hdr of cluster_header.v
// ----------------- End of IOs -------------------------- //
endmodule // sparc
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A41O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__A41O_FUNCTIONAL_PP_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a41o (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2, A3, A4 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A41O_FUNCTIONAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A211O_FUNCTIONAL_V
`define SKY130_FD_SC_HS__A211O_FUNCTIONAL_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a211o (
VPWR,
VGND,
X ,
A1 ,
A2 ,
B1 ,
C1
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
// Local signals
wire C1 and0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , and0_out, C1, B1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A211O_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); int n, k, num = 0; cin >> n >> k; vector<pair<int, int> > a(n); for (int i = 0; i < n; i++) { cin >> a[i].first >> a[i].second; a[i].first = -a[i].first; } (sort(a.begin(), a.end())); int fi = a[k - 1].first, sec = a[k - 1].second; for (int i = 0; i < n; i++) { if (fi == a[i].first && sec == a[i].second) { num++; } } cout << num; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__LSBUF_BLACKBOX_V
`define SKY130_FD_SC_LP__LSBUF_BLACKBOX_V
/**
* lsbuf: ????.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__lsbuf (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 DESTPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 DESTVPB;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__LSBUF_BLACKBOX_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2013 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [19:0] in = crc[19:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [19:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[19:0]),
// Inputs
.in (in[19:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {44'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hdb7bc61592f31b99
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
typedef struct packed {
logic [7:0] cn;
logic vbfval;
logic vabval;
} rel_t;
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input [19:0] in;
output [19:0] out;
rel_t [1:0] i; // From ifb0 of ifb.v, ...
rel_t [1:0] o; // From ifb0 of ifb.v, ...
assign i = in;
assign out = o;
sub sub
(
.i (i[1:0]),
.o (o[1:0]));
endmodule
module sub (/*AUTOARG*/
// Outputs
o,
// Inputs
i
);
input rel_t [1:0] i;
output rel_t [1:0] o;
assign o = i;
endmodule
// Local Variables:
// verilog-typedef-regexp: "_t$"
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRDLRTP_BLACKBOX_V
`define SKY130_FD_SC_LP__SRDLRTP_BLACKBOX_V
/**
* srdlrtp: ????.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__srdlrtp (
Q ,
RESET_B,
D ,
GATE ,
SLEEP_B
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input SLEEP_B;
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRDLRTP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e9; int c2i(char c) { if (c <= 9 ) return c - 0 ; return c - A + 10; } long long conv(string num, int base) { long long res = 0; for (int i = 0; i < (int)num.length(); i++) { if (c2i(num[i]) >= base) return INF; res = res * base + c2i(num[i]); } return res; } int main() { string inp, h, m; cin >> inp; for (int i = 0; i < (int)inp.length(); i++) if (inp[i] == : ) inp[i] = ; istringstream sin(inp); sin >> h >> m; vector<int> res; for (int base = 2; base <= 100; base++) if (conv(h, base) < 24 && conv(m, base) < 60) res.push_back(base); if (res.empty()) cout << 0 << endl; else if (res.back() == 100) cout << -1 << endl; else { for (int i = 0; i < (int)res.size(); i++) cout << res[i] << ; cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long mod = 1e9 + 7; void self_add(long long &x, long long y) { x = (x + y) % mod; } long long binpow(long long a, long long n) { long long res = 1; while (n) { if (n & 1) res = (res * a) % mod; n >>= 1; a = (a * a) % mod; } return res; } int main() { long long n; cin >> n; long long fact = 1; for (long long i = 2; i <= n; i++) { fact = (fact * (i)) % mod; } long long power = binpow(2, n - 1); long long ans = (fact - power) % mod; if (ans < 0) ans += mod; cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long tc, n, m, a, b, k; string str; char c; set<long long> s; map<long long, long long> mp; int main() { int k2, k3, k5, k6, ans = 0; cin >> k2 >> k3 >> k5 >> k6; int x = min(k2, k5); x = min(x, k6); ans += 256 * x; k2 -= x; x = min(k2, k3); ans += 32 * x; cout << ans << n ; }
|
#include <bits/stdc++.h> using namespace std; long long n, a[200005], sum, cnt, ans; int main() { cin >> n; for (int i = 1; i <= n; i++) { scanf( %lld , &a[i]); sum += a[i]; } for (int i = 1; i <= n; i += 2) cnt += a[i]; ans = cnt; for (int i = 1; i < n; i++) { cnt = sum - cnt + a[i]; ans = max(ans, cnt); } printf( %lld n , ans); }
|
//
// Generated by Bluespec Compiler (build 0fccbb13)
//
//
// Ports:
// Name I/O size props
// RDY_mem_server_request_put O 1 reg
// mem_server_response_get O 256 reg
// RDY_mem_server_response_get O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// mem_server_request_put I 353
// EN_mem_server_request_put I 1
// EN_mem_server_response_get I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkMem_Model(CLK,
RST_N,
mem_server_request_put,
EN_mem_server_request_put,
RDY_mem_server_request_put,
EN_mem_server_response_get,
mem_server_response_get,
RDY_mem_server_response_get);
input CLK;
input RST_N;
// action method mem_server_request_put
input [352 : 0] mem_server_request_put;
input EN_mem_server_request_put;
output RDY_mem_server_request_put;
// actionvalue method mem_server_response_get
input EN_mem_server_response_get;
output [255 : 0] mem_server_response_get;
output RDY_mem_server_response_get;
// signals for module outputs
wire [255 : 0] mem_server_response_get;
wire RDY_mem_server_request_put, RDY_mem_server_response_get;
// ports of submodule f_raw_mem_rsps
wire [255 : 0] f_raw_mem_rsps$D_IN, f_raw_mem_rsps$D_OUT;
wire f_raw_mem_rsps$CLR,
f_raw_mem_rsps$DEQ,
f_raw_mem_rsps$EMPTY_N,
f_raw_mem_rsps$ENQ,
f_raw_mem_rsps$FULL_N;
// ports of submodule rf
wire [255 : 0] rf$D_IN, rf$D_OUT_1;
wire [63 : 0] rf$ADDR_1,
rf$ADDR_2,
rf$ADDR_3,
rf$ADDR_4,
rf$ADDR_5,
rf$ADDR_IN;
wire rf$WE;
// rule scheduling signals
wire CAN_FIRE_mem_server_request_put,
CAN_FIRE_mem_server_response_get,
WILL_FIRE_mem_server_request_put,
WILL_FIRE_mem_server_response_get;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h362;
reg [31 : 0] v__h356;
// synopsys translate_on
// remaining internal signals
wire mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2;
// action method mem_server_request_put
assign RDY_mem_server_request_put = f_raw_mem_rsps$FULL_N ;
assign CAN_FIRE_mem_server_request_put = f_raw_mem_rsps$FULL_N ;
assign WILL_FIRE_mem_server_request_put = EN_mem_server_request_put ;
// actionvalue method mem_server_response_get
assign mem_server_response_get = f_raw_mem_rsps$D_OUT ;
assign RDY_mem_server_response_get = f_raw_mem_rsps$EMPTY_N ;
assign CAN_FIRE_mem_server_response_get = f_raw_mem_rsps$EMPTY_N ;
assign WILL_FIRE_mem_server_response_get = EN_mem_server_response_get ;
// submodule f_raw_mem_rsps
FIFO2 #(.width(32'd256), .guarded(1'd1)) f_raw_mem_rsps(.RST(RST_N),
.CLK(CLK),
.D_IN(f_raw_mem_rsps$D_IN),
.ENQ(f_raw_mem_rsps$ENQ),
.DEQ(f_raw_mem_rsps$DEQ),
.CLR(f_raw_mem_rsps$CLR),
.D_OUT(f_raw_mem_rsps$D_OUT),
.FULL_N(f_raw_mem_rsps$FULL_N),
.EMPTY_N(f_raw_mem_rsps$EMPTY_N));
// submodule rf
RegFileLoad #(.file("Mem.hex"),
.addr_width(32'd64),
.data_width(32'd256),
.lo(64'd0),
.hi(64'd8388607),
.binary(1'd0)) rf(.CLK(CLK),
.ADDR_1(rf$ADDR_1),
.ADDR_2(rf$ADDR_2),
.ADDR_3(rf$ADDR_3),
.ADDR_4(rf$ADDR_4),
.ADDR_5(rf$ADDR_5),
.ADDR_IN(rf$ADDR_IN),
.D_IN(rf$D_IN),
.WE(rf$WE),
.D_OUT_1(rf$D_OUT_1),
.D_OUT_2(),
.D_OUT_3(),
.D_OUT_4(),
.D_OUT_5());
// submodule f_raw_mem_rsps
assign f_raw_mem_rsps$D_IN = rf$D_OUT_1 ;
assign f_raw_mem_rsps$ENQ =
EN_mem_server_request_put &&
mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2 &&
!mem_server_request_put[352] ;
assign f_raw_mem_rsps$DEQ = EN_mem_server_response_get ;
assign f_raw_mem_rsps$CLR = 1'b0 ;
// submodule rf
assign rf$ADDR_1 = mem_server_request_put[319:256] ;
assign rf$ADDR_2 = 64'h0 ;
assign rf$ADDR_3 = 64'h0 ;
assign rf$ADDR_4 = 64'h0 ;
assign rf$ADDR_5 = 64'h0 ;
assign rf$ADDR_IN = mem_server_request_put[319:256] ;
assign rf$D_IN = mem_server_request_put[255:0] ;
assign rf$WE =
EN_mem_server_request_put &&
mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2 &&
mem_server_request_put[352] ;
// remaining internal signals
assign mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2 =
mem_server_request_put[319:256] < 64'h0000000000800000 ;
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (EN_mem_server_request_put &&
!mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2)
begin
v__h362 = $stime;
#0;
end
v__h356 = v__h362 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (EN_mem_server_request_put &&
!mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2)
$display("%0d: ERROR: Mem_Model.request.put: addr 0x%0h >= size 0x%0h (num raw-mem words)",
v__h356,
mem_server_request_put[319:256],
64'h0000000000800000);
if (RST_N != `BSV_RESET_VALUE)
if (EN_mem_server_request_put &&
!mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2)
$finish(32'd1);
end
// synopsys translate_on
endmodule // mkMem_Model
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR3_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__OR3_BEHAVIORAL_V
/**
* or3: 3-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__or3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A, C );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR3_BEHAVIORAL_V
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: dbg_uart_tasks.v
//
// *Module Description:
// openMSP430 debug interface UART tasks
//
// *Author(s):
// - Olivier Girard,
//
//----------------------------------------------------------------------------
// $Rev: 17 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $
//----------------------------------------------------------------------------
// Register B/W and addresses
parameter CPU_ID_LO = (8'h00 | 8'h00);
parameter CPU_ID_HI = (8'h00 | 8'h01);
parameter CPU_CTL = (8'h40 | 8'h02);
parameter CPU_STAT = (8'h40 | 8'h03);
parameter MEM_CTL = (8'h40 | 8'h04);
parameter MEM_ADDR = (8'h00 | 8'h05);
parameter MEM_DATA = (8'h00 | 8'h06);
parameter MEM_CNT = (8'h00 | 8'h07);
parameter BRK0_CTL = (8'h40 | 8'h08);
parameter BRK0_STAT = (8'h40 | 8'h09);
parameter BRK0_ADDR0 = (8'h00 | 8'h0A);
parameter BRK0_ADDR1 = (8'h00 | 8'h0B);
parameter BRK1_CTL = (8'h40 | 8'h0C);
parameter BRK1_STAT = (8'h40 | 8'h0D);
parameter BRK1_ADDR0 = (8'h00 | 8'h0E);
parameter BRK1_ADDR1 = (8'h00 | 8'h0F);
parameter BRK2_CTL = (8'h40 | 8'h10);
parameter BRK2_STAT = (8'h40 | 8'h11);
parameter BRK2_ADDR0 = (8'h00 | 8'h12);
parameter BRK2_ADDR1 = (8'h00 | 8'h13);
parameter BRK3_CTL = (8'h40 | 8'h14);
parameter BRK3_STAT = (8'h40 | 8'h15);
parameter BRK3_ADDR0 = (8'h00 | 8'h16);
parameter BRK3_ADDR1 = (8'h00 | 8'h17);
// Read / Write commands
parameter DBG_WR = 8'h80;
parameter DBG_RD = 8'h00;
// Synchronization value
parameter DBG_SYNC = 8'h80;
//----------------------------------------------------------------------------
// UART COMMUNICATION DATA RATE CONFIGURATION
//----------------------------------------------------------------------------
// If the auto synchronization mode is set, then the communication speed
// is configured by the testbench.
// If not, the values from the openMSP430.inc file are taken over.
`ifdef DBG_UART_AUTO_SYNC
parameter UART_BAUD = ;
integer UART_PERIOD = /UART_BAUD;
`else
integer UART_PERIOD = `DBG_UART_CNT;
`endif
//----------------------------------------------------------------------------
// Receive UART frame from CPU Debug interface (8N1)
//----------------------------------------------------------------------------
task dbg_uart_rx;
output [7:0] dbg_rxbuf;
reg [7:0] dbg_rxbuf;
reg [7:0] rxbuf;
integer rxcnt;
begin
#(1);
dbg_uart_rx_busy = 1'b1;
@(negedge dbg_uart_txd);
dbg_rxbuf = 0;
rxbuf = 0;
#(3*UART_PERIOD/2);
for (rxcnt = 0; rxcnt < 8; rxcnt = rxcnt + 1)
begin
rxbuf = {dbg_uart_txd, rxbuf[7:1]};
#(UART_PERIOD);
end
dbg_rxbuf = rxbuf;
dbg_uart_rx_busy = 1'b0;
end
endtask
task dbg_uart_rx16;
reg [7:0] rxbuf_lo;
reg [7:0] rxbuf_hi;
begin
rxbuf_lo = 8'h00;
rxbuf_hi = 8'h00;
dbg_uart_rx(rxbuf_lo);
dbg_uart_rx(rxbuf_hi);
dbg_uart_buf = {rxbuf_hi, rxbuf_lo};
end
endtask
task dbg_uart_rx8;
reg [7:0] rxbuf;
begin
rxbuf = 8'h00;
dbg_uart_rx(rxbuf);
dbg_uart_buf = {8'h00, rxbuf};
end
endtask
//----------------------------------------------------------------------------
// Transmit UART frame to CPU Debug interface (8N1)
//----------------------------------------------------------------------------
task dbg_uart_tx;
input [7:0] txbuf;
reg [9:0] txbuf_full;
integer txcnt;
begin
#(1);
dbg_uart_tx_busy = 1'b1;
dbg_uart_rxd_pre = 1'b1;
txbuf_full = {1'b1, txbuf, 1'b0};
for (txcnt = 0; txcnt < 10; txcnt = txcnt + 1)
begin
#(UART_PERIOD);
dbg_uart_rxd_pre = txbuf_full[txcnt];
end
dbg_uart_tx_busy = 1'b0;
end
endtask
task dbg_uart_tx16;
input [15:0] txbuf;
begin
dbg_uart_tx(txbuf[7:0]);
dbg_uart_tx(txbuf[15:8]);
end
endtask
always @(posedge mclk or posedge dbg_rst)
if (dbg_rst)
begin
dbg_uart_rxd_sel <= 1'b0;
dbg_uart_rxd_dly <= 1'b1;
end
else if (dbg_en)
begin
dbg_uart_rxd_sel <= dbg_uart_rxd_meta ? $random : 1'b0;
dbg_uart_rxd_dly <= dbg_uart_rxd_pre;
end
assign dbg_uart_rxd = dbg_uart_rxd_sel ? dbg_uart_rxd_dly : dbg_uart_rxd_pre;
//----------------------------------------------------------------------------
// Write to Debug register
//----------------------------------------------------------------------------
task dbg_uart_wr;
input [7:0] dbg_reg;
input [15:0] dbg_data;
begin
dbg_uart_tx(DBG_WR | dbg_reg);
dbg_uart_tx(dbg_data[7:0]);
if (~dbg_reg[6])
dbg_uart_tx(dbg_data[15:8]);
end
endtask
//----------------------------------------------------------------------------
// Read Debug register
//----------------------------------------------------------------------------
task dbg_uart_rd;
input [7:0] dbg_reg;
reg [7:0] rxbuf_lo;
reg [7:0] rxbuf_hi;
begin
rxbuf_lo = 8'h00;
rxbuf_hi = 8'h00;
dbg_uart_tx(DBG_RD | dbg_reg);
dbg_uart_rx(rxbuf_lo);
if (~dbg_reg[6])
dbg_uart_rx(rxbuf_hi);
dbg_uart_buf = {rxbuf_hi, rxbuf_lo};
end
endtask
//----------------------------------------------------------------------------
// Send synchronization frame
//----------------------------------------------------------------------------
task dbg_uart_sync;
begin
dbg_uart_tx(DBG_SYNC);
repeat(10) @(posedge mclk);
end
endtask
|
#include <bits/stdc++.h> using namespace std; map<long long, long long> mp; void Hash(string str, long long B, long long mod) { long long power = 1, h = 0; long long m = (int)str.length(); for (long long i = m - 1; i >= 0; i--) { h = h + (power * (str[i] - a + 1)) % mod; h = h % mod; power = (power * B) % mod; } mp[h]++; } bool match(string str, long long B, long long mod) { long long power = 1, h = 0; long long m = (int)str.length(); for (long long i = m - 1; i >= 0; i--) { h = h + (power * (str[i] - a + 1)) % mod; h = h % mod; power = (power * B) % mod; } power = 1; for (long long i = m - 1; i >= 0; i--) { long long t1, t2; if (str[i] == a ) { t1 = h + power; t1 = t1 % mod; t2 = t1 + power; t2 = t2 % mod; } else if (str[i] == b ) { t1 = h - power; t1 = (t1 + mod) % mod; t2 = h + power; t2 = (t2 + mod) % mod; } else { t1 = h - power; t1 = (t1 + mod) % mod; t2 = t1 - power; t2 = (t2 + mod) % mod; } power = (power * B) % mod; if (mp[t1] != 0) return true; if (mp[t2] != 0) return true; } return false; } int main() { long long B[10], mod[10]; B[0] = 137, B[1] = 347; mod[0] = 100404001, mod[1] = 1000000007; int n, m; scanf( %d %d , &n, &m); string str[n], query[m]; for (int i = 0; i < n; i++) cin >> str[i]; for (int i = 0; i < m; i++) cin >> query[i]; bool ans[m]; memset(ans, true, sizeof ans); for (int i = 0; i < 2; i++) { mp.clear(); for (int j = 0; j < n; j++) { Hash(str[j], B[i], mod[i]); } for (int j = 0; j < m; j++) { if (match(query[j], B[i], mod[i]) == false) ans[j] = false; } } for (int j = 0; j < m; j++) { if (ans[j]) printf( YES n ); else printf( NO n ); } }
|
`ifdef __ICARUS__
`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
`endif
module top;
parameter pval = -2;
reg pass = 1'b1;
reg [14:-1] big = 16'h0123;
reg [15:0] big_0 = 16'h0123;
reg signed [15:0] idxs [0:1];
reg signed [15:0] a;
reg [4*8:1] res;
initial begin
/* If this fails it is likely because the index width is less
* than an integer width. */
a = -2;
$sformat(res, "%b", big[a+:4]);
if (res !== "011x") begin
$display("Failed: &PV<> check 1, expected 4'b011x, got %s.", res);
pass = 1'b0;
end
a = 0;
idxs[0] = -1;
$sformat(res, "%b", big_0[idxs[a]+:4]);
if (res !== "011x") begin
$display("Failed: &PV<> check 2, expected 4'b011x, got %s.", res);
pass = 1'b0;
end
/* This should work since it is a constant value. */
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
$sformat(res, "%b", big[pval+:4]);
`else
$sformat(res, "%bx", big[(pval+1)+:3]);
`endif
if (res !== "011x") begin
$display("Failed: &PV<> check 3, expected 4'b011x, got %s.", res);
pass = 1'b0;
end
/* This should always work since it uses the index directly. */
a = -1;
$sformat(res, "%b", big_0[a+:4]);
if (res !== "011x") begin
$display("Failed: &PV<> check 4, expected 4'b011x, got %s.", res);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O221A_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__O221A_FUNCTIONAL_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__o221a (
X ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
and and0 (and0_out_X, or0_out, or1_out, C1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O221A_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S50_BLACKBOX_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S50_BLACKBOX_V
/**
* clkdlybuf4s50: Clock Delay Buffer 4-stage 0.59um length inner stage
* gates.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__clkdlybuf4s50 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S50_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int N, K; char s[1100000]; int cnt[1100000][3], tot[1100000]; int pb[1100000], pw[1100000]; bool can(int p, int f) { if (p < K) return false; if (f) { if (p - pb[p - 1] - 1 < K) return false; if (p > K && s[p - K - 1] == W ) return false; return true; } else { if (p - pw[p - 1] - 1 < K) return false; if (p > K && s[p - K - 1] == B ) return false; return true; } } int main() { int b, w, i; scanf( %d%d , &N, &K); scanf( %s , s); if (N < K * 2) { puts( 0 ); return 0; } b = w = -1; for (i = 0; i < N; i++) { if (s[i] == B ) b = i; if (s[i] == W ) w = i; pb[i] = b; pw[i] = w; } cnt[0][0] = 1; tot[0] = 1; for (i = 1; i <= N; i++) { if (s[i - 1] == X ) tot[i] = tot[i - 1] * 2 % 1000000007; else tot[i] = tot[i - 1]; if (s[i - 1] == X ) cnt[i][2] = cnt[i - 1][2] * 2 % 1000000007; else cnt[i][2] = cnt[i - 1][2]; if (can(i, 1)) { cnt[i][2] += cnt[max(i - K - 1, 0)][1]; cnt[i][2] %= 1000000007; if (can(i - K, 0)) { cnt[i][2] += cnt[max(i - K * 2 - 1, 0)][0]; cnt[i][2] %= 1000000007; } } if (s[i - 1] == X ) cnt[i][0] = cnt[i - 1][0] * 2 % 1000000007; else cnt[i][0] = cnt[i - 1][0]; if (can(i, 0)) { cnt[i][0] -= cnt[max(i - K - 1, 0)][0]; if (cnt[i][0] < 0) cnt[i][0] += 1000000007; } cnt[i][1] = tot[i]; cnt[i][1] -= cnt[i][0]; if (cnt[i][1] < 0) cnt[i][1] += 1000000007; cnt[i][1] -= cnt[i][2]; if (cnt[i][1] < 0) cnt[i][1] += 1000000007; } printf( %d n , cnt[N][2]); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 100, M = 10000; int n, m, a[N + 9], ca; double x, ans; void into() { scanf( %d%lf , &n, &x); int p = 0; for (int i = 1; i <= n; ++i) { int t; scanf( %d , &t); t << 1 <= x ? ans += t : m += a[++ca] = t; } x /= 2; } double dp[N + 9][M + 9]; void Get_dp() { dp[0][0] = 1; for (int i = 1; i <= ca; ++i) for (int j = i; j >= 1; --j) for (int k = m; k >= a[i]; --k) dp[j][k] += dp[j - 1][k - a[i]] * j / (ca - j + 1); } void Get_ans() { for (int i = 1; i <= ca; ++i) for (int j = 0; j <= m; ++j) ans += dp[i][j] * min((1.0 * n / i + 1) * x, 1.0 * j / i); } void work() { Get_dp(); Get_ans(); } void outo() { printf( %.12lf n , ans); } int main() { into(); work(); outo(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-8; const int inf = 0x3f3f3f3f; const int maxn = 2000 + 10; long long MOD = 1e9 + 7; long long fac[200010]; void getFac() { fac[0] = 1; for (int i = 1; i < 200010; i++) { fac[i] = fac[i - 1] * i % MOD; } } long long powerMod(long long x, long long n) { long long ans = 1; x %= MOD; while (n > 0) { if (n & 1) { ans = (ans * x) % MOD; } x = (x * x) % MOD; n >>= 1; } return ans; } long long C(long long n, long long m) { if (m > n) { return 0; } else { return fac[n] * powerMod(fac[m] * fac[n - m], MOD - 2) % MOD; } } long long Lucas(long long n, long long m) { if (m == 0) { return 1; } else { return C(n % MOD, m % MOD) * Lucas(n / MOD, m / MOD) % MOD; } } struct Point { int r, c; Point(int a = 0, int b = 0) { r = a; c = b; } }; bool operator<(const Point& a, const Point& b) { return a.r < b.r || (a.r == b.r && a.c < b.c); } int h, w, n; Point point[maxn]; vector<int> G[maxn]; long long dp[maxn]; long long dfs(int u) { if (dp[u] >= 0) { return dp[u]; } long long ret = Lucas(h - point[u].r + w - point[u].c, h - point[u].r); int glen = G[u].size(); for (int i = 0; i < glen; i++) { int v = G[u][i]; ret = (ret - Lucas(point[v].r - point[u].r + point[v].c - point[u].c, point[v].r - point[u].r) * dfs(v)) % MOD; } return dp[u] = (ret + MOD) % MOD; } int main() { getFac(); scanf( %d%d%d , &h, &w, &n); for (int i = 0; i < n; i++) { scanf( %d%d , &point[i].r, &point[i].c); } point[n++] = Point(1, 1); point[n++] = Point(h, w); sort(point, point + n); for (int i = 0; i < n - 1; i++) { for (int j = i + 1; j < n; j++) { { G[i].push_back(j); } } } for (int i = 0; i < n; i++) { dp[i] = -1; } dp[n - 1] = 0; long long ans = dfs(0); printf( %I64d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long maxn = 1e6 + 5; const int INF = 0x7fffffff; bool p(long long a) { for (long long i = 2; i <= sqrt(a); i++) { if (a % i == 0) return 0; } return 1; } int main() { int n; cin >> n; int c = n; while (!p(c)) { c++; } cout << c << n ; for (int i = 1; i < n; i++) cout << i << << i + 1 << n ; cout << 1 << << n << n ; for (int i = 1; i <= c - n; i++) cout << i << << n - i << n ; }
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 , unroll-loops ) using namespace std; template <typename T1, typename T2> inline void checkmin(T1 &x, T2 y) { if (x > y) x = y; } template <typename T1, typename T2> inline void checkmax(T1 &x, T2 y) { if (x < y) x = y; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n, k; cin >> n >> k; vector<string> arr(n); vector<vector<long long>> cnt(n, vector<long long>(n)); for (auto &i : arr) cin >> i; for (int i = 0; i <= n - k; ++i) for (int j = 0; j < n; ++j) { bool flag = true; for (int p = i; p < i + k; ++p) flag = flag && (arr[p][j] == . ); if (flag) for (int p = i; p < i + k; ++p) ++cnt[p][j]; } if (k > 1) { for (int j = 0; j <= n - k; ++j) for (int i = 0; i < n; ++i) { bool flag = true; for (int p = j; p < j + k; ++p) flag = flag && (arr[i][p] == . ); if (flag) for (int p = j; p < j + k; ++p) ++cnt[i][p]; } } long long x = 0, y = 0; for (int i = 0; i < n; ++i) for (int j = 0; j < n; ++j) { if (cnt[i][j] > cnt[x][y]) { x = i; y = j; } } cout << x + 1 << << y + 1; return 0; }
|
#include <bits/stdc++.h> using namespace std; int t; int n; long long a[200010]; int ans_check[200010]; int main() { int i, j, k; scanf( %d , &t); while (t--) { int check = 0; int cnt = 1; memset(ans_check, 0, sizeof(ans_check)); scanf( %d , &n); for (i = 1; i <= n; i++) { scanf( %64d , &a[i]); } sort(a + 1, a + n + 1); long long ans_uncheck = a[1] * a[n]; for (i = 1; i <= n; i++) if (a[i] * a[n - i + 1] != ans_uncheck || a[i] == ans_uncheck || a[n - i + 1] == ans_uncheck) { printf( -1 n ); check = 1; break; } if (check == 1) continue; long long che = 2; int ch = 0; long long tmpp = ans_uncheck; while (ans_uncheck > 1) { if (ans_uncheck % che == 0) { if (ch == 1) cnt++; ans_uncheck /= che; ch = 0; ans_check[cnt]++; } else { che++; ch = 1; } } long long check2 = 1; for (i = 1; i <= cnt; i++) check2 *= (ans_check[i] + 1); if (cnt == 1) { if (n != ans_check[1] - 1) { printf( -1 n ); check = 1; } } else if (check2 != n + 2) { printf( -1 n ); check = 1; } if (check == 1) continue; cout << tmpp << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxN = 100100; const int maxM = maxN << 1; const int maxB = 17; int n, Q, Log[maxN]; int edgecnt = -1, Head[maxN], Next[maxM], V[maxM], W[maxM], Dst[maxN]; class Tree { public: int root, Dep[maxN], Fa[maxN], Dst[maxN], Mx[maxN], ST[maxB][maxN], Mxd[maxB][maxN], dfncnt, dfn[maxN], lst[maxN]; int lcnt, Mark[maxN]; pair<int, int> Leaf[maxN]; void dfs_init(int u, int fa) { Dep[u] = 0; ST[0][u] = fa; for (int i = Head[u]; i != -1; i = Next[i]) if (V[i] != fa) { dfs_init(V[i], u); if (Dep[V[i]] + W[i] > Dep[u]) Mx[u] = V[i], Dep[u] = Dep[V[i]] + W[i]; } return; } void dfs_push(int u, int fa, int w) { Dep[u] = Dep[fa] + 1; dfn[u] = ++dfncnt; Mxd[0][dfncnt] = Dst[u]; if (Mx[u] == 0) Leaf[++lcnt] = make_pair(w, u); else { Fa[Mx[u]] = u; for (int i = Head[u]; i != -1; i = Next[i]) if (V[i] != fa) Dst[V[i]] = Dst[u] + W[i], dfs_push(V[i], u, (V[i] == Mx[u]) ? w + W[i] : W[i]); } lst[u] = dfncnt; return; } void Init(int r) { root = r; dfs_init(root, 0); Dep[root] = 1; Dst[root] = 0; dfs_push(root, 0, 0); for (int i = 1; i < maxB; i++) for (int j = 1; j <= n; j++) ST[i][j] = ST[i - 1][ST[i - 1][j]]; sort(&Leaf[1], &Leaf[lcnt + 1]); reverse(&Leaf[1], &Leaf[lcnt + 1]); for (int i = 1; i <= lcnt; i++) Leaf[i].first += Leaf[i - 1].first; for (int i = 1; i <= lcnt; i++) { int now = Leaf[i].second; while (now) Mark[now] = i, now = Fa[now]; } for (int i = 1; i < maxB; i++) for (int j = 1; j + (1 << (i)) - 1 <= n; j++) Mxd[i][j] = max(Mxd[i - 1][j], Mxd[i - 1][j + (1 << (i - 1))]); return; } int LCA(int u, int v) { if (Dep[u] < Dep[v]) swap(u, v); for (int i = maxB - 1; i >= 0; i--) if (ST[i][u] && Dep[ST[i][u]] >= Dep[v]) u = ST[i][u]; if (u == v) return u; for (int i = maxB - 1; i >= 0; i--) if (ST[i][u] && ST[i][v] && ST[i][u] != ST[i][v]) u = ST[i][u], v = ST[i][v]; return ST[0][u]; } int GET(int u, int cnt) { cnt = min(cnt * 2 - 1, lcnt); if (Mark[u] <= cnt) return Leaf[cnt].first; int ret = Leaf[cnt - 1].first; int now = u; for (int i = maxB - 1; i >= 0; i--) if (ST[i][now] && Mark[ST[i][now]] > cnt) now = ST[i][now]; now = ST[0][now]; int l = dfn[u], r = lst[u], lg = Log[r - l + 1]; int mxd = max(Mxd[lg][l], Mxd[lg][r - (1 << (lg)) + 1]); ret = ret + mxd - Dst[now]; return max(ret, Leaf[cnt].first + mxd - Dst[Leaf[Mark[now]].second]); } }; Tree T1, T2; void Add_Edge(int u, int v, int w); void Bfs(int S); int main() { for (int i = 2; i < maxN; i++) Log[i] = Log[i >> 1] + 1; scanf( %d%d , &n, &Q); memset(Head, -1, sizeof(Head)); for (int i = 1; i < n; i++) { int u, v, w; scanf( %d%d%d , &u, &v, &w); Add_Edge(u, v, w); Add_Edge(v, u, w); } int S, T; Bfs(1); S = 1; for (int i = 1; i <= n; i++) if (Dst[S] < Dst[i]) S = i; Bfs(S); T = 1; for (int i = 1; i <= n; i++) if (Dst[T] < Dst[i]) T = i; T1.Init(S); T2.Init(T); int lstans = 0; while (Q--) { int x, y; scanf( %d%d , &x, &y); x = (x + lstans - 1) % n + 1; y = (y + lstans - 1) % n + 1; printf( %d n , lstans = max(T1.GET(x, y), T2.GET(x, y))); } return 0; } void Add_Edge(int u, int v, int w) { Next[++edgecnt] = Head[u]; Head[u] = edgecnt; V[edgecnt] = v; W[edgecnt] = w; return; } void Bfs(int S) { static int vis[maxN], Qu[maxN]; memset(vis, 0, sizeof(vis)); int l = 1, r = 1; Qu[1] = S; Dst[S] = 0; vis[S] = 1; while (l <= r) for (int u = Qu[l++], i = Head[u]; i != -1; i = Next[i]) if (vis[V[i]] == 0) Dst[Qu[++r] = V[i]] = Dst[u] + W[i], vis[V[i]] = 1; return; }
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const long long INF = 1e9 + 9; const long long N = 500500; signed main(void) { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cout.precision(10); cout << fixed; long long v; cin >> v; if (v == 2) { cout << 2; return 0; } cout << 1; return 0; }
|
#include <bits/stdc++.h> using namespace std; struct pp { int val; int same; }; vector<pp> with[100005]; vector<int> v[100005]; int color[100005]; int currcolor[100005]; bool ending = false; void dfs(int parent, int curr) { if (ending == true) return; for (int i = 1; i <= with[curr][0].val; i++) { if (ending == true) return; if (with[curr][i].val == parent) continue; int vertex = with[curr][i].val; if ((currcolor[vertex] != -1) && ((currcolor[vertex] + currcolor[curr] + with[curr][i].same) % 2 == 0)) { cout << NO n ; ending = true; return; } if (currcolor[vertex] != -1) continue; if (with[curr][i].same == 1) currcolor[vertex] = currcolor[curr]; else currcolor[vertex] = 1 - currcolor[curr]; dfs(curr, vertex); } } int main() { int n, m; cin >> n >> m; pp nullpp; nullpp.val = 0, nullpp.same = 0; for (int i = 1; i <= m; i++) with[i].push_back(nullpp); for (int i = 1; i <= n; i++) cin >> color[i]; for (int i = 1; i <= m; i++) { int k, val; cin >> k; for (int j = 1; j <= k; j++) { cin >> val; v[val].push_back(i); } } for (int i = 1; i <= n; i++) { with[v[i][0]][0].val++; pp ed; ed.val = v[i][1]; ed.same = color[i]; with[v[i][0]].push_back(ed); with[v[i][1]][0].val++; ed.val = v[i][0]; with[v[i][1]].push_back(ed); } for (int i = 1; i <= m; i++) currcolor[i] = -1; for (int i = 1; i <= m; i++) if (currcolor[i] == -1) { currcolor[i] = 1; dfs(-1, i); } if (ending == false) cout << YES n ; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21A_SYMBOL_V
`define SKY130_FD_SC_HDLL__O21A_SYMBOL_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o21a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21A_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFBBP_PP_SYMBOL_V
`define SKY130_FD_SC_LP__SDFBBP_PP_SYMBOL_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdfbbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
input SET_B ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFBBP_PP_SYMBOL_V
|
// DEFINES
`define BITS 32 // Bit width of the operands
module mm3(clock,
reset,
a1,
a2,
a3,
b1,
b2,
b3,
out
);
// SIGNAL DECLARATIONS
input clock;
input reset;
input [`BITS-1:0] a1;
input [`BITS-1:0] a2;
input [`BITS-1:0] a3;
input [`BITS-1:0] b1;
input [`BITS-1:0] b2;
input [`BITS-1:0] b3;
output [`BITS-1:0] out;
wire [`BITS-1:0] x1;
wire [`BITS-1:0] x2;
wire [`BITS-1:0] x3;
wire [`BITS-1:0] add4;
wire [`BITS-1:0] add5;
reg [`BITS-1:0] x3_reg1;
reg [`BITS-1:0] x3_reg2;
reg [`BITS-1:0] x3_reg3;
reg [`BITS-1:0] x3_reg4;
reg [`BITS-1:0] x3_reg5;
reg [`BITS-1:0] x3_reg6;
wire [`BITS-1:0] out;
// ASSIGN STATEMENTS
//assign x1 = a1 * b1;
wire [7:0] x1_control;
fpu_mul x1_mul
(
.clk(clock),
.opa(a1),
.opb(b1),
.out(x1),
.control(x1_control)
);
//assign x2 = a2 * b2;
wire [7:0] x2_control;
fpu_mul x2_mul
(
.clk(clock),
.opa(a2),
.opb(b2),
.out(x2),
.control(x2_control)
);
//assign x3 = a3 * b3;
wire [7:0] x3_control;
fpu_mul x3_mul
(
.clk(clock),
.opa(a3),
.opb(b3),
.out(x3),
.control(x3_control)
);
//assign add4 = x1 + x2;
wire [7:0] add4_control;
fpu_add add4_add
(
.clk(clock),
.opa(x1),
.opb(x2),
.out(add4),
.control(add4_control)
);
//assign out = add4 + x3_reg5;
wire [7:0] out_control;
fpu_add out_add
(
.clk(clock),
.opa(add4),
.opb(x3_reg6),
.out(out),
.control(out_control)
);
always @(posedge clock)
begin
x3_reg1 <= x3;
x3_reg2 <= x3_reg1;
x3_reg3 <= x3_reg2;
x3_reg4 <= x3_reg3;
x3_reg5 <= x3_reg4;
x3_reg6 <= x3_reg5;
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_min_rq_rhq_buf.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
/*
// Description: Request Header Queue Buffer
// Top level Module: jbi_min_rq_rhq_buf
// Where Instantiated: jbi_min_rq_rhq
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "jbi.h"
module jbi_min_rq_rhq_buf(/*AUTOARG*/
// Outputs
rhq_rdata,
// Inputs
clk, cpu_clk, hold, csr_16x65array_margin, testmux_sel, rhq_csn_wr,
rhq_csn_rd, rhq_waddr, rhq_raddr, wdq_rhq_wdata
);
input clk;
input cpu_clk;
input hold;
input [4:0] csr_16x65array_margin;
input testmux_sel;
input rhq_csn_wr;
input rhq_csn_rd;
input [`JBI_RHQ_ADDR_WIDTH-1:0] rhq_waddr;
input [`JBI_RHQ_ADDR_WIDTH-1:0] rhq_raddr;
input [`JBI_RHQ_WIDTH-1:0] wdq_rhq_wdata;
output [`JBI_RHQ_WIDTH-1:0] rhq_rdata;
////////////////////////////////////////////////////////////////////////
// Interface signal type declarations
////////////////////////////////////////////////////////////////////////
wire [`JBI_RHQ_WIDTH-1:0] rhq_rdata;
////////////////////////////////////////////////////////////////////////
// Local signal declarations
////////////////////////////////////////////////////////////////////////
wire dangle;
bw_rf_16x65 u_rhq_buf
(.rd_clk(cpu_clk), // read clock
.wr_clk(clk), // read clock
.csn_rd(rhq_csn_rd), // read enable -- active low
.csn_wr(rhq_csn_wr), // write enable -- active low
.hold(hold), // Bypass signal -- unflopped -- bypass input data when 0
.scan_en(1'b0), // Scan enable unflopped
.margin(csr_16x65array_margin), // Delay for the circuits--- set to 10101
.rd_a(rhq_raddr), // read address
.wr_a(rhq_waddr), // Write address
.di({1'b0, wdq_rhq_wdata}), // Data input
.testmux_sel(testmux_sel), // bypass signal -- unflopped -- testmux_sel = 1 bypasses di to do
.si(), // scan in -- NOT CONNECTED
.so(), // scan out -- TIED TO ZERO
.listen_out({dangle, rhq_rdata}), // Listening flop--
.do() // Data out
);
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../common/mem/rtl/")
// verilog-auto-sense-defines-constant:t
// End:
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } string toBin(long long a) { string res = ; while (a) { res += char((a & 1) + 0 ); a >>= 1; } reverse(res.begin(), res.end()); return res; } const int mod = 1e9 + 7; long long expo(long long base, long long pow) { long long ans = 1; while (pow != 0) { if (pow & 1 == 1) { ans = ans * base; ans = ans % mod; } base *= base; base %= mod; pow /= 2; } return ans; } long long inv(long long x) { return expo(x, mod - 2); } double pi = 3.141592653589793238462643; double error = 0.0000001; const int M = 100001; int main() { int k, a, b, v; cin >> k >> a >> b >> v; int tot = 0; int box = 0; while (true) { int sect = min(b + 1, k); b -= (sect - 1); tot += sect * v; box++; if (tot >= a) break; } cout << box; }
|
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1); long long n, a[103][2601] = {}, ans = 0, mod = 1000000007, tmp = 0; string second; char c; vector<pair<int, int> > vp; bool first, f1; bool cmpvp(pair<int, int> p1, pair<int, int> p2) { if (p1.first < p2.first) return 1; if (p1.first == p2.first) if (p1.second < p2.second) return 1; return 0; } int main() { for (int i = 0; i < 26; ++i) a[1][i] = 1; for (int i = 2; i <= 100; ++i) { for (int j = 0; j <= 2600; ++j) { for (int k = 0; k < 26; ++k) a[i][j + k] = (a[i][j + k] + a[i - 1][j]) % mod; } } cin >> n; for (int i = 0; i < n; ++i) { tmp = 0; cin >> second; for (int j = 0; second[j]; ++j) tmp += second[j] - a ; cout << a[second.size()][tmp] - 1 << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 4e5 + 100; vector<int> vec[maxn]; int n, m, k; int d[maxn], cnt; bool vis[maxn]; void dfs(int x) { vis[x] = 1; d[++cnt] = x; for (int i = 0; i < vec[x].size(); i++) { if (vis[vec[x][i]]) continue; dfs(vec[x][i]); d[++cnt] = x; } } int main() { scanf( %d%d%d , &n, &m, &k); for (int i = 1; i <= m; i++) { int u, v; scanf( %d%d , &u, &v); vec[u].push_back(v); vec[v].push_back(u); } dfs(1); int x = (2 * n + k - 1) / k; for (int i = 1; i <= k; i++) { int c = min(x, cnt); if (c == 0) { cout << 1 1 << endl; continue; } cout << c << ; for (int i = 1; i <= c && cnt != 0; i++, cnt--) { cout << d[cnt] << ; } cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> a; while (n) { int x = n, p = 1, m = 0; while (x) { if (x % 10) m += p; x /= 10; p *= 10; } n -= m; a.push_back(m); } cout << a.size() << endl; for (int &i : a) cout << i << ; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A22O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__A22O_BEHAVIORAL_PP_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a22o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X , and1_out, and0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A22O_BEHAVIORAL_PP_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:58:54 03/17/2011
// Design Name:
// Module Name: LED7SEG
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module LED7SEG(DIGIT, DISPLAY, value_A, value_B, value_result_tens, value_result_units, sign_result, sign_A, sign_B, clk);
input clk;
input [3:0] value_A;
input [3:0] value_B;
input [3:0] value_result_tens;
input [3:0] value_result_units;
input sign_result;
input sign_A;
input sign_B;
output reg [3:0] DIGIT;
output reg [8:0] DISPLAY;
reg [3:0] value;
reg sign;
always @ ( posedge clk ) begin
case(DIGIT)
4'b0111: begin
value = value_B;
sign = sign_B;
DIGIT <= 4'b1011;
end
4'b1011: begin
value = value_result_tens;
sign = 0;
DIGIT <= 4'b1101;
end
4'b1101: begin
value = value_result_units;
sign = sign_result;
DIGIT <= 4'b1110;
end
4'b1110: begin
value = value_A;
sign = sign_A;
DIGIT <= 4'b0111;
end
default begin
DIGIT <= 4'b0111;
end
endcase
end
always @(*)begin
case (value)
4'h0: DISPLAY = { ~sign , 8'b11000000 };
4'h1: DISPLAY = { ~sign , 8'b11111001 };
4'h2: DISPLAY = { ~sign , 8'b00100100 };
4'h3: DISPLAY = { ~sign , 8'b00110000 };
4'h4: DISPLAY = { ~sign , 8'b00011001 };
4'h5: DISPLAY = { ~sign , 8'b00010010 };
4'h6: DISPLAY = { ~sign , 8'b00000010 };
4'h7: DISPLAY = { ~sign , 8'b11111000 };
4'h8: DISPLAY = { ~sign , 8'b00000000 };
4'h9: DISPLAY = { ~sign , 8'b00010000 };
default:begin
DISPLAY = 9'b111111111;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_DLATCH_P_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_HDLL__UDP_DLATCH_P_PP_PG_N_BLACKBOX_V
/**
* udp_dlatch$P_pp$PG$N: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__udp_dlatch$P_pp$PG$N (
Q ,
D ,
GATE ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input GATE ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_DLATCH_P_PP_PG_N_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 5e5 + 5; const long long inf = 1e17; const int mod = 1e9 + 7; vector<int> edge[maxn]; bool mark[maxn]; int h[maxn]; vector<int> ant; void dfs(int v) { mark[v] = true; if (edge[v].size() == 1) ant.push_back(h[v]); for (int u : edge[v]) { if (mark[u]) continue; h[u] = h[v] + 1; dfs(u); } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; int n; cin >> n; for (int i = 0; i < n - 1; i++) { int v, u; cin >> v >> u; v--; u--; edge[u].push_back(v); edge[v].push_back(u); } mark[0] = true; int ans = 0; for (int u : edge[0]) { ant.clear(); dfs(u); int l = -1; sort(ant.begin(), ant.end()); for (int i : ant) { ans = max(ans, max(l + 1, i)); l = max(l + 1, i); } } cout << ans + 1 << endl; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// Color Space Conversion, adder. This is a simple adder, but had to be
// pipe-lined for faster clock rates. The delay input is delay-matched to
// the sum pipe-line stages
`timescale 1ps/1ps
module ad_csc_1_add #(
parameter DELAY_DATA_WIDTH = 16) (
// all signed
input clk,
input [24:0] data_1,
input [24:0] data_2,
input [24:0] data_3,
input [24:0] data_4,
output reg [ 7:0] data_p,
// delay match
input [DW:0] ddata_in,
output reg [DW:0] ddata_out);
localparam DW = DELAY_DATA_WIDTH - 1;
// internal registers
reg [DW:0] p1_ddata = 'd0;
reg [24:0] p1_data_1 = 'd0;
reg [24:0] p1_data_2 = 'd0;
reg [24:0] p1_data_3 = 'd0;
reg [24:0] p1_data_4 = 'd0;
reg [DW:0] p2_ddata = 'd0;
reg [24:0] p2_data_0 = 'd0;
reg [24:0] p2_data_1 = 'd0;
reg [DW:0] p3_ddata = 'd0;
reg [24:0] p3_data = 'd0;
// internal signals
wire [24:0] p1_data_1_p_s;
wire [24:0] p1_data_1_n_s;
wire [24:0] p1_data_1_s;
wire [24:0] p1_data_2_p_s;
wire [24:0] p1_data_2_n_s;
wire [24:0] p1_data_2_s;
wire [24:0] p1_data_3_p_s;
wire [24:0] p1_data_3_n_s;
wire [24:0] p1_data_3_s;
wire [24:0] p1_data_4_p_s;
wire [24:0] p1_data_4_n_s;
wire [24:0] p1_data_4_s;
// pipe line stage 1, get the two's complement versions
assign p1_data_1_p_s = {1'b0, data_1[23:0]};
assign p1_data_1_n_s = ~p1_data_1_p_s + 1'b1;
assign p1_data_1_s = (data_1[24] == 1'b1) ? p1_data_1_n_s : p1_data_1_p_s;
assign p1_data_2_p_s = {1'b0, data_2[23:0]};
assign p1_data_2_n_s = ~p1_data_2_p_s + 1'b1;
assign p1_data_2_s = (data_2[24] == 1'b1) ? p1_data_2_n_s : p1_data_2_p_s;
assign p1_data_3_p_s = {1'b0, data_3[23:0]};
assign p1_data_3_n_s = ~p1_data_3_p_s + 1'b1;
assign p1_data_3_s = (data_3[24] == 1'b1) ? p1_data_3_n_s : p1_data_3_p_s;
assign p1_data_4_p_s = {1'b0, data_4[23:0]};
assign p1_data_4_n_s = ~p1_data_4_p_s + 1'b1;
assign p1_data_4_s = (data_4[24] == 1'b1) ? p1_data_4_n_s : p1_data_4_p_s;
always @(posedge clk) begin
p1_ddata <= ddata_in;
p1_data_1 <= p1_data_1_s;
p1_data_2 <= p1_data_2_s;
p1_data_3 <= p1_data_3_s;
p1_data_4 <= p1_data_4_s;
end
// pipe line stage 2, get the sum (intermediate, 4->2)
always @(posedge clk) begin
p2_ddata <= p1_ddata;
p2_data_0 <= p1_data_1 + p1_data_2;
p2_data_1 <= p1_data_3 + p1_data_4;
end
// pipe line stage 3, get the sum (final, 2->1)
always @(posedge clk) begin
p3_ddata <= p2_ddata;
p3_data <= p2_data_0 + p2_data_1;
end
// output registers, output is unsigned (0 if sum is < 0) and saturated.
// the inputs are expected to be 1.4.20 format (output is 8bits).
always @(posedge clk) begin
ddata_out <= p3_ddata;
if (p3_data[24] == 1'b1) begin
data_p <= 8'h00;
end else if (p3_data[23:20] == 'd0) begin
data_p <= p3_data[19:12];
end else begin
data_p <= 8'hff;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title :
// File :
// Author : Jim MacLeod
// Created : 01-Dec-2011
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
//////////////////////////////////////////////////////////////////
// Float to fixed converts floating point numbers to 16.16 sign
//
//
module flt_fx_23p9
(
input [31:0] fp_in, // Floating point in IEEE fmt
output reg [31:0] int_out // Fixed point integer out
);
//
// 23.9, UV.
//
wire [7:0] bias_exp; /* Real exponent -127 - 128 */
wire [7:0] bias_exp2; /* Real exponent 2's comp */
wire [39:0] fixed_out2; /* 2's complement of fixed out */
wire [47:0] bias_mant; /* mantissa expanded to 16.16 fmt */
reg [47:0] int_fixed_out;
reg [31:0] fixed_out;
assign bias_mant = {25'h0001, fp_in[22:0]};
assign bias_exp = fp_in[30:23] - 'd127;
assign bias_exp2 = ~bias_exp + 1;
// infinity or NaN - Don't do anything special, will overflow
always @* begin
// zero condition
if (fp_in[30:0] == 31'b0) int_fixed_out = 0;
// negative exponent
else if (bias_exp[7]) int_fixed_out = bias_mant >> bias_exp2;
// positive exponent
else int_fixed_out = bias_mant << bias_exp;
fixed_out = int_fixed_out[45:14];
int_out = (fp_in[31]) ? ~fixed_out + 1 : fixed_out;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFINV_16_V
`define SKY130_FD_SC_LP__BUFINV_16_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog wrapper for bufinv with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__bufinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__bufinv_16 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__bufinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__bufinv_16 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__bufinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFINV_16_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND4_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__AND4_PP_BLACKBOX_V
/**
* and4: 4-input AND.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__and4 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND4_PP_BLACKBOX_V
|
/*
* Check the basic parsing.
*/
// A global timeunit and timeprecision are OK
timeunit 100us;
timeprecision 1us;
/*
* Check the various timeunit/precision combinations (this is valid SV syntax).
*/
// A local time unit is OK.
module check_tu;
timeunit 10us;
endmodule
// A local time precision is OK.
module check_tp;
timeprecision 10us;
endmodule
// Both a local time unit and precision are OK.
module check_tup;
timeunit 10us;
timeprecision 10us;
endmodule
// Both a local time unit and precision are OK (check both orders).
module check_tpu;
timeprecision 10us;
timeunit 10us;
endmodule
/*
* Now do the same with repeat declarations (this is valid SV syntax).
*/
// A global timeunit and timeprecision are OK
timeunit 100us;
timeprecision 1us;
// A local time unit is OK.
module check_tu_d;
timeunit 10us;
timeunit 10us;
endmodule
// A local time precision is OK.
module check_tp_d;
timeprecision 10us;
timeprecision 10us;
endmodule
// Both a local time unit and precision are OK.
module check_tup_d;
timeunit 10us;
timeprecision 10us;
timeunit 10us;
timeprecision 10us;
endmodule
// Both a local time unit and precision are OK (check both orders).
module check_tpu_d;
timeprecision 10us;
timeunit 10us;
timeprecision 10us;
timeunit 10us;
endmodule
/*
* Now check all the valid timeunit and time precision values.
*/
module check_100s;
timeunit 100s;
timeprecision 100s;
endmodule
module check_10s;
timeunit 10s;
timeprecision 10s;
endmodule
module check_1s;
timeunit 1s;
timeprecision 1s;
endmodule
module check_100ms;
timeunit 100ms;
timeprecision 100ms;
endmodule
module check_10ms;
timeunit 10ms;
timeprecision 10ms;
endmodule
module check_1ms;
timeunit 1ms;
timeprecision 1ms;
endmodule
module check_100us;
timeunit 100us;
timeprecision 100us;
endmodule
module check_10us;
timeunit 10us;
timeprecision 10us;
endmodule
module check_1us;
timeunit 1us;
timeprecision 1us;
endmodule
module check_100ns;
timeunit 100ns;
timeprecision 100ns;
endmodule
module check_10ns;
timeunit 10ns;
timeprecision 10ns;
endmodule
module check_1ns;
timeunit 1ns;
timeprecision 1ns;
endmodule
module check_100ps;
timeunit 100ps;
timeprecision 100ps;
endmodule
module check_10ps;
timeunit 10ps;
timeprecision 10ps;
endmodule
module check_1ps;
timeunit 1ps;
timeprecision 1ps;
endmodule
module check_100fs;
timeunit 100fs;
timeprecision 100fs;
endmodule
module check_10fs;
timeunit 10fs;
timeprecision 10fs;
endmodule
module check_1fs;
timeunit 1fs;
timeprecision 1fs;
endmodule
module check1;
initial begin
$printtimescale(check_100s);
$printtimescale(check_10s);
$printtimescale(check_1s);
$printtimescale(check_100ms);
$printtimescale(check_10ms);
$printtimescale(check_1ms);
$printtimescale(check_100us);
$printtimescale(check_10us);
$printtimescale(check_1us);
$printtimescale(check_100ns);
$printtimescale(check_10ns);
$printtimescale(check_1ns);
$printtimescale(check_100ps);
$printtimescale(check_10ps);
$printtimescale(check_1ps);
$printtimescale(check_100fs);
$printtimescale(check_10fs);
$printtimescale(check_1fs);
$display("");
$printtimescale(check_tu);
$printtimescale(check_tp);
$printtimescale(check_tup);
$printtimescale(check_tpu);
$display("");
$printtimescale(check_tu_d);
$printtimescale(check_tp_d);
$printtimescale(check_tup_d);
$printtimescale(check_tpu_d);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int r = 0, u = 0; string s; cin >> s; for (int i = 0; i < s.size(); i++) { if (s[i] == L ) r--; else if (s[i] == R ) r++; else if (s[i] == U ) u++; else if (s[i] == D ) u--; } r *= r < 0 ? -1 : 1; u *= u < 0 ? -1 : 1; if ((r + u) % 2 == 0) cout << (r + u) / 2; else cout << -1; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100005; const int inf = 1 << 30; const long long INF = 1ll << 61; const double oo = 1 << 30; const long long zqc = 1e9 + 7; int n, k; int t, x; vector<int> a; int gcd(int a, int b) { return !b ? a : gcd(b, a % b); } int main() { scanf( %d%d , &n, &k); t = n / 2; --t; x = k - t; if (k == 0 && n == 1) return 0 * printf( 1 ); if (x <= 0) return 0 * printf( -1 ); if (n == 1) return 0 * printf( -1 ); a.push_back(x); a.push_back(2 * x); for (int i = 1; i <= 1e9; ++i) { if (a.size() == n) break; if (x == i || 2 * x == i) continue; if (a.size() % 2 == 1 && gcd(a[a.size() - 1], i) != 1) continue; a.push_back(i); } for (auto p : a) printf( %d , p); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFSBP_TB_V
`define SKY130_FD_SC_HDLL__SDFSBP_TB_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__sdfsbp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg SET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SCD = 1'b0;
#60 SCE = 1'b0;
#80 SET_B = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 D = 1'b1;
#200 SCD = 1'b1;
#220 SCE = 1'b1;
#240 SET_B = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 D = 1'b0;
#360 SCD = 1'b0;
#380 SCE = 1'b0;
#400 SET_B = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SET_B = 1'b1;
#600 SCE = 1'b1;
#620 SCD = 1'b1;
#640 D = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SET_B = 1'bx;
#760 SCE = 1'bx;
#780 SCD = 1'bx;
#800 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hdll__sdfsbp dut (.D(D), .SCD(SCD), .SCE(SCE), .SET_B(SET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFSBP_TB_V
|
#include <bits/stdc++.h> using namespace std; constexpr int MAXN = 128; int type[MAXN][MAXN]; constexpr char* pat[6] = { #//. , #. , .# , .//# , .... , #### }; int main() { int n, m, a, b, c, k, x, y; scanf( %d%d , &n, &m); scanf( %d%d%d , &a, &b, &c); k = 0; for (int i = 0; i < a; ++i, ++k) type[k / m][k % m] = 5; y = k % m; for (int i = 0; i < m; ++i, ++k) type[k / m][k % m] = (((k % m - y) % 2 == 0) ^ (k % m < y)) ? 0 : 1; for (int i = 0; i < b; ++i, ++k) type[k / m][k % m] = 4; for (int i = m; i < c; ++i, ++k) for (int j = 0; j < 4; ++j) { x = k / m; y = k % m; if ((x == 0 || ((type[x - 1][y] ^ j) & 2) != 0) && (y == 0 || ((type[x][y - 1] ^ j) & 1) != 0)) { type[k / m][k % m] = j; break; } } for (int i = 0; i < n + n; ++i) { for (int j = 0; j < m + m; ++j) putchar(pat[type[i / 2][j / 2]][i % 2 * 2 + j % 2]); putchar( n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<long long int> v; int bil; void gen(long long int now) { if (now > 1000000000LL) return; if (now != 0) v.push_back(now); gen(now * 10 + 4); gen(now * 10 + 7); } int main(void) { gen(0); sort(v.begin(), v.end()); cin >> bil; for (int i = 0; i < v.size(); i++) { if (v[i] == bil) { cout << i + 1 << endl; return 0; } } }
|
/*
########################################################################
ELINK TX CONFIGURATION REGISTER FILE
########################################################################
*/
`include "elink_regmap.v"
module etx_cfg (/*AUTOARG*/
// Outputs
mi_dout, tx_enable, mmu_enable, gpio_enable, remap_enable,
gpio_data, ctrlmode, ctrlmode_bypass,
// Inputs
reset, clk, mi_en, mi_we, mi_addr, mi_din, tx_status
);
/******************************/
/*Compile Time Parameters */
/******************************/
parameter PW = 104;
parameter RFAW = 6;
parameter DEFAULT_VERSION = 16'h0000;
/******************************/
/*HARDWARE RESET (EXTERNAL) */
/******************************/
input reset;
input clk;
/*****************************/
/*SIMPLE MEMORY INTERFACE */
/*****************************/
input mi_en;
input mi_we;
input [RFAW+1:0] mi_addr; // complete address (no shifting!)
input [31:0] mi_din; // (lower 2 bits not used)
output [31:0] mi_dout;
/*****************************/
/*ELINK CONTROL SIGNALS */
/*****************************/
//tx (static configs)
output tx_enable; // enable signal for TX
output mmu_enable; // enables MMU on transmit path
output gpio_enable; // forces TX output pins to constants
output remap_enable; // enable address remapping
input [15:0] tx_status; // etx status signals
//sampled by tx_lclk (test)
output [8:0] gpio_data; // data for elink outputs (static)
//dynamic (control timing by use mode)
output [3:0] ctrlmode; // value for emesh ctrlmode tag
output ctrlmode_bypass; // selects ctrlmode
//registers
reg [15:0] ecfg_version_reg;
reg [10:0] ecfg_tx_config_reg;
reg [8:0] ecfg_tx_gpio_reg;
reg [2:0] ecfg_tx_status_reg;
reg [31:0] mi_dout;
reg ecfg_access;
//wires
wire ecfg_read;
wire ecfg_write;
wire ecfg_tx_config_write;
wire ecfg_tx_gpio_write;
wire ecfg_tx_test_write;
wire ecfg_tx_addr_write;
wire ecfg_tx_data_write;
wire loop_mode;
/*****************************/
/*ADDRESS DECODE LOGIC */
/*****************************/
//read/write decode
assign ecfg_write = mi_en & mi_we;
assign ecfg_read = mi_en & ~mi_we;
//Config write enables
assign ecfg_version_write = ecfg_write & (mi_addr[RFAW+1:2]==`E_VERSION);
assign ecfg_tx_config_write = ecfg_write & (mi_addr[RFAW+1:2]==`ETX_CFG);
assign ecfg_tx_status_write = ecfg_write & (mi_addr[RFAW+1:2]==`ETX_STATUS);
assign ecfg_tx_gpio_write = ecfg_write & (mi_addr[RFAW+1:2]==`ETX_GPIO);
//###########################
//# TX CONFIG
//###########################
always @ (posedge clk)
if(reset)
ecfg_tx_config_reg[10:0] <= 11'b0;
else if (ecfg_tx_config_write)
ecfg_tx_config_reg[10:0] <= mi_din[10:0];
assign tx_enable = 1'b1;//TODO: fix! ecfg_tx_config_reg[0];
assign mmu_enable = ecfg_tx_config_reg[1];
assign remap_enable = ecfg_tx_config_reg[3:2]==2'b01;
assign ctrlmode[3:0] = ecfg_tx_config_reg[7:4];
assign ctrlmode_bypass = ecfg_tx_config_reg[8];
assign gpio_enable = (ecfg_tx_config_reg[10:9]==2'b01);
//###########################
//# STATUS REGISTER
//###########################
always @ (posedge clk)
if(reset)
ecfg_tx_status_reg[2:0] <= 'd0;
else
ecfg_tx_status_reg[2:0]<= ecfg_tx_status_reg[2:0] | tx_status[2:0];
//###########################
//# GPIO DATA
//###########################
always @ (posedge clk)
if(reset)
ecfg_tx_gpio_reg[8:0] <= 'd0;
else if (ecfg_tx_gpio_write)
ecfg_tx_gpio_reg[8:0] <= mi_din[8:0];
assign gpio_data[8:0] = ecfg_tx_gpio_reg[8:0];
//###########################
//# VERSION
//###########################
always @ (posedge clk)
if(reset)
ecfg_version_reg[15:0] <= DEFAULT_VERSION;
else if (ecfg_version_write)
ecfg_version_reg[15:0] <= mi_din[15:0];
//###############################
//# DATA READBACK MUX
//###############################
//Pipelineing readback
always @ (posedge clk)
if(ecfg_read)
case(mi_addr[RFAW+1:2])
`ETX_CFG: mi_dout[31:0] <= {21'b0, ecfg_tx_config_reg[10:0]};
`ETX_GPIO: mi_dout[31:0] <= {23'b0, ecfg_tx_gpio_reg[8:0]};
`ETX_STATUS: mi_dout[31:0] <= {16'b0, tx_status[15:3],ecfg_tx_status_reg[2:0]};
`E_VERSION: mi_dout[31:0] <= {16'b0, ecfg_version_reg[15:0]};
default: mi_dout[31:0] <= 32'd0;
endcase // case (mi_addr[RFAW+1:2])
else
mi_dout[31:0] <= 32'd0;
endmodule // ecfg_tx
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2014 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2014.3
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Static Synchronous RAM 64-Deep by 1-Wide
// /___/ /\ Filename : RAM64X1S.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 03/23/04 - Initial version.
// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove for-loop in initial block;
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 04/18/13 - PR683925 - add invertible pin support.
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module RAM64X1S #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [63:0] INIT = 64'h0,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
) (
output O,
input A0,
input A1,
input A2,
input A3,
input A4,
input A5,
input D,
input WCLK,
input WE
);
// define constants
localparam MODULE_NAME = "RAM64X1S";
reg trig_attr = 1'b0;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
wire IS_WCLK_INVERTED_BIN;
wire D_in;
wire WCLK_in;
wire WE_in;
wire [5:0] A_in;
assign IS_WCLK_INVERTED_BIN = IS_WCLK_INVERTED;
`ifdef XIL_TIMING
wire D_dly;
wire WCLK_dly;
wire WE_dly;
wire [5:0] A_dly;
reg notifier;
wire sh_clk_en_p;
wire sh_clk_en_n;
wire sh_we_clk_en_p;
wire sh_we_clk_en_n;
assign A_in = A_dly;
assign D_in = D_dly;
assign WCLK_in = WCLK_dly ^ IS_WCLK_INVERTED_BIN;
assign WE_in = (WE === 1'bz) || WE_dly; // rv 1
`else
assign A_in = {A5, A4, A3, A2, A1, A0};
assign D_in = D;
assign WCLK_in = WCLK ^ IS_WCLK_INVERTED_BIN;
assign WE_in = (WE === 1'bz) || WE; // rv 1
`endif
reg [63:0] mem;
initial
mem = INIT;
assign O = mem[A_in];
always @(posedge WCLK_in)
if (WE_in == 1'b1) mem[A_in] <= #100 D_in;
`ifdef XIL_TIMING
always @(notifier) mem[A_in] <= 1'bx;
assign sh_clk_en_p = ~IS_WCLK_INVERTED_BIN;
assign sh_clk_en_n = IS_WCLK_INVERTED_BIN;
assign sh_we_clk_en_p = WE_in && ~IS_WCLK_INVERTED_BIN;
assign sh_we_clk_en_n = WE_in && IS_WCLK_INVERTED_BIN;
specify
(WCLK => O) = (0:0:0, 0:0:0);
(A0 => O) = (0:0:0, 0:0:0);
(A1 => O) = (0:0:0, 0:0:0);
(A2 => O) = (0:0:0, 0:0:0);
(A3 => O) = (0:0:0, 0:0:0);
(A4 => O) = (0:0:0, 0:0:0);
(A5 => O) = (0:0:0, 0:0:0);
$period (negedge WCLK &&& WE, 0:0:0, notifier);
$period (posedge WCLK &&& WE, 0:0:0, notifier);
$setuphold (negedge WCLK, negedge A0, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[0]);
$setuphold (negedge WCLK, negedge A1, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[1]);
$setuphold (negedge WCLK, negedge A2, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[2]);
$setuphold (negedge WCLK, negedge A3, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[3]);
$setuphold (negedge WCLK, negedge A4, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[4]);
$setuphold (negedge WCLK, negedge A5, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[5]);
$setuphold (negedge WCLK, negedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,D_dly);
$setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly);
$setuphold (negedge WCLK, posedge A0, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[0]);
$setuphold (negedge WCLK, posedge A1, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[1]);
$setuphold (negedge WCLK, posedge A2, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[2]);
$setuphold (negedge WCLK, posedge A3, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[3]);
$setuphold (negedge WCLK, posedge A4, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[4]);
$setuphold (negedge WCLK, posedge A5, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[5]);
$setuphold (negedge WCLK, posedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,D_dly);
$setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, negedge A0, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[0]);
$setuphold (posedge WCLK, negedge A1, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[1]);
$setuphold (posedge WCLK, negedge A2, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[2]);
$setuphold (posedge WCLK, negedge A3, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[3]);
$setuphold (posedge WCLK, negedge A4, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[4]);
$setuphold (posedge WCLK, negedge A5, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[5]);
$setuphold (posedge WCLK, negedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,D_dly);
$setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, posedge A0, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[0]);
$setuphold (posedge WCLK, posedge A1, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[1]);
$setuphold (posedge WCLK, posedge A2, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[2]);
$setuphold (posedge WCLK, posedge A3, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[3]);
$setuphold (posedge WCLK, posedge A4, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[4]);
$setuphold (posedge WCLK, posedge A5, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[5]);
$setuphold (posedge WCLK, posedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,D_dly);
$setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
#include <bits/stdc++.h> const int maxn = 1e6 + 5; const int maxm = 1e5 + 5; using namespace std; int rd() { int x = 0; char c = getchar(); while (!isdigit(c)) c = getchar(); while (isdigit(c)) x = (x << 3) + (x << 1) + c - 0 , c = getchar(); return x; } int n, head[maxn], tot, a, b, c, d, cnt, Node, rk[maxn], len, lst[maxn], top; int lena, lenb, lenc, lend, mx; vector<int> vec[maxn]; bitset<maxm> res; struct node { int v, nxt; } e[maxn << 1]; void add(int u, int v) { e[++tot].v = v; e[tot].nxt = head[u]; head[u] = tot; } void dfs(int u, int y) { bool flag = true; for (int i = head[u]; i; i = e[i].nxt) { int v = e[i].v; if (v == y) continue; if (u == 1) ++cnt; flag = false; dfs(v, u); } if (flag) vec[cnt].push_back(u), rk[u] = cnt; } bool check() { lena = ((int)vec[rk[a]].size()); lenb = ((int)vec[rk[b]].size()); lenc = ((int)vec[rk[c]].size()); lend = ((int)vec[rk[d]].size()); for (int i = max(0, len - lena - lenb); i <= len - 2; i++) { if (lenc <= i && res[i - lenc]) return true; if (lend <= i && res[i - lend]) return true; } for (int i = max(0, len - lenc - lend); i <= len - 2; i++) { if (lena <= i && res[i - lena]) return true; if (lenb <= i && res[i - lenb]) return true; } return false; } int main() { n = rd(); a = rd(); b = rd(); c = rd(); d = rd(); for (int i = 2, u; i <= n; i++) { u = rd(); add(u, i); add(i, u); } dfs(1, 0); for (int i = 1; i <= cnt; i++) { Node += ((int)vec[i].size()); if (i != rk[a] && i != rk[b] && i != rk[c] && i != rk[d]) lst[++top] = ((int)vec[i].size()), mx = max(mx, ((int)vec[i].size())); } if (Node & 1) { puts( No ); return 0; } len = Node / 2 + 1; if (rk[a] == rk[b]) { puts( No ); return 0; } if (rk[c] == rk[d]) { puts( No ); return 0; } if (((int)vec[rk[a]].size()) > Node - len || ((int)vec[rk[b]].size()) > Node - len || ((int)vec[rk[c]].size()) > Node - len || ((int)vec[rk[d]].size()) > Node - len || mx > Node - len) { puts( No ); return 0; } res.set(0); for (int i = 1; i <= top; i++) res |= res << lst[i]; puts(check() ? Yes : No ); return 0; }
|
module test ();
reg pass = 1'b1;
reg d;
real f = 0.0;
always @(d) assign f = 0;
initial begin
// Verify the initial value.
#1;
if (f != 0.0) begin
$display("Failed initial value, expected 0.0, got %f", f);
pass = 1'b0;
end
// Verify the value can change.
#1 f = 1.0;
if (f != 1.0) begin
$display("Failed value change, expected 1.0, got %f", f);
pass = 1'b0;
end
// Verify that the assign changed the value and that a normal assign
// is blocked.
#1 d = 0;
#1 f = 1.0;
if (f != 0.0) begin
$display("Failed assign holding, expected 0.0, got %f", f);
pass = 1'b0;
end
// Verify that the release holds the previous value.
#1 deassign f;
if (f != 0.0) begin
$display("Failed release holding, expected 0.0, got %f", f);
pass = 1'b0;
end
// Verify that the value can be changed after a release.
#1 f = 1.0;
if (f != 1.0) begin
$display("Failed release, expected 1.0, got %f", f);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long n, m; while (cin >> n >> m) { long long a[100100], b[101000], p, x, i, j, mm, l, r, cc = 0, pp, y, m1, qq = 0; l = 1; r = n + 1; while (l <= r) { x = (l + r) / 2; mm = 1; pp = 0; while (1) { if (x / mm == 0) { break; } pp += x / mm; mm *= m; } if (n > pp) l = x + 1; else r = x - 1; } cout << l << n ; } return 0; }
|
//MODULE REFERENCE
`define dut dut
`define tenv_clock tenv_clock
`define tenv_usbdev tenv_usbdev
`define tenv_usbhost tenv_usbhost
//MODULE INCLUDING
`include "tenv_link/tenv_usbtrver.v"
module tenv_link;
//CONNECTION WITH DEVICE SPECIFIC LOGIC INTERFACE
assign `dut.clk_4xrate= `tenv_clock.x4;
assign #1 `dut.rst0_async= `tenv_usbdev.rst0_async;
assign #1 `dut.rst0_sync= `tenv_usbdev.rst0_sync;
assign #1 `tenv_usbdev.trsac_req= `dut.trsac_req;
assign #1 `tenv_usbdev.trsac_ep= `dut.trsac_ep;
assign #1 `tenv_usbdev.trsac_type= `dut.trsac_type;
assign #1 `dut.trsac_reply= `tenv_usbdev.trsac_reply;
assign #1 `dut.rfifo_rd= `tenv_usbdev.rfifo_rd;
assign #1 `tenv_usbdev.rfifo_empty= `dut.rfifo_empty;
assign #1 `tenv_usbdev.rfifo_rdata= `dut.rfifo_rdata;
assign #1 `dut.tfifo_wr= `tenv_usbdev.tfifo_wr;
assign #1 `tenv_usbdev.tfifo_full= `dut.tfifo_full;
assign #1 `dut.tfifo_wdata= `tenv_usbdev.tfifo_wdata;
assign #1 `dut.ep_enable= `tenv_usbdev.ep_enable;
assign #1 `dut.ep_isoch= `tenv_usbdev.ep_isoch;
assign #1 `dut.ep_intnoretry= `tenv_usbdev.ep_intnoretry;
assign #1 `dut.device_wakeup= `tenv_usbdev.device_wakeup;
assign #1 `dut.device_speed= `tenv_usbdev.speed;
assign #1 `dut.device_addr_wr= `tenv_usbdev.device_addr_wr;
assign #1 `dut.device_addr= `tenv_usbdev.device_addr;
assign #1 `dut.device_config_wr= `tenv_usbdev.device_config_wr;
assign #1 `dut.device_config= `tenv_usbdev.device_config;
assign #1 `tenv_usbdev.device_state=`dut.device_state;
assign #1 `tenv_usbdev.sof_tick= `dut.sof_tick;
assign #1 `tenv_usbdev.sof_value= `dut.sof_value;
//CONNECTION WITH USB LINE THROUGH USB TRANSCEIVER
tenv_usbtrver i_duttrver (
.sync_clk(1'b0),
.sync_mode(1'b0),
.speed(`tenv_usbdev.speed),
.dinp(`dut.dtx_plus),
.dinn(`dut.dtx_minus),
.doe(`dut.dtx_oe),
.doutp(`dut.drx_plus),
.doutn(`dut.drx_minus),
.doutdif(`dut.drx),
.usb_dp(`tenv_usbhost.dp),
.usb_dn(`tenv_usbhost.dn)
);
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_fptoui(clock, resetn,
i_datain, i_datain_valid, o_datain_stall,
o_dataout, i_dataout_stall, o_dataout_valid);
parameter DATA_WIDTH = 32;
parameter LATENCY = 3;
parameter FIFO_DEPTH = 64;
input clock, resetn;
input [DATA_WIDTH-1:0] i_datain;
input i_datain_valid;
output o_datain_stall;
output [DATA_WIDTH-1:0] o_dataout;
input i_dataout_stall;
output o_dataout_valid;
reg [LATENCY-1:0] shift_reg_valid;
wire [DATA_WIDTH-1:0] fifo_dataout;
wire fifo_dataout_valid;
wire is_stalled;
wire is_fifo_stalled;
vfabric_buffered_fifo fifo_in ( .clock(clock), .resetn(resetn),
.data_in(i_datain), .data_out(fifo_dataout), .valid_in(i_datain_valid),
.valid_out( fifo_dataout_valid ), .stall_in(is_fifo_stalled), .stall_out(o_datain_stall) );
defparam fifo_in.DATA_WIDTH = DATA_WIDTH;
defparam fifo_in.DEPTH = FIFO_DEPTH;
acl_fp_fptoui fp2ui( .clock(clock), .enable(~is_stalled),
.resetn(resetn), .dataa(fifo_dataout), .result(o_dataout));
always @(posedge clock or negedge resetn)
begin
if (~resetn)
begin
shift_reg_valid <= {LATENCY{1'b0}};
end
else
begin
if(~is_stalled)
shift_reg_valid <= { fifo_dataout_valid, shift_reg_valid[LATENCY-1:1] };
end
end
assign is_stalled = (shift_reg_valid[0] & i_dataout_stall);
assign is_fifo_stalled = (shift_reg_valid[0] & i_dataout_stall) | ~fifo_dataout_valid;
assign o_dataout_valid = shift_reg_valid[0];
endmodule
|
#include <bits/stdc++.h> using namespace std; int arr[100][100]; bool dp[100][100][1000]; bool W[100][100][1000]; int main() { int N; int M; int K; scanf( %d %d %d , &N, &M, &K); K++; char ch[101]; for (int n = 0; n < N; n++) { scanf( %s , ch); for (int m = 0; m < M; m++) { arr[n][m] = ch[m] - 0 ; } } memset(dp, false, sizeof(dp)); for (int m = 0; m < M; m++) { dp[N - 1][m][arr[N - 1][m]] = true; } for (int n = N - 2; n >= 0; n--) { for (int m = 0; m < M; m++) { int y[] = {n + 1, n + 1}; int x[] = {m - 1, m + 1}; for (int pos = 0; pos < 2; pos++) { int Y = y[pos]; int X = x[pos]; if (Y >= 0 && Y < N && X >= 0 && X < M) { for (int k = 0; k < 1000; k++) { if (dp[Y][X][k]) { dp[n][m][k + arr[n][m]] = true; W[n][m][k + arr[n][m]] = pos; } } } } } } int sol = -1; int pos = -1; for (int k = 0; k < 1000; k += K) { for (int m = 0; m < M; m++) { if (dp[0][m][k]) { sol = k; pos = m; } } } printf( %d n , sol); if (sol != -1) { int help = sol; stack<int> st; for (int n = 0; n < N - 1; n++) { st.push(W[n][pos][help]); if (W[n][pos][help] == 0) { help -= arr[n][pos]; pos--; } else { help -= arr[n][pos]; pos++; } } printf( %d n , pos + 1); while (!st.empty()) { if (st.top() == 0) { printf( R ); } else { printf( L ); } st.pop(); } printf( n ); } return 0; }
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_256_134.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.0.0 Build 211 04/27/2016 SJ Standard Edition
// ************************************************************
//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_256_134 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
q,
usedw);
input aclr;
input clock;
input [133:0] data;
input rdreq;
input wrreq;
output empty;
output [133:0] q;
output [7:0] usedw;
wire sub_wire0;
wire [133:0] sub_wire1;
wire [7:0] sub_wire2;
wire empty = sub_wire0;
wire [133:0] q = sub_wire1[133:0];
wire [7:0] usedw = sub_wire2[7:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.q (sub_wire1),
.usedw (sub_wire2),
.almost_empty (),
.almost_full (),
.eccstatus (),
.full (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Stratix V",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 134,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "134"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "134"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "134"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 134 0 INPUT NODEFVAL "data[133..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: q 0 0 134 0 OUTPUT NODEFVAL "q[133..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL "usedw[7..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 134 0 data 0 0 134 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: q 0 0 134 0 @q 0 0 134 0
// Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_256_134.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_256_134.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_256_134.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_256_134.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_256_134_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_256_134_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 18:54:10 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_nco_0_0_stub.v
// Design : ip_design_nco_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "nco,Vivado 2017.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_AXILiteS_AWADDR,
s_axi_AXILiteS_AWVALID, s_axi_AXILiteS_AWREADY, s_axi_AXILiteS_WDATA,
s_axi_AXILiteS_WSTRB, s_axi_AXILiteS_WVALID, s_axi_AXILiteS_WREADY,
s_axi_AXILiteS_BRESP, s_axi_AXILiteS_BVALID, s_axi_AXILiteS_BREADY,
s_axi_AXILiteS_ARADDR, s_axi_AXILiteS_ARVALID, s_axi_AXILiteS_ARREADY,
s_axi_AXILiteS_RDATA, s_axi_AXILiteS_RRESP, s_axi_AXILiteS_RVALID,
s_axi_AXILiteS_RREADY, ap_clk, ap_rst_n)
/* synthesis syn_black_box black_box_pad_pin="s_axi_AXILiteS_AWADDR[5:0],s_axi_AXILiteS_AWVALID,s_axi_AXILiteS_AWREADY,s_axi_AXILiteS_WDATA[31:0],s_axi_AXILiteS_WSTRB[3:0],s_axi_AXILiteS_WVALID,s_axi_AXILiteS_WREADY,s_axi_AXILiteS_BRESP[1:0],s_axi_AXILiteS_BVALID,s_axi_AXILiteS_BREADY,s_axi_AXILiteS_ARADDR[5:0],s_axi_AXILiteS_ARVALID,s_axi_AXILiteS_ARREADY,s_axi_AXILiteS_RDATA[31:0],s_axi_AXILiteS_RRESP[1:0],s_axi_AXILiteS_RVALID,s_axi_AXILiteS_RREADY,ap_clk,ap_rst_n" */;
input [5:0]s_axi_AXILiteS_AWADDR;
input s_axi_AXILiteS_AWVALID;
output s_axi_AXILiteS_AWREADY;
input [31:0]s_axi_AXILiteS_WDATA;
input [3:0]s_axi_AXILiteS_WSTRB;
input s_axi_AXILiteS_WVALID;
output s_axi_AXILiteS_WREADY;
output [1:0]s_axi_AXILiteS_BRESP;
output s_axi_AXILiteS_BVALID;
input s_axi_AXILiteS_BREADY;
input [5:0]s_axi_AXILiteS_ARADDR;
input s_axi_AXILiteS_ARVALID;
output s_axi_AXILiteS_ARREADY;
output [31:0]s_axi_AXILiteS_RDATA;
output [1:0]s_axi_AXILiteS_RRESP;
output s_axi_AXILiteS_RVALID;
input s_axi_AXILiteS_RREADY;
input ap_clk;
input ap_rst_n;
endmodule
|
// ---------------------------------------------
// external memory controller
// ---------------------------------------------
// The CPU runs at ~50MHz (20ns)
//
// When accessing byte-wide external memory, sufficient wait states
// need to be added to allow two slower memory cycles to happen
// (low byte then high byte)
//
// IS61WV25616EDBLL-10TLI RAM timings:
// -- Read access time is 10ns
//
// -- Min write pulse is 8ns, write happens on rising edge
// -- Address setup from falling edge of write is 8ns
// -- Address hold from rising edge of write is 0ns
// -- Data setup from rising edge of write is 9ns
// -- Address hold from rising edge of write is 0ns
//
// To err on the safe side, we allow 2 cycles for each half-word access
//
// So a complete external memory access (both 16-bit half-words) takes 4 cycles
//
// Which means the memory controller must insert 3 wait states
module memory_controller
(
clock,
reset_b,
// CPU Signals
ext_cs_b,
cpu_rnw,
cpu_clken,
cpu_addr,
cpu_dout,
ext_dout,
// Ram Signals
ram_cs_b,
ram_oe_b,
ram_we_b,
ram_data_in,
ram_data_out,
ram_data_oe,
ram_addr
);
parameter DSIZE = 32;
parameter ASIZE = 20;
input clock;
input reset_b;
// CPU Signals
input ext_cs_b;
input cpu_rnw;
output cpu_clken;
input [ASIZE-1:0] cpu_addr;
input [DSIZE-1:0] cpu_dout;
output [DSIZE-1:0] ext_dout;
// Ram Signals
output ram_cs_b;
output ram_oe_b;
output ram_we_b;
output [17:0] ram_addr;
input [15:0] ram_data_in;
output [15:0] ram_data_out;
output ram_data_oe;
wire ext_a_lsb;
reg ext_we_b;
reg [15:0] ram_data_last;
reg [1:0] count;
// Count 0..3 during external memory cycles
always @(posedge clock)
if (!reset_b)
count <= 0;
else if (!ext_cs_b || count > 0)
count <= count + 1;
// Drop clken for 3 cycles during an external memory access
assign cpu_clken = !(!ext_cs_b && count < 3);
// A0 = 0 for count 0,1 (low half-word) and A0 = 1 for count 2,3 (high half-word)
assign ext_a_lsb = count[1];
// Generate clean write co-incident with cycles 1 and 3
// This gives a cycle of address/data setup and
// Important this is a register so it is glitch free
always @(posedge clock)
if (!cpu_rnw && !ext_cs_b && !count[0])
ext_we_b <= 1'b0;
else
ext_we_b <= 1'b1;
// The low byte is registered at the end of cycle 1
// The high byte is consumed directly from RAM at the end of cycle 3
always @(posedge clock)
if (count[0] == 1'b1)
ram_data_last <= ram_data_in;
assign ext_dout = { ram_data_in, ram_data_last };
// ---------------------------------------------
// external RAM
// ---------------------------------------------
assign ram_addr = {cpu_addr[16:0], ext_a_lsb};
assign ram_cs_b = ext_cs_b;
assign ram_oe_b = !cpu_rnw;
assign ram_we_b = ext_we_b;
assign ram_data_oe = !cpu_rnw;
assign ram_data_out = ext_a_lsb == 1 ? cpu_dout[31:16] :
cpu_dout[15:0] ;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRBP_BLACKBOX_V
`define SKY130_FD_SC_LS__DLRBP_BLACKBOX_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlrbp (
Q ,
Q_N ,
RESET_B,
D ,
GATE
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRBP_BLACKBOX_V
|
/////////////////////////////////////////////////////////////////////
//// ////
//// SPI Slave Model ////
//// ////
//// Authors: Richard Herveille () www.asics.ws ////
//// ////
//// http://www.opencores.org/projects/simple_spi/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Richard Herveille ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: spi_slave_model.v,v 1.1 2004-02-28 16:01:47 rherveille Exp $
//
// $Date: 2004-02-28 16:01:47 $
// $Revision: 1.1 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
//
//
//
// Requires: Verilog2001
`include "timescale.v"
module spi_slave_model (
input wire csn;
input wire sck
input wire di;
output wire do
);
//
// Variable declaration
//
wire debug = 1'b1;
wire cpol = 1'b0;
wire cpha = 1'b0;
reg [7:0] mem [7:0]; // initiate memory
reg [2:0] mem_adr; // memory address
reg [7:0] mem_do; // memory data output
reg [7:0] sri, sro; // 8bit shift register
reg [2:0] bit_cnt;
reg ld;
wire clk;
//
// module body
//
assign clk = cpol ^ cpha ^ sck;
// generate shift registers
always @(posedge clk)
sri <= #1 {sri[6:0],di};
always @(posedge clk)
if (&bit_cnt)
sro <= #1 mem[mem_adr];
else
sro <= #1 {sro[6:0],1'bx};
assign do = sro[7];
//generate bit-counter
always @(posedge clk, posedge csn)
if(csn)
bit_cnt <= #1 3'b111;
else
bit_cnt <= #1 bit_cnt - 3'h1;
//generate access done signal
always @(posedge clk)
ld <= #1 ~(|bit_cnt);
always @(negedge clk)
if (ld) begin
mem[mem_adr] <= #1 sri;
mem_adr <= #1 mem_adr + 1'b1;
end
initial
begin
bit_cnt=3'b111;
mem_adr = 0;
sro = mem[mem_adr];
end
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: adc_data_fifo.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1.dp1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module adc_data_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input aclr;
input [11:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [11:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [11:0] sub_wire1;
wire sub_wire2;
wire wrfull = sub_wire0;
wire [11:0] q = sub_wire1[11:0];
wire rdempty = sub_wire2;
dcfifo dcfifo_component (
.rdclk (rdclk),
.wrclk (wrclk),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.wrfull (sub_wire0),
.q (sub_wire1),
.rdempty (sub_wire2),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Cyclone V",
dcfifo_component.lpm_numwords = 2048,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 12,
dcfifo_component.lpm_widthu = 11,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "2048"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "12"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "12"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "12"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 12 0 INPUT NODEFVAL "data[11..0]"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 12 0 data 0 0 12 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q 0 0 12 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n; long int a = 0, b = 0, c = 0; for (int i = 0; i < n; i++) { cin >> k; a = a + k; } for (int i = 0; i < n - 1; i++) { cin >> k; b = b + k; } for (int i = 0; i < n - 2; i++) { cin >> k; c = c + k; } cout << a - b << endl << b - c; return 0; }
|
module BET_FSM (
clk_50,
rst,
// ram (BET) ports
ram_addr,
ram_r,
ram_w,
ram_w_en,
// garbage collection ports
garbage_en,
garbage_state,
garbage_addr
);
parameter T = 100;
parameter BET_size = 8192;
parameter cmp_ratio = 3'd0,
cmp_flag_count = 3'd1,
rst_bet = 3'd2,
read_bet = 3'd3,
check_flag = 3'd4,
errase_start = 3'd5,
errase_done = 3'd6;
input clk_50, rst;
input ram_r, garbage_state;
output ram_w, ram_w_en, garbage_en;
output [11:0] garbage_addr, ram_addr;
reg ram_w, ram_w_en, flag, garbage_en;
reg [2:0] NS,S;
reg [11:0] f_index,f_index_next, ram_addr, garbage_addr, count;
reg [31:0] e_cnt, f_cnt,ratio;
always @(posedge clk_50 or negedge rst) begin
if (rst == 1'b0) begin
S <= cmp_ratio;
NS <= cmp_ratio;
end else begin
S <= NS;
case (S)
cmp_ratio:
begin
if (ratio < T)
NS <= cmp_ratio;
else
NS <= cmp_flag_count;
end
cmp_flag_count:
begin
if (f_cnt < BET_size)
NS <= read_bet;
else
NS <= rst_bet;
end
rst_bet:
begin
if (count <= BET_size) begin
count <= count + 1'b1;
ram_w_en <= 1'b1;
ram_w <= 1'b0;
ram_addr <= count;
end else begin
f_cnt <= 32'd0;
count <= 12'd0;
NS <= cmp_ratio;
end
end
read_bet:
begin
flag <= ram_r;
ram_addr <= f_index_next;
end
check_flag:
begin
if( flag == 1'b1) begin
NS <= read_bet;
f_index <= f_index_next;
f_index_next <= f_index_next + 1'b1;
end else begin
NS <= errase_start;
end
end
errase_start:
begin
garbage_addr <= f_index;
if (garbage_state == 1'b0) begin
garbage_en <= 1'b1;
NS <= errase_done;
end else begin
garbage_en <= 1'b0;
NS <= errase_start;
end
end
errase_done:
begin
if (garbage_state == 1'b1) begin
NS <= errase_done;
end else begin
NS <= cmp_ratio;
end
end
default:
begin
NS <= cmp_ratio;
end
endcase
end
end
always @ (posedge clk_50 or negedge rst) begin
if (rst == 1'b0) begin
ratio <= 32'd0;
end else begin
ratio <= e_cnt / f_cnt;
end
end
endmodule
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.