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#include <bits/stdc++.h> using namespace std; string s; int n, x, y; void upd(pair<int, int> &pos, char mv, int d) { switch (mv) { case U : pos.second += d; break; case D : pos.second -= d; break; case L : pos.first -= d; break; case R : pos.first += d; break; } } bool can(pair<int, int> u, pair<int, int> v, int len) { int d = abs(u.first - v.first) + abs(u.second - v.second); if ((d & 1) != (len & 1)) return false; return len >= d; } bool ok(int len) { pair<int, int> pos = make_pair(0, 0); for (int i = len; i < n; ++i) upd(pos, s[i], 1); int l = 0, r = len; while (true) { if (can(pos, make_pair(x, y), len)) return true; if (r == n) break; upd(pos, s[l++], 1); upd(pos, s[r++], -1); } return false; } int main() { cin >> n >> s >> x >> y; if (!ok(n)) { cout << -1 << endl; return 0; } int l = 0, r = n; while (l < r) { int m = (l + r) >> 1; if (ok(m)) r = m; else l = m + 1; } cout << r << endl; return 0; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLXTP_BEHAVIORAL_V
`define SKY130_FD_SC_HD__DLXTP_BEHAVIORAL_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hd__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dlxtp (
Q ,
D ,
GATE
);
// Module ports
output Q ;
input D ;
input GATE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
reg notifier ;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
assign awake = ( VPWR === 1'b1 );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLXTP_BEHAVIORAL_V
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#include <bits/stdc++.h> using namespace std; const int INF = (1LL << 30) - 1; const long long int LINF = (1LL << 62) - 1; const int NMAX = (1e5) + 5; int N, M; int pile[NMAX]; bool check(long long int time) { int i, k; long long int curr; int P[NMAX]; memcpy(P, pile, sizeof(pile)); for (i = N, k = 1; k <= M; k++) { while (P[i] == 0 && i >= 1) i--; if (i == 0) return 1; curr = i; while (curr < time) { if (curr + P[i] <= time) { curr += P[i]; P[i] = 0; } else { P[i] -= time - curr; curr = time; } while (P[i] == 0 && i >= 1) i--; if (i == 0) return 1; } } return 0; } int main() { int i; long long int lo = 0, hi = 0, mi; long long int sol; cin.sync_with_stdio(false); scanf( %d%d , &N, &M); hi += N; for (i = 1; i <= N; i++) { scanf( %d , &pile[i]); hi += pile[i]; } sol = hi; while (lo <= hi) { mi = (lo + hi) / 2; if (check(mi)) { sol = min(sol, mi); hi = mi - 1; } else lo = mi + 1; } printf( %lld n , sol); return 0; }
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#include <bits/stdc++.h> using namespace std; void fast(); int main() { fast(); int n, cookies[105] = {0}; cin >> n; int sum = 0; for (int i = 0; i < n; ++i) { cin >> cookies[i]; sum += cookies[i]; } int cnt = 0; for (int i = 0; i < n; ++i) { int cook = sum; cook -= cookies[i]; if (cook % 2 == 0) ++cnt; } cout << cnt; return 0; } void fast() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); }
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#include <bits/stdc++.h> using namespace std; const long long maxn = 200005; struct node { long long ab; long long cab; } a[maxn], b[maxn]; struct mon { long long x, y, z; } mo[maxn]; bool cmpab(struct node ab1, struct node ab2) { return ab1.ab < ab2.ab; } bool cmpm(struct mon mo1, struct mon mo2) { return mo1.x < mo2.x; } struct cmp1 { bool operator()(const node &a, const node &b) const { return a.ab < b.ab; } }; long long trb[4 * maxn + 1] = {0}, trbk[4 * maxn + 1] = {0}; void build(long long k, long long l, long long r, long long l1, long long r1, long long val) { if (l1 <= l && r <= r1) { trbk[k] += val; } else if (!(r < l1 || r1 < l)) { long long m = (l + r) / 2; trbk[k * 2 + 2] += trbk[k], trbk[k * 2 + 1] += trbk[k]; trbk[k] = 0; build(k * 2 + 1, l, m, l1, r1, val); build(k * 2 + 2, m + 1, r, l1, r1, val); trb[k] = max(trb[k * 2 + 1] + trbk[k * 2 + 1], trb[k * 2 + 2] + trbk[k * 2 + 2]); } else { return; } } long long cal(long long k, long long l, long long r, long long l1, long long r1) { if (l1 <= l && r <= r1) { return trb[k] + trbk[k]; } else if (!(r < l1 || r1 < l)) { long long m = (l + r) / 2; trbk[k * 2 + 2] += trbk[k], trbk[k * 2 + 1] += trbk[k]; trbk[k] = 0; trb[k] = max(trb[k * 2 + 1] + trbk[k * 2 + 1], trb[k * 2 + 2] + trbk[k * 2 + 2]); long long ans1 = cal(k * 2 + 1, l, m, l1, r1); long long ans2 = cal(k * 2 + 2, m + 1, r, l1, r1); return max(ans1, ans2); } else { return 0; } } long long bi(long long l, long long r, long long val) { long long m = (l + r) / 2; if (l == r) { return m; } else if (b[m].ab <= val) { return bi(m + 1, r, val); } else { return bi(l, m, val); } } int main(void) { long long n, m, p; scanf( %lld%lld%lld , &n, &m, &p); for (long long i = 0; i < n; i++) { scanf( %lld%lld , &a[i].ab, &a[i].cab); } for (long long i = 0; i < m; i++) { scanf( %lld%lld , &b[i].ab, &b[i].cab); } for (long long i = 0; i < p; i++) { scanf( %lld%lld%lld , &mo[i].x, &mo[i].y, &mo[i].z); } sort(a, a + n, cmpab); sort(b, b + m, cmpab); sort(mo, mo + p, cmpm); long long ma = -a[0].cab - b[0].cab; long long monu = 0; for (long long i = 0; i < m; i++) { build(0, 0, m - 1, i, i, -b[i].cab); } for (long long i = 0; i < n; i++) { while (a[i].ab > mo[monu].x && monu < p) { if (mo[monu].y >= b[m - 1].ab) { monu++; continue; } long long num = bi(0, m - 1, mo[monu].y); build(0, 0, m - 1, num, m - 1, mo[monu].z); monu++; } ma = max(ma, -a[i].cab + cal(0, 0, m - 1, 0, m - 1)); } printf( %lld , ma); }
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#include <bits/stdc++.h> using namespace std; char a; int r, c; bool side(int x) { if (x == 1 or x == 8) return true; return false; } int type(int x, int y) { if (side(x) and side(y)) return 1; if (side(x) or side(y)) return 2; return 3; } int main() { scanf( %c%d , &a, &r); c = a - a + 1; int ty = type(r, c); if (ty == 1) printf( 3 ); else if (ty == 2) printf( 5 ); else printf( 8 ); return 0; }
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#include <bits/stdc++.h> using namespace std; #define int long long int void next(char &x){ if(x<= b ){ x++; }else{ x= a ; } } void solve() { int n,k; cin>>n>>k; char cur= a ; for(int i=0;i<n;i++){ cout<<cur; next(cur); } cout<<endl; } signed main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); int t; cin >> t; while (t--){ solve(); } }
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`default_nettype none
`define WIDTH 16
module j1(
input wire clk,
input wire resetq,
output wire io_rd,
output wire io_wr,
output wire [15:0] mem_addr,
output wire mem_wr,
output wire [`WIDTH-1:0] dout,
input wire [`WIDTH-1:0] io_din,
output wire [12:0] code_addr,
input wire [15:0] insn);
reg [3:0] dsp, dspN; // data stack pointer
reg [`WIDTH-1:0] st0, st0N; // top of data stack
reg dstkW; // data stack write
reg [12:0] pc /* verilator public_flat */, pcN; // program counter
wire [12:0] pc_plus_1 = pc + 13'd1;
reg rstkW; // return stack write
wire [`WIDTH-1:0] rstkD; // return stack write value
reg reboot = 1;
assign mem_addr = st0[15:0];
assign code_addr = pcN;
// The D and R stacks
wire [`WIDTH-1:0] st1, rst0;
reg [1:0] dspI, rspI;
stack2 #(.DEPTH(15)) dstack(.clk(clk), .rd(st1), .we(dstkW), .wd(st0), .delta(dspI));
stack2 #(.DEPTH(17)) rstack(.clk(clk), .rd(rst0), .we(rstkW), .wd(rstkD), .delta(rspI));
wire [16:0] minus = {1'b1, ~st0} + st1 + 1;
wire signedless = st0[15] ^ st1[15] ? st1[15] : minus[16];
always @*
begin
// Compute the new value of st0
casez ({pc[12], insn[15:8]})
9'b1_???_?????: st0N = insn; // literal
9'b0_1??_?????: st0N = { {(`WIDTH - 15){1'b0}}, insn[14:0] }; // literal
9'b0_000_?????: st0N = st0; // jump
9'b0_010_?????: st0N = st0; // call
9'b0_001_?????: st0N = st1; // conditional jump
9'b0_011_?0000: st0N = st0; // ALU operations...
9'b0_011_?0001: st0N = st1;
9'b0_011_?0010: st0N = st0 + st1;
9'b0_011_?0011: st0N = st0 & st1;
9'b0_011_?0100: st0N = st0 | st1;
9'b0_011_?0101: st0N = st0 ^ st1;
9'b0_011_?0110: st0N = ~st0;
9'b0_011_?0111: st0N = {`WIDTH{(minus == 0)}}; // =
9'b0_011_?1000: st0N = {`WIDTH{(signedless)}}; // <
9'b0_011_?1001: st0N = {st0[`WIDTH - 1], st0[`WIDTH - 1:1]};
9'b0_011_?1010: st0N = {st0[`WIDTH - 2:0], 1'b0};
9'b0_011_?1011: st0N = rst0;
9'b0_011_?1100: st0N = minus[15:0];
9'b0_011_?1101: st0N = io_din;
9'b0_011_?1110: st0N = {{(`WIDTH - 4){1'b0}}, dsp};
9'b0_011_?1111: st0N = {`WIDTH{(minus[16])}}; // u<
default: st0N = {`WIDTH{1'bx}};
endcase
end
wire func_T_N = (insn[6:4] == 1);
wire func_T_R = (insn[6:4] == 2);
wire func_write = (insn[6:4] == 3);
wire func_iow = (insn[6:4] == 4);
wire func_ior = (insn[6:4] == 5);
wire is_alu = !pc[12] & (insn[15:13] == 3'b011);
assign mem_wr = !reboot & is_alu & func_write;
assign dout = st1;
assign io_wr = !reboot & is_alu & func_iow;
assign io_rd = !reboot & is_alu & func_ior;
assign rstkD = (insn[13] == 1'b0) ? {{(`WIDTH - 14){1'b0}}, pc_plus_1, 1'b0} : st0;
always @*
begin
casez ({pc[12], insn[15:13]})
4'b1_???,
4'b0_1??: {dstkW, dspI} = {1'b1, 2'b01};
4'b0_001: {dstkW, dspI} = {1'b0, 2'b11};
4'b0_011: {dstkW, dspI} = {func_T_N, {insn[1:0]}};
default: {dstkW, dspI} = {1'b0, 2'b00};
endcase
dspN = dsp + {dspI[1], dspI[1], dspI};
casez ({pc[12], insn[15:13]})
4'b1_???: {rstkW, rspI} = {1'b0, 2'b11};
4'b0_010: {rstkW, rspI} = {1'b1, 2'b01};
4'b0_011: {rstkW, rspI} = {func_T_R, insn[3:2]};
default: {rstkW, rspI} = {1'b0, 2'b00};
endcase
casez ({reboot, pc[12], insn[15:13], insn[7], |st0})
7'b1_0_???_?_?: pcN = 0;
7'b0_0_000_?_?,
7'b0_0_010_?_?,
7'b0_0_001_?_0: pcN = insn[12:0];
7'b0_1_???_?_?,
7'b0_0_011_1_?: pcN = rst0[13:1];
default: pcN = pc_plus_1;
endcase
end
always @(negedge resetq or posedge clk)
begin
if (!resetq) begin
reboot <= 1'b1;
{ pc, dsp, st0} <= 0;
end else begin
reboot <= 0;
{ pc, dsp, st0} <= { pcN, dspN, st0N };
end
end
endmodule
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// megafunction wizard: %ALTDDIO_OUT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altddio_out
// ============================================================
// File Name: ddio_out.v
// Megafunction Name(s):
// altddio_out
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 222 10/21/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ddio_out (
aclr,
datain_h,
datain_l,
outclock,
dataout);
input aclr;
input [3:0] datain_h;
input [3:0] datain_l;
input outclock;
output [3:0] dataout;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [3:0] sub_wire0;
wire [3:0] dataout = sub_wire0[3:0];
altddio_out altddio_out_component (
.outclock (outclock),
.datain_h (datain_h),
.aclr (aclr),
.datain_l (datain_l),
.dataout (sub_wire0),
.aset (1'b0),
.oe (1'b1),
.oe_out (),
.outclocken (1'b1),
.sclr (1'b0),
.sset (1'b0));
defparam
altddio_out_component.extend_oe_disable = "UNUSED",
altddio_out_component.intended_device_family = "Arria II GX",
altddio_out_component.lpm_type = "altddio_out",
altddio_out_component.oe_reg = "UNUSED",
altddio_out_component.width = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ARESET_MODE NUMERIC "0"
// Retrieval info: PRIVATE: CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: OE NUMERIC "0"
// Retrieval info: PRIVATE: OE_REG NUMERIC "0"
// Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
// Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIDTH NUMERIC "4"
// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
// Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
// Retrieval info: CONSTANT: WIDTH NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: datain_h 0 0 4 0 INPUT NODEFVAL datain_h[3..0]
// Retrieval info: USED_PORT: datain_l 0 0 4 0 INPUT NODEFVAL datain_l[3..0]
// Retrieval info: USED_PORT: dataout 0 0 4 0 OUTPUT NODEFVAL dataout[3..0]
// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
// Retrieval info: CONNECT: @datain_h 0 0 4 0 datain_h 0 0 4 0
// Retrieval info: CONNECT: @datain_l 0 0 4 0 datain_l 0 0 4 0
// Retrieval info: CONNECT: dataout 0 0 4 0 @dataout 0 0 4 0
// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
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#include <bits/stdc++.h> using namespace std; char opt; long long a, b, c, ansa, ansb, ansc, anslen = 15; void dfs(long long a, long long b, long long c, long long nowa, long long nowb, int pre, long long len, long long step) { if (len >= anslen) return; if (!a && !b && !c && !pre) { ansa = nowa, ansb = nowb, anslen = len; return; } if (!c) { long long tmp = a + b + pre; int cnt = 0; while (tmp) cnt++, tmp /= 10; dfs(0, 0, 0, nowa + step * a, nowb + step * b, 0, len + cnt, step); return; } if ((a + b + pre) % 10 == c % 10) { dfs(a / 10, b / 10, c / 10, nowa + step * (a % 10), nowb + step * (b % 10), (a % 10 + b % 10 + pre) / 10, len, step * 10); return; } dfs(a * 10 + (c + 10 - b % 10 - pre) % 10, b, c, nowa, nowb, pre, len + 1, step); dfs(a, b * 10 + (c + 10 - a % 10 - pre) % 10, c, nowa, nowb, pre, len + 1, step); dfs(a, b, c * 10 + (a + b + pre) % 10, nowa, nowb, pre, len + 1, step); } int main() { cin >> a >> opt >> b >> opt >> c; dfs(a, b, c, 0, 0, 0, 0, 1); cout << ansa << + << ansb << = << ansa + ansb << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; const int MAX_N = 200000; struct el { int l, r, id; } a[MAX_N], b[MAX_N]; long k[MAX_N]; class compare { public: bool operator()(el a, el b) { return a.r < b.r; } }; int main() { int n, m; cin >> n; for (int i = 0; i < n; i++) { cin >> a[i].l >> a[i].r; a[i].id = i; } cin >> m; for (int i = 0; i < m; i++) { cin >> b[i].l >> b[i].r >> k[i]; b[i].id = i; } compare cmp; sort(a, a + n, cmp); sort(b, b + m, cmp); int uk = 0; vector<int> ans(n); multimap<int, int> mp; for (int i = 0; i < m; i++) { while (uk < n && a[uk].r <= b[i].r) mp.insert(make_pair(a[uk].l, a[uk].id)), uk++; map<int, int>::iterator it; for (it = mp.lower_bound(b[i].l); it != mp.end() && k[b[i].id]; it = mp.lower_bound(b[i].l)) { ans[it->second] = b[i].id + 1; k[b[i].id]--; mp.erase(it); } } if (mp.empty() && uk == n) { cout << YES n ; copy(ans.begin(), ans.end(), ostream_iterator<int>(cout, )); } else cout << NO ; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, a, b, x, y, flag = 0; cin >> n >> a >> x >> b >> y; int in = 0; for (int i = 0; i < n; i++) { a = a % n + 1; b = b - 1; if (b == 0) b = n; if (a == b) { cout << YES ; flag = 1; break; } if (a == x or b == y) break; } if (flag == 0) cout << NO ; return 0; }
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#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; template <class T> inline bool chmin(T& a, T b) { if (a > b) { a = b; return true; } return false; } template <class T> inline bool chmax(T& a, T b) { if (a < b) { a = b; return true; } return false; } const int MOD = 1000000007; const int INF = 1000000001; const ll LINF = 1000000001000000001LL; void solve(); int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout << fixed << setprecision(numeric_limits<double>::max_digits10); solve(); return 0; } void solve() { int t; cin >> t; while (t--) { int n, m; cin >> n >> m; vector<int> a(n); for (int i = (0); i < ((n)); i++) cin >> a[i]; vector<int> b(n, false); int p; for (int i = (0); i < ((m)); i++) { cin >> p; p--; b[p] = true; } bool ok = true; for (int i = (0); i < ((n)); i++) { for (int j = (i); j < (n); j++) { if (!b[j]) { for (int k = (j + 1); k < (n); k++) { if (a[i] > a[k]) { ok = false; break; } } if (!ok) break; } } if (!ok) break; for (int j = (i - 1); j < (0); j++) { if (!b[j]) { for (int k = (0); k < ((j + 1)); k++) { if (a[i] < a[k]) { ok = false; break; } } if (!ok) break; } } if (!ok) break; } cout << (ok ? YES : NO ) << n ; } }
|
#include <bits/stdc++.h> using namespace std; int R; vector<int> hv, use; vector<char> ans; int req[1000005]; int fr[1000005]; int main() { int n; scanf( %d , &n); if (n >= 1389) R = 4; else if (n >= 232) R = 3; else if (n >= 199) R = 2; else if (n >= 2) R = 1; else { printf( a a n ); return 0; } for (int i = 0; i < R; i++) hv.push_back(0); hv.push_back(1); for (int i = R + 1;; i++) { hv.push_back(hv.back() * i / (i - R)); if (hv.back() > n) break; } for (int &u : hv) u--; for (int i = 0; i < 2 * R; i++) hv[i] = 0; for (int i = 1; i <= n; i++) req[i] = 10000005; for (int i = 0; i <= n; i++) fr[i] = -1; for (int i = 1; i <= n; i++) for (unsigned j = 0; j < hv.size(); j++) if (hv[j] <= i) { if (req[i - hv[j]] + j < req[i]) { req[i] = req[i - hv[j]] + j; fr[i] = j; } } else break; n--; for (int i = n; i; i -= hv[fr[i]]) use.push_back(fr[i]); for (unsigned i = 0; i < use.size(); i++) for (int j = 0; j < R; j++) printf( %c , a + i); for (int i = use.size() - 1; i >= 0; i--) for (int j = 2 * R; j < use[i]; j++) printf( %c , a + i); for (unsigned i = 0; i < use.size(); i++) for (int j = 0; j < R; j++) printf( %c , a + i); printf( ); for (unsigned i = 0; i < use.size(); i++) for (int j = 0; j < R; j++) printf( %c , a + i); printf( n ); return 0; }
|
module encoder(in,out);
input [39:0] in;
output [5:0] out;
assign out = (in[0]==1'b1)?6'd0:
(in[1]==1'b1)?6'd1:
(in[2]==1'b1)?6'd2:
(in[3]==1'b1)?6'd3:
(in[4]==1'b1)?6'd4:
(in[5]==1'b1)?6'd5:
(in[6]==1'b1)?6'd6:
(in[7]==1'b1)?6'd7:
(in[8]==1'b1)?6'd8:
(in[9]==1'b1)?6'd9:
(in[10]==1'b1)?6'd10:
(in[11]==1'b1)?6'd11:
(in[12]==1'b1)?6'd12:
(in[13]==1'b1)?6'd13:
(in[14]==1'b1)?6'd14:
(in[15]==1'b1)?6'd15:
(in[16]==1'b1)?6'd16:
(in[17]==1'b1)?6'd17:
(in[18]==1'b1)?6'd18:
(in[19]==1'b1)?6'd19:
(in[20]==1'b1)?6'd20:
(in[21]==1'b1)?6'd21:
(in[22]==1'b1)?6'd22:
(in[23]==1'b1)?6'd23:
(in[24]==1'b1)?6'd24:
(in[25]==1'b1)?6'd25:
(in[26]==1'b1)?6'd26:
(in[27]==1'b1)?6'd27:
(in[28]==1'b1)?6'd28:
(in[29]==1'b1)?6'd29:
(in[30]==1'b1)?6'd30:
(in[31]==1'b1)?6'd31:
(in[32]==1'b1)?6'd32:
(in[33]==1'b1)?6'd33:
(in[34]==1'b1)?6'd34:
(in[35]==1'b1)?6'd35:
(in[36]==1'b1)?6'd36:
(in[37]==1'b1)?6'd37:
(in[38]==1'b1)?6'd38:
(in[39]==1'b1)?6'd39:
6'b000000;
endmodule
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-8; int i, j, k, l, n, m, K[120], tmp, flag, bo; struct point { int x, y; } a[120]; struct ppp { double x, y; } O; double ans; int dot(point &a, point &b, point &c, point &d) { return (b.x - a.x) * (d.x - c.x) + (b.y - a.y) * (d.y - c.y); } double dist(ppp &a, point &b) { return sqrt((b.x - a.x) * (b.x - a.x) + (b.y - a.y) * (b.y - a.y)); } void calc(double a, double b, double c, double d, double e, double f) { O.y = (a * f - d * c) / (b * d - e * a); O.x = (b * f - c * e) / (a * e - b * d); } bool Find(int x, int y) { for (int i = 1; i <= n; ++i) if (a[i].x == x && a[i].y == y) return 1; return 0; } int main() { scanf( %d , &n); for (i = 1; i <= n; ++i) scanf( %d%d , &a[i].x, &a[i].y); for (i = 1; i <= n; ++i) K[i] = a[i].x * a[i].x + a[i].y * a[i].y; for (i = 1; i <= n; ++i) for (j = i + 1; j <= n; ++j) for (k = j + 1; k <= n; ++k) { tmp = dot(a[i], a[j], a[i], a[k]); bo = 0; if (tmp < 0 || tmp == 0 && !Find(a[j].x + a[k].x - a[i].x, a[j].y + a[k].y - a[i].y)) continue; if (tmp == 0) bo = 1, O.x = (a[j].x + a[k].x) / 2.0, O.y = (a[j].y + a[k].y) / 2.0; tmp = dot(a[j], a[i], a[j], a[k]); if (tmp < 0 || tmp == 0 && !Find(a[i].x + a[k].x - a[j].x, a[i].y + a[k].y - a[j].y)) continue; if (tmp == 0) bo = 1, O.x = (a[i].x + a[k].x) / 2.0, O.y = (a[i].y + a[k].y) / 2.0; tmp = dot(a[k], a[i], a[k], a[j]); if (tmp < 0 || tmp == 0 && !Find(a[i].x + a[j].x - a[k].x, a[i].y + a[j].y - a[k].y)) continue; if (tmp == 0) bo = 1, O.x = (a[i].x + a[j].x) / 2.0, O.y = (a[i].y + a[j].y) / 2.0; if (!bo) calc(a[j].x - a[i].x, a[j].y - a[i].y, (K[i] - K[j]) / 2.0, a[k].x - a[i].x, a[k].y - a[i].y, (K[i] - K[k]) / 2.0); double R = dist(O, a[i]); for (l = 1; l <= n; ++l) if (l != i && l != j && l != k && dist(O, a[l]) + eps < R) break; if (l <= n) continue; ans = max(ans, R); flag = 1; } if (!flag) printf( -1 n ); else printf( %.6lf n , ans); }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// raminfr.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// Inferrable Distributed RAM for FIFOs ////
//// ////
//// Known problems (limits): ////
//// None . ////
//// ////
//// To Do: ////
//// Nothing so far. ////
//// ////
//// Author(s): ////
//// - ////
//// - Jacob Gorban ////
//// ////
//// Created: 2002/07/22 ////
//// Last Updated: 2002/07/22 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: raminfr.v,v $
// Revision 1.2 2002/07/29 21:16:18 gorban
// The uart_defines.v file is included again in sources.
//
// Revision 1.1 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
//Following is the Verilog code for a dual-port RAM with asynchronous read.
module raminfr
(clk, we, a, dpra, di, dpo);
parameter addr_width = 4;
parameter data_width = 8;
parameter depth = 16;
input clk;
input we;
input [addr_width-1:0] a;
input [addr_width-1:0] dpra;
input [data_width-1:0] di;
//output [data_width-1:0] spo;
output [data_width-1:0] dpo;
reg [data_width-1:0] ram [depth-1:0];
wire [data_width-1:0] dpo;
wire [data_width-1:0] di;
wire [addr_width-1:0] a;
wire [addr_width-1:0] dpra;
always @(posedge clk) begin
if (we)
ram[a] <= di;
end
// assign spo = ram[a];
assign dpo = ram[dpra];
endmodule
|
#include <bits/stdc++.h> using namespace std; int P; int g1() { double p = rand() / 32767.0, s = 0, g = 1; for (int k = 0;; k++) { if (k) g *= k; double c = pow(P, k) * exp(-P) / g; s += c; if (p <= s) return k; } } int g2() { double p = rand() / 32767.0, s = 0; for (int k = 0; k <= P + P; k++) { s += 1.0 / (2 * P + 1); if (p <= s) return k; } return P + P; } int main() { int v; scanf( %d , &v); while (v--) { vector<int> vs; for (int i = 0; i < 250; i++) { int x; scanf( %d , &x); vs.push_back(x); } double avr = 0, ss = 0; for (int i = 0; i < 250; i++) avr += (double)vs[i]; avr /= 250; int mx = 0; for (int i = 0; i < 250; i++) ss += (vs[i] - avr) * (vs[i] - avr), mx = max(mx, vs[i]); ss /= avr; if (ss < 500) printf( %d n , int(avr + 0.5)); else printf( %d n , int(mx / 2.0 + 0.5)); } }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
reg [31:0] sum;
wire [15:0] out0;
wire [15:0] out1;
wire [15:0] inData = crc[15:0];
wire wr0a = crc[16];
wire wr0b = crc[17];
wire wr1a = crc[18];
wire wr1b = crc[19];
fifo fifo (
// Outputs
.out0 (out0[15:0]),
.out1 (out1[15:0]),
// Inputs
.clk (clk),
.wr0a (wr0a),
.wr0b (wr0b),
.wr1a (wr1a),
.wr1b (wr1b),
.inData (inData[15:0]));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%x q=%x\n",$time, cyc, crc, sum);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 32'h0;
end
else if (cyc>10 && cyc<90) begin
sum <= {sum[30:0],sum[31]} ^ {out1, out0};
end
else if (cyc==99) begin
if (sum !== 32'he8bbd130) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module fifo (/*AUTOARG*/
// Outputs
out0, out1,
// Inputs
clk, wr0a, wr0b, wr1a, wr1b, inData
);
input clk;
input wr0a;
input wr0b;
input wr1a;
input wr1b;
input [15:0] inData;
output [15:0] out0;
output [15:0] out1;
reg [15:0] mem [1:0];
reg [15:0] memtemp2 [1:0];
reg [15:0] memtemp3 [1:0];
assign out0 = {mem[0] ^ memtemp2[0]};
assign out1 = {mem[1] ^ memtemp3[1]};
always @(posedge clk) begin
// These mem assignments must be done in order after processing
if (wr0a) begin
memtemp2[0] <= inData;
mem[0] <= inData;
end
if (wr0b) begin
memtemp3[0] <= inData;
mem[0] <= ~inData;
end
if (wr1a) begin
memtemp3[1] <= inData;
mem[1] <= inData;
end
if (wr1b) begin
memtemp2[1] <= inData;
mem[1] <= ~inData;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int mmax, sum, n, t; int main() { cin >> n; sum = 0; mmax = 0; for (int i = 0; i < n; i++) { cin >> t; sum += t; mmax = max(t, mmax); } cout << mmax - (sum - mmax) + 1; }
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ebi
//
// Generated
// by: wig
// on: Fri Jul 7 06:44:20 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../bugver.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ebi.v,v 1.2 2006/07/10 07:30:09 wig Exp $
// $Date: 2006/07/10 07:30:09 $
// $Log: ebi.v,v $
// Revision 1.2 2006/07/10 07:30:09 wig
// Updated more testcasess.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ebi
//
// No user `defines in this module
module ebi
//
// Generated Module ebi_i
//
(
cs2_o, // EBI bug missing generated port
cs3_o, // EBI bug, worked because only one step
open_t, // Merge open port 2Merge open port 1Merge open port 0
open_tbs // open bus port
);
// Generated Module Outputs:
output cs2_o;
output cs3_o;
output [2:0] open_t;
output [2:0] open_tbs;
// Generated Wires:
wire cs2_o;
wire cs3_o;
wire [2:0] open_t;
wire [2:0] open_tbs;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of ebi
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDLCLKP_1_V
`define SKY130_FD_SC_HS__SDLCLKP_1_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog wrapper for sdlclkp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sdlclkp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdlclkp_1 (
GCLK,
GATE,
CLK ,
SCE ,
VPWR,
VGND
);
output GCLK;
input GATE;
input CLK ;
input SCE ;
input VPWR;
input VGND;
sky130_fd_sc_hs__sdlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK(CLK),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdlclkp_1 (
GCLK,
GATE,
CLK ,
SCE
);
output GCLK;
input GATE;
input CLK ;
input SCE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__sdlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK(CLK),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDLCLKP_1_V
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
//////////////////////////////////////////////////////////////////////////////////
// Company: Microsoft Research Asia
// Engineer: Jiansong Zhang
//
// Create Date: 21:39:39 06/01/2009
// Design Name:
// Module Name: tx_engine
// Project Name: Sora
// Target Devices: Virtex5 LX50T
// Tool versions: ISE10.1.03
// Description:
// Purpose: Contains 25 ms timers for each outstanding read request. If any
// timer reaches 0 than completion timeout is signalled.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module completion_timeout(
input clk,
input rst,
input [31:0] pending_req,
output reg comp_timeout
);
`ifdef ML505
reg [15:0] count;
`else
reg [17:0] count; //free running counter creates 1.048576 ms timer
`endif
wire [31:0] pending_req_rise;
wire [31:0] pending_req_fall;
reg [31:0] shift_in = 0;
reg [4:0] reset_count[31:0];
wire [31:0] srl_reset;
wire [31:0] comp_timeout_vector;
reg [31:0] comp_timeout_vector_d1;
wire comp_timeout_or;
wire comp_timeout_one;
reg comp_timeout_d1;
always@(posedge clk)begin
if(rst)
count <= 0;
else
count <= count + 1;
end
//timer is asserted every 1.045876 ms
assign timer = (count == 0) ? 1'b1 : 1'b0;
//create 32 shift register instances and associated logic
genvar i;
generate
for(i=0;i<32;i=i+1)begin: replicate
edge_detect edge_detect_inst(
.clk(clk),
.rst(rst),
.in(pending_req[i]),
.rise_out(pending_req_rise[i]),
.fall_out(pending_req_fall[i])
);
//pending req logic
//create a signal that sets when pending req is high and resets
//timer pulses. Pending req gets priority over timer if both
//signals occur simultaneously
always@(posedge clk)begin
if(pending_req_rise[i]) //set latch
shift_in[i] <= 1'b1;
else if(timer || pending_req_fall[i]) //reset latch
shift_in[i] <= 1'b0;
end
always@(posedge clk)begin
if(rst)
reset_count[i][4:0] <= 5'b00000;
else if (pending_req_fall[i] == 1'b1)
reset_count[i][4:0] <= 5'b11001;
else if (reset_count[i][4:0] == 5'b00000)
reset_count[i][4:0] <= 5'b00000;
else
reset_count[i][4:0] <= reset_count[i][4:0] - 1;
end
assign srl_reset[i] = | reset_count[i][4:0];
SRLC32E #(
.INIT(32'h00000000)
) SRLC32E_inst (
.Q(comp_timeout_vector[i]), // SRL data output
.Q31(), // SRL cascade output pin
.A(5'b11000), // 5-bit shift depth select input
.CE((srl_reset[i]) ? srl_reset[i] : timer), // Clock enable input
.CLK(clk), // Clock input
.D((srl_reset[i]) ? ~srl_reset[i] : shift_in[i]) // SRL data input
);
end
endgenerate
always@(posedge clk)begin
comp_timeout_vector_d1[31:0] <= comp_timeout_vector[31:0];
end
assign comp_timeout_or = |comp_timeout_vector_d1[31:0];
rising_edge_detect comp_timeout_one_inst(
.clk(clk),
.rst(rst),
.in(comp_timeout_or),
.one_shot_out(comp_timeout_one)
);
always@(posedge clk)begin
comp_timeout_d1 <= comp_timeout_one;
comp_timeout <= comp_timeout_d1;
end
endmodule
|
#include <bits/stdc++.h> int main() { int p[105]; int n, m, i, j, t; memset(p, 0, sizeof(p)); scanf( %d%d , &n, &m); for (i = 0; i < m; i++) { scanf( %d , &t); for (j = t; p[j] == 0; j++) p[j] = t; } for (i = 1; i < n; i++) printf( %d , p[i]); printf( %d n , p[n]); return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [3:0] l_stop = crc[3:0];
wire [3:0] l_break = crc[7:4];
wire [3:0] l_continue = crc[11:8];
/*AUTOWIRE*/
wire [15:0] out0 = Test0(l_stop, l_break, l_continue);
wire [15:0] out1 = Test1(l_stop, l_break, l_continue);
wire [15:0] out2 = Test2(l_stop, l_break, l_continue);
wire [15:0] out3 = Test3(l_stop, l_break, l_continue);
// Aggregate outputs into a single result vector
wire [63:0] result = {out3,out2,out1,out0};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
if (out0!==out1) $stop;
if (out0!==out2) $stop;
if (out0!==out3) $stop;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h293e9f9798e97da0
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
function [15:0] Test0;
input [3:0] loop_stop;
input [3:0] loop_break;
input [3:0] loop_continue;
integer i;
reg broken;
Test0 = 0;
broken = 0;
begin
for (i=1; i<20; i=i+1) begin
if (!broken) begin
Test0 = Test0 + 1;
if (i[3:0] != loop_continue) begin // continue
if (i[3:0] == loop_break) begin
broken = 1'b1;
end
if (!broken) begin
Test0 = Test0 + i[15:0];
end
end
end
end
end
endfunction
function [15:0] Test1;
input [3:0] loop_stop;
input [3:0] loop_break;
input [3:0] loop_continue;
integer i;
Test1 = 0;
begin : outer_block
for (i=1; i<20; i=i+1) begin : inner_block
Test1 = Test1 + 1;
// continue, IE jump to end-of-inner_block. Must be inside inner_block.
if (i[3:0] == loop_continue) disable inner_block;
// break, IE jump to end-of-outer_block. Must be inside outer_block.
if (i[3:0] == loop_break) disable outer_block;
Test1 = Test1 + i[15:0];
end : inner_block
end : outer_block
endfunction
function [15:0] Test2;
input [3:0] loop_stop;
input [3:0] loop_break;
input [3:0] loop_continue;
integer i;
Test2 = 0;
begin
for (i=1; i<20; i=i+1) begin
Test2 = Test2 + 1;
if (i[3:0] == loop_continue) continue;
if (i[3:0] == loop_break) break;
Test2 = Test2 + i[15:0];
end
end
endfunction
function [15:0] Test3;
input [3:0] loop_stop;
input [3:0] loop_break;
input [3:0] loop_continue;
integer i;
Test3 = 0;
begin
for (i=1; i<20; i=i+1) begin
Test3 = Test3 + 1;
if (i[3:0] == loop_continue) continue;
// return, IE jump to end-of-function optionally setting return value
if (i[3:0] == loop_break) return Test3;
Test3 = Test3 + i[15:0];
end
end
endfunction
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 5; const int INF = 0x3f3f3f3f; int dp[N]; struct node { int v, id; } a[N][2]; void up1(int sta, int cost, int i) { if (a[sta][0].v > cost) { a[sta][1] = a[sta][0]; a[sta][0] = {cost, i}; } else if (a[sta][1].v > cost) { a[sta][1] = {cost, i}; } } int num = -1, now, cs; pair<int, int> ans; void up2(node x, node y, int sta) { if (x.v == INF || y.v == INF) return; now = x.v + y.v; if (dp[sta] > num || (dp[sta] == num && cs > now)) { num = dp[sta]; cs = now; ans = {x.id, y.id}; } } int main() { int k, n, m, sta, v, cost; scanf( %d %d , &n, &m); for (int i = 1; i <= n; i++) { scanf( %d , &k); sta = 0; for (int j = 1; j <= k; j++) { scanf( %d , &v); sta |= 1 << (v - 1); } dp[sta]++; } int mx = 0; for (int i = 0; i < 9; i++) { for (int j = (1 << 9) - 1; j >= 0; j--) { if ((1 << i) & j) dp[j] = dp[j] + dp[j ^ (1 << i)]; mx = max(mx, dp[j]); } } for (int j = 0; j < (1 << 9); j++) a[j][0].v = a[j][1].v = INF; for (int i = 1; i <= m; i++) { scanf( %d %d , &cost, &k); sta = 0; for (int j = 1; j <= k; j++) { scanf( %d , &v); sta |= 1 << (v - 1); } up1(sta, cost, i); } for (int i = 0; i < (1 << 9); i++) { for (int j = 0; j < (1 << 9); j++) { if (i == j) up2(a[i][0], a[i][1], i); else up2(a[i][0], a[j][0], i | j); } } printf( %d %d n , ans.first, ans.second); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, V, i, x, y, z, tot, e[505], fir[505], ne[505 * 2], la[505 * 2], va[505 * 2]; double v, o, a[505][505], b[505], c[505]; void ins(int x, int y, int z) { la[++tot] = y; ne[tot] = fir[x]; fir[x] = tot; va[tot] = z; } void dfs(int A, int x, int fa, long long z) { if (z <= V) a[x][A] = 1; for (int i = fir[x]; i; i = ne[i]) if (la[i] != fa) dfs(A, la[i], x, z + va[i]); } void pivot(int l, int e) { int i, j; for (a[l][e] = 1 / a[l][e], b[l] *= a[l][e], i = 1; i <= n; i++) if (i != e) a[l][i] *= a[l][e]; for (i = 1; i <= m; i++) if (i != l && fabs(a[i][e]) > 1e-7) { for (b[i] -= a[i][e] * b[l], j = 1; j <= n; j++) if (j != e) a[i][j] -= a[i][e] * a[l][j]; a[i][e] *= -a[l][e]; } for (v += c[e] * b[l], i = 1; i <= n; i++) if (i != e) c[i] -= c[e] * a[l][i]; c[e] *= -a[l][e]; } double simplex() { for (int i, j, e, l; 1;) { for (i = 1; i <= n; i++) if (c[i] > 1e-7) break; if ((e = i) == n + 1) return v; double tmp = 1e99; for (i = 1; i <= m; i++) if (a[i][e] > 1e-7 && tmp > b[i] / a[i][e]) tmp = b[i] / a[i][e], l = i; if (tmp == 1e99) break; pivot(l, e); } return 1e99; } int main() { for (scanf( %d%d , &n, &V), i = 1; i <= n; i++) scanf( %d , &e[i]), b[i] = !e[i], a[i][n + 1] = 1, a[i][n + 2] = -1, c[n + 1] += e[i], c[n + 2] -= e[i], c[i] = 1; for (i = 1; i < n; i++) scanf( %d%d%d , &x, &y, &z), ins(x, y, z), ins(y, x, z); for (i = 1; i <= n; i++) dfs(i, i, 0, 0); m = n; n += 2; o = simplex(); if (o == 1e99) puts( -1 ); else printf( %.0lf , o); }
|
#include <bits/stdc++.h> using namespace std; const long long int N = 1e9 + 7; long long int h[200009], a[200009]; int main() { long long int n, m, i, b, j, c, d, x, y, z, k, sum = 0, l, r = 1; vector<long long int> v; vector<long long int>::iterator it; cin >> n; cout << (n / 2) + 1; }
|
#include <bits/stdc++.h> using namespace std; double EPS = 1e-11; double a[4]; double p[4][2] = {{-1, -1}, {1, -1}, {-1, 1}, {1, 1}}; bool poss(double thr) { double min03 = numeric_limits<double>::infinity(); double max03 = -numeric_limits<double>::infinity(); double min12 = numeric_limits<double>::infinity(); double max12 = -numeric_limits<double>::infinity(); for (int i = 0; i < 4; i++) { min03 = min(min03, (a[0] + thr * p[i][0]) * (a[3] + thr * p[i][1])); min12 = min(min12, (a[1] + thr * p[i][0]) * (a[2] + thr * p[i][1])); max03 = max(max03, (a[0] + thr * p[i][0]) * (a[3] + thr * p[i][1])); max12 = max(max12, (a[1] + thr * p[i][0]) * (a[2] + thr * p[i][1])); } return !(max03 < min12 || max12 < min03); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); for (int i = 0; i < 4; i++) cin >> a[i]; double lo = 0, hi = 1e9; for (int i = 0; i < 10000; i++) { const double mid = (lo + hi) / 2; if (poss(mid)) hi = mid; else lo = mid; } cout << setprecision(20) << lo << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; struct Query { int id, left, right, time, blockLeft, blockRight; Query() : id(-1), left(-1), right(-1), time(-1), blockLeft(-1), blockRight(-1) {} Query(int id, int left, int right, int time, int blockLeft, int blockRight) : id(id), left(left), right(right), time(time), blockLeft(blockLeft), blockRight(blockRight) {} bool operator<(const Query &otherQuery) const { if (blockLeft != otherQuery.blockLeft) { return blockLeft < otherQuery.blockLeft; } if (blockRight != otherQuery.blockRight) { return blockRight < otherQuery.blockRight; } return time < otherQuery.time; } }; struct Operation { int pos, oldValue, newValue; Operation() : pos(-1), oldValue(-1), newValue(-1) {} Operation(int pos, int oldValue, int newValue) : pos(pos), oldValue(oldValue), newValue(newValue) {} }; void del(int value, int *cnts, int *saveValues) { if (cnts[value] > 0) saveValues[cnts[value]]--; cnts[value]--; if (cnts[value] > 0) saveValues[cnts[value]]++; } void add(int value, int *cnts, int *saveValues) { if (cnts[value] > 0) saveValues[cnts[value]]--; cnts[value]++; if (cnts[value] > 0) saveValues[cnts[value]]++; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, q; cin >> n >> q; int sqrtValue = pow(n, 2.0 / 3.0), *values = new int[n + 1], *tmpValues = new int[n + 1]; if (sqrtValue == 0) sqrtValue = 1; vector<int> disValues; for (int i = 1; i <= n; i++) { cin >> values[i]; tmpValues[i] = values[i]; disValues.push_back(values[i]); } Query *querys = new Query[q + 1]; Operation *opts = new Operation[q + 1]; int cntQuerys = 0, cntOpts = 0; for (int i = 1; i <= q; i++) { int opt; cin >> opt; if (opt == 1) { int left, right; cin >> left >> right; ++cntQuerys; querys[cntQuerys] = Query(cntQuerys, left, right, cntOpts, left / sqrtValue, right / sqrtValue); } else { int pos, value; cin >> pos >> value; ++cntOpts; opts[cntOpts] = Operation(pos, tmpValues[pos], value); tmpValues[pos] = value; disValues.push_back(value); } } sort(disValues.begin(), disValues.end()); disValues.resize(unique(disValues.begin(), disValues.end()) - disValues.begin()); for (int i = 1; i <= cntOpts; i++) { Operation &tmpOpt = opts[i]; tmpOpt.oldValue = lower_bound(disValues.begin(), disValues.end(), tmpOpt.oldValue) - disValues.begin(); tmpOpt.newValue = lower_bound(disValues.begin(), disValues.end(), tmpOpt.newValue) - disValues.begin(); } for (int i = 1; i <= n; i++) { values[i] = lower_bound(disValues.begin(), disValues.end(), values[i]) - disValues.begin(); } int valueSize = static_cast<int>(disValues.size()), *cnts = new int[valueSize + 3], *saveValues = new int[n + 2]; memset(cnts, 0, sizeof(int) * (valueSize + 3)); memset(saveValues, 0, sizeof(int) * (n + 2)); int *results = new int[cntQuerys + 1]; sort(querys + 1, querys + cntQuerys + 1); int l = 1, r = 0, time = 0; for (int i = 1; i <= cntQuerys; i++) { Query &tmpQuery = querys[i]; while (l > tmpQuery.left) { l--; add(values[l], cnts, saveValues); } while (l < tmpQuery.left) { del(values[l], cnts, saveValues); l++; } while (r > tmpQuery.right) { del(values[r], cnts, saveValues); r--; } while (r < tmpQuery.right) { r++; add(values[r], cnts, saveValues); } while (time < tmpQuery.time) { time++; Operation &tmpOpt = opts[time]; if (tmpOpt.pos >= l && tmpOpt.pos <= r) { del(tmpOpt.oldValue, cnts, saveValues); add(tmpOpt.newValue, cnts, saveValues); } values[tmpOpt.pos] = tmpOpt.newValue; } while (time > tmpQuery.time) { Operation &tmpOpt = opts[time]; if (tmpOpt.pos >= l && tmpOpt.pos <= r) { del(tmpOpt.newValue, cnts, saveValues); add(tmpOpt.oldValue, cnts, saveValues); } values[tmpOpt.pos] = tmpOpt.oldValue; time--; } for (int i = 1;; i++) { if (i > n) { results[tmpQuery.id] = 0; } if (saveValues[i] == 0) { results[tmpQuery.id] = i; break; } } } for (int i = 1; i <= cntQuerys; i++) { cout << results[i] << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; string t(int a) { int i, tmp = 1; for (i = 1; i <= a; i *= 3) { } string s; for (; i >= 1; i /= 3) { if (a / i == 2) s += 2 , a %= i; else if (a / i == 1) s += 1 , a %= i; else s += 0 ; } return s; } int main() { int i, a, b = 0, c; cin >> a >> c; string s1, s2, s3; s1 = t(a), s2 = t(c); int t = max(((int)s1.size()), ((int)s2.size())); for (i = 0; i < t; i++) { if (((int)s1.size()) - t + i >= 0) a = s1[((int)s1.size()) - t + i] - 0 ; else a = 0; if (((int)s2.size()) - t + i >= 0) c = s2[((int)s2.size()) - t + i] - 0 ; else c = 0; s3 += ((c - a + 3) % 3 + 0 ); } reverse(s3.begin(), s3.end()); for (i = 0; i < ((int)s3.size()); i++) { t = 1; for (int j = 0; j < i; j++) t *= 3; b += (s3[i] - 0 ) * t; } cout << b << endl; }
|
#include <bits/stdc++.h> using namespace std; template <class T, class U> inline T max(T &a, U &b) { return a > b ? a : b; } template <class T, class U> inline T min(T &a, U &b) { return a < b ? a : b; } template <class T> T gcd(T a, T b) { return (b != 0 ? gcd<T>(b, a % b) : a); } template <class T> T lcm(T a, T b) { return (a / gcd<T>(a, b) * b); } class CLASS_NAME { public: int method_NAME() {} }; int main() { int n; string a, b; cin >> n; for (__typeof(0) i = 0; i <= n - 1; i++) a.push_back( 0 ); for (__typeof(0) i = 0; i <= n - 1; i++) b.push_back( 0 ); int k = n / 2; for (__typeof(0) i = 0; i <= k - 1; i++) { a[i] = 1 ; b[i] = 1 ; } vector<int> v, arra, arrb; for (__typeof(0) i = 0; i <= n - 1; i++) { int x, y; cin >> x >> y; arra.push_back(x); arrb.push_back(y); v.push_back(x); v.push_back(y); } sort(v.begin(), v.end()); int tmp = v[n - 1]; for (__typeof(0) i = 0; i <= n - 1; i++) { if (arra[i] <= tmp) a[i] = 1 ; if (arrb[i] <= tmp) b[i] = 1 ; } cout << a << endl << b << endl; return 0; }
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: wdata_router.v
//
// Description:
// Contains SI-side write command queue.
// Target MI-slot index is pushed onto queue when S_AVALID transfer is received.
// Queue is popped when WLAST data beat is transferred.
// W-channel input is transferred to MI-slot output selected by queue output.
//--------------------------------------------------------------------------
//
// Structure:
// wdata_router
// axic_reg_srl_fifo
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_wdata_router #
(
parameter C_FAMILY = "none", // FPGA Family.
parameter integer C_WMESG_WIDTH = 1, // Width of all data signals
parameter integer C_NUM_MASTER_SLOTS = 1, // Number of M_* ports.
parameter integer C_SELECT_WIDTH = 1, // Width of S_ASELECT.
parameter integer C_FIFO_DEPTH_LOG = 0 // Queue depth = 2**C_FIFO_DEPTH_LOG.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave Data Ports
input wire [C_WMESG_WIDTH-1:0] S_WMESG,
input wire S_WLAST,
input wire S_WVALID,
output wire S_WREADY,
// Master Data Ports
output wire [C_WMESG_WIDTH-1:0] M_WMESG, // Broadcast to all MI-slots
output wire M_WLAST, // Broadcast to all MI-slots
output wire [C_NUM_MASTER_SLOTS-1:0] M_WVALID, // Per MI-slot
input wire [C_NUM_MASTER_SLOTS-1:0] M_WREADY, // Per MI-slot
// Address Arbiter Ports
input wire [C_SELECT_WIDTH-1:0] S_ASELECT, // Target MI-slot index from SI-side AW command
input wire S_AVALID,
output wire S_AREADY
);
localparam integer P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG <= 5) ? C_FIFO_DEPTH_LOG : 5; // Max depth = 32
// Decode select input to 1-hot
function [C_NUM_MASTER_SLOTS-1:0] f_decoder (
input [C_SELECT_WIDTH-1:0] sel
);
integer i;
begin
for (i=0; i<C_NUM_MASTER_SLOTS; i=i+1) begin
f_decoder[i] = (sel == i);
end
end
endfunction
//---------------------------------------------------------------------------
// Internal signal declarations
//---------------------------------------------------------------------------
wire [C_NUM_MASTER_SLOTS-1:0] m_select_hot;
wire [C_SELECT_WIDTH-1:0] m_select_enc;
wire m_avalid;
wire m_aready;
//---------------------------------------------------------------------------
// Router
//---------------------------------------------------------------------------
// SI-side write command queue
axi_data_fifo_v2_1_axic_reg_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (C_SELECT_WIDTH),
.C_FIFO_DEPTH_LOG (P_FIFO_DEPTH_LOG),
.C_USE_FULL (1)
)
wrouter_aw_fifo
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (S_ASELECT),
.S_VALID (S_AVALID),
.S_READY (S_AREADY),
.M_MESG (m_select_enc),
.M_VALID (m_avalid),
.M_READY (m_aready)
);
assign m_select_hot = f_decoder(m_select_enc);
// W-channel payload and LAST are broadcast to all MI-slot's W-mux
assign M_WMESG = S_WMESG;
assign M_WLAST = S_WLAST;
// Assert m_aready when last beat acknowledged by slave
assign m_aready = m_avalid & S_WVALID & S_WLAST & (|(M_WREADY & m_select_hot));
// M_WVALID is generated per MI-slot (including error handler at slot C_NUM_MASTER_SLOTS).
// The slot selected by the head of the queue (m_select_enc) is enabled.
assign M_WVALID = {C_NUM_MASTER_SLOTS{S_WVALID & m_avalid}} & m_select_hot;
// S_WREADY is muxed from the MI slot selected by the head of the queue (m_select_enc).
assign S_WREADY = m_avalid & (|(M_WREADY & m_select_hot));
endmodule
`default_nettype wire
|
// Two modules are built as part of solution
// First define a 4 bit block and then reuse
module jcsablock(Y,carryout,A,B,carryin);
output [3:0]Y;
output carryout;
input [3:0]A,B;
input carryin;
wire [3:0]g,p;// generate and propogate
wire [4:0]c;// intermediate carry of adders, one extra for coding simplicity
wire z;// for the mux
assign c[0] = carryin; // this line is not needed can be directly written
genvar i;
for (i=0; i<=3; i=i+1)
begin
assign p[i] = A[i] ^ B[i];
assign c[i+1] = ( A[i] & B[i] ) | ( A[i] & c[i] ) | ( B[i] & c[i] );
assign Y[i] = A[i] ^ B[i] ^ c[i];
end
// now assign the mux value correctly
assign z = p[0] & p [1] & p[2] & p[3];
assign carryout = z ? carryin : c[4];
endmodule
// Second reuse the above block modules to build the final adder
// The adder is a 8 bit adder which will make use of two blocks of 4 bit each
module jcarryskipadder(Y,carryout,A,B,carryin);
output [7:0]Y;
output carryout;
input [7:0]A,B;
input carryin;
wire c4; // intermediate carry obtained from first block
jcsablock b1 (Y[3:0],c4,A[3:0],B[3:0],carryin);
jcsablock b2 (Y[7:4],carryout,A[7:4],B[7:4],c4); // pass the intermediate carry here
endmodule
|
//
// Copyright (c) 2013 Colin Rothwell
// All rights reserved.
//
// This software was developed by SRI International and the University of
// Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
// ("CTSRD"), as part of the DARPA CRASH research programme.
//
// @BERI_LICENSE_HEADER_START@
//
// Licensed to BERI Open Systems C.I.C. (BERI) under one or more contributor
// license agreements. See the NOTICE file distributed with this work for
// additional information regarding copyright ownership. BERI licenses this
// file to you under the BERI Hardware-Software License, Version 1.0 (the
// "License"); you may not use this file except in compliance with the
// License. You may obtain a copy of the License at:
//
// http://www.beri-open-systems.org/legal/license-1-0.txt
//
// Unless required by applicable law or agreed to in writing, Work distributed
// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// @BERI_LICENSE_HEADER_END@
//
module RunMegafunctionTest(input clk, input rst);
//mkTestMegafunctions mf(.CLK(clk), .RST_N(rst));
//mkTest mf(.CLK(clk), .RST_N(rst));
//mkCompositeOpTests test(clk, rst);
mkMegafunctionServerTests tests(clk, rst);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__TAPVGND_BLACKBOX_V
`define SKY130_FD_SC_HDLL__TAPVGND_BLACKBOX_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection
* 1 row down.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__tapvgnd ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__TAPVGND_BLACKBOX_V
|
#include <bits/stdc++.h> bool debug = 1; const long long MOD = 1000000007; const double PI = acos(-1.0); const double eps = 1e-9; using namespace std; int main() { int n, m; int c[100100], a[100100]; cin >> n >> m; for (int i = 0; i < n; i++) { scanf( %d , &c[i]); } for (int i = 0; i < m; i++) { scanf( %d , &a[i]); } int j = 0; for (int i = 0; i < n; i++) { if (j < m and c[i] <= a[j]) j++; } cout << j << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; scanf( %d %d , &n, &m); char A[147][10047]; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) scanf( %c , &A[i][j]); int P[147][10047]; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) P[i][j] = -1; queue<int> Q; for (int j = 0; j < m; j++) if (A[i][j] == 1 ) { Q.push(j); Q.push(0); P[i][j] = 0; } while (!Q.empty()) { int kde = Q.front(); Q.pop(); int kolko = Q.front(); Q.pop(); int dx[] = {1, -1}; for (int k = 0; k < 2; k++) { int kde1 = kde + dx[k]; kde1 += m; kde1 %= m; if (P[i][kde1] == -1) { P[i][kde1] = kolko + 1; Q.push(kde1); Q.push(kolko + 1); } } } } int vys = -1; int V[10047]; for (int i = 0; i < m; i++) V[i] = 0; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { if (P[i][j] == -1) V[j] = -1; else if (V[j] != -1) V[j] += P[i][j]; } vys = V[0]; for (int i = 0; i < m; i++) vys = min(vys, V[i]); printf( %d n , vys); return 0; }
|
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
/***************************************************************************
****************************************************************************
***
*** Program File: @(#)ff_primitives.v
***
****************************************************************************
****************************************************************************/
module fj_dff_e(q, d, clk);
output q;
input d, clk;
reg q;
always @(posedge (clk)) begin
q <= #1 d;
end
endmodule
module fj_dff_ec(q, d, clk, c);
output q;
input d, clk, c;
reg q;
always @(posedge clk or posedge c) begin
if (c)
q <= #1 1'b0;
else
q <= #1 d;
end
endmodule
module fj_dff_es(q, d, clk, s);
output q;
input d, clk, s;
reg q;
always @(posedge clk or posedge s) begin
if (s)
q <= #1 1'b1;
else
q <= #1 d;
end
endmodule
module fj_dff_ecs(q, d, clk, c, s);
output q;
input d, clk, c, s;
reg q;
always @(posedge clk or posedge s or posedge c) begin
if (c)
q <= #1 1'b0;
else if (s)
q <= #1 1'b1;
else
q <= #1 d;
end
endmodule
module fj_dff_e_muxscan(q, d, si, sm, clk);
output q;
input d, si, sm, clk;
reg q;
always @(posedge clk) begin
if (sm==1'b0)
q <= #1 d;
else if (sm==1'b1)
q <= #1 si;
else q <= #1 1'bx;
end
endmodule
module fj_dff_ec_muxscan(q, d, si, sm, clk, c);
output q;
input d, si, sm, clk, c;
reg q;
always @(posedge clk or posedge c) begin
if (c)
q <= #1 1'b0;
else if (sm==1'b0)
q <= #1 d;
else if (sm==1'b1)
q <= #1 si;
else q <= #1 1'bx;
end
endmodule
module fj_dff_es_muxscan(q, d, si, sm, clk, s);
output q;
input d, si, sm, clk, s;
reg q;
always @(posedge clk or posedge s) begin
if (s)
q <= #1 1'b1;
else if (sm==1'b0)
q <= #1 d;
else if (sm==1'b1)
q <= #1 si;
else q <= #1 1'bx;
end
endmodule
module fj_dff_ecs_muxscan(q, d, si, sm, clk, c, s);
output q;
input d, si, sm, clk, c, s;
reg q;
always @(posedge clk or posedge c or posedge s) begin
if (s)
q <= #1 1'b1;
else if (c)
q <= #1 1'b0;
else if (sm==1'b0)
q <= #1 d;
else if (sm==1'b1)
q <= #1 si;
else q <= #1 1'bx;
end
endmodule
module fj_latch_e(Q, G, D);
output Q;
input G, D;
reg Q;
always @ (G or D) begin
if (G==1) Q <= #1 D;
end
endmodule
module fj_xctrl(oe, en,en_);
output oe;
input en, en_;
assign oe = (en && (~en_));
endmodule
module UDP_MUX21(O_, A,B, S);
output O_;
input A, B, S;
assign O_ = ((~A && ~S) || (~B && S));
endmodule
module UDP_LATCH(Q, G_,D);
output Q;
input G_, D;
reg Q;
always @ (G_ or D) begin
if (G_==0) Q <= #1 D;
end
endmodule
module UDP_LATCH1(Q_, G1,G2, D1,D2);
output Q_;
input G1, G2, D1, D2;
reg Q_;
always @ (G1 or G2 or D1 or D2) begin
if ((G1==1) & (G2==0)) Q_ <= #1 D1;
else if ((G1==0) & (G2==1)) Q_ <= #1 D2;
end
endmodule
module UDP_LATCH2(Q_, G1A,G1B, D);
output Q_;
input G1A, G1B, D;
reg Q_;
always @ (G1A or G1B or D) begin
if ((G1A==1) & (G1B==1)) Q_ <= #1 ~D;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; const int dx[8] = {0, -1, 0, 1, -1, -1, 1, 1}, dy[8] = {1, 0, -1, 0, -1, 1, -1, 1}; int a[100005]; int cnt = 0; int n, m, k; vector<int> vt[100005], vt2[2]; stack<int> st; int dfn[100005], color[100005]; void dfs(int x, int fa) { st.push(x); dfn[x] = st.size(); for (int i = 0; i < vt[x].size(); i++) { int v = vt[x][i]; if (v == fa) continue; if (!dfn[v]) { dfs(v, x); } else if (dfn[x] - dfn[v] + 1 <= k && dfn[x] > dfn[v]) { cout << 2 << endl; cout << dfn[x] - dfn[v] + 1 << endl; while (1) { cout << st.top() << ; if (st.top() == v) { exit(0); } st.pop(); } } } st.pop(); } void dfs2(int x, int fa, int co) { vt2[co].push_back(x); color[x] = co; if (vt2[co].size() == k) { for (int i = 0; i < vt2[co].size(); i++) { cout << vt2[co][i] << ; } exit(0); } for (int i = 0; i < vt[x].size(); i++) { int v = vt[x][i]; if (v == fa || color[v] != -1) continue; dfs2(v, x, co ^ 1); } } void solve() { memset(color, -1, sizeof color); cin >> n >> m >> k; for (int i = 1; i <= m; i++) { int x, y; cin >> x >> y; vt[x].push_back(y); vt[y].push_back(x); } dfs(1, 0); k = (k + 1) / 2; cout << 1 << endl; dfs2(1, 0, 0); } int main() { ios::sync_with_stdio(0); ; solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; signed main() { cin.tie(nullptr)->sync_with_stdio(false); long long _; for (cin >> _; _--;) { long long n, m, k; cin >> n >> m >> k; long long mn = (n % 2 == 1 ? m / 2 : 0); long long mx = n * m / 2 - (m % 2 == 1 ? n / 2 : 0); if (mn <= k and k <= mx and (k - mn) % 2 == 0) cout << YES n ; else cout << NO n ; } }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build Mon Oct 10 19:07:27 MDT 2016
// Date : Mon Oct 30 11:41:09 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dbg_ila_stub.v
// Design : dbg_ila
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
probe18, probe19, probe20, probe21, probe22, probe23, probe24, probe25, probe26, probe27)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[63:0],probe8[0:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[63:0],probe13[0:0],probe14[0:0],probe15[0:0],probe16[0:0],probe17[0:0],probe18[7:0],probe19[8:0],probe20[0:0],probe21[2:0],probe22[2:0],probe23[0:0],probe24[7:0],probe25[0:0],probe26[3:0],probe27[7:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [0:0]probe2;
input [0:0]probe3;
input [0:0]probe4;
input [0:0]probe5;
input [0:0]probe6;
input [63:0]probe7;
input [0:0]probe8;
input [0:0]probe9;
input [0:0]probe10;
input [0:0]probe11;
input [63:0]probe12;
input [0:0]probe13;
input [0:0]probe14;
input [0:0]probe15;
input [0:0]probe16;
input [0:0]probe17;
input [7:0]probe18;
input [8:0]probe19;
input [0:0]probe20;
input [2:0]probe21;
input [2:0]probe22;
input [0:0]probe23;
input [7:0]probe24;
input [0:0]probe25;
input [3:0]probe26;
input [7:0]probe27;
endmodule
|
//hardware top level module
module sm_top
(
input clkIn,
input rst_n,
input [ 3:0 ] clkDevide,
input clkEnable,
output clk,
input [ 4:0 ] regAddr,
output [31:0 ] regData
);
//metastability input filters
wire [ 3:0 ] devide;
wire enable;
wire [ 4:0 ] addr;
sm_metafilter #(.SIZE(4)) f0(clkIn, clkDevide, devide);
sm_metafilter #(.SIZE(1)) f1(clkIn, clkEnable, enable);
sm_metafilter #(.SIZE(5)) f2(clkIn, regAddr, addr );
//cores
//clock devider
sm_clk_divider sm_clk_divider
(
.clkIn ( clkIn ),
.rst_n ( rst_n ),
.devide ( devide ),
.enable ( enable ),
.clkOut ( clk )
);
//instruction memory
wire [31:0] imAddr;
wire [31:0] imData;
sm_rom reset_rom(imAddr, imData);
sm_cpu sm_cpu
(
.clk ( clk ),
.rst_n ( rst_n ),
.regAddr ( addr ),
.regData ( regData ),
.imAddr ( imAddr ),
.imData ( imData )
);
endmodule
//metastability input filter module
module sm_metafilter
#(
parameter SIZE = 1
)
(
input clk,
input [ SIZE - 1 : 0] d,
output reg [ SIZE - 1 : 0] q
);
reg [ SIZE - 1 : 0] data;
always @ (posedge clk) begin
data <= d;
q <= data;
end
endmodule
//tunable clock devider
module sm_clk_divider
#(
parameter shift = 16
)
(
input clkIn,
input rst_n,
input [ 3:0 ] devide,
input enable,
output clkOut
);
wire [31:0] cntr;
wire [31:0] cntrNext = cntr + 1;
sm_register_we r_cntr(clkIn, rst_n, enable, cntrNext, cntr);
assign clkOut = cntr[shift + devide];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR4_PP_SYMBOL_V
`define SKY130_FD_SC_HD__NOR4_PP_SYMBOL_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nor4 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR4_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A21BO_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__A21BO_FUNCTIONAL_PP_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a21bo (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out_X , B1_N, nand0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nand1_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A21BO_FUNCTIONAL_PP_V
|
`include "crt_address_decoder.v"
`include "crt_register.v"
module crt(
input clk,
input reset,
input cs,
input we,
input [3:0] addr,
inout [15:0] data,
output irq,
output vs,
output hs,
output ven,
output [2:0] clksel,
output [31:0] pixaddr
);
// One-hot chip select bus for registers
wire addr_cr, addr_ia, addr_ir, addr_ic;
wire addr_sh, addr_sl, addr_fh, addr_fl;
wire addr_ve, addr_vf, addr_vv, addr_vb;
wire addr_he, addr_hf, addr_hv, addr_hb;
// Standard 1920*1080@60Hz
localparam [15:0] T_HS = 16'd44; // horizontal sync
localparam [15:0] T_HB = 16'd148; // horizontal back porch
localparam [15:0] T_HV = 16'd1920; // horizontal video
localparam [15:0] T_HF = 16'd88; // horizontal front porch
localparam [15:0] T_VS = 16'd5; // vertical sync
localparam [15:0] T_VB = 16'd36; // vertical back porch
localparam [15:0] T_VV = 16'd540; // vertical video
localparam [15:0] T_VF = 16'd4; // vertical front porch
// Positions are relative to
localparam [15:0] INIT_HB = (T_HS);
localparam [15:0] INIT_HV = (T_HS + T_HB);
localparam [15:0] INIT_HF = (T_HS + T_HB + T_HV);
localparam [15:0] INIT_HE = (T_HS + T_HB + T_HV + T_HF - 16'd1);
localparam [15:0] INIT_VB = (T_VS);
localparam [15:0] INIT_VV = (T_VS + T_VB);
localparam [15:0] INIT_VF = (T_VS + T_VB + T_VV);
localparam [15:0] INIT_VE = (T_VS + T_VB + T_VV + T_VF - 16'd1);
localparam [15:0] INIT_IC = 16'd0;
localparam [15:0] INIT_IR = 16'd0;
localparam [15:0] INIT_CR = 16'h0002;
localparam [15:0] INIT_SL = 16'h0080;
localparam [15:0] INIT_SH = 16'h0000;
localparam [15:0] INIT_FL = 16'h0000;
localparam [15:0] INIT_FH = 16'h0001;
localparam [15:0] INIT_IRQ = 16'h0000;
wire [15:0] address_decode;
crt_address_decoder addr_decode(
.addr(addr),
.cs(cs),
.q(address_decode)
);
assign {
addr_cr, addr_ia, addr_ir, addr_ic,
addr_sh, addr_sl, addr_fh, addr_fl,
addr_ve, addr_vf, addr_vv, addr_vb,
addr_he, addr_hf, addr_hv, addr_hb
} = address_decode;
// DFFs
reg [15:0] currentrow;
reg [15:0] currentcol;
reg [31:0] currentaddr;
reg currentfield;
wire [15:0] hbporch, hvideo, hfporch, hend;
wire [15:0] vbporch, vvideo, vfporch, vend;
wire [15:0] irqc, irqr;
wire [15:0] control;
wire [31:0] startaddr;
wire [31:0] stride;
// Determine how far it is in addresses from the start
// of one scanline to the start of the next
wire [31:0] row2row = (hend - hvideo) + stride;
// The start address of the second field
wire [31:0] startaddr2 = startaddr + row2row;
wire [31:0] nextstartaddr = currentfield ? startaddr2 : startaddr;
// The last scanline is half length when interlaced
wire [15:0] hend2 = {1'b0, hend[15:1]};
wire [15:0] hendv = video_interlaced ? hend2 : hend;
crt_register #(.WIDTH(16)) reg_hb(
.clk(clk),
.reset(reset),
.resetvalue(INIT_HB),
.cs(addr_hb),
.we(we),
.value(hbporch),
.data(data)
);
// hvideo
crt_register #(.WIDTH(16)) reg_hv(
.clk(clk),
.reset(reset),
.resetvalue(INIT_HV),
.cs(addr_hv),
.we(we),
.value(hvideo),
.data(data)
);
// hfporch
crt_register #(.WIDTH(16)) reg_hf(
.clk(clk),
.reset(reset),
.resetvalue(INIT_HF),
.cs(addr_hf),
.we(we),
.value(hfporch),
.data(data)
);
// hend
crt_register #(.WIDTH(16)) reg_he(
.clk(clk),
.reset(reset),
.resetvalue(INIT_HE),
.cs(addr_he),
.we(we),
.value(hend),
.data(data)
);
// vbporch
crt_register #(.WIDTH(16)) reg_vb(
.clk(clk),
.reset(reset),
.resetvalue(INIT_VB),
.cs(addr_vb),
.we(we),
.value(vbporch),
.data(data)
);
// vvideo
crt_register #(.WIDTH(16)) reg_vv(
.clk(clk),
.reset(reset),
.resetvalue(INIT_VV),
.cs(addr_vv),
.we(we),
.value(vvideo),
.data(data)
);
// vfporch
crt_register #(.WIDTH(16)) reg_vf(
.clk(clk),
.reset(reset),
.resetvalue(INIT_VF),
.cs(addr_vf),
.we(we),
.value(vfporch),
.data(data)
);
// vend
crt_register #(.WIDTH(16)) reg_ve(
.clk(clk),
.reset(reset),
.resetvalue(INIT_VE),
.cs(addr_ve),
.we(we),
.value(vend),
.data(data)
);
// irqc
crt_register #(.WIDTH(16)) reg_ic(
.clk(clk),
.reset(reset),
.resetvalue(INIT_IC),
.cs(addr_ic),
.we(we),
.value(irqc),
.data(data)
);
// irqr
crt_register #(.WIDTH(16)) reg_ir(
.clk(clk),
.reset(reset),
.resetvalue(INIT_IR),
.cs(addr_ir),
.we(we),
.value(irqr),
.data(data)
);
// control
crt_register #(.WIDTH(16)) reg_cr(
.clk(clk),
.reset(reset),
.resetvalue(INIT_CR),
.cs(addr_cr),
.we(we),
.value(control),
.data(data)
);
// stride low
crt_register #(.WIDTH(16)) reg_sl(
.clk(clk),
.reset(reset),
.resetvalue(INIT_SL),
.cs(addr_sl),
.we(we),
.value(stride[15:0]),
.data(data)
);
// stride high
crt_register #(.WIDTH(16)) reg_sh(
.clk(clk),
.reset(reset),
.resetvalue(INIT_SH),
.cs(addr_sh),
.we(we),
.value(stride[31:16]),
.data(data)
);
// frame low
crt_register #(.WIDTH(16)) reg_fl(
.clk(clk),
.reset(reset),
.resetvalue(INIT_FL),
.cs(addr_fl),
.we(we),
.value(startaddr[15:0]),
.data(data)
);
// frame high
crt_register #(.WIDTH(16)) reg_fh(
.clk(clk),
.reset(reset),
.resetvalue(INIT_FH),
.cs(addr_fh),
.we(we),
.value(startaddr[31:16]),
.data(data)
);
// irq
crt_register #(.WIDTH(16)) reg_ia(
.clk(clk),
.reset(reset | (we & addr_ia)),
.resetvalue(INIT_IRQ),
.cs(irq_set),
.we(irq_set),
.value(irqout),
.data(irq_set_data)
);
// Combinatorial examination of current state
// Phases of horizontal and vertical trace:
// Sync
// back porch
// video
// front porch
wire irq_enabled = control[15];
wire hsync_invert = control[14];
wire vsync_invert = control[13];
wire video_interlaced = control[1];
wire video_enabled = ~control[0];
wire [2:0] clk_select = control[7:5];
wire is_currentcol_0 = (currentcol == 1'b0);
wire is_currentcol_ge_hvideo = (currentcol >= hvideo);
wire is_currentcol_lt_hbporch = (currentcol < hbporch);
wire is_currentcol_lt_hfporch = (currentcol < hfporch);
wire is_currentcol_hfporch = (currentcol == hfporch);
wire is_currentcol_hendv = (currentcol == hendv);
wire is_currentcol_hend = (currentcol == hend);
wire is_currentrow_0 = (currentrow == 1'b0);
wire is_currentrow_ge_vvideo = (currentrow >= vvideo);
wire is_currentrow_lt_vbporch = (currentrow < vbporch);
wire is_currentrow_lt_vfporch = (currentrow < vfporch);
wire is_currentrow_vfporch = (currentrow == vfporch);
wire is_currentrow_vend = (currentrow == vend);
wire in_start = is_currentrow_0 & is_currentcol_0;
wire in_end = is_currentrow_vfporch & is_currentcol_hfporch;
wire in_restart_addr = (in_start | in_end);
wire in_hsync = is_currentcol_lt_hbporch;
//wire in_hbporch = currentcol >= hbporch && currentcol < hvideo;
wire in_hvideo = is_currentcol_ge_hvideo & is_currentcol_lt_hfporch;
//wire in_hfporch = currentcol >= hfporch && currentcol < hend;
// The last scanline is half-length when interlaced
wire in_hend = (video_interlaced & is_currentrow_vend &
is_currentcol_hendv) | is_currentcol_hend;
wire in_vsync = is_currentrow_lt_vbporch;
//wire in_vbporch = currentrow >= vbporch && currentrow < vvideo;
wire in_vvideo = is_currentrow_ge_vvideo && is_currentrow_lt_vfporch;
//wire in_vfporch = currentrow >= vfporch && currentrow < vend;
wire in_vend = is_currentcol_hendv & is_currentrow_vend;
wire irq_rowmatch = (currentrow == irqr);
wire irq_colmatch = (currentcol == irqc);
wire irq_match = irq_rowmatch & irq_colmatch;
wire irq_set = irq_match & irq_enabled;
wire [15:0] irq_set_data = 16'b1;
wire in_video = in_hvideo & in_vvideo;
wire [15:0] nextcol = currentcol + 1'b1;
wire [15:0] nextrow = currentrow + 1'b1;
wire [31:0] nextpixeladdr = currentaddr + 1'b1;
wire [31:0] nextrowaddr = currentaddr + stride;
wire [15:0] irqout;
wire [15:0] dataout;
wire dataout_en;
// Drive outputs
assign hs = in_hsync ^ hsync_invert;
assign vs = in_vsync ^ vsync_invert;
assign ven = in_video & video_enabled;
assign clksel = clk_select;
assign pixaddr = currentaddr;
assign irq = irqout[0];
always @(posedge clk)
begin
currentfield <= (reset | ~in_vend) ? (currentfield & ~reset)
: ((currentfield & video_interlaced) ^ video_interlaced);
// Address jumps to start of next row at horizontal end
// Address jumps to beginning of frame at vertical end
// Address steps forward one pixel if in video
// Otherwise stays at same address
currentaddr <= (reset | in_restart_addr) ? nextstartaddr :
(in_hend & in_vvideo) ? nextrowaddr :
in_video ? nextpixeladdr :
currentaddr;
// Current row resets if at vertical end,
// Advances to the next line if at horizontal end
// Otherwise stays on the same row
currentrow <= (reset | in_vend) ? 1'b0 :
in_hend ? nextrow :
currentrow;
// Update currentcol
// The next column, or reset at horizontal end
// Never stops, only resets at max value
currentcol <= (reset | in_hend) ? 1'b0 :
nextcol;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n, sum = 0; long long ans = 0; cin >> n; char s[n]; cin >> (s + 1); map<int, int> f; f[0] = 1; for (int i = 1; i <= n; i++) { int tmp = s[i] - 0 ; sum += tmp; ans += f[sum - i]; f[sum - i]++; } cout << ans << endl; } }
|
//---------------------------------------------------------------------------
//-- Copyright 2015 - 2017 Systems Group, ETH Zurich
//--
//-- This hardware module is free software: you can redistribute it and/or
//-- modify it under the terms of the GNU General Public License as published
//-- by the Free Software Foundation, either version 3 of the License, or
//-- (at your option) any later version.
//--
//-- This program is distributed in the hope that it will be useful,
//-- but WITHOUT ANY WARRANTY; without even the implied warranty of
//-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
//-- GNU General Public License for more details.
//--
//-- You should have received a copy of the GNU General Public License
//-- along with this program. If not, see <http://www.gnu.org/licenses/>.
//---------------------------------------------------------------------------
module nukv_Feedback #(
parameter KEY_WIDTH = 128,
parameter META_WIDTH = 96
)
(
// Clock
input wire clk,
input wire rst,
input wire [KEY_WIDTH+META_WIDTH-1:0] fb_in_data,
input wire fb_in_valid,
output wire fb_in_ready,
output wire [KEY_WIDTH+META_WIDTH-1:0] fb_out_data,
output wire fb_out_valid,
input wire fb_out_ready,
input wire [KEY_WIDTH+META_WIDTH-1:0] reg_in_data,
input wire reg_in_valid,
output wire reg_in_ready,
output wire [KEY_WIDTH+META_WIDTH-1:0] reg_out_data,
output wire reg_out_valid,
input wire reg_out_ready
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[100005], ans[100005], ti[100005], app[100005], t, n; int cnt(int k) { int ret = 1, count = 0; ++t; for (int i = 1; i <= n; i++) { if (ti[a[i]] != t) { ti[a[i]] = t; app[a[i]] = false; } if (!app[a[i]]) { if (count == k) { count = 0; ret++; ti[a[i]] = ++t; } count++; } app[a[i]] = true; } return ret; } void solve(int l, int r, int lo, int hi) { if (l > r) return; int mid = (l + r) / 2; int res = lo == hi ? lo : cnt(mid); ans[mid] = res; solve(l, mid - 1, res, hi); solve(mid + 1, r, lo, res); } int main() { cin >> n; for (int i = 1; i <= n; i++) scanf( %d , &a[i]); solve(1, n, 1, n); for (int i = 1; i <= n; i++) { if (i > 1) printf( ); printf( %d , ans[i]); } cout << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, t; cin >> n >> t; int d = 1; while (t > 1) { if (t % 2) { cout << 0 << endl; return 0; } t /= 2; d++; } long long dp[60][60] = {}; dp[1][1] = 1; long long cur = 1; long long lv = 1; long long ans = 0; int i = 2; n++; for (i = 2; i <= 60; i++) { for (int j = 1; j <= i; j++) { dp[i][j] = dp[i - 1][j - 1] + dp[i - 1][j]; } lv *= 2; cur += lv; if (cur > n) break; ans += dp[i][d]; } n -= lv - 1; while (lv > 1) { lv /= 2; i--; if (n >= lv) { ans += dp[i][d]; n -= lv; d--; } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; bool IsPrime(int n) { if (n == 1) return false; for (int d = 2; d * d <= n; d++) { if (n % d == 0) return false; } return true; } int main() { int n; cin >> n; int count = 0; while (n > 0) { int j = 0; int k = n; int amx = INT_MIN; while (k > 0) { j = k % 10; k = k / 10; amx = max(amx, j); } n -= amx; count++; } cout << count << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; int x = (n + 3) / 4; int p = n - x; while (p--) cout << 9 ; while (x--) cout << 8 ; cout << endl; } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRBP_BEHAVIORAL_V
`define SKY130_FD_SC_MS__DLRBP_BEHAVIORAL_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_ms__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dlrbp (
Q ,
Q_N ,
RESET_B,
D ,
GATE
);
// Module ports
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire RESET ;
reg notifier ;
wire D_delayed ;
wire GATE_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_ms__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRBP_BEHAVIORAL_V
|
/* This file is part of JT12.
JT12 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 29-10-2018
*/
module jt12_eg_cnt(
input rst,
input clk,
input clk_en /* synthesis direct_enable */,
input zero,
output reg [14:0] eg_cnt
);
reg [1:0] eg_cnt_base;
always @(posedge clk, posedge rst) begin : envelope_counter
if( rst ) begin
eg_cnt_base <= 2'd0;
eg_cnt <=15'd0;
end
else begin
if( zero && clk_en ) begin
// envelope counter increases every 3 output samples,
// there is one sample every 24 clock ticks
if( eg_cnt_base == 2'd2 ) begin
eg_cnt <= eg_cnt + 1'b1;
eg_cnt_base <= 2'd0;
end
else eg_cnt_base <= eg_cnt_base + 1'b1;
end
end
end
endmodule // jt12_eg_cnt
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EBUFN_BLACKBOX_V
`define SKY130_FD_SC_HD__EBUFN_BLACKBOX_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__ebufn (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__EBUFN_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int N = 2002; int a[N][N] = {0}, b[N][N] = {0}; int c[N] = {0}, d[N] = {0}, e[N] = {0}, f[N] = {0}; int main() { int n, m, ans = 0; cin >> n >> m; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { cin >> a[i][j]; b[i][j] = a[i][j]; if (a[i][j] == 0) { if (c[i] == 1) ans++; if (d[j] == 1) ans++; } else { c[i] = 1, d[j] = 1; } } } for (int i = n; i >= 1; i--) { for (int j = m; j >= 1; j--) { if (b[i][j] == 0) { if (e[i] == 1) ans++; if (f[j] == 1) ans++; } else { e[i] = 1, f[j] = 1; } } } cout << ans << endl; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRTP_OV2_BEHAVIORAL_V
`define SKY130_FD_SC_LP__SDFRTP_OV2_BEHAVIORAL_V
/**
* sdfrtp_ov2: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_lp__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__sdfrtp_ov2 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_lp__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRTP_OV2_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; long long ar[1000010]; int main() { long long n; cin >> n; long long ans = 0; if (n % 2 == 1) puts( 0 ); else { n = n / 2; n = (n - 1) / 2; cout << n << endl; } return 0; }
|
module DataMem (
input clk, rst,
input MemWrite, MemRead,
input rx,
input [31:0] addr, wdata,
input [7:0] switch,
output tx,
output reg [31:0] rdata,
output reg [7:0] led,
output reg [11:0] digi,
output irq
);
parameter RAM_SIZE = 256;
parameter RAM_BIT = 8; // 2^8 = 256
reg [31:0] DATA[RAM_SIZE-1:0];
reg [31:0] TH, TL;
reg [2:0] TCON;
reg [7:0] UART_RXD, UART_TXD;
reg [1:0] UART_CON;
reg enable; // UART enable
wire rx_s, tx_s; // UART status
wire [7:0] rx_d; // receive data
integer i;
assign irq = TCON[2];
// read
always @ (*) begin
if(MemRead) begin
case (addr)
32'h4000_0000: rdata <= TH;
32'h4000_0004: rdata <= TL;
32'h4000_0008: rdata <= {29'b0, TCON};
32'h4000_000c: rdata <= {24'b0, led};
32'h4000_0010: rdata <= {24'b0, switch};
32'h4000_0014: rdata <= {20'b0, digi};
32'h4000_0018: rdata <= {24'b0, UART_TXD};
32'h4000_001c: rdata <= {24'b0, UART_RXD};
32'h4000_0020: rdata <= {28'b0, UART_CON, 2'b0};
default: begin
rdata <= ( (addr[RAM_BIT+1:2]<RAM_SIZE) && ~addr[30] ) ?
DATA[ addr[RAM_BIT+1:2] ] : 32'b0;
end
endcase
end else
rdata <= 32'b0;
end
// write
always @ (posedge clk or posedge rst) begin
if (rst) begin // posedge rst
for(i=0;i<256;i=i+1) DATA[i]<=32'b0;
TH <= 32'b0;
TL <= 32'b0;
TCON <= 3'b0; // all disable
led <= 8'b0;
digi <= 12'b0;
end else begin
if(TCON[0]) begin // TIM enable
if(TL==32'hffff_ffff) begin
TL <= TH;
TCON[2] <= TCON[1] ? 1'b1 : 1'b0;
end else begin
TL <= TL + 1'b1;
end
end
if(MemWrite)
case (addr)
32'h4000_0000: TH <= wdata;
32'h4000_0004: TL <= wdata;
32'h4000_0008: TCON <= wdata[2:0];
32'h4000_000C: led <= wdata[7:0];
32'h4000_0014: digi <= wdata[11:0];
default: if ( (addr[RAM_BIT+1:2]<RAM_SIZE) && ~addr[30] )
DATA[ addr[RAM_BIT+1:2] ] <= wdata;
endcase
end
end
// UART control
UART_RX uartrx(
.clk(clk), .rst(rst),
.RX(rx),
.DATA(rx_d),
.STATUS(rx_s)
);
UART_TX uarttx(
.clk(clk), .rst(rst),
.DATA(UART_TXD),
.EN(enable),
.TX(tx),
.STATUS(),
.END(tx_s)
);
always @ (posedge clk or posedge rst) begin
if(rst) begin
UART_CON <= 2'b0;
UART_TXD <= 8'b0;
UART_RXD <= 8'b0;
enable <= 1'b0;
end else begin
if(MemWrite)
case (addr)
32'h4000_0018: begin
UART_TXD <= wdata[7:0];
enable <= 1'b1;
end
32'h4000_0020: UART_CON <= wdata[3:2];
default: ;
endcase
if(MemRead)
case (addr)
32'h4000_0018: UART_CON[0] <= 1'b0;
32'h4000_001c: UART_CON[1] <= 1'b0;
default: ;
endcase
if(rx_s) begin
UART_RXD <= rx_d;
UART_CON[1] <= 1'b1;
end
if(tx_s) begin
UART_CON[0] <= 1'b1;
enable <= 1'b0;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO1N_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__INPUTISO1N_PP_SYMBOL_V
/**
* inputiso1n: Input isolation, inverted sleep.
*
* X = (A & SLEEP_B)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__inputiso1n (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP_B,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO1N_PP_SYMBOL_V
|
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
`timescale 1ns/1ns
module hshrink(
input [3:0] SHRINK, // Shrink value
input CK, L,
output OUTA, OUTB
);
wire [3:0] nSHRINK;
wire [3:0] U193_REG;
wire [3:0] T196_REG;
wire [3:0] U243_REG;
wire [3:0] U226_REG;
wire [3:0] U193_P;
wire [3:0] T196_P;
wire [3:0] U243_P;
wire [3:0] U226_P;
assign nSHRINK[3:0] = ~SHRINK[3:0];
// Lookup
assign U193_P[0] = ~&{nSHRINK[3:2]};
assign U193_P[1] = ~&{nSHRINK[3:1]};
assign U193_P[2] = ~&{nSHRINK[3], ~&{SHRINK[2:1]}};
assign U193_P[3] = 1'b1;
assign T196_P[0] = ~|{&{SHRINK[2], ~|{SHRINK[1:0], SHRINK[3]}}, ~|{SHRINK[3:2]}};
assign T196_P[1] = ~&{nSHRINK[3:0]};
assign T196_P[2] = ~&{~&{SHRINK[1:0]}, ~|{SHRINK[3:2]}};
assign T196_P[3] = ~&{nSHRINK[3], ~&{SHRINK[2:0]}};
assign U243_P[0] = ~|{nSHRINK[3], ~|{SHRINK[2:1]}};
assign U243_P[1] = ~|{nSHRINK[3:2]};
assign U243_P[2] = ~|{nSHRINK[3:1]};
assign U243_P[3] = SHRINK[3];
assign U226_P[0] = ~&{~&{SHRINK[1:0], nSHRINK[2], SHRINK[3]}, ~&{SHRINK[3:2]}};
assign U226_P[1] = &{SHRINK[3:0]};
assign U226_P[2] = ~|{nSHRINK[3], ~|{SHRINK[2:0]}};
assign U226_P[3] = ~|{~&{SHRINK[3:2]}, ~|{SHRINK[1:0]}};
// Shift registers
FS2 U193(CK, U193_P, 1'b1, ~L, U193_REG);
BD3 T193A(U193_REG[3], T193A_OUT);
FS2 T196(CK, T196_P, T193A_OUT, ~L, T196_REG);
FS2 U243(CK, U243_P, 1'b1, ~L, U243_REG);
BD3 U258A(U243_REG[3], U258A_OUT);
FS2 U226(CK, U226_P, U258A_OUT, ~L, U226_REG);
assign OUTA = T196_REG[3];
assign OUTB = U226_REG[3];
/*always@(*)
begin
case (SHRINK)
4'h0: BITMAP <= 16'b0000000010000000;
4'h1: BITMAP <= 16'b0000100010000000;
4'h2: BITMAP <= 16'b0000100010001000;
4'h3: BITMAP <= 16'b0010100010001000;
4'h4: BITMAP <= 16'b0010100010001010;
4'h5: BITMAP <= 16'b0010101010001010;
4'h6: BITMAP <= 16'b0010101010101010;
4'h7: BITMAP <= 16'b1010101010101010;
4'h8: BITMAP <= 16'b1010101011101010;
4'h9: BITMAP <= 16'b1011101011101010;
4'hA: BITMAP <= 16'b1011101011101011;
4'hB: BITMAP <= 16'b1011101111101011;
4'hC: BITMAP <= 16'b1011101111101111;
4'hD: BITMAP <= 16'b1111101111101111;
4'hE: BITMAP <= 16'b1111101111111111;
4'hF: BITMAP <= 16'b1111111111111111;
endcase
end*/
endmodule
|
`timescale 1ns / 1ps
/*
Copyright 2015, Google Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:49:03 02/02/2015
// Design Name:
// Module Name: sha256
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sha256_core (
input clk,
input load_i,
input [511:0] data_i,
input [255:0] state_i,
output [255:0] state_o,
output reg busy_o
);
localparam SHA256_MAX_STEP = 64;
`define STATE_LOAD(i) state_i[256 - (i * 32) - 1: 256 - (i * 32) - 32]
reg [31:0] A, B, C, D, E, F, G, H;
reg [31:0] A_new, B_new, C_new, D_new, E_new, F_new, G_new, H_new;
reg [31:0] HKW, HKW_new;
reg [6:0] step, step_new;
reg busy_new;
wire [31:0] W, K;
assign state_o = { A, B, C, D, E, F, G, H };
sha256_W W_inst(
.clk(clk),
.data_i(data_i),
.load_i(load_i),
.busy_i(busy_o),
.W_o(W)
);
sha256_K K_inst(
.step_i(step[5:0]),
.K_o(K)
);
always @(posedge clk)
begin
busy_o <= busy_new;
step <= step_new;
A <= A_new;
B <= B_new;
C <= C_new;
D <= D_new;
E <= E_new;
F <= F_new;
G <= G_new;
H <= H_new;
HKW <= HKW_new;
end
always @*
begin
step_new = 0;
if(~load_i & busy_o)
step_new = step + 1;
end
always @*
begin : HKW_update
reg [31:0] H_pre;
H_pre = G;
if(step == 0)
H_pre = `STATE_LOAD(7);
HKW_new = H_pre + K + W;
end
reg [31:0] T1, T2;
always @*
begin : T1_update
reg [31:0] Ch, S1;
Ch = (E & F) ^ (~E & G);
S1 = {E[5:0],E[31:6]} ^ {E[10:0],E[31:11]} ^ {E[24:0],E[31:25]};
T1 = S1 + Ch + HKW;
end
always @*
begin : T2_update
reg [31:0] Maj, S0;
Maj = (A & (B ^ C)) ^ (B & C);
S0 = {A[1:0],A[31:2]} ^ {A[12:0],A[31:13]} ^ {A[21:0],A[31:22]};
T2 = S0 + Maj;
end
always @*
begin
busy_new = 0;
A_new = A;
B_new = B;
C_new = C;
D_new = D;
E_new = E;
F_new = F;
G_new = G;
H_new = H;
if(load_i)
begin
busy_new = 1;
A_new = `STATE_LOAD(0);
B_new = `STATE_LOAD(1);
C_new = `STATE_LOAD(2);
D_new = `STATE_LOAD(3);
E_new = `STATE_LOAD(4);
F_new = `STATE_LOAD(5);
G_new = `STATE_LOAD(6);
H_new = `STATE_LOAD(7);
end
else if(busy_o)
begin
if(step == SHA256_MAX_STEP + 1)
begin
A_new = A + `STATE_LOAD(0);
B_new = B + `STATE_LOAD(1);
C_new = C + `STATE_LOAD(2);
D_new = D + `STATE_LOAD(3);
E_new = E + `STATE_LOAD(4);
F_new = F + `STATE_LOAD(5);
G_new = G + `STATE_LOAD(6);
H_new = H + `STATE_LOAD(7);
end
else if(step == 0)
begin
busy_new = 1;
A_new = A;
B_new = B;
C_new = C;
D_new = D;
E_new = E;
F_new = F;
G_new = G;
H_new = H;
end
else
begin
busy_new = 1;
A_new = T1 + T2;
B_new = A;
C_new = B;
D_new = C;
E_new = D + T1;
F_new = E;
G_new = F;
H_new = G;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX = 1000011; bool hsh[MAX]; int fact[MAX]; void sieve(int n) { int i, a; for (i = 2; i <= n; i++) hsh[i] = true; for (i = 2; i <= n; i++) if (hsh[i]) { a = 2; fact[i] = i; while (a * i <= n) hsh[a * i] = false, fact[a * i] = i, a++; } } int factorize(int n) { set<int> st; int cnt = 0; while (n > 1) { cnt++; st.insert(fact[n]); n /= fact[n]; } if (cnt == 1) return -1; return *(--st.end()); } int main() { cin.sync_with_stdio(false); int n, m; sieve(1e6); cin >> n; m = factorize(n); if (m == -1) { cout << n; return 0; } int pre = n; int temp = n - m + 1; int ans = INT_MAX; while (n >= temp) { m = factorize(n); if (m == -1) { n--; continue; } ans = min(ans, n - m + 1); n--; } if (ans == INT_MAX) ans = pre; cout << ans; return 0; }
|
// -*- Mode: Verilog -*-
// Filename : display_regs.v
// Description : Seven Segment Display Registers
// Author : Philip Tracton
// Created On : Thu May 28 23:27:56 2015
// Last Modified By: Philip Tracton
// Last Modified On: Thu May 28 23:27:56 2015
// Update Count : 0
// Status : Unknown, Use with caution!
module display_regs (/*AUTOARG*/
// Outputs
data_out, segment0, segment1, segment2, segment3,
// Inputs
clk, reset, port_id, data_in, read_strobe, write_strobe
) ;
parameter BASE_ADDRESS = 8'h00;
input clk;
input reset;
input [7:0] port_id;
input [7:0] data_in;
output [7:0] data_out;
input read_strobe;
input write_strobe;
output [7:0] segment0;
output [7:0] segment1;
output [7:0] segment2;
output [7:0] segment3;
//
// Registers
//
reg [3:0] segment0 = 4'h0;
reg [3:0] segment1 = 4'h0;
reg [3:0] segment2 = 4'h0;
reg [3:0] segment3 = 4'h0;
reg [7:0] data_out = 8'h00;
//
// Address Decode
//
wire segment0_enable = (port_id == (BASE_ADDRESS + 0));
wire segment1_enable = (port_id == (BASE_ADDRESS + 1));
wire segment2_enable = (port_id == (BASE_ADDRESS + 2));
wire segment3_enable = (port_id == (BASE_ADDRESS + 3));
//
// Write Logic
//
always @(posedge clk)
if (write_strobe) begin
if (segment0_enable) begin
segment0 <= data_in;
end
if (segment1_enable) begin
segment1 <= data_in;
end
if (segment2_enable) begin
segment2 <= data_in;
end
if (segment3_enable) begin
segment3 <= data_in;
end
end // if (write_strobe)
//
// Read Logic
//
always @(posedge clk) begin
if (segment0_enable) begin
data_out[3:0] <= segment0[3:0];
end
else if (segment1_enable) begin
data_out[3:0] <= segment1[3:0];
end
else if (segment2_enable) begin
data_out[3:0] <= segment2[3:0];
end
else if (segment3_enable) begin
data_out[3:0] <= segment3[3:0];
end
else begin
data_out <= 8'h00;
end
end // always @ (posedge clk)
endmodule // display_regs
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*
* SVN revision information:
* $Rev:: $:
* $Author:: $:
* $Date:: $:
*
* Initial version: M. Lemarenko
*/
module uart_master(
input UART_CLK_X4,
input UART_RST,
input UART_RX,
output UART_TX,
inout [7:0] BUS_DATA,
output reg [31:0] BUS_ADD,
output reg BUS_WR,
output reg BUS_RD
);
wire clk;
assign clk = UART_CLK_X4;
wire [7:0] data_i;
reg [7:0] data_o;
assign data_i = BUS_DATA;
assign BUS_DATA = BUS_WR ? data_o : 8'bzzzz_zzzz;
reg [7:0] tx_byte;
wire [7:0] rx_byte;
wire is_receiving, is_transmitting, recv_error,received;
reg transmit;
uart u_uart(
// Inputs
.clk_uart_x4(clk),
.rst(UART_RST),
.rx(UART_RX),
.transmit(transmit),
.tx_byte(tx_byte),
// Outputs
.tx(UART_TX),
.received(received),
.rx_byte(rx_byte),
.is_receiving(is_receiving),
.is_transmitting(is_transmitting),
.recv_error(recv_error)
);
integer i;
reg [4:0] STATE, NEXTSTATE;
reg [31:0] cnt;
wire [31:0] block_len;
reg [7:0] block_len_0[3:0];
reg op_done;
wire [31:0] address_0;
reg [7:0] address_0_0[3:0];
//reg [7:0] test_mem [255:0];
wire[7:0] roger_word [2:0];
assign block_len = {block_len_0[3], block_len_0[2], block_len_0[1],block_len_0[0]};
assign address_0 = {address_0_0[3], address_0_0[2], address_0_0[1],address_0_0[0]};
assign roger_word[0] = {8'h4f}; // "OK\n"
assign roger_word[1] = {8'h4B}; // "OK\n"
assign roger_word[2] = {8'h0D}; // "OK\n"
localparam IDLE = 0, //idle :)
SET_LEN = 1, //sets the length of the block to be read
SET_ADD = 2, //sets the start address
READ = 3, //reads a block of mem
WRITE = 4, //writes a block of mem
ROGER = 5; //confirms the reception
////////////////////////////// TAKTBLOCK /////////////////////////////////////
always @(posedge clk or posedge UART_RST)
if (UART_RST) begin
STATE <= IDLE;
end
else begin
STATE <= NEXTSTATE;
end
// END ALWAYS
////////////////////////////// Kombinatorischer Block /////////////////////////////////////
assign uart_busy = is_receiving || is_transmitting;
//reset counter:
//reg rst_counter[31:0];
//
//always @(posedge clk) begin
// rst_counter <= rst_counter + 1;
// if(UART_RST or recv_error) begin
// rst_counter <= 0;
// end
//end
always @* begin
NEXTSTATE = IDLE;
//if (!uart_busy)
case (STATE)
IDLE: begin
if (received) begin
if (rx_byte ==8'h6c) begin // ascii "l"
$write(".........set length\n");
NEXTSTATE = SET_LEN;
end else if (rx_byte ==8'h61) begin // ascii "a"
NEXTSTATE = SET_ADD;
$write(".........set address\n");
end else if (rx_byte==8'h72) begin // ascii "r"
NEXTSTATE = READ;
$write(".........read\n");
end else if (rx_byte==8'h77) begin // ascii "w"
NEXTSTATE = WRITE;
$write(".........write\n");
end else
NEXTSTATE = IDLE;
end
end
SET_LEN:begin
if ((!uart_busy)&&op_done)
NEXTSTATE = ROGER;
else
NEXTSTATE = SET_LEN;
end
SET_ADD:begin
if ((!uart_busy)&&op_done)
NEXTSTATE = ROGER;
else
NEXTSTATE = SET_ADD;
end
READ: begin
if ((!uart_busy)&&op_done)
NEXTSTATE = ROGER;
else
NEXTSTATE = READ;
end
WRITE: begin
if ((!uart_busy)&&op_done)
NEXTSTATE = ROGER;
else
NEXTSTATE = WRITE;
end
ROGER: begin
if ((!uart_busy)&&op_done) begin
NEXTSTATE = IDLE;
$write("ROGER\n");
end else
NEXTSTATE = ROGER;
end
default: begin
NEXTSTATE = IDLE;
end
endcase
end // END ALWAYS
////////////////////////////// Anweisungsblock /////////////////////////////////////
wire new_state_strobe;
assign new_state_strobe = (STATE != NEXTSTATE);
//assign add = address_0+cnt;
always @(posedge clk or posedge UART_RST)
if (UART_RST) begin
cnt <= 0;
op_done <= 0;
transmit <= 0;
BUS_WR <= 0;
BUS_RD <= 0;
address_0_0[3] <= 0;
address_0_0[2] <= 0;
address_0_0[1] <= 0;
address_0_0[0] <= 0;
block_len_0[3] <= 0;
block_len_0[2] <= 0;
block_len_0[1] <= 0;
block_len_0[0] <= 1;
end else if (new_state_strobe) begin
op_done <= 0;
cnt <= 0;
BUS_WR <= 0;
transmit <= 0;
BUS_RD <= 0;
end else begin
case (STATE)
IDLE: begin
end
SET_LEN:begin
if (cnt > 3)
op_done <=1;
else if (received) begin
$write("setting the length byte %d to value %d\n",cnt,rx_byte);
block_len_0[cnt] <= rx_byte;
cnt <= cnt+1;
end
end
SET_ADD:begin
if (cnt > 3)
op_done <=1;
else if (received) begin
$write("setting the address byte %d to value %d\n",cnt,rx_byte);
address_0_0[cnt] <= rx_byte;
cnt <= cnt+1;
end
end
READ: begin
//slow down the clk by 4 to get enogh time to update the value
//hence cnt/4 and cnt[1:0]==3
if(is_transmitting)
transmit <= 0;
else if (cnt/4 >= block_len)
op_done <= 1;
else if ((!is_transmitting)&&(!transmit)) begin
if (cnt[1:0]==3) begin
// $write("transmitting the byte %d of value %d\n",cnt/4,tx_byte);
transmit <= 1;
end
tx_byte <= data_i;
BUS_ADD <= address_0+cnt/4;
cnt <= cnt + 1;
BUS_RD <= 1;
end
end
WRITE: begin
if (cnt >= block_len)
op_done <=1;
else if (received) begin
$write("setting the byte %d to value %d\n",cnt,rx_byte);
//test_mem[address_0+cnt] <= rx_byte;
BUS_ADD <= address_0+cnt;
BUS_WR <= 1;
cnt <= cnt + 1;
data_o <= rx_byte;
end
end
ROGER: begin
if(is_transmitting)
transmit <= 0;
else if (cnt > 2) begin
op_done <=1;
end else if ((!is_transmitting)&&(!transmit)) begin
tx_byte <= roger_word[cnt];
cnt <= cnt + 1;
transmit <= 1;
end
end
default: begin
end
endcase // STATE
end
endmodule
|
// wasca_mm_interconnect_0_avalon_st_adapter_001.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 193
`timescale 1 ps / 1 ps
module wasca_mm_interconnect_0_avalon_st_adapter_001 #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 34,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [33:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
wasca_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1010; char s[100]; bool ops[256]; int relabel[N * 6]; int va[N * 6][2]; int typ[N * 6]; bool vis[N * 6], beres[N * 6]; string detail[N * 6]; map<string, int> ex; map<pair<pair<int, int>, int>, int> rel; vector<string> ans; char usea; int usev; string nxtvar() { while (true) { string cur = string() + usea + to_string(usev); if (!ex.count(cur)) { ex.insert(make_pair(cur, 0)); return cur; } if (++usev == 1000) { usev = 0; ++usea; } } } int strcnt; int gid(const string& str) { auto it = ex.find(str); if (it != ex.end()) return it->second; ex.insert(make_pair(str, ++strcnt)); detail[strcnt] = str; return strcnt; } int nid(const string& str) { detail[++strcnt] = str; return ex[str] = strcnt; } void dfs(int u) { if (vis[u]) return; vis[u] = true; if (typ[u] == 0) { relabel[u] = u; return; } if (typ[u] == -1) { if (beres[u]) { if (typ[va[u][0]]) { beres[va[u][0]] = true; } else { if (detail[va[u][0]] != res ) ans.push_back( res= + detail[va[u][0]]); return; } } dfs(va[u][0]); relabel[u] = relabel[va[u][0]]; return; } dfs(va[u][0]); dfs(va[u][1]); pair<pair<int, int>, int> spec( make_pair(relabel[va[u][0]], relabel[va[u][1]]), typ[u]); relabel[u] = u; if (!rel.count(spec)) { rel.insert(make_pair(spec, u)); detail[u] = nxtvar(); ans.push_back((beres[u] ? string( res ) : detail[u]) + = + detail[relabel[va[u][0]]] + char(typ[u]) + detail[relabel[va[u][1]]]); } else relabel[u] = rel[spec]; } int main() { usea = a ; usev = 0; ops[ $ ] = true; ops[ ^ ] = true; ops[ # ] = true; ops[ & ] = true; int t; scanf( %d , &t); while (t--) { scanf( %s , s); char *p1 = s, *p2; while (*p1 != = ) ++p1; string a(s, p1); p2 = p1; while (!ops[*p2] && *p2) ++p2; if (ops[*p2]) { string b(p1 + 1, p2), c(p2 + 1); int bi = gid(b), ci = gid(c); int ai = nid(a); typ[ai] = *p2; va[ai][0] = bi; va[ai][1] = ci; } else { string b(p1 + 1); int bi = gid(b); int ai = nid(a); typ[ai] = -1; va[ai][0] = bi; } } int resi = gid( res ); beres[resi] = true; dfs(resi); printf( %lu n , ans.size()); for (auto str : ans) puts(str.c_str()); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAX = 1e5 + 10; const int MAXN = 1e4 + 10; const int MOD = 1e9 + 7; const int inf = 1e9; const double pi = acos(-1.0); const double eps = 1e-6; int dx[] = {0, -1, 0, 1}; int dy[] = {1, 0, -1, 0}; int x, y; int main() { ios::sync_with_stdio(false); cin.tie(0); int a, b, c; cin >> x >> y; a = b = c = y; int res = 0; while (a < x || b < x || c < x) { int maxa = max(a, max(b, c)); int maxc = min(a, min(b, c)); int maxb = a + b + c - maxa - maxc; int l = maxa + maxb - maxc - 1; if (a == maxc) a += l; else if (b == maxc) b += l; else c += l; res++; } cout << res; return 0; }
|
//Instruction decoder
`include "verilog/riscv_instr_defines.v"
module decode
(
input wire[31:0] instr_dec_i,
output wire[4:0] rs1_dec_o,
output wire[4:0] rs2_dec_o,
output wire[4:0] rd_dec_o,
output wire[6:0] op_dec_o,
output wire[2:0] funct3_dec_o,
output wire[6:0] funct7_dec_o,
output wire is_r_type_dec_o,
output wire is_i_type_dec_o,
output wire is_s_type_dec_o,
output wire is_b_type_dec_o,
output wire is_u_type_dec_o,
output wire is_j_type_dec_o,
output wire[11:0] i_type_imm_dec_o,
output wire[11:0] s_type_imm_dec_o,
output wire[11:0] b_type_imm_dec_o,
output wire[19:0] u_type_imm_dec_o,
output wire[19:0] j_type_imm_dec_o
);
//Populate the output fields using the input instruction
wire[4:0] rs1_dec;
wire[4:0] rs2_dec;
wire[4:0] rd_dec;
wire[6:0] op_dec;
wire[2:0] funct3_dec;
wire[6:0] funct7_dec;
reg is_r_type_dec;
reg is_i_type_dec;
reg is_s_type_dec;
reg is_b_type_dec;
reg is_u_type_dec;
reg is_j_type_dec;
wire[11:0] i_type_imm_dec;
wire[11:0] s_type_imm_dec;
wire[11:0] b_type_imm_dec;
wire[19:0] u_type_imm_dec;
wire[19:0] j_type_imm_dec;
assign rs1_dec_o = rs1_dec;
assign rs2_dec_o = rs2_dec;
assign rd_dec_o = rd_dec;
assign op_dec_o = op_dec;
assign funct3_dec_o = funct3_dec;
assign funct7_dec_o = funct7_dec;
assign is_r_type_dec_o = is_r_type_dec;
assign is_i_type_dec_o = is_i_type_dec;
assign is_s_type_dec_o = is_s_type_dec;
assign is_b_type_dec_o = is_b_type_dec;
assign is_u_type_dec_o = is_u_type_dec;
assign is_j_type_dec_o = is_j_type_dec;
assign i_type_imm_dec_o = i_type_imm_dec;
assign s_type_imm_dec_o = s_type_imm_dec;
assign b_type_imm_dec_o = b_type_imm_dec;
assign u_type_imm_dec_o = u_type_imm_dec;
assign j_type_imm_dec_o = j_type_imm_dec;
assign rd_dec = instr_dec_i[11:7];
assign rs1_dec = instr_dec_i[19:15];
assign rs2_dec = instr_dec_i[24:20];
assign op_dec = instr_dec_i[6:0];
assign funct3_dec = instr_dec_i[14:12];
assign funct7_dec = instr_dec_i[31:25];
always @ *
begin
is_r_type_dec = 1'b0;
is_i_type_dec = 1'b0;
is_s_type_dec = 1'b0;
is_b_type_dec = 1'b0;
is_u_type_dec = 1'b0;
is_j_type_dec = 1'b0;
case (op_dec)
`R_TYPE: is_r_type_dec = 1'b1;
`I_TYPE_0,
`I_TYPE_1: is_i_type_dec = 1'b1;
`S_TYPE: is_s_type_dec = 1'b1;
`B_TYPE: is_b_type_dec = 1'b1;
`AUIPC,
`LUI: is_u_type_dec = 1'b1;
`J_TYPE: is_j_type_dec = 1'b1;
endcase
end
assign i_type_imm_dec = instr_dec_i[31:20];
assign s_type_imm_dec = {instr_dec_i[31:25], instr_dec_i[11:7]};
assign b_type_imm_dec = {instr_dec_i[31], instr_dec_i[7],
instr_dec_i[30:25],
instr_dec_i[11:8]};
assign u_type_imm_dec = instr_dec_i[31:12];
assign j_type_imm_dec = {instr_dec_i[31], instr_dec_i[19:12],
instr_dec_i[20], instr_dec_i[30:21]};
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; ++i) { cin >> a[i]; } sort(a.begin(), a.end()); bool ok = true; int cur = -1; int q = 0; for (int i = 0; i < n; ++i) { if (q == 0) { if (cur != -1 && a[i] != a[i - 1]) { ok = false; break; } q = 1; cur = a[i]; } else { if (cur == a[i]) { ++q; } else { if (cur == a[i] - 1) { --q; } else { ok = false; break; } } } } ok &= q == 0; if (ok) { cout << YES n ; } else { cout << NO n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR4_TB_V
`define SKY130_FD_SC_HD__OR4_TB_V
/**
* or4: 4-input OR.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__or4.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_hd__or4 dut (.A(A), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR4_TB_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e+5 + 10; long long b[MAXN], l[MAXN], r[MAXN], o[MAXN], dp[MAXN]; int main() { int n; cin >> n; for (int i = 0; i < n - 1; i++) { cin >> b[i]; } for (int i = 1; i < n; i++) { l[i] = b[i - 1] - (b[i - 1] % 2) + l[i - 1]; if (b[i - 1] == 1) l[i] = 0; } for (int i = n - 2; i > -1; i--) { r[i] = b[i] - (b[i] % 2) + r[i + 1]; if (b[i] == 1) r[i] = 0; } for (int i = 1; i < n; i++) { o[i] = o[i - 1] + b[i - 1] - (b[i - 1] % 2 == 0); } long long ans = 0, m = 0; for (int i = 0; i < n; i++) { m = max(m, l[i] - o[i]); ans = max(ans, r[i] + o[i] + m); } cout << ans; return 0; }
|
/////////////////////////////////////////////////////////////////////
//// ////
//// FIFO 4 entries deep ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/sasc/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: sasc_fifo4.v,v 1.1.1.1 2002/09/16 16:16:41 rudi Exp $
//
// $Date: 2002/09/16 16:16:41 $
// $Revision: 1.1.1.1 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: sasc_fifo4.v,v $
// Revision 1.1.1.1 2002/09/16 16:16:41 rudi
// Initial Checkin
//
//
//
//
//
//
`timescale 1ns / 100ps
// 4 entry deep fast fifo
module sasc_fifo4(/*AUTOARG*/
// Outputs
dout, full, empty,
// Inputs
clk, rst_n, clr, din, we, re
);
input clk, rst_n;
input clr;
input [7:0] din;
input we;
output [7:0] dout;
input re;
output full, empty;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [7:0] mem[0:3];
reg [1:0] wp;
reg [1:0] rp;
wire [1:0] wp_p1;
wire [1:0] rp_p1;
wire full, empty;
reg gb;
// wire [7:0] mem0 = mem[0];
// wire [7:0] mem1 = mem[1];
// wire [7:0] mem2 = mem[2];
// wire [7:0] mem3 = mem[3];
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
always @(posedge clk or negedge rst_n)
if(!rst_n) wp <= 2'h0;
else
if(clr) wp <= 2'h0;
else
if(we) wp <= wp_p1;
assign wp_p1 = wp + 2'h1;
always @(posedge clk or negedge rst_n)
if(!rst_n) rp <= 2'h0;
else
if(clr) rp <= 2'h0;
else
if(re) rp <= rp_p1;
assign rp_p1 = rp + 2'h1;
// Fifo Output
assign dout = mem[ rp ];
// Fifo Input
always @(posedge clk)
if(we) mem[ wp ] <= din;
// Status
assign empty = (wp == rp) & !gb;
assign full = (wp == rp) & gb;
// Guard Bit ...
always @(posedge clk)
if(!rst_n) gb <= 1'b0;
else
if(clr) gb <= 1'b0;
else
if((wp_p1 == rp) & we) gb <= 1'b1;
else
if(re) gb <= 1'b0;
endmodule
|
module edge_detect(
input clk, //输入系统时钟
input rst_n, //复位信号，低电平有效
input rx_int, //需要检测的输入信号
output pos_rx_int, //检测到上升沿信号
output neg_rx_int, //检测到下降沿信号
output doub_rx_int //双边检测信号
);
reg rx_int0,rx_int1,rx_int2; //在内部新建寄存器，用来暂存数据信号
//若这里只用到两个寄存器变量，那么边沿检测信号是实时输出的
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
rx_int0 <= 1'b0;
rx_int1 <= 1'b0;
rx_int2 <= 1'b0;
end
else
begin
rx_int0 <= rx_int; //初始值信号赋值给0
rx_int1 <= rx_int0; //0的前一个周期的信号赋给1
rx_int2 <= rx_int1; //1的前一个周期的信号赋给2
end
end
assign pos_rx_int = rx_int1 & ~rx_int2; //前一个周期的信号为0，当前周期信号为1，则上升沿检测信号为1（有效），即检测到一个上升沿信号
assign neg_rx_int = ~rx_int1 & rx_int2; //前一个周期的信号为1，当前周期信号为0，则下降沿检测信号为1（有效），即检测到一个下降沿信号
assign doub_rx_int = rx_int1 ^ rx_int2; //两次变量发生变化时，双边检测信号为1（有效），即检测到上升沿、和下降沿信号
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:27:45 02/22/2015
// Design Name:
// Module Name: NormaliseAdder
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module NormaliseAdderProcess(
input [31:0] z_postAddState,
input [3:0] Opcode_AddState,
input idle_AddState,
input [31:0] sout_AddState,
input [27:0] sum_AddState,
input [7:0] InsTagAdder,
input clock,
output reg idle_NormaliseSum,
output reg [31:0] sout_NormaliseSum,
output reg [27:0] sum_NormaliseSum,
output reg [3:0] Opcode_NormaliseSum,
output reg [31:0] z_postNormaliseSum,
output reg [7:0] InsTagNormaliseAdder
);
parameter no_idle = 1'b0,
put_idle = 1'b1;
wire [7:0] s_exponent;
assign s_exponent = sout_AddState[30:23];
parameter sin_cos = 4'd0,
sinh_cosh = 4'd1,
arctan = 4'd2,
arctanh = 4'd3,
exp = 4'd4,
sqr_root = 4'd5, // Pre processed input is given 4'd11
// This requires pre processing. x = (a+1)/2 and y = (a-1)/2
division = 4'd6,
tan = 4'd7, // This is iterative. sin_cos followed by division.
tanh = 4'd8, // This is iterative. sinh_cosh followed by division.
nat_log = 4'd9, // This requires pre processing. x = (a+1) and y = (a-1)
hypotenuse = 4'd10,
PreProcess = 4'd11;
always @ (posedge clock)
begin
InsTagNormaliseAdder <= InsTagAdder;
z_postNormaliseSum <= z_postAddState;
Opcode_NormaliseSum <= Opcode_AddState;
//if(Opcode_AddState == PreProcess) begin
idle_NormaliseSum <= idle_AddState;
if (idle_AddState != put_idle) begin
sout_NormaliseSum[31] <= sout_AddState[31];
sout_NormaliseSum[22:0] <= sout_AddState[22:0];
if (sum_AddState[27] == 1'b1) begin
sout_NormaliseSum[30:23] <= s_exponent + 1;
sum_NormaliseSum <= sum_AddState >> 1;
end
else if(sum_AddState[26:3] == 24'h000000) begin
sout_NormaliseSum[30:23] <= 10'h382;
end
else if (sum_AddState[26:4] == 23'h000000) begin
sout_NormaliseSum[30:23] <= s_exponent - 23;
sum_NormaliseSum <= sum_AddState << 23;
end
else if (sum_AddState[26:5] == 22'h000000) begin
sout_NormaliseSum[30:23] <= s_exponent - 22;
sum_NormaliseSum <= sum_AddState << 22;
end
else if (sum_AddState[26:6] == 21'h000000) begin
sout_NormaliseSum[30:23] <= s_exponent - 21;
sum_NormaliseSum <= sum_AddState << 21;
end
else if (sum_AddState[26:7] == 20'h00000) begin
sout_NormaliseSum[30:23] <= s_exponent - 20;
sum_NormaliseSum <= sum_AddState << 20;
end
else if (sum_AddState[26:8] == 19'h00000) begin
sout_NormaliseSum[30:23] <= s_exponent - 19;
sum_NormaliseSum <= sum_AddState << 19;
end
else if (sum_AddState[26:9] == 18'h00000) begin
sout_NormaliseSum[30:23] <= s_exponent - 18;
sum_NormaliseSum <= sum_AddState << 18;
end
else if (sum_AddState[26:10] == 17'h00000) begin
sout_NormaliseSum[30:23] <= s_exponent - 17;
sum_NormaliseSum <= sum_AddState << 17;
end
else if (sum_AddState[26:11] == 16'h0000) begin
sout_NormaliseSum[30:23] <= s_exponent - 16;
sum_NormaliseSum <= sum_AddState << 16;
end
else if (sum_AddState[26:12] == 15'h0000) begin
sout_NormaliseSum[30:23] <= s_exponent - 15;
sum_NormaliseSum <= sum_AddState << 15;
end
else if (sum_AddState[26:13] == 14'h0000) begin
sout_NormaliseSum[30:23] <= s_exponent - 14;
sum_NormaliseSum <= sum_AddState << 14;
end
else if (sum_AddState[26:14] == 13'h0000) begin
sout_NormaliseSum[30:23] <= s_exponent - 13;
sum_NormaliseSum <= sum_AddState << 13;
end
else if (sum_AddState[26:15] == 12'h000) begin
sout_NormaliseSum[30:23] <= s_exponent - 12;
sum_NormaliseSum <= sum_AddState << 12;
end
else if (sum_AddState[26:16] == 11'h000) begin
sout_NormaliseSum[30:23] <= s_exponent - 11;
sum_NormaliseSum <= sum_AddState << 11;
end
else if (sum_AddState[26:17] == 10'h000) begin
sout_NormaliseSum[30:23] <= s_exponent - 10;
sum_NormaliseSum <= sum_AddState << 10;
end
else if (sum_AddState[26:18] == 9'h0000) begin
sout_NormaliseSum[30:23] <= s_exponent - 9;
sum_NormaliseSum <= sum_AddState << 9;
end
else if (sum_AddState[26:19] == 8'h00) begin
sout_NormaliseSum[30:23] <= s_exponent - 8;
sum_NormaliseSum <= sum_AddState << 8;
end
else if (sum_AddState[26:20] == 7'h00) begin
sout_NormaliseSum[30:23] <= s_exponent - 7;
sum_NormaliseSum <= sum_AddState << 7;
end
else if (sum_AddState[26:21] == 6'h00) begin
sout_NormaliseSum[30:23] <= s_exponent - 6;
sum_NormaliseSum <= sum_AddState << 6;
end
else if (sum_AddState[26:22] == 5'h00) begin
sout_NormaliseSum[30:23] <= s_exponent - 5;
sum_NormaliseSum <= sum_AddState << 5;
end
else if (sum_AddState[26:23] == 4'h0) begin
sout_NormaliseSum[30:23] <= s_exponent - 4;
sum_NormaliseSum <= sum_AddState << 4;
end
else if (sum_AddState[26:24] == 3'h0) begin
sout_NormaliseSum[30:23] <= s_exponent - 3;
sum_NormaliseSum <= sum_AddState << 3;
end
else if (sum_AddState[26:25] == 2'h0) begin
sout_NormaliseSum[30:23] <= s_exponent - 2;
sum_NormaliseSum <= sum_AddState << 2;
end
else if (sum_AddState[26] == 1'h0) begin
sout_NormaliseSum[30:23] <= s_exponent - 1;
sum_NormaliseSum <= sum_AddState << 1;
end
else begin
sout_NormaliseSum[30:23] <= s_exponent;
sum_NormaliseSum <= sum_AddState;
end
end
else begin
sout_NormaliseSum <= sout_AddState;
sum_NormaliseSum <= 0;
end
//end
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
//
// Module: generic_cntr_reg.v
// Project: NF2.1
// Author: Jad Naous/Glen Gibb
// Description: Implements a generic counter register block that uses RAM and
// temporarily stores updates in registers before committing them to RAM.
//
// This design is efficient in that the update registers are kept small so one
// large adder can be shared amongst all registers. The routing resources
// associated with the RAM simplifies the routing of the registers.
// Demultiplexes, stores and serves register requests
//
// To use this block you should specify a number of parameters at
// instantiation:
// TAG -- the tag to match against (probably defined in udp_defines.v)
// REG_ADDR_WIDTH -- width of the address block allocated to this register
// group. It is important that this is specified correctly
// as this width is used to enable tag matching
// NUM_REGS_USED -- how many registers in this block?
// NUM_INSTANCES -- how many instances of the counters shall we emulate
//
// Other parameter which may be useful
// INPUT_WIDTH -- width of each update input
// MIN_UPDATE_INTERVAL -- how many clock cycles between successive update
// inputs
// RESET_ON_READ -- reset registers when read
//
// Last Modified: 2/22/08 by Jad Naous to allow decrements and to not ack addresses
// that are not found.
// 3/29/08 by Jad Naous to force reg file into bram
// 4/14/08 by Jad Naous to make bram write-first, fixing an issue
///////////////////////////////////////////////////////////////////////////////
module generic_cntr_regs
#(
parameter UDP_REG_SRC_WIDTH = 2,
parameter TAG = 0, // Tag to match against
parameter REG_ADDR_WIDTH = 5, // Width of block addresses
parameter NUM_REGS_USED = 8, // How many registers
parameter REG_START_ADDR = 0, // Address of the first counter
parameter INPUT_WIDTH = 1, // Width of each update request
parameter MIN_UPDATE_INTERVAL = 8, // Clocks between successive inputs
parameter REG_WIDTH = `CPCI_NF2_DATA_WIDTH, // How wide should each counter be?
parameter RESET_ON_READ = 0,
// Don't modify the parameters below. They are used to calculate the
// widths of the various register inputs/outputs.
parameter REG_END_ADDR = REG_START_ADDR + NUM_REGS_USED, // address of last counter + 1
parameter UPDATES_START = REG_START_ADDR * INPUT_WIDTH, // first bit of the updates vector
parameter UPDATES_END = REG_END_ADDR * INPUT_WIDTH // bit after last bit of the updates vector
)
(
input reg_req_in,
input reg_ack_in,
input reg_rd_wr_L_in,
input [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in,
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in,
input [UDP_REG_SRC_WIDTH-1:0] reg_src_in,
output reg reg_req_out,
output reg reg_ack_out,
output reg reg_rd_wr_L_out,
output reg [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_out,
output reg [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_out,
output reg [UDP_REG_SRC_WIDTH-1:0] reg_src_out,
// --- update interface
input [UPDATES_END - 1:UPDATES_START] updates,
input [REG_END_ADDR-1:REG_START_ADDR] decrement, // if 1 then subtract the update, else add.
input clk,
input reset
);
`LOG2_FUNC
`CEILDIV_FUNC
// ------------- Internal parameters --------------
localparam MIN_CYCLE_TIME = NUM_REGS_USED + 1;
// Calculate the number of updates we can see in a single cycle through the
// RAM.
//
// This should be:
// ceil(MIN_CYCLE_TIME / MIN_UPDATE_INTERVAL)
localparam UPDATES_PER_CYCLE = ceildiv(MIN_CYCLE_TIME, MIN_UPDATE_INTERVAL);
localparam LOG_UPDATES_PER_CYCLE = log2(UPDATES_PER_CYCLE);
// Calculate how much storage to allocate for each delta
//
// A single update requires INPUT_WIDTH bits of storage
// In the worst case we would add the updates and get a total of
// (2^INPUT_WIDTH - 1) * UPDATES_PER_CYCLE
// This can be represented in:
// log2( (2^INPUT_WIDTH - 1) * UPDATES_PER_CYCLE )
// = INPUT_WIDTH + log2(UPDATES_PER_CYCLE)
// we add one for sign extension.
localparam DELTA_WIDTH = INPUT_WIDTH + LOG_UPDATES_PER_CYCLE + 1;
localparam RESET = 0,
NORMAL = 1;
// ------------- Wires/reg ------------------
reg [REG_WIDTH-1:0] reg_file [REG_START_ADDR:REG_END_ADDR-1];
wire [REG_ADDR_WIDTH-1:0] addr, addr_d1;
wire [`UDP_REG_ADDR_WIDTH-REG_ADDR_WIDTH-1:0] tag_addr;
reg [REG_ADDR_WIDTH-1:0] reg_cnt;
wire [REG_ADDR_WIDTH-1:0] reg_cnt_nxt;
wire [REG_ADDR_WIDTH-1:0] reg_file_rd_addr;
reg [REG_ADDR_WIDTH-1:0] reg_file_rd_addr_ram;
wire [REG_ADDR_WIDTH-1:0] reg_file_wr_addr;
reg [DELTA_WIDTH-1:0] deltas[REG_START_ADDR:REG_END_ADDR-1];
wire [DELTA_WIDTH-1:0] delta;
wire [DELTA_WIDTH-1:0] update[REG_START_ADDR:REG_END_ADDR-1];
wire [REG_WIDTH-1:0] reg_file_out;
reg [REG_WIDTH-1:0] reg_file_in;
reg reg_file_wr_en;
reg [REG_ADDR_WIDTH-1:0] reg_cnt_d1;
reg reg_rd_req_good_d1, reg_wr_req_good_d1;
reg [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in_d1;
reg [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in_d1;
reg reg_req_in_d1;
reg reg_ack_in_d1;
reg reg_rd_wr_L_in_d1;
reg [UDP_REG_SRC_WIDTH-1:0] reg_src_in_d1;
integer i;
reg state;
// -------------- Logic --------------------
assign addr = reg_addr_in[REG_ADDR_WIDTH-1:0];
assign addr_d1 = reg_addr_in_d1[REG_ADDR_WIDTH-1:0];
assign tag_addr = reg_addr_in[`UDP_REG_ADDR_WIDTH - 1:REG_ADDR_WIDTH];
assign addr_good = addr < REG_END_ADDR && addr >= REG_START_ADDR;
assign tag_hit = tag_addr == TAG;
assign reg_rd_req_good = (tag_hit && addr_good && reg_req_in && reg_rd_wr_L_in);
assign reg_wr_req_good = (tag_hit && addr_good && reg_req_in && ~reg_rd_wr_L_in);
assign reg_cnt_nxt = (reg_cnt==REG_END_ADDR-1'b1) ? REG_START_ADDR : reg_cnt + 1'b1;
assign delta = deltas[reg_cnt_d1];
assign reg_file_rd_addr = reg_rd_req_good ? addr : reg_cnt;
assign reg_file_wr_addr = (state == RESET
? reg_cnt
: (reg_wr_req_good_d1 || reg_rd_req_good_d1)
? addr_d1 : reg_cnt_d1);
// choose when and what to write in the ram
always @(*) begin
reg_file_in = reg_file_out + {{(REG_WIDTH - DELTA_WIDTH){delta[DELTA_WIDTH-1]}}, delta};
reg_file_wr_en = 0;
if(state == RESET || (reg_rd_req_good_d1 && RESET_ON_READ)) begin
reg_file_wr_en = 1;
reg_file_in = 0;
end
else if(!reg_wr_req_good_d1 && !reg_rd_req_good_d1) begin
reg_file_wr_en = 1;
end
else if(reg_wr_req_good_d1) begin
reg_file_in = reg_data_in_d1;
reg_file_wr_en = 1;
end
end // always @ (*)
// Generate the individual update lines from the updates vector
//
// Note: I have the ugly bit selection because ModelSim doesn't seem to
// like parameters used in :+ selects! :-(
generate
genvar j;
for (j = REG_START_ADDR; j < REG_END_ADDR; j = j + 1) begin : update_gen
assign update[j] = {{(DELTA_WIDTH - INPUT_WIDTH){1'b0}}, updates[(j + 1) * INPUT_WIDTH - 1 : j * INPUT_WIDTH]};
end
endgenerate
/*********** RAM *************/
always @(posedge clk) begin
// write to the register file
if(reg_file_wr_en) begin
reg_file[reg_file_wr_addr] <= reg_file_in;
end
reg_file_rd_addr_ram <= reg_file_rd_addr;
end
assign reg_file_out = reg_file[reg_file_rd_addr_ram];
/****************************/
// State machine that handles register access from the CPU
always @(posedge clk) begin
if(reset) begin
reg_cnt <= REG_START_ADDR;
reg_rd_req_good_d1 <= 0;
reg_wr_req_good_d1 <= 0;
reg_req_in_d1 <= 0;
reg_ack_out <= 0;
reg_req_out <= 0;
state <= RESET;
for (i = REG_START_ADDR; i < REG_END_ADDR; i = i + 1) begin
deltas[i] <= 0;
end
end // if (reset)
else begin
reg_cnt_d1 <= reg_cnt;
if(state == RESET) begin
reg_cnt <= reg_cnt_nxt;
if(reg_cnt == REG_END_ADDR-1'b1) begin
state <= NORMAL;
end
end
else begin
/*********************************************************************
* first stage - read bram, latch reg req signals
*/
reg_cnt <= (reg_rd_req_good || reg_wr_req_good) ? reg_cnt : reg_cnt_nxt;
reg_rd_req_good_d1 <= reg_rd_req_good;
reg_wr_req_good_d1 <= reg_wr_req_good;
reg_addr_in_d1 <= reg_addr_in;
reg_data_in_d1 <= reg_data_in;
reg_req_in_d1 <= reg_req_in;
reg_ack_in_d1 <= reg_ack_in;
reg_rd_wr_L_in_d1 <= reg_rd_wr_L_in;
reg_src_in_d1 <= reg_src_in;
// synthesis translate_off
if(reg_ack_in && (reg_rd_req_good || reg_wr_req_good)) begin
$display("%t %m ERROR: Register request already ack even though", $time);
$display("it should be destined to this module. This can happen");
$display("if two modules have aliased register addresses.");
$stop;
end
// synthesis translate_on
/********************************************************************
* second stage - output rd req or do write req or delta update
*/
reg_ack_out <= reg_rd_req_good_d1 || reg_wr_req_good_d1 || reg_ack_in_d1;
reg_data_out <= reg_rd_req_good_d1 ? reg_file_out : reg_data_in_d1;
reg_addr_out <= reg_addr_in_d1;
reg_req_out <= reg_req_in_d1;
reg_rd_wr_L_out <= reg_rd_wr_L_in_d1;
reg_src_out <= reg_src_in_d1;
/*******************************************************************
* update the deltas
*/
for (i = REG_START_ADDR; i < REG_END_ADDR; i = i + 1) begin
// if we just update the register corresponding to this delta then
// clear it.
if ((i==reg_cnt_d1) // this delta was committed to reg_file
&& !reg_wr_req_good_d1 // we didn't write in this cycle
&& !(reg_rd_req_good_d1 && RESET_ON_READ) // we didn't read and reset
) begin
deltas[i] <= decrement[i] ? -update[i] : update[i];
end
else begin
deltas[i] <= decrement[i] ? deltas[i] - update[i] : deltas[i] + update[i];
end
end // for (i = REG_START_ADDR; i < REG_END_ADDR; i = i + 1)
end // else: !if(state == RESET)
end // else: !if(reset)
end // always @ (posedge clk)
endmodule
|
#include <bits/stdc++.h> int n; char str[50]; int F[50], sz[50]; inline int find(int x) { return x == F[x] ? x : F[x] = find(F[x]); } inline void merge(int x, int y) { x = find(x); y = find(y); if (x == y) return; F[y] = x; sz[x] += sz[y]; } std::vector<int> G[55]; int id[66]; int e[25]; int f[(1 << 23) + 5], g[(1 << 23) + 5], coe[(1 << 23) + 5]; int main() { scanf( %d , &n); for (int i = 0; i <= n - 1; ++i) F[i] = i, sz[i] = 1; for (int i = 0; i <= n - 1; ++i) { scanf( %s , str); for (int j = i + 1; j <= n - 1; ++j) { if (str[j] == A ) merge(i, j); if (str[j] == X ) G[i].emplace_back(j), G[j].emplace_back(i); } } int ans = n - 1; n = 0; for (int i = 0; i <= ans; ++i) id[i] = find(i); for (int i = 0; i <= ans; ++i) for (auto x : G[i]) if (id[i] == id[x]) { puts( -1 ); exit(0); } for (int i = 0; i <= ans; ++i) { if (sz[id[i]] == 1) { id[i] = -1; continue; } if (id[i] != i) { id[i] = id[id[i]]; continue; } id[i] = n++; } if (n <= 1) { printf( %d n , ans + n); return 0; } assert(n <= 23); for (int i = 0; i <= ans; ++i) for (auto x : G[i]) if (~id[i] && ~id[x]) e[id[i]] |= (1 << id[x]); f[0] = coe[0] = 1; for (int S = 1; S <= (1 << n) - 1; ++S) { int lb = __builtin_ctz(S); f[S] = (!(e[lb] & S)) & f[S ^ (1 << lb)]; coe[S] = -coe[S ^ (1 << lb)]; } for (int i = 0; i <= n - 1; ++i) { for (int S = 0; S <= (1 << n) - 1; ++S) { if ((S >> i) & 1) f[S] += f[S ^ (1 << i)]; } } for (int i = 0; i <= (1 << n) - 1; ++i) g[i] = f[i]; for (int k = 1; k <= n; ++k) { auto chk = [&]() { int ans = 0; for (int S = 0; S <= (1 << n) - 1; ++S) ans += g[S] * coe[S]; return ans != 0; }; if (chk()) { printf( %d n , ans + k); return 0; } for (int S = 0; S <= (1 << n) - 1; ++S) g[S] *= f[S]; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFRTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__SDFRTP_BEHAVIORAL_PP_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hvl__udp_dff_pr_pp_pg_n.v"
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_hvl__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire buf0_out_Q ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out , D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign cond0 = ( RESET_B_delayed === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) & cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) & cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) & cond0 );
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFRTP_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, s; cin >> n >> s; map<int, long long> sale; map<int, long long> buy; for (int i = 0; i < n; i++) { char c; cin >> c; if (c == B ) { int price, num; cin >> price >> num; buy[price] += num; } else { int price, num; cin >> price >> num; sale[price] += num; } } auto itb = sale.begin(); stack<pair<long long, long long>> answ; for (int i = 0; i < min(int(sale.size()), s); i++) { answ.push((*itb)); itb++; } while (!answ.empty()) { cout << S << << answ.top().first << << answ.top().second << endl; answ.pop(); } auto its = buy.end(); for (int i = 0; i < min(int(buy.size()), s); i++) { its--; cout << B << << (*its).first << << (*its).second << endl; } cin >> n; return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> using min_pq = priority_queue<T, vector<T>, greater<T>>; const int MAXN = 1e5 + 10, MAXQ = 3e5 + 10, MAXL = 18, ALP = 26, MOD = 1e9 + 7, MAXK = 17, MAXA = 10, MAXB = 24, MAXBB = (1 << MAXB); const string no = NO n , yes = YES n ; const int hA[4] = {1, 0, -1, 0}, kA[4] = {0, 1, 0, -1}; const int INF = 1e9 + 10; int n, par[MAXN], md[MAXN], st[MAXN], tt = 0; vector<int> adj[MAXN]; int dfs1(int c = 0) { md[c] = 1; for (auto nxt : adj[c]) md[c] = max(md[c], dfs1(nxt) + 1); return md[c]; } void dfs2(int c = 0) { sort(adj[c].begin(), adj[c].end(), [&](int i, int j) { return md[i] < md[j]; }); st[tt++] = c; for (auto nxt : adj[c]) dfs2(nxt); } void solve() { cin >> n; for (int i = 1; i < n; i++) { cin >> par[i], adj[par[i]].push_back(i); } dfs1(), dfs2(); vector<int> ans; ans.reserve(n); for (int i = 1; i < n; i++) { for (int a = st[i], b = st[i - 1]; b != par[a]; b = par[b]) ans.push_back(a); } for (int i = 0; i < n; i++) cout << st[i] << ; cout << n ; cout << (int)ans.size() << n ; for (int c : ans) cout << c << ; cout << n ; } int main() { ios::sync_with_stdio(false); cin.tie(0); int t_c = 1; while (t_c--) solve(); }
|
#include <bits/stdc++.h> using namespace std; const int N = 1000 * 100 + 20; int main() { ios::sync_with_stdio(false), cin.tie(0), cout.tie(0); int t; cin >> t; while (t--) { long long n, k; cin >> n >> k; if (k % 2 == n % 2 && (k * k) <= n) cout << YES << endl; else cout << NO << endl; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLXTN_TB_V
`define SKY130_FD_SC_MS__DLXTN_TB_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dlxtn.v"
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg GATE_N;
initial
begin
GATE_N = 1'b0;
end
always
begin
#5 GATE_N = ~GATE_N;
end
sky130_fd_sc_ms__dlxtn dut (.D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .GATE_N(GATE_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLXTN_TB_V
|
#include <bits/stdc++.h> using int64 = long long; constexpr int Maxn = 200000; constexpr int p = 1000000007; template <class _Tp1, class _Tp2> inline void inc(_Tp1& x, const _Tp2& y) { x += y; (p <= x) && (x -= p); } template <class _Tp1, class _Tp2> inline void dec(_Tp1& x, const _Tp2& y) { x -= y; (x < 0) && (x += p); } template <class _Tp> inline int md(const _Tp& v) { return v < 0 ? ((0 <= p + v) ? (p + v) : (v % p + p)) : (v < p) ? v : (v % p); } namespace IOManager { constexpr int FILESZ(131072); unsigned char buf[FILESZ]; const unsigned char *ibuf = buf, *tbuf = buf; struct IOManager { inline unsigned char gc() { return (ibuf == tbuf) && (tbuf = (ibuf = buf) + fread(buf, 1, FILESZ, stdin), ibuf == tbuf) ? EOF : *ibuf++; } template <class _Tp> inline operator _Tp() { _Tp s = 0u; unsigned char c = gc(), w = 0; for (; c < 48; c = gc()) (c == 45) && (w = 1); for (; c > 47; c = gc()) s = (_Tp)(s * 10u + c - 48u); return w ? -s : s; } }; } // namespace IOManager IOManager::IOManager io; const int n = io; int64 bit[Maxn + 1]; inline void update(const int& x, const int& d) { for (int i = x; i <= n; i += i & -i) bit[i] += d; } inline int64 sum(const int& x) { int64 s = 0; for (int i = x; i; i -= i & -i) s += bit[i]; return s; } int bitp[Maxn + 1]; inline void updatep(const int& x, const int& d) { for (int i = x; i <= n; i += i & -i) inc(bitp[i], d); } inline int sump(const int& x) { int64 s = 0; for (int i = x; i; i -= i & -i) s += bitp[i]; return s % p; } int a[Maxn + 1], w[Maxn + 1]; int main() { int q = io; for (int i = 1; i <= n; ++i) a[i] = (int)io - i; for (int i = 1; i <= n; ++i) w[i] = io, update(i, w[i]), updatep(i, (int64)w[i] * a[i] % p); int64 sl, sm, sr; for (int x, y, l, m, r; q; --q) if (x = io, y = io, x < 0) { int d = y - w[x = -x]; w[x] = y; update(x, d); updatep(x, md((int64)d * a[x])); } else { l = x; r = y; sl = sum(l - 1); sr = sum(r) - sl; for (; l < r;) ((sum(m = (l + r) >> 1) - sl) * 2 < sr) ? (l = m + 1) : (r = m); sm = sum(m = l); sr += sl; printf( %d n , md((int64)(sump(y) - sump(m) * 2ll + (int64)(sm - sr + sm - sl) % p * a[m] % p + sump(x - 1)))); } return 0; }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module feedforward_AXILiteS_s_axi
#(parameter
C_S_AXI_ADDR_WIDTH = 5,
C_S_AXI_DATA_WIDTH = 32
)(
// axi4 lite slave signals
input wire ACLK,
input wire ARESET,
input wire ACLK_EN,
input wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR,
input wire AWVALID,
output wire AWREADY,
input wire [C_S_AXI_DATA_WIDTH-1:0] WDATA,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB,
input wire WVALID,
output wire WREADY,
output wire [1:0] BRESP,
output wire BVALID,
input wire BREADY,
input wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR,
input wire ARVALID,
output wire ARREADY,
output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA,
output wire [1:0] RRESP,
output wire RVALID,
input wire RREADY,
output wire interrupt,
// user signals
output wire ap_start,
input wire ap_done,
input wire ap_ready,
input wire ap_idle,
input wire [7:0] ap_return,
output wire [7:0] P_mode_V
);
//------------------------Address Info-------------------
// 0x00 : Control signals
// bit 0 - ap_start (Read/Write/COH)
// bit 1 - ap_done (Read/COR)
// bit 2 - ap_idle (Read)
// bit 3 - ap_ready (Read)
// bit 7 - auto_restart (Read/Write)
// others - reserved
// 0x04 : Global Interrupt Enable Register
// bit 0 - Global Interrupt Enable (Read/Write)
// others - reserved
// 0x08 : IP Interrupt Enable Register (Read/Write)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0x0c : IP Interrupt Status Register (Read/TOW)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0x10 : Data signal of ap_return
// bit 7~0 - ap_return[7:0] (Read)
// others - reserved
// 0x18 : Data signal of P_mode_V
// bit 7~0 - P_mode_V[7:0] (Read/Write)
// others - reserved
// 0x1c : reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
//------------------------Parameter----------------------
localparam
ADDR_AP_CTRL = 5'h00,
ADDR_GIE = 5'h04,
ADDR_IER = 5'h08,
ADDR_ISR = 5'h0c,
ADDR_AP_RETURN_0 = 5'h10,
ADDR_P_MODE_V_DATA_0 = 5'h18,
ADDR_P_MODE_V_CTRL = 5'h1c,
WRIDLE = 2'd0,
WRDATA = 2'd1,
WRRESP = 2'd2,
RDIDLE = 2'd0,
RDDATA = 2'd1,
ADDR_BITS = 5;
//------------------------Local signal-------------------
reg [1:0] wstate;
reg [1:0] wnext;
reg [ADDR_BITS-1:0] waddr;
wire [31:0] wmask;
wire aw_hs;
wire w_hs;
reg [1:0] rstate;
reg [1:0] rnext;
reg [31:0] rdata;
wire ar_hs;
wire [ADDR_BITS-1:0] raddr;
// internal registers
wire int_ap_idle;
wire int_ap_ready;
reg int_ap_done;
reg int_ap_start;
reg int_auto_restart;
reg int_gie;
reg [1:0] int_ier;
reg [1:0] int_isr;
reg [7:0] int_ap_return;
reg [7:0] int_P_mode_V;
//------------------------Instantiation------------------
//------------------------AXI write fsm------------------
assign AWREADY = (wstate == WRIDLE);
assign WREADY = (wstate == WRDATA);
assign BRESP = 2'b00; // OKAY
assign BVALID = (wstate == WRRESP);
assign wmask = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} };
assign aw_hs = AWVALID & AWREADY;
assign w_hs = WVALID & WREADY;
// wstate
always @(posedge ACLK) begin
if (ARESET)
wstate <= WRIDLE;
else if (ACLK_EN)
wstate <= wnext;
end
// wnext
always @(*) begin
case (wstate)
WRIDLE:
if (AWVALID)
wnext = WRDATA;
else
wnext = WRIDLE;
WRDATA:
if (WVALID)
wnext = WRRESP;
else
wnext = WRDATA;
WRRESP:
if (BREADY)
wnext = WRIDLE;
else
wnext = WRRESP;
default:
wnext = WRIDLE;
endcase
end
// waddr
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (aw_hs)
waddr <= AWADDR[ADDR_BITS-1:0];
end
end
//------------------------AXI read fsm-------------------
assign ARREADY = (rstate == RDIDLE);
assign RDATA = rdata;
assign RRESP = 2'b00; // OKAY
assign RVALID = (rstate == RDDATA);
assign ar_hs = ARVALID & ARREADY;
assign raddr = ARADDR[ADDR_BITS-1:0];
// rstate
always @(posedge ACLK) begin
if (ARESET)
rstate <= RDIDLE;
else if (ACLK_EN)
rstate <= rnext;
end
// rnext
always @(*) begin
case (rstate)
RDIDLE:
if (ARVALID)
rnext = RDDATA;
else
rnext = RDIDLE;
RDDATA:
if (RREADY & RVALID)
rnext = RDIDLE;
else
rnext = RDDATA;
default:
rnext = RDIDLE;
endcase
end
// rdata
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (ar_hs) begin
rdata <= 1'b0;
case (raddr)
ADDR_AP_CTRL: begin
rdata[0] <= int_ap_start;
rdata[1] <= int_ap_done;
rdata[2] <= int_ap_idle;
rdata[3] <= int_ap_ready;
rdata[7] <= int_auto_restart;
end
ADDR_GIE: begin
rdata <= int_gie;
end
ADDR_IER: begin
rdata <= int_ier;
end
ADDR_ISR: begin
rdata <= int_isr;
end
ADDR_AP_RETURN_0: begin
rdata <= int_ap_return[7:0];
end
ADDR_P_MODE_V_DATA_0: begin
rdata <= int_P_mode_V[7:0];
end
endcase
end
end
end
//------------------------Register logic-----------------
assign interrupt = int_gie & (|int_isr);
assign ap_start = int_ap_start;
assign int_ap_idle = ap_idle;
assign int_ap_ready = ap_ready;
assign P_mode_V = int_P_mode_V;
// int_ap_start
always @(posedge ACLK) begin
if (ARESET)
int_ap_start <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0] && WDATA[0])
int_ap_start <= 1'b1;
else if (int_ap_ready)
int_ap_start <= int_auto_restart; // clear on handshake/auto restart
end
end
// int_ap_done
always @(posedge ACLK) begin
if (ARESET)
int_ap_done <= 1'b0;
else if (ACLK_EN) begin
if (ap_done)
int_ap_done <= 1'b1;
else if (ar_hs && raddr == ADDR_AP_CTRL)
int_ap_done <= 1'b0; // clear on read
end
end
// int_auto_restart
always @(posedge ACLK) begin
if (ARESET)
int_auto_restart <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0])
int_auto_restart <= WDATA[7];
end
end
// int_gie
always @(posedge ACLK) begin
if (ARESET)
int_gie <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_GIE && WSTRB[0])
int_gie <= WDATA[0];
end
end
// int_ier
always @(posedge ACLK) begin
if (ARESET)
int_ier <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_IER && WSTRB[0])
int_ier <= WDATA[1:0];
end
end
// int_isr[0]
always @(posedge ACLK) begin
if (ARESET)
int_isr[0] <= 1'b0;
else if (ACLK_EN) begin
if (int_ier[0] & ap_done)
int_isr[0] <= 1'b1;
else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
int_isr[0] <= int_isr[0] ^ WDATA[0]; // toggle on write
end
end
// int_isr[1]
always @(posedge ACLK) begin
if (ARESET)
int_isr[1] <= 1'b0;
else if (ACLK_EN) begin
if (int_ier[1] & ap_ready)
int_isr[1] <= 1'b1;
else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
int_isr[1] <= int_isr[1] ^ WDATA[1]; // toggle on write
end
end
// int_ap_return
always @(posedge ACLK) begin
if (ARESET)
int_ap_return <= 0;
else if (ACLK_EN) begin
if (ap_done)
int_ap_return <= ap_return;
end
end
// int_P_mode_V[7:0]
always @(posedge ACLK) begin
if (ARESET)
int_P_mode_V[7:0] <= 0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_P_MODE_V_DATA_0)
int_P_mode_V[7:0] <= (WDATA[31:0] & wmask) | (int_P_mode_V[7:0] & ~wmask);
end
end
//------------------------Memory logic-------------------
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Muhammad Ijaz
//
// Create Date: 08/08/2017 10:53:59 AM
// Design Name:
// Module Name: DUAL_PORT_MEMORY
// Project Name: RISC-V
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module DUAL_PORT_MEMORY #(
parameter MEMORY_WIDTH = 512 ,
parameter MEMORY_DEPTH = 512 ,
parameter MEMORY_LATENCY = "LOW_LATENCY" ,
parameter INIT_FILE = ""
) (
input CLK ,
input [$clog2(MEMORY_DEPTH-1) - 1 : 0] WRITE_ADDRESS ,
input [MEMORY_WIDTH-1 : 0] DATA_IN ,
input WRITE_ENABLE ,
input [$clog2(MEMORY_DEPTH-1)-1 : 0] READ_ADDRESS ,
input READ_ENBLE ,
output [MEMORY_WIDTH-1 : 0] DATA_OUT
);
reg [MEMORY_WIDTH - 1 : 0] memory [MEMORY_DEPTH - 1 : 0] ;
reg [MEMORY_WIDTH - 1 : 0] data_out_reg_1 ;
integer i;
initial
begin
if (INIT_FILE != "")
begin
$readmemh(INIT_FILE, memory, 0, MEMORY_DEPTH-1);
end
else
begin
for (i = 0; i < MEMORY_DEPTH; i = i + 1)
memory [ i ] = {MEMORY_WIDTH{1'b0}};
end
data_out_reg_1 = {MEMORY_WIDTH{1'b0}};
end
always @(posedge CLK)
begin
if (WRITE_ENABLE)
begin
memory [WRITE_ADDRESS] <= DATA_IN ;
end
if (READ_ENBLE)
begin
data_out_reg_1 <= memory [READ_ADDRESS] ;
end
end
generate
if (MEMORY_LATENCY == "LOW_LATENCY")
begin
assign DATA_OUT = data_out_reg_1;
end
else
begin
reg [MEMORY_WIDTH - 1 :0] data_out_reg_2 = {MEMORY_WIDTH{1'b0}} ;
initial
begin
data_out_reg_2 = {MEMORY_WIDTH{1'b0}};
end
always @(posedge CLK)
begin
if (READ_ENBLE)
begin
data_out_reg_2 <= data_out_reg_1;
end
end
assign DATA_OUT = data_out_reg_2;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:1000000000 ) using namespace std; const long long inf = (long long)1e18; const long double eps = 1e-8; const long double pi = 3.1415926535; string a[100000][8]; bool u[100000][8][8]; int sx, sy, tx, ty; bool f; void dfs(int x, int y, int t) { u[t][x][y] = 1; if (tx == x && ty == y) f = 1; if (t < 99999 && a[t + 1][x][y] != S && !u[t + 1][x][y]) dfs(x, y, t + 1); if (t < 99999 && x > 0 && !u[t + 1][x - 1][y] && a[t][x - 1][y] != S && a[t + 1][x - 1][y] != S ) dfs(x - 1, y, t + 1); if (t < 99999 && y > 0 && !u[t + 1][x][y - 1] && a[t][x][y - 1] != S && a[t + 1][x][y - 1] != S ) dfs(x, y - 1, t + 1); if (t < 99999 && x < 7 && !u[t + 1][x + 1][y] && a[t][x + 1][y] != S && a[t + 1][x + 1][y] != S ) dfs(x + 1, y, t + 1); if (t < 99999 && y < 7 && !u[t + 1][x][y + 1] && a[t][x][y + 1] != S && a[t + 1][x][y + 1] != S ) dfs(x, y + 1, t + 1); if (t < 99999 && x > 0 && y > 0 && !u[t + 1][x - 1][y - 1] && a[t][x - 1][y - 1] != S && a[t + 1][x - 1][y - 1] != S ) dfs(x - 1, y - 1, t + 1); if (t < 99999 && y > 0 && x < 7 && !u[t + 1][x + 1][y - 1] && a[t][x + 1][y - 1] != S && a[t + 1][x + 1][y - 1] != S ) dfs(x + 1, y - 1, t + 1); if (t < 99999 && x > 0 && y < 7 && !u[t + 1][x - 1][y + 1] && a[t][x - 1][y + 1] != S && a[t + 1][x - 1][y + 1] != S ) dfs(x - 1, y + 1, t + 1); if (t < 99999 && y < 7 && x < 7 && !u[t + 1][x + 1][y + 1] && a[t][x + 1][y + 1] != S && a[t + 1][x + 1][y + 1] != S ) dfs(x + 1, y + 1, t + 1); } int main() { for (int i = 0; i < 8; ++i) { cin >> a[0][i]; for (int j = 0; j < 8; ++j) { if (a[0][i][j] == A ) { tx = i; ty = j; } if (a[0][i][j] == M ) { sx = i; sy = j; } } } f = 0; for (int i = 1; i < 100000; ++i) for (int j = 0; j < 8; ++j) for (int k = 0; k < 8; ++k) if (j > 0 && a[i - 1][j - 1][k] == S ) a[i][j] += S ; else a[i][j] += . ; dfs(sx, sy, 0); if (f) cout << WIN ; else cout << LOSE ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); long long n, a, b, c = 0; cin >> n >> a; for (int i = 1; i <= n; i++) { if (i * n >= a && a % i == 0) c++; } cout << c; }
|
#include <bits/stdc++.h> using namespace std; const long long mx = 3e5 + 66; const long long mod = 1e9 + 7; const long long inf = 8e18 + 66; const int llg = 25; const long long mxk = 31700000; long long power(long long a, long long b, long long md) { if (b == 0) return 1; long long c = power(a, b / 2, md); if (b % 2) return c * c % md * a % md; else return c * c % md; } int n, a[mx], la[mx], ra[mx], rmq[2][llg][mx], val[2][mx], lga[mx], l[llg][mx], r[llg][mx]; int cmx(int x, int y, int b) { if (val[b][x] < val[b][y]) return y; return x; } void build(int b) { for (int i = 1; i < 3 * n + 1; i++) { rmq[b][0][i] = i; if (b == 0) val[b][i] = -la[i]; else val[b][i] = ra[i]; } for (int i = 1; i < lga[3 * n] + 1; i++) for (int j = 1; j + (1 << i) - 1 <= 3 * n; j++) { rmq[b][i][j] = cmx(rmq[b][i - 1][j], rmq[b][i - 1][j + (1 << (i - 1))], b); } } int maxq(int x, int y, int b) { int k = lga[y - x + 1]; return cmx(rmq[b][k][x], rmq[b][k][y - (1 << k) + 1], b); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); for (int i = 2; i < mx; i++) { lga[i] = lga[i / 2] + 1; } cin >> n; if (n == 1) { cout << 0; return 0; } for (int i = 1; i < n + 1; i++) { cin >> a[i]; a[i + n * 2] = a[i + n] = a[i]; } for (int i = 1; i < 3 * n + 1; i++) { la[i] = max(1, i - a[i]); ra[i] = min(3 * n, a[i] + i); } for (int i = 0; i < lga[3 * n] + 1; i++) { l[i][1] = 1; r[i][3 * n] = 3 * n; } for (int i = 1; i < 3 * n + 1; i++) { l[0][i] = la[i]; r[0][i] = ra[i]; } build(0); build(1); for (int i = 1; i < lga[n * 3] + 1; i++) { for (int j = 1; j < 3 * n + 1; j++) { int al = maxq(l[i - 1][j], r[i - 1][j], 0); int ar = maxq(l[i - 1][j], r[i - 1][j], 1); l[i][j] = min(l[i - 1][al], l[i - 1][ar]); r[i][j] = max(r[i - 1][al], r[i - 1][ar]); } } for (int i = n + 1; i < 2 * n + 1; i++) { int ans = 1, u = i, v = i; for (int j = lga[3 * n]; j >= 0; j--) { if (max(r[j][u], r[j][v]) - min(l[j][u], l[j][v]) < n - 1) { int al = maxq(l[j][u], r[j][v], 0); int ar = maxq(l[j][u], r[j][v], 1); u = al, v = ar, ans += (1 << j); } } cout << ans << ; } }
|
#include <bits/stdc++.h> using namespace std; void bktk(int i, char *s, int val, int &ans, vector<int> &cnt) { if (!s[i]) { ans += cnt[val]; return; } val *= 3; if (s[i] == A ) { bktk(i + 1, s, val, ans, cnt); bktk(i + 1, s, val + 1, ans, cnt); } if (s[i] == a ) { bktk(i + 1, s, val + 2, ans, cnt); } if (s[i] == O ) { bktk(i + 1, s, val, ans, cnt); } if (s[i] == o ) { bktk(i + 1, s, val + 1, ans, cnt); bktk(i + 1, s, val + 2, ans, cnt); } if (s[i] == X ) { bktk(i + 1, s, val, ans, cnt); bktk(i + 1, s, val + 2, ans, cnt); } if (s[i] == x ) { bktk(i + 1, s, val + 1, ans, cnt); } } int main() { int w, n, m; scanf( %d %d %d , &w, &n, &m); vector<int> f(1 << w, 0); for (int i = 1; i <= n; i++) { int x; scanf( %d , &x); f[x]++; } vector<int> b3(1 << w, 0); for (int i = 0; i < (1 << w); i++) { for (int k = w - 1; k >= 0; k--) { b3[i] = b3[i] * 3 + ((i >> k) & 1); } } vector<int> cnt(531441, 0); for (int i = 0; i < (1 << w); i++) { for (int j = 0; j < (1 << w); j++) { cnt[b3[i] + b3[j]] += f[i] * f[j]; } } while (m--) { char s[14]; scanf( %s , s); int ans = 0; bktk(0, s, 0, ans, cnt); printf( %d n , ans); } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A22OI_1_V
`define SKY130_FD_SC_HS__A22OI_1_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a22oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a22oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a22oi_1 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A22OI_1_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:41:03 11/08/2015
// Design Name: Integradorv2
// Module Name: /home/rafa/Descargas/Digital/IntegradorV2/inter_tst.v
// Project Name: IntegradorV2
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Integradorv2
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module inter_tst;
// Inputs
reg [15:0] a;
reg [15:0] dt;
reg enable;
reg rst;
reg clk;
// Outputs
wire [15:0] v;
wire busy;
// Instantiate the Unit Under Test (UUT)
Integradorv2 uut (
.a(a),
.dt(dt),
.enable(enable),
.rst(rst),
.clk(clk),
.v(v),
.busy(busy)
);
initial begin
// Initialize Inputs
a = 16'hAA;
dt = 5'd10;
enable = 0;
rst = 1;
clk = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
enable = 1;
rst = 0;
end
always #5 clk <= !clk;
endmodule
|
#include <bits/stdc++.h> using namespace std; int m, n, t, k; int main() { while (scanf( %d%d , &n, &k) == 2) { if (k > n || (n >= 2 && k == 1)) printf( -1 n ); else if (k == 1) printf( %c n , a ); else { int m = n - (k - 2); for (int i = 0; i < m; i++) printf( %c , i % 2 == 0 ? a : b ); for (int i = 0; i < k - 2; i++) printf( %c , a + 2 + i); printf( n ); } } return 0; }
|
module staff(
input [7:0]scan_code1,
output [15:0]sound1,
output sound_off1
);
//////SoundOff Key///////
assign sound_off1=(scan_code1==8'hf0)?0:1;
/////////Channel-1 Trigger////////
wire L_5_tr=(scan_code1==8'h1c)?1:0;//-5
wire L_6_tr=(scan_code1==8'h1b)?1:0;//-6
wire L_7_tr=(scan_code1==8'h23)?1:0;//-7
wire M_1_tr=(scan_code1==8'h2b)?1:0;//1
wire M_2_tr=(scan_code1==8'h34)?1:0;//2
wire M_3_tr=(scan_code1==8'h33)?1:0;//3
wire M_4_tr=(scan_code1==8'h3b)?1:0;//4
wire M_5_tr=(scan_code1==8'h42)?1:0;//5
wire M_6_tr=(scan_code1==8'h4b)?1:0;//6
wire M_7_tr=(scan_code1==8'h4c)?1:0;//7
wire H_1_tr=(scan_code1==8'h52)?1:0;//+1
wire H_2_tr=0;//+2
wire H_3_tr=0;//+3
wire H_4_tr=0;//+4
wire H_5_tr=0;//+5
wire Hu4_tr=0;//((!get_gate) && (scan_code==8'h15))?1:0;//+#4
wire Hu2_tr=0;//((!get_gate) && (scan_code==8'h1d))?1:0;//+#2
wire Hu1_tr=(scan_code1==8'h5b)?1:0;//+#1
wire Mu6_tr=(scan_code1==8'h4d)?1:0;//#6
wire Mu5_tr=(scan_code1==8'h44)?1:0;//#5
wire Mu4_tr=(scan_code1==8'h43)?1:0;//#4
wire Mu2_tr=(scan_code1==8'h35)?1:0;//#2
wire Mu1_tr=(scan_code1==8'h2c)?1:0;//#1
wire Lu6_tr=(scan_code1==8'h24)?1:0;//-#6
wire Lu5_tr=(scan_code1==8'h1d)?1:0;//-#5
wire Lu4_tr=(scan_code1==8'h15)?1:0;//-#4
assign sound1=( //channel-1 frequency
(Lu4_tr)?400 :(
(L_5_tr)?423 :(
(Lu5_tr)?448 :(
(L_6_tr)?475 :(
(Lu6_tr)?503 :(
(L_7_tr)?533 :(
(M_1_tr)?565 :(
(Mu1_tr)?599 :(
(M_2_tr)?634 :(
(Mu2_tr)?672 :(
(M_3_tr)?712 :(
(M_4_tr)?755 :(
(Mu4_tr)?800 :(
(M_5_tr)?847 :(
(Mu5_tr)?897 :(
(M_6_tr)?951 :(
(Mu6_tr)?1007 :(
(M_7_tr)?1067 :(
(H_1_tr)?1131 :(
(Hu1_tr)?1198 :1
)))))))))))))))))))
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1005; const int M = 11; const int MOD = 1e9 + 7; int n, m; int dp[M][N][N]; int solve(int idx, int a, int b) { if (idx >= m) return 1; int& r = dp[idx][a][b]; if (r != -1) return r; r = solve(idx + 1, a, b); if (a < b) { r = (r + solve(idx, a + 1, b)) % MOD; r = (r + solve(idx, a, b - 1)) % MOD; } if (a + 1 < b) r = ((r - solve(idx, a + 1, b - 1)) % MOD + MOD) % MOD; return r; } int main() { cin >> n >> m; memset(dp, -1, sizeof dp); cout << solve(0, 1, n) << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int A, D, C; vector<int> atk, def, ciel; bool used[110]; int partial(void) { int N = min(A, C), i, ans = 0; for ((i) = 0; (i) < (int)(N); (i)++) if (atk[i] < ciel[C - 1 - i]) ans += ciel[C - 1 - i] - atk[i]; return ans; } int search(int x) { int i; for ((i) = 0; (i) < (int)(C); (i)++) if (ciel[i] >= x && !used[i]) { used[i] = true; return i; } return -1; } int all(void) { int i, defsum = 0; for ((i) = 0; (i) < (int)(D); (i)++) { int x = search(def[i] + 1); if (x == -1) return 0; defsum += ciel[x]; } for ((i) = 0; (i) < (int)(A); (i)++) { int x = search(atk[i]); if (x == -1) return 0; } int ans = 0; for ((i) = 0; (i) < (int)(C); (i)++) ans += ciel[i]; for ((i) = 0; (i) < (int)(A); (i)++) ans -= atk[i]; ans -= defsum; return ans; } int main(void) { int N, i, x; cin >> N >> C; for ((i) = 0; (i) < (int)(N); (i)++) { string type; cin >> type >> x; if (type == ATK ) atk.push_back(x); else def.push_back(x); } for ((i) = 0; (i) < (int)(C); (i)++) { cin >> x; ciel.push_back(x); } sort(atk.begin(), atk.end()); sort(def.begin(), def.end()); sort(ciel.begin(), ciel.end()); A = atk.size(); D = def.size(); int ans1 = partial(); int ans2 = all(); cout << max(ans1, ans2) << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, a[1001][1001]; set<int> r[1001], c[1001]; map<int, int> r_m[1001], c_m[1001]; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { scanf( %d , &a[i][j]); r[i].insert(a[i][j]); c[j].insert(a[i][j]); } } for (int i = 1; i <= n; i++) { int w = 1; for (int x : r[i]) { r_m[i][x] = w; w++; } } for (int i = 1; i <= m; i++) { int w = 1; for (int x : c[i]) { c_m[i][x] = w; w++; } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { int x = r_m[i][a[i][j]]; int y = c_m[j][a[i][j]]; if (x > y) { printf( %d , max((int)r[i].size(), (int)c[j].size() + x - y)); } else { printf( %d , max((int)r[i].size() + y - x, (int)c[j].size())); } } printf( n ); } return 0; }
|
`timescale 1 ns / 1 ps
module axis_lfsr #
(
parameter integer AXIS_TDATA_WIDTH = 64,
parameter HAS_TREADY = "FALSE"
)
(
// System signals
input wire aclk,
input wire aresetn,
// Master side
input wire m_axis_tready,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid
);
reg [AXIS_TDATA_WIDTH-1:0] int_lfsr_reg, int_lfsr_next;
reg int_enbl_reg, int_enbl_next;
always @(posedge aclk)
begin
if(~aresetn)
begin
int_lfsr_reg <= 64'h5555555555555555;
int_enbl_reg <= 1'b0;
end
else
begin
int_lfsr_reg <= int_lfsr_next;
int_enbl_reg <= int_enbl_next;
end
end
generate
if(HAS_TREADY == "TRUE")
begin : HAS_TREADY
always @*
begin
int_lfsr_next = int_lfsr_reg;
int_enbl_next = int_enbl_reg;
if(~int_enbl_reg)
begin
int_enbl_next = 1'b1;
end
if(int_enbl_reg & m_axis_tready)
begin
int_lfsr_next = {int_lfsr_reg[62:0], int_lfsr_reg[62] ~^ int_lfsr_reg[61]};
end
end
end
else
begin : NO_TREADY
always @*
begin
int_lfsr_next = int_lfsr_reg;
int_enbl_next = int_enbl_reg;
if(~int_enbl_reg)
begin
int_enbl_next = 1'b1;
end
if(int_enbl_reg)
begin
int_lfsr_next = {int_lfsr_reg[62:0], int_lfsr_reg[62] ~^ int_lfsr_reg[61]};
end
end
end
endgenerate
assign m_axis_tdata = int_lfsr_reg;
assign m_axis_tvalid = int_enbl_reg;
endmodule
|
// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
//
// Permission:
//
// Lattice Semiconductor grants permission to use this code
// pursuant to the terms of the Lattice Semiconductor Corporation
// Open Source License Agreement.
//
// Disclaimer:
//
// Lattice Semiconductor provides no warranty regarding the use or
// functionality of this code. It is the user's responsibility to
// verify the user's design for consistency and functionality through
// the use of formal verification methods.
//
// --------------------------------------------------------------------
//
// Lattice Semiconductor Corporation
// 5555 NE Moore Court
// Hillsboro, OR 97214
// U.S.A
//
// TEL: 1-800-Lattice (USA and Canada)
// (other locations)
//
// web: http://www.latticesemi.com/
// email:
//
// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm_mc_arithmetic.v
// Title : Multi-cycle arithmetic unit.
// Dependencies : lm32_include.v
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// =============================================================================
`include "lm32_include.v"
`define LM32_MC_STATE_RNG 2:0
`define LM32_MC_STATE_IDLE 3'b000
`define LM32_MC_STATE_MULTIPLY 3'b001
`define LM32_MC_STATE_MODULUS 3'b010
`define LM32_MC_STATE_DIVIDE 3'b011
`define LM32_MC_STATE_SHIFT_LEFT 3'b100
`define LM32_MC_STATE_SHIFT_RIGHT 3'b101
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_mc_arithmetic (
// ----- Inputs -----
clk_i,
rst_i,
stall_d,
kill_x,
`ifdef CFG_MC_DIVIDE_ENABLED
divide_d,
modulus_d,
`endif
`ifdef CFG_MC_MULTIPLY_ENABLED
multiply_d,
`endif
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
shift_left_d,
shift_right_d,
sign_extend_d,
`endif
operand_0_d,
operand_1_d,
// ----- Ouputs -----
result_x,
`ifdef CFG_MC_DIVIDE_ENABLED
divide_by_zero_x,
`endif
stall_request_x
);
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input clk_i; // Clock
input rst_i; // Reset
input stall_d; // Stall instruction in D stage
input kill_x; // Kill instruction in X stage
`ifdef CFG_MC_DIVIDE_ENABLED
input divide_d; // Perform divide
input modulus_d; // Perform modulus
`endif
`ifdef CFG_MC_MULTIPLY_ENABLED
input multiply_d; // Perform multiply
`endif
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
input shift_left_d; // Perform left shift
input shift_right_d; // Perform right shift
input sign_extend_d; // Whether to sign-extend (arithmetic) or zero-extend (logical)
`endif
input [`LM32_WORD_RNG] operand_0_d;
input [`LM32_WORD_RNG] operand_1_d;
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
output [`LM32_WORD_RNG] result_x; // Result of operation
reg [`LM32_WORD_RNG] result_x;
`ifdef CFG_MC_DIVIDE_ENABLED
output divide_by_zero_x; // A divide by zero was attempted
reg divide_by_zero_x;
`endif
output stall_request_x; // Request to stall pipeline from X stage back
wire stall_request_x;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
reg [`LM32_WORD_RNG] p; // Temporary registers
reg [`LM32_WORD_RNG] a;
reg [`LM32_WORD_RNG] b;
`ifdef CFG_MC_DIVIDE_ENABLED
wire [32:0] t;
`endif
reg [`LM32_MC_STATE_RNG] state; // Current state of FSM
reg [5:0] cycles; // Number of cycles remaining in the operation
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
reg sign_extend_x; // Whether to sign extend of zero extend right shifts
wire fill_value; // Value to fill with for right barrel-shifts
`endif
/////////////////////////////////////////////////////
// Combinational logic
/////////////////////////////////////////////////////
// Stall pipeline while any operation is being performed
assign stall_request_x = state != `LM32_MC_STATE_IDLE;
`ifdef CFG_MC_DIVIDE_ENABLED
// Subtraction
assign t = {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]} - b;
`endif
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
// Determine fill value for right shift - Sign bit for arithmetic shift, or zero for logical shift
assign fill_value = (sign_extend_x == `TRUE) & b[`LM32_WORD_WIDTH-1];
`endif
/////////////////////////////////////////////////////
// Sequential logic
/////////////////////////////////////////////////////
// Perform right shift
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
cycles <= {6{1'b0}};
p <= {`LM32_WORD_WIDTH{1'b0}};
a <= {`LM32_WORD_WIDTH{1'b0}};
b <= {`LM32_WORD_WIDTH{1'b0}};
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
sign_extend_x <= 1'b0;
`endif
`ifdef CFG_MC_DIVIDE_ENABLED
divide_by_zero_x <= `FALSE;
`endif
result_x <= {`LM32_WORD_WIDTH{1'b0}};
state <= `LM32_MC_STATE_IDLE;
end
else
begin
`ifdef CFG_MC_DIVIDE_ENABLED
divide_by_zero_x <= `FALSE;
`endif
case (state)
`LM32_MC_STATE_IDLE:
begin
if (stall_d == `FALSE)
begin
cycles <= `LM32_WORD_WIDTH;
p <= 32'b0;
a <= operand_0_d;
b <= operand_1_d;
`ifdef CFG_MC_DIVIDE_ENABLED
if (divide_d == `TRUE)
state <= `LM32_MC_STATE_DIVIDE;
if (modulus_d == `TRUE)
state <= `LM32_MC_STATE_MODULUS;
`endif
`ifdef CFG_MC_MULTIPLY_ENABLED
if (multiply_d == `TRUE)
state <= `LM32_MC_STATE_MULTIPLY;
`endif
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
if (shift_left_d == `TRUE)
begin
state <= `LM32_MC_STATE_SHIFT_LEFT;
sign_extend_x <= sign_extend_d;
cycles <= operand_1_d[4:0];
a <= operand_0_d;
b <= operand_0_d;
end
if (shift_right_d == `TRUE)
begin
state <= `LM32_MC_STATE_SHIFT_RIGHT;
sign_extend_x <= sign_extend_d;
cycles <= operand_1_d[4:0];
a <= operand_0_d;
b <= operand_0_d;
end
`endif
end
end
`ifdef CFG_MC_DIVIDE_ENABLED
`LM32_MC_STATE_DIVIDE:
begin
if (t[32] == 1'b0)
begin
p <= t[31:0];
a <= {a[`LM32_WORD_WIDTH-2:0], 1'b1};
end
else
begin
p <= {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]};
a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0};
end
result_x <= a;
if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE))
begin
// Check for divide by zero
divide_by_zero_x <= b == {`LM32_WORD_WIDTH{1'b0}};
state <= `LM32_MC_STATE_IDLE;
end
cycles <= cycles - 1'b1;
end
`LM32_MC_STATE_MODULUS:
begin
if (t[32] == 1'b0)
begin
p <= t[31:0];
a <= {a[`LM32_WORD_WIDTH-2:0], 1'b1};
end
else
begin
p <= {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]};
a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0};
end
result_x <= p;
if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE))
begin
// Check for divide by zero
divide_by_zero_x <= b == {`LM32_WORD_WIDTH{1'b0}};
state <= `LM32_MC_STATE_IDLE;
end
cycles <= cycles - 1'b1;
end
`endif
`ifdef CFG_MC_MULTIPLY_ENABLED
`LM32_MC_STATE_MULTIPLY:
begin
if (b[0] == 1'b1)
p <= p + a;
b <= {1'b0, b[`LM32_WORD_WIDTH-1:1]};
a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0};
result_x <= p;
if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE))
state <= `LM32_MC_STATE_IDLE;
cycles <= cycles - 1'b1;
end
`endif
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
`LM32_MC_STATE_SHIFT_LEFT:
begin
a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0};
result_x <= a;
if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE))
state <= `LM32_MC_STATE_IDLE;
cycles <= cycles - 1'b1;
end
`LM32_MC_STATE_SHIFT_RIGHT:
begin
b <= {fill_value, b[`LM32_WORD_WIDTH-1:1]};
result_x <= b;
if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE))
state <= `LM32_MC_STATE_IDLE;
cycles <= cycles - 1'b1;
end
`endif
endcase
end
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// Discrete Cosine Transform Unit ////
//// ////
//// Author: Richard Herveille ////
//// ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: dctu.v,v 1.3 2002/10/31 12:50:03 rherveille Exp $
//
// $Date: 2002/10/31 12:50:03 $
// $Revision: 1.3 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: dctu.v,v $
// Revision 1.3 2002/10/31 12:50:03 rherveille
// *** empty log message ***
//
// Revision 1.2 2002/10/23 09:06:59 rherveille
// Improved many files.
// Fixed some bugs in Run-Length-Encoder.
// Removed dependency on ud_cnt and ro_cnt.
// Started (Motion)JPEG hardware encoder project.
//
//synopsys translate_off
//`include "timescale.v"
//synopsys translate_on
module dctu(clk, ena, ddgo, x, y, ddin, dout);
parameter coef_width = 16;
parameter di_width = 8;
parameter [2:0] v = 0;
parameter [2:0] u = 0;
//
// inputs & outputs
//
input clk;
input ena;
input ddgo; // double delayed go signal
input [2:0] x, y;
input [di_width:1] ddin; // delayed data input
output [11:0] dout;
//
// variables
//
reg [ 31:0] coef;
wire [coef_width +10:0] result;
`include "dct_cos_table.v"
//
// module body
//
// hookup cosine-table
always @(posedge clk)
if(ena)
coef <= #1 dct_cos_table(x, y, u, v);
// hookup dct-mac unit
dct_mac #(8, coef_width)
macu (
.clk(clk),
.ena(ena),
.dclr(ddgo),
.din(ddin),
.coef( coef[31:31 -coef_width +1] ),
.result(result)
);
assign dout = result[coef_width +10: coef_width -1];
endmodule
|
module testbench;
`include "test_bsg_clock_params.v"
localparam cycle_time_lp = 20;
wire clk;
wire reset;
localparam width_lp = 16;
localparam els_lp = 4;
bsg_nonsynth_clock_gen #(.cycle_time_p(cycle_time_lp)) clock_gen
(.o(clk));
bsg_nonsynth_reset_gen #(.reset_cycles_lo_p(5)
,.reset_cycles_hi_p(5)
) reset_gen
(.clk_i(clk)
,.async_reset_o(reset)
);
logic [width_lp-1:0] test_data_in, test_data_out, test_data_check;
wire test_valid_in, test_valid_out, test_ready_out, test_ready_in;
logic [31:0] ctr;
bsg_cycle_counter counter (.clk_i(clk)
,.reset_i(reset)
,.ctr_r_o(ctr)
);
// *******************************************************
// ** generate pattern of valids
localparam pattern_width_lp = 20;
wire [$clog2(pattern_width_lp)-1:0] pattern_bit;
logic [pattern_width_lp-1:0] test_pattern, test_pattern_r;
bsg_circular_ptr #(.slots_p(1 << pattern_width_lp)
,.max_add_p(1)
) seq
(.clk(clk)
,.reset_i(reset)
,.add_i (pattern_bit == (pattern_width_lp-1))
,.o (test_pattern)
);
// cycles through each bit of the battern
bsg_circular_ptr #(.slots_p(pattern_width_lp)
,.max_add_p(1)
) sequ
(.clk(clk)
,.reset_i(reset)
,.add_i (1'b1)
,.o (pattern_bit)
);
assign test_valid_in = test_pattern[pattern_bit];
// our readies will be reflected and inverted
assign test_ready_in = ~test_pattern[pattern_width_lp-pattern_bit-1];
// end generate pattern of valids
// *******************************************************
// *******************************************************
// generate data
bsg_circular_ptr #(.slots_p(1 << width_lp)
,.max_add_p(1)
) gen
(.clk(clk)
,.reset_i(reset)
,.add_i (test_valid_in & test_ready_out)
,.o (test_data_in)
);
// end generate data
// *******************************************************
localparam verbose_lp=0;
always @(posedge clk)
begin
if (test_valid_in & test_ready_out & verbose_lp)
$display("### %x sent %x bypass_mode=%x",ctr, test_data_in,fifo.bypass_mode);
end
wire test_yumi_in = test_ready_in & test_valid_out;
bsg_fifo_1r1w_large #(.width_p(width_lp)
,.els_p(els_lp)
) fifo
(.clk_i(clk)
,.reset_i(reset )
,.data_i (test_data_in)
,.v_i (test_valid_in)
,.ready_o(test_ready_out)
,.v_o (test_valid_out)
,.data_o (test_data_out)
,.yumi_i (test_yumi_in) // recycle
);
bsg_circular_ptr #(.slots_p (1 << width_lp)
,.max_add_p(1)
) check
(.clk(clk)
,.reset_i(reset)
,.add_i (test_yumi_in)
,.o (test_data_check)
);
always_ff @(posedge clk)
begin
test_pattern_r <= test_pattern;
if (test_yumi_in & ~(|test_pattern) & (&test_pattern_r))
$finish();
end
always @(posedge clk)
begin
assert (reset | ((test_yumi_in !== 1'b1) | (test_data_check == test_data_out)))
else
begin
$error("### mismatched value v=%x y=%x ch=%x da=%x reset=%x",test_valid_out, test_yumi_in, test_data_check, test_data_out, reset);
$finish;
end
if (~reset & test_yumi_in === 1'b1)
if (verbose_lp | ((test_data_out & 16'hffff) == 0))
$display("### %x received %x (1rw r=%x w=%x f=%x e=%x) pattern=%b storage=%d"
, ctr, test_data_out, fifo.big1p.rd_ptr, fifo.big1p.wr_ptr
, fifo.big1p.fifo_full, fifo.big1p.fifo_empty, test_pattern, fifo.num_elements_debug);
if (verbose_lp | 1)
if (fifo.num_elements_debug > els_lp+6)
$display("### storing %d els!\n", fifo.num_elements_debug);
// IMPORTANT TEST: test that the fifo will never register full with less than els_lp
// elements actually stored.
if (~test_ready_out & test_valid_in)
// mbt: seems like this should be "<" -- so this fifo actually stores N+1 elements?
if (fifo.num_elements_debug <= els_lp)
begin
$display("### %x FAIL BAD FULL %x (1rw r=%x w=%x f=%x e=%x) pattern=%b storage=%d"
, ctr, test_data_out, fifo.big1p.rd_ptr, fifo.big1p.wr_ptr
, fifo.big1p.fifo_full, fifo.big1p.fifo_empty, test_pattern, fifo.num_elements_debug);
$finish;
end
// IMPORTANT TEST: test that the fifo will never register empty if there are actually
// elements stored.
//
if (~test_valid_out & (fifo.num_elements_debug != 0))
begin
$display("### %x FAIL BAD empty %x (1rw r=%x w=%x f=%x e=%x) pattern=%b storage=%d"
, ctr, test_data_out, fifo.big1p.rd_ptr, fifo.big1p.wr_ptr
, fifo.big1p.fifo_full, fifo.big1p.fifo_empty, test_pattern, fifo.num_elements_debug);
$finish;
end
end
endmodule
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