	// Generate Clock here
	initial
	begin
		clock = 0;


  frame=1'b0; irdy=1'b0;
  $display("time=%t frame=%0d irdy=%0d", $time, frame, irdy);
  repeat (5) @(posedge clk);
endtask


uvm_blocking_put_imp #(T,consumer #(T)) in;


tracebackinfo_str = {"\n", indentation_str, report_object_name, ",",


constraint c { addr >= 0 && addr < 'h100; }


`uvm_info("producer", $sformatf("Sending %s",p.get_name()), UVM_MEDIUM)


always_ff @(posedge aclk or negedge areset_n) begin


    );

    `LOGIC_AXI4_STREAM_IF_TX_ASSIGN(tx, tx);


    );

    `LOGIC_AXI4_STREAM_IF_TX_ASSIGN(tx, tx);
endmodule


                    next_addr_state = SETUP;
                end
            end


            prop_buffer[write_ptr] <= wprop;
        end


            RESPONSE: begin
                if(axilite_rready) begin
                    next_read_state = IDLE;
                end


        .R(1'b0),   // 1-bit reset
        .S(1'b0)    // 1-bit set
    );

    always @(posedge sdclk_bufg) begin


                if(ridx >= 17 - 1) begin//crc16 and a stop bit
                    next_sddat_state = READY_TO_SUSPEND;
                end
            end


    assign resparg = response.arg;

    always_ff @(posedge clk) begin


                    memory[avs_b_address][i] <= avs_b_writedata[i];
        if (avs_b_read)
            avs_b_readdata <= memory[avs_b_address];


                    F3_SLTU: return SLTU;
                    F3_XOR:  return XOR;
                    F3_OR:   return OR;
                    F3_AND:  return AND;
                    // for immediate shifts we check the 6th bit in the shift amount is 0


    memory_debug #(
        .ADDR_WIDTH(ADDR_WIDTH)
    ) main_mem_debug (
        .clock,
        .address(main_address),


assign ppu_addr_out[18:10] = ext_ntram_access


assign cpu_addr_out[26:13] = {prg_base[26:14] | (prg_addr_mapped[20:14] & ~prg_mask[20:14]), prg_addr_mapped[13]};


assign sram_ce = sram_ce_w | cpu_data_out_enabled;


    logic spike_out;
    neuron dut(clk, rst, en, potent_in, spike_out);


    logic clk, rst, en;
    always begin clk <= 1'b1; #5; clk <= 1'b0; #5; end
    initial begin rst = 1'b1; #18; rst = 1'b0; end


            .DATA_WIDTH(DATA_WIDTH), .TAG_WIDTH(TAG_WIDTH)
        ) rch(


    input logic  signal,  // signal to be counted

    output logic [CNT_WIDTH - 1 : 0] cnt
);


                .spike_in(prev_layer_spike),
                .spike_out(curr_layer_spike[k])
            );


    comparer_recursivenode #(
        .LEFT(0), .RIGHT(ITEM_CNT-1),


sum_potent_in = sum_potent_in + potent_in[i];


    logic init_ren, init_wen, init_done;
    always_ff @(posedge clk)
    begin
        if (rst) init_timer <= 1'b0;


    	$display("Hash: %h", hashed);
    	$finish;
	end
endmodule


    	assign rst = 0;
    	while(done !== 1'b1) begin


sha_mainloop uut(.padded(padded), .clk(clk), .rst(rst));


assign padded = {message, 1'b1, {zero_width{1'b0}}, {back_0_width{1'b0}}, MSG_SIZE};


module sha_padder_tb;
	logic [511:0] padded;
	logic [23:0] message;


			default: state = STATE_BUSY;
		endcase

		case (state_reg)
			READY, MISSED_ACK, PRE_WRITE: scl_o = 0;


	input logic data_ready,
	input logic signed[15:0] value,
	output logic signed[15:0] filtered


	output logic[2:0] LEDS
);
	localparam signed MOTOR_MIN = 190;
	localparam signed MOTOR_MAX = 600;


	wire signed[60:0] scaled_gyro = gyro * FS; // 15 bits to right of binary point
	wire signed[63:0] scaled_gyro_aligned = {scaled_gyro, {3{1'b0}}}; // 18 bits to right of binary point


	end else begin
		last_ppm <= ppm;
		//ch_out <= '{ch[0], ch[1], ch[2], ch[3], ch[4], ch[5]};
		if(ppm & ~last_ppm) begin


input logic [11:0] val [0:3];
output logic [3:0] pwm = 4'b0;


`define ASSERT(CONDITION, MESSAGE) if ((CONDITION)==1'b1); else begin $display($sformatf("Error: %s", $sformatf MESSAGE)); ERROR = 1; end


        MEM_d[lru_d].data = 0; // TODO
        MEM_d[lru_d].tag = 0; // TODO
        MEM_d[lru_d].valid = 0; // TODO
        lru_d = 0; // TODO


module unread (
    input logic d_i
);

endmodule


      // value is being written to victim cache
      // then we need need to do memory request write to icache sram
      VICTIM_MISS: begin
          cmp_en_d = 1'b0;


assign data_type = packet_header[0][5:0];


zero_accumulator <= zero_accumulator + 1'd1;


module raw8 (
    input logic [7:0] image_data [3:0],
    input logic image_data_enable,


);

logic [31:0] unpacked_image_data;
assign unpacked_image_data = {image_data[3], image_data[2], image_data[1], image_data[0]};


begin
    if (image_data_enable)
    begin


module yuv422_8bit (
    input logic [7:0] image_data [3:0],
    input logic image_data_enable,
    output logic [23:0] yuv [1:0],
    output logic yuv_enable


                assert (word_count == {TEST1[4], TEST1[3]}) else $fatal(1, "Expected word count '%h%h' but was %h", TEST1[4], TEST1[3], word_count);
                assert (image_data_type == TEST1[2]) else $fatal(1, "Expected data type %h but was %h", TEST1[2], image_data_type);
                $display("Test 1 complete");
                current_test <= 1;
                test_index <= 1'd0;


        begin
            assert(d_phy_receiver.state == 2'd0) else $fatal(1, "receiver is in %d but should've returned to UNKNOWN", d_phy_receiver.state);
            $finish;
        end


		wait(tb_ARESETn === 0) @(posedge tb_ACLK);
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);


        .S_AXI_BRESP    (s_axi_bresp),
        .S_AXI_BVALID   (s_axi_bvalid),
        .S_AXI_BREADY   (s_axi_bready),
        .S_AXI_ARID     (s_axi_arid),
        .S_AXI_ARADDR   (s_axi_araddr),


module IntXbar( // @[:Top.ZynqFPGAConfig.fir@3.2]
  input   auto_int_in_1_0, // @[:Top.ZynqFPGAConfig.fir@6.4]
  output  auto_int_out_2 // @[:Top.ZynqFPGAConfig.fir@6.4]


        o_valid <= 1'd0;

        o_ready <= 1'b1;


reg [DATA_WIDTH-1:0] 	mem [2**ADDR_WIDTH];


	output logic [DIMENSION-1:0][PIX_WIDTH-1:0] o_data
);


                .cols_cntr(           ),
                .rows_cntr(           )
            );


for (int i = 1; i < POOL_DIMENSION; i++) begin


            .IN_DIMENSION      (FLAT_DIMENSION[numb]                                     ),
            .OUT_DIMENSION     (FLAT_DIMENSION[numb+1]                                   )
        ) inst_fully_connected_layer1 (
            .clk                 (clk                                           ),


            `ALU_OR     : result = operand_1 | operand_2;
            `ALU_XOR    : result = operand_1 ^ operand_2;

            `ALU_SLT    : result = $signed(operand_1) < $signed(operand_2) ? 1 : 0;


module Multiplier_16bit
(
    input   wire    [15 : 0] operand_1,
    input   wire    [15 : 0] operand_2,


        case (instruction_type)
            `I_TYPE : immediate = { {21{instruction[31]}}, instruction[30 : 20] };
            `S_TYPE : immediate = { {21{instruction[31]}}, instruction[30 : 25], instruction[11 : 7] };
            `B_TYPE : immediate = { {20{instruction[31]}}, instruction[7], instruction[30 : 25], instruction[11 : 8], 1'b0 };
            `U_TYPE : immediate = { instruction[31 : 12], {12{1'b0}} };


                            begin
                                aluOperation <= `ALU_SUB;
                            end

                            `BLT :


    // Memory //
    ////////////

    reg [31 : 0] Memory [0 : 4 * 1024 - 1];
    initial $readmemh(`FIRMWARE, Memory);


    input wire [WIDTH - 1 : 0] write_data,

    output reg [WIDTH - 1 : 0] read_data_1,


            `FPU_ADD    : begin result = operand_1 + operand_2; ready = 1; end
            `FPU_SUB    : begin result = operand_1 - operand_2; ready = 1; end
            `FPU_MUL    : begin result = product[WIDTH + FBITS - 1 : FBITS]; ready = product_ready; end
            `FPU_SQRT   : begin result = root; ready = root_ready; end
            default     : begin result = 'bz; ready = 0; end


  m_axi_awlen,
  m_axi_awsize,
  m_axi_awburst,
  m_axi_awlock,
  m_axi_awcache,


assign IF.WSTRB       = slave_mode? s_axi_wstrb : {(C_AXI_WDATA_WIDTH/8){1'bz}};


axi_strb_t   axi_wstrb;
logic        axi_wlast;


    aclk,
    arstn,
    button,
    button_debounced


           - `FAIL_IF_NOT();
           - `FAIL_IF_EQUAL();
           - `FAIL_IF_NOT_EQUAL();
        */


        arstn_i = 1'b1;
        arstn_o = 1'b1;
    end
    endtask


    output reg  [BUS_WIDTH-1:0] tdata_o
    );


            synchro <= {synchro[0], tvalid_i};
        end


module clk_rst_gen #(
  parameter realtime      ClkPeriod = 0ps, // minimum: 2ps
  parameter int unsigned  RstClkCycles = 0
) (
  output logic clk_o,


    assert (AcqDelay > 0ps)
      else $fatal("The acquisition delay must be greater than 0!");
    assert (AcqDelay > ApplDelay)


  input  logic    clk_i,
  input  logic    rst_ni,

  output data_t   data_o


    @(posedge clk_i);
    forever begin
      rand_success = std::randomize(rand_delay) with {
        rand_delay >= MinWaitCycles;
        rand_delay <= MaxWaitCycles;


assert (rand_success) else $error("Failed to randomize wait cycles!");


    input logic valid_i,
    input T data_i
);

    T in_wave;


            end
            @(posedge clk_i);


        $display("y (float) = %f", y.fval);
        $finish();
    end


        .IW_Y(IW_Y), .QW_Y(QW_Y)
    ) u_interp (.m(m), .x(x), .b(b), .y(y));

    initial begin


    // clipped value
    assign out = positiveclip ? maxval :
                 negativeclip ? minval : in[outw-1:0];


);
    localparam int out_wl = `fp_wl(fp);
    localparam longint ival = longint'(float * (2.0 ** `fp_qw(fp))); // rounds to nearest integer
    localparam longint top = 2 ** (out_wl - 1) - 1;
    localparam longint bot = -(2 ** (out_wl - 1));


`define sub_iw(fp1, fp2) `add_iw(fp1, fp2)


    sfp.in      in1, in2,   // input sfp signal
    sfp.out     out,        // output sfp signal (= in1 + in2)
    output      clipping    // clipping indicator (active-high)
);


    if ((`fp_iw(out) != iw_aligned + 1) || (`fp_qw(out) != qw_aligned))
        $error({"%m: Incorrect output word length for a full-width subtract!",
                "Make sure out.iw = max(in1.iw, in2.iw) + 1 and out.qw = max(in1.qw, in2.qw)!"});

    // resize in1 and in2 to have the same word length with an aligned binary point


    sfp.in    in,        // input sfp signal
    sfp.out   out        // output sfp signal
);

    sfp_resize_ind #(.clip(clip)) u_resize_ind (.in(in), .out(out), .clipping());


      HSIZE_B64  : get_bytes_per_beat =   8;
      HSIZE_B128 : get_bytes_per_beat =  16;
      HSIZE_B256 : get_bytes_per_beat =  32;


hburst = (HDATA_SIZE == 64) ? HBURST_INCR4 : HBURST_SINGLE;


    .ip       ( ip       ), //Interrupt Pending

    .ie       ( ie       ), //Interrupt Enable


  always @(posedge clk_i,negedge rst_ni)
    if      (!rst_ni      ) priority_o <= 0;
    else if ( ip_i && ie_i) priority_o <= priority_i;


output [SOURCES      -1:0] ip,                  //Interrupt Pending for each source


      case (register_function(write_register))
        ID     : ; //A write to ID generates a strobe signal
        default: registers[write_register] <= gen_wval( registers[write_register], wdata, be);
      endcase


             else
               nxt_pending_cnt = pending_cnt;
      2'b11: nxt_pending_cnt = pending_cnt; //do nothing
    endcase


  parameter PRIORITIES = 7,
  parameter HI         = 16,
  parameter LO         = 0,

  //These should be localparams, but that's not supported by all tools yet


                else
                    next_state = AXI_MASTER_0;
            end
            AXI_MASTER_2: begin                 //2号主机占用总线状态，响应请求优先级为：2>3>0>1


                s_AWREGION  =  m0_AWREGION;
                s_AWUSER    =  m0_AWUSER;
                s_AWVALID   =  m0_AWVALID;
                s_WID       =  m0_WID;


                s0_RREADY  = '0;
                s1_RREADY  = '0;


	//写数据通道
	logic	[31:0]		WID;
	logic	[1023:0]	WDATA;
	logic	[127:0]		WSTRB;
	logic	  			WLAST;


        else
            AWVALID <= #TCO AWVALID;
    end

    always_ff@(posedge ACLK, negedge ARESETn)begin


instr = {instr, $sformatf("csrr x%0d, 0x%0x # %0s", cfg.gpr[0], status, status.name())};


privileged_mode_t supported_privileged_mode[] = {MACHINE_MODE};


assign level_intpend_w_prior_en_1[m+1] = '0 ;


.debug_brkpt_status    (debug_brkpt_status),


      2'b00:  mnemonic = "sb";
      2'b01:  mnemonic = "sh";
      2'b10:  mnemonic = "sw";
      default: begin
        decode_mnemonic("INVALID");


parameter logic [31:0] INSN_FENCE   = { 17'b?,             3'b000, 5'b?, {OPCODE_MISC_MEM} };


.o_register_read_data   (w_register_read_data[64*(4+i)+:64]),


`rggen_ral_create_field(error_src, 1, 1, "RO", 1, 1'h0, 1, -1, "")


      dma_desc[i].src_addr  = dma_desc_src_vec[i*`DMA_ADDR_WIDTH +: `DMA_ADDR_WIDTH];
      dma_desc[i].dst_addr  = dma_desc_dst_vec[i*`DMA_ADDR_WIDTH +: `DMA_ADDR_WIDTH];
      dma_desc[i].num_bytes = dma_desc_byt_vec[i*`DMA_ADDR_WIDTH +: `DMA_ADDR_WIDTH];
      dma_desc[i].wr_mode   = dma_mode_t'(dma_desc_wr_mod[i]);
      dma_desc[i].rd_mode   = dma_mode_t'(dma_desc_rd_mod[i]);


output  logic [WIDTH-1:0]                   data_o,


  always_comb begin : wr_streamer
    dma_stream_wr_o   = s_dma_str_in_t'('0);


    .dma_abort_i      (dma_ctrl_i.abort_req),
    .dma_maxb_i       (dma_ctrl_i.max_burst),


        'd2:  strobe = 'b0011;
        'd3:  strobe = 'b0111;
        'd4:  strobe = 'b1111;
        default:  strobe = '0;
      endcase


  output logic        [3:0] dma_m_awregion,
  output axi_user_req_t     dma_m_awuser,


);
    localparam ADD = 2'b00,
        SUB = 2'b01,
        MUL = 2'b10,


                                channel_serving_consumer[j] = 1;
                                current_consumer[i] <= j;


                        decoded_reg_write_enable <= 1;
                        decoded_reg_input_mux <= 2'b10;
                    end


            done <= 0;
            blocks_dispatched = 0;
            blocks_done = 0;


                FETCHED: begin
                    // Reset when core_state = DECODE
                    if (core_state == 3'b010) begin
                        fetcher_state <= IDLE;


                always @(posedge clk) begin
                    lsu_read_valid[lsu_index] <= core_lsu_read_valid[j];
                    lsu_read_address[lsu_index] <= core_lsu_read_address[j];


    parameter DATA_MEM_DATA_BITS = 8,
    parameter PROGRAM_MEM_ADDR_BITS = 8
) (
    input wire clk,


                            // LDR
                            registers[decoded_rd_address] <= lsu_out;


                end
                REQUEST: begin


function void {:NAME:}Agent::build_phase (uvm_phase phase);


`uvm_info(tID, $sformatf("build_phase begin ..."), UVM_HIGH)


function {:NAME:}Scoreboard::new (string name="{:NAME:}Scoreboard", uvm_component parent=null);


extern function new (string name="{:NAME:}Sequence");


module {:NAME:}_test_top;

    import uvm_pkg::*;
    import {:NAME:}_test_pkg::*;


extern function void   do_copy (uvm_object rhs);


   axis_gpio
     #(
       .BYTE_START(BYTE_START),


ERROR expression expression ERROR primary mintypmax_expression expression

if ((gpio_in_q[i] == 0) && (gpio_out_i[i] == 1)) begin


                     // No prefix, skip to data
                     next_state = DATA;


                  next_state = current_state;

               end
            end


    // input slave axis interface
    input [WORD_LENGTH-1:0] s_axis_data,
    input		    s_axis_valid,
    input		    s_axis_last,
    output		    s_axis_ready,


	 DATA:  begin
	    assert(uart_data_counter < WORD_LENGTH);
	    assert(UART_TX == fv_data[uart_data_counter]);


   assign lfsr_c[9] = (data_in[1] ^ lfsr_q[1] ^ lfsr_q[11]);
   assign lfsr_c[10] = lfsr_q[12];
   assign lfsr_c[11] = lfsr_q[13];


   assign header.ipv4.time_to_live = {<<8{TIME_TO_LIVE}};
   assign header.ipv4.protocol = {<<8{PROTOCOL}};
   assign header.ipv4.header_checksum = {<<8{HEADER_CHECKSUM}};


            end
          DATA  :
            begin
               tx_valid = 1;
               tx_data  = data_buffer[MII_WIDTH-1:0];


	   end
	end
     end // always @ (posedge clk)

   typedef struct      packed {


    output [1:0]	ETH_TXD,

    // Ports of Axi Master Bus Interface M00_AXIS
    input wire		m00_axis_aclk,
    input wire		m00_axis_aresetn,


ShiftRegMC ShiftRead (.clock, .reset, .ShiftInput(ShiftInputRd), .ShiftOutput(ShiftOutputRd));


((cs_n === LOW) && (cke === `HIGH) && $fell(act_n))|-> ##TRCD ($fell(`CAS) || $rose(act_n));


			5'b10000: next = write;
			5'b01000: next = read;
			5'b00100: next = writeA;
			5'b00010: next = readA;


	input write,
	output [63:0] DataBus,
	input [7:0][63:0] DataHost,
	output logic DQS_t,
	output logic DQS_c);


assign read_valid = IF.valid_data;

endmodule


module CountdownTimer(clock, Reset, HitZero,Load);
input clock;
input Reset;
input logic [31:0] Load;


uvm_config_db#(virtual spi_interface)::set(this, "agt", "vif", vif);


          data_out_reg<=shift_reg;
        else if(count<8)begin


  assign data_out=read?data_out_reg:8'h00;

  always@(posedge sclk)
    if(load) begin


function void build_phase(uvm_phase phase);


  property p2;
    @(posedge mclk)
      disable iff(!reset)
    load_slave|->!read_slave;


if ( ld_params_rd_reg & (lt_params[(PARAMS_BITS+225)+:5]==ENGINE_ID) )// (lt_params[233:226] == ENGINE_ID))


                        state             <= RD_END;
                    else


    reg             [31:0] work_group_size;
    reg             [31:0] stride         ;
    reg                    isRdLatencyTest;
    reg             [63:0] mem_op_index   ;
    reg [ADDR_WIDTH - 1:0] offset_addr    ;


 xdma_control  #(
 .N_MEM_INTF        (N_MEM_INTF),
 .N_ULTRARAM_INTF   (N_ULTRARAM_INTF)


          end
          else
            r_nstate                    = RIDLE;
        end


.AXI_17_ARESET_N     (hbm_axi[17].arstn  ), //resetn


output              [15:0] lat_timer       ,


                    state                 <= RD_END;
                end
            end

            RD_END:


          else
            r_nstate                    = RIDLE;
        end


      READ_WRITE: begin
        //  Read data is available


  reg [5:0] data_read_state = 0;

  localparam READ_ADDRESS_DELAY = 1;


  synch_3 rx_synch (
      cart_tran_pin31,


          begin
            addr[15:12] <= digit;


    end

    prev_audio_mclk <= audio_mclk;
  end


      READ_DELAY: begin
        read_state <= READ_WRITE;
      end


);

  reg [WIDTH-1:0] stage_1;
  reg [WIDTH-1:0] stage_2;


  end

  always begin
    #half_period_mem clk_memory = ~clk_memory;
  end


    else $error("read_en changed");

    #(8 * period_mem);


  localparam period = 20;
  localparam half_period = period / 2;

  localparam period_read = 10;


    input  logic [WID-1:0] win,   // Write data
    input  logic [WID-1:0] din,   // Current value
    input  logic           cin,   // Carry in
    output logic [WID-1:0] dout,  // New value


        ta_ctrl.toggle = ctrl.cra.outmode;
        tb_ctrl.toggle = ctrl.crb.outmode;

        // Contrary to what's stated in the datasheet, the control register
        // LOAD bit is actually stored, and is ANDed with the control register


        .phi2_dn (phi2_dn),
        .res     (res),


    input  logic phi2_dn,
    input  logic pad_i,
    output logic posedge_o


    input  logic        rd,
    input  logic        we,
    input  cia::reg4_t  addr,


                tx_sp_next <= sr[7];
            end
        end


    always_comb begin
        prescaler_next = { hi_w ? data : prescaler[15:8], lo_w ? data : prescaler[7:0] };


          2'b01: { tod_sample, tod_hold } = 2'b01;
          2'b10: { tod_sample, tod_hold } = 2'b10;
          2'b11: { tod_sample, tod_hold } = 2'b00;
        endcase


    // Reset is asserted from the very beginning.
    always_comb begin
        rst_24 = !(bram_cnt == 8'hff);


    inout logic PB0,
    inout logic PB1,


        if(rst) begin
            data_out <= 0;


ERROR for_step operator_assignment expression expression primary


		altpll_component.port_extclk2 = "PORT_UNUSED",
		altpll_component.port_extclk3 = "PORT_UNUSED",
		altpll_component.width_clock = 5;


                ram_pong[ram_wr_addr] <= i_data;
            end
            ram_wr_addr <= ram_wr_addr + 1;
            if(ram_wr_addr == ram_cmp) begin
                ram_select  <= ~ram_select;


            case(nibble_idx)
                0: nibble_to_send = sample_out[23:20];
                1: nibble_to_send = sample_out[19:16];
                2: nibble_to_send = sample_out[15:12];
                3: nibble_to_send = sample_out[11:8];


            tx_baud_en <= 0;
        end
        if(rst) begin


    bit [DAC_BITLEN:0] acc1 = 0;
    always_ff @(posedge clk) begin
        acc1 <= acc1[DAC_BITLEN-1:0] + dac_input;


            sample_in = sample_in + 1;
            //write to file
            $fdisplay(fd, "%f", adc_input);
            //wait for clock


        wait(rst == 0);
        fd = $fopen(OUTPUT_FILE, "w");
        repeat(50) @(posedge clk);


    bit sim_done = 0;
    initial begin
        $dumpfile("dump.vcd");
        $dumpvars;
        wait(sim_done == 1);


			 axim.BREADY = '0;
			 BNext_state_M = B_START_M;
			end


                                                        wrap_boundary2 = 16 * 1;
                                                    end

                                             3'b001:begin
                                                        wrap_boundary2 = 16 * 2;


// After WLAST is asserted, slave should initiate response
property AXI_WLAST_BVALID_p;
@(posedge clk)


env.drvr.read_size_invalid(rand_awid, rand_awaddr_valid, rand_awaddr_invalid, rand_awaddr_readonly, rand_wdata, rand_araddr_valid, rand_araddr_invalid, rand_arid );


                                                address_slave_reg = address_slave_temp;

                                            read_mem[address_slave_reg] =  axim.RDATA[15:8];


                                                    end

                                             3'b010:begin
                                                        wrap_boundary2 = 4 * 4;


logic	[1:0]	AWBURST;
logic	[2:0]	AWSIZE;


        if (check_clr_req_i) begin
            check_clr_gnt_o = 1'b1;


                    end else begin
                        aw_state_d = SEND_AW;
                    end
                    // Remember outstanding W beats before injected request
                    if (aw_state_q == WAIT_RESULT_AW) begin


`ifndef VERILATOR
    initial begin: validate_params
        assert (DATA_WIDTH > 0)


logic [2:0]                  int_axi_ar_size;


.CUT_OUP_POP_INP_GNT ( CutOupPopInpGnt )


        .AXI_MAX_READ_TXNS   (AXI_MAX_READ_TXNS),
        .AXI_MAX_WRITE_TXNS  (AXI_MAX_WRITE_TXNS),
        .AXI_USER_AS_ID      (AXI_USER_AS_ID),
        .AXI_USER_ID_MSB     (AXI_USER_ID_MSB),
        .AXI_USER_ID_LSB     (AXI_USER_ID_LSB),


                if (!(slv_ar_valid_i && slv_ar_lock_i &&
                        slv_ar_addr_i[AXI_ADDR_WIDTH-1:AXI_ADDR_LSB] == clr_addr_q)) begin


    input  logic    rst_ni,
    AXI_BUS.Master  mst,
    AXI_BUS.Slave   slv


        .slv_aw_valid_i(slv_aw_valid_i),

        .slv_ar_addr_i(slv_ar_addr_i),
        .slv_ar_prot_i(slv_ar_prot_i),
        .slv_ar_region_i(slv_ar_region_i),


automatic logic [2:0]                size;


input   [AXI_USER_WIDTH-1:0]   mst_r_user_i,


                    end
                    default: begin
                        w_data = data_uo;


slave = axi_slave::type_id::create("slave", this);


input AWID, AWADDR, AWLEN, AWSIZE, AWBURST,AWVALID, WID, WDATA, WSTRB, WLAST, WVALID,


if(!uvm_config_db#(test_config)::get(null, "uvm_test_top.seq", "config", test_cfg))


virtual axi_intf#(.D_WIDTH(D_WIDTH), .A_WIDTH(A_WIDTH)).SMON vif;


        env_cfg.intf = intf;
        uvm_config_db#(env_config)::set(null, "uvm_test_top", "config", env_cfg);
        uvm_config_db#(env_config)::set(null, "uvm_test_top.env.master", "config", env_cfg);


  input reset;
  output locked;
  input clk_in1_p;


if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin


phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;


even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);


    .gt_rxn                   ( SATA0_B_N                              ),
    .gt_txp                   ( SATA0_A_P                              ),
    .gt_txn                   ( SATA0_A_N                              ),
    // user clock output
    .clk                      ( clk                                    ),


                end
                S_DATA: begin
                    cnt <= cnt + 5'd1;
                    if(cnt[1:0] == '1) rx_data <= {rbit, rx_data[7:1]};
                    if(cnt      == '1) stat <= (PARITY=="NONE") ? S_OKAY : S_PARI;


        txdata     <= '1;
        fifo_rptr  <= '0;
        fifo_rd_en <= '0;
        {send_data, send_last} <= '0;


            end
            WAIT_RD_DATA : begin
                gtrxreset_o <= 1'b1;


wire        gt_txoutclk;
wire        drp_clk;


PRIM_R_ERR : begin  rx_dword_en <= 1'b1;                             end


always@(posedge clk)
 if (Res)
  ECC_status <= 1'h0;
 else


assign ecc[7]=1'b0;
assign ecc[6]=rp1;
assign ecc[5]=rp2;
assign ecc[4]=Din[3];


if(command[2] != {bfm.CE_n,bfm.CLE,bfm.ALE,bfm.RE_n,bfm.WE_n}) begin


ERROR ERROR expression primary concatenation ERROR expression expression primary

bins SysReset_and_Write		= binsof(Commands) intersect {program_page} && (binsof(SystemReset.SysReset));				// System reset and write command active at the same time


     2'b10 : addr_data <= rad_1;
     2'b01 : addr_data <= cad_2;
     default: addr_data <= cad_1;
  endcase


	case(random_cmd)
		program_page:	write_cycle(Addr);

		read_page:	read_cycle(Addr);


localparam int MTR_BASE            = (PRV_BASE + 2);            // metrics base address


            state_next = S_AWAIT_REGS;
          end
        end else if (csValid == 0) begin
          // CPU is responding with a write to the CPU->FPGA queue
          state_next = S_AWAIT_CONSUME_END;


localparam int BENCHMARK_TIMER     = makestuff_tlp_xcvr_pkg::CTL_BASE - 1;


    .rxData_out       (rxData),  // Host->FPGA pipe
    .rxSOP_out        (rxSOP),
    .rxEOP_out        (rxEOP),
    .rxValid_out      (rxValid),


.txdetectrx4      (1'b0),                                                                                // (terminated)


.rx_in6           (),                                                                                // (terminated)


localparam int REG_BAR             = (0);


    .c2fWrData_out   (c2fWrData),
    .c2fRdPtr_out    (c2fRdPtr),
    .c2fDTAck_in     (c2fDTAck)
  );


localparam int CHECKSUM_MSW  = makestuff_tlp_xcvr_pkg::CTL_BASE - 1;


  logic txEOP;
  logic txValid;
  logic txReady;

  pcie_sv pcie_inst(


1,                  // display EP config space after setup


.dut_hip_pipe_rxvalid3         (dut_pcie_tb_hip_pipe_rxvalid3)             //               .rxvalid3


.powerdown5       (2'b00),                                                                                // (terminated)


import monitor_clear, monitor_write, monitor_read


if (now.psel == 1'b1 && now.penable == 1'b1 && now.pready == 1'b1)


assert (rx.data[0].last == (tx.data.size == tx.addr.len));


this.txid = $urandom_range(0, (1 << TXID_BITS) - 1);


assert (fixed_1b.data[2].strb == 16'h0040);


virtual interface axi_intf #(WIDTH, SIZE) intf;


) extends uvm_sequence#(axi_m_Sequence_Item#(WIDTH, SIZE));


drv = axi_s_driver#(WIDTH, SIZE)::type_id::create("drv", this);


function new(string name="axi_s_driver",uvm_component parent);


drv2sb_export_drv = new("drv2sb_export_drv", this);


                read_burst_next = s_axi_arburst;

                s_axi_arready_next = 1'b0;
                read_state_next = READ_STATE_BURST;


      .clk          (intf.clk),
      .s_axi_wdata  (intf.WDATA),
      .s_axi_wstrb  (intf.WSTRB),
      .s_axi_wvalid (intf.WVALID),


#(
    parameter bit [2:0] AUDIO_CHANNEL_COUNT = 3'd1, // 2 channels. See CEA-861-D table 17 for details.
    parameter bit [7:0] CHANNEL_ALLOCATION = 8'h00, // Channel 0 = Front Left, Channel 1 = Front Right (0-indexed)
    parameter bit DOWN_MIX_INHIBITED = 1'b0, // Permitted or no information about any assertion of this. The DM_INH field is to be set only for DVD-Audio applications.


                aligned_frame_counter[i] = 8'(frame_counter + i - CHANNEL_STATUS_LENGTH);
            else
                aligned_frame_counter[i] = 8'(frame_counter + i);
        end
        assign header[23 - (3-i)] = aligned_frame_counter[i] == 8'd0 && audio_sample_word_present[i];


    parameter bit [1:0] PICTURE_ASPECT_RATIO = 2'b00, // No data, See CEA-CEB16 for more information about Active Format Description processing.
    parameter bit [3:0] ACTIVE_FORMAT_ASPECT_RATIO = 4'b1000, // Not valid unless ACTIVE_FORMAT_INFO_PRESENT = 1'b1, then Same as picture aspect ratio


    input logic reset,
    input logic data_island_period,
    input logic [23:0] header, // See Table 5-8 Packet Types
    input logic [55:0] sub [3:0],


    if (reset || video_field_end)
    begin
        audio_info_frame_sent <= 1'b0;


        assign sub[i] = {packet_bytes[6 + i*7], packet_bytes[5 + i*7], packet_bytes[4 + i*7], packet_bytes[3 + i*7], packet_bytes[2 + i*7], packet_bytes[1 + i*7], packet_bytes[0 + i*7]};
    end
endgenerate

endmodule


module spd_tb();

logic [55:0] sub [3:0];

source_product_description_info_frame #(


            s_axi_arready_next = 1'b1;

            if (s_axi_arready && s_axi_arvalid) begin


                    axi_arlen = (LINE_WIDTH / AXI_DATA_WIDTH) - 1;
                    read_state = R_DFETCH;
                end else begin


    addr_t stable_addr, stable_addr_q;
    logic [DATA_WIDTH/8-1:0] stable_wstrb;
    logic [DATA_WIDTH/8-1:0] stable_wstrb_q;
    logic [DATA_WIDTH-1:0] stable_wdata;


    output var                       imem_fault,

    output var [ADDRESS_WIDTH-1:0]   req_addr,
    output var                       req_valid,


module resetgen(input wire clock, input wire reset, input wire axi_arvalid, input wire axi_arready);
    initial assume(reset);
endmodule


	(* keep *) `rvformal_rand_reg next_dmem_res_r_valid;
	(* keep *) `rvformal_rand_reg next_dmem_res_r_fault;


initial begin
	if ($test$plusargs("vcd")) begin
		$dumpfile("testbench.vcd");
		$dumpvars(0, testbench);


);

// Create reset signal 16 clocks long
reg reset = 1'b1;


	(* keep *) wire [31:0] dmem_addr;
	(* keep *) wire [ 3:0] dmem_wstrb;
	(* keep *) wire [31:0] dmem_wdata;

	wire [31:0] check_imem_addr;


10'b 0000100_001 /* ZIP   */: begin next_wr = insn[24:20] == 5'b 01111; illinsn = !next_wr; next_rd = 0; for (int i=0; i<16; i=i+1) begin next_rd[2*i] = rs1_value[i]; next_rd[2*i+1] = rs1_value[i+16]; end end


		.reset     (reset     ),
		.stall     (stall     ),


			READ :  next_state = (axibus_s[sel_s].r.valid && axibus_m[sel_m].r.ready) ? IDLE : READ;
			WRITE : next_state = (axibus_s[sel_s].b.valid && axibus_m[sel_m].b.ready) ? IDLE : WRITE;


input araddr, arvalid, output arready, input arlen, arsize, arburst,


			IDLE : next_state = (start_read_delay) ? RADDR : ((start_write_delay) ? WADDR : IDLE);
			RADDR : if (m_axi.arvalid && m_axi.arready) next_state = RDATA;
			RDATA : if (m_axi.rvalid  && m_axi.rready && m_axi.rlast) next_state = IDLE;


					addr  <= s_axi.araddr;
					len   <= s_axi.arlen;
					size  <= s_axi.arsize;
					burst <= s_axi.arburst;


		end else begin
			start_read_delay  <= start_read;
			start_write_delay <= start_write;
		end


typedef logic [STRB_WIDTH - 1 : 0] strb_t;


			IDLE : next_state = (s_axi_lite.arvalid) ? RADDR : (s_axi_lite.awvalid) ? WADDR : IDLE;
			RADDR : if (s_axi_lite.arvalid && s_axi_lite.arready) next_state = RDATA;
			RDATA : if (s_axi_lite.rvalid  && s_axi_lite.rready ) next_state = IDLE;
			WADDR : if (s_axi_lite.awvalid && s_axi_lite.awready) next_state = WDATA;
			WDATA : if (s_axi_lite.wvalid  && s_axi_lite.wready ) next_state = WRESP;


		case (state)
			IDLE : if (start_delay) next_state = SEND;
			SEND : if (m_axi_stream.tlast) next_state = IDLE;
			default : next_state = IDLE;
		endcase


typedef logic [DATA_WIDTH - 1 : 0] data_t;


		case (state)
			IDLE : next_state = RECV;
			RECV : next_state = RECV;
			default : next_state = IDLE;
		endcase


  input  logic clk_i,
  output logic clk_o
);

  tc_clk_buffer i_tc_clk_buffer (


                assign M[i*8+j] = BEN[i];
             end
        end
   endgenerate


  input  logic [ADDR_WIDTH-1:0] A,
  output logic [DATA_WIDTH-1:0] Q


  input  logic clk0_i,
  input  logic clk1_i,
  input  logic clk_sel_i,
  output logic clk_o
);


  pulp_clock_gating i_clk_gate (
    .clk_i,
    .en_i ( r_reg[STAGES-1] ),
    .test_en_i,


  output logic sleepout_o
);

  assign sleepout_o = sleep_i;


  end

`endif
`endif
// pragma translate_on


  assign clk_o = clk0_i & clk1_i;

endmodule


        "zeros":  init_val[i] = {DataWidth{1'b0}};
        "ones":   init_val[i] = {DataWidth{1'b1}};
        "random": init_val[i] = {DataWidth{$urandom()}};
        default:  init_val[i] = {DataWidth{1'bx}};
      endcase


  input  logic                 rst_ni,     // Asynchronous reset active low
  // implementation-related IO


  input  logic ena_i,
  output logic data_o
);

  assign data_o = ena_i ? data_i : 1'b0;