// Copyright 2019 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.

// Author: Robert Balas <balasr@iis.ee.ethz.ch>

module fifo_v3_properties #(
    parameter bit          FALL_THROUGH = 1'b0, // fifo is in fall-through mode
    parameter int unsigned DATA_WIDTH   = 32,   // default data width if the fifo is of type logic
    parameter int unsigned DEPTH        = 8,    // depth can be arbitrary from 0 to 2**32
    parameter type dtype                = logic [DATA_WIDTH-1:0],
    // DO NOT OVERWRITE THIS PARAMETER
    parameter int unsigned ADDR_DEPTH   = (DEPTH > 1) ? $clog2(DEPTH) : 1
) (
    input logic                    clk_i, // Clock
    input logic                    rst_ni, // Asynchronous reset active low
    input logic                    flush_i, // flush the queue
    input logic                    testmode_i, // test_mode to bypass clock gating
    // status flags
    input logic                    full_o, // queue is full
    input logic                    empty_o, // queue is empty
    input logic [ADDR_DEPTH-1:0]   usage_o, // fill pointer
    // as long as the queue is not full we can push new data
    input logic                    push_i, // data is valid and can be pushed to the queue
    // as long as the queue is not empty we can pop new elements
    input logic                    pop_i, // pop head from queue

    input logic [ADDR_DEPTH - 1:0] read_pointer_n,
    input logic [ADDR_DEPTH - 1:0] read_pointer_q,
    input logic [ADDR_DEPTH - 1:0] write_pointer_n,
    input logic [ADDR_DEPTH - 1:0] write_pointer_q,

    input logic [ADDR_DEPTH:0]     status_cnt_n, // counter to keep track of the current queue status
    input logic [ADDR_DEPTH:0]     status_cnt_q
);

    localparam int unsigned FIFO_DEPTH = (DEPTH > 0) ? DEPTH : 1;
    // verbatim from fifo_v3
    localparam int unsigned FIFO_SIZE  = FIFO_DEPTH[ADDR_DEPTH:0];

    logic [ADDR_DEPTH-1:0] fill_level;
    logic                  read_incr;
    logic                  write_incr;
    int                    writes = 0; // number of writes to fifo
    int                    reads  = 0; // number of reads from fifo

    // We use this as a workaround to trigger and initial event at the beginning
    // of the simulation. I can't think of a better way with the subset of sv
    // yosys supports.
    logic init = 1'b0;
    always_ff @(posedge clk_i) init <= 1'b1;

    // make sure that we touch the reset but otherwise we don't constrain it in
    // any way

    // assume property(@(posedge clk_i)
    //     disable iff (!rst_ni) (empty_o |-> !pop_i));

    assign fill_level = writes - reads;
    assign read_incr = read_pointer_n - read_pointer_q;
    assign write_incr = write_pointer_n - write_pointer_q;

    // writes and reads track the number of writes and reads to the fifo. Our
    // assumption and assertions make sure that these values stay logically
    // consistent.
    always_ff @(posedge clk_i, negedge rst_ni) begin
        if (!rst_ni) begin
            writes <= 0;
            reads  <= 0;
        end else begin
            if (flush_i) begin
                writes <= 0;
                reads  <= 0;
            end else begin
                writes <= writes + write_incr;
                reads  <= reads + read_incr;
            end
        end
    end

    // assume that we test for a finite amount of transactions otherwise the
    // solver tries to be cute by overflowing the writes and reads variables
    assume property (@(posedge clk_i)
        (reads < 1024 && writes < 1024));
    // start induction with correct internal fill level
    assume property (@(posedge clk_i)
        ((writes - reads) == status_cnt_q));

    // don't underflow
    assert property (@(posedge clk_i)
        (writes >= reads));
    // don't overflow
    assert property (@(posedge clk_i)
        ((writes - reads) <= FIFO_SIZE));

    // do we set fill indicators properly
    assert property (@(posedge clk_i)
        ((writes == reads) |-> empty_o));
    assert property (@(posedge clk_i)
        (((writes - reads) == FIFO_SIZE) |-> full_o));
    // check if we compute fill level correctly
    assert property (@(posedge clk_i)
        disable iff (!rst_ni) (fill_level == usage_o));

    // sanity of internal vars
    assert property (@(posedge clk_i)
        status_cnt_q <= FIFO_SIZE);

    // make sure we hit the interesting cases
    cover property (@(posedge clk_i)
        full_o == 1'b1);
    cover property (@(posedge clk_i)
        empty_o == 1'b1);

endmodule // fifo_v3_properties

// propagate parameters from fifo_v3 to properties
bind fifo_v3 fifo_v3_properties #(
    .FALL_THROUGH(FALL_THROUGH), .DATA_WIDTH(DATA_WIDTH), .DEPTH(DEPTH)
) i_fifo_v3_properties(.*);

    assume property (@(posedge clk_i) (!init) |-> !rst_ni);

    // we don't have tests for FALL_THROUGH mode
    always_comb assert (FALL_THROUGH == 1'b0);


//----------------------------------------------------------------------------------
// This code is copyrighted by BrentWang and cannot be used for commercial purposes
// The github address:https://github.com/brentwang-lab/uvm_tb_gen
// You can refer to the book <UVM Experiment Guide> for learning, this is on this github
// If you have any questions, please contact email:brent_wang@foxmail.com
//----------------------------------------------------------------------------------
//
// Author  : BrentWang
// Project : UVM study
// Date    : Sat Jan 26 06:05:52 WAT 2022
//----------------------------------------------------------------------------------
//
// Description:
//     File for dadd_environment.sv
//----------------------------------------------------------------------------------
class dadd_environment extends uvm_env;
    `uvm_component_utils(dadd_environment)
    virtual dadd_interface vif;
    uvm_event_pool event_pool;
    dadd_iagent iagt;

    dadd_refmodel refmdl;
    dadd_scoreboard scb;
    uvm_tlm_analysis_fifo #(dadd_item) dadd_iagt_to_refmdl_fifo;
    uvm_tlm_analysis_fifo #(dadd_item) dadd_oagt_to_scb_fifo;
    uvm_tlm_analysis_fifo #(dadd_item) dadd_refmdl_to_scb_fifo;
    extern function new(string name ="dadd_environment", uvm_component parent);
    extern function void build_phase(uvm_phase phase);
    extern function void connect_phase(uvm_phase phase);
    extern task          reset_phase(uvm_phase phase);
endclass: dadd_environment

function dadd_environment :: new(string name ="dadd_environment", uvm_component parent);
    super.new(name, parent);
endfunction: new

function void dadd_environment :: build_phase(uvm_phase phase);
    iagt = dadd_iagent :: type_id :: create("iagt",this);
    oagt = dadd_oagent :: type_id :: create("oagt",this);
    refmdl = dadd_refmodel :: type_id :: create("refmdl",this);
    scb =  dadd_scoreboard :: type_id :: create("scb",this);
    dadd_iagt_to_refmdl_fifo = new("dadd_iagt_to_refmdl_fifo",this);
    dadd_oagt_to_scb_fifo = new("dadd_oagt_to_scb_fifo",this);
    dadd_refmdl_to_scb_fifo = new("dadd_refmdl_to_scb_fifo",this);
    if(!uvm_config_db #(virtual dadd_interface) :: get(this,"","vif",vif))
        `uvm_fatal("dadd_environment","The interface is not get !!!");
    iagt.vif = vif;
    oagt.vif = vif;
    oagt.event_pool = event_pool;

endfunction : build_phase

function void dadd_environment :: connect_phase(uvm_phase phase);
    iagt.ap.connect(dadd_iagt_to_refmdl_fifo.analysis_export);
    refmdl.port.connect(dadd_iagt_to_refmdl_fifo.blocking_get_export);

    oagt.ap.connect(dadd_oagt_to_scb_fifo.analysis_export);
    scb.act_port.connect(dadd_oagt_to_scb_fifo.blocking_get_export);

    refmdl.ap.connect(dadd_refmdl_to_scb_fifo.analysis_export);
    scb.exp_port.connect(dadd_refmdl_to_scb_fifo.blocking_get_export);

endfunction : connect_phase

task          dadd_environment :: reset_phase(uvm_phase phase);
    dadd_iagt_to_refmdl_fifo.flush();
    dadd_oagt_to_scb_fifo.flush();
    dadd_refmdl_to_scb_fifo.flush();
endtask : reset_phase


//----------------------------------------------------------------------------------
// This code is copyrighted by BrentWang and cannot be used for commercial purposes
// The github address:https://github.com/brentwang-lab/uvm_tb_gen
// You can refer to the book <UVM Experiment Guide> for learning, this is on this github
// If you have any questions, please contact email:brent_wang@foxmail.com
//----------------------------------------------------------------------------------
//
// Author  : BrentWang
// Project : UVM study
// Date    : Sat Jan 26 06:05:52 WAT 2022
//----------------------------------------------------------------------------------
//
// Description:
//     File for apb_master_config.sv
//----------------------------------------------------------------------------------
`ifndef APB_MASTER_CONFIG__SV
`define APB_MASTER_CONFIG__SV
class apb_master_config extends apb_base_config;
    bool use_reg_model = False;
    `uvm_object_utils_begin(apb_master_config)

    `uvm_object_utils_end

    extern function new(string name = "apb_master_config");
endclass : apb_master_config

function apb_master_config :: new(string name = "apb_master_config");
    super.new(name);
endfunction : new
`endif// APB_MASTER_CONFIG__SV


`define bsg_mem_1r1w_sync_mask_write_bit_2rf_macro(words,bits,tag) \
  `bsg_mem_1r1w_sync_mask_write_bit_macro(words,bits,tag)
`define bsg_mem_1r1w_sync_mask_write_bit_2sram_macro(words,bits,tag) \
  `bsg_mem_1r1w_sync_mask_write_bit_macro(words,bits,tag)
`define bsg_mem_1r1w_sync_mask_write_bit_2hdsram_macro(words,bits,tag) \
  `bsg_mem_1r1w_sync_mask_write_bit_macro(words,bits,tag)

`define bsg_mem_1r1w_sync_mask_write_bit_macro(words,bits,tag)\
  if (harden_p && els_p == words && width_p == bits)          \
    begin: macro                                              \
      bsg_mem_1r1w_sync_mask_write_bit_w``bits``_d``words``_``tag``_hard mem (.*); \
    end

`endif


//
// Paul Gao 08/2019
//
//

`timescale 1ps/1ps

`include "bsg_noc_links.svh"

module bsg_fifo_1r1w_small_hardened_tester

 #(parameter top_num_clocks_p = 3
  ,parameter width_p  = 64
  ,parameter els_p    = 4
  ,parameter channel_width_p = 8
  )

  ();

  `declare_bsg_ready_and_link_sif_s(width_p, bsg_ready_and_link_sif_s);

  logic master_clk, master_reset;
  logic client_clk, client_reset;
  logic fifo_clk, fifo_reset;

  logic master_en;
  logic master_error;
  logic [31:0] master_sent, master_received;

  bsg_ready_and_link_sif_s master_node_link_li;
  bsg_ready_and_link_sif_s master_node_link_lo;

  bsg_ready_and_link_sif_s client_node_link_li;
  bsg_ready_and_link_sif_s client_node_link_lo;

  bsg_fifo_1r1w_small_hardened_test_node
 #(.num_channels_p(width_p/channel_width_p)
  ,.channel_width_p(channel_width_p)
  ,.is_client_node_p(0)
  ) master_node
  (.node_clk_i  (master_clk)
  ,.node_reset_i(master_reset)
  ,.node_en_i   (master_en)

  ,.error_o   (master_error)
  ,.sent_o    (master_sent)
  ,.received_o(master_received)

  ,.clk_i   (fifo_clk)
  ,.reset_i (fifo_reset)

  ,.link_i(master_node_link_li)
  ,.link_o(master_node_link_lo)
  );

  bsg_fifo_1r1w_small
 #(.width_p (width_p)
  ,.els_p   (els_p)
  ,.harden_p(1)
  ) fifo_m2c
  (.clk_i  (fifo_clk)
  ,.reset_i(fifo_reset)
  ,.v_i    (master_node_link_lo.v)
  ,.ready_param_o(master_node_link_li.ready_and_rev)
  ,.data_i (master_node_link_lo.data)
  ,.v_o    (client_node_link_li.v)
  ,.data_o (client_node_link_li.data)
  ,.yumi_i (client_node_link_li.v & client_node_link_lo.ready_and_rev)
  );

  bsg_fifo_1r1w_small
 #(.width_p (width_p)
  ,.els_p   (els_p)
  ,.harden_p(1)
  ) fifo_c2m
  (.clk_i  (fifo_clk)
  ,.reset_i(fifo_reset)
  ,.v_i    (client_node_link_lo.v)
  ,.ready_param_o(client_node_link_li.ready_and_rev)
  ,.data_i (client_node_link_lo.data)
  ,.v_o    (master_node_link_li.v)
  ,.data_o (master_node_link_li.data)
  ,.yumi_i (master_node_link_li.v & master_node_link_lo.ready_and_rev)
  );

  bind bsg_fifo_1r1w_small_hardened bsg_fifo_1r1w_small_hardened_cov
 #(.els_p(els_p)
  ) pc_cov
  (.*
  );

  bsg_fifo_1r1w_small_hardened_test_node
 #(.num_channels_p(width_p/channel_width_p)
  ,.channel_width_p(channel_width_p)
  ,.is_client_node_p(1)
  ) client_node
  (.node_clk_i  (client_clk)
  ,.node_reset_i(client_reset)
  ,.node_en_i   (1'b0)

  ,.error_o   ()
  ,.sent_o    ()
  ,.received_o()

  ,.clk_i   (fifo_clk)
  ,.reset_i (fifo_reset)

  ,.link_i(client_node_link_li)
  ,.link_o(client_node_link_lo)
  );

  // Simulation of Clock
  localparam num_clocks_lp = top_num_clocks_p;
  wire [num_clocks_lp-1:0][31:0] clk_period_lo = {32'd7, 32'd5, 32'd3};

  logic [num_clocks_lp-1:0] master_clks, fifo_clks, client_clks;
  for (genvar i = 0; i < num_clocks_lp; i++)
  begin
    always #(clk_period_lo[i]) master_clks[i] = ~master_clks[i];
    always #(clk_period_lo[i])   fifo_clks[i]   = ~fifo_clks[i];
    always #(clk_period_lo[i]) client_clks[i] = ~client_clks[i];
  end

  logic [3:0] master_sel, fifo_sel, client_sel;
  assign master_clk = master_clks[master_sel];
  assign fifo_clk = fifo_clks[fifo_sel];
  assign client_clk = client_clks[client_sel];

  initial
  begin

    $display("Start Simulation\n");

    // Init
    master_clks = '1;
    fifo_clks = '1;
    client_clks = '1;

    #500;

    for (integer i = 0; i < num_clocks_lp; i++)
      begin
    for (integer j = 0; j < num_clocks_lp; j++)
      begin
    for (integer k = 0; k < num_clocks_lp; k++)
      begin

    master_sel = i;
    fifo_sel = j;
    client_sel = k;

    master_reset = 1;
    fifo_reset = 1;
    client_reset = 1;

    master_en = 0;

    #500;

    // fifo reset
    @(posedge fifo_clk); #1;
    fifo_reset = 0;
    $display("fifo reset LOW");
    #500;

    // node reset
    @(posedge master_clk); #1;
    master_reset = 0;
    @(posedge client_clk); #1;
    client_reset = 0;
    $display("node reset LOW");
    #500;

    $display("start running test");

    // node enable
    @(posedge master_clk); #1;
    master_en = 1;
    $display("node enable HIGH");

    #50000;

    // node disable
    @(posedge master_clk); #1;

    $display("node enable LOW");

    #5000

    assert(master_error == 0)
    else
      begin
        $error("\nFAIL... Error in loopback node");
        $finish;
      end

    assert(master_sent == master_received)
    else
      begin
        $error("\nFAIL... Loopback node sent %d packets but received only %d\n", master_sent, master_received);
        $finish;
      end

    end
    end
    end

    $display("\nPASS!\n");

    $display("Loopback node sent and received %d packets\n", master_sent);

    $finish;

  end

endmodule


//
// -------------------------------------------------------------
//    Copyright 2004-2011 Synopsys, Inc.
//    Copyright 2010 Mentor Graphics Corporation
//    Copyright 2010 Cadence Design Systems, Inc.
//    All Rights Reserved Worldwide
//
//    Licensed under the Apache License, Version 2.0 (the
//    "License"); you may not use this file except in
//    compliance with the License.  You may obtain a copy of
//    the License at
//
//        http://www.apache.org/licenses/LICENSE-2.0
//
//    Unless required by applicable law or agreed to in
//    writing, software distributed under the License is
//    distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
//    CONDITIONS OF ANY KIND, either express or implied.  See
//    the License for the specific language governing
//    permissions and limitations under the License.
// -------------------------------------------------------------
//

program test;

import uvm_pkg::*;
import apb_pkg::*;

`include "reg_model.sv"
`include "tb_env.sv"
`include "testlib.sv"

class dut_reset_seq extends uvm_sequence;

   function new(string name = "dut_reset_seq");
      super.new(name);
   endfunction

   `uvm_object_utils(dut_reset_seq)

   virtual task body();
      tb_top.rst = 1;
      repeat (5) @(negedge tb_top.clk);
      tb_top.rst = 0;
   endtask
endclass

initial
begin
   static tb_env env = new("env");

uvm_config_db#(apb_vif)::set(env, "apb", "vif", $root.tb_top.apb0);


//----------------------------------------------------------------------
//   Copyright 2010-2011 Cadence Design Systems, Inc.
//   Copyright 2010 Mentor Graphics Corporation
//   All Rights Reserved Worldwide
//
//   Licensed under the Apache License, Version 2.0 (the
//   "License"); you may not use this file except in
//   compliance with the License.  You may obtain a copy of
//   the License at
//
//       http://www.apache.org/licenses/LICENSE-2.0
//
//   Unless required by applicable law or agreed to in
//   writing, software distributed under the License is
//   distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
//   CONDITIONS OF ANY KIND, either express or implied.  See
//   the License for the specific language governing
//   permissions and limitations under the License.
//----------------------------------------------------------------------

//Field Macros:
//This test verifies that the auto-config functionality in uvm_field_sarray_object
//macro works as expected.
//
//The macros which are tested are:
//  `uvm_field_sarray_object

//Pass/Fail criteria:
//  The set_config_* must produce the correct results.
//

module test;
  import uvm_pkg::*;
  `include "uvm_macros.svh"

  typedef enum { RED, ORANGE, YELLOW, GREEN, BLUE, INDIGO, VIOLET } colors;

  class myobject extends uvm_sequence_item;
    colors color = RED;
    int    i = 0;
    string str = "default";

    `uvm_object_utils_begin(myobject)
      `uvm_field_enum(colors, color, UVM_DEFAULT)
      `uvm_field_int(i, UVM_DEFAULT)
      `uvm_field_string(str, UVM_DEFAULT)
    `uvm_object_utils_end

  function new(string name="myobject");
     super.new(name);
  endfunction

  endclass

  class container extends uvm_sequence_item;
    myobject object[3];
    int value = 0;
    `uvm_object_utils_begin(container)
      `uvm_field_sarray_object(object, UVM_DEFAULT)
      `uvm_field_int(value, UVM_DEFAULT)
    `uvm_object_utils_end
    function new(string name = "container");
      super.new(name);
      foreach(object[i]) object[i] = new;
      object[0].color = ORANGE; object[0].i = 'haa; object[0].str = "zero";
      object[1].color = GREEN; object[1].i = 'hbb; object[1].str = "one";
      object[2].color = VIOLET; object[2].i = 'hcc; object[2].str = "two";
    endfunction
  endclass

  class test extends uvm_test;
    container cfg_field_set_clone = new;
    container cfg_field_set_ref = new;
    container cfg_field_notset;
    container  cfg_field_set_sub = new;

    `uvm_new_func
    `uvm_component_utils_begin(test)
      `uvm_field_object(cfg_field_set_clone, UVM_DEFAULT)
      `uvm_field_object(cfg_field_set_ref, UVM_DEFAULT)
      `uvm_field_object(cfg_field_notset, UVM_DEFAULT)
      `uvm_field_object(cfg_field_set_sub, UVM_DEFAULT)
    `uvm_component_utils_end

    task run;
      if(cfg_field_set_clone.object[0] == cfg_container.object[0]) begin
        uvm_report_info("FAILED", "*** UVM TEST FAILED cfg_field_set_clone is set to ref ***", UVM_NONE);
      end
      if((cfg_field_set_clone.value != 0) || (cfg_field_set_clone.object[0].color != BLUE) ||
         (cfg_field_set_clone.object[0].i != 55) || (cfg_field_set_clone.object[0].str != "from cfg")) begin
cfg_field_set_clone.print();
        uvm_report_info("FAILED", "*** UVM TEST FAILED cfg_field_set_clone is not set correctly ***", UVM_NONE);
      end

      if(cfg_field_set_ref.object[0] != cfg_container.object[0])
        uvm_report_info("FAILED", "*** UVM TEST FAILED cfg_field_set_ref is not set to ref ***", UVM_NONE);
      if(cfg_field_notset != null)
        uvm_report_info("FAILED", "*** UVM TEST FAILED cfg_field_notset is set ***", UVM_NONE);

      if((cfg_field_set_sub.value != 0) || (cfg_field_set_sub.object[0] == cfg_container.object[0]) ||
         (cfg_field_set_sub.object[0].color != BLUE) || (cfg_field_set_sub.object[0].i != 55) ||
         (cfg_field_set_sub.object[0].str != "from cfg"))
        uvm_report_info("FAILED", "*** UVM TEST FAILED cfg_field_set_sub is not set correctly ***", UVM_NONE);

      recording_detail=UVM_LOW;

      uvm_report_info("PASSED", "*** UVM TEST PASSED ***", UVM_NONE);

    endtask
  endclass

  initial begin
    cfg_container.value = 22;
    cfg_container.object[0] = new;
    cfg_container.object[0].color = BLUE;
    cfg_container.object[0].i = 55;
    cfg_container.object[0].str = "from cfg";
    set_config_object("*", "cfg_field_set_clone.object[0]", cfg_container.object[0]);
    set_config_object("*", "cfg_field_set_ref.object[0]", cfg_container.object[0], 0);
    set_config_object("*", "cfg_field_set_sub.object[0]", cfg_container.object[0]);
    run_test();
  end

endmodule


//----------------------------------------------------------------------
//   Copyright 2010 Mentor Graphics Corporation
//   Copyright 2010-2011 Synopsys, Inc
//   All Rights Reserved Worldwide
//
//   Licensed under the Apache License, Version 2.0 (the
//   "License"); you may not use this file except in
//   compliance with the License.  You may obtain a copy of
//   the License at
//
//       http://www.apache.org/licenses/LICENSE-2.0
//
//   Unless required by applicable law or agreed to in
//   writing, software distributed under the License is
//   distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
//   CONDITIONS OF ANY KIND, either express or implied.  See
//   the License for the specific language governing
//   permissions and limitations under the License.
//----------------------------------------------------------------------

class target extends uvm_component;

   local bit [31:0] m_data;

   uvm_tlm_b_target_socket #(target, apb_rw) sock;

   `uvm_component_utils(target)

   function new(string name = "target", uvm_component parent = null);
      super.new(name, parent);
      sock = new("sock", this);

      m_data = 32'hDEADBEEF;
   endfunction

   task b_transport(apb_rw rw, uvm_tlm_time delay);

      case (rw.addr)

       32'h0000_FF00: begin
          if (rw.kind == apb_rw::READ) rw.data = m_data;

       end

      endcase

      #5;
   endtask

   function void start_of_simulation_phase(uvm_phase phase);
      `uvm_info("TRGT/RPT/START", $sformatf("m_data: 'h%h", m_data), UVM_NONE)
   endfunction

   function void report_phase(uvm_phase phase);
      `uvm_info("TRGT/RPT/FINAL", $sformatf("m_data: 'h%h", m_data), UVM_NONE)
   endfunction

endclass


//----------------------------------------------------------------------
//   Copyright 2010 Synopsys, Inc.
//   All Rights Reserved Worldwide
//
//   Licensed under the Apache License, Version 2.0 (the
//   "License"); you may not use this file except in
//   compliance with the License.  You may obtain a copy of
//   the License at
//
//       http://www.apache.org/licenses/LICENSE-2.0
//
//   Unless required by applicable law or agreed to in
//   writing, software distributed under the License is
//   distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
//   CONDITIONS OF ANY KIND, either express or implied.  See
//   the License for the specific language governing
//   permissions and limitations under the License.
//----------------------------------------------------------------------

program top;

import uvm_pkg::*;

initial
begin


`include "config.svh"
`include "lab_specific_board_config.svh"

module board_specific_top
# (
    parameter clk_mhz       = 50,
              pixel_mhz     = 25,

              w_key         = 4,
              w_sw          = 4,
              w_led         = 4,
              w_digit       = 0,
              w_gpio        = 0,


    (
        .clk        ( clk      ),
        .rst        ( rst      ),
        .hgfedcba   ( hgfedcba ),
        .digit      ( digit    ),
        .ledr       ( tm_led   ),
        .keys       ( tm_key   ),
        .sio_clk    ( gpio [2] ),  // Pin 7 from left top
        .sio_stb    ( gpio [3] ),  // Pin 6 from left top
        .sio_data   ( gpio [4] )   // Pin 8 from left top
    );

    assign gpio [1] = 1'b0;  // GND       Pin 4 from left top
    assign gpio [0] = 1'b1;  // VCC 3.3V  Pin 5 from left top

endmodule

    tm1638_board_controller
    # (
        .clk_mhz ( clk_mhz    ),


        module ExampOutput
           (/*AUTOOUTPUT*/
           // Beginning of automatic outputs (from unused autoinst outputs)
           output          o                       // From instName of InstModule.v
           // End of automatics
            );
           InstModule instName
             (/*AUTOINST*/
              // Outputs
              .o                        (o));
        endmodule

// Local Variables:
// indent-tabs-mode: nil
// End:

        module InstModule (output o);
        endmodule


module test(/*AUTOARG*/
   // Outputs
   a1, b1, c1, one
   );

   output [5:0] a1;
   output [5:0] b1;
   output [5:0] c1;

   /*AUTOREG*/

   //wire [5:0]   a2,b2,c2;

   assign {a1,b1,c1} = {a2,b2,c2};


// file: clk_ref.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
//  Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
//   Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
//----------------------------------------------------------------------------
// clk_out1____50.000______0.000______50.0______129.198_____89.971
//
//----------------------------------------------------------------------------
// Input Clock   Freq (MHz)    Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_____________200____________0.010

`timescale 1ps/1ps

module clk_ref_clk_wiz

 (// Clock in ports
  // Clock out ports
  output        clk_out1,
  // Status and control signals
  input         resetn,
  output        locked,
  input         clk_in1_p,
  input         clk_in1_n
 );
  // Input buffering
  //------------------------------------
wire clk_in1_clk_ref;
wire clk_in2_clk_ref;
  IBUFDS clkin1_ibufgds
   (.O  (clk_in1_clk_ref),
    .I  (clk_in1_p),
    .IB (clk_in1_n));

  // Clocking PRIMITIVE
  //------------------------------------

  // Instantiation of the MMCM PRIMITIVE
  //    * Unused inputs are tied off
  //    * Unused outputs are labeled unused

  wire        clk_out1_clk_ref;
  wire        clk_out2_clk_ref;
  wire        clk_out3_clk_ref;
  wire        clk_out4_clk_ref;
  wire        clk_out5_clk_ref;
  wire        clk_out6_clk_ref;
  wire        clk_out7_clk_ref;

  wire [15:0] do_unused;
  wire        drdy_unused;
  wire        psdone_unused;
  wire        locked_int;
  wire        clkfbout_clk_ref;
  wire        clkfbout_buf_clk_ref;
  wire        clkfboutb_unused;
    wire clkout0b_unused;
   wire clkout1_unused;
   wire clkout1b_unused;
   wire clkout2_unused;
   wire clkout2b_unused;
   wire clkout3_unused;
   wire clkout3b_unused;
   wire clkout4_unused;
  wire        clkout5_unused;
  wire        clkout6_unused;
  wire        clkfbstopped_unused;
  wire        clkinstopped_unused;
  wire        reset_high;

  MMCME2_ADV
  #(.BANDWIDTH            ("OPTIMIZED"),
    .CLKOUT4_CASCADE      ("FALSE"),
    .COMPENSATION         ("ZHOLD"),
    .STARTUP_WAIT         ("FALSE"),
    .DIVCLK_DIVIDE        (1),
    .CLKFBOUT_MULT_F      (5.000),
    .CLKFBOUT_PHASE       (0.000),
    .CLKFBOUT_USE_FINE_PS ("FALSE"),
    .CLKOUT0_DIVIDE_F     (20.000),
    .CLKOUT0_PHASE        (0.000),
    .CLKOUT0_DUTY_CYCLE   (0.500),
    .CLKOUT0_USE_FINE_PS  ("FALSE"),
    .CLKIN1_PERIOD        (5.000))
  mmcm_adv_inst
    // Output clocks
   (
    .CLKFBOUT            (clkfbout_clk_ref),
    .CLKFBOUTB           (clkfboutb_unused),
    .CLKOUT0             (clk_out1_clk_ref),
    .CLKOUT0B            (clkout0b_unused),
    .CLKOUT1             (clkout1_unused),
    .CLKOUT1B            (clkout1b_unused),
    .CLKOUT2             (clkout2_unused),
    .CLKOUT2B            (clkout2b_unused),
    .CLKOUT3             (clkout3_unused),
    .CLKOUT3B            (clkout3b_unused),
    .CLKOUT4             (clkout4_unused),
    .CLKOUT5             (clkout5_unused),
    .CLKOUT6             (clkout6_unused),
     // Input clock control
    .CLKFBIN             (clkfbout_buf_clk_ref),
    .CLKIN1              (clk_in1_clk_ref),

     // Tied to always select the primary input clock
    .CLKINSEL            (1'b1),
    // Ports for dynamic reconfiguration
    .DADDR               (7'h0),
    .DCLK                (1'b0),
    .DEN                 (1'b0),
    .DI                  (16'h0),
    .DO                  (do_unused),
    .DRDY                (drdy_unused),
    .DWE                 (1'b0),
    // Ports for dynamic phase shift
    .PSCLK               (1'b0),
    .PSEN                (1'b0),
    .PSINCDEC            (1'b0),
    .PSDONE              (psdone_unused),
    // Other control and status signals
    .LOCKED              (locked_int),
    .CLKINSTOPPED        (clkinstopped_unused),
    .CLKFBSTOPPED        (clkfbstopped_unused),
    .PWRDWN              (1'b0),
    .RST                 (reset_high));
  assign reset_high = ~resetn;

  assign locked = locked_int;
// Clock Monitor clock assigning
//--------------------------------------
 // Output buffering
  //-----------------------------------

  BUFG clkf_buf
   (.O (clkfbout_buf_clk_ref),
    .I (clkfbout_clk_ref));

  BUFG clkout1_buf
   (.O   (clk_out1),
    .I   (clk_out1_clk_ref));

endmodule


// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors.  Please refer to the applicable
// agreement for further details.

////////////////////////////////////////////////////////////////////
//
//   ALTERA_INT_OSC
//
//  Copyright (C) 1991-2013 Altera Corporation
//  Your use of Altera Corporation's design tools, logic functions
//  and other software and tools, and its AMPP partner logic
//  functions, and any output files from any of the foregoing
//  (including device programming or simulation files), and any
//  associated documentation or information are expressly subject
//  to the terms and conditions of the Altera Program License
//  Subscription Agreement, Altera MegaCore Function License
//  Agreement, or other applicable license agreement, including,
//  without limitation, that your use is for the sole purpose of
//  programming logic devices manufactured by Altera and sold by
//  Altera or its authorized distributors.  Please refer to the
//  applicable agreement for further details.
//
////////////////////////////////////////////////////////////////////

// synthesis VERILOG_INPUT_VERSION VERILOG_2001

`timescale 1 ps / 1 ps

module  altera_int_osc
	(
	clkout,
	oscena);

	parameter DEVICE_FAMILY   = "MAX 10";
	parameter DEVICE_ID       = "08";
	parameter CLOCK_FREQUENCY = "dummy";

	output   clkout;
	input   oscena;

	wire  wire_clkout;

			fiftyfivenm_oscillator # (	//MAX 10
				.device_id(DEVICE_ID),
				.clock_frequency(CLOCK_FREQUENCY)
			) oscillator_dut (
				.clkout(wire_clkout),
				.clkout1(),
				.oscena(oscena));
			end
	endgenerate

endmodule //altera_int_osc
//VALID FILE

	assign clkout = wire_clkout;

	// -------------------------------------------------------------------
	// Instantiate wysiwyg for chipidblock according to device family


// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Constants for use in primitives

// This file is auto-generated.

package caliptra_prim_pkg;

  // Implementation target specialization

    ImplGeneric,
    ImplXilinx,
    ImplBadbit
  } impl_e;
endpackage : caliptra_prim_pkg


// Copyright lowRISC contributors (OpenTitan project).
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0

`include "caliptra_prim_assert.sv"

/**
 * Tile-Link UL command integrity check
 */

module caliptra_tlul_cmd_intg_chk import caliptra_tlul_pkg::*; (
  // TL-UL interface
  input  tl_h2d_t tl_i,

  // error output
  output logic err_o
);

  logic [1:0] err;
  logic data_err;
  tl_h2d_cmd_intg_t cmd;
  assign cmd = extract_h2d_cmd_intg(tl_i);

  caliptra_prim_secded_inv_64_57_dec u_chk (
    .data_i({tl_i.a_user.cmd_intg, H2DCmdMaxWidth'(cmd)}),
    .data_o(),
    .syndrome_o(),
    .err_o(err)
  );

  caliptra_tlul_data_integ_dec u_caliptra_tlul_data_integ_dec (
    .data_intg_i({tl_i.a_user.data_intg, DataMaxWidth'(tl_i.a_data)}),
    .data_err_o(data_err)
  );

  // error output is transactional, it is up to the instantiating module
  // to determine if a permanent latch is feasible
  // [LOWRISC] err and data_err is unknown when a_valid is low, so we can't cover
  // the condition coverage - (|err | (|data_err)) == 0/1, when a_valid = 0, which is
  // fine as driving unknown is better. `err_o` is used as a condition in other places,
  // which needs to be covered with 0 and 1, so it's OK to disable the entire coverage.

  `CALIPTRA_ASSERT_INIT(PayLoadWidthCheck, $bits(tl_h2d_cmd_intg_t) <= H2DCmdMaxWidth)

endmodule // caliptra_tlul_payload_chk

  //VCS coverage off
  // pragma coverage off
  assign err_o = tl_i.a_valid & (|err | (|data_err));
  //VCS coverage on
  // pragma coverage on


// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0

`ifdef TEST_VERBOSE
 `define WRITE_VERBOSE(args) $write args
`else
 `define WRITE_VERBOSE(args)
`endif

module t(/*AUTOARG*/
   // Inputs
   clk
   );
   input clk;

   event e1;
   event e2;
   event e3;
`ifndef IVERILOG
   event ev [3:0];
`endif

   int   cyc = 0;

   int last_event = 0;
   always @(e1) begin
      `WRITE_VERBOSE(("[%0t] e1\n", $time));
      if (!e1.triggered) $stop;
      last_event[1] = 1;
   end

   always @(e2) begin
      `WRITE_VERBOSE(("[%0t] e2\n", $time));
      if (!e2.triggered) $stop;
      last_event[2] = 1;
   end

   always @(posedge clk) begin
      `WRITE_VERBOSE(("[%0t] cyc=%0d last_event=%5b\n", $time, cyc, last_event));
      cyc <= cyc + 1;
      case (cyc)
         default: begin
            // Check no initial or spurious trigger
<TARGET>
         end
         //
         10: begin

            -> e1;
            if (!e1.triggered) $stop;
            if (e3.triggered) $stop;
            -> e3;
            if (!e3.triggered) $stop;
         end
         11: begin
            if (last_event != 32'b10) $stop;
            last_event = 0;
            if (e3.triggered) $stop;
         end
         //
         13: begin
            if (last_event != 0) $stop;
            ->> e2;
            if (e2.triggered) $stop;
            if (e3.triggered) $stop;
         end
         14: begin
            if (last_event != 32'b100) $stop;
            last_event = 0;
         end
         //
         99: begin
            $write("*-* All Finished *-*\n");
            $finish;
         end
      endcase
   end

endmodule


// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0

// Based on tests emitted by t_gate_tree.py

module t (clk);
  input clk;

  logic reset;

   reg [255:0] v2_0;
   reg [255:0] v1_0;
   reg [255:0] v1_1;
   reg [255:0] v1_2;
   reg [255:0] v1_3;
   reg [255:0] v1_4;
   reg [255:0] v1_5;
   reg [255:0] v1_6;
   reg [255:0] v1_7;
   // verilator lint_off MULTIDRIVEN
   reg [255:0] dummy;
   // verilator lint_on MULTIDRIVEN

   Calculate calc0(.clk(clk), .reset(reset), .v1_0(v1_0), .v1_1(dummy), .v1_2(dummy), .v1_3(dummy), .v1_4(dummy), .v1_5(dummy), .v1_6(dummy), .v1_7(dummy));
   Calculate calc1(.clk(clk), .reset(reset), .v1_0(dummy), .v1_1(v1_1), .v1_2(dummy), .v1_3(dummy), .v1_4(dummy), .v1_5(dummy), .v1_6(dummy), .v1_7(dummy));
   Calculate calc2(.clk(clk), .reset(reset), .v1_0(dummy), .v1_1(dummy), .v1_2(v1_2), .v1_3(dummy), .v1_4(dummy), .v1_5(dummy), .v1_6(dummy), .v1_7(dummy));
   Calculate calc3(.clk(clk), .reset(reset), .v1_0(dummy), .v1_1(dummy), .v1_2(dummy), .v1_3(v1_3), .v1_4(dummy), .v1_5(dummy), .v1_6(dummy), .v1_7(dummy));
   Calculate calc4(.clk(clk), .reset(reset), .v1_0(dummy), .v1_1(dummy), .v1_2(dummy), .v1_3(dummy), .v1_4(v1_4), .v1_5(dummy), .v1_6(dummy), .v1_7(dummy));
   Calculate calc5(.clk(clk), .reset(reset), .v1_0(dummy), .v1_1(dummy), .v1_2(dummy), .v1_3(dummy), .v1_4(dummy), .v1_5(v1_5), .v1_6(dummy), .v1_7(dummy));
   Calculate calc6(.clk(clk), .reset(reset), .v1_0(dummy), .v1_1(dummy), .v1_2(dummy), .v1_3(dummy), .v1_4(dummy), .v1_5(dummy), .v1_6(v1_6), .v1_7(dummy));
   Calculate calc7(.clk(clk), .reset(reset), .v1_0(dummy), .v1_1(dummy), .v1_2(dummy), .v1_3(dummy), .v1_4(dummy), .v1_5(dummy), .v1_6(dummy), .v1_7(v1_7));
   always @ (posedge clk) v2_0 <= v1_0 + v1_1 + v1_2 + v1_3 + v1_4 + v1_5 + v1_6 + v1_7;
   Check chk(.clk(clk), .reset(reset), .v2_0(v2_0));
endmodule

module Check(input clk, output logic reset, input reg [255:0] v2_0);
  integer cyc=0;
   always @ (posedge clk) begin
      cyc <= cyc + 1;
`ifdef TEST_VERBOSE
         $write("[%0t] rst=%0x  v0_0=%0x  v1_0=%0x  result=%0x\n", $time, reset, v0_0, v1_0, v2_0);
`endif
      if (cyc==0) begin
         reset <= 1;
      end
      else if (cyc==10) begin
         reset <= 0;
      end
`ifndef SIM_CYCLES
 `define SIM_CYCLES 99
`endif
      else if (cyc==`SIM_CYCLES) begin
         if (v2_0 != 256'd2017) $stop;
         $write("VARS=64 WIDTH=256 WORKINGSET=2KB\n");
         $write("*-* All Finished *-*\n");
         $finish;
      end
   end

endmodule

module Calculate(input clk,
   input reset,
   output reg [255:0] v1_0,
   output reg [255:0] v1_1,
   output reg [255:0] v1_2,
   output reg [255:0] v1_3,
   output reg [255:0] v1_4,
   output reg [255:0] v1_5,
   output reg [255:0] v1_6,
   output reg [255:0] v1_7
   );
   reg [255:0] v0_0;
   reg [255:0] v0_1;
   reg [255:0] v0_2;
   reg [255:0] v0_3;
   reg [255:0] v0_4;
   reg [255:0] v0_5;
   reg [255:0] v0_6;
   reg [255:0] v0_7;
   reg [255:0] v0_8;
   reg [255:0] v0_9;
   reg [255:0] v0_10;
   reg [255:0] v0_11;
   reg [255:0] v0_12;
   reg [255:0] v0_13;
   reg [255:0] v0_14;
   reg [255:0] v0_15;
   reg [255:0] v0_16;
   reg [255:0] v0_17;
   reg [255:0] v0_18;
   reg [255:0] v0_19;
   reg [255:0] v0_20;
   reg [255:0] v0_21;
   reg [255:0] v0_22;
   reg [255:0] v0_23;
   reg [255:0] v0_24;
   reg [255:0] v0_25;
   reg [255:0] v0_26;
   reg [255:0] v0_27;
   reg [255:0] v0_28;
   reg [255:0] v0_29;
   reg [255:0] v0_30;
   reg [255:0] v0_31;
   reg [255:0] v0_32;
   reg [255:0] v0_33;
   reg [255:0] v0_34;
   reg [255:0] v0_35;
   reg [255:0] v0_36;
   reg [255:0] v0_37;
   reg [255:0] v0_38;
   reg [255:0] v0_39;
   reg [255:0] v0_40;
   reg [255:0] v0_41;
   reg [255:0] v0_42;
   reg [255:0] v0_43;
   reg [255:0] v0_44;
   reg [255:0] v0_45;
   reg [255:0] v0_46;
   reg [255:0] v0_47;
   reg [255:0] v0_48;
   reg [255:0] v0_49;
   reg [255:0] v0_50;
   reg [255:0] v0_51;
   reg [255:0] v0_52;
   reg [255:0] v0_53;
   reg [255:0] v0_54;
   reg [255:0] v0_55;
   reg [255:0] v0_56;
   reg [255:0] v0_57;
   reg [255:0] v0_58;
   reg [255:0] v0_59;
   reg [255:0] v0_60;
   reg [255:0] v0_61;
   reg [255:0] v0_62;
   reg [255:0] v0_63;

   always @ (posedge clk) v0_0 <= reset ? 256'd1 : v0_1;
   always @ (posedge clk) v0_1 <= reset ? 256'd1 : v0_2;
   always @ (posedge clk) v0_2 <= reset ? 256'd2 : v0_3;
   always @ (posedge clk) v0_3 <= reset ? 256'd3 : v0_4;
   always @ (posedge clk) v0_4 <= reset ? 256'd4 : v0_5;
   always @ (posedge clk) v0_5 <= reset ? 256'd5 : v0_6;
   always @ (posedge clk) v0_6 <= reset ? 256'd6 : v0_7;
   always @ (posedge clk) v0_7 <= reset ? 256'd7 : v0_0;
   always @ (posedge clk) v0_8 <= reset ? 256'd8 : v0_9;
   always @ (posedge clk) v0_9 <= reset ? 256'd9 : v0_10;
   always @ (posedge clk) v0_10 <= reset ? 256'd10 : v0_11;
   always @ (posedge clk) v0_11 <= reset ? 256'd11 : v0_12;
   always @ (posedge clk) v0_12 <= reset ? 256'd12 : v0_13;
   always @ (posedge clk) v0_13 <= reset ? 256'd13 : v0_14;
   always @ (posedge clk) v0_14 <= reset ? 256'd14 : v0_15;
   always @ (posedge clk) v0_15 <= reset ? 256'd15 : v0_8;
   always @ (posedge clk) v0_16 <= reset ? 256'd16 : v0_17;
   always @ (posedge clk) v0_17 <= reset ? 256'd17 : v0_18;
   always @ (posedge clk) v0_18 <= reset ? 256'd18 : v0_19;
   always @ (posedge clk) v0_19 <= reset ? 256'd19 : v0_20;
   always @ (posedge clk) v0_20 <= reset ? 256'd20 : v0_21;
   always @ (posedge clk) v0_21 <= reset ? 256'd21 : v0_22;
   always @ (posedge clk) v0_22 <= reset ? 256'd22 : v0_23;
   always @ (posedge clk) v0_23 <= reset ? 256'd23 : v0_16;
   always @ (posedge clk) v0_24 <= reset ? 256'd24 : v0_25;
   always @ (posedge clk) v0_25 <= reset ? 256'd25 : v0_26;
   always @ (posedge clk) v0_26 <= reset ? 256'd26 : v0_27;
   always @ (posedge clk) v0_27 <= reset ? 256'd27 : v0_28;
   always @ (posedge clk) v0_28 <= reset ? 256'd28 : v0_29;
   always @ (posedge clk) v0_29 <= reset ? 256'd29 : v0_30;
   always @ (posedge clk) v0_30 <= reset ? 256'd30 : v0_31;
   always @ (posedge clk) v0_31 <= reset ? 256'd31 : v0_24;
   always @ (posedge clk) v0_32 <= reset ? 256'd32 : v0_33;
   always @ (posedge clk) v0_33 <= reset ? 256'd33 : v0_34;
   always @ (posedge clk) v0_34 <= reset ? 256'd34 : v0_35;
   always @ (posedge clk) v0_35 <= reset ? 256'd35 : v0_36;
   always @ (posedge clk) v0_36 <= reset ? 256'd36 : v0_37;
   always @ (posedge clk) v0_37 <= reset ? 256'd37 : v0_38;
   always @ (posedge clk) v0_38 <= reset ? 256'd38 : v0_39;
   always @ (posedge clk) v0_39 <= reset ? 256'd39 : v0_32;
   always @ (posedge clk) v0_40 <= reset ? 256'd40 : v0_41;
   always @ (posedge clk) v0_41 <= reset ? 256'd41 : v0_42;
   always @ (posedge clk) v0_42 <= reset ? 256'd42 : v0_43;
   always @ (posedge clk) v0_43 <= reset ? 256'd43 : v0_44;
   always @ (posedge clk) v0_44 <= reset ? 256'd44 : v0_45;
   always @ (posedge clk) v0_45 <= reset ? 256'd45 : v0_46;
   always @ (posedge clk) v0_46 <= reset ? 256'd46 : v0_47;
   always @ (posedge clk) v0_47 <= reset ? 256'd47 : v0_40;
   always @ (posedge clk) v0_48 <= reset ? 256'd48 : v0_49;
   always @ (posedge clk) v0_49 <= reset ? 256'd49 : v0_50;
   always @ (posedge clk) v0_50 <= reset ? 256'd50 : v0_51;
   always @ (posedge clk) v0_51 <= reset ? 256'd51 : v0_52;
   always @ (posedge clk) v0_52 <= reset ? 256'd52 : v0_53;
   always @ (posedge clk) v0_53 <= reset ? 256'd53 : v0_54;
   always @ (posedge clk) v0_54 <= reset ? 256'd54 : v0_55;
   always @ (posedge clk) v0_55 <= reset ? 256'd55 : v0_48;
   always @ (posedge clk) v0_56 <= reset ? 256'd56 : v0_57;
   always @ (posedge clk) v0_57 <= reset ? 256'd57 : v0_58;
   always @ (posedge clk) v0_58 <= reset ? 256'd58 : v0_59;
   always @ (posedge clk) v0_59 <= reset ? 256'd59 : v0_60;
   always @ (posedge clk) v0_60 <= reset ? 256'd60 : v0_61;
   always @ (posedge clk) v0_61 <= reset ? 256'd61 : v0_62;
   always @ (posedge clk) v0_62 <= reset ? 256'd62 : v0_63;
   always @ (posedge clk) v0_63 <= reset ? 256'd63 : v0_56;

   always @ (posedge clk) v1_0 <= v0_0 + v0_1 + v0_2 + v0_3 + v0_4 + v0_5 + v0_6 + v0_7;
   always @ (posedge clk) v1_1 <= v0_8 + v0_9 + v0_10 + v0_11 + v0_12 + v0_13 + v0_14 + v0_15;
   always @ (posedge clk) v1_2 <= v0_16 + v0_17 + v0_18 + v0_19 + v0_20 + v0_21 + v0_22 + v0_23;
   always @ (posedge clk) v1_3 <= v0_24 + v0_25 + v0_26 + v0_27 + v0_28 + v0_29 + v0_30 + v0_31;
   always @ (posedge clk) v1_4 <= v0_32 + v0_33 + v0_34 + v0_35 + v0_36 + v0_37 + v0_38 + v0_39;
   always @ (posedge clk) v1_5 <= v0_40 + v0_41 + v0_42 + v0_43 + v0_44 + v0_45 + v0_46 + v0_47;
   always @ (posedge clk) v1_6 <= v0_48 + v0_49 + v0_50 + v0_51 + v0_52 + v0_53 + v0_54 + v0_55;