m_axi_gmem_ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ADDR_WIDTH-1 downto 0);


    s_axi_control_WREADY : OUT STD_LOGIC;
    s_axi_control_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_CONTROL_DATA_WIDTH-1 downto 0);
    s_axi_control_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_CONTROL_DATA_WIDTH/8-1 downto 0);
    s_axi_control_ARVALID : IN STD_LOGIC;
    s_axi_control_ARREADY : OUT STD_LOGIC;


architecture xilinx of blk_mem_gen_v8_4_4 is
  begin
  end
architecture xilinx;


    GENERIC (
      C_FAMILY : STRING;
      C_XDEVICEFAMILY : STRING;


      C_HAS_WE => 1,
      C_MEM_INIT_FILE => "no_coe_file_loaded",


    overflow : OUT STD_LOGIC;
    empty : OUT STD_LOGIC;
    wr_rst_busy : OUT STD_LOGIC;
    rd_rst_busy : OUT STD_LOGIC
  );


    rd_en : IN STD_LOGIC;
    dout : OUT STD_LOGIC_VECTOR(291 DOWNTO 0);
    full : OUT STD_LOGIC;
    overflow : OUT STD_LOGIC;
    empty : OUT STD_LOGIC;


            a_int <= "0000";
        elsif rising_edge(CLK) then
            ndev_sel_int <= NDEV_SEL;
            nio_sel_int <= NIO_SEL;
            nio_stb_int <= NIO_STB;


    NWE : out std_logic;
    PHI0 : in std_logic;
    NRESET : in std_logic;
    RNW : in std_logic;


   CLK_process :process
   begin
		CLK <= '0';


                data_out(0) <= slavesel;
                data_out(3 downto 1) <= (others => '0');
                data_out(4) <= sdhc;


      -- Delay SCL and SDA by 1 clock cycle
      scl_prev_reg   <= scl_internal;
      sda_prev_reg   <= sda_internal;


  begin
    if rising_edge(clk) then
      if data_valid = '1' then
        data_from_master_reg <= data_from_master;
      end if;


    if ENDSIM = false then
      uniform(seed1, seed2, rand_sda);  -- generate random number
      sda_spike_should_happen := rand_sda;
      uniform(seed1, seed2, rand_sda);  -- generate random number


    clk        : in  std_logic);
end entity debounce;


						end if;

						state_one <= '1';
					   	state_two <= '1';
					   	state_three <= '1';


            if (RST = '1') then
                uart_ticks <= 0;
                uart_clk_en <= '0';
            elsif (uart_ticks = divider_value-1) then
                uart_ticks <= 0;


        uart_rx_parity_check_reg : process (CLK)
        begin
            if (rising_edge(CLK)) then
                if (RST = '1') then
                    rx_parity_error <= '0';


                tx_pstate <= idle;
            else


	PORT
	(
		address		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
		clock		: IN STD_LOGIC  := '1';
		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)


	vga_clk : out std_logic;
	vga_g : out std_logic_vector(9 downto 0);
	vga_blank : out std_logic;


entity ntsc_sync_generator is Port (
	clk_50 : in std_logic;
	reset : in std_logic;


entity palette is Port (
    index : in std_logic_vector(3 downto 0);
    luma : out std_logic_vector(10 downto 0);


		address		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
		clock		: IN STD_LOGIC  := '1';
		q		: OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
	);
END sine_rom;


			hs_out		: out std_logic;
			de_out		: out std_logic);


		if (to_integer(unsigned(random)) < g_st) then
			g_sp <= '1';


		else
			tmp_sum_1 <= 0;
		end if;

		if sp_2 = '1' then


                    v_th            => v_th)
        port map(   clk             => clk,


            -- If current pixel is in the horizontal range of text
            if horzCoord >= position.x and horzCoord < position.x + (FONT_WIDTH * textlength) then


                inYRange := true;
            end if;

            -- need to check if the pixel is on for text
            if inXRange and inYRange then


constant init_type_outArbiterPort: type_outArbiterPort := (dataWaiting => false, data => (others => '0'), dataWritten => false);


    yCoord: in std_logic_vector(11 downto 0);
    pixOn: out std_logic
   );


                            elsif spi_tx_byte_idx = 9 then
                                spi_tx_byte := axi_rdata(7 downto 0);
                            else
                                -- Read status byte:


    generic(
        SPI_CPOL : natural range 0 to 1 := 0; -- SPI clock polarity


        variable status  : std_logic_vector(7 downto 0);

        alias s_axi_awvalid_mask is << signal .tb_spi2axi.s_axi_awvalid_mask : std_logic >>;
        alias s_axi_arvalid_mask is << signal .tb_spi2axi.s_axi_arvalid_mask : std_logic >>;


            end loop;
            assert tx_byte_idx = tx_bytes'length severity failure;
            --


    );
    port(
        -- Record Interfaces


        clock       : in std_logic;
        reset       : in std_logic;
        write_data  : in std_logic_vector(FIFO_WIDTH-1 downto 0);
        read_data   : out std_logic_vector(FIFO_WIDTH-1 downto 0);


                    fifo_data_in        <= uart_data_out;
                end if;
                -- Clear transmission request strobe upon acknowledge.


                readline(input_file, data_line);
                read(data_line, data, read_ok);
                local_data          <= to_stdlogicvector(data);


                    elsif uart_rx_data_sr(1) = '0' and uart_rx_filter > 0 then
                        uart_rx_filter <= uart_rx_filter - 1;
                    end if;
                    -- set the rx bit.
                    if uart_rx_filter = 3 then


    mod_in : in signed (4 downto 0);
    mod_in_vld : in std_logic;

    pwm_p : out std_logic := '0';
    pwm_n : out std_logic := '0'


process (i2s_l_in, gain)
begin
	l_in <= shift_left(resize(i2s_l_in,32), to_integer(gain));
end process;


	elsif (bclk_edge = b"01") then
		framesync <= '0';
	end if;


process (mul_inp_1, mul_inp_2)
begin
	--multiply and do right-shift by 15 (fixed-point mult with 32-bit int and q1.15 value)
    mul_result <= resize(shift_right(mul_inp_1*mul_inp_2,15),32);
end process;


    i2s_bclk : out std_logic;
    i2s_lr   : out std_logic;
    i2s_din  : in std_logic;


    begin
        if (ap_clk'event and ap_clk =  '1') then


          clk       : in std_logic
    );
end entity;


            mem_size    : integer := 64
    );
    port (


        else
            ap_ready <= ap_const_logic_0;


		i, a:        in std_ulogic;
		o:          out std_ulogic;
   		oe, ie, ae:  in std_ulogic);


		while (count < cfg.clocks or cfg.forever)  and halt = '0' loop
			clk <= '1';
			wait for clock_period / 2;


		debug:           natural         := 0; -- will not synthesize if greater than zero (debug off = 0)
		uart_use_cfg:    boolean         := false;
		uart_fifo_depth: natural         := 0


		if rst = '1' and g.asynchronous_reset then
			reset;
		elsif rising_edge(clk) then
			if rst = '1' and not g.asynchronous_reset then


	begin
		if rising_edge(clk) then
			if dwe = '1' then
				ram(to_integer(unsigned(addr))) := din;
			end if;


        when c_sub =>
          v_result := std_logic_vector(unsigned('0' & DinA_i) -
                                       unsigned('0' & DinB_i));
        when c_and => v_result := ('0', DinA_i and DinB_i);
        when c_or  => v_result := ('0', DinA_i or  DinB_i);


    AFTER_RESET : process (all) is
    begin
      if (not Reset_n_i) then
        RESET_DATA : assert unsigned(Data_o) = to_unsigned(InitVal, Data_o'length);


        if (Wen_i = '0' and s_almost_empty) then
          Empty_o <= '1';
        end if;
        Full_o <= '0';
      end if;


    Din_i        : in  std_logic_vector(Width-1 downto 0);
    Full_o       : out std_logic;


  Accept_o <= not s_full;
  Valid_o  <= not s_empty;


      end if;
    end process AFTER_RESET;


       case v is
         when "00" => r:=chimp;
         when "01" => r:=gorilla;


         when "00" => r:=chimp;
         when "01" => r:=gorilla;
         when "10" => r:=phb;
         when others => r:=chimp; -- error


         when "01" => r:=gorilla;
         when "10" => r:=chimp;
         when others => r:=phb; -- error
       end case;


    variable expected_value : std_ulogic_vector(width-1 downto 0);
    variable test_passed : boolean;
    variable temp_addr : std_ulogic_vector(addressWidth-1 downto 0);


architecture rtl of vhd_dut is
  signal registers_i_i : example_in_record_type;


		rout <= ra after delay;
		raddr <= (others => '0') after delay;
		raddr(npc'range) <= npc after delay;


	process (clk) begin
		if rising_edge(clk) then
			print_debug_info;
		end if;
	end process;


en_non_io_tb:       boolean  := false;       -- Do not generate UART, talk directly to `system.vhd` which is faster


--		rst:         in std_ulogic;
		halted:     out std_ulogic;
		blocked:    out std_ulogic;
		-- synthesis translate_on


		addr: in  std_ulogic_vector(addr_length - 1 downto 0);
		din:  in  std_ulogic_vector(data_length - 1 downto 0);


    C_HAS_MUX_OUTPUT_REGS_B      : integer := 0;
    C_MUX_PIPELINE_STAGES        : integer := 0;
    C_HAS_SOFTECC_INPUT_REGS_A   : integer := 0;
    C_HAS_SOFTECC_OUTPUT_REGS_B  : integer := 0;


    dinb                         : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
    doutb                        : out std_logic_vector(c_read_width_b - 1 downto 0);
    injectsbiterr                : in std_logic := '0';
    injectdbiterr                : in std_logic := '0';
    eccpipece                    : in std_logic := '0';


doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)


ATTRIBUTE DowngradeIPIdentifiedWarnings OF mult_gen_0_arch: ARCHITECTURE IS "yes";


        vs_out    : out std_logic;                      -- corresponding to video-in
        hs_out    : out std_logic;
        de_out    : out std_logic;
        r_out     : out std_logic_vector(7 downto 0);
        g_out     : out std_logic_vector(7 downto 0);


address		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);


        reset    : in  std_logic;
        write_en : in  std_logic;
        data_in  : in  std_logic_vector(23 downto 0);
        data_out : out std_logic_vector(23 downto 0));
end lane_linemem;


        data_out : out std_logic_vector(23 downto 0));
end lane_sobel;


        vs_in  : in  std_logic;
        hs_in  : in  std_logic;
        de_in  : in  std_logic;
        vs_out : out std_logic;


            assert false
              report "MISMATCH in simulation at position x=" & integer'image(x_pos) & " y=" & integer'image(y_pos)
              severity note;
          end if;
        end if;


           data_valid_in   : in  STD_LOGIC                     := '0';
           data_enable_in  : in  STD_LOGIC;
           data_out        : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');


            data_enable_out <= '0';
            if data_enable_in = '1' then


when "1110" => max_count <= to_unsigned(      1_249,27);  -- 100,000 packets per second


           link_1000mb      : out STD_LOGIC;
           link_full_duplex : out STD_LOGIC;


                    doutclk(1) <= '0';
                else


clk_proc: process
    begin
        clk100MHz <= '0';
        wait for 5 ns;
        clk100MHz <= '1';


  );
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------


architecture stub of shift_RAM_3X3_8bit is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;


your_instance_name : shift_RAM_3X3_8bit
  PORT MAP (
    D => D,
    CLK => CLK,
    SCLR => SCLR,


  attribute C_DEFAULT_DATA of shift_RAM_3X3_8bit_c_shift_ram_v12_0_12 : entity is "00000000";
  attribute C_DEPTH : integer;


attribute x_core_info : string;
attribute x_core_info of stub : architecture is "c_shift_ram_v12_0_12,Vivado 2018.3";
begin


    CLK : IN STD_LOGIC;
    SCLR : IN STD_LOGIC;
    Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
  );


		wdog_led	: out std_logic;								-- WDOG - output for resetting the watchdog and driving the LED
 		rst_n		: in std_logic;								-- RESET - reset input, disables memory paging, watchdog
																		-- and sets divisor value to '1' (active low)
		rom_cs_n	: out std_logic;								-- ROM_CS - ROM chip select output (active low)


			q <= '0';										-- Reset if rst_n is active
		elsif rising_edge(clk) then
         q <= d;											-- Write data on the rising edge of clk
		end if;
	end process;


   begin
		if rising_edge(clk) then
			q <= d;
		end if;
	end process;


	end process;
end architecture behavioral;


		wraddress	: in std_logic_vector (1 downto 0); -- Input (write) address
		wren			: in std_logic;							-- Write enable
		rden			: in std_logic;							-- Read enable (register outputs "000000" when rden is inactive)
		q				: out std_logic_vector (5 downto 0)	-- Data (read) output
   );


   begin
		if rst_n = '0' then
			q <= "000000";									-- Reset if rst_n is active


entity uart_freq_divider is
   port
   (
		divisor	: in std_logic_vector(4 downto 0);	-- Divisor value
      clk_in	: in std_logic;							-- Clock input


        elsif rising_edge(clk) then
            count    <= count + 1;
            feedback <= '1';


    ARST_AVL_N : out STD_LOGIC_VECTOR ( 0 to 0 );
    CLK_AVL : out STD_LOGIC;


                            srst             <= avl_writedata(0);
                        when 1 =>


        elsif rising_edge(CLK_OUT) then
            toggle_sr <= toggle_sr(toggle_sr'high - 1 downto 0) & toggle;
        end if;
    end process;


entity sha256_digester is
    port (
        CLK       : in  std_logic;
        ARST_N    : in  std_logic;


            if (feedback = '0') then
                HASH(C_WORD_SIZE - 1 downto 0)               <= std_logic_vector(unsigned(STATE(C_WORD_SIZE - 1 downto 0))               + unsigned(state_out_slv(C_NUM_DIGESTERS - 1)(C_WORD_SIZE - 1 downto 0)));
                HASH(2*C_WORD_SIZE - 1 downto C_WORD_SIZE)   <= std_logic_vector(unsigned(STATE(2*C_WORD_SIZE - 1 downto C_WORD_SIZE))   + unsigned(state_out_slv(C_NUM_DIGESTERS - 1)(2*C_WORD_SIZE - 1 downto C_WORD_SIZE)));
                HASH(3*C_WORD_SIZE - 1 downto 2*C_WORD_SIZE) <= std_logic_vector(unsigned(STATE(3*C_WORD_SIZE - 1 downto 2*C_WORD_SIZE)) + unsigned(state_out_slv(C_NUM_DIGESTERS - 1)(3*C_WORD_SIZE - 1 downto 2*C_WORD_SIZE)));


if (startup_rounds_count < C_NUM_STARTUP_ROUNDS) then


          if Inc_S = '1' then
            S <= S + 1;
          end if;
          if Dec_S = '1' and (RstCycle = '0' or Mode = "00") then -- Decrement during reset - 6502 only?


          P_Out(Flag_Z) <= '0';
        end if;
      when ALU_OP_ANC=>
        P_Out(Flag_N) <= Q_t(7);


              when Cycle_1 =>
                Jump <= "01";
              when others =>
            end case;


      return Cycle_1;
    when Cycle_1=>
      return Cycle_2;
    when Cycle_2=>
      return Cycle_3;


				end if;
				if MDMA(2) and (vicCycle = cycleSpriteB) and (sprite = 0) then
					baSprite26 <= '0';


        r            : out unsigned(7 downto 0);
        g            : out unsigned(7 downto 0);
        b            : out unsigned(7 downto 0);


	-- count 6 qclk cycles = ~8 MHz, then transform into clk1m/2m/4m
	cpu_cnt1_p: process(reset, cpu_cnt1, memclk_int)
	begin


			when "1001" =>
				clk4m <= '1';
			when others =>
				null;
			end case;


				and petio ='1' else
			'0';

	ffsel <= '0' when avalid='0' else
			'1' when low64k ='1'


		elsif (rising_edge(qclk) and phi2='0') then
--			if (forceb0= '1') then
--				bankl <= (others => '0');
--			else
				bankl <= D;


				DOUT(4) <= cpha;
				DOUT(3) <= '0';
				DOUT(2 downto 0) <= sel(2 downto 0);


vid_p: process(chr40, chr80, pxl40, pxl80, qclk)


			vpagelo <= x"00";
		elsif (falling_edge(phi2)


ARCHITECTURE bd_48ac_psr_aclk_0_arch OF bd_48ac_psr_aclk_0 IS
  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;


      C_EXT_RESET_HIGH => '0',
      C_AUX_RESET_HIGH => '0',
      C_NUM_BUS_RST => 1,
      C_NUM_PERP_RST => 1,


        prmry_resetn                : in  std_logic                             ;               --
        prmry_in                    : in  std_logic                             ;               --


  anAdder: process (sel,op_a,op_b)
  begin
     if sel = '1' then
        outp <= op_a + op_b;
     else


  cell: nr_r4_half_cell port map( op_r => rem_in(i),
        op_y => reg_Y(i), op_3y => reg_3Y(i),


  sr <= op_r(YBITS);
  op_4r <= op_r(YBITS-1 downto 0) & x_1 & x_0;


 Q:  out std_logic_vector(7 downto 0);
 clk: in std_logic;
 reset: in std_logic;
 rx_done_tick : in std_logic );
end DFF;


process (clk,reset)
begin
if(reset= '0')then
r_reg <= (others => '0');
elsif(clk'event and clk='1')then


reset_av : out std_logic;
scl : inout std_logic;
sda : inout std_logic;


architecture Behavioral of bof is
begin
bi <= sig_out when dir = '1' else 'Z';
sig_in <= bi;
end Behavioral;


entity timer is
generic (N:integer :=3);
PORT(
clk,reset: in std_logic;
Q : out std_logic_vector(N-1 downto 0)


				rx_clk_en	<=	'1';
				counter		:=	0;
			else


		Clock	: in	STD_LOGIC;
		Reset	: in	STD_LOGIC;
		LED		: out	STD_LOGIC_VECTOR (7 downto 0)


      info("RAW generic: " & tb_cfg);
      if run("stringified JSON generic") then


entity tb_encodings is
  generic (runner_cfg : string);
end entity;


variable result: string (1 to str'length * 2);


  use JSON.json.jsonIsNumber;
end context;


								Result.Content(ContentWriter)					:= CurrentChar;
							when 'e' | 'E' =>
								ContentWriter													:= ContentWriter + 1;
								Result.Content(ContentWriter)					:= CurrentChar;


signal dbg_bit                     : std_logic_vector(8 downto 0);


       app_rd_data_valid              => app_rd_data_valid,
       app_rdy                        => app_rdy,
       app_wdf_rdy                    => app_wdf_rdy,
       app_sr_req                     => app_sr_req,


    uart_rxd_out : out std_logic;
    uart_txd_in : in std_logic;
    ja : inout std_logic_vector(7 downto 0);
    jb : inout std_logic_vector(7 downto 0);


	--		Response
	axi_bid           <= o.pcis.write.resp.bid     ;
	axi_bresp         <= o.pcis.write.resp.bresp   ;
	axi_bvalid        <= o.pcis.write.resp.bvalid  ;
	--		Ready


  -- and FE_TOWARDZERO floating point rounding macros.

  type round_type is (round_nearest,    -- Default, nearest LSB '0'


      when others =>
        assert not ISSUE_ERROR
          report fixed_pkg'instance_name
          & "OREAD Error: Read a '" & c &


            when round_neginf =>
              if arg_int /= 0 and result (exponent_width) = '1' then


if rising_edge(out_clk) then
    wr_ptr_gray_sync1_reg <= wr_ptr_gray_reg;
    wr_ptr_gray_sync2_reg <= wr_ptr_gray_sync1_reg;


  pipe_ready <= '1';
  valid_out <= valid_out_pipe;


    --invertor 2
    inv_lut2: LUT1
    generic map (init => X"1")
    port map (
            I0    => delay2,


entity Ring_osc_3 is
    port (    clk        : in     STD_LOGIC;
            D_out    : out     STD_LOGIC
        );
end Ring_osc_3;


    C_EN_SAFETY_CKT              : integer := 0;
    C_DISABLE_WARN_BHV_RANGE     : integer := 0;
    C_COUNT_36K_BRAM             : string  := "";


    clka => clka,
    ena => ena,
    addra => addra,
    douta => douta


    clka : IN STD_LOGIC;
    ena : IN STD_LOGIC;
    addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
    douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
  );


COMPONENT fifo_rx
  PORT (
    clk : IN STD_LOGIC;


    srst : IN STD_LOGIC;
    din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);


    clk => clk,
    srst => srst,
    din => din,
    wr_en => wr_en,


      D => \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.srst_d2\,
      Q => \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.srst_d3\,
      R => '0'
    );


attribute syn_black_box of stub : architecture is true;


                                        (C_VECTOR_WIDTH - 1 downto 0)           ;               --
        prmry_ack                   : out std_logic                             ;
                                                                                --


                 FIFO_Read     => FIFO_Read,
                 Data_Out      => Data_Out,
                 FIFO_Full     => FIFO_Full,
                 FIFO_Empty    => FIFO_Empty,
                 Addr          => Addr,


  ATTRIBUTE X_INTERFACE_INFO OF m_axi_mem_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MEM ARPROT";
  ATTRIBUTE X_INTERFACE_INFO OF m_axi_mem_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MEM ARREADY";
  ATTRIBUTE X_INTERFACE_INFO OF m_axi_mem_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MEM ARSIZE";
  ATTRIBUTE X_INTERFACE_INFO OF m_axi_mem_aruser: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MEM ARUSER";
  ATTRIBUTE X_INTERFACE_INFO OF m_axi_mem_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MEM ARVALID";


        RESOLUTION   : string  := "HD1080P"; -- HD1080P, HD720P, SVGA, VGA
        GEN_PATTERN  : boolean := false; -- generate pattern or objects
        GEN_PIX_LOC  : boolean := true; -- generate location counters for x / y coordinates
        OBJECT_SIZE  : natural := 16; -- size of the objects. should be higher than 11


                rgb <= wall_rgb;
            elsif ball_on='1' then
                rgb <= ball_rgb;
            elsif box_on='1' then


                case state is
                when s0 =>


    );
    port(
        -- reset and clocks


--   OSERDESE2 is an encrypted IP, so convert that to
--   OSERDESE1 (6-series serdes)
fors6: if SERIES6 = true generate


            if din(i) = '1' then
                c := c + 1;
            end if;


            wait for clk_period/2;
            clk <= not clk;
        --end loop;


    enb : IN STD_LOGIC;
    addrb : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
    doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
  );
END COMPONENT;


    addrb : in STD_LOGIC_VECTOR ( 18 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 11 downto 0 )
  );


    addra : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
    dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
    clkb : IN STD_LOGIC;


    clkb : in STD_LOGIC;
    enb : in STD_LOGIC;
    addrb : in STD_LOGIC_VECTOR ( 18 downto 0 );


C_EN_SAFETY_CKT              : integer := 0;


      C_READ_WIDTH_B => 12,
      C_WRITE_DEPTH_B => 307200,
      C_READ_DEPTH_B => 307200,
      C_ADDRB_WIDTH => 19,
      C_HAS_MEM_OUTPUT_REGS_A => 0,


  signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
  signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;


entity clk_wiz_0 is
  Port (
    clk_in1 : in STD_LOGIC;
    clk_out1 : out STD_LOGIC;
    clk_out2 : out STD_LOGIC


attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fifo_generator_v13_2_10,Vivado 2024.1";
begin


      PRE => src_arst,
      Q => arststages_ff(0)
    );


    dout : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
    full : OUT STD_LOGIC;
    empty : OUT STD_LOGIC;
    rd_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);


    );
clkout1_buf: unisim.vcomponents.BUFG
     port map (


  port (
    clk_out_200M : out STD_LOGIC;
    locked : out STD_LOGIC;


    locked : out STD_LOGIC;
    clk_in1_10M : in STD_LOGIC
  );


ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";


      C_NUM_FILTS : INTEGER;
      C_NUM_TAPS : INTEGER;


			  end if;

          when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or


      if (Lpf_reset = '1') then
        core <= '1';


      ipif_interrupt_PROCESS: process(ip_interrupt_or, ipif_glbl_irpt_enable_reg)
         begin
            ipif_interrupt  <=  ip_interrupt_or and ipif_glbl_irpt_enable_reg;
      end process ipif_interrupt_PROCESS;


        prmry_in                    : in  std_logic                             ;               --
        prmry_vect_in               : in  std_logic_vector                                      --
                                        (C_VECTOR_WIDTH - 1 downto 0)           ;               --


		variable addr_n: std_ulogic_vector(addr'range) := (others => '0');
	begin
		addr_n := priority(irc_n, not lowest_interrupt_first);
		addr_o <= addr_n after g.delay;
		if select_bit(mask_n, addr_n) = '1' then


		ps2_data:     in  std_ulogic; -- data signal from PS/2 keyboard
		ps2_code_new: out std_ulogic; -- flag that new PS/2 code is available on ps2_code bus
		ps2_code:     out std_ulogic_vector(7 downto 0)); -- code received from PS/2
end entity;


		port map(
			clk => clk,
			rst => rst,
			we  => mem_data_i_we,


		report "clk_process end";
		wait;
	end process;


if count = unsigned(compare) and enabled = '1' then


		btnc:     in  std_ulogic                    := 'X';  -- button centre
		btnl:     in  std_ulogic                    := 'X';  -- button left


entity uart_tx is
	generic (g: common_generics; N: positive; format: std_ulogic_vector(7 downto 0) := uart_8N1);


duration: process begin wait for simulation_us; stop <= true; wait; end process;


		load: in  std_ulogic;
		ce:   in  std_ulogic;
		do:   out std_ulogic := '0';
		di:   in  std_ulogic_vector(N - 1 downto 0));
end entity;


muhammadaldacher/MSc_Courses_SJSU/EE178 - Digital Design with FPGA/LABs _ Project/LAB6_Line Drawing Algorithm/lab6.srcs/sources_1/ip/framebuffer/framebuffer.vho

    douta => douta,
    clkb => clkb,
    web => web,
    addrb => addrb,


muhammadaldacher/MSc_Courses_SJSU/EE178 - Digital Design with FPGA/LABs _ Project/LAB6_Line Drawing Algorithm/lab6.srcs/sources_1/ip/framebuffer/framebuffer_sim_netlist.vhdl


muhammadaldacher/MSc_Courses_SJSU/EE178 - Digital Design with FPGA/LABs _ Project/LAB6_Line Drawing Algorithm/lab6.srcs/sources_1/ip/framebuffer/framebuffer_stub.vhdl

attribute black_box_pad_pin of stub : architecture is "clka,wea[0:0],addra[15:0],dina[3:0],douta[3:0],clkb,web[0:0],addrb[14:0],dinb[7:0],doutb[7:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_3,Vivado 2016.2";
begin
end;


muhammadaldacher/MSc_Courses_SJSU/EE178 - Digital Design with FPGA/LABs _ Project/LAB6_Line Drawing Algorithm/lab6.srcs/sources_1/ip/framebuffer/misc/blk_mem_gen_v8_3.vhd

architecture xilinx of blk_mem_gen_v8_3_3 is
  begin
  end
architecture xilinx;


muhammadaldacher/MSc_Courses_SJSU/EE178 - Digital Design with FPGA/LABs _ Project/LAB6_Line Drawing Algorithm/lab6.srcs/sources_1/ip/framebuffer/synth/framebuffer.vhd

    clkb : IN STD_LOGIC;
    web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    addrb : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
    dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
    doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)


muhammadaldacher/MSc_Courses_SJSU/EE178 - Digital Design with FPGA/LABs _ Project/LAB8_Digital Analog Clock Project/EE178_FinalProject.srcs/sources_1/ip/framebuffer/framebuffer.vho

------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : framebuffer


muhammadaldacher/MSc_Courses_SJSU/EE178 - Digital Design with FPGA/LABs _ Project/LAB8_Digital Analog Clock Project/EE178_FinalProject.srcs/sources_1/ip/framebuffer/framebuffer_sim_netlist.vhdl

\prim_noinit.ram\: entity work.\framebuffer_blk_mem_gen_prim_wrapper__parameterized0\
     port map (
      DOADO(0) => DOADO(0),
      DOBDO(1 downto 0) => DOBDO(1 downto 0),


muhammadaldacher/MSc_Courses_SJSU/EE178 - Digital Design with FPGA/LABs _ Project/LAB8_Digital Analog Clock Project/EE178_FinalProject.srcs/sources_1/ip/framebuffer/framebuffer_stub.vhdl

    dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 7 downto 0 )
  );


muhammadaldacher/MSc_Courses_SJSU/EE178 - Digital Design with FPGA/LABs _ Project/LAB8_Digital Analog Clock Project/EE178_FinalProject.srcs/sources_1/ip/framebuffer/misc/blk_mem_gen_v8_3.vhd


muhammadaldacher/MSc_Courses_SJSU/EE178 - Digital Design with FPGA/LABs _ Project/LAB8_Digital Analog Clock Project/EE178_FinalProject.srcs/sources_1/ip/framebuffer/synth/framebuffer.vhd

      C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
      C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
      C_USE_SOFTECC : INTEGER;


            if (SAMPLE_EN = '1') then
                btn_raw_sample_reg <= btn_raw_sync_reg2;
            end if;
        end if;


            clk_en_1k_reg <= '0';
        elsif (rising_edge(CLK)) then
            clk_en_1k_reg <= clk_en_1k_comb;
        end if;
    end process;


    attribute PRESERVE of meta_reg  : signal is TRUE;
    attribute PRESERVE of reset_reg : signal is TRUE;

begin


                sseg_dp    <= not DOTS(2);
                sseg_anode <= "1011";


    s_dout_reg_p : process (CLK, reset)
    begin
        if (reset = '1') then
            s_dout_reg <= (others => '0');


    rst_btn <= not RST_BTN_N;

    rst_sync_i : entity work.RST_SYNC


                second_edge_en <= '0';
                rx_data_vld    <= '0';


    clk_gen_p : process
    begin
        CLK <= '0';
        wait for CLK_PERIOD/2;
        CLK <= '1';


        if (v_test_done = '1') then
            wait for 100*CLK_PERIOD;
            sim_done <= '1';
            report "======== SIMULATION SUCCESSFULLY COMPLETED! ========";
            wait;


        USB_StreamSLWR_n : out std_logic;
        USB_StreamFX2Rdy : in std_logic;
        USB_StreamData : inout std_logic_vector(15 downto 0);


      output_offset <= (others => '0');
      output_number <= X"00";
    elsif rising_edge(clk) then
      -- In the previous phase, we've set the 'overflow' flag.


		USB_StreamCLK <= '0';
		wait for USB_StreamCLK_period/2;
		USB_StreamCLK <= '1';
		wait for USB_StreamCLK_period/2;
   end process;


      -- (2xy)
      XYpXY_reg <= resize(scalb(XY_reg, 1), XYpXY_reg);

      -- Debugging the computations.
      -- if is_used_slot(2) = '1' then


subtype iterations is unsigned(7 downto 0);


  type fixed_round_style_type is (fixed_round, fixed_truncate);

  type fixed_overflow_style_type is (fixed_saturate, fixed_wrap);


        assert not ISSUE_ERROR
          report fixed_pkg'instance_name
          & "OREAD Error: Read a '" & c &


constant connnectionRange : constIntArray (3 downto 0) := (12,10,3,0);


architecture behave of control is

  type delay_array is array (1 to delay) of std_logic;


  port    ( clk : in std_logic;
				inputsIn : in input;
				output : out integer range 0 to 255);


        clk_o     : out std_logic;                      -- output clock (do not modify)
        led       : out std_logic_vector(2 downto 0));  -- not supported by remote lab
end nn_rgb;


	(
		address		: IN STD_LOGIC_VECTOR (11 DOWNTO 0);
		clock		: IN STD_LOGIC  := '1';


  signal vs_delay : delay_array;
  signal hs_delay : delay_array;
  signal de_delay : delay_array;


            w2 : integer;
            w3 : integer;


        enable_in : in  std_logic_vector(2 downto 0);   -- three slide switches
        -- video in


		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);


    write (l_sim, y_size);
    writeline(response_file, l_sim);
    write (l_sim, string'("255"));       -- maximum value
    writeline(response_file, l_sim);


      CLKFBOUT_PHASE : real := 0.0;
      REF_JITTER1 : real := 0.100;


entity SiaMinerUart_tb is end SiaMinerUart_tb;


      -- These last FIFO flops could be  implemented outside for flexibility
      -- (consider last round). There is no B because it is buffered in by
      -- the next MixG on the pipeline.
      A3 <= A2;


constant kHashLen  : unsigned(7 downto 0) := x"20"; -- 32 bytes


    A_in  : in  U64Array_t(3 downto 0);
    B_in  : in  U64Array_t(3 downto 0);
    C_in  : in  U64Array_t(3 downto 0);


entity SiaMinerPiped_tb is
  generic (runner_cfg : string);
end SiaMinerPiped_tb;


constant kStdTestNonce : unsigned(63 downto 0) := x"0000000000000000";


--    if (sum(8) = '0') then
      AUDIO_OUT <= sum(7 downto 0);


  p_cnt_compare_comb : process(pcount,lcount)
  begin
    hterm <= (pcount = (PIXEL_PER_LINE(10 downto 0) - "1"));
    vterm <= (lcount = (LINE_PER_FRAME( 9 downto 0) - "1"));
  end process;


  p_we : process(RW_L, CS_L, ENA)
  begin
    we <= (not CS_L) and (not RW_L) and ENA;
  end process;


      LANG					=> LANG,
		SHIPS					=> SHIPS,


    C_DOUT       : out   std_logic_vector( 7 downto 0);
    C_RW_L       : in    std_logic;
    VMEM_L       : in    std_logic;

    DMA_GO_L     : in    std_logic;


            meta_reg  <= '0';
            reset_reg <= meta_reg;
        end if;


        PARITY_BIT    : string  := "none"; -- legal values: "none", "even", "odd", "mark", "space"
        USE_DEBOUNCER : boolean := True    -- enable/disable debouncer
    );


                    wb_dout <= debug_reg;
                when others =>


    signal uart_dout     : std_logic_vector(7 downto 0);
    signal uart_dout_vld : std_logic;
    signal uart_din      : std_logic_vector(7 downto 0);
    signal uart_din_vld  : std_logic;


    Generic (
        DIV_MAX_VAL  : integer := 16;


        all_bits_or_l : for i in 0 to SHREG_DEPTH-1 loop
            or_var := or_var or input_shreg(i);
        end loop;
        output_reg_rst <= not or_var;
    end process;


            PARITY_OUT <= parity_temp;
        end process;
    end generate;


            when databits =>
                tx_ready <= '0';
                tx_data_out_sel <= "10";
                tx_bit_count_en <= '1';
                tx_clk_div_clr <= '0';


        if (rising_edge(CLK)) then
            uart_rxd_meta_n   <= not UART_RXD;
            uart_rxd_synced_n <= uart_rxd_meta_n;
        end if;
    end process;


        RST <= '1';
        wait for CLK_PERIOD*3;
          RST <= '0';


	port (
		x,y: in std_logic_vector(31 downto 0);
		z: out std_logic_vector(31 downto 0)


		in_1, in_2: std_logic_vector(31 downto 0);
		alu_control_fuct: in std_logic_vector(3 downto 0);
		zero: out std_logic;
		alu_result: out std_logic_vector(31 downto 0)


entity alu_control is
	port (
		funct: in std_logic_vector(5 downto 0);


reg_dest,jump, branch, mem_read, mem_to_reg, mem_write, alu_src, reg_write: out std_logic;


			alu_control_fuct: out std_logic_vector(3 downto 0)
		);
	end component;


architecture beh of mux is
	begin
	z <= x when (s='0') else y;
end beh;


entity registers is
	port (
        ck: in std_logic;
		reg_write: in std_logic;


	begin
	temp <= std_logic_vector(resize(unsigned(x), n2)); -- This is required if you want to increase or decease the number of bits
	y <= std_logic_vector(shift_left(signed(temp), k));


architecture beh of sign_extend is
	begin
	y <= std_logic_vector(resize(signed(x), y'length));
end beh;


        end for;
        for all : bist_RF2
          use configuration work.bist_rf2_asic;
        end for;
      end for;


          use configuration work.bist_rf1_inferred;
        end for;
        for all : bist_RF2


  for arch
    for g : gpsif
      use configuration work.gpsif_sim;
    end for;


constant NULL_DMA_REQ : dma_req_t := ( req => (others => '0') );


entity gpsif_top is
  generic (   GPSIF_NC : integer := 7;
         ANGLE_INI_OLD : boolean := false );
  port (
    clk     : in std_logic;


    variable LI    : line;
    variable input : std_logic_vector(1 downto 0);
  begin
    -- gps signal input
    input_loop: while true loop


        end if;
        readline(FI, LI);
        read(LI, input(1 downto 0));
        gps_d <= input;


      case s(i) is
        when LF | CR => s_no_eol(i) := '_';
        when others  => s_no_eol(i) := s(i);
      end case;


    end case;

    --Scan_Err <= '0'; -- to create an on-purpose error on Scan_Err !

  end if;


    read_key       => read_key,
--    AN             => LEDG(7 downto 4),
    GAMEPORT       => GAMEPORT,


                  when x"3" =>          -- C030 - C03F
                    SPEAKER_SELECT <= '1';
                  when x"4" =>


    clk  : in  std_logic;
    dout : out unsigned(4 downto 0));


    variable new_phase : integer;
    variable rel_phase : std_logic_vector(3 downto 0);
  begin
    if rising_edge(CLK_14M) then
      if reset = '1' then


  begin
    if rising_edge(clk) then
      dout <= ROM(TO_INTEGER(addr));


      if state = NORMAL_KEY then
        latched_code <= code ;
        key_pressed <= '1';
      end if;


entity timing_testbench is

end timing_testbench;


      hires_delayed <= graph_shiftreg(0);
    end if;
  end process;


            joined <= data_in & joined(joined'high downto 5) ;
         else
            joined <= (data_in xor "11111") & joined(joined'high downto 5) ;
         end if;


            -- We've just seen a sync codeword, so restart the counter
            -- This means that we are in sync
            ------------------------------------------------------------
            since_sync  <= (others => '0');


         else
            sync_seen <= '0';
         end if;
      end if;
   end process;


           clk_input     : in  STD_LOGIC;
           strobe        : in  STD_LOGIC;
           ser_data      : out  STD_LOGIC_VECTOR (4 downto 0);
           ser_input     : in STD_LOGIC);
end input_serialiser;


data_out(3) <= sometimes_inverted(3) XNOR sometimes_inverted(2);


           clk_x1        : out STD_LOGIC;
           clk_x2        : out STD_LOGIC;
           clk_x10       : out STD_LOGIC;
           serdes_strobe : out STD_LOGIC);
end dvid_out_clocking;


           strobe     : in  STD_LOGIC;
           ser_data   : in  STD_LOGIC_VECTOR (4 downto 0);
           ser_output : out STD_LOGIC);
end output_serialiser;


		vsync      : IN std_logic;
		tmds_out_p : OUT std_logic_vector(3 downto 0);
		tmds_out_n : OUT std_logic_vector(3 downto 0)
		);


			strIndex <= strIndex + 1;
		end if;
	end if;
end process;


begin
   if clk'EVENT AND clk = '1' then
      if reset_periodic_check_cnt = '1' then
         periodic_check_cnt <= 0;
      elsif periodic_check_cnt = (CHECK_PERIOD_CLOCKS - 1) then


         else
            enable_mouse_display <= '0';
         end if;
      end if;


if(delay_100us_counter_enable = '1') then


           DATA : in  STD_LOGIC_VECTOR (7 downto 0);
           CLK : in  STD_LOGIC;
           READY : out  STD_LOGIC;
           UART_TX : out  STD_LOGIC);
end UART_TX_CTRL;


port
 (-- Clock in ports
  clk_in1           : in     std_logic;
  -- Clock out ports
  clk_out1          : out    std_logic


  -- Clock out ports
  clk_out1          : out    std_logic
 );


if (sig_cntrs_ary(index) = CNTR_MAX) then


					txState <= RDY;
				else
					txState <= LOAD_BIT;
				end if;
			end if;


  signal FLOAT_VCCINT_ALARM : std_logic;
  signal FLOAT_USER_TEMP_ALARM : std_logic;
  signal FLOAT_VBRAM_ALARM : std_logic;
  signal FLOAT_MUXADDR : std_logic_vector (4 downto 0);
  signal aux_channel_p : std_logic_vector (15 downto 0);


    dclk_in : in STD_LOGIC;
    vauxp6 : in STD_LOGIC;
    vauxn6 : in STD_LOGIC;
    vauxp7 : in STD_LOGIC;


      I2 => ua_narrow_load1_carry_n_6,
      I3 => s_axi_araddr_0_sn_1,
      I4 => \GEN_NARROW_CNT.narrow_bram_addr_inc_d1_reg\,
      I5 => Q(0),


s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);


    s_axi_bid : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
    s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);


    peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
    interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
    peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
  );


      bus_struct_reset => bus_struct_reset,
      peripheral_reset => peripheral_reset,
      interconnect_aresetn => interconnect_aresetn,
      peripheral_aresetn => peripheral_aresetn


    GENERIC (
      C_FAMILY : STRING;
      C_EXT_RST_WIDTH : INTEGER;
      C_AUX_RST_WIDTH : INTEGER;


    maxigp0_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    maxigp0_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );


    saxigp2_bvalid : out STD_LOGIC;
    saxigp2_bready : in STD_LOGIC;
    saxigp2_arid : in STD_LOGIC_VECTOR ( 5 downto 0 );
    saxigp2_araddr : in STD_LOGIC_VECTOR ( 48 downto 0 );


            REG_SYNDROME: process (S_AXI_AClk)
            begin
                if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
                    syndrome_r <= syndrome_ns;


                                    -- 1 is single bit input
        C_FLOP_INPUT                : integer range 0 to 1 := 0                 ;
        C_VECTOR_WIDTH              : integer range 0 to 64 := 32               ;
        C_MTBF_STAGES               : integer range 0 to 6 := 2
            -- Vector Data witdth


      --elsif Chip_Reset_Req_d3='1' then
      --  from_sys <= '0';
      elsif (Core = '0') then
        from_sys <='0';


      if aAxiLiteReset_n = '0' then
        axi_bvalid  <= '0';


      elsif rGammaFactor = "010" then -- Gamma Factor = 1 / 1.5
        rStoredData <= rStoredCoefs1_5(to_integer(unsigned(rReadAddr)));
      elsif rGammaFactor = "011" then -- Gamma Factor = 1 / 1.8
        rStoredData <= rStoredCoefs1_8(to_integer(unsigned(rReadAddr)));


S_AXI_0_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );


      m_axis_video_tuser => m_axis_video_tuser,
      m_axis_video_tlast => m_axis_video_tlast,


  attribute NotValidForBitStream of design_1_axi4stream_vip_0_0 : entity is true;
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of design_1_axi4stream_vip_0_0 : entity is "design_1_axi4stream_vip_0_0,axi4stream_vip_v1_1_3_top,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of design_1_axi4stream_vip_0_0 : entity is "yes";


    s_axis_tuser : in STD_LOGIC_VECTOR ( 0 to 0 )
  );


   generic map (
      kPolarity => '0')
   port map (
      aRst => aLockedIn,


    clk   : in  std_ulogic;             -- Clock 8x higher than can bitrate
    rst   : in  std_ulogic;
    rx    : in  std_ulogic;
    debug : out std_ulogic;


  begin
    if rst = '1' then
      prev_ready    <= '0';
      send_req      <= '0';


    );

  port(
    clk : in  std_ulogic;
    rst : in  std_ulogic;


        bus_1_idle_counter := 0;
        tx_en_1            <= '0';


  end record message;
end package flexray;


      rx    : in  std_ulogic;
      tx    : out std_ulogic;
      debug : out std_ulogic;
      msg   : out work.can.message;
      ready : out std_ulogic);


			areset	: IN STD_LOGIC ;
			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);


wait for 1980 ns;
channel_0 <= '0';
wait for 10020 ns;


entity flexray_generator is
  port (channel_0 : out std_ulogic);
end entity flexray_generator;


begin
    clk <= '0';
    wait for clk_period/2;
    clk <= '1';
    wait for clk_period/2;


    clk <= '1';
    wait for clk_period/2;


    wait until ack = '1';
    write <= '0';
    wait for clk_period;


           data_a : out STD_LOGIC_VECTOR (15 downto 0);
           data_b : out STD_LOGIC_VECTOR (15 downto 0);
           valid : out STD_LOGIC);
end adc;


                end if;
            end if;

        when others =>
            state := S_START;


           adf_le : out STD_LOGIC;
           adf_clk : out STD_LOGIC;


    end if;

    if clear_buffer = '1' then
        write_pointer <= (others => '0');
        read_pointer <= (others => '0');


if rising_edge(clk) then
    pipe_le(0) <= spi_le_int;


           rst : in STD_LOGIC;
           adf_done : in STD_LOGIC;
           sample_valid : out STD_LOGIC;


						case(rgb) is
							when "101000" => pixel <= "100100"; -- BROWN
							when others => pixel <= rgb;
						end case;


						end if;
					end if;
				else
					peak := 128*1024;


			if (rdaddress < 405) then
				q(7 downto 0) <= ram(to_integer(rdaddress & '0'));
			end if;
		end if;
	end process;


				else
					q <= ram(to_integer(rdaddress(9 downto 1))) (15 downto 8);
				end if;


	begin
		if (rising_edge(clk)) then
			if (enable = '1') then
				if (hcount(2 downto 0) = "111") then
					pixel <= pr & sr & pg & sg & pb & sb;


		max_col				: out unsigned(9 downto 0);
		max_row				: out unsigned(9 downto 0);

		samples				: in unsigned(2 downto 0);


		inclk0		: IN STD_LOGIC  := '0';
		c0		: OUT STD_LOGIC ;
		c1		: OUT STD_LOGIC ;
		c2		: OUT STD_LOGIC
	);


		wren				: out std_logic;
		rd_req			: in std_logic;
		rd_ack			: out std_logic;


ENTITY dac_counter IS
	PORT
	(
		aclr		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;


	if (rising_edge(clock_pixel)) then
		--wait until (clock_pixel'event and clock_pixel='1' and hcount(2 downto 0) = dac_step);


				hcount := hcount + 1;
			else
				video_active <= '1';
			end if;


	(
		inclk0		: IN STD_LOGIC  := '0';
		c0		: OUT STD_LOGIC ;


		operation_mode		: STRING;
		outdata_aclr_b		: STRING;
		outdata_reg_b		: STRING;
		power_up_uninitialized		: STRING;
		widthad_a		: NATURAL;


		pixelIn		: in unsigned(15 downto 0);
		rowStoreNr	: in unsigned(9 downto 0);
		colStoreNr	: buffer unsigned(9 downto 0);
		rowStoreReq	: in std_logic;


	D0 : OUT std_logic;
	D1 : OUT std_logic;
	D2 : OUT std_logic;
	VGAR0 : OUT std_logic;
	VGAR1 : OUT std_logic;


h_sync: process (clock_vga, hcount)
variable row : integer range 0 to 1024;
begin
	if (rising_edge(clock_vga)) then
	   hsync <= '1';


                  run <= '1';
               end if;


      p_SyncClkGen : process
      begin


   Port (

   s_axi_aclk : IN STD_LOGIC;
   s_axi_aresetn : IN STD_LOGIC;


      );

   control:
   entity work.control(rtl)
      generic map (


         result := resize(op1, BITS+1) + resize(op2, BITS+1);  -- adder output

         offsetOut := i*(BITS+1);   -- result offset within ouput vector


            we_e <= x"FF";
            data_e <= (others => '0');
            addr_cnt <= addr_cnt + 1;


   process(clk)
   begin
      if rising_edge(clk) then
         count <= count + 1;


      if rising_edge(clk) then
         ones <= sum;
         validOut <= valid;


      if rising_edge(clk) then
         q <= sig_i;
      end if;


         C => target_clk,
         CE => '1',
         CLR => '0',
         D => asyn


begin
   while (not sim_end) loop
	  clk <= '0';
	  wait for (clk_period / 2);


ENTITY clock_divider_testbench IS
END clock_divider_testbench;


ENTITY axi_rc_servo_controller_testbench IS
END axi_rc_servo_controller_testbench;


        when idle =>
            next_state <= idle;
        if go = '1' then
            next_state <= running;


	PORT
		(
		-- User signals
		clk			: in  STD_LOGIC;
        resetn       : in STD_LOGIC;


		-- AXI write data channel signals
		WDATA			: out  STD_LOGIC_VECTOR(31 downto 0);
		WSTRB			: out  STD_LOGIC_VECTOR(3 downto 0);


servo_clk_gen : process
begin
   while (not sim_end) loop
	  clk <= '0';


                current_state <= next_state;
            end if;
        end if;


		slow_clk : out std_logic;
		slow_rst : out std_logic


		else
			control_counter <= control_counter + 1;


					DO <= Save_Mux;
				when "11000" =>
					SP(7 downto 0) <= unsigned(Save_Mux);
				when "11001" =>


				F_Out(Flag_S) <= F_In(Flag_S);
				F_Out(Flag_Z) <= F_In(Flag_Z);


					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
				when others =>


		TS                      : out std_logic_vector(2 downto 0);
		IntCycle_n      : out std_logic;
		IntE            : out std_logic;
		Stop            : out std_logic


				if WEH = '1' then
					RegsH(to_integer(unsigned(AddrA))) <= DIH;
				end if;
				if WEL = '1' then
					RegsL(to_integer(unsigned(AddrA))) <= DIL;


		DOBH            : out std_logic_vector(7 downto 0);
		DOBL            : out std_logic_vector(7 downto 0);
		DOCH            : out std_logic_vector(7 downto 0);


				if TState = "010" and Wait_n = '1' then
					DI_Reg <= DI;


							end if;
						when others =>
							A <= std_logic_vector(PC);
						end case;


		Flag_P : integer := 2;
		Flag_X : integer := 3;


			case cc is
			when "000" => return F(7) = '0'; -- NZ


		Call                    : out std_logic;
		RstP                    : out std_logic;


		Reg1L : RAM16X1D
			port map(
			DPO => DOBL(i),
			SPO => DOAL(i),


		RD_n            : out std_logic;
		WR_n            : out std_logic;
		RFSH_n          : out std_logic;
		HALT_n          : out std_logic;
		BUSAK_n         : out std_logic;


	process(CLK, RESET)
	begin
		if (RESET='1') then
			D1 <= (others => '0');


			if (input2(4)='1') then
				part5 <= (others => '0');
			else


		fmin : IN std_logic_vector(7 downto 0);
		dmout : OUT std_logic_vector (11 DOWNTO 0)
	);
END circuit ;


    Sampler_D: in   STD_LOGIC;      -- Result from integrated comparator for GPIO1/10

    push_button1: in   STD_LOGIC;      -- RF Local oscillator frequency increase


entity FIR8 is
port(clock : in std_logic;
	reset : in std_logic;


	pwm_value: in unsigned (11 downto 0);  -- PWM value input reg
    PWM_Q: out std_logic -- PWM output pin


		push_button2 => n_pb2
    );

end architecture;


    attribute NGD_DRC_MASK of Structure : architecture is 1;

begin
    -- component instantiation statements


  clk_25M <= clki;
  pll_25M_50M_8M33: entity work.lfxp2_pll_25M_50M_8M33
    port map (
      clk => clk_25M,


	flash_so: in std_logic;
	flash_cen, flash_sck, flash_si: out std_logic;