  CLKPERIOD                   : time    := 10 ns;
  STOPCOUNT                   : integer := 200
);
end entity;


architecture xilinx of blk_mem_gen_v8_4_4 is
  begin
  end
architecture xilinx;


ENTITY SIMON_CIPHER_TB IS
END SIMON_CIPHER_TB;


architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;


                        when done =>
                            -- Normal mode, fixed brightness
                            if LED_STATES(i) = '1' then
                                led_values(i) <= BRIGHTNESS;
                            end if;


  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of pll_main_pll_main_clk_wiz : entity is "pll_main_clk_wiz";


begin
	-- some defaults
	dec.op <= op_ld;


                elsif (unsigned(DATA_OUT_OV(7 downto 0)) = x"00" ) then
                    start_activated_by_i2c_next <= '0';
                end if;


    crc_good    :   out std_logic ;
    crc_valid   :   out std_logic


--signals to synhronize the screen
hsync <= '1' when hst_sig >= Hf and hst_sig < Hf + Hs else '0';


			  readsignal : in std_logic;
           CLK : in STD_LOGIC;
           registerbits : out STD_LOGIC_VECTOR (31 downto 0) := (others => '0')
	);
end rw_register;


				CR <= L(7);
				IntL <= L(6 downto 0) & CI;


		end if;
	end process;

	odata_rdy <= en and parchecked;


			O_dataA <= regs(to_integer(unsigned(I_selA)));
			O_dataB <= regs(to_integer(unsigned(I_selB)));
			if (I_we = '1') then
				regs(to_integer(unsigned(I_selD))) <= I_dataD;


    full : OUT STD_LOGIC;
    empty : OUT STD_LOGIC
  );
END shd_pe_fifo;


			        		DATA_OUT <= REG4;
				            else
						    REGD := (DATA_IN+REG4) mod 128;
						    temp := DATA_IN+REG4;


      when "010"  => load_data <= FLOATIS_LAT;
      when "011"  => load_data <= FSQRTS_LAT;


						when "10" =>
							INT_MASK_PRE <= CPU_DO(2 downto 0);


		wait until rising_edge(clk2); vin <= CONV_STD_LOGIC_VECTOR(data(index)(8),12);
		wait until rising_edge(clk2); vin <= CONV_STD_LOGIC_VECTOR(data(index)(4),12);


    vga_v_cnt : in STD_LOGIC_VECTOR ( 7 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ram_read_0_ram_read : entity is "ram_read";


    src_TDATA_blk_n_assign_proc : process(src_data_V_0_state, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, exitcond_reg_151)
    begin
        if (((exitcond_reg_151 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
            src_TDATA_blk_n <= src_data_V_0_state(0);


                            decoded.alu_func <= ALU_SRL;
                        end if;
                    when "110"  => decoded.alu_func <= ALU_OR;
                    when "111"  => decoded.alu_func <= ALU_AND;


    sd_#L_#R_rx : in  std_logic; -- serial data receive
    sd_#L_#R_tx : out std_logic; -- serial data transmit
    from_faust_#L : in std_logic_vector(d_width-1 downto 0); -- left channel data to transmit bit by bit
    from_faust_#R : in std_logic_vector(d_width-1 downto 0); -- right channel data to transmit bit by bit


variable TempReg                    : std_logic_vector((Axi_DataSize_Con-1) downto 0);


          when 13 =>
            if (v_mode = '0') then


			SPO		: out std_ulogic;
			A0		: in std_ulogic;


	port(
		A : in  std_logic_vector(7 downto 0);
		Z : out std_logic_vector(2 downto 0);
		V : out std_logic
	);


round_const : in std_logic_vector(7 downto 0);


  );
  attribute CORE_GENERATION_INFO : string;


                when PC_JMP_REG_RELATIVE         => add_LHS := unsigned(a);
                when others                      => add_LHS := unsigned(RESET_VECTOR);
            end case;


begin
    if rising_edge(clk_in) then
        clk_cntr <= std_logic_vector(unsigned(clk_cntr)+1);
    end if;
end process;


      src_clk => s_axi_aclk,
      src_data => dma_x_length_int_32b,
      src_data_valid => dma_x_length_int_valid,
      dst_clk => ADCxN_clk,


		port_scandata		: STRING;
		port_scandataout		: STRING;
		port_scandone		: STRING;
		port_scanread		: STRING;
		port_scanwrite		: STRING;


  process
  begin
    while True loop
        CLK <= '0';


    if rising_edge(clk_dsp) then
        if (reset = '1') then
            cnt_rdy <= (0 => '1', others => '0');
            rd_mx   <= '0';
            addrb   <= (others => '0');


    SIGNAL E_RXD : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)) IS
  BEGIN
    E_RX_DV <= '1';


entity tb_mux_74xx151 is

end tb_mux_74xx151;


                        delay_signals(i) <= delay_signals(i + 1);
                    end if;
                end if;


        lockout_o    <= HI;
        lockoutCnt_v := lockoutCnt_v - 1;
      else


data_i             : in  t_ethernet_data;


	--ROM_OFFSET			:	std_logic_vector(7 downto 0) := "00000010";
	-- +3
	ROM_OFFSET			:	std_logic_vector(7 downto 0) := "00000100";

	-- ROM offset for ZXMMC+ external Flash banks


entity Turnstile_Example_TB is
end entity Turnstile_Example_TB;


attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;


           si_wu : out STD_LOGIC;
           last_byte : in STD_LOGIC);


      src_count_ff <= src_count_nxt;
      src_ready_ext_ff <= src_ready_nxt;
    end if;
  end process;


  begin
      if start_xfer = '1' then
          state_cntr <= "00000000";
      else


    -- UART0
    OrangeCrab_GPIO_0 : in  std_logic;


sh2_7:  entity work.shreg generic map (2,3) port map (clk,command(162 downto 160),Op2cx);
sh2_8:  entity work.shreg generic map (2,3) port map (clk,command(165 downto 163),Op2cy);
sh2_9:  entity work.shreg generic map (2,8) port map (clk,command(175 downto 168),Op2cc);


    port (
      rst_n_i : in  std_logic := '1';
      clka_i  : in  std_logic;


    \G_1PIPE_IFACE.s_daddr_r_reg[4]\ : in STD_LOGIC;
    \xsdb_reg_reg[1]\ : in STD_LOGIC;
    basic_trigger : in STD_LOGIC;


            -- Data: input / output data ports
            A               => dspA_M2, -- 30-bit input: A data input
            B               => dspB_12, -- 18-bit input: B data input
            C               => (others=>'0'),
            D               => (others=>'0'),


    buffer_overflow_error : out STD_LOGIC;
    buffer_to_stream_error : out STD_LOGIC;
    m00_axis_aclk : in STD_LOGIC;
    m00_axis_aresetn : in STD_LOGIC;
    m00_axis_tvalid : out STD_LOGIC;


        UPPER_WORD  : in  HALFWORD_TYPE; --!< The upper halfword (16 Bit) of the instruction.
        WRITE_EN    : in  std_logic_vector(0 to 2); --!< Write enable flags for each word.


        process (clk)
        begin
            if (rising_edge(clk)) then


attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_divisor_tvalid,s_axis_divisor_tdata[31:0],s_axis_dividend_tvalid,s_axis_dividend_tdata[31:0],m_axis_dout_tvalid,m_axis_dout_tdata[63:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "div_gen_v5_1_13,Vivado 2018.2";


        mtxr_in_spi_sck,
        mtxr_in_spi_mosi,
        mtxr_in_spi_ss,
        mtxr_in_spi_trigger,


        CLKOS: out  std_logic);
end component;


    		else
    			delay_line(0) <= nd;
    			delay_line(1 to MUL_LATENCY+1-1) <= delay_line(0 to MUL_LATENCY+1-2);


    buttonUser:         in      std_logic;   -- high active

    --leds
    leds:               out     std_logic_vector( 5 downto 0 );


generic (
   EBS_AD_RNGE  : natural := 16;  -- adressing range
   EBS_AD_BASE  : natural := 2;   -- usual memory segment
   EBS_AD_SIZE  : natural := 512; -- size in segment
   EBS_AD_OFST  : natural := 0;   -- offset in segment


subtype phys_addr is std_logic_vector(vp_addr_width - 1 downto 0);


port (
	clk   :  in std_ulogic;
	reset :  in std_ulogic;
	fd    :  in std_ulogic; -- First data. 1: SEED is used (initialise and calculate), 0: Previous CRC is used (continue and calculate)
	nd    :  in std_ulogic; -- New Data. d input has a valid data. Calculate new CRC


VHDL-100-Projects/Stage 1 - Combinational Basics/23_Ripple_Carry_Adder_4_Bit/RCA4Bit_tb.vhd


      use configuration work.ram_1rw_sim;
    end for;
    for ram
      for all : ram_2rw


entity op_sub is
generic (
			constant data_width : integer := 8;
			constant addr_cnt	:integer := 20


					fifo_en_count <= fifo_en_count + 1;
					-- alt_tap = img_width - (window_size - 1)


    addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
    douta : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
  );
END txt_idx_map_rom;


							FIFO_WR <= '1';
							DEC_ADDR <= std_logic_vector( unsigned(DEC_ADDR) + 1 );
							DROM_READ <= '0';
							WS <= WS_LOAD_FIFO3;
						end if;


        else
            p_ZL13weight_memory_7_ce0_local <= ap_const_logic_0;


            p_ZL13weight_memory_7_ce0_local <= ap_const_logic_1;
        else
            p_ZL13weight_memory_7_ce0_local <= ap_const_logic_0;
        end if;
    end process;


            packet_out_request : out std_logic := '0';
            packet_out_granted : in  std_logic := '0';
            packet_out_valid   : out std_logic := '0';


entity tb_defragment_and_check_crc is
    Port ( a : in STD_LOGIC);
end tb_defragment_and_check_crc;


    signal tx_swing_0p4     : STD_LOGIC := '1';
    signal tx_swing_0p6     : STD_LOGIC := '0';
    signal tx_swing_0p8     : STD_LOGIC := '0';


package OsvvmTypesPkg is

  type slv_vector is array (integer range <>) of std_logic_vector ;
  type uv_vector is array (integer range <>) of unsigned ;
  type sv_vector is array (integer range <>) of signed ;


entity AlertLog_Demo_Global is
end AlertLog_Demo_Global ;


				end if;
			end if;

			-- save track state machine
			case save_track_stage is


    PLLA_inst: PLLA
        generic map (
            FCLKIN => "50",
            IDIV_SEL => 1,


  constant CopyRightNotice : STRING
    := "Copyright  2008 IEEE. All rights reserved.";


          when 10 to 18 => func_width := 10;
          when 19 to 36 => func_width := 9;
          when others => func_width := 12;
        end case;


					if TState = "100" then
						MREQ_n <= '1';


CONSTANT CLOCKS_PER_LINE                    : INTEGER := 1368;                              -- 342*4


					when x"21" => SS_DO <= "00000" & STACK_RAM(0)(10 downto 8);
					when x"22" => SS_DO <= STACK_RAM(1)(7 downto 0);


		CLK			: in std_logic;
		ENABLE		: in std_logic;

		INIT_ADDR	: in std_logic_vector(23 downto 0);


			when 'H' =>			return 'H';
			when '-' =>			return '-';
			when others =>	return 'X';


    rts : out std_logic
  );
end sdrc4_queens_uart;


		VIDEO_G :  OUT  STD_LOGIC_VECTOR(video_bits-1 DOWNTO 0);
		VIDEO_R :  OUT  STD_LOGIC_VECTOR(video_bits-1 DOWNTO 0);
		VIDEO_BLANK : out std_logic;


		pbi_rom_address: out std_logic_vector(12 downto 0);
		pbi_rom_address_enable: out std_logic;
		data_out: out std_logic_vector(7 downto 0);
		cache_data_out: out std_logic_vector(7 downto 0);
		data_out_enable: out std_logic


	 portc  : inout std_logic_vector(7 downto 0);
	 portd  : inout std_logic_vector(7 downto 0);
	 porte  : inout std_logic_vector(7 downto 0);


	if rising_edge(clk) then
	    if dv_par = '1' then
		if lval_in = '0' and fval_in = '1' then
		    read_sync <= '1';


    elsif rising_edge(clk_i) then
      clken <= clkgen_i(to_integer(unsigned(clkprsc)));


      irq_o <= '0';
    elsif rising_edge(clk_i) then
      irq_o <= ctrl.enable and (not fifo.tx_avail) and (not serial.busy);
    end if;


                                       when x"67" =>
                                          dataLen <= to_unsigned(3, dataLen'length);
                                          data(0) <= "00" & buf_tm_hour;


      VRAM_Hi_be           : in    std_logic_vector(3 downto 0);
      vram_blocked         : out   std_logic;


		I_UDSn				: in	std_logic;
		I_LDSn				: in	std_logic;
		I_CRAMn				: in	std_logic;
		I_BR_Wn				: in	std_logic;


  -- This assertion fails at cycle 15
  ONEHOT0_1_a : assert always onehot0(b);


	a0 		:	in signed(coeff_bits - 1 downto 0);
	a1 		:	in signed(coeff_bits - 1 downto 0);
	a2 		:	in signed(coeff_bits - 1 downto 0);


          o_TX_Active <= '0';
          r_TX_Done   <= '1';
          r_SM_Main   <= s_Idle;


constant UCode_Addr_TMDS      : natural := 384;


delayline(delayline'high downto 1) <= delayline(delayline'high - 1 downto 0);


							sCounter <= PERIODS_A;
						end if;


output_row_20, output_row_21, output_row_22, output_row_23, output_row_24, output_row_25, output_row_26, output_row_27, output_row_28, output_row_29,


vga_green  : out   std_logic_vector(7 downto 5);


            cnt     <= (others => '0');
            cnt_smp <= (others => '0');
        elsif rising_edge(clk) then


            end if;
    end process BKEND_RDCE_REG;


--        when '-'    => return_vector(char_ptr-2 to char_ptr) := "---";
-- but synplicity does
        when '_'    => char_ptr                              := char_ptr + 3;


attribute dont_touch of s_axis_tready : signal is "true";


	if rising_edge(clk) then
		romsel_a<=from_zpu.memAAddr(maxAddrBitBRAM);
		romsel_b<=from_zpu.memBAddr(maxAddrBitBRAM);
	end if;
end process;


red_out : out std_logic_vector(7 downto 0);


entity NIOS is
	port (
		clk_clk : in std_logic := '0'  -- clk.clk
	);
end entity NIOS;


	GENERIC (
		lpm_hint		: STRING;
		lpm_representation		: STRING;


    n_clk => clk,
    reset => reset,
    ocp_core_m.MCmd => ocp_M_Cmd,


  ATTRIBUTE X_INTERFACE_INFO OF phy_rx_data: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RXD";
  ATTRIBUTE X_INTERFACE_INFO OF phy_dv: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RX_DV";
  ATTRIBUTE X_INTERFACE_INFO OF phy_crs: SIGNAL IS "xilinx.com:interface:mii:1.0 MII CRS";
  ATTRIBUTE X_INTERFACE_INFO OF phy_rx_clk: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RX_CLK";


      wr_log(i) := std_ulogic_vector(to_stdlogicvector(random(word'length)));
    end loop;

    wait until falling_edge(clock);


    if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
      if (Lpf_reset='1'           --or
          --System_Reset_Req_d3='1' or
          --Chip_Reset_Req_d3='1'   or
	  --ris_edge = '1'


architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_2_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top


    addra : in STD_LOGIC_VECTOR ( 2 downto 0 );
    douta : out STD_LOGIC_VECTOR ( 16 downto 0 )


	core: entity fft1024_wide generic map(dataBits=>dataBits, twBits=>twBits)
		port map(clk=>clk, phase=>core_phase(10-1 downto 0), din=>core_din, dout=>core_dout);


	generic(dataBits: integer := 18;
			twiddleBits: integer := 12;
			subOrder1,subOrder2: integer := 4;
			twiddleDelay: integer := 7;


		AddrWidth	: integer := 11;
		DataWidth	: integer := 8
	);
	port(
		Clk			: in std_logic;


component Resync1b_cp2 is port(
	                        cp2  : in  std_logic;
							DIn  : in  std_logic;


					  mack             : in  std_logic;
 				      -- Interrupt support
			          aes_irq          : out std_logic;


                  end if;

               when RESAMPLE_CLAMP =>
                  if (resampleSum < -32768) then clamp := x"8000";


constant cmd  : string := parse_command(cfg);


bcd_clk                     : in  std_logic;


    PORT(
         clk_i : IN  std_logic;
         blinker_o : OUT  std_logic


    clk_i          : in  std_logic;     -- Master clock.
    lock_i         : in  std_logic                                  := YES;  -- True if clock is stable.


        lpm_width    : natural;
        -- Specifies the number of clock cycles of latency associated with the
        -- alb, aeb, agb, ageb, aleb or aneb output.
        lpm_pipeline : natural := 0;


                     VitalPathDelay01 (
                       OutSignal => dataout(i),
                       OutSignalName => "dataout",
                       OutTemp => dataout_tmp(i),


                        accum(i).i <= resize(shift_right(preamble(i).i*sample.i + preamble(i).q*sample.q, 14),16);
                        accum(i).q <= resize(shift_right(- preamble(i).q*sample.i + preamble(i).i*sample.q, 14),16);


            when READ_SAMPLES =>
                if( fifo_empty = '0' ) then
                    future.rindex <= current.rindex + 1 ;


    Port ( clk : in  STD_LOGIC;
           stream_channel_count : out std_logic_vector(2 downto 0);
           ready : out  STD_LOGIC;


  port (
    a : in STD_LOGIC_VECTOR ( 9 downto 0 );
    d : in STD_LOGIC_VECTOR ( 31 downto 0 );
    dpra : in STD_LOGIC_VECTOR ( 9 downto 0 );
    clk : in STD_LOGIC;


  attribute C_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dist_mem_gen_v8_0_13 : entity is 1024;
  attribute C_ELABORATION_DIR : string;


architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;


attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,addra[8:0],douta[38:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_2,Vivado 2018.3";


entity tb_high_speed_uart is
end tb_high_speed_uart;


begin

  control : entity work.one_slot_break_dvr_dataless


		inclk0		: IN STD_LOGIC  := '0';
		c0		: OUT STD_LOGIC ;
		c1		: OUT STD_LOGIC
	);
END pll2;


        when 'D'       => result(i*4+3 downto i*4) := x"D";
        when 'E'       => result(i*4+3 downto i*4) := x"E";


    we <= I_CS and (not I_RW_L);
  end process;


    BEGIN
        IF( CLK21M'EVENT AND CLK21M = '1' )THEN
            WAIT_ROM_Q <= WAIT_ROM(COMBINED_ADDR_REG);
        END IF;
    END PROCESS;


        sdram_clk_o         : out   std_logic;
        sdram_cs_o          : out   std_logic;
        sdram_we_o          : out   std_logic;

        -- PS/2


        counter := x"000000";
        clk_4hz <= not clk_4hz;
      else


      DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
      DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,


  );
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbm_v3_0_0_ctl_reg;


    wr_clk : in STD_LOGIC;
    rd_clk : in STD_LOGIC;
    din : in STD_LOGIC_VECTOR ( 15 downto 0 );
    wr_en : in STD_LOGIC;


      I0 => '0',
      O => ram_afull_i
    );
i_1: unisim.vcomponents.LUT1


IBUF_DS_ODIV2 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)


      s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
      s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
      s_axi_wlast => '0',


	 absB <= abs(B);

	 sel	<= "00" when absB = 1 else -- selecting shift


	port(
 		clk : in std_logic;
 		we, en : in std_logic;
 		do : out std_logic_vector(7 downto 0 );
 		di : in std_logic_vector(7 downto 0 );


  signal microblaze_1_axi_periph_to_s00_couplers_AWVALID : STD_LOGIC;
  signal microblaze_1_axi_periph_to_s00_couplers_BREADY : STD_LOGIC;
  signal microblaze_1_axi_periph_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal microblaze_1_axi_periph_to_s00_couplers_BVALID : STD_LOGIC;


    S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
    S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );


                                        (C_VECTOR_WIDTH - 1 downto 0)                           --

    );


entity my_ent_generic_port is
  generic (
    PORT_COUNT    : natural;
    port_COUNT    : natural;
    generic_COUNT : natural;


        s_axi_rready  : in std_logic; --! @end

        --! @virtualbus video_in_axi_stream @dir in A slave axi stream interface for video in
        --! axis data bus, transfers two pixels per clock with pixel width of 12 bits in mono color


		elsif rising_edge(sclk) then
			if (sys_ce = '1') then
				case rmw_state is
				when rmw_IDLE =>


	srstn	:in std_logic;
	pclk	:in std_logic;
	mpu_ce  :in std_logic := '1';
	prstn	:in std_logic


  attribute XILINX_LEGACY_PRIM of clkout1_buf : label is "BUFG";
  attribute BOX_TYPE of mmcme3_adv_inst : label is "PRIMITIVE";
  attribute OPT_MODIFIED : string;
  attribute OPT_MODIFIED of mmcme3_adv_inst : label is "MLO";
begin


    clkb : in STD_LOGIC;
    enb : in STD_LOGIC;
    addrb : in STD_LOGIC_VECTOR ( 4 downto 0 );


constant ne               : INTEGER := (VALUE'length+2)/3;


      when '1' =>
        return '1';
    end case;


attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_80M,clk_10M,clk_160M,clk_in1_p,clk_in1_n";
begin


attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "wr_clk,rd_clk,din[15:0],wr_en,rd_en,dout[15:0],full,empty";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fifo_generator_v13_2_5,Vivado 2020.1";


                  state <= videoDataPreamble;
                  ctl0 <= '1';
                  ctl1 <= '0';
                  ctl2 <= '0';


    process (clka)
    begin
        if rising_edge(clka) then


    begin
        if( tb_end = '1' )then
            wait;


variable port_a_disc_time  : std_logic_vector( 20 downto 0 ) := "000000000000000000000";


        In_A        : in    std_logic_vector(fixFmtWidthFromString(AFmt_g) - 1 downto 0);
        In_B        : in    std_logic_vector(fixFmtWidthFromString(BFmt_g) - 1 downto 0);
        -- Output


        case crcWidth is
            when 8 => return x"D5";
            when 16 => return x"0589";
            when others => report "Error: unuspoorted CrcWdith_g" severity error;
        end case;


                        ch2_dly_irq_set_i  <= '0';
                    elsif(ch2_dly_fast_incr = '1' and ch2_delay_tc = '1')then
                        ch2_delay_count    <= (others => '0');
                        ch2_dly_irq_set_i  <= '1';
                    elsif(ch2_dly_fast_incr = '1')then


		                flag_to_repeat_after_fsize_less_err  <= '0';
		            elsif(fsize_mismatch_err_i = '1')then
		                flag_to_repeat_after_fsize_less_err  <= '1';
		            end if;
		        end if;


constant c_nb_line_pxls : natural := log2i(c_img_cols-1) + 1;


      when 6 => return "6";
      when 7 => return "7";


entity tb_assign_last is
  generic (
    runner_cfg : string
  );
end entity;


    input_phase : in u_unsigned(
      get_phase_width(


`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)


constant PHASE_LEN                      : natural := 2**PHASE_W;


subtype FSM_STATE_T is std_logic_vector(DIGIT_CNT-1 downto 0);


         IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
           sim_stop_cntr <= sim_stop_cntr - "1";


      for i in PLOG downto 0 loop
         if (leadZerosBin(i) = '1') then
            dtemp := (others => '0');


	type mem_type is array (0 to RAM_SIZE - 1) of std_logic_vector(RAM_D_WIDTH - 1 downto 0);

	--impure function init_mem(mif_file_name : in string) return mem_type is


    trans_in: in ipbus_trans_out;
    pkt: out std_logic_vector(NSRC - 1 downto 0)
  );

end trans_arb;


constant IPBUS_SEL_WIDTH: positive := 1;


    m_axi_mm2s_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_mm2s_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_mm2s_arvalid : out STD_LOGIC;


    dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
    douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
    clkb : IN STD_LOGIC;
    web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    addrb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);


    constant ap_const_logic_1 : STD_LOGIC := '1';
    constant ap_const_boolean_1 : BOOLEAN := true;
    constant ap_const_logic_0 : STD_LOGIC := '0';


-- Generate level 3 logic
mux_3_0 <= mux_2_0 when sel(2) = '0' else mux_2_1;

-- output logic


    tdo : in STD_LOGIC;
    Scan_En : in STD_LOGIC;
    Scan_Reset : in STD_LOGIC;
    Scan_Reset_Sel : in STD_LOGIC;


    s_axi_bready : IN STD_LOGIC;
    s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);


constant kCtlTkn0 : std_logic_vector(9 downto 0) := "1101010100";


    S_AXI_LITE_CTRL_rvalid : out STD_LOGIC;
    S_AXI_LITE_CTRL_rready : in STD_LOGIC;


    wait for 0 ns ;  wait for 0 ns ;
    TranscriptOpen ;
    SetTranscriptMirror(TRUE) ;


      when AWQOS =>              return to_integer(AxiBus.WriteAddress.QOS   ) ;
      when AWREGION =>           return to_integer(AxiBus.WriteAddress.Region) ;


			cntr := (others => '0');
		elsif rising_edge(in_clk) then
			if in_rst='1' then


      CEP               => one,
      CEM               => one,
      CECTRL            => one,
      CECARRYIN         => one,
	  CECINSUB          => one,


            state_reg          <= answer_ack_start;
            bits_processed_reg <= 0;


		s_axis_tdata	: in std_logic_vector(31 downto 0);
		s_axis_tready   : out std_logic;
		s_axis_tvalid	: in std_logic;


      END IF;
    END IF;
  END PROCESS PipelineRegister_process;


    shared_uvvm_state := INIT_COMPLETED;
    wait;
  end process p_initialize_uvvm;


    -- send x"AA" from sbi interface to UART 2
    log(ID_LOG_HDR, "Check simple transmit", C_SCOPE_J2);
    sbi_write(SBI_VVCT, 2, C_ADDR_TX_DATA, x"AA", "TX_DATA", C_SCOPE_J2);


			if (FSMCache_ARPReq_TimeoutCounter_rst = '1') then
				ARPReq_TimeoutCounter_s		<= to_signed(ARPREQ_TIMEOUTCOUNTER_MAX, ARPReq_TimeoutCounter_s'length);
			else
				ARPReq_TimeoutCounter_s		<= ARPReq_TimeoutCounter_s - 1;


if C_SIM_VERBOSE then		report "simInitialize:" severity NOTE;			end if;