target:
  process( clk ) is
  begin
    if rising_edge( clk ) then
      if ( colorMode = '1' ) then
        redPxlOut <= redGBACol;


target:
          elsif ( curPacket( packetBits - 1 downto packetBits - prefixLen ) = osdState_prefix ) then
            osdActive <= curPacket( 0 );
            osdState( 6 downto 0 ) <= curPacket( 7 downto 1 );


target:
  process( clk ) is
  begin
    if ( rising_edge( clk ) ) then
      if ( fsmSingleValCur = applyMask ) then
        maskedVal <= ( nextMask and doSig ) or ( nextVal and not( nextMask ) ) ;


target:
        ind := offset + x;

        charPxl <= font( char )( ind );
      end if;
    end if;


target:
        end if;

        cnt <= tmpCnt;
      end if;


target:
entity gbaColorCorrNew is
  port(
    gbaRed : in std_logic_vector( 4 downto 0 );
    gbaGreen : in std_logic_vector( 4 downto 0 );


target:
        readSel( i ) <= '0';
      end if;
    end loop;
  end process;


target:
      mainMenu( SMOOTHFIELDY )( SMOOTHFIELDX + 2 ) <= 6;
    end if;

    if ( pixelGrid_int = '1' ) then
      if ( bgrid_int = '1' ) then


target:
signal butUp, butDown, butLeft, butRight, butA, butB, butL, butR,
  butStart, butSelect : std_logic;


target:
    redDataIn : in std_logic_vector( 7 downto 0 );
    blueDataIn : in std_logic_vector( 7 downto 0 );
    greenDataIn : in std_logic_vector( 7 downto 0 );


target:
            rOut <= smoothOut( 0 )( 3 )( 0 );
            gOut <= smoothOut( 0 )( 3 )( 1 );


target:
	p_detect : process(clk) is
		variable v_enable : std_wire;


target:
	ypos   : in  t_ppos;
	reg    : in  t_regs;

	o_vbrd : out std_wire;


target:
(
	clk      : in  std_wire; -- must be twice the video clock (16 times ph0)
	rst      : in  std_wire;


target:
	signal   data_in       : std_word(c_bit_width - 1 downto 0);
	signal   push_in       : std_wire;


target:
				o_clk    <= '0';
			end if;
		end if;


target:
						when MODE_STD_TEXT =>
							o_colr <= x"0";     -- BLACK
						when MODE_MCL_TEXT =>


target:
	i_sprt_prio : in  std_wire;
	i_sprt_colr : in  t_colr;


target:
			end if;
		end if;
	end process;

end architecture;


target:
	i_data  : in  std_word(7 downto 0);
	o_prio  : out std_wire;
	o_actv  : out std_wire;
	o_colr  : out t_colr


target:
			ypos  <= h65_ypos;
			specs <= c_vic_h65_specs;


target:
	-- vic detection
	vic_type     : out t_vic_type;


target: constant c_xpos_bits : positive := bits_for_range(c_max_xlen);


target:
begin
if rising_edge(cEng_core) then
    count12MHz_stable <= count12MHz;
end if;
end process;


target:
entity alu_int32_div_tb is
--  Port ( );
end alu_int32_div_tb;


target:
   begin
		I_clk <= '0';
		wait for I_clk_period/2;
		I_clk <= '1';
		wait for I_clk_period/2;


target:
    constant STATE_IDLE : integer := 0;
    constant STATE_INFLIGHTU : integer := 1;
    constant STATE_COMPLETE : integer := 2;


target: constant EXCEPTION_STORE_AMO_PAGE_FAULT:        std_logic_vector(XLEN32M1 downto 0):=  X"0000000f";


target:
                                interrupt_was_inactive <= '0';
                                interrupt_state <= "001";
                                next_s_state <= "0000001"; --F


target:
        I_int_data : in STD_LOGIC_VECTOR(31 downto 0);
        I_int : in STD_LOGIC;
        O_int_ack : out STD_LOGIC;

        -- memory interface


target:
            csr_instret <= std_logic_vector(unsigned(csr_instret) + 1);
        end if;


target:
                    actual_int <= '1';
                    actual_int_data <= I_int_data1;
                    int1_ack <= '1';
                elsif I_enMask(2) = '1' and I_int2 = '1' and int2_ack = '0' then
                    actual_int <= '1';


target:
                end if;
            elsif state = 2 then
                cmd <= '0';
                state <= 0;


target:
	begin
		if rising_edge(I_clk) then
			case I_nPCop is


target:
        O_dataA  : out STD_LOGIC_VECTOR (XLENM1 downto 0);-- regRS1 data out
        O_dataB  : out STD_LOGIC_VECTOR (XLENM1 downto 0) -- regRS2 data out


target:
        O_memOp : out STD_LOGIC_VECTOR(4 downto 0);     -- Memory operation
        O_csrOP : out STD_LOGIC_VECTOR(4 downto 0);     -- CSR operations
        O_csrAddr : out STD_LOGIC_VECTOR(11 downto 0);  -- CSR address
        O_trapExit : out STD_LOGIC;                     -- request to exit trap handler


target: constant SYSTEM   : std_logic_vector(6 downto 0) := "1110011";


target:
                  dsp_out_accum_results(f) <= std_logic_vector(unsigned(accum_partial_results_stg_1(f)(15 downto 0))  +
                                                            unsigned(accum_partial_results_stg_1(f)(31 downto 16)) +


target:
                      if(rs1(instr_word_IE) /= 0) then
                        MHPMCOUNTER9(h) <= (MHPMCOUNTER9(h) or csr_wdata_i);
                      end if;
                    when CSRRC|CSRRCI =>
                      csr_rdata_o_replicated(h) <= MHPMCOUNTER9(h);


target:
        h := g;  -- set the spm rd/wr ports equal to the "for-loop"
      elsif multithreaded_accl_en = 0 then
        h := f;  -- set the spm rd/wr ports equal to the "for-generate"
      end if;
      --  Addition in SIMD Virtual Parallelism is executed here, if the carries are blocked, we will have a chain of 8-bit or 16-bit adders, else we have 32-bit adders


target:
                  end if;
                when others =>
                  null;


target:
                  case FUNCT3_wires is
                    when ADD => --ADD instruction
                      decoded_instruction_IE <= ADD7_pattern;


target:
        pass_BLTU <= '1';
      else
        pass_BGEU <= '1';
      end if;
    end if;


target:
  begin
    if busy_ID = '0' then
      instr_req_o <= '1';
    else
      instr_req_o <= '0';


target:
                  misaligned_err              <= '1';
                elsif load_err = '1' then  -- AAA move to data_valid_waiting stage


target:
            if decoded_instruction_LS(KMEMLD_bit_position)   = '1' then
              write(row0, string'("    kmemld x"));
            end if;


target:
    mepc_incremented_pc               : out array_2D(THREAD_POOL_SIZE - 1 downto 0)(31 downto 0);
    mepc_interrupt_pc                 : out array_2D(THREAD_POOL_SIZE - 1 downto 0)(31 downto 0);
    irq_pending                       : out std_logic_vector(THREAD_POOL_SIZE - 1 downto 0);
    clk_i                             : in  std_logic;


target:
	MUL_WB                     : in  std_logic_vector(31 downto 0);
	LS_WB                      : in  std_logic_vector(31 downto 0);
	instr_word_LS_WB           : in  std_logic_vector(31 downto 0);
	instr_word_IE_WB           : in  std_logic_vector(31 downto 0);
	harc_LS_WB                 : in  integer range THREAD_POOL_SIZE-1 downto 0;


target:
    Addr_Width            : natural;
    SIMD                  : natural;
    --------------------------------
    ACCL_NUM              : natural;


target:
      sc_addr_wr(h)(l) <= (others => '0');
      sc_data_wr(h)(l) <= (others => '0');
    end loop;
    rd_offset(h)                       <= (others => (others => '0'));


target:
  begin
    if rst_ni = '0' then
    elsif rising_edge(clk_i) then
      pc_except_value <= pc_except_value_wire;  -- AAA verify if it is working for DSP and LSU (not verified yet)


target:
architecture rtl of joyquad is
  type reg_t is record
    d   : unsigned(7 downto 0);
    v   : std_ulogic;
    vq  : std_ulogic;


target: constant RGA_DIWSTRT  : addr_t := x"08E";


target:
    d1  : in  std_ulogic;
    q   : out std_ulogic
  );
end;


target: if cmd.log < LOG_DEBUG then return; end if;


target:
            deni.drd <= (others => 'Z') after 20 ns;
          else
            rgacmd.rdata <= deno.drd;


target:
    rga_write(rgacmd, RGA_COLOR00, x"0000");
    rga_write(rgacmd, RGA_COLOR01, x"0111");
    rga_write(rgacmd, RGA_COLOR02, x"0222");


target:
    m0v             : in    std_ulogic;
    m0h             : in    std_ulogic;


target:
  begin
    report "Procedure STOP called with status: " & INTEGER'image(STATUS)
      severity failure;


target: type round_type is (round_nearest,    -- Default, nearest LSB '0'


target:
      when '9'       => result := x"9"; good := true;
      when 'A' | 'a' => result := x"A"; good := true;
      when 'B' | 'b' => result := x"B"; good := true;


target:
    variable outarray           : cry_type;  -- array for output
    variable in1array, in2array : cry_type;  -- array for input


target:
        fpresult := neg_zerofp (fraction_width => fraction_width-guard,
                                exponent_width => exponent_width);
      when others =>


target:
        when round_inf =>
          round := remainder(2) and not isign;
        when round_neginf =>
          round := remainder(2) and isign;
        when others =>


target:
          outarray(0) := not (in1reg3);
        when "001" =>
          outarray(0) := in1reg3 and in2reg3;
        when "010" =>


target:
  function \?<\ (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
  begin
    return \?<\ (UNSIGNED(L), UNSIGNED(R));
  end function \?<\;


target:
          and (tvar < roundvar and tvar > -roundvar) then
--            and ((bvalue-roundvar) = real(frcptr)) then
          write (L, frcptr);  -- Just a short integer, write it.
        elsif (exp >= dwidth) or (exp < -4) then
          -- in "e" format (modified)


target:
      when '6'       => result := x"6"; good := true;
      when '7'       => result := x"7"; good := true;
      when '8'       => result := x"8"; good := true;
      when '9'       => result := x"9"; good := true;
      when 'A' | 'a' => result := x"A"; good := true;


target:
      when '0' => result := o"0"; good := true;
      when '1' => result := o"1"; good := true;
      when '2' => result := o"2"; good := true;
      when '3' => result := o"3"; good := true;


target:
entity test_fixed_synth is
  generic (
    quiet : boolean := false);  -- make the simulation quiet
end entity test_fixed_synth;


target:
    generic map (
      BITWIDTH  => BITWIDTH,
      IMAGE_WIDTH => IMAGE_WIDTH,
      KERNEL_SIZE => KERNEL_SIZE,
      NB_IN_FLOWS => NB_IN_FLOWS


target:
begin
  out_data <= in_data(to_integer(unsigned(sel)));
  out_dv   <= in_dv;
  out_fv   <= in_fv;


target:
       out_valid => s_out_valid
       );
   out_dv <= s_out_valid;
   out_fv <= s_out_valid;


target:
      if (in_valid = '1') then
        mcm_loop : for i in 0 to DOT_PRODUCT_SIZE - 1 loop
          out_data(i) <= KERNEL_VALUE(i) * in_data(i);


target:
     elsif(rising_edge(clk)) then
       if (enable = '1') then


target:
    enable   : in  std_logic;
    in_data  : in  std_logic_vector((BITWIDTH-1) downto 0);
    in_dv    : in  std_logic;


target:
    SUM_WIDTH  : integer
    );
  port(
    in_data  : in  std_logic_vector (SUM_WIDTH-1 downto 0);


target: constant V2           : integer := SCALE_FACTOR - 10;


target:
entity maxPool is
  generic(
    BITWIDTH  : integer;
    IMAGE_WIDTH : integer;