diff --git a/DATA_MANIFEST.md b/DATA_MANIFEST.md index 0fd5c1d099fa432314a9d96a0ca51b00c01e48bc..16dbb97cd96c04f49a7b8845d947e146aaf204c8 100644 --- a/DATA_MANIFEST.md +++ b/DATA_MANIFEST.md @@ -3,7 +3,7 @@ Each case provides four aligned artifacts under a common root: testbench// verilator differential testbench (run via run_once.sh / run_verilator.sh) snapshots// pre-PR repository snapshot (RTL sources) - patches/.patch the fix; testbench reverse-applies for buggy, applies for fixed + patches/.patch the fix; each harness sets up the pre-fix tree for the buggy phase and applies this for the fixed phase issues/ issue description testbench/_* shared run helpers (sourced by per-case scripts) diff --git a/Phoenix-Bench-croissant.json b/Phoenix-Bench-croissant.json index 722128adc6463aa4046941dd8f3c71ccd6075626..373356acdbab22fc2960bc8f79a0ed692ee86b2d 100644 --- a/Phoenix-Bench-croissant.json +++ b/Phoenix-Bench-croissant.json @@ -5340,7 +5340,7 @@ "instances/instance_id": "FPGA-MAFIA_fpga_mafia_pr499", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/FPGA-MAFIA_fpga_mafia_pr499", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/FPGA-MAFIA_fpga_mafia_pr499.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/FPGA-MAFIA_fpga_mafia_pr499" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/FPGA-MAFIA_fpga_mafia_pr499" }, { "instances/instance_id": "FPGA-MAFIA_fpga_mafia_pr548", @@ -5430,13 +5430,13 @@ "instances/instance_id": "HiSA-Team_Simply-V_pr52", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/HiSA-Team_Simply-V_pr52", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/HiSA-Team_Simply-V_pr52.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/HiSA-Team_Simply-V_pr52" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/HiSA-Team_Simply-V_pr52" }, { "instances/instance_id": "HiSA-Team_Simply-V_pr68", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/HiSA-Team_Simply-V_pr68", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/HiSA-Team_Simply-V_pr68.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/HiSA-Team_Simply-V_pr68" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/HiSA-Team_Simply-V_pr68" }, { "instances/instance_id": "HiSA-Team_Simply-V_pr92", @@ -5496,7 +5496,7 @@ "instances/instance_id": "MiSTer-devel_Gameboy_MiSTer_pr24", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_Gameboy_MiSTer_pr24", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_Gameboy_MiSTer_pr24.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_Gameboy_MiSTer_pr24" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/MiSTer-devel_Gameboy_MiSTer_pr24" }, { "instances/instance_id": "MiSTer-devel_Gameboy_MiSTer_pr240", @@ -5514,7 +5514,7 @@ "instances/instance_id": "MiSTer-devel_Gameboy_MiSTer_pr96", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_Gameboy_MiSTer_pr96", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_Gameboy_MiSTer_pr96.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_Gameboy_MiSTer_pr96" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/MiSTer-devel_Gameboy_MiSTer_pr96" }, { "instances/instance_id": "MiSTer-devel_Genesis_MiSTer_pr144", @@ -5694,13 +5694,13 @@ "instances/instance_id": "Panda-Cores_PandaZero_pr14", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/Panda-Cores_PandaZero_pr14", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/Panda-Cores_PandaZero_pr14.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/Panda-Cores_PandaZero_pr14" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/Panda-Cores_PandaZero_pr14" }, { "instances/instance_id": "Panda-Cores_PandaZero_pr3", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/Panda-Cores_PandaZero_pr3", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/Panda-Cores_PandaZero_pr3.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/Panda-Cores_PandaZero_pr3" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/Panda-Cores_PandaZero_pr3" }, { "instances/instance_id": "Panda-Cores_PandaZero_pr4", @@ -5778,7 +5778,7 @@ "instances/instance_id": "UTOSS_risc-v_pr115", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr115", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr115.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr115" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/UTOSS_risc-v_pr115" }, { "instances/instance_id": "UTOSS_risc-v_pr127", @@ -5885,8 +5885,8 @@ { "instances/instance_id": "UTOSS_risc-v_pr81", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr81", - "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr81.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr81" + "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/main/patches/UTOSS_risc-v_pr81.patch", + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/UTOSS_risc-v_pr81" }, { "instances/instance_id": "UTOSS_risc-v_pr83", @@ -5910,7 +5910,7 @@ "instances/instance_id": "UTOSS_risc-v_pr97", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr97", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr97.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr97" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/UTOSS_risc-v_pr97" }, { "instances/instance_id": "Wren6991_Hazard3_pr23", @@ -5964,7 +5964,7 @@ "instances/instance_id": "alexforencich_verilog-pcie_pr19", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/alexforencich_verilog-pcie_pr19", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/alexforencich_verilog-pcie_pr19.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/alexforencich_verilog-pcie_pr19" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/alexforencich_verilog-pcie_pr19" }, { "instances/instance_id": "alexforencich_verilog-pcie_pr20", @@ -6078,7 +6078,7 @@ "instances/instance_id": "bensampson5_libsv_pr150", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bensampson5_libsv_pr150", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bensampson5_libsv_pr150.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bensampson5_libsv_pr150" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/bensampson5_libsv_pr150" }, { "instances/instance_id": "bensampson5_libsv_pr153", @@ -6174,7 +6174,7 @@ "instances/instance_id": "bespoke-silicon-group_basejump_stl_pr675", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bespoke-silicon-group_basejump_stl_pr675", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bespoke-silicon-group_basejump_stl_pr675.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bespoke-silicon-group_basejump_stl_pr675" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/bespoke-silicon-group_basejump_stl_pr675" }, { "instances/instance_id": "bespoke-silicon-group_basejump_stl_pr676", @@ -6414,7 +6414,7 @@ "instances/instance_id": "chipsalliance_caliptra-rtl_pr1132", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-rtl_pr1132", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-rtl_pr1132.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-rtl_pr1132" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/chipsalliance_caliptra-rtl_pr1132" }, { "instances/instance_id": "chipsalliance_caliptra-rtl_pr757", @@ -6432,37 +6432,37 @@ "instances/instance_id": "chipsalliance_caliptra-rtl_pr883", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-rtl_pr883", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-rtl_pr883.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-rtl_pr883" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/chipsalliance_caliptra-rtl_pr883" }, { "instances/instance_id": "chipsalliance_caliptra-rtl_pr919", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-rtl_pr919", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-rtl_pr919.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-rtl_pr919" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/chipsalliance_caliptra-rtl_pr919" }, { "instances/instance_id": "chipsalliance_caliptra-rtl_pr921", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-rtl_pr921", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-rtl_pr921.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-rtl_pr921" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/chipsalliance_caliptra-rtl_pr921" }, { "instances/instance_id": "chipsalliance_caliptra-rtl_pr963", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-rtl_pr963", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-rtl_pr963.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-rtl_pr963" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/chipsalliance_caliptra-rtl_pr963" }, { "instances/instance_id": "chipsalliance_caliptra-ss_pr550", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-ss_pr550", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-ss_pr550.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-ss_pr550" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/chipsalliance_caliptra-ss_pr550" }, { "instances/instance_id": "chipsalliance_caliptra-ss_pr565", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-ss_pr565", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-ss_pr565.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-ss_pr565" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/chipsalliance_caliptra-ss_pr565" }, { "instances/instance_id": "chipsalliance_caliptra-ss_pr590", @@ -6474,13 +6474,13 @@ "instances/instance_id": "chipsalliance_caliptra-ss_pr750", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-ss_pr750", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-ss_pr750.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-ss_pr750" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/chipsalliance_caliptra-ss_pr750" }, { "instances/instance_id": "chipsalliance_caliptra-ss_pr838", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-ss_pr838", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-ss_pr838.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-ss_pr838" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/chipsalliance_caliptra-ss_pr838" }, { "instances/instance_id": "chipsalliance_i3c-core_pr35", @@ -6534,7 +6534,7 @@ "instances/instance_id": "hdl-util_hdmi_pr12", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/hdl-util_hdmi_pr12", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/hdl-util_hdmi_pr12.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/hdl-util_hdmi_pr12" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/hdl-util_hdmi_pr12" }, { "instances/instance_id": "hdl-util_hdmi_pr15", @@ -6912,7 +6912,7 @@ "instances/instance_id": "lowRISC_ibex_pr1917", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/lowRISC_ibex_pr1917", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/lowRISC_ibex_pr1917.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/lowRISC_ibex_pr1917" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/lowRISC_ibex_pr1917" }, { "instances/instance_id": "lowRISC_ibex_pr2166", @@ -6948,7 +6948,7 @@ "instances/instance_id": "lowRISC_ibex_pr2269", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/lowRISC_ibex_pr2269", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/lowRISC_ibex_pr2269.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/lowRISC_ibex_pr2269" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/lowRISC_ibex_pr2269" }, { "instances/instance_id": "lowRISC_opentitan_pr28469", @@ -7098,7 +7098,7 @@ "instances/instance_id": "muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr29", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr29", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr29.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr29" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr29" }, { "instances/instance_id": "muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr31", @@ -7194,7 +7194,7 @@ "instances/instance_id": "openhwgroup_cv32e40s_pr254", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_cv32e40s_pr254", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_cv32e40s_pr254.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_cv32e40s_pr254" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/openhwgroup_cv32e40s_pr254" }, { "instances/instance_id": "openhwgroup_cv32e40s_pr259", @@ -7212,7 +7212,7 @@ "instances/instance_id": "openhwgroup_cv32e40x_pr894", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_cv32e40x_pr894", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_cv32e40x_pr894.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_cv32e40x_pr894" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/openhwgroup_cv32e40x_pr894" }, { "instances/instance_id": "openhwgroup_cv32e41p_pr15", @@ -7392,13 +7392,13 @@ "instances/instance_id": "pulp-platform_axi_pr138", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_pr138", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_pr138.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_pr138" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/pulp-platform_axi_pr138" }, { "instances/instance_id": "pulp-platform_axi_pr185", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_pr185", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_pr185.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_pr185" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/pulp-platform_axi_pr185" }, { "instances/instance_id": "pulp-platform_axi_pr224", @@ -7518,7 +7518,7 @@ "instances/instance_id": "pulp-platform_axi_riscv_atomics_pr37", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_riscv_atomics_pr37", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_riscv_atomics_pr37.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_riscv_atomics_pr37" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/pulp-platform_axi_riscv_atomics_pr37" }, { "instances/instance_id": "pulp-platform_axi_riscv_atomics_pr38", @@ -7536,7 +7536,7 @@ "instances/instance_id": "pulp-platform_carfield_pr27", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_carfield_pr27", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_carfield_pr27.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_carfield_pr27" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/pulp-platform_carfield_pr27" }, { "instances/instance_id": "pulp-platform_carfield_pr41", @@ -7595,8 +7595,8 @@ { "instances/instance_id": "pulp-platform_common_cells_pr188", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_common_cells_pr188", - "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_common_cells_pr188.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_common_cells_pr188" + "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/main/patches/pulp-platform_common_cells_pr188.patch", + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/pulp-platform_common_cells_pr188" }, { "instances/instance_id": "pulp-platform_common_cells_pr222", @@ -7734,13 +7734,13 @@ "instances/instance_id": "pulp-platform_neureka_pr30", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_neureka_pr30", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_neureka_pr30.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_neureka_pr30" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/pulp-platform_neureka_pr30" }, { "instances/instance_id": "pulp-platform_pulp_soc_pr23", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_pulp_soc_pr23", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_pulp_soc_pr23.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_pulp_soc_pr23" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/pulp-platform_pulp_soc_pr23" }, { "instances/instance_id": "pulp-platform_pulp_soc_pr41", @@ -7829,8 +7829,8 @@ { "instances/instance_id": "pulp-platform_register_interface_pr32", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_register_interface_pr32", - "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_register_interface_pr32.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_register_interface_pr32" + "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/main/patches/pulp-platform_register_interface_pr32.patch", + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/pulp-platform_register_interface_pr32" }, { "instances/instance_id": "pulp-platform_register_interface_pr33", @@ -7901,8 +7901,8 @@ { "instances/instance_id": "pulp-platform_riscv-dbg_pr123", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_riscv-dbg_pr123", - "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_riscv-dbg_pr123.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_riscv-dbg_pr123" + "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/main/patches/pulp-platform_riscv-dbg_pr123.patch", + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/pulp-platform_riscv-dbg_pr123" }, { "instances/instance_id": "pulp-platform_riscv-dbg_pr145", @@ -7992,7 +7992,7 @@ "instances/instance_id": "pulp-platform_tech_cells_generic_pr17", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_tech_cells_generic_pr17", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_tech_cells_generic_pr17.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_tech_cells_generic_pr17" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/pulp-platform_tech_cells_generic_pr17" }, { "instances/instance_id": "pulp-platform_tech_cells_generic_pr22", @@ -8076,7 +8076,7 @@ "instances/instance_id": "svunit_svunit_pr114", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/svunit_svunit_pr114", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/svunit_svunit_pr114.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/svunit_svunit_pr114" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/svunit_svunit_pr114" }, { "instances/instance_id": "svunit_svunit_pr197", @@ -8100,7 +8100,7 @@ "instances/instance_id": "taichi-ishitani_tvip-axi_pr36", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/taichi-ishitani_tvip-axi_pr36", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/taichi-ishitani_tvip-axi_pr36.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/taichi-ishitani_tvip-axi_pr36" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/taichi-ishitani_tvip-axi_pr36" }, { "instances/instance_id": "taichi-ishitani_tvip-axi_pr44", @@ -8112,7 +8112,7 @@ "instances/instance_id": "taichi-ishitani_tvip-axi_pr47", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/taichi-ishitani_tvip-axi_pr47", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/taichi-ishitani_tvip-axi_pr47.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/taichi-ishitani_tvip-axi_pr47" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/taichi-ishitani_tvip-axi_pr47" }, { "instances/instance_id": "taichi-ishitani_tvip-axi_pr50", @@ -8130,13 +8130,13 @@ "instances/instance_id": "va7deo_zerowing_pr17", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/va7deo_zerowing_pr17", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/va7deo_zerowing_pr17.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/va7deo_zerowing_pr17" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/va7deo_zerowing_pr17" }, { "instances/instance_id": "verilator_verilator_pr6552", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6552", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6552.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6552" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/verilator_verilator_pr6552" }, { "instances/instance_id": "verilator_verilator_pr6573", @@ -8178,7 +8178,7 @@ "instances/instance_id": "verilator_verilator_pr6697", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6697", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6697.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6697" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/verilator_verilator_pr6697" }, { "instances/instance_id": "verilator_verilator_pr6723", @@ -8189,8 +8189,8 @@ { "instances/instance_id": "verilator_verilator_pr6737", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6737", - "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6737.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6737" + "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/main/patches/verilator_verilator_pr6737.patch", + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/verilator_verilator_pr6737" }, { "instances/instance_id": "verilator_verilator_pr6815", @@ -8232,7 +8232,7 @@ "instances/instance_id": "verilator_verilator_pr6870", "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6870", "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6870.patch", - "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6870" + "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/verilator_verilator_pr6870" }, { "instances/instance_id": "verilator_verilator_pr6876", @@ -8284,7 +8284,7 @@ "http://mlcommons.org/croissant/RAI/1.0" ], "name": "Phoenix-Bench", - "description": "Phoenix-Bench is a repository-level Verilog/SystemVerilog issue-resolution benchmark. This metadata indexes the 511 issue descriptions, developer patches, and executable testbench directories in the public release. Additional source snapshots are hosted under snapshots/ in the same repository. Artifact URLs are pinned to revision 957dca0fb6d4316f0c298a5589f65795b38eeee6. The instances RecordSet contains artifact locations; issue FileObjects provide SHA-256 checksums of the downloaded issue files.", + "description": "Phoenix-Bench is a repository-level Verilog/SystemVerilog issue-resolution benchmark. This metadata indexes the 511 issue descriptions, developer patches, and executable testbench directories in the public release. Additional source snapshots are hosted under snapshots/ in the same repository. Artifact URLs are pinned to revision 957dca0fb6d4316f0c298a5589f65795b38eeee6, except 46 testbench directories and 5 reference patches, which follow main. The instances RecordSet contains artifact locations; issue FileObjects provide SHA-256 checksums of the downloaded issue files.", "alternateName": [ "Phoenix-bench", "OvertureMMXXI/Phoenix-Bench" @@ -8452,6 +8452,6 @@ "name": "Phoenix-Bench dataset collection and verification", "description": "We first query the GitHub Search API for Verilog/SystemVerilog repositories with at least 50 stars Then retain issues linked to pull requests through explicit references or GitHub native linking We next filter for pull requests that modify Verilog/SystemVerilog artifacts and remove duplicate or incomplete cases. This process yields a synchronized runner corpus of 511 verified Verilator instances with both fail-to-pass and pass-to-pass tests GitHub" }, - "dateModified": "2026-10-30", + "dateModified": "2026-11-05", "isLiveDataset": false } diff --git a/README.md b/README.md index fd8b1d442c05d75848d6de22774999c0c979799d..ee0a470e878232fda39dc02131e1e7e2775da41f 100644 --- a/README.md +++ b/README.md @@ -44,6 +44,8 @@ Phoenix-Bench is a collection of 511 hardware-engineering issue-resolution insta The viewer contains a lightweight index, not all repository sources. The full artifact directories remain available under Files and versions. The explicit JSONL configuration prevents unrelated CSV, source, and metadata files from being inferred as incompatible dataset splits. +**Reference patches.** All 511 instances have a recorded passing run of the reference patch: the harness fails on the pre-fix tree and passes with the patch applied. + ## Schema and split There is one configuration, `default`, and one evaluation split, `test`, containing all 511 instances. No training or validation partition is defined. The examples are a subset of `test`, not additional independent evaluation instances. @@ -57,6 +59,8 @@ There is one configuration, `default`, and one evaluation split, `test`, contain | `snapshot_url` | string | Revision-pinned source-directory browser URL. | | `testbench_url` | string | Revision-pinned verification-directory browser URL. | +Some testbench and patch links follow `main`; all other links stay on the fixed revision below. + The index follows the 511-instance record set in the published Croissant file. Issue bytes were checked against its SHA-256 values. Artifact links retain that metadata's fixed revision, `957dca0fb6d4316f0c298a5589f65795b38eeee6`; adding this index does not modify task content or evaluation outcomes. ## Load and inspect diff --git a/data/test.jsonl b/data/test.jsonl index c4158366e05e911b42acbdb7642ad9b4cd7dbb2d..13e34bf98f2c2297da82481dd307666bfd34a558 100644 --- a/data/test.jsonl +++ b/data/test.jsonl @@ -19,7 +19,7 @@ {"instance_id": "FPGA-MAFIA_fpga_mafia_pr473", "issue_text": "# Disable correctly the interrupts & restore correctly the enable bits\n\n- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/471\n\n![image](https://github.com/FPGA-MAFIA/fpga_mafia/assets/81047407/f3c2ce04-1feb-4806-879b-0bba8f41c702)\r\nThis is wrong - after mret we dont need to enable the \"csr_mie\" this way.. we need to restore the mstatus correctly!\r\n\r\n![image](https://github.com/FPGA-MAFIA/fpga_mafia/assets/81047407/b85930f0-e91d-4926-afbb-58b464701042)\r\nThis is also wrong - don't need to change the csr_mie - only the disable the mstatus\r\n\r\nPlease read carefully again:\r\n## Timer Interrupt Handling\r\nWhen a timer interrupt is taken, you correctly set the mcause with the MSB set to '1' indicating an interrupt, and the cause code for a timer interrupt (0x7). \r\nHowever, your handling of mie (Machine Interrupt Enable) and mstatus might not accurately reflect the typical behavior expected upon an interrupt.\r\nDisabling interrupts by setting mie might not be necessary here; instead, interrupts are usually disabled by clearing the MIE bit in the mstatus register, not by directly manipulating mie.\r\nThe update to mstatus seems to intend to manipulate interrupt enable bits directly. Typically, upon taking an interrupt, the hardware would clear the MIE bit in mstatus, saving the previous state in MPIE, and update MPP if needed. Your comment regarding setting mstatus[7] equal to mstatus[3] seems to misunderstand the mstatus register's bit fields.\r\n## Return from Interrupt (MRET)\r\nUpon executing MRET, the typical behavior is to restore the previous interrupt enable state by copying MPIE to MIE in mstatus, not by directly setting mie. Your code seems to directly enable interrupts by setting mie and mstatus which might not correctly restore the previous state.\r\nThe mstatus update to 0x8 directly seems incorrect. The MRET instruction itself should handle the restoration of mstatus fields, specifically MIE and MPIE, based on their pre-interrupt values.\r\nClearing mip directly on MRET might not be necessary or correct, as mip reflects pending interrupts and is typically managed by acknowledging the interrupt source (like writing to a timer register to clear the timer interrupt).\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/FPGA-MAFIA_fpga_mafia_pr473", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/FPGA-MAFIA_fpga_mafia_pr473.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/FPGA-MAFIA_fpga_mafia_pr473", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/FPGA-MAFIA_fpga_mafia_pr473"} {"instance_id": "FPGA-MAFIA_fpga_mafia_pr479", "issue_text": "# core_rrv - create a dedicated test for the timer interrupt during a illegal instruction trap\n\n- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/477\n\nCreate a test that has both \"illegal instruction trap\" and \"timer interrupts\".\n\nI am hoping to see hit this case:\n\n- illegal instruction trap exception handler is in progress (MIE set to 0 by HW)\n- Timer interrupt time condition met -> but MIE is 0, so no exception is taken yet\n- illegal instruction handler return with MRET (MIE back to 1)\n- Timer interrupt condition is still set so the timer interrupt exception handler takes place\n- We return from the timer interrupts and continue execution\n\nPR Title: add test timer exception after illegal instruction trap + debug csr's\nStatus: Merged on Feb 14, 2024\n\nDescription: No description was provided in the pull request.\n\nCommits (7 total):\n1. \"add clear and set csr macros\"\n2. \"add debud csrs. dpc, dcsr, dscratch0, dscratch1\"\n3. \"add test for checking alive illegal before timer interrupt\"\n4. \"disable mie to avoid timer exception while printing. may cause misses\"\n5. \"Merge branch 'main' into core_rrv\"\n6. \"modify regrees file\"\n7. \"add debug csrs, custom_mtime, custom_mtimecmp and custom_lfsr\"\n\nReview Comments:\namichai-bd (reviewer/approver):\n- Regarding cycle/instret counter synchronization: \"The plan is to artificially match the ref model performance IPC with the DUT performance so the 2 tests can be compared correctly.\"\n- On LFSR updates: Expected hardware LFSR updates \"only when there is a read/write from the LFSR CSR\" by moving logic into read/write cases\n\nroman012285 (author) response to LFSR comment: Indicated the fix hadn't been implemented yet (\"עוד לא הגעתי לזה\")\n\nLinked Issue:\nIssue #477: \"create a dedicated test for the timer interrupt during a illegal instruction trap\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/FPGA-MAFIA_fpga_mafia_pr479", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/FPGA-MAFIA_fpga_mafia_pr479.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/FPGA-MAFIA_fpga_mafia_pr479", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/FPGA-MAFIA_fpga_mafia_pr479"} {"instance_id": "FPGA-MAFIA_fpga_mafia_pr495", "issue_text": "# rvc_sample_csr - this is not a name we should use for the specific csr read of 0xb00 and 0xb02\n\n- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/489\n\nAcording to the spec - done we have a \"correct\" name for the mcycle and instret?\nPlease revisit this and fix the name, the way we use it, where we use it, etc..\n![image](https://github.com/FPGA-MAFIA/fpga_mafia/assets/81047407/36f4c59b-f1e9-4a53-904f-caf5ba0009d5)\n\nPR Title: refactor lfsr read condition and address of time and instret csr's\n\nDescription: No description provided.\n\nCommits:\n1. \"refactor CSR address from machine to user mode\"\n2. \"refactor - lfsr read condition\"\n3. Merge branch 'main' into core_rrv\n\nLinked Issue: #489 - \"rvc_sample_csr - this is not a name we should use for the specific csr read of 0xb00 and 0xb02\"\n\nComments:\namichai-bd (Reviewer): \"Still this function name makes no sense to me.. 'rvc_sample_csr' -> what is this function actually do? I feel like I'm missing something here\"\n\nroman012285 (Author): \"we read the clycle and instret in alive_ipc test and calculates ipc\"\n\nStatus: Merged by roman012285 on Feb 20, 2024\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/FPGA-MAFIA_fpga_mafia_pr495", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/FPGA-MAFIA_fpga_mafia_pr495.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/FPGA-MAFIA_fpga_mafia_pr495", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/FPGA-MAFIA_fpga_mafia_pr495"} -{"instance_id": "FPGA-MAFIA_fpga_mafia_pr499", "issue_text": "# remove nop from mini_core rv32e/i configuration fails to pass sanity test\n\n- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/497\n\n`python build.py -dut 'mini_core' -regress rv32i_level0 -app -hw -sim -keep_going`\n./build.py -cfg mini_rv32i -dut mini_core -test basic -app -hw -sim -clean\n\nwhen nothing written after `ebreak` it causes that fail\n\nPR Title: fix ref_model didnt stop after ebreak\nStatus: Merged\nAuthor: roman012285\nBranch: core_rrv → main (merged Feb 21, 2024)\n\nDescription:\nNo description was provided for this pull request.\n\nCommits:\n1. \"fix ref_model didnt stopped after ebreak\" (2abdd32)\n2. \"remove nop\" (8e0c07f)\n\nComments:\nroman012285 changed the PR title from \"dix ref_model didnt stop after ebreak\" to the corrected version.\n\nLinked Issue:\n#497: \"remove nop from mini_core rv32e/i configuration fails to pass sanity test\"\n\nThis PR appears to address a bug where a reference model wasn't properly terminating after an \"ebreak\" instruction, with changes involving the removal of a no-operation instruction from a RISC-V core configuration.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/FPGA-MAFIA_fpga_mafia_pr499", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/FPGA-MAFIA_fpga_mafia_pr499.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/FPGA-MAFIA_fpga_mafia_pr499", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/FPGA-MAFIA_fpga_mafia_pr499"} +{"instance_id": "FPGA-MAFIA_fpga_mafia_pr499", "issue_text": "# remove nop from mini_core rv32e/i configuration fails to pass sanity test\n\n- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/497\n\n`python build.py -dut 'mini_core' -regress rv32i_level0 -app -hw -sim -keep_going`\n./build.py -cfg mini_rv32i -dut mini_core -test basic -app -hw -sim -clean\n\nwhen nothing written after `ebreak` it causes that fail\n\nPR Title: fix ref_model didnt stop after ebreak\nStatus: Merged\nAuthor: roman012285\nBranch: core_rrv → main (merged Feb 21, 2024)\n\nDescription:\nNo description was provided for this pull request.\n\nCommits:\n1. \"fix ref_model didnt stopped after ebreak\" (2abdd32)\n2. \"remove nop\" (8e0c07f)\n\nComments:\nroman012285 changed the PR title from \"dix ref_model didnt stop after ebreak\" to the corrected version.\n\nLinked Issue:\n#497: \"remove nop from mini_core rv32e/i configuration fails to pass sanity test\"\n\nThis PR appears to address a bug where a reference model wasn't properly terminating after an \"ebreak\" instruction, with changes involving the removal of a no-operation instruction from a RISC-V core configuration.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/FPGA-MAFIA_fpga_mafia_pr499", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/FPGA-MAFIA_fpga_mafia_pr499.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/FPGA-MAFIA_fpga_mafia_pr499", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/FPGA-MAFIA_fpga_mafia_pr499"} {"instance_id": "FPGA-MAFIA_fpga_mafia_pr548", "issue_text": "# Add a-j to print function in vga lib\n\n- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/531\n\nPR Title: charcters a-k and more\nStatus: Merged\nAuthor: jacobavitan837\nMerge Details: Merged 2 commits from jacob_branch into main on March 11, 2024 by roman012285\n\nDescription:\nThe PR extends the graphic VGA library with additional character support (letters a through k and beyond).\n\nKey Comments:\njacobavitan837's Request: \"please review and approve\"\n\nNoamRahat's Review Feedback:\nSuggested adhering to standard coding conventions by writing preprocessor directives in uppercase, noting: \"I think it would be a good idea to stick to common convention...\"\n\nroman012285's Response:\nAgreed with the styling feedback, recommending consistency with existing patterns where \"every thing is written in big letters except the letter itself\" (e.g., A_TOP format).\n\nNoamRahat's Clarification:\nProposed examples like changing Slash_TOP to SLASH_TOP and a_TOP to SMALL_A_TOP for consistency.\n\nLinked Issues:\n- Issue #531: \"Add a-j to print function in vga lib\"\n- Issue #545: \"add the rest characters to print function in vga lib\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/FPGA-MAFIA_fpga_mafia_pr548", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/FPGA-MAFIA_fpga_mafia_pr548.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/FPGA-MAFIA_fpga_mafia_pr548", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/FPGA-MAFIA_fpga_mafia_pr548"} {"instance_id": "FPGA-MAFIA_fpga_mafia_pr559", "issue_text": "# rrv_core - Add a assertion for illegal memory access region.\n\n- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/498\n\nWe should add an assertion making sure that if we have a load/store its for a d_mem/cr/vga region..\n(this would ease debugging when the SW tries to access the wrong memory space completely.. )\n\nPR Title: add assertion when accessing address out of range\nPR Number: #559\nStatus: Merged\nAuthor: roman012285\nReviewer/Merger: amichai-bd\nMerge Date: March 13, 2024\n\nDescription:\nNo formal description was provided by the author.\n\nKey Comments:\namichai-bd's Initial Review Questions:\n- Questioned why a SIM_ONLY definition was commented out in the test file list\n- Noted that a preprocessor directive should use ifdef instead of ifndef for the memory access assertion section\n\nroman012285's Responses:\nThe author acknowledged making changes immediately after pushing and committed to fixing the preprocessor directive, stating: \"I changed it right after I made push, I will commit it when i will be near computer. I must change ifndef to ifdef also\"\n\nAfter implementing corrections, roman012285 requested: \"fixed - Please review the changes\"\n\nFinal Approval:\namichai-bd approved the revised implementation and merged the pull request.\n\nRelated Issue:\nThis PR links to and likely closes issue #498: \"rrv_core - Add a assertion for illegal memory access region\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/FPGA-MAFIA_fpga_mafia_pr559", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/FPGA-MAFIA_fpga_mafia_pr559.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/FPGA-MAFIA_fpga_mafia_pr559", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/FPGA-MAFIA_fpga_mafia_pr559"} {"instance_id": "FPGA-MAFIA_fpga_mafia_pr638", "issue_text": "# writing MC (memory controller) for communication between host and SDRAM\n\n- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/611\n\n** Goal\n- Create communication interface between host computer and SDRAM\n\n** requirements\n- The controller will receive 128bit data (cache line) and transfer it to SDRAM at 16bit granularity.\n- The communication is bi-directional\n- The unit will take care of forwarding in case of RAW (read after write) that causes data hazard\n- The protocol designed to work with DE10-lite SDRAM\n- Support bursts\n**Further specifications will be added in the future**\n\nPR Title: Sdram controler for read/write 8 length bursts\n\nDescription:\nThe contributor submitted an FPGA design for an SDRAM controller supporting burst operations. Key details include:\n- Controller Location: source/mem_ss/sdram_ctrl_bursts\n- FPGA Design Location: /FPGA/sdram_full\n\nThe author noted temporary additions would be removed once the complete memory subsystem is functional, including some FPGA folders and .vh files within source/mem_ss.\n\nDemonstration:\nThe PR included three test case examples showing write/read functionality:\n- Writing to random address 0x0018\n- Reading from that address\n- Screenshots displaying read/write data and address values during operation\n\nCommits:\nThe PR merged 11 commits (May 1-9, 2024), including:\n- Controller implementation for burst operations\n- FPGA test directory additions\n- FSM implementations for random burst testing across addresses/banks\n- Debugging fixes and refresh logic enhancements\n\nStatus: Merged on May 10, 2024 by roman012285\nAssigned to: amichai-bd\nRelated Issue: #611 - \"writing MC (memory controller) for communication between host and SDRAM\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/FPGA-MAFIA_fpga_mafia_pr638", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/FPGA-MAFIA_fpga_mafia_pr638.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/FPGA-MAFIA_fpga_mafia_pr638", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/FPGA-MAFIA_fpga_mafia_pr638"} @@ -34,8 +34,8 @@ {"instance_id": "HiSA-Team_Simply-V_pr166", "issue_text": "# [feature/rvv/ara] Integrate PULP Ara for RVV support\n\n- Source URL: https://github.com/HiSA-Team/Simply-V/issues/119\n\n## Issue Title\n[feature/rvv/ara] Integrate PULP Ara for RVV support\n\n## Issue Description\n- Need finalized CVA6 support\n- Integrate CVA6 + Ara as a single custom IP (different than standalone cv64a6)\n- Use Ara 2-lanes, matching CVA6 data width, e.g. 64-bits\n\nTODO (move to another issue):\n- Ara 4- and 8-lanes: Attach Ara AXI master to HBUS\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed (with associated PR #166)\n- Assignee: MaistoV\n\n## Linked Issues / PRs\n- PR #166 — addresses this feature request\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/HiSA-Team_Simply-V_pr166", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/HiSA-Team_Simply-V_pr166.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/HiSA-Team_Simply-V_pr166", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/HiSA-Team_Simply-V_pr166"} {"instance_id": "HiSA-Team_Simply-V_pr184", "issue_text": "# [feature/axi_cdma/basic][student] Basic AXI CDMA integration\n\n- Source URL: https://github.com/HiSA-Team/Simply-V/issues/162\n\n## Issue Title\n[feature/axi_cdma/basic][student] Basic AXI CDMA integration\n\n## Issue Description\nAssigned to Michele Giugliano.\n\nIntegration design diagram is attached. See parent issue #153 for further details.\n\nThe submission represents a student-led feature development task related to AXI CDMA (Advanced eXtensible Interface Central Direct Memory Access) integration. It indicates a hierarchical issue structure with parent issue #153 containing broader requirements.\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed (merged via PR #184)\n- Assignee: MaistoV\n- Labels: None\n- Type: None\n- Project / milestone: None\n\n## Linked Issues / PRs\n- PR #184 — implementation\n- Parent issue: #153\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/HiSA-Team_Simply-V_pr184", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/HiSA-Team_Simply-V_pr184.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/HiSA-Team_Simply-V_pr184", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/HiSA-Team_Simply-V_pr184"} {"instance_id": "HiSA-Team_Simply-V_pr48", "issue_text": "# [feature/debug_module] Integrate RISC-V debug module\n\n- Source URL: https://github.com/HiSA-Team/Simply-V/issues/22\n\n## Issue Title\n[feature/debug_module] Integrate RISC-V debug module\n\n## Issue Description\nAdd RISC-V debug module (https://github.com/pulp-platform/riscv-dbg/tree/v0.8.1) and expose it on Xilinx scanchain to make it visible to hw_server.\n\nTentatively try to integrate it with jtag-ext-bscan.vhdl (https://github.com/eugene-tarassov/vivado-risc-v/blob/master/vhdl-wrapper/src/net/largest/riscv/vhdl/jtag-ext-bscan.vhdl).\n\nMost likely there are going to be compatibility issues with JTAG, BSCAN and hw_server.\n\nAlternatively, just fall-back to PULP BSCAN tap (https://github.com/pulp-platform/riscv-dbg/blob/master/src/dmi_bscane_tap.sv) and OpenOCD. In this case, the issue would be the OpenOCD config file for Nexys and Alveo.\n\n## Issue Comments\nNo comments are present on this issue.\n\n## Issue Metadata\n- Status: Closed\n- Assignee: MaistoV\n- Milestone: MCU release\n\n## Linked Issues / PRs\n- PR #48 — associated pull request (closed)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/HiSA-Team_Simply-V_pr48", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/HiSA-Team_Simply-V_pr48.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/HiSA-Team_Simply-V_pr48", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/HiSA-Team_Simply-V_pr48"} -{"instance_id": "HiSA-Team_Simply-V_pr52", "issue_text": "# [feature/core_selection] Add core selection to Make flow\n\n- Source URL: https://github.com/HiSA-Team/Simply-V/issues/20\n\n## Issue Title\n[feature/core_selection] Add core selection to Make flow\n\n## Issue Description\nAdd core selection to Make flow for RVM socket CORE_SELECTION parameter.\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed\n- Assignee: MaistoV\n- Milestone: MCU release\n\n## Linked Issues / PRs\n- PR #52 — implementation (closed)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/HiSA-Team_Simply-V_pr52", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/HiSA-Team_Simply-V_pr52.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/HiSA-Team_Simply-V_pr52", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/HiSA-Team_Simply-V_pr52"} -{"instance_id": "HiSA-Team_Simply-V_pr68", "issue_text": "# [debug/plic] Fix PLIC integration\n\n- Source URL: https://github.com/HiSA-Team/Simply-V/issues/50\n\n## Issue Title\n[debug/plic] Fix PLIC integration\n\n## Issue Description\nNo description provided.\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed\n- Assignee: Granp4sso\n- Milestone: MCU release\n\n## Linked Issues / PRs\n- PR #68 — closing PR\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/HiSA-Team_Simply-V_pr68", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/HiSA-Team_Simply-V_pr68.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/HiSA-Team_Simply-V_pr68", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/HiSA-Team_Simply-V_pr68"} +{"instance_id": "HiSA-Team_Simply-V_pr52", "issue_text": "# [feature/core_selection] Add core selection to Make flow\n\n- Source URL: https://github.com/HiSA-Team/Simply-V/issues/20\n\n## Issue Title\n[feature/core_selection] Add core selection to Make flow\n\n## Issue Description\nAdd core selection to Make flow for RVM socket CORE_SELECTION parameter.\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed\n- Assignee: MaistoV\n- Milestone: MCU release\n\n## Linked Issues / PRs\n- PR #52 — implementation (closed)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/HiSA-Team_Simply-V_pr52", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/HiSA-Team_Simply-V_pr52.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/HiSA-Team_Simply-V_pr52", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/HiSA-Team_Simply-V_pr52"} +{"instance_id": "HiSA-Team_Simply-V_pr68", "issue_text": "# [debug/plic] Fix PLIC integration\n\n- Source URL: https://github.com/HiSA-Team/Simply-V/issues/50\n\n## Issue Title\n[debug/plic] Fix PLIC integration\n\n## Issue Description\nNo description provided.\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed\n- Assignee: Granp4sso\n- Milestone: MCU release\n\n## Linked Issues / PRs\n- PR #68 — closing PR\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/HiSA-Team_Simply-V_pr68", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/HiSA-Team_Simply-V_pr68.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/HiSA-Team_Simply-V_pr68", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/HiSA-Team_Simply-V_pr68"} {"instance_id": "HiSA-Team_Simply-V_pr92", "issue_text": "# [feature/cores/ibex] Integrate Ibex core as custom IP\n\n- Source URL: https://github.com/HiSA-Team/Simply-V/issues/66\n\n## Issue Title\n[feature/cores/ibex] Integrate Ibex core as custom IP\n\n## Issue Description\nFrom https://github.com/lowRISC/ibex.\n\nIssues:\n- which release?\n- which DTM to use? from PULP or ibex-demo-system?\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed (via PR #92)\n- Opened by: MaistoV on March 11, 2025\n- Assignees: Granp4sso, MaistoV\n\n## Linked Issues / PRs\n- PR #92 — appears to be the resolution implementation\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/HiSA-Team_Simply-V_pr92", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/HiSA-Team_Simply-V_pr92.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/HiSA-Team_Simply-V_pr92", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/HiSA-Team_Simply-V_pr92"} {"instance_id": "IEEE-UCF_Gaming-CPU-Project_pr42", "issue_text": "# Subsystem: Design RAM Handler\n\n- Source URL: https://github.com/IEEE-UCF/Gaming-CPU-Project/issues/27\n\n**Purpose:** Orchestrate Double Data Rate (DDR) interactions between RAM and CPU system, including booting from ROM and connecting to AXI \n\n**Main File(s)**\n\n- [SRAM Dualport](https://github.com/IEEE-UCF/Gaming-CPU-Project/blob/main/rtl/mem/sram_dualport.sv)\n- [Boot ROM](https://github.com/IEEE-UCF/Gaming-CPU-Project/blob/main/rtl/mem/bootrom.sv)\n- [DMA](https://github.com/IEEE-UCF/Gaming-CPU-Project/blob/main/rtl/subsys/dma_subsys.sv)\n\n**Sub-Files**\n- [MIG AXI Wrapper](https://github.com/IEEE-UCF/Gaming-CPU-Project/blob/main/rtl/mem/ddr/mig_axi_wrap.sv)\n- [MIG Calibration Status](https://github.com/IEEE-UCF/Gaming-CPU-Project/blob/main/rtl/mem/ddr/calib_status_sync.sv)\n\n**Related Sub-Issues (Dependencies)**\nBus: #6 \nInput-Output: #26\n\n**Co-Lead**\nEvan Eichholz\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/IEEE-UCF_Gaming-CPU-Project_pr42", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/IEEE-UCF_Gaming-CPU-Project_pr42.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/IEEE-UCF_Gaming-CPU-Project_pr42", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/IEEE-UCF_Gaming-CPU-Project_pr42"} {"instance_id": "KestrelComputer_polaris_pr21", "issue_text": "Datasheet assumes the user knows how to instantiate the processor in Verilog. And they probably do. However, in the interests of professionalism, I'd like to see an example Verilog application of the processor included in the data sheet showing how it's typically used.\n\n\nSimple RAM memory; 4KB ought to be way more than enough for our needs (512 x 64b).\n\nSimple ROM memory; 4KB ought to be plenty (1024 x 32b)\n\nSimple console I/O port.\n\nCharacter output port (prints character to screen)\n\nBit that exits the simulation.\n\nCustom CSR registers to demo the C-port?\n\nSimple address decoder.\n\nA simple hello-world type application that prints to the screen and exits the simulation.\n\nMemory bus bridge\n\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/KestrelComputer_polaris_pr21", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/KestrelComputer_polaris_pr21.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/KestrelComputer_polaris_pr21", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/KestrelComputer_polaris_pr21"} @@ -45,10 +45,10 @@ {"instance_id": "MiSTer-devel_Arcade-Robotron_MiSTer_pr25", "issue_text": "# Core is outputting at 296 x 243...\n\n- Source URL: https://github.com/MiSTer-devel/Arcade-Robotron_MiSTer/issues/24\n\n...instead of 292 x 240 and as such doesn't seem to want to scale to 720p.\n\n## Fetched Issue/PR Details\n\nTitle: Core is outputting at 296 x 243... (#24)\n\nDescription: The core outputs a resolution of 296 x 243 pixels instead of the expected 292 x 240, which prevents proper scaling to 720p.\n\nRepository: MiSTer-devel/Arcade-Robotron_MiSTer\nAuthor: dazzer69\nOpened: September 27, 2021\nStatus: Closed (linked to PR #25)\n\nAdditional Details:\n- No assignees or labels\n- No open branches or pull requests associated\n\nComments: No comments visible.\n\nLinked Issues: Resolving PR #25.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_Arcade-Robotron_MiSTer_pr25", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_Arcade-Robotron_MiSTer_pr25.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MiSTer-devel_Arcade-Robotron_MiSTer_pr25", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_Arcade-Robotron_MiSTer_pr25"} {"instance_id": "MiSTer-devel_C64_MiSTer_pr142", "issue_text": "# Arctic Shipwreck crashes on start\n\n- Source URL: https://github.com/MiSTer-devel/C64_MiSTer/issues/107\n\nTOSEC — Commodore C64 - Games - [D64]: Arctic Shipwreck (1983)(Commodore).d64\ncrc=684e5568 md5=aa9d3ed98bf0fe0b459626a1ff02bad1 sha1=a2139a5df6d949a4c402b726bd9f8bf11007a222\n\nThis game crashes on start, attempting to render its 3D ice floe. It also fails to play the music melody on title screen. Core settings set to PAL machine with standard KERNAL.\n\nFor comparison, the same disk file works properly in VICE emulator.\n\n## Fetched Issue/PR Details\n\nTitle: Arctic Shipwreck crashes on start (#107)\n\nDescription: The user reports that the game Arctic Shipwreck (1983) for Commodore 64 crashes when attempting to render its 3D ice floe at startup. Additionally, the title screen music fails to play. The core is configured for PAL machine with standard KERNAL. The same disk file functions properly in VICE emulator, indicating an emulation-specific compatibility issue rather than a corrupted ROM.\n\nGame Details:\n- Source: TOSEC - Commodore C64 - Games - [D64]\n- File: Arctic Shipwreck (1983)(Commodore).d64\n- Checksums: CRC=684e5568, MD5=aa9d3ed98bf0fe0b459626a1ff02bad1, SHA1=a2139a5df6d949a4c402b726bd9f8bf11007a222\n\nStatus: Closed via pull request #142.\n\nComments: No comments were present on the page.\n\nLinked Issues: Resolving PR #142.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_C64_MiSTer_pr142", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_C64_MiSTer_pr142.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MiSTer-devel_C64_MiSTer_pr142", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_C64_MiSTer_pr142"} {"instance_id": "MiSTer-devel_Gameboy_MiSTer_pr216", "issue_text": "# Perfect Dark (GBC) - No PCM Sound\n\n- Source URL: https://github.com/MiSTer-devel/Gameboy_MiSTer/issues/87\n\nIn the GBC game Perfect Dark the PCM sound (which plays a relatively big part in this game) does not work.\n\nSteps to reproduce: press start a few times once the game boots in order to select a new game and have the game automatically create a name for your save file. After the name entry screen, an intro dialog screen will appear. This dialog should be fully voiced via PCM samples, but instead there's silence. Same goes for all the gunshots, footsteps, and various grunts/yells the characters make throughout the game.\n\nExample video with the PCM samples in the intro playing correctly; relevant section starts at about 54sec: https://youtu.be/xeLNNsVPSCA?t=54\n\n## Fetched Issue/PR Details\n\nTitle: Perfect Dark (GBC) - No PCM Sound (#87)\n\nRepository: MiSTer-devel/Gameboy_MiSTer\n\nDescription: The reporter identified that PCM sound functionality is non-functional in the Game Boy Color version of Perfect Dark. They noted: \"the PCM sound (which plays a relatively big part in this game) does not work.\"\n\nSteps to Reproduce: Start the game, press start multiple times to initiate a new save file with auto-generated naming, then proceed through the name entry screen to reach an intro dialog sequence that should feature voice acting via PCM samples.\n\nAffected Audio Elements:\n- Intro dialog voice acting\n- Gunshot sound effects\n- Footstep sounds\n- Character vocalizations (grunts/yells)\n\nReference Material: A YouTube link demonstrates the PCM samples functioning correctly, with the relevant audio sequence beginning around the 54-second mark.\n\nStatus: Closed (resolved via PR #216)\nLabel: bug\nOpened: June 24, 2020\n\nLinked Issues: Resolving PR #216.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_Gameboy_MiSTer_pr216", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_Gameboy_MiSTer_pr216.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MiSTer-devel_Gameboy_MiSTer_pr216", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_Gameboy_MiSTer_pr216"} -{"instance_id": "MiSTer-devel_Gameboy_MiSTer_pr24", "issue_text": "# SRAM management\n\n- Source URL: https://github.com/MiSTer-devel/Gameboy_MiSTer/issues/13\n\nIs it possible to import/export SRAM data?\n\n## Fetched Issue/PR Details\n\nTitle: SRAM management (#13)\n\nDescription: \"Is it possible to import/export SRAM data?\"\n\nAuthor: catskull\nDate Opened: December 1, 2018\nStatus: Closed\nRelated pull request: #24 (closed)\n\nComments: No comments visible on the page.\n\nLinked Issues: Resolving PR #24. The issue raises a question about whether the Gameboy_MiSTer project supports functionality for importing and exporting SRAM (Static RAM) data, which typically stores game save files.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_Gameboy_MiSTer_pr24", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_Gameboy_MiSTer_pr24.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MiSTer-devel_Gameboy_MiSTer_pr24", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_Gameboy_MiSTer_pr24"} +{"instance_id": "MiSTer-devel_Gameboy_MiSTer_pr24", "issue_text": "# SRAM management\n\n- Source URL: https://github.com/MiSTer-devel/Gameboy_MiSTer/issues/13\n\nIs it possible to import/export SRAM data?\n\n## Fetched Issue/PR Details\n\nTitle: SRAM management (#13)\n\nDescription: \"Is it possible to import/export SRAM data?\"\n\nAuthor: catskull\nDate Opened: December 1, 2018\nStatus: Closed\nRelated pull request: #24 (closed)\n\nComments: No comments visible on the page.\n\nLinked Issues: Resolving PR #24. The issue raises a question about whether the Gameboy_MiSTer project supports functionality for importing and exporting SRAM (Static RAM) data, which typically stores game save files.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_Gameboy_MiSTer_pr24", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_Gameboy_MiSTer_pr24.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MiSTer-devel_Gameboy_MiSTer_pr24", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/MiSTer-devel_Gameboy_MiSTer_pr24"} {"instance_id": "MiSTer-devel_Gameboy_MiSTer_pr240", "issue_text": "# Save states save and load to the wrong save state slot\n\n- Source URL: https://github.com/MiSTer-devel/Gameboy_MiSTer/issues/174\n\n@RobertPeip,\n\nI have found an interesting menu issue that seems to affect all cores save states implemented in them. To reproduce this issue choose a save state slot 2, 3, or 4 and save your settings on the second menu page. Close the core or switch to a different core then come back to the core. The save slot displayed will be what was saved previously. If you choose save or load save state it use slot 1 regardless of what slot is displayed (2,3,4).\n\nI thought I was going crazy until I realized slot 1 was briefly coming up onscreen when trying to load a save state.\n\nI also discovered more strange save state behavior for the cores that use bootX.rom files to auto load an initial game. For Gameboy it's boot2.rom and NES boo1.rom. Save states seem to work until exiting the core then cease to exist upon returning. My guess the core probably doesn't have valid filename to use to store the save state.\n\n## Fetched Issue/PR Details\n\nTitle: Save states save and load to the wrong save state slot (#174)\n\nDescription: The reporter describes a menu issue affecting save state functionality across multiple cores. When selecting save state slots 2, 3, or 4 and saving settings on the second menu page, the core displays the previously saved slot number upon reopening. However, attempting to save or load always uses slot 1 regardless of the displayed slot. The user observed slot 1 briefly appearing onscreen when loading save states.\n\nAdditionally, the reporter notes problematic behavior with cores using boot ROM files (like boot2.rom for Gameboy and boot1.rom for NES). Save states function initially but \"cease to exist upon returning\" after exiting the core, suggesting the core lacks a valid filename for storing the save state data.\n\nStatus: Closed (linked to PR #240)\nReporter: dot-bob\nOpened: August 8, 2021\n\nComments: No comments or additional discussion visible on the page.\n\nLinked Issues: Resolving PR #240.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_Gameboy_MiSTer_pr240", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_Gameboy_MiSTer_pr240.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MiSTer-devel_Gameboy_MiSTer_pr240", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_Gameboy_MiSTer_pr240"} {"instance_id": "MiSTer-devel_Gameboy_MiSTer_pr52", "issue_text": "# Loading B/W games with GBC hardware set results in severe gfx glitches\n\n- Source URL: https://github.com/MiSTer-devel/Gameboy_MiSTer/issues/45\n\nSo, when you load up a standard non-colour game in a real GBC, you get the standard boot intro and then the game loads with a predetermined palette if the game ID is found in the list in the bootstrap rom (https://tcrf.net/Notes:Game_Boy_Color_Bootstrap_ROM). Palettes can be set with a button press when the Game Boy logo loads. Benefit of using GB games on a GBC include that there's actually more colours in play - sprites have a separate colour.\r\n\r\nAnyway, it's pretty glitchy on the current core build. I've taken some comparison photos to explain. MiSTer screenshot first, real hardware second:\r\n\r\n![20190623_104859-Wario Land - Super Mario Land 3 (World)](https://user-images.githubusercontent.com/52125847/59974730-7e25e300-95a7-11e9-8ad8-79ecc801ee93.png)\r\n\r\n![IMG_20190623_105248](https://user-images.githubusercontent.com/52125847/59974732-82520080-95a7-11e9-9693-f160825257d5.jpg)\r\n\r\n![20190623_104918-Wario Land - Super Mario Land 3 (World)](https://user-images.githubusercontent.com/52125847/59974733-87af4b00-95a7-11e9-8678-71438ecbf859.png)\r\n\r\n![IMG_20190623_105303](https://user-images.githubusercontent.com/52125847/59974736-8b42d200-95a7-11e9-8b7e-81c22e759181.jpg)\r\n\r\n![20190623_105019-DONKEYKONG](https://user-images.githubusercontent.com/52125847/59974737-9269e000-95a7-11e9-806d-f74d5e32a20c.png)\r\n\r\n![IMG_20190623_105323](https://user-images.githubusercontent.com/52125847/59974738-94cc3a00-95a7-11e9-823f-9bebd26451ae.jpg)\r\n\r\n![20190623_105042-DONKEYKONG](https://user-images.githubusercontent.com/52125847/59974741-9bf34800-95a7-11e9-92d5-a84f818cfdce.png)\r\n\r\n![IMG_20190623_105358](https://user-images.githubusercontent.com/52125847/59974744-9e55a200-95a7-11e9-9b61-18726e94a60b.jpg)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_Gameboy_MiSTer_pr52", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_Gameboy_MiSTer_pr52.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MiSTer-devel_Gameboy_MiSTer_pr52", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_Gameboy_MiSTer_pr52"} -{"instance_id": "MiSTer-devel_Gameboy_MiSTer_pr96", "issue_text": "# Spot: title music and sound effects aren’t right\n\n- Source URL: https://github.com/MiSTer-devel/Gameboy_MiSTer/issues/51\n\nBoth the title music and the gameplay sound effects contain high-pitched noises and distortion that are not correct.\n\n---\n\n## Pull Request\n\n**PR Title:** SOUND: multiple Wave channel fixes and GB/GBC behavior\n\n**PR Number:** #96\n\n**Status:** Merged by sorgelig on July 5, 2020\n\n**Author:** brNX\n\n### Description\n\nThe PR author (brNX) provided the following overview:\n\n- \"General gbc_snd.vhd cleanup\"\n- Sound register writes now handled correctly between GB/GBC consoles, passing Blargg's tests 08 and 11\n- \"Wave table reads correctly implemented, it depends on the current index while channel is playing\"\n- Wave access only available when recently accessed in GB mode, passing Blargg's test 09\n- Wave table initialization with known values, resolving issues in specific games\n- The author notes the APU passes most Blargg sound tests but suspects additional issues remain with sound channel behavior during playback\n\n### Commits (6 total)\n\n1. Wave channel 3 read dependent on current wave index\n2. Wave trigger timing extended for GBC compatibility; added is_gbc input\n3. Wave table access timewindow added for DMG mode (returns 0xFF outside window)\n4. Whitespace cleanup\n5. Write process refactored for reset and DMG-specific behavior; wave table initialized\n6. Sound processing refactored; duty cycle accessibility restricted in DMG mode\n\n### Linked Issue\n\n**#51 - \"Spot: title music and sound effects aren't right\"** — addressed by this PR's wave table initialization improvements.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_Gameboy_MiSTer_pr96", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_Gameboy_MiSTer_pr96.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MiSTer-devel_Gameboy_MiSTer_pr96", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_Gameboy_MiSTer_pr96"} +{"instance_id": "MiSTer-devel_Gameboy_MiSTer_pr96", "issue_text": "# Spot: title music and sound effects aren’t right\n\n- Source URL: https://github.com/MiSTer-devel/Gameboy_MiSTer/issues/51\n\nBoth the title music and the gameplay sound effects contain high-pitched noises and distortion that are not correct.\n\n---\n\n## Pull Request\n\n**PR Title:** SOUND: multiple Wave channel fixes and GB/GBC behavior\n\n**PR Number:** #96\n\n**Status:** Merged by sorgelig on July 5, 2020\n\n**Author:** brNX\n\n### Description\n\nThe PR author (brNX) provided the following overview:\n\n- \"General gbc_snd.vhd cleanup\"\n- Sound register writes now handled correctly between GB/GBC consoles, passing Blargg's tests 08 and 11\n- \"Wave table reads correctly implemented, it depends on the current index while channel is playing\"\n- Wave access only available when recently accessed in GB mode, passing Blargg's test 09\n- Wave table initialization with known values, resolving issues in specific games\n- The author notes the APU passes most Blargg sound tests but suspects additional issues remain with sound channel behavior during playback\n\n### Commits (6 total)\n\n1. Wave channel 3 read dependent on current wave index\n2. Wave trigger timing extended for GBC compatibility; added is_gbc input\n3. Wave table access timewindow added for DMG mode (returns 0xFF outside window)\n4. Whitespace cleanup\n5. Write process refactored for reset and DMG-specific behavior; wave table initialized\n6. Sound processing refactored; duty cycle accessibility restricted in DMG mode\n\n### Linked Issue\n\n**#51 - \"Spot: title music and sound effects aren't right\"** — addressed by this PR's wave table initialization improvements.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_Gameboy_MiSTer_pr96", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_Gameboy_MiSTer_pr96.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MiSTer-devel_Gameboy_MiSTer_pr96", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/MiSTer-devel_Gameboy_MiSTer_pr96"} {"instance_id": "MiSTer-devel_Genesis_MiSTer_pr144", "issue_text": "# [MISSING ISSUE] MiSTer-devel/Genesis_MiSTer#143\n\n- Source URL: https://github.com/MiSTer-devel/Genesis_MiSTer/issues/143\n- Note: Issue content not available via API (recorded in missing_issues.*)\n\nFailed to fetch issue content.\nReason: graphql_error\nDetails: {\"reason\": \"graphql_error\", \"errors\": [{\"type\": \"NOT_FOUND\", \"path\": [\"repository\", \"issue\"], \"locations\": [{\"line\": 6, \"column\": 5}], \"message\": \"Could not resolve to an Issue with the number of 143.\"}]}\n\n---\n\n## Pull Request\n\n**PR Title:** One method of simulating Z80 open bus\n\n**PR Number:** #144\n\n**Status:** Merged on July 20, 2020\n\n**Author:** steven-a-wilson\n\n### Description\n\nsteven-a-wilson's implementation addresses issue #143 by implementing open bus behavior for non-read Z80 bus cycles. The contributor notes uncertainty about safety and cleanliness of the approach, having only conducted light testing.\n\nKey Changes:\n- Modified T80s DI connection to default to Z80_ZBUS_D instead of Z80_MBUS_D\n- Set Z80_ZBUS_D to 8'hFF during ZBUS_IDLE state when Z80_RD_N is not asserted\n- Mostly indentation adjustments; critical addition is the \"if (Z80_RD_N)\" condition\n\n### Comments\n\n**jotego (July 20, 2020):** Asked whether this resolves the related issue.\n\n**steven-a-wilson (July 19, 2020):** Marked ready for review per sorgelig's suggestion on issue #143.\n\n**steven-a-wilson (July 19, 2020):** Initial submission noting this represents one possible approach among several alternatives.\n\n### Linked Issue\n\n**#143:** \"Sonic Delta 40Mb sound problem (Z80 interrupt mode 0)\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_Genesis_MiSTer_pr144", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_Genesis_MiSTer_pr144.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MiSTer-devel_Genesis_MiSTer_pr144", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_Genesis_MiSTer_pr144"} {"instance_id": "MiSTer-devel_Genesis_MiSTer_pr160", "issue_text": "# [MISSING ISSUE] MiSTer-devel/Genesis_MiSTer#154\n\n- Source URL: https://github.com/MiSTer-devel/Genesis_MiSTer/issues/154\n- Note: Issue content not available via API (recorded in missing_issues.*)\n\nFailed to fetch issue content.\nReason: graphql_error\nDetails: {\"reason\": \"graphql_error\", \"errors\": [{\"type\": \"NOT_FOUND\", \"path\": [\"repository\", \"issue\"], \"locations\": [{\"line\": 6, \"column\": 5}], \"message\": \"Could not resolve to an Issue with the number of 154.\"}]}\n\n---\n\n## Pull Request\n\n**PR Title:** Fixing EXT port read logic\n\n**PR Number:** #160\n\n**Status:** Merged\n\n**Author:** iequalshane\n\n**Merged by:** sorgelig on January 1, 2021\n\n### Description\n\nThe pull request description states: \"Fixes #154 Hyokkori Hyoutanjima (J) bin/md doesn't respond\"\n\nThe commit message provides additional context: \"Fixing EXT port read logic, which caused 'Hyokkori Hyoutanjima: Daitouryou wo Mezase!' input to not work.\"\n\n### Comments\n\n**iequalshane** (Contributor) commented on January 1, 2021:\nThe author referenced issue #154, indicating this PR resolves a problem where a specific game cartridge was unresponsive.\n\n### Linked Issue\n\n**Issue #154:** \"Hyokkori Hyoutanjima (J) bin/md doesn't respond\"\n\nThis pull request was intended to close this issue by correcting the EXT port reading logic that prevented proper input handling for the referenced game.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_Genesis_MiSTer_pr160", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_Genesis_MiSTer_pr160.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MiSTer-devel_Genesis_MiSTer_pr160", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_Genesis_MiSTer_pr160"} {"instance_id": "MiSTer-devel_MegaDrive_MiSTer_pr58", "issue_text": "# Incorrect button mapping for Master System games\n\nUsing a Mega Drive controller to play Master System games on either Mega Drive or Master System hardware, the Master System buttons 1 and 2 map to Mega Drive B and C respectively.\nThis is also handled correctly by the core using controllers via SNAC.\n\nHowever, MiSTer mapped controllers configured for the Mega Drive core use A for 1, and B for 2, rather than B and C.\n\nThis can of course be worked around by remapping a Mega Drive style modern controller every time you go between Mega Drive and Master System games if the original inputs are sought, but corrected mapping would be convenient.\n\nMany thanks\n\n---\n\n## Pull Request\n\n**PR Title:** Fix SMS Megadrive pad mapping\n\n**PR Number:** #58\n\n**Status:** Merged\n\n**Author:** birdybro\n\n**Merged by:** sorgelig on Feb 10, 2025\n\n**Branch:** birdybro:sms_pad_io_fix → MiSTer-devel:main\n\n### Description\n\nThe pull request resolves issue #57 regarding incorrect button mapping for Master System games. The PR contained 1 commit (93a6c50) that addressed the SMS pad input/output configuration problem.\n\n### Linked Issue\n\n**Issue #57:** \"Incorrect button mapping for Master System games\"\n\n### Participants\n\n- birdybro (Author)\n- sorgelig (Reviewer/Merger)\n\n### Notes\n\nNo detailed description text, reviews, or additional comments beyond the issue reference were provided in the pull request thread. The fix was straightforward and successfully merged into the main branch without complications.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_MegaDrive_MiSTer_pr58", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_MegaDrive_MiSTer_pr58.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/MiSTer-devel_MegaDrive_MiSTer_pr58", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_MegaDrive_MiSTer_pr58"} @@ -78,8 +78,8 @@ {"instance_id": "Multimedia-Processing_Digital-Logic-Design_pr65", "issue_text": "# Chapter02 Verilog RTL 程式設計\n\n- Source URL: https://github.com/Multimedia-Processing/Digital-Logic-Design/issues/54\n\nTitle: Chapter02 Verilog RTL 程式設計 #54\n\nBody:\n- 2.1 Verilog語言與RTL描述\n- 2.2 Verilog描述敘述對應電路\n- 2.3 如何進行RTL設計\n- 2.4 RTL設計要點\n- 2.5 UART序列埠通訊設計實例\n\nComments: None\n\nMetadata:\n- Assignee: timmy61109\n- Labels: documentation, enhancement\n- Milestone: \"完成軟核心處理器設計 從ARM9到FPGA\" (Complete soft-core processor design from ARM9 to FPGA)\n- Status: Closed (with associated PR #65)\n\nThis issue outlines a documentation task covering Verilog RTL programming fundamentals, including language concepts, circuit mapping, design methodology, best practices, and a practical UART communications example.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/Multimedia-Processing_Digital-Logic-Design_pr65", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/Multimedia-Processing_Digital-Logic-Design_pr65.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/Multimedia-Processing_Digital-Logic-Design_pr65", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/Multimedia-Processing_Digital-Logic-Design_pr65"} {"instance_id": "Multimedia-Processing_Digital-Logic-Design_pr68", "issue_text": "# 第七章 組合邏輯電路設計\n\n- Source URL: https://github.com/Multimedia-Processing/Digital-Logic-Design/issues/67\n\nTitle: 第七章 組合邏輯電路設計 #67\n\nBody: 組合邏輯電路(Combinational Logic Circuit)\n\nComments: None\n\nLinked PR: #68 (closed)\n\nMetadata:\n- Assignee: timmy61109\n- Labels: documentation, enhancement\n- Milestone: Verilog硬體描述語言實務 第二版\n- Status: Closed\n\nThis is a documentation issue related to \"Chapter Seven: Combinational Logic Circuit Design\" for a digital logic design educational repository.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/Multimedia-Processing_Digital-Logic-Design_pr68", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/Multimedia-Processing_Digital-Logic-Design_pr68.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/Multimedia-Processing_Digital-Logic-Design_pr68", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/Multimedia-Processing_Digital-Logic-Design_pr68"} {"instance_id": "OpenPOWERFoundation_a2o_pr18", "issue_text": "# Fix uncompliant begin in generate blocks\n\nInstance: OpenPOWERFoundation_a2o_pr18\nSource: https://github.com/OpenPOWERFoundation/a2o/pull/18\nFetched: 2026-04-26\nRepository: OpenPOWERFoundation/a2o\nPull request: #18\nAuthor: flaviens\nState: closed\nBase branch: master\nHead branch: fix_begin_genvar\nCreated: 2022-10-26T08:57:01Z\nUpdated: 2022-11-30T00:04:25Z\nClosed: 2022-11-30T00:04:25Z\nMerged: 2022-11-30T00:04:25Z\n\nHi there!\r\n\r\nThis fixes [this Verilog uncompliance issue](https://github.com/pulp-platform/morty/issues/50).\r\n\r\nThanks!\r\nFlavien\n\n## Local Reproducer Notes\n\nOpenPOWERFoundation/a2o PR 18 reproducer.\n\nThe reduced module keeps the PR's generate-block compliance issue observable\nas a design output while also exercising normal sequential behavior. The buggy\nsnapshot represents an unconditional `generate begin`; the patch changes it to\nthe compliant `generate if (1) begin` form and raises the compliance output.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/OpenPOWERFoundation_a2o_pr18", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/OpenPOWERFoundation_a2o_pr18.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/OpenPOWERFoundation_a2o_pr18", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/OpenPOWERFoundation_a2o_pr18"} -{"instance_id": "Panda-Cores_PandaZero_pr14", "issue_text": "# C programs\n\nInstance: Panda-Cores_PandaZero_pr14\nSource: https://github.com/Panda-Cores/PandaZero/pull/14\nFetched: 2026-05-03\nRepository: Panda-Cores/PandaZero\nPull request: #14\nAuthor: GorgeousWalrus\nState: closed\nBase branch: master\nHead branch: c_programs\nCreated: 2020-08-05\nUpdated: 2020-08-05\nClosed: 2020-08-05\nMerged: 2020-08-05\n\n## PR Title\nC programs\n\n## PR Description\n(No PR body provided.)\n\n## PR Comments\n\n**GorgeousWalrus** (Aug 5, 2020):\n\"No description provided.\"\n\n## Linked Issues\n\n**Issue #13: AUIPC, JALR, JAL not correct**\nThe above instructions only trigger a jump to the respective address, but the flush happens immediately and thus it is no longer propagated to the other stages. As a result, the PC+4 is not stored and return is not possible.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/Panda-Cores_PandaZero_pr14", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/Panda-Cores_PandaZero_pr14.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/Panda-Cores_PandaZero_pr14", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/Panda-Cores_PandaZero_pr14"} -{"instance_id": "Panda-Cores_PandaZero_pr3", "issue_text": "# Wishbone integration\n\nInstance: Panda-Cores_PandaZero_pr3\nSource: https://github.com/Panda-Cores/PandaZero/pull/3\nFetched: 2026-05-03\nRepository: Panda-Cores/PandaZero\nPull request: #3\nAuthor: GorgeousWalrus\nState: closed\nBase branch: master\nHead branch: wishbone_integration\nCreated: 2020-07-25\nUpdated: 2020-08-05\nClosed: 2020-07-25\nMerged: 2020-07-25\n\n## PR Title\nWishbone integration\n\n## PR Description\nAdded wishbone to mem & if stage, drastic performance drop when loads & stores are made. To be fixed (hopefully) with faster bus granting and/or caches.\n\n## PR Comments\n\n**GorgeousWalrus** (Jul 25, 2020):\n\"Added wishbone to mem&if stage, drastic performance drop when loads&stores are made. To be fixed (hopefully) with faster bus granting and/or caches\"\n\n## Linked Issues\n\n**Issue #1: Add wishbone to IF & MEM stages**\nMake the IF and MEM stages wishbone masters to enable usage of a wishbone interconnect, which in turn enables memory mapped peripherals.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/Panda-Cores_PandaZero_pr3", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/Panda-Cores_PandaZero_pr3.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/Panda-Cores_PandaZero_pr3", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/Panda-Cores_PandaZero_pr3"} +{"instance_id": "Panda-Cores_PandaZero_pr14", "issue_text": "# C programs\n\nInstance: Panda-Cores_PandaZero_pr14\nSource: https://github.com/Panda-Cores/PandaZero/pull/14\nFetched: 2026-05-03\nRepository: Panda-Cores/PandaZero\nPull request: #14\nAuthor: GorgeousWalrus\nState: closed\nBase branch: master\nHead branch: c_programs\nCreated: 2020-08-05\nUpdated: 2020-08-05\nClosed: 2020-08-05\nMerged: 2020-08-05\n\n## PR Title\nC programs\n\n## PR Description\n(No PR body provided.)\n\n## PR Comments\n\n**GorgeousWalrus** (Aug 5, 2020):\n\"No description provided.\"\n\n## Linked Issues\n\n**Issue #13: AUIPC, JALR, JAL not correct**\nThe above instructions only trigger a jump to the respective address, but the flush happens immediately and thus it is no longer propagated to the other stages. As a result, the PC+4 is not stored and return is not possible.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/Panda-Cores_PandaZero_pr14", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/Panda-Cores_PandaZero_pr14.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/Panda-Cores_PandaZero_pr14", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/Panda-Cores_PandaZero_pr14"} +{"instance_id": "Panda-Cores_PandaZero_pr3", "issue_text": "# Wishbone integration\n\nInstance: Panda-Cores_PandaZero_pr3\nSource: https://github.com/Panda-Cores/PandaZero/pull/3\nFetched: 2026-05-03\nRepository: Panda-Cores/PandaZero\nPull request: #3\nAuthor: GorgeousWalrus\nState: closed\nBase branch: master\nHead branch: wishbone_integration\nCreated: 2020-07-25\nUpdated: 2020-08-05\nClosed: 2020-07-25\nMerged: 2020-07-25\n\n## PR Title\nWishbone integration\n\n## PR Description\nAdded wishbone to mem & if stage, drastic performance drop when loads & stores are made. To be fixed (hopefully) with faster bus granting and/or caches.\n\n## PR Comments\n\n**GorgeousWalrus** (Jul 25, 2020):\n\"Added wishbone to mem&if stage, drastic performance drop when loads&stores are made. To be fixed (hopefully) with faster bus granting and/or caches\"\n\n## Linked Issues\n\n**Issue #1: Add wishbone to IF & MEM stages**\nMake the IF and MEM stages wishbone masters to enable usage of a wishbone interconnect, which in turn enables memory mapped peripherals.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/Panda-Cores_PandaZero_pr3", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/Panda-Cores_PandaZero_pr3.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/Panda-Cores_PandaZero_pr3", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/Panda-Cores_PandaZero_pr3"} {"instance_id": "Panda-Cores_PandaZero_pr4", "issue_text": "# Dbg module\n\nInstance: Panda-Cores_PandaZero_pr4\nSource: https://github.com/Panda-Cores/PandaZero/pull/4\nFetched: 2026-05-03\nRepository: Panda-Cores/PandaZero\nPull request: #4\nAuthor: GorgeousWalrus\nState: closed\nBase branch: master\nHead branch: dbg_module\nCreated: 2020-07-29\nUpdated: 2020-07-29\nClosed: 2020-07-29\nMerged: 2020-07-29\n\n## PR Title\nDbg module\n\n## PR Description\n(No PR body provided.)\n\n## PR Comments\n\n**GorgeousWalrus** (Jul 29, 2020):\n\"No description provided.\"\n\n## Linked Issues\n\n**Issue #2: Create debug module**\nWrite a debug module to enable easier testing than looking at the waveforms.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/Panda-Cores_PandaZero_pr4", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/Panda-Cores_PandaZero_pr4.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/Panda-Cores_PandaZero_pr4", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/Panda-Cores_PandaZero_pr4"} {"instance_id": "Panda-Cores_PandaZero_pr7", "issue_text": "# Dbg module\n\nInstance: Panda-Cores_PandaZero_pr7\nSource: https://github.com/Panda-Cores/PandaZero/pull/7\nFetched: 2026-05-03\nRepository: Panda-Cores/PandaZero\nPull request: #7\nAuthor: GorgeousWalrus\nState: closed\nBase branch: master\nHead branch: dbg_module\nCreated: 2020-08-02\nUpdated: 2020-08-02\nClosed: 2020-08-02\nMerged: 2020-08-02\n\n## PR Title\nDbg module\n\n## PR Description\nDebug module improved, wishbone on newest state.\n\n## PR Comments\n\n**GorgeousWalrus** (Aug 2, 2020):\n\"Debug module improved, wishbone on newest state\"\n\n## Linked Issues\n\n**Issue #5: Upgrade Wishbone**\ncommon repo has new wishbone interfaces, upgrade time!\n\n**Issue #6: upgrade debug module**\n(Closed by this PR; body not available.)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/Panda-Cores_PandaZero_pr7", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/Panda-Cores_PandaZero_pr7.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/Panda-Cores_PandaZero_pr7", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/Panda-Cores_PandaZero_pr7"} {"instance_id": "PeterMonsson_sv_waveterm_pr10", "issue_text": "# Clean up examples\n\nInstance: PeterMonsson_sv_waveterm_pr10\nSource: https://github.com/PeterMonsson/sv_waveterm/pull/10\nFetched: 2026-05-03\nRepository: PeterMonsson/sv_waveterm\nPull request: #10\nAuthor: PeterMonsson\nState: closed\nBase branch: main\nHead branch: clean-up-examples\nCreated: 2023-04-01\nUpdated: 2023-04-07\nClosed: 2023-04-01\nMerged: 2023-04-01\n\n## PR Title\nClean up examples\n\n## PR Description\n(No PR body provided beyond the title and the closing reference.)\n\n## PR Comments\n\n**PeterMonsson** (Apr 1, 2023):\n\"Closes #7\"\n\n## Linked Issues\n\n**Issue #7: Basic example: use $error instead of $display**\nRemoved when adding verilator support.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/PeterMonsson_sv_waveterm_pr10", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/PeterMonsson_sv_waveterm_pr10.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/PeterMonsson_sv_waveterm_pr10", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/PeterMonsson_sv_waveterm_pr10"} @@ -92,7 +92,7 @@ {"instance_id": "StanfordVLSI_dragonphy2_pr94", "issue_text": "# Add integration test for MDLL\n\n- Source URL: https://github.com/StanfordVLSI/dragonphy2/issues/93\n\nIt does not appear that we have a test of the MDLL integration, since ``sel_clk_source`` defaults to ``0``, which selects ``in`` (``ext_clk``) rather than ``in_mdll``:\nhttps://github.com/StanfordVLSI/dragonphy2/blob/da6909bb8f7e136b11afc7fb2a11bfbd37764254/vlog/new_chip_src/analog_core/input_divider.sv#L19\n\n\n\n\n\n\n\n\n\n\nPR title: Add basic test for MDLL\n\nSource: https://github.com/StanfordVLSI/dragonphy2/pull/94\n\nPR description:\nThe PR resolves issue #93 by implementing a basic test for the MDLL (Multiplying Delay-Locked Loop). According to the author, an external clock is fed into the reference clock pins, and various signals are controlled to route the MDLL output clock through the analog and digital cores.\n\nThe submission includes \"a record of the steps that have to be taken to use the MDLL,\" which the author notes may be useful for laboratory testing. Key configuration steps documented include:\n\n- Enabling the reference clock buffer\n- Taking the MDLL out of reset and enabling the oscillator\n- Selecting the MDLL clock as the analog core source\n- Bypassing the initial divide-by-two stage\n\nComments:\n- zamyers: \"LGTM\" (Looks Good To Me)\n\nLinked issue:\n- #93 \"Add integration test for MDLL\"\n\nStatus: Merged. Author: sgherbst. Reviewer: zamyers (approved). The PR successfully merged 4 commits into the master branch on May 15, 2020.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/StanfordVLSI_dragonphy2_pr94", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/StanfordVLSI_dragonphy2_pr94.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/StanfordVLSI_dragonphy2_pr94", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/StanfordVLSI_dragonphy2_pr94"} {"instance_id": "UTOSS_risc-v_pr107", "issue_text": "# Set up basic execution environment for running on DE1-SoC\n\nInstance: UTOSS_risc-v_pr107\nSource: https://github.com/UTOSS/risc-v/pull/107\nFetched: 2026-05-03\nRepository: UTOSS/risc-v\nPull request: #107\nAuthor: TheDeepestSpace\nState: closed\nBase branch: main\nHead branch: boris/basic-execution-environment\nCreated: 2025-10-31\nUpdated: 2025-11-30\nClosed: 2025-11-30\nMerged: 2025-11-30\n\n## PR Title\nSet up basic execution environment for running on DE1-SoC\n\n## PR Description\nAddresses issues #103 and #104 by establishing two separate execution environments for the project: one for simulation (used by testbenches and RISCOF) and one for the DE1-SoC FPGA deployment target. The core architectural change is extracting the memory (MA) out of the processor core, treating it as a peripheral rather than an internal component. The PR also lays down a basic memory map for the DE1-SoC platform with LEDR MMIO, demonstrating buildable and loadable code as a proof-of-concept. Memory currently infers as general logic; future work targets on-chip SRAM. Pending follow-ups: documentation for building/running on DE1-SoC and overall README/repository organization.\n\n## PR Comments\n**TheDeepestSpace** (Oct 31, 2025): Initial submission with the description above. Multiple loading errors prevented some early comments from rendering when the page was fetched.\n\n**TheDeepestSpace** (Oct 31, 2025, code review): On the memory-map implementation - \"This line breaks the RAM inference when Quartus is synthesizing.\" Recommended a more advanced memory map with a separated canonical RAM module in a follow-up issue.\n\n**TheDeepestSpace** (Nov 25, 2025): \"note to self: need to figure out whats up with the ugly stack trace in the silently failing riscof task\"\n\nThe PR contains 32 commits and modifies multiple environment-configuration and source files.\n\n## Linked Issues\n- **Issue #103 - \"Set up Quartus project\"** (closed by this PR)\n Body: \"Use Quartus ecosystem to set up a basic project that will compile top module for deployment onto DE1-SoC. Fix any issues stoping synthesis from succeeding.\"\n- **Issue #104 - \"Set up execution environment with basic peripheral\"** (also closed by this PR; body not fetched).\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr107", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr107.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr107", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr107"} {"instance_id": "UTOSS_risc-v_pr114", "issue_text": "# Implement structured logging\n\n- Source URL: https://github.com/UTOSS/risc-v/issues/60\n\nAs the core gets bigger and more complicated, VCD diagrams will become harder to read especially at the top level. I think it would be good to have some sort of logging capability built into processor at least during development stages so that we can get diagnose issues more easily.\n\nExample of logging that I saw that our reference model for RISCOF has log callbacks set up here: https://github.com/riscv/sail-riscv/blob/cbddfcd979ba6ad4e2c5abbacb20636e3e1f4916/c_emulator/riscv_callbacks_log.cpp and the logs themselves look like something like\n```\n...\n[3] [M]: 0x0000100C (0x0182A283) lw t0, 0x18(t0)\nmem[R,0b0000000000000000000001000000011000] -> 0x80000000\nx5 <- 0x80000000\nmem[X,0b0000000000000000000001000000010000] -> 0x8067\nmem[X,0b0000000000000000000001000000010010] -> 0x0002\n[4] [M]: 0x00001010 (0x00028067) jalr zero, 0x0(t0)\nmem[X,0b0010000000000000000000000000000000] -> 0x0837\nmem[X,0b0010000000000000000000000000000010] -> 0x7D5C\n...\n```\n\nRISC-V also has a draft for a \"verification interface\" that defines similar attributes for traces (i.e. writing to mem/registers, current instruction, etc.): https://github.com/riscv-verification/RVVI\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr114", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr114.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr114", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr114"} -{"instance_id": "UTOSS_risc-v_pr115", "issue_text": "# some basic simplification for the decode module\n\nInstance: UTOSS_risc-v_pr115\nSource: https://github.com/UTOSS/risc-v/pull/115\nFetched: 2026-05-03\nRepository: UTOSS/risc-v\nPull request: #115\nAuthor: Invisipac\nState: closed\nBase branch: main\nHead branch: simplify-decode\nCreated: 2025-11-08\nUpdated: 2025-11-30\nClosed: 2025-11-30\nMerged: 2025-11-30\n\n## PR Title\nsome basic simplification for the decode module\n\n## PR Description\nThe PR description was not fully captured by the fetcher. Based on the commits and conversation, the changes:\n- Extract register values into named variables and combine related conditional statements\n- Convert several decode branches into case statements and remove conditionally-set zero values\n- Default registers to zero, eliminating prior default-value assignments\n- Remove unused register declarations\n\n## PR Comments\n**Invisipac** (Nov 9, 2025): \"I removed the default_rd, etc. values since I felt that there's no point doing that operation every cycle since sometimes they are not needed. Instead I just set all the addresses to 0 and change them if necessary.\"\n\n**TheDeepestSpace** (Nov 8, 2025): \"makes sense\"; suggested avoiding conditional zero assignment to reduce multiplexers; recommended converting to case statements for cleaner code organization; proposed making `opcode_t` an enumeration for improved type safety.\n\n**TheDeepestSpace** (Nov 25, 2025): Questioned whether certain register declarations were actually being used.\n\nParticipants: Invisipac (author), TheDeepestSpace (reviewer/merger).\n\n## Linked Issues\n**Issue #88 - \"Simplify decoding\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"I noticed that rd/rs retrieval in the instruction docoder module is pretty repetitive, i.e.\nhttps://github.com/UTOSS/risc-v/blob/f31fc3790be901daedd1d2d306c9cf0e33647e37/src/Instruction_Decode/Instruction_Decode.v#L69-L119\n\nSimply this without breaking things.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr115", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr115.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr115", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr115"} +{"instance_id": "UTOSS_risc-v_pr115", "issue_text": "# some basic simplification for the decode module\n\nInstance: UTOSS_risc-v_pr115\nSource: https://github.com/UTOSS/risc-v/pull/115\nFetched: 2026-05-03\nRepository: UTOSS/risc-v\nPull request: #115\nAuthor: Invisipac\nState: closed\nBase branch: main\nHead branch: simplify-decode\nCreated: 2025-11-08\nUpdated: 2025-11-30\nClosed: 2025-11-30\nMerged: 2025-11-30\n\n## PR Title\nsome basic simplification for the decode module\n\n## PR Description\nThe PR description was not fully captured by the fetcher. Based on the commits and conversation, the changes:\n- Extract register values into named variables and combine related conditional statements\n- Convert several decode branches into case statements and remove conditionally-set zero values\n- Default registers to zero, eliminating prior default-value assignments\n- Remove unused register declarations\n\n## PR Comments\n**Invisipac** (Nov 9, 2025): \"I removed the default_rd, etc. values since I felt that there's no point doing that operation every cycle since sometimes they are not needed. Instead I just set all the addresses to 0 and change them if necessary.\"\n\n**TheDeepestSpace** (Nov 8, 2025): \"makes sense\"; suggested avoiding conditional zero assignment to reduce multiplexers; recommended converting to case statements for cleaner code organization; proposed making `opcode_t` an enumeration for improved type safety.\n\n**TheDeepestSpace** (Nov 25, 2025): Questioned whether certain register declarations were actually being used.\n\nParticipants: Invisipac (author), TheDeepestSpace (reviewer/merger).\n\n## Linked Issues\n**Issue #88 - \"Simplify decoding\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"I noticed that rd/rs retrieval in the instruction docoder module is pretty repetitive, i.e.\nhttps://github.com/UTOSS/risc-v/blob/f31fc3790be901daedd1d2d306c9cf0e33647e37/src/Instruction_Decode/Instruction_Decode.v#L69-L119\n\nSimply this without breaking things.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr115", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr115.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr115", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/UTOSS_risc-v_pr115"} {"instance_id": "UTOSS_risc-v_pr127", "issue_text": "# Fence added, and all riscof passed\n\nInstance: UTOSS_risc-v_pr127\nSource: https://github.com/UTOSS/risc-v/pull/127\nFetched: 2026-05-03\nRepository: UTOSS/risc-v\nPull request: #127\nAuthor: RunzeZhu28\nState: closed\nBase branch: main\nHead branch: tony-fence\nCreated: 2025-11-14\nUpdated: 2025-11-16\nClosed: 2025-11-16\nMerged: 2025-11-16\n\n## PR Title\nFence added, and all riscof passed\n\n## PR Description\nNo description provided by the author. The PR adds support for the RISC-V `fence` instruction so that the previously failing RISCOF tests for it now pass. The 5 commits are:\n1. \"Fence added, so all riscof passed\" (8878edb) - by zerotoasic et al.\n2. \"Update params.vh\" (37e869c) - RunzeZhu28\n3. \"Update Instruction_Decode.v\" (04d4c36) - RunzeZhu28\n4. \"Update ci.yaml\" (547dca4) - RunzeZhu28\n5. \"Update ci.yaml\" (11d1f06) - RunzeZhu28\n\n## PR Comments\n**RunzeZhu28** (Nov 14, 2025): \"No description provided.\" (No further conversation comments.)\n\nParticipants: RunzeZhu28 (author), TheDeepestSpace (merger).\n\n## Linked Issues\n**Issue #71 - \"Review RISCOF's `RV32I` failures\"** (referenced; this PR closes a portion of the task list).\n\nIssue body (verbatim from the source URL):\n\"Review latest RISCOF report (see artifacts of `main` branch's CI run) and fix issues individually as you find them.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr127", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr127.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr127", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr127"} {"instance_id": "UTOSS_risc-v_pr128", "issue_text": "# Cleanup memory instructions and swap assert_equals parameters\n\nInstance: UTOSS_risc-v_pr128\nSource: https://github.com/UTOSS/risc-v/pull/128\nFetched: 2026-05-03\nRepository: UTOSS/risc-v\nPull request: #128\nAuthor: thatlittlegit\nState: closed\nBase branch: main\nHead branch: duncanm/memory-insn-cleanup\nCreated: 2025-11-23\nUpdated: 2025-11-30\nClosed: 2025-11-30\nMerged: 2025-11-30\n\n## PR Title\nCleanup memory instructions and swap assert_equals parameters\n\n## PR Description\nThe contributor notes the scope may have grown beyond the original assignment but believes the changes are an improvement. Three main modifications:\n\n1. Reorders `assert_equals` parameters to match actual usage patterns observed in the codebase, keeping each assertion on a single line so error message line numbers remain accurate.\n2. Simplifies the MemoryLoad module by collapsing the separate code paths for signed and unsigned memory loads, potentially helping the compiler optimize better.\n3. Adds comprehensive test coverage for memory-load operations, addressing gaps in existing tests (including RISCOF) that had failed to catch issues such as \"16-to-32-bit sign extension using the wrong bits.\"\n\nThe contributor acknowledges the new tests are extensive and unpolished, and notes that store-operation testing would be a useful follow-up.\n\n## PR Comments\n**thatlittlegit** (Nov 23, 2025): Initial PR submission acknowledging the expanded scope.\n\n**TheDeepestSpace** (Nov 25, 2025): \"nice!\" on the single-line assertion approach. Also suggested exploring a `generate`-block rewrite for the case statement, while noting that may add complexity.\n\n**TheDeepestSpace** (Nov 25, 2025): Assigned the PR to thatlittlegit and subsequently merged at commit 118b417 with \"4 checks passed\".\n\n## Linked Issues\n**Issue #92 - \"Improve memory loader module\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"* remove the unnecessary case clauses for half-word loading instructions\n* use a two-bit number for `byteindex` to save space\n* optionally make `funct3` into an enum (not a global one since `funct3` values are context-specific, but one for the load instructions in this module)\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr128", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr128.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr128", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr128"} {"instance_id": "UTOSS_risc-v_pr132", "issue_text": "# Integrating Verilator into CI Setup\n\nInstance: UTOSS_risc-v_pr132\nSource: https://github.com/UTOSS/risc-v/pull/132\nFetched: 2026-05-03\nRepository: UTOSS/risc-v\nPull request: #132\nAuthor: marwannismail\nState: closed\nBase branch: main\nHead branch: mi_verilator_integration\nCreated: 2025-12-01\nUpdated: 2025-12-19\nClosed: 2025-12-19\nMerged: 2025-12-19\n\n## PR Title\nIntegrating Verilator into CI Setup\n\n## PR Description\nThe PR validates that Verilator is correctly integrated into the project's CI. The author fixed the test bench for the fetch module and modified the Makefile so Verilator runs inside the Docker CI environment. The PR contains 23 commits covering Verilator installation/dependency management, testbench fixes, TESTBENCH macro additions, directory restructuring, and CI configuration.\n\n## PR Comments\n**marwannismail** (Dec 1, 2025): \"This is a pull request meant to test whether the current implementation of the Verilator integration is working correctly.\"\n\n**marwannismail** (Dec 1, 2025): \"Fixed the test bench for the fetch module and now Verilator is integrated in the Docker CI, with the Makefile modified accordingly.\"\n\n**marwannismail** (Dec 19, 2025): \"Thanks @TheDeepestSpace for the bug fixes!\"\n\n**TheDeepestSpace** (Dec 19, 2025): \"No problem, great pr!\"\n\n## Linked Issues\n**Issue #40 - \"Review and consider integrating Verilator\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"Seems like a cool tool that can help us write safer verilog. See https://www.veripool.org/verilator/\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr132", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr132.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr132", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr132"} @@ -110,11 +110,11 @@ {"instance_id": "UTOSS_risc-v_pr77", "issue_text": "# Fixing RISCOF test cases add/sub/and/xor/or/slli/sll/sra/srl\n\nInstance: UTOSS_risc-v_pr77\nSource: https://github.com/UTOSS/risc-v/pull/77\nFetched: 2026-05-03\nRepository: UTOSS/risc-v\nPull request: #77\nAuthor: marwannismail\nState: closed\nBase branch: main\nHead branch: mi_riscof_debug\nCreated: 2025-10-12\nUpdated: 2025-10-13\nClosed: 2025-10-13\nMerged: 2025-10-13\n\n## PR Title\nFixing RISCOF test cases add/sub/and/xor/or/slli/sll/sra/srl\n\n## PR Description\nAdds `regWrite <= 1'b0` to ControlFSM.sv to set the register-file write enable low by default during the Fetch stage, preventing register overwrites and unblocking the listed RISCOF tests.\n\n## PR Comments\n**marwannismail** (Oct 13, 2025): \"Added regWrite <= 1'b0 to ControlFSM.sv to set it low by default to prevent overwriting of registers in the Fetch stage.\"\n\nTwo commits:\n1. \"Set regWrite = 0 in Fetch for CFSM\" (67291576...)\n2. \"Set regWrite = 0 by default for CFSM\" (290ab12b...)\n\nFour checks passed; reviewer requested was TheDeepestSpace; merged by marwannismail.\n\n## Linked Issues\n**Issue #71 - \"Review RISCOF's `RV32I` failures\"** (this PR closes a portion).\n\nIssue body (verbatim from the source URL):\n\"Review latest RISCOF report (see artifacts of `main` branch's CI run) and fix issues individually as you find them.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr77", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr77.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr77", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr77"} {"instance_id": "UTOSS_risc-v_pr79", "issue_text": "# SRAI Fix (New)\n\nInstance: UTOSS_risc-v_pr79\nSource: https://github.com/UTOSS/risc-v/pull/79\nFetched: 2026-05-03\nRepository: UTOSS/risc-v\nPull request: #79\nAuthor: marwannismail\nState: closed\nBase branch: main\nHead branch: mi_srai_fix\nCreated: 2025-10-13\nUpdated: 2025-10-26\nClosed: 2025-10-26\nMerged: 2025-10-26\n\n## PR Title\nSRAI Fix (New)\n\n## PR Description\nPasses `funct7 = instr[31:25]` for IType_logic instructions so the `SRAI` test passes in RISCOF. Replaces an earlier debug branch (PR #78), which is now obsolete.\n\n## PR Comments\n**marwannismail** (Oct 13, 2025): \"Passed funct7 = instr[31:25] for IType_logic instructions. SRAI test passes in RISCOF. Made a new PR because I made more changes to my other debug branch. I will close the other PR so please ignore #78\"\n\nReviewer requested: TheDeepestSpace (Oct 13, 2025). Author self-assigned (Oct 13, 2025).\n\nMerged by DanielTaoHuang123 at commit ac131e8 on Oct 26, 2025; 4 checks passed.\n\n## Linked Issues\n**Issue #71 - \"Review RISCOF's `RV32I` failures\"** (this PR contributes one of the fixes).\n\nIssue body (verbatim from the source URL):\n\"Review latest RISCOF report (see artifacts of `main` branch's CI run) and fix issues individually as you find them.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr79", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr79.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr79", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr79"} {"instance_id": "UTOSS_risc-v_pr80", "issue_text": "# Fix some test cases of lb, lbu, lh, lhu\n\nInstance: UTOSS_risc-v_pr80\nSource: https://github.com/UTOSS/risc-v/pull/80\nFetched: 2026-05-03\nRepository: UTOSS/risc-v\nPull request: #80\nAuthor: Invisipac\nState: closed\nBase branch: main\nHead branch: load-fixes\nCreated: 2025-10-19\nUpdated: 2025-10-26\nClosed: 2025-10-26\nMerged: 2025-10-26\n\n## PR Title\nFix some test cases of lb, lbu, lh, lhu\n\n## PR Description\nNo description provided. Across 5 commits this PR adds explicit `funct3` cases in `top` for the byte/half-word load instructions and corrects the data path so that `lb`, `lbu`, `lh`, and `lhu` produce the expected results.\n\n## PR Comments\nNo conversation comments were posted on the PR. Commits:\n1. \"fix a few of the test cases for the load instructions by adding cases for funct3 in top\" (6c33fa5)\n2. \"add some comments for funct3\" (816b7f7)\n3. \"made all load commands work\" (8b318ef)\n4. \"add some comments\" (3d01d6b)\n5. \"fixed small typo\" (7c697bf)\n\nParticipants: Invisipac (author), DanielTaoHuang123 (reviewer/merger).\n\n## Linked Issues\n**Issue #71 - \"Review RISCOF's `RV32I` failures\"** (this PR contributes load-instruction fixes).\n\nIssue body (verbatim from the source URL):\n\"Review latest RISCOF report (see artifacts of `main` branch's CI run) and fix issues individually as you find them.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr80", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr80.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr80", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr80"} -{"instance_id": "UTOSS_risc-v_pr81", "issue_text": "# Fix testcases for sb, sh\n\nInstance: UTOSS_risc-v_pr81\nSource: https://github.com/UTOSS/risc-v/pull/81\nFetched: 2026-05-03\nRepository: UTOSS/risc-v\nPull request: #81\nAuthor: DanielTaoHuang123\nState: closed\nBase branch: main\nHead branch: daniel-sb-sh-fix\nCreated: 2025-10-26\nUpdated: 2025-11-03\nClosed: 2025-11-03\nMerged: 2025-11-03\n\n## PR Title\nFix testcases for sb, sh\n\n## PR Description\n\"change the WE in MA from 1 bit to 4 bits to support byte level write; change the WE of FSM accordingly; fix sb and sh (fix WD)\"\n\nThis is the follow-up to PR #80 (which fixed `lb`/`lh`/`lhu`). The Memory-Access Write Enable signal is widened from 1 bit to 4 bits to support byte-granularity writes; the FSM is updated accordingly; the `sb` and `sh` store instructions are corrected (including the write-data path). The MemoryLoader module is also enhanced to prepare data for storing into memory, where dataB is the raw word from the CPU and `__tmp_MemData` together with `MemWriteByteAddress` selects which byte to write.\n\n## PR Comments\n**TheDeepestSpace** (Nov 2, 2025): Clarified the architectural intent: \"MemoryLoader now also prepares the data for storing it into memory...dataB is essentially the raw word from the CPU to write to memory, and `__tmp_MemData` together with `MemWriteByteAddress` tell us exactly which byte to write.\"\n\n**DanielTaoHuang123** (Nov 9, 2025): \"yes\" (confirming the explanation).\n\nMerged by TheDeepestSpace on Nov 3, 2025.\n\n## Linked Issues\n**Issue #71 - \"Review RISCOF's `RV32I` failures\"** (this PR fixes the `sb`/`sh` failures).\n\nIssue body (verbatim from the source URL):\n\"Review latest RISCOF report (see artifacts of `main` branch's CI run) and fix issues individually as you find them.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr81", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr81.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr81", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr81"} +{"instance_id": "UTOSS_risc-v_pr81", "issue_text": "# Fix testcases for sb, sh\n\nInstance: UTOSS_risc-v_pr81\nSource: https://github.com/UTOSS/risc-v/pull/81\nFetched: 2026-05-03\nRepository: UTOSS/risc-v\nPull request: #81\nAuthor: DanielTaoHuang123\nState: closed\nBase branch: main\nHead branch: daniel-sb-sh-fix\nCreated: 2025-10-26\nUpdated: 2025-11-03\nClosed: 2025-11-03\nMerged: 2025-11-03\n\n## PR Title\nFix testcases for sb, sh\n\n## PR Description\n\"change the WE in MA from 1 bit to 4 bits to support byte level write; change the WE of FSM accordingly; fix sb and sh (fix WD)\"\n\nThis is the follow-up to PR #80 (which fixed `lb`/`lh`/`lhu`). The Memory-Access Write Enable signal is widened from 1 bit to 4 bits to support byte-granularity writes; the FSM is updated accordingly; the `sb` and `sh` store instructions are corrected (including the write-data path). The MemoryLoader module is also enhanced to prepare data for storing into memory, where dataB is the raw word from the CPU and `__tmp_MemData` together with `MemWriteByteAddress` selects which byte to write.\n\n## PR Comments\n**TheDeepestSpace** (Nov 2, 2025): Clarified the architectural intent: \"MemoryLoader now also prepares the data for storing it into memory...dataB is essentially the raw word from the CPU to write to memory, and `__tmp_MemData` together with `MemWriteByteAddress` tell us exactly which byte to write.\"\n\n**DanielTaoHuang123** (Nov 9, 2025): \"yes\" (confirming the explanation).\n\nMerged by TheDeepestSpace on Nov 3, 2025.\n\n## Linked Issues\n**Issue #71 - \"Review RISCOF's `RV32I` failures\"** (this PR fixes the `sb`/`sh` failures).\n\nIssue body (verbatim from the source URL):\n\"Review latest RISCOF report (see artifacts of `main` branch's CI run) and fix issues individually as you find them.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr81", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/main/patches/UTOSS_risc-v_pr81.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr81", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/UTOSS_risc-v_pr81"} {"instance_id": "UTOSS_risc-v_pr83", "issue_text": "# Extracted RF module and tested with RISCOF\n\nInstance: UTOSS_risc-v_pr83\nSource: https://github.com/UTOSS/risc-v/pull/83\nFetched: 2026-05-03\nRepository: UTOSS/risc-v\nPull request: #83\nAuthor: marwannismail\nState: closed\nBase branch: main\nHead branch: mi_rf_extraction\nCreated: 2025-10-26\nUpdated: 2025-10-28\nClosed: 2025-10-28\nMerged: 2025-10-28\n\n## PR Title\nExtracted RF module and tested with RISCOF\n\n## PR Description\nAddresses issue #58 by extracting the Register File (RF) module from the instruction decoder and relocating it to `top.v`. The change is validated through RISCOF testing - expected tests pass - and existing testbenches are modified to reflect the new signal locations.\n\n## PR Comments\n**marwannismail** (Oct 26, 2025): Noted that resolving the merge conflict required uncommenting the `funct3` declaration and accepting changes that removed `clk`, `reset`, `ResultsData`, `baseAddr`, and `writeData` as ports of the Instruction_Decode module.\n\n**marwannismail** (Oct 26, 2025): \"Merge conflict resolved manually once merged main into working branch and added tweaks.\"\n\n**TheDeepestSpace** (Oct 27, 2025): \"This looks great!\" Indicated willingness to merge pending feedback from another contributor.\n\n## Linked Issues\n**Issue #58 - \"Extract RF module from instruction decoder\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"RF and instruction decoding seem to be quite different in their functionalities so it might make sense to stick RF right into `top` since its a pretty integral module.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr83", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr83.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr83", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr83"} {"instance_id": "UTOSS_risc-v_pr85", "issue_text": "# Add jalr feature, fix tb issues and add more tb for jal and jalr\n\nInstance: UTOSS_risc-v_pr85\nSource: https://github.com/UTOSS/risc-v/pull/85\nFetched: 2026-05-03\nRepository: UTOSS/risc-v\nPull request: #85\nAuthor: RunzeZhu28\nState: closed\nBase branch: main\nHead branch: tony_jalr\nCreated: 2025-10-27\nUpdated: 2025-10-28\nClosed: 2025-10-28\nMerged: 2025-10-28\n\n## PR Title\nAdd jalr feature, fix tb issues and add more tb for jal and jalr\n\n## PR Description\nNo description was provided. The PR adds support for `jalr`, fixes existing testbench issues, and expands tests for both `jal` and `jalr`. Two commits: 9828b2f and 5fef62b.\n\n## PR Comments\n**TheDeepestSpace** (Oct 28, 2025): Suggested minimising FSM states to reduce flip-flops. Noted that `JALR_CALC` duplicates `MEMADR` functionality and recommended renaming `JALR_STEP2` to `JALRWB` for consistency. Approved with \"Looks great, thanks Tony!\"\n\n## Linked Issues\n**Issue #71 - \"Review RISCOF's `RV32I` failures\"** (this PR contributes `jal`/`jalr` fixes).\n\nIssue body (verbatim from the source URL):\n\"Review latest RISCOF report (see artifacts of `main` branch's CI run) and fix issues individually as you find them.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr85", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr85.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr85", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr85"} {"instance_id": "UTOSS_risc-v_pr95", "issue_text": "# Update `iverilog` to latest snapshot\n\nInstance: UTOSS_risc-v_pr95\nSource: https://github.com/UTOSS/risc-v/pull/95\nFetched: 2026-05-03\nRepository: UTOSS/risc-v\nPull request: #95\nAuthor: TheDeepestSpace\nState: closed\nBase branch: main\nHead branch: boris/update-verilog\nCreated: 2025-10-28\nUpdated: 2025-10-28\nClosed: 2025-10-28\nMerged: 2025-10-28\n\n## PR Title\nUpdate `iverilog` to latest snapshot\n\n## PR Description\nNo description was provided. Single commit (9cdf413): \"update iverilog to latest snapshot.\"\n\n## PR Comments\nNo conversation comments. Activity: TheDeepestSpace self-assigned, linked issue #64, and merged at commit 0e5962b. 4 checks passed.\n\n## Linked Issues\n**Issue #64 - \"Update `iverilog`\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"Move to a newer version of `iverilog`. We are at 12.0, which is the latest stable one but its over 2 years old, and we may be missing out on a log of bug fixes and new features. Let's bump up to latest master (see https://github.com/steveicarus/iverilog) and keep tabs on new releases.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr95", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr95.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr95", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr95"} -{"instance_id": "UTOSS_risc-v_pr97", "issue_text": "# Fix more stylistic infractions\n\nInstance: UTOSS_risc-v_pr97\nSource: https://github.com/UTOSS/risc-v/pull/97\nFetched: 2026-05-03\nRepository: UTOSS/risc-v\nPull request: #97\nAuthor: TheDeepestSpace\nState: closed\nBase branch: main\nHead branch: boris/svlint-style-keyword\nCreated: 2025-10-28\nUpdated: 2025-10-28\nClosed: 2025-10-28\nMerged: 2025-10-28\n\n## PR Title\nFix more stylistic infractions\n\n## PR Description\nNo description was provided. Single commit \"fix more infractions\" (e745cd9). The PR addresses additional SVLint style-ruleset violations as part of the broader effort tracked in issue #91.\n\n## PR Comments\nNo conversation comments. TheDeepestSpace self-assigned, then merged commit 95d3d06 into main on Oct 28, 2025; 4 checks passed.\n\n## Linked Issues\n**Issue #91 - \"Integrate SVLint's style ruleset\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"See https://github.com/dalance/svlint/blob/15d7ccba7de2ec55dffd4dbfbd174a700b912ff2/rulesets/style.toml\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr97", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr97.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr97", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr97"} +{"instance_id": "UTOSS_risc-v_pr97", "issue_text": "# Fix more stylistic infractions\n\nInstance: UTOSS_risc-v_pr97\nSource: https://github.com/UTOSS/risc-v/pull/97\nFetched: 2026-05-03\nRepository: UTOSS/risc-v\nPull request: #97\nAuthor: TheDeepestSpace\nState: closed\nBase branch: main\nHead branch: boris/svlint-style-keyword\nCreated: 2025-10-28\nUpdated: 2025-10-28\nClosed: 2025-10-28\nMerged: 2025-10-28\n\n## PR Title\nFix more stylistic infractions\n\n## PR Description\nNo description was provided. Single commit \"fix more infractions\" (e745cd9). The PR addresses additional SVLint style-ruleset violations as part of the broader effort tracked in issue #91.\n\n## PR Comments\nNo conversation comments. TheDeepestSpace self-assigned, then merged commit 95d3d06 into main on Oct 28, 2025; 4 checks passed.\n\n## Linked Issues\n**Issue #91 - \"Integrate SVLint's style ruleset\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"See https://github.com/dalance/svlint/blob/15d7ccba7de2ec55dffd4dbfbd174a700b912ff2/rulesets/style.toml\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr97", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr97.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/UTOSS_risc-v_pr97", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/UTOSS_risc-v_pr97"} {"instance_id": "Wren6991_Hazard3_pr23", "issue_text": "# Fix abstract command using wrong register when initiated by abstractauto\n\nInstance: Wren6991_Hazard3_pr23\nSource: https://github.com/Wren6991/Hazard3/pull/23\nFetched: 2026-04-26\nRepository: Wren6991/Hazard3\nPull request: #23\nAuthor: Wren6991\nState: closed\nBase branch: stable\nHead branch: fix-dm-abstractauto-regno\nCreated: 2024-10-12T18:58:43Z\nUpdated: 2024-10-12T22:57:18Z\nClosed: 2024-10-12T19:03:45Z\nMerged: 2024-10-12T19:03:45Z\n\nThis affects memory downloads from the debugger when System Bus Access is not enabled or not configured.\r\n\r\nThis bug was introduced in https://github.com/Wren6991/Hazard3/commit/78a5cb98ea5d184c7b8bf31249ce8ac69e4abf68\r\n\r\nReleasing as a point fix due to severity and due to the fix being localised to the Debug Module.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/Wren6991_Hazard3_pr23", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/Wren6991_Hazard3_pr23.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/Wren6991_Hazard3_pr23", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/Wren6991_Hazard3_pr23"} {"instance_id": "Wren6991_Hazard3_pr28", "issue_text": "# Coding style change for Verilator compatibility (fixes #21)\n\nInstance: Wren6991_Hazard3_pr28\nSource: https://github.com/Wren6991/Hazard3/pull/28\nFetched: 2026-04-26\nRepository: Wren6991/Hazard3\nPull request: #28\nAuthor: Wren6991\nState: closed\nBase branch: stable\nHead branch: fix-21\nCreated: 2024-12-09T05:41:41Z\nUpdated: 2025-06-09T00:00:13Z\nClosed: 2024-12-09T05:55:00Z\nMerged: 2024-12-09T05:55:00Z\n\nThe boundary_conditions process in hazard3_frontend needs to be scheduled at least twice to resolve to the correct values. There are multiple possible interleavings, which should all result in the same result. However Verilator schedules the process only once.\r\n\r\nWork around this by moving the tie-off of the problematic variable into the synchronous update process.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/Wren6991_Hazard3_pr28", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/Wren6991_Hazard3_pr28.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/Wren6991_Hazard3_pr28", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/Wren6991_Hazard3_pr28"} {"instance_id": "Wren6991_Hazard3_pr41", "issue_text": "# Release v1.1.1 to stable\n\nInstance: Wren6991_Hazard3_pr41\nSource: https://github.com/Wren6991/Hazard3/pull/41\nFetched: 2026-04-26\nRepository: Wren6991/Hazard3\nPull request: #41\nAuthor: Wren6991\nState: closed\nBase branch: stable\nHead branch: develop\nCreated: 2026-03-12T18:19:01Z\nUpdated: 2026-03-12T18:28:21Z\nClosed: 2026-03-12T18:28:21Z\nMerged: 2026-03-12T18:28:21Z\n\n## PR Title\nRelease v1.1.1 to stable\n\n## PR Description\nNo description was provided for this pull request. The PR is a release-merge of `develop` into `stable` containing 8 commits that constitute Hazard3 v1.1.1:\n\n1. Update mimpid: 1.2 prerelease\n2. Fix repeated transfer on APB async bridge when instantiated separately to the JTAG-DTM\n3. Don't report failed exclusive writes as faults in `rvfi_bus_observer`; latch `rvfi_intr` signal; fix exclusives hookup in riscv-formal tb\n4. Fix uninitialised variable in `wfi_loop` tests\n5. Fix non-synthesisable statement in `hazard3_rvfi_monitor` when `HAZARD3_RVFI_STANDALONE` is defined\n6. Fix RVFI monitor reporting memory write for exclusive store that fails in data phase\n7. Fix: hardware breakpoint on CSR-writing instruction does not inhibit CSR write\n8. Set `mimpid` version to 1.1.1; update release notes in asciidoc\n\n## PR Comments\nNo conversation comments were posted on the PR. No assignees, labels, milestones, or external reviewers.\n\n## Linked Issues\nNo linked issues are referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/Wren6991_Hazard3_pr41", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/Wren6991_Hazard3_pr41.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/Wren6991_Hazard3_pr41", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/Wren6991_Hazard3_pr41"} @@ -123,7 +123,7 @@ {"instance_id": "YosysHQ_picorv32_pr244", "issue_text": "# Fix RV32E shifts by immediates >= 0x10\n\nInstance: YosysHQ_picorv32_pr244\nSource: https://github.com/YosysHQ/picorv32/pull/244\nFetched: 2026-05-03\nRepository: YosysHQ/picorv32\nPull request: #244\nAuthor: MichaelBell\nState: closed\nBase branch: main\nHead branch: fix-rv32e\nCreated: 2023-08-20\nUpdated: 2024-03-26\nClosed: 2024-03-26\nMerged: 2024-03-26\n\n## PR Title\nFix RV32E shifts by immediates >= 0x10\n\n## PR Description\nResolves issue #211. Makes shift-by-immediate instructions on the RV32E configuration use the full 5-bit immediate field rather than truncating it to 4 bits, so e.g. `slli` works with shift amounts >= 0x10. The author notes they did not exhaustively test other RV32E instructions but did not find further breakage in cursory testing, and that the change appears not to break Q-register instructions on RV32I (untested).\n\n## PR Comments\n**MichaelBell** (Aug 20, 2023): \"This fixes #211. I haven't found any other broken instructions on RV32E, but I haven't done rigorous testing. A cursory check suggests this change doesn't break the Q register instructions in RV32I, but I haven't tested that at all.\"\n\n**KrystalDelusion** (Mar 26, 2024): Force-pushed and merged the PR at commit de92ce5.\n\n## Linked Issues\n**Issue #211 - \"Bug when using RV32E (ENABLE_REGS_16_31=0)\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"Support for rv32e is buggy. Setting ENABLE_REGS_16_31 = 0 leads to the following:\n\n- regindex_bits will be 4 (instead of 5)\n- decoded_rs2 will be 4 bits wide (instead of 5)\n- reg_sh will be set to the 4 least significant bits of the immediate field of the instruction, instead of the full 5 bits\n- shift immediate instructions will fail (e.g. slli)\n\nEasily fixed by setting decoded_rs2 (and possibly decoded_rs1 and decoded_rs) fixed 5 bits wide, instead of having it depend on the size of the register file.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/YosysHQ_picorv32_pr244", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/YosysHQ_picorv32_pr244.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/YosysHQ_picorv32_pr244", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/YosysHQ_picorv32_pr244"} {"instance_id": "YosysHQ_picorv32_pr9", "issue_text": "# Deassert pcpi_valid upon asserting sbreak IRQ\n\nInstance: YosysHQ_picorv32_pr9\nSource: https://github.com/YosysHQ/picorv32/pull/9\nFetched: 2026-05-03\nRepository: YosysHQ/picorv32\nPull request: #9\nAuthor: stevekerrison\nState: closed\nBase branch: master\nHead branch: master (stevekerrison/picorv32 fork)\nCreated: 2016-05-31\nUpdated: 2016-06-01\nClosed: 2016-06-01\nMerged: 2016-06-01\n\n## PR Title\nDeassert pcpi_valid upon asserting sbreak IRQ\n\n## PR Description\nAddresses issue #8 (incorrect handling of SBREAK / illegal instructions when PCPI is enabled): on `sbreak` / illegal instruction the core now deasserts `pcpi_valid` when raising the SBREAK IRQ, so the next valid PCPI instruction is not mis-flagged as another `sbreak`.\n\nThe author notes two remaining considerations:\n1. Instructions like `sbreak` take roughly 16 cycles to trigger an IRQ because of PCPI timeout delays; immediate IRQ triggering for these instructions could be useful, though external PCPI modules might handle it differently.\n2. The behaviour of `sbreak` or illegal instructions inside ISRs is not examined here, although trapping seems like the natural answer.\n\n## PR Comments\n**stevekerrison** (May 31, 2016): \"This fixes #8\" along with the two unresolved follow-up considerations described above.\n\nThe PR was merged on Jun 1, 2016.\n\n## Linked Issues\n**Issue #8 - \"Incorrect handling of SBREAK/ILLNSN with PCPI\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"I'm trying to put a minimal example of this together (or a patch if I get there quicker), but won't get a chance until tomorrow. I leave this here for now as a test of my own sanity.\n\nIf PCPI is enabled and an illegal instruction or `sbreak` occur, upon `retirq`, the signal `pcpi_valid` remains asserted. The eventual effect of this is that when the next valid PCPI instruction comes along, it causes another `SBREAK` IRQ to occur, presumably because the PCPI timeout never got reset.\n\nI actually want to handle `ecall`, and I guess I could do it with another PCPI extension, but that seems like a less graceful solution.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/YosysHQ_picorv32_pr9", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/YosysHQ_picorv32_pr9.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/YosysHQ_picorv32_pr9", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/YosysHQ_picorv32_pr9"} {"instance_id": "ZipCPU_wb2axip_pr71", "issue_text": "# Fixed calculation of sufficiently_filled when the FIFO is full and aw_requests_remaining is less than a maximum burst\n\nInstance: ZipCPU_wb2axip_pr71\nSource: https://github.com/ZipCPU/wb2axip/pull/71\nFetched: 2026-05-03\nRepository: ZipCPU/wb2axip\nPull request: #71\nAuthor: mbiermann-mo-space\nState: closed\nBase branch: master\nHead branch: fix/axis2mm_sufficiently_filled\nCreated: 2025-01-16\nUpdated: 2025-02-05\nClosed: 2025-01-23\nMerged: 2025-01-23\n\n## PR Title\nFixed calculation of sufficiently_filled when the FIFO is full and aw_requests_remaining is less than a maximum burst\n\n## PR Description\nWhen `aw_requests_remaining` is less than `1 << LGMAXBURST`, the entire `data_available` value should be checked instead of just the lower `data_available[LGMAXBURST-1:0]` slice. In the contributor's case `data_available` was `0x200`, so the slice evaluated to 0 and the transfer never finished. Fixes issue #69.\n\n## PR Comments\n**mbiermann-mo-space** (Jan 16, 2025): Initial pull request submission with the problem description.\n\n**ZipCPU** (Jan 17, 2025): \"Pending further discussion and review.\"\n\n**ZipCPU** (Jan 23, 2025): \"Thank you. Dan\" - merged the PR.\n\n**mbiermann-mo-space** (Feb 5, 2025): Deleted the feature branch.\n\n## Linked Issues\n**Issue #69 - \"axis2mm hangs for small transaction sizes when the FIFO is full (i.e. when r_continuous is set to 1)\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"Maybe I'm misinterpreting the correct usage of r_continuous.\nThe FIFO being reset means that some data is lost correct?\nI'd like to avoid that however this isn't critical for my application so for now a workaround is to just not use r_continuous.\n\nThe core reports it is busy however S_AXIS_TREADY stays at 0 and the transfer is never finished (even after several seconds r_busy stays 1 for small transfer sizes).\n\nFor me it happens when I:\n- direct the core to write 1MiB\n- don't start another transfer immediately after (no error bit is set though)\n- after a while start another transfer\n - from a new address instead of the one where the core left off (the address is the same as for the first transfer)\n - with a comparatively low length (16 bytes and 1024 bytes both don't work, 4096 bytes does)\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/ZipCPU_wb2axip_pr71", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/ZipCPU_wb2axip_pr71.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/ZipCPU_wb2axip_pr71", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/ZipCPU_wb2axip_pr71"} -{"instance_id": "alexforencich_verilog-pcie_pr19", "issue_text": "# Fix multi-driven net issue when S_RAM_SEL_WIDTH = 0\n\nInstance: alexforencich_verilog-pcie_pr19\nSource: https://github.com/alexforencich/verilog-pcie/pull/19\nFetched: 2026-04-26\nRepository: alexforencich/verilog-pcie\nPull request: #19\nAuthor: Basseuph\nState: closed\nBase branch: master\nHead branch: mle/fix_multi_net_driver\nCreated: 2021-12-10T16:52:24Z\nUpdated: 2021-12-10T20:56:16Z\nClosed: 2021-12-10T20:47:04Z\nMerged: 2021-12-10T20:47:04Z\n\n## PR Title\nFix multi-driven net issue when S_RAM_SEL_WIDTH = 0\n\n## PR Description\nAs per a discussion on slack we built a corundum design with a single interface and multiple ports and there were actually two issues. One was fixed already, see 3a124837115e51e2273ab7d1c61d80ee01f891c1 in verilog-pcie. A very similar one was still to be fixed and this PR now proposes the respective fix.\n\nThe PR adapts the same fix that was already applied to the `dma_ram_demux_rd.v` module to the `dma_ram_demux_wr.v` module.\n\n## PR Comments\n\n**Basseuph** (Dec 10, 2021):\nThe submitter's initial message explained the context and referenced a similar fix that had already been applied to the `dma_ram_demux_rd.v` module, noting this PR adapts that same solution to the `dma_ram_demux_wr.v` module.\n\n**alexforencich** (Dec 10, 2021):\n\"LGTM\" (looks good to me)\n\n**alexforencich** (Dec 10, 2021):\n\"dang it, I thought I selected the right option to avoid the merge commit. I guess I need to clean that up...\"\n\n**alexforencich** (Dec 10, 2021):\n\"I just pulled it directly from your branch; I'll get this merged into Corundum shortly. Also, I recommend adding your MLE email address to your github profile so your commits will link back to your github account.\"\n\n## Linked Issues\nNo linked issues are referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/alexforencich_verilog-pcie_pr19", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/alexforencich_verilog-pcie_pr19.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/alexforencich_verilog-pcie_pr19", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/alexforencich_verilog-pcie_pr19"} +{"instance_id": "alexforencich_verilog-pcie_pr19", "issue_text": "# Fix multi-driven net issue when S_RAM_SEL_WIDTH = 0\n\nInstance: alexforencich_verilog-pcie_pr19\nSource: https://github.com/alexforencich/verilog-pcie/pull/19\nFetched: 2026-04-26\nRepository: alexforencich/verilog-pcie\nPull request: #19\nAuthor: Basseuph\nState: closed\nBase branch: master\nHead branch: mle/fix_multi_net_driver\nCreated: 2021-12-10T16:52:24Z\nUpdated: 2021-12-10T20:56:16Z\nClosed: 2021-12-10T20:47:04Z\nMerged: 2021-12-10T20:47:04Z\n\n## PR Title\nFix multi-driven net issue when S_RAM_SEL_WIDTH = 0\n\n## PR Description\nAs per a discussion on slack we built a corundum design with a single interface and multiple ports and there were actually two issues. One was fixed already, see 3a124837115e51e2273ab7d1c61d80ee01f891c1 in verilog-pcie. A very similar one was still to be fixed and this PR now proposes the respective fix.\n\nThe PR adapts the same fix that was already applied to the `dma_ram_demux_rd.v` module to the `dma_ram_demux_wr.v` module.\n\n## PR Comments\n\n**Basseuph** (Dec 10, 2021):\nThe submitter's initial message explained the context and referenced a similar fix that had already been applied to the `dma_ram_demux_rd.v` module, noting this PR adapts that same solution to the `dma_ram_demux_wr.v` module.\n\n**alexforencich** (Dec 10, 2021):\n\"LGTM\" (looks good to me)\n\n**alexforencich** (Dec 10, 2021):\n\"dang it, I thought I selected the right option to avoid the merge commit. I guess I need to clean that up...\"\n\n**alexforencich** (Dec 10, 2021):\n\"I just pulled it directly from your branch; I'll get this merged into Corundum shortly. Also, I recommend adding your MLE email address to your github profile so your commits will link back to your github account.\"\n\n## Linked Issues\nNo linked issues are referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/alexforencich_verilog-pcie_pr19", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/alexforencich_verilog-pcie_pr19.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/alexforencich_verilog-pcie_pr19", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/alexforencich_verilog-pcie_pr19"} {"instance_id": "alexforencich_verilog-pcie_pr20", "issue_text": "# Fix reg to wire declaration\n\nInstance: alexforencich_verilog-pcie_pr20\nSource: https://github.com/alexforencich/verilog-pcie/pull/20\nFetched: 2026-04-26\nRepository: alexforencich/verilog-pcie\nPull request: #20\nAuthor: joft-mle\nState: closed\nBase branch: master\nHead branch: mle/fix-202112b\nCreated: 2021-12-15T18:14:34Z\nUpdated: 2021-12-17T08:39:51Z\nClosed: 2021-12-16T08:27:43Z\nMerged: 2021-12-16T08:27:43Z\n\n## PR Title\nFix reg to wire declaration\n\n## PR Description\nJust a small independent one-line issue spotted by @andreasbraun90 during the ongoing ZynqMP porting effort.\n\n## PR Comments\n\n**joft-mle** (Dec 15, 2021):\n\"Just a small independent one-line issue spotted by @andreasbraun90 during the ongoing ZynqMP porting effort.\"\n\n**alexforencich** (Dec 16, 2021):\n\"Nice, I will get this merged into Corundum shortly\"\n\n## PR Metadata\n- Status: Merged\n- Merged by: alexforencich\n- Merge date: Dec 16, 2021\n- Commit: be331e7\n- Author: Andreas Braun (missinglinkelectronics)\n- Participants: joft-mle, alexforencich, andreasbraun90\n\n## Linked Issues\nNo linked issues were referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/alexforencich_verilog-pcie_pr20", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/alexforencich_verilog-pcie_pr20.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/alexforencich_verilog-pcie_pr20", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/alexforencich_verilog-pcie_pr20"} {"instance_id": "aolofsson_oh_pr109", "issue_text": "# Fix width of padring 'dout' ports\n\nInstance: aolofsson_oh_pr109\nSource: https://github.com/aolofsson/oh/pull/109\nFetched: 2026-04-26\nRepository: aolofsson/oh\nPull request: #109\nAuthor: nmoroze\nState: closed\nBase branch: master\nHead branch: master\nCreated: 2021-07-06T21:52:56Z\nUpdated: 2021-07-25T02:11:39Z\nClosed: 2021-07-25T02:11:39Z\nMerged: 2021-07-25T02:11:39Z\n\n## PR Title\nFix width of padring 'dout' ports\n\n## PR Description\nNo description body was provided in this pull request.\n\n## PR Comments\n\n**nmoroze** (Jul 6, 2021):\n\"I believe the extra `-1`s are likely a typo!\"\n\n**aolofsson** (Jul 25, 2021):\n\"Thanks for the fix!\"\n\n## PR Metadata\n- Status: Merged\n- Merge Date: Jul 25, 2021\n- Commit Hash: b52c45d119d346094d92ae467abefcc073355eb9\n- Source Branch: nmoroze/oh:master\n- Target Branch: aolofsson/oh:master\n- Participants: nmoroze, aolofsson\n\n## Linked Issues\nNo linked issues were referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/aolofsson_oh_pr109", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/aolofsson_oh_pr109.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/aolofsson_oh_pr109", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/aolofsson_oh_pr109"} {"instance_id": "aolofsson_oh_pr110", "issue_text": "# Add \"tech config\" pass-through for technology-specific GPIO configuration\n\nInstance: aolofsson_oh_pr110\nSource: https://github.com/aolofsson/oh/pull/110\nFetched: 2026-04-26\nRepository: aolofsson/oh\nPull request: #110\nAuthor: nmoroze\nState: closed\nBase branch: master\nHead branch: master\nCreated: 2021-08-10T14:36:30Z\nUpdated: 2021-08-16T02:49:10Z\nClosed: 2021-08-16T02:49:10Z\nMerged: 2021-08-16T02:49:10Z\n\nSorry for the large diff, oh_padring.v had something going on with a mix of tabs and spaces that was screwing up my editor, so I fixed that up. \r\n\r\nAlso, I'm not 100% sold on the name tech_cfg, so happy to take suggestions there.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/aolofsson_oh_pr110", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/aolofsson_oh_pr110.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/aolofsson_oh_pr110", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/aolofsson_oh_pr110"} @@ -142,7 +142,7 @@ {"instance_id": "bensampson5_libsv_pr109", "issue_text": "# 8b/10b decoder improvements\n\n- Source URL: https://github.com/bensampson5/libsv/issues/107\n\nFeature list\n- Add input clock, reset, and move running disparity to an internal calculation\n- Add enable input ``i_en``\n- Register outputs\n\nAdditional TODO\n- Fix testbench\n- Update docs for 8b10b decoder (take a look at 8b10b encoder)\n\n## PR Content from GitHub\n\n# PR Summary: 8b/10b Decoder Improvements\n\n**PR Title:** 8b/10b decoder improvements #109\n\n**Status:** Merged (November 28, 2021)\n\n---\n\n## PR Description\n\nThis pull request addresses issue #107 and implements several enhancements to the 8b/10b decoder module:\n\n**Features Added:**\n- Input clock, reset signals, with running disparity moved to internal calculation\n- Enable input (`i_en`)\n- Registered outputs\n\n**Pending Tasks:**\n- Fix testbench\n- Update documentation (referencing the 8b10b encoder documentation as a model)\n\n---\n\n## PR Activity Timeline\n\n**Commits:** 4 commits were merged\n- Implementation of new 8b/10b decoder features\n- Format fixes\n- Linting corrections\n- Documentation updates\n\n**Labels:** enhancement (New feature or request)\n\n**Assignee:** bensampson5 (repository owner)\n\n**Linked Issue:** Successfully closes issue #107 regarding 8b/10b decoder improvements\n\n---\n\n## Discussion\n\nThe PR shows standard GitHub workflow activity with commit additions, label application, and self-assignment by the author. No reviewer comments or additional discussion beyond the initial feature list was documented.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bensampson5_libsv_pr109", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bensampson5_libsv_pr109.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bensampson5_libsv_pr109", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bensampson5_libsv_pr109"} {"instance_id": "bensampson5_libsv_pr119", "issue_text": "# Add include guards to all source files\n\n- Source URL: https://github.com/bensampson5/libsv/issues/117\n\n\n## PR Content from GitHub\n\n# GitHub Pull Request Summary\n\n**PR Title:** Issue 117 add include guards to all source files\n\n**PR Number:** #119\n\n**Status:** Merged\n\n**Repository:** bensampson5/libsv\n\n**Merge Date:** January 29, 2022\n\n**Author:** bensampson5\n\n---\n\n## PR Description\n\nThe pull request description area appears to have encountered loading errors on the page, preventing the full body text from being extracted. However, the PR references \"Closes #117,\" indicating it addresses a specific issue.\n\n---\n\n## Commits\n\n1. \"Add include guards to all files that don't have it\" (commit 6da745c)\n2. \"Fix format\" (commit b44a92d)\n\n---\n\n## Linked Issue\n\n**Issue #117:** \"Add include guards to all source files\"\n\nThe full issue body text could not be extracted due to page loading errors.\n\n---\n\n## Comments\n\nNo user comments were successfully loaded on the conversation thread due to technical issues with the page rendering.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bensampson5_libsv_pr119", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bensampson5_libsv_pr119.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bensampson5_libsv_pr119", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bensampson5_libsv_pr119"} {"instance_id": "bensampson5_libsv_pr132", "issue_text": "# Write documentation for priority encoder\n\n- Source URL: https://github.com/bensampson5/libsv/issues/113\n\n\n## PR Content from GitHub\n\n# Pull Request Summary\n\n**PR Title:** Add documentation for priority_encoder #132\n\n**PR Status:** Merged on January 30, 2022\n\n**PR Description Body:** Not explicitly provided in the page content.\n\n## PR Comments\n\n**Author: bensampson5** (Jan 30, 2022)\n\"Closes #113\"\n\n## Linked Issue\n\n**Issue Title:** Write documentation for priority encoder\n\n**Issue Number:** #113\n\n**Issue Description Body:** Not visible in the provided page content.\n\n## Additional Details\n\n- **Merged By:** bensampson5\n- **Commits:** 1 commit (8b7bf0f)\n- **Branch:** issue-113-Write_documentation_for_priority_encoder merged into main\n- **Assignee:** bensampson5\n- **Reviewers:** None\n- **Labels:** None\n- **Milestone:** None\n\nThe pull request successfully merged documentation additions for the priority_encoder component, directly addressing the requirements outlined in issue #113.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bensampson5_libsv_pr132", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bensampson5_libsv_pr132.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bensampson5_libsv_pr132", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bensampson5_libsv_pr132"} -{"instance_id": "bensampson5_libsv_pr150", "issue_text": "# Fix reconvergence issue with synchronizer\n\n- Source URL: https://github.com/bensampson5/libsv/issues/149\n\nSynchronizer can't handle multibit data so update to be just a single bit synchronizer\n\n## PR Content from GitHub\n\n# Pull Request Summary\n\n**PR Title:** Fix reconvergence issue in synchronizer\n\n**PR Number:** #150\n\n**Repository:** bensampson5/libsv\n\n**Status:** Merged (February 7, 2022)\n\n---\n\n## PR Description\nThe PR description body was not fully visible in the provided content. The only explicit reference states: \"Closes #149\"\n\n---\n\n## Comments\n\n**Author:** bensampson5\n\nComment text: \"Closes #149\"\n\n---\n\n## Linked Issue\n\n**Issue #149 Title:** Fix reconvergence issue with synchronizer\n\n**Issue Description:** The full issue body was not included in the extracted content, though the PR references it as the issue being resolved.\n\n---\n\n## Merge Information\n\n- **Merged by:** bensampson5\n- **Merge commit:** 989a51a\n- **Source branch:** issue-149-Fix_reconvergence_issue_with_synchronizer\n- **Target branch:** main\n- **Commits included:** 1\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bensampson5_libsv_pr150", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bensampson5_libsv_pr150.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bensampson5_libsv_pr150", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bensampson5_libsv_pr150"} +{"instance_id": "bensampson5_libsv_pr150", "issue_text": "# Fix reconvergence issue with synchronizer\n\n- Source URL: https://github.com/bensampson5/libsv/issues/149\n\nSynchronizer can't handle multibit data so update to be just a single bit synchronizer\n\n## PR Content from GitHub\n\n# Pull Request Summary\n\n**PR Title:** Fix reconvergence issue in synchronizer\n\n**PR Number:** #150\n\n**Repository:** bensampson5/libsv\n\n**Status:** Merged (February 7, 2022)\n\n---\n\n## PR Description\nThe PR description body was not fully visible in the provided content. The only explicit reference states: \"Closes #149\"\n\n---\n\n## Comments\n\n**Author:** bensampson5\n\nComment text: \"Closes #149\"\n\n---\n\n## Linked Issue\n\n**Issue #149 Title:** Fix reconvergence issue with synchronizer\n\n**Issue Description:** The full issue body was not included in the extracted content, though the PR references it as the issue being resolved.\n\n---\n\n## Merge Information\n\n- **Merged by:** bensampson5\n- **Merge commit:** 989a51a\n- **Source branch:** issue-149-Fix_reconvergence_issue_with_synchronizer\n- **Target branch:** main\n- **Commits included:** 1\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bensampson5_libsv_pr150", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bensampson5_libsv_pr150.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bensampson5_libsv_pr150", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/bensampson5_libsv_pr150"} {"instance_id": "bensampson5_libsv_pr153", "issue_text": "# Mistake in `libsv/libsv/coders/encoder_8b10b.sv`\n\n- Source URL: https://github.com/bensampson5/libsv/issues/151\n\nHello!\n\nI am working on implementing 8b/10b encoding in a different project, and I stumbled upon the lookup table for encoding in this project. After writing my tests, I think I have found a mistake in your code in [encoder_8b10b.sv](https://github.com/bensampson5/libsv/blob/main/libsv/coders/encoder_8b10b.sv): for all code groups D28.X, the last 6 bits are `001110` while they should actually be `011100` according to the table in IEEE 802.3. Could this be possible?\n\n## PR Content from GitHub\n\n# Pull Request Summary\n\n**PR Title:** fix 8b10b encoder issue\n\n**PR Number:** #153\n\n**Status:** Merged\n\n**Author:** bensampson5\n\n**Merge Date:** May 26, 2024\n\n---\n\n## PR Description\n\nThe PR description area contains an error message stating \"There was an error while loading. Please reload this page.\" The actual description content is not accessible in the provided content.\n\nHowever, the PR references and closes issue #151: \"Mistake in `libsv/libsv/coders/encoder_8b10b.sv`\"\n\n---\n\n## Activity Timeline\n\n- **Commit:** `beb1c29` with message \"fix encoder issue\"\n- **Label Added:** bug (Something isn't working)\n- **Assignee:** bensampson5 (self-assigned)\n- **Merge Commit:** `d3b4b3b` merged into main branch\n- **Branch Deleted:** issue-151-Mistake_in_libsv/libsv/coders/encoder_8b10b_sv\n\n---\n\n## Comments\n\nNo user comments are accessible due to loading errors displayed in the page content.\n\n---\n\n## Linked Issue\n\n**Issue #151:** \"Mistake in `libsv/libsv/coders/encoder_8b10b.sv`\" -- addressed by this PR.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bensampson5_libsv_pr153", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bensampson5_libsv_pr153.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bensampson5_libsv_pr153", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bensampson5_libsv_pr153"} {"instance_id": "bensampson5_libsv_pr19", "issue_text": "# Write Verilator testbench for counter\n\n- Source URL: https://github.com/bensampson5/libsv/issues/7\n\n\n## PR Content from GitHub\n\n# Pull Request Summary\n\n**PR Title:** Docker try catch2 #19\n\n**PR Status:** Merged (December 29, 2020)\n\n**PR Description Body:**\nThe description content failed to load properly in the provided page content, showing \"Uh oh! There was an error while loading. Please reload this page.\" However, the PR closing statement indicates: \"Closes #7\" and \"Closes #11\"\n\n**PR Comments:**\nNo readable comment content was successfully extracted from the conversation section due to loading errors displayed on the page.\n\n**Linked Issues:**\n1. **Issue #11:** \"See if catch2 can be leveraged for unit testing IP\"\n2. **Issue #7:** \"Write Verilator testbench for counter\"\n\n**Commits Included (6 total):**\n- Add catch2 install to Dockerfile\n- Integrate catch2\n- Write unit test for counter\n- Added SRC_DIR to CMake\n- Add ninja-build install to Dockerfile\n- Update readme and format counter.sv\n\n**Author:** bensampson5\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bensampson5_libsv_pr19", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bensampson5_libsv_pr19.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bensampson5_libsv_pr19", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bensampson5_libsv_pr19"} {"instance_id": "bensampson5_libsv_pr2", "issue_text": "# Write some kind of IP\n\n- Source URL: https://github.com/bensampson5/libsv/issues/1\n\nThe catalog needs to be started with at least one kind of IP. Let's pick a parameterized counter that counts up.\n\nTasks:\n- [ ] Create a new Verilog file `counter.v`\n- [ ] Write a testbench for it\n- [ ] Simulate it to validate it's operation\n\n## PR Content from GitHub\n\n# GitHub Pull Request #2 Summary\n\n**PR Title:** \"1 write some kind of ip\"\n\n**PR Description Body:** \"Closes #1\"\n\n**Commits (6 total):**\n1. Implement counter.v\n2. Move counter.v into src/\n3. Add counter_tb.sv to tb/\n4. Create .gitignore and ignore .vcd files\n5. Add async active low reset to counter\n6. Add counter_tb\n\n**PR Comments:** None visible in the conversation section (loading error prevented full display)\n\n**Linked Issue #1 Title:** \"Write some kind of IP\"\n\n**Status:** Merged on December 23, 2020 by bensampson5\n\nThe pull request addressed a straightforward request to implement digital hardware IP (intellectual property), specifically a counter module written in SystemVerilog with accompanying testbench files.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bensampson5_libsv_pr2", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bensampson5_libsv_pr2.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bensampson5_libsv_pr2", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bensampson5_libsv_pr2"} @@ -158,7 +158,7 @@ {"instance_id": "bespoke-silicon-group_basejump_stl_pr472", "issue_text": "# Potential bug in hardened fifo module\n\nThe hardened fifo module contains a variable `read_write_same_addr_n`, which is currently assigned as `wptr_r == rptr_r`. The comment for this variable mentions that it should be 1 when the fifo is empty, but the condition is true for both empty and full fifo conditions. The line in question is given below:\n\nhttps://github.com/bespoke-silicon-group/basejump_stl/blob/4cfaeb454a7278f7d13eb766dad07ce34fefcdea/bsg_dataflow/bsg_fifo_1r1w_small_hardened.v#L118\n\nIf this variable is 1 when the fifo is full, it prevents the memory read as in https://github.com/bespoke-silicon-group/basejump_stl/blob/4cfaeb454a7278f7d13eb766dad07ce34fefcdea/bsg_dataflow/bsg_fifo_1r1w_small_hardened.v#L95\nThe assignment can instead be `assign read_write_same_addr_n = empty`.\n\n## Linked Issue Content from GitHub\n\n**Issue #465: Potential bug in hardened fifo module**\n\n- Body: `read_write_same_addr_n = wptr_r == rptr_r` is true for both empty AND full conditions, but the comment says it should be 1 only when empty. When fifo is full, this prevents memory read at line 95 (`r_v_i (~read_write_same_addr_n)`). Suggested fix: `assign read_write_same_addr_n = empty`.\n- Author: Shashank-Vijay, Opened July 19, 2021. Status: Closed (resolved via PR #472). Label: bug.\n- Comments: None.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bespoke-silicon-group_basejump_stl_pr472", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bespoke-silicon-group_basejump_stl_pr472.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bespoke-silicon-group_basejump_stl_pr472", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bespoke-silicon-group_basejump_stl_pr472"} {"instance_id": "bespoke-silicon-group_basejump_stl_pr668", "issue_text": "# Reusable module for IPOLY hashing logic\n\nInstance: bespoke-silicon-group_basejump_stl_pr668\nSource: https://github.com/bespoke-silicon-group/basejump_stl/pull/668\nFetched: 2026-04-26\nRepository: bespoke-silicon-group/basejump_stl\nPull request: #668\nAuthor: tommydcjung\nState: closed\nBase branch: master\nHead branch: ipoly_hashing_module\nCreated: 2023-12-06T00:58:23Z\nUpdated: 2023-12-09T17:55:30Z\nClosed: 2023-12-09T00:12:19Z\nMerged: 2023-12-09T00:12:19Z\n\n## PR Description\nNo description was provided by the contributor.\n\n## Comments and Discussion\n\ntommydcjung (Contributor) - December 6, 2023:\nInitial submission with no description provided.\n\ntommydcjung - December 6, 2023:\nCorrected the PR title from \"Reusuable\" to \"Reusable\".\n\ndpetrisko (Reviewer) - December 7, 2023:\nAsked whether supporting smaller bank configurations would be feasible, suggesting this feature \"might be worth it to support for tiny manycores / BP multicores\".\n\ntommydcjung - December 8, 2023:\nResponded by adding support for 4 and 8 banks in addition to the existing configuration.\n\ndpetrisko - December 9, 2023:\nApproved the changes and merged the pull request.\n\n## Additional Context\nThe PR branch `ipoly_hashing_module` was deleted after merging. The changes have been referenced in subsequent commits across multiple repositories.\n\nNo linked issues were referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bespoke-silicon-group_basejump_stl_pr668", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bespoke-silicon-group_basejump_stl_pr668.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bespoke-silicon-group_basejump_stl_pr668", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bespoke-silicon-group_basejump_stl_pr668"} {"instance_id": "bespoke-silicon-group_basejump_stl_pr673", "issue_text": "# bsg_dataflow/bsg_fifo_bypass.sv: Port/variable name mismatch\n\nIn bsg_dataflow/bsg_fifo_bypass.sv there is a variable `fifo_ready_param_i` that does not match up with any port name.\n\nhttps://github.com/bespoke-silicon-group/basejump_stl/blob/14f29e4d8a498ad62ec05fe232407f9d887e36a9/bsg_dataflow/bsg_fifo_bypass.sv#L4-L36\n\nBy comparison with the [testbench](https://github.com/bespoke-silicon-group/basejump_stl/blob/14f29e4d8a498ad62ec05fe232407f9d887e36a9/testing/bsg_dataflow/bsg_fifo_bypass/testbench.sv#L46), I assume this is supposed to be `fifo_ready_i`?\n\n## Linked Issue Content from GitHub\n\n**Issue #672: bsg_dataflow/bsg_fifo_bypass.sv: Port/variable name mismatch**\n\n- Body: Variable `fifo_ready_param_i` doesn't match any port name. Module ports declare `fifo_ready_i` but internal assignment uses `fifo_ready_param_i` (`assign ready_param_o = fifo_ready_param_i;`). Comparison with testbench suggests it should be `fifo_ready_i`.\n- Opened March 1, 2024. Linked PR: #673.\n- Comments: None.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bespoke-silicon-group_basejump_stl_pr673", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bespoke-silicon-group_basejump_stl_pr673.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bespoke-silicon-group_basejump_stl_pr673", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bespoke-silicon-group_basejump_stl_pr673"} -{"instance_id": "bespoke-silicon-group_basejump_stl_pr675", "issue_text": "The variable addr_li is referenced before declaration in bsg_mem/bsg_mem_1rw_sync_mask_write_bit_from_1r1w.sv. While in principle an HDL shouldn't have any problem with this, some compilers don't like it very much. Causes compile errors in Questa/Modelsim and Synopsys DC (and possibly others as well).\n\nbasejump_stl/bsg_mem/bsg_mem_1rw_sync_mask_write_bit_from_1r1w.sv\n\nLines 65 to 69 in 2a73106\n\n wire addr_match = w_addr_r == addr_li;\n wire bypass_n = v_and_w_r & addr_match;\n wire bypass_r;\n\n wire [addr_width_lp-1:0] addr_li = els_p > 1 ? addr_i : '0;\nThe easy solution is to move L69 up to before L65. This resolves errors in both tools.\n\n## Linked Issue Content from GitHub\n\n**Issue #674: bsg_mem/bsg_mem_1rw_sync_mask_write_bit_from_1r1w.sv: Variable used before declaration**\n\n- Body: `addr_li` referenced before declaration. Causes compile errors in Questa/Modelsim and Synopsys DC. Suggested fix: move line 69 (the `addr_li` declaration) up to before line 65.\n- Linked PR: #675.\n- Comments: None.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bespoke-silicon-group_basejump_stl_pr675", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bespoke-silicon-group_basejump_stl_pr675.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bespoke-silicon-group_basejump_stl_pr675", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bespoke-silicon-group_basejump_stl_pr675"} +{"instance_id": "bespoke-silicon-group_basejump_stl_pr675", "issue_text": "The variable addr_li is referenced before declaration in bsg_mem/bsg_mem_1rw_sync_mask_write_bit_from_1r1w.sv. While in principle an HDL shouldn't have any problem with this, some compilers don't like it very much. Causes compile errors in Questa/Modelsim and Synopsys DC (and possibly others as well).\n\nbasejump_stl/bsg_mem/bsg_mem_1rw_sync_mask_write_bit_from_1r1w.sv\n\nLines 65 to 69 in 2a73106\n\n wire addr_match = w_addr_r == addr_li;\n wire bypass_n = v_and_w_r & addr_match;\n wire bypass_r;\n\n wire [addr_width_lp-1:0] addr_li = els_p > 1 ? addr_i : '0;\nThe easy solution is to move L69 up to before L65. This resolves errors in both tools.\n\n## Linked Issue Content from GitHub\n\n**Issue #674: bsg_mem/bsg_mem_1rw_sync_mask_write_bit_from_1r1w.sv: Variable used before declaration**\n\n- Body: `addr_li` referenced before declaration. Causes compile errors in Questa/Modelsim and Synopsys DC. Suggested fix: move line 69 (the `addr_li` declaration) up to before line 65.\n- Linked PR: #675.\n- Comments: None.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bespoke-silicon-group_basejump_stl_pr675", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bespoke-silicon-group_basejump_stl_pr675.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bespoke-silicon-group_basejump_stl_pr675", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/bespoke-silicon-group_basejump_stl_pr675"} {"instance_id": "bespoke-silicon-group_basejump_stl_pr676", "issue_text": "# bsg_dmc/bsg_dmc_dly_line_v3.sv: Fix missing include\n\nInstance: bespoke-silicon-group_basejump_stl_pr676\nSource: https://github.com/bespoke-silicon-group/basejump_stl/pull/676\nFetched: 2026-04-26\nRepository: bespoke-silicon-group/basejump_stl\nPull request: #676\nAuthor: infinitymdm\nState: closed\nBase branch: master\nHead branch: fix_bsg_dmc_missing_include\nCreated: 2024-03-11T20:12:47Z\nUpdated: 2024-09-09T15:18:04Z\nClosed: 2024-03-11T21:39:37Z\nMerged: 2024-03-11T21:39:37Z\n\n## PR Description\n\ninfinitymdm reported that a necessary include statement was absent from the file `bsg_dmc/bsg_dmc_dly_line_v3.sv`. The contributor noted: \"Without this line we get errors when trying to run simulation since the file uses some of the macros defined in bsg_misc/bsg_defines.sv.\"\n\n## Comments\n\ndpetrisko (Reviewer/Approver):\n\"LGTM\" - indicating approval of the changes.\n\n## Additional Context\n\nMerged by dpetrisko on March 11, 2024. Branch deleted on September 9, 2024.\n\nNo linked issues were explicitly referenced in the pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bespoke-silicon-group_basejump_stl_pr676", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bespoke-silicon-group_basejump_stl_pr676.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bespoke-silicon-group_basejump_stl_pr676", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bespoke-silicon-group_basejump_stl_pr676"} {"instance_id": "bespoke-silicon-group_basejump_stl_pr677", "issue_text": "# Update bsg_defines.sv for yosys\n\nInstance: bespoke-silicon-group_basejump_stl_pr677\nSource: https://github.com/bespoke-silicon-group/basejump_stl/pull/677\nFetched: 2026-04-26\nRepository: bespoke-silicon-group/basejump_stl\nPull request: #677\nAuthor: dpetrisko\nState: closed\nBase branch: master\nHead branch: dpetrisko-patch-24\nCreated: 2024-03-27T20:31:35Z\nUpdated: 2024-03-28T22:52:07Z\nClosed: 2024-03-28T22:52:06Z\nMerged: 2024-03-28T22:52:06Z\n\n## PR Description\nThe pull request lacks a detailed description body. The primary context comes from the comments.\n\n## Comments\n\ndpetrisko (Mar 27, 2024):\n\"YOSYS is not Vivado, so we should identify it as such\"\n\nstdavids (Mar 28, 2024):\nApproved the changes with a review of the modified files.\n\n## Additional Context\nLabels: bug. Commits: 1 (a47e1e1). The change updates `bsg_defines.sv` to properly distinguish between the YOSYS synthesis tool and Vivado, rather than treating them identically. The change was approved and incorporated into the master branch.\n\nNo linked issues were referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bespoke-silicon-group_basejump_stl_pr677", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bespoke-silicon-group_basejump_stl_pr677.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bespoke-silicon-group_basejump_stl_pr677", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bespoke-silicon-group_basejump_stl_pr677"} {"instance_id": "bespoke-silicon-group_basejump_stl_pr697", "issue_text": "# fix bsg_transpose_reduce\n\nInstance: bespoke-silicon-group_basejump_stl_pr697\nSource: https://github.com/bespoke-silicon-group/basejump_stl/pull/697\nFetched: 2026-04-26\nRepository: bespoke-silicon-group/basejump_stl\nPull request: #697\nAuthor: tommydcjung\nState: closed\nBase branch: master\nHead branch: bsg_transpose_reduce_fix\nCreated: 2024-10-04T20:39:37Z\nUpdated: 2024-10-06T17:35:28Z\nClosed: 2024-10-06T17:35:25Z\nMerged: 2024-10-06T17:35:25Z\n\n## PR Description\n\nNo description was provided for this pull request.\n\n## Comments\n\ndpetrisko (October 5, 2024):\n\"Looks good!\" - approval comment left during the review process.\n\n## Additional Context\n\nReviewers: dpetrisko approved the changes; taylor-bsg was requested for review. Commits: 1 commit (58dd32b). Merged by tommydcjung on October 6, 2024.\n\nNo linked issues were explicitly documented in the pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bespoke-silicon-group_basejump_stl_pr697", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bespoke-silicon-group_basejump_stl_pr697.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/bespoke-silicon-group_basejump_stl_pr697", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bespoke-silicon-group_basejump_stl_pr697"} @@ -198,18 +198,18 @@ {"instance_id": "chipsalliance_adams-bridge_pr77", "issue_text": "# keygen/signing/verifying_process signals need zeroize to be cleared\n\n- Source URL: https://github.com/chipsalliance/adams-bridge/issues/69\n\nwe need to clear them when the process is completed\nhttps://github.com/chipsalliance/adams-bridge/blob/b43c7bc0150e045a7bc2b86f5e5c2d9c36e22f6d/src/mldsa_top/rtl/mldsa_ctrl.sv#L1036C1-L1039C85\n\nPR Title: External_Mu enhancement\n\nDescription:\nThe PR description was not fully loaded in the content provided, but the initial comment indicates:\n- Fixed issue #69\n- Fixed issue #75\n\nLinked Issues:\nIssue #75: \"writing internal mu to hwif_in\"\nIssue #69: \"keygen/signing/verifying_process signals need zeroize to be cleared\"\n\nCommits (13 total):\nKey commits include:\n- Added ExternalMu support\n- Removed hardware write access to mu API\n- Moved external_mu register before memory API\n- Stored internal mu to hwif_in\n- Cleared keygen/signing/verify_process when process completes\n- Hard turned off ExternalMu until validation is ready\n- Multiple automated timestamp stamps and branch merges\n\nComments & Activity:\nmojtaba-bisheh (Jan 23, 2025): Opened PR and requested reviews from Nitsirks and upadhyayulakiran\nNitsirks (Jan 28, 2025): Approved changes and merged the PR\n\nStatus:\nMerged on January 28, 2025. The external_mu branch was subsequently deleted.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_adams-bridge_pr77", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_adams-bridge_pr77.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_adams-bridge_pr77", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_adams-bridge_pr77"} {"instance_id": "chipsalliance_adams-bridge_pr79", "issue_text": "# Main fsm in adamsbridge_ctrl module never checks if the last msg is sent or dropped in message interface.\n\n- Source URL: https://github.com/chipsalliance/adams-bridge/issues/78\n\nThe msg interface driven by the adamsbridge_ctrl has a valid(msg_valid_o) and ready(msg_rdy_i). The valid signal is asserted when the message is being loaded to the keccak buffer for the length defined by the sequencer. And this interface is flopped by a clk cycle. Now once the last msg which is set(msg_done and there is no hold) the fsm in the ctrl module makes a transition from `MLDSA_CTRL_MSG_LOAD to `MLDSA_CTRL_FUNC_START with valid and valid data but if there is no ready signal incoming from the present clk cycle then the valid stays asserted till the ready is asserted. But the main fsm never checks if this last msg is ever sent to the keccak and advances in the transitions.\n\nPR Title: aligning msg fsm to msg interface better\nStatus: Merged (January 31, 2025)\nAuthor: Nitsirks\nBranch: user/dev/michnorris/msg_fsm_fix → main\n\nDescription:\nThe primary issue addressed: \"state won't transition to function start until the entire message has been sent\"\n\nCommits (5 total):\n1. Initial commit with FSM alignment improvements\n2. Fixed a typo in sample offset values for pk\n3. Merge of main branch\n4. Fixed privatekey read mechanism for keygen process unlock\n5. Automated pipeline timestamp/hash update\n\nReview Activity:\n- mojtaba-bisheh approved the changes (initially January 28, then again January 31 after additional commits)\n- upadhyayulakiran was requested for review but status remains pending\n\nLinked Issues:\nThis PR may close:\n- Issue #83: \"PRIVKEY_OUT read mechanism\"\n- Issue #78: \"Main fsm in adamsbridge_ctrl module never checks if the last msg is sent or dropped\"\n\nRepository: chipsalliance/adams-bridge\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_adams-bridge_pr79", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_adams-bridge_pr79.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_adams-bridge_pr79", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_adams-bridge_pr79"} {"instance_id": "chipsalliance_adams-bridge_pr82", "issue_text": "# Update directed KATs with pure MLDSA\n\n- Source URL: https://github.com/chipsalliance/adams-bridge/issues/60\n\nPR Title: updated KATs\nStatus: Merged on January 30, 2025\n\nDescription:\nThe PR description provided only states: \"Updated KAT vectors\"\n\nCommits:\n1. 9c6c65b - \"updated KATs\"\n2. 1119aa7 - \"MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/KAT_uvm_update' with updated timestamp and hash after successful run\"\n\nComments:\nekarabu (Jan 29, 2025): \"Updated KAT vectors\"\nCopilot AI (Jan 30, 2025): Could not review the pull request. Five files with unsupported languages were present, including SystemVerilog sequence files and workflow metadata files.\nmojtaba-bisheh (Jan 30, 2025): Approved the changes\n\nLinked Issues:\n- #60 - \"Update directed KATs with pure MLDSA\" (closed by this PR)\n\nReviewers:\n- mojtaba-bisheh: Approved\n- Nitsirks: Awaiting review\n- upadhyayulakiran: Awaiting review\n- Copilot: Reviewed (unable to process files)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_adams-bridge_pr82", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_adams-bridge_pr82.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_adams-bridge_pr82", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_adams-bridge_pr82"} -{"instance_id": "chipsalliance_caliptra-rtl_pr1132", "issue_text": "[2.0] Manu&Prod debug does not grant DMI register access #1129\n\nCaliptra DMI registers are not accessible in Manuf debug and Prod debug security states.\n\nNote: Credit to Nuvoton team for finding this\nThe Caliptra Core JTAG remains locked because the unlock_caliptra_security_state register stays asserted. This causes cptra_security_state_Latched_d.debug_locked and\ncptra_security_state_Latched_f.debug_locked to never reach the required state of both being 0. As a result, the Caliptra Core JTAG cannot be released.\n\nPR Title: [RTL] Fix for security state debug not unlocking after manuf/prod dbg unlock flow patch_v2.1\nPR Number: #1132\nStatus: Merged (November 22, 2025)\n\nDescription:\nThe pull request addresses a bug in the security state capturing logic. According to the author, the change \"removes the else condition from the second flop in the security state capturing logic.\" The static unlock signal was preventing the second register from receiving updated values after completing the debug unlock procedure.\n\nKey Changes:\nThe submission consisted of three commits:\n1. c724a52 - Removed the else term to allow the secondary flop to receive the updated value when manufacturing or production debug unlock is granted\n2. 9e92dc5 - Fixed security state capturing flops for lint by properly observing the reset term\n3. a7d582c - Automated pipeline timestamp and hash update following successful execution\n\nIssue Resolution:\nThis pull request addresses issue #1130, titled \"[2.1] Manu&Prod debug does not grant DMI register access\"\n\nReview & Approval:\n- calebofearth approved the changes on November 22, 2025\n- ekarabu approved the changes on November 22, 2025\n- calebofearth merged the pull request and deleted the feature branch\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-rtl_pr1132", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-rtl_pr1132.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_caliptra-rtl_pr1132", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-rtl_pr1132"} +{"instance_id": "chipsalliance_caliptra-rtl_pr1132", "issue_text": "[2.0] Manu&Prod debug does not grant DMI register access #1129\n\nCaliptra DMI registers are not accessible in Manuf debug and Prod debug security states.\n\nNote: Credit to Nuvoton team for finding this\nThe Caliptra Core JTAG remains locked because the unlock_caliptra_security_state register stays asserted. This causes cptra_security_state_Latched_d.debug_locked and\ncptra_security_state_Latched_f.debug_locked to never reach the required state of both being 0. As a result, the Caliptra Core JTAG cannot be released.\n\nPR Title: [RTL] Fix for security state debug not unlocking after manuf/prod dbg unlock flow patch_v2.1\nPR Number: #1132\nStatus: Merged (November 22, 2025)\n\nDescription:\nThe pull request addresses a bug in the security state capturing logic. According to the author, the change \"removes the else condition from the second flop in the security state capturing logic.\" The static unlock signal was preventing the second register from receiving updated values after completing the debug unlock procedure.\n\nKey Changes:\nThe submission consisted of three commits:\n1. c724a52 - Removed the else term to allow the secondary flop to receive the updated value when manufacturing or production debug unlock is granted\n2. 9e92dc5 - Fixed security state capturing flops for lint by properly observing the reset term\n3. a7d582c - Automated pipeline timestamp and hash update following successful execution\n\nIssue Resolution:\nThis pull request addresses issue #1130, titled \"[2.1] Manu&Prod debug does not grant DMI register access\"\n\nReview & Approval:\n- calebofearth approved the changes on November 22, 2025\n- ekarabu approved the changes on November 22, 2025\n- calebofearth merged the pull request and deleted the feature branch\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-rtl_pr1132", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-rtl_pr1132.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_caliptra-rtl_pr1132", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/chipsalliance_caliptra-rtl_pr1132"} {"instance_id": "chipsalliance_caliptra-rtl_pr757", "issue_text": "# [RTL] AXI Sub Arb fix. Add recovery inf synchros. Export trace signals. Move SS dbg unlock reg to pwrgood.\n\nInstance: chipsalliance_caliptra-rtl_pr757\nSource: https://github.com/chipsalliance/caliptra-rtl/pull/757\nFetched: 2026-04-26\nRepository: chipsalliance/caliptra-rtl\nPull request: #757\nAuthor: calebofearth\nState: closed\nBase branch: msft-daily-20250226\nHead branch: cwhitehead-msft-axi-sub-fix\nCreated: 2025-02-26T06:10:12Z\nUpdated: 2025-02-27T07:10:02Z\nClosed: 2025-02-27T07:09:58Z\nMerged: 2025-02-27T07:09:58Z\n\nAXI Sub Arb fix. \r\n* Resolves #753 \r\n\r\nAdd synchronizers to input signals from subsystem recovery interface. \r\nExport RISC-V trace signals for debug.\r\nMove SS dbg unlock level reg to pwrgood so it's sticky and persists across warm resets without having to redo the debug unlock flow.\n\n## Local Reproducer Notes\n\n# chipsalliance_caliptra-rtl_pr757\n\nMinimal fail-to-pass Verilator case for the AXI subordinate arbiter priority fix.\n\nThe buggy arbiter does not keep write priority while a held final write beat is still in progress, allowing a later read to steal the component interface. The patch keeps priority for any in-progress transfer.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-rtl_pr757", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-rtl_pr757.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_caliptra-rtl_pr757", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-rtl_pr757"} {"instance_id": "chipsalliance_caliptra-rtl_pr791", "issue_text": "# Port connection errors in aes_wrap.sv\n\n- Source URL: https://github.com/chipsalliance/caliptra-rtl/issues/766\n\nIn src/aes/rtl/aes_wrap.sv:\nh2d_intg.a_user.data_intg is driven both in line 69 (as part of a struct) and in line 75.\nunused_idle is 1 bit wide but the source, aes.idle_o (line 87), is of type mubi4_t which is 4 bit wide.\n\nPR Title: updating aes file lists to remove aes_wrap\n\nDescription:\nThe pull request removes aes_wrap from file lists because it is a testbench file rather than a production component. This change addresses issue #766, which documented port connection errors in the aes_wrap.sv file.\n\nAuthor: Nitsirks\nStatus: Merged on March 4, 2025\n\nKey Details:\n- Source Branch: user/dev/michnorris/aes_file_fix\n- Target Branch: msft-daily-20250303\n- Commits: 1 commit (86cfe52)\n- Reviewer Approval: Mojtaba Bisheh approved the changes\n\nRelated Issue:\nIssue #766 titled \"Port connection errors in aes_wrap.sv\" was addressed and closed by this pull request.\n\nComments:\nNitsirks provided a concise explanation: \"aes wrap is a tb file, removing from file lists fixes issue 766\"\n\nThe change was straightforward—removing a testbench file from production file lists to prevent configuration errors and streamline the build process.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-rtl_pr791", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-rtl_pr791.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_caliptra-rtl_pr791", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-rtl_pr791"} -{"instance_id": "chipsalliance_caliptra-rtl_pr883", "issue_text": "# caliptra_prim_macros.svh not found in caliptra_rtl directory\n\n- Source URL: https://github.com/chipsalliance/caliptra-rtl/issues/867\n\nHi Team,\n\nIn the RTL, there's an include for caliptra_prim_macros.svh,\nbut I wasn't able to find this file anywhere in the caliptra_rtl directory.\n\nCould you please let me know where this file is located or how I can obtain it?\n\n![Image](https://github.com/user-attachments/assets/556005c7-f51d-4f1b-961f-4e744c93f9b3)\n\nPR Title: [RTL] GitHub Issues fixes #883\nStatus: Merged on May 30, 2025\n\nDescription:\nThis PR addresses multiple GitHub issues by:\n- Changing INC_ASSERT to CALIPTRA_INC_ASSERT across RTL files\n- Adding ifndef SYNTHESIS guard in axi_if.sv to exclude simulation tasks from synthesis\n- Adding keyvault package dependencies to configuration files\n- Regenerating and updating file lists\n\nKey Changes:\nThe contributor updated assertion macros for consistency, modified compilation directives for tool-agnostic synthesis guards (initially XCELIUM-specific, later generalized to SYNTHESIS), and added missing macro definitions like CALIPTRA_WITHIN_MARGIN.\n\nReview Process:\nCopilot AI noted concerns about macro inconsistencies: \"The change in the assertion guard macro is inconsistent with other files that use CALIPTRA_INC_ASSERT\" and questioned whether SYNTHESIS was the correct condition for task compilation control.\n\nnileshbpat raised similar points about macro usage consistency.\n\nclayton8 approved after addressing concerns, confirming corrections to macro definitions and placements.\n\nupadhyayulakiran approved the final version.\n\nRelated Issues Closed:\n- Issue #811: Simulation tasks conflict with caliptra-ss RTL\n- Issue #867: Missing caliptra_prim_macros.svh file\n- Issue #888: Tasks incompatible with emulators\n\nParticipants: 6 contributors including anjpar (author), clayton8, upadhyayulakiran, nileshbpat, bharatpillilli (merger), and Copilot AI reviewer.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-rtl_pr883", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-rtl_pr883.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_caliptra-rtl_pr883", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-rtl_pr883"} -{"instance_id": "chipsalliance_caliptra-rtl_pr919", "issue_text": "# Simulation tasks in src/axi/rtl/axi_if.sv lines 167-399 conflict with caliptra-ss RTL in lc_ctrl.sv and otp_ctrl.sv\n\n- Source URL: https://github.com/chipsalliance/caliptra-rtl/issues/811\n\nWhen trying to compile caliptra-ss using Cadence Xcelium, there are conflicts between the axi_if simulation tasks (lines 167-399) and functional RTL.\n\nExample error (paths are relative to caliptra-ss top):\nxmelab: *E,ICDPAV (src/lc_ctrl/rtl/lc_ctrl.sv,201|28): Illegal combination of driver and procedural assignment to variable araddr detected (procedural assignment found in task/function rst_mgr at line 177 in file third_party/caliptra-rtl/src/axi/rtl/axi_if.sv).\n\nPR Title: [VAL] Add XCELIUM ifdef to resolve conflict of functional RTL and sim tasks\nPR Number: #919\nStatus: Merged\nAuthor: calebofearth\nMerge Date: July 11, 2025\n\nDescription:\nThis PR replaces #916 to allow running the full pipeline check and resolves issue #811. The change addresses a conflict between simulation tasks in the AXI interface and Caliptra-SS RTL modules.\n\nKey Details:\nRelated Issue: #811 - \"Simulation tasks in src/axi/rtl/axi_if.sv lines 167-399 conflict with caliptra-ss RTL\"\n\nCommits:\n1. Add define to resolve conflict of functional RTL and simulation tasks in Xcelium\n2. Microsoft automated pipeline timestamp and hash update\n\nReviewers & Approvals:\n- upadhyayulakiran (approved July 11)\n- nileshbpat (approved July 11)\n\nTest Status: 77 checks passed\n\nNotable Activity:\nThe PR underwent force-pushes and branch updates before final approval. Initial reviews from both approvers were dismissed on July 10, then re-requested July 11 after updates. The branch `assaf-nt-axi-if-tasks` was deleted following successful merge.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-rtl_pr919", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-rtl_pr919.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_caliptra-rtl_pr919", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-rtl_pr919"} -{"instance_id": "chipsalliance_caliptra-rtl_pr921", "issue_text": "# ECC pubkey check in ECDH\n\n- Source URL: https://github.com/chipsalliance/caliptra-rtl/issues/917\n\nIn the ECDH feature, ecc_dsa_ctrl we check if the input publickey is on the curve but the flag which is set when publickey is valid is not used for any external output indicating the publickey is valid or invalid. Ideally, I expect an error in this whereas the error_flag is not set in this case.\n\n[This line](https://github.com/chipsalliance/caliptra-rtl/blob/3964d76133a48befb0a192501e6f75b290e2d84e/src/ecc/rtl/ecc_dsa_ctrl.sv#L674) needs to be updated to validate pubkey in both verifying and ECDH flow.\n\nPR Title: [RTL/VAL] Fix ECDH pubkey check\nStatus: Merged on July 14, 2025\n\nDescription:\nThe PR addresses a bug in the ECDH feature where the ecc_dsa_ctrl block performs internal validation of input public keys to verify they lie on the curve. The update ensures that invalid public keys properly trigger error conditions rather than proceeding silently.\n\nRelated Issue: #917 - \"ECC pubkey check in ECDH\"\n\nKey Changes:\n- Fixed ECDH public key validation logic\n- Updated ECC test coverage\n- Includes automated pipeline stamps with updated timestamps\n\nReview & Approval:\nReviewers:\n- Nitsirks (approved)\n- calebofearth (approved and merged)\n\nParticipants: mojtaba-bisheh, calebofearth, Nitsirks\n\nCommits (6 total):\nNotable commits include:\n- \"fixed ECDH pbkey check\"\n- \"updated ecc coverage\"\n- Merge commits integrating main branch updates\n- Automated pipeline validation stamps\n\nThe pull request successfully passed 78 checks before merging.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-rtl_pr921", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-rtl_pr921.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_caliptra-rtl_pr921", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-rtl_pr921"} -{"instance_id": "chipsalliance_caliptra-rtl_pr963", "issue_text": "# Undefined macros in AES due to missing includes\n\n- Source URL: https://github.com/chipsalliance/caliptra-rtl/issues/977\n\nOn the 2.1 SS FPGA I hack aes_clp_wrapper.sv to include caliptra_reg_field_defines.svh and kv_macros.svh to avoid undefined macro errors. kv_macros.svh gets included from several of the crypto components like ecc, hmac, and sha512 but not for aes. caliptra_reg_field_defines.svh is included mostly from testbenches and soc_ifc.\nThe workaround for kv_macros.svh is also being used in the 2.0 FPGA.\nMy ask is that we consider if these includes should be added to AES.\n\nError requiring caliptra_reg_field_defines.svh:\n```\nERROR: [Synth 8-10157] use of undefined macro 'AES_REG_DATA_IN_0' [/fourtb/jlmahowa/caliptra-mcu-sw-lock/hw/fpga/caliptra_build/caliptra_fpga_project.gen/sources_1/bd/caliptra_fpga_project_bd/ipshared/25c5/src/aes_clp_wrapper.sv:190]\n```\nError requiring kv_macros.svh:\n```\nERROR: [Synth 8-10157] use of undefined macro 'CALIPTRA_KV_READ_CTRL_REG2STRUCT' [/fourtb/jlmahowa/caliptra-mcu-sw-lock/hw/fpga/caliptra_build/caliptra_fpga_project.gen/sources_1/bd/caliptra_fpga_project_bd/ipshared/978d/src/aes_clp_wrapper.sv:401]\n\nERROR: [Synth 8-10157] use of undefined macro 'CALIPTRA_KV_WRITE_CTRL_REG2STRUCT' [/fourtb/jlmahowa/caliptra-mcu-sw-lock/hw/fpga/caliptra_build/caliptra_fpga_project.gen/sources_1/bd/caliptra_fpga_project_bd/ipshared/978d/src/aes_clp_wrapper.sv:402]```\n\nPR Title: [RTL] Update KeyVault error flagging conditions and AES key manager reg stage\nPR Number: #963\nRepository: chipsalliance/caliptra-rtl\nStatus: Merged (Aug 27, 2025)\nBase Branch: msft-daily-20250827\n\nDescription:\nThe pull request addresses three main objectives:\n1. KeyVault Error Status Management: Modified KeyVault clients to \"latch and preserve error status on kv access instead of using the status from the final beat of the transfer\"\n2. AES Key Zeroization: Updated the AES Caliptra wrapper to \"clear (with zeroes) the intermediate key registering stage when reading a new key from keyvault\"\n3. Header File Inclusion: Added necessary header files to aes_clp_wrapper to resolve issue #977 regarding undefined macros\n\nVerification Approach:\nThe implementation includes:\n- Test cases validating KeyVault client reads with operation interrupts\n- Test assertions for AES zeroization of buffered key values\n- Directed tests for read error recovery scenarios\n\nContributors:\n- calebofearth (primary contributor)\n- Nitsirks (Michael Norris - co-author)\n- bharatpillilli (reviewer)\n\nReview Status:\nSuccessfully approved by both reviewers with 131 of 133 checks passing.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-rtl_pr963", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-rtl_pr963.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_caliptra-rtl_pr963", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-rtl_pr963"} -{"instance_id": "chipsalliance_caliptra-ss_pr550", "issue_text": "# MCU ROM\n\n- Source URL: https://github.com/chipsalliance/caliptra-ss/issues/533\n\nwhy does the MCU ROM has an AXI wr interface (rom is not wettable...)\n\nPR Title: [DOC][VAL] Disconnect MCU ROM wr path in TB; clarify MCU ROM if connection req and SRAM error handling sections\nPR Number: #550\nStatus: Merged\nMerge Date: June 26, 2025\nMerged By: calebofearth\nBranch: cwhitehead-msft-spec-upd-err-handle → main\n\nDescription:\nThe pull request addresses two related issues:\n- chipsalliance/Caliptra#320\n- caliptra-ss#533 (MCU ROM)\n\nThe changes involve documentation and validation updates focused on modifying MCU ROM write path connectivity in testbenches, clarifying MCU ROM connection requirements, and refining SRAM error handling documentation sections.\n\nKey Commits (15 total):\nNotable changes include:\n- Fixed typo in SS port naming\n- Updated memory export interface table and documentation\n- Added example register map pages link to README\n- Revised SRAM error/recovery flow section with clarifications\n- Updated ROM interface connectivity requirements with write path disabled\n- Disconnected write-path for MCU ROM\n- Renamed SRAM error handling section to emphasize example-only flow\n- Reduced unnecessary verbiage in error handling specifications\n- Regenerated table of contents\n\nReviews & Approvals:\n- bharatpillilli: Approved changes (with prior comment thread)\n- Nitsirks: Approved changes\n\nParticipants: 3 (calebofearth, bharatpillilli, Nitsirks)\n\nTechnical Details:\nAll 8 checks passed successfully before merge.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-ss_pr550", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-ss_pr550.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_caliptra-ss_pr550", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-ss_pr550"} -{"instance_id": "chipsalliance_caliptra-ss_pr565", "issue_text": "# VCS Error in testbench file fc_lcc_tb_services\n\n- Source URL: https://github.com/chipsalliance/caliptra-ss/issues/484\n\nIn the file caliptra_ss/src/integration/testbench/fc_lcc_tb_services.sv on line 34 is the statement\n\nlogic lcc_external_clk_req = 1'b0;\n\nThis signal is also used in an always block with non-blocking statements. It is also initialized there with the negedge of reset. For a least our version of VCS this is causing an error. To fix this require removing the initialization in the logic statement.\n\nlogic lcc_external_clk_req;\n\nPR Title: Coverage updates and fixed gh484\nStatus: Merged (July 3, 2025)\nAuthor: nileshbpat\nBranch: pateln_fix_gh484 → main\n\nDescription:\nThe PR addressed two main objectives:\n1. Updated coverage documentation - Refreshed links to coverage reports and added analysis notes from the latest coverage report findings.\n2. Fixed Issue #484 - Resolved a VCS error that was occurring in the testbench file fc_lcc_tb_services, specifically a \"multiple driver issue.\"\n\nCommits (4 total):\n- Resolved multiple driver issue\n- Updated Coverage links\n- Added Coverage Analysis notes and links from latest coverage reports\n- Microsoft automated pipeline timestamp/hash stamp\n\nReviews & Approvals:\nbharatpillilli approved the changes after reviewing the documentation updates.\ncalebofearth previously approved but the review was dismissed after subsequent commits.\n\nRelated Issue:\nThis PR successfully closes: \"VCS Error in testbench file fc_lcc_tb_services #484\"\n\nDownstream Impact:\nThis PR was later incorporated into larger feature merges, including PR #597 (\"MCI-LCC Updates with VolatileLock and Debug Connection\").\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-ss_pr565", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-ss_pr565.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_caliptra-ss_pr565", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-ss_pr565"} +{"instance_id": "chipsalliance_caliptra-rtl_pr883", "issue_text": "# caliptra_prim_macros.svh not found in caliptra_rtl directory\n\n- Source URL: https://github.com/chipsalliance/caliptra-rtl/issues/867\n\nHi Team,\n\nIn the RTL, there's an include for caliptra_prim_macros.svh,\nbut I wasn't able to find this file anywhere in the caliptra_rtl directory.\n\nCould you please let me know where this file is located or how I can obtain it?\n\n![Image](https://github.com/user-attachments/assets/556005c7-f51d-4f1b-961f-4e744c93f9b3)\n\nPR Title: [RTL] GitHub Issues fixes #883\nStatus: Merged on May 30, 2025\n\nDescription:\nThis PR addresses multiple GitHub issues by:\n- Changing INC_ASSERT to CALIPTRA_INC_ASSERT across RTL files\n- Adding ifndef SYNTHESIS guard in axi_if.sv to exclude simulation tasks from synthesis\n- Adding keyvault package dependencies to configuration files\n- Regenerating and updating file lists\n\nKey Changes:\nThe contributor updated assertion macros for consistency, modified compilation directives for tool-agnostic synthesis guards (initially XCELIUM-specific, later generalized to SYNTHESIS), and added missing macro definitions like CALIPTRA_WITHIN_MARGIN.\n\nReview Process:\nCopilot AI noted concerns about macro inconsistencies: \"The change in the assertion guard macro is inconsistent with other files that use CALIPTRA_INC_ASSERT\" and questioned whether SYNTHESIS was the correct condition for task compilation control.\n\nnileshbpat raised similar points about macro usage consistency.\n\nclayton8 approved after addressing concerns, confirming corrections to macro definitions and placements.\n\nupadhyayulakiran approved the final version.\n\nRelated Issues Closed:\n- Issue #811: Simulation tasks conflict with caliptra-ss RTL\n- Issue #867: Missing caliptra_prim_macros.svh file\n- Issue #888: Tasks incompatible with emulators\n\nParticipants: 6 contributors including anjpar (author), clayton8, upadhyayulakiran, nileshbpat, bharatpillilli (merger), and Copilot AI reviewer.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-rtl_pr883", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-rtl_pr883.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_caliptra-rtl_pr883", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/chipsalliance_caliptra-rtl_pr883"} +{"instance_id": "chipsalliance_caliptra-rtl_pr919", "issue_text": "# Simulation tasks in src/axi/rtl/axi_if.sv lines 167-399 conflict with caliptra-ss RTL in lc_ctrl.sv and otp_ctrl.sv\n\n- Source URL: https://github.com/chipsalliance/caliptra-rtl/issues/811\n\nWhen trying to compile caliptra-ss using Cadence Xcelium, there are conflicts between the axi_if simulation tasks (lines 167-399) and functional RTL.\n\nExample error (paths are relative to caliptra-ss top):\nxmelab: *E,ICDPAV (src/lc_ctrl/rtl/lc_ctrl.sv,201|28): Illegal combination of driver and procedural assignment to variable araddr detected (procedural assignment found in task/function rst_mgr at line 177 in file third_party/caliptra-rtl/src/axi/rtl/axi_if.sv).\n\nPR Title: [VAL] Add XCELIUM ifdef to resolve conflict of functional RTL and sim tasks\nPR Number: #919\nStatus: Merged\nAuthor: calebofearth\nMerge Date: July 11, 2025\n\nDescription:\nThis PR replaces #916 to allow running the full pipeline check and resolves issue #811. The change addresses a conflict between simulation tasks in the AXI interface and Caliptra-SS RTL modules.\n\nKey Details:\nRelated Issue: #811 - \"Simulation tasks in src/axi/rtl/axi_if.sv lines 167-399 conflict with caliptra-ss RTL\"\n\nCommits:\n1. Add define to resolve conflict of functional RTL and simulation tasks in Xcelium\n2. Microsoft automated pipeline timestamp and hash update\n\nReviewers & Approvals:\n- upadhyayulakiran (approved July 11)\n- nileshbpat (approved July 11)\n\nTest Status: 77 checks passed\n\nNotable Activity:\nThe PR underwent force-pushes and branch updates before final approval. Initial reviews from both approvers were dismissed on July 10, then re-requested July 11 after updates. The branch `assaf-nt-axi-if-tasks` was deleted following successful merge.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-rtl_pr919", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-rtl_pr919.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_caliptra-rtl_pr919", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/chipsalliance_caliptra-rtl_pr919"} +{"instance_id": "chipsalliance_caliptra-rtl_pr921", "issue_text": "# ECC pubkey check in ECDH\n\n- Source URL: https://github.com/chipsalliance/caliptra-rtl/issues/917\n\nIn the ECDH feature, ecc_dsa_ctrl we check if the input publickey is on the curve but the flag which is set when publickey is valid is not used for any external output indicating the publickey is valid or invalid. Ideally, I expect an error in this whereas the error_flag is not set in this case.\n\n[This line](https://github.com/chipsalliance/caliptra-rtl/blob/3964d76133a48befb0a192501e6f75b290e2d84e/src/ecc/rtl/ecc_dsa_ctrl.sv#L674) needs to be updated to validate pubkey in both verifying and ECDH flow.\n\nPR Title: [RTL/VAL] Fix ECDH pubkey check\nStatus: Merged on July 14, 2025\n\nDescription:\nThe PR addresses a bug in the ECDH feature where the ecc_dsa_ctrl block performs internal validation of input public keys to verify they lie on the curve. The update ensures that invalid public keys properly trigger error conditions rather than proceeding silently.\n\nRelated Issue: #917 - \"ECC pubkey check in ECDH\"\n\nKey Changes:\n- Fixed ECDH public key validation logic\n- Updated ECC test coverage\n- Includes automated pipeline stamps with updated timestamps\n\nReview & Approval:\nReviewers:\n- Nitsirks (approved)\n- calebofearth (approved and merged)\n\nParticipants: mojtaba-bisheh, calebofearth, Nitsirks\n\nCommits (6 total):\nNotable commits include:\n- \"fixed ECDH pbkey check\"\n- \"updated ecc coverage\"\n- Merge commits integrating main branch updates\n- Automated pipeline validation stamps\n\nThe pull request successfully passed 78 checks before merging.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-rtl_pr921", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-rtl_pr921.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_caliptra-rtl_pr921", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/chipsalliance_caliptra-rtl_pr921"} +{"instance_id": "chipsalliance_caliptra-rtl_pr963", "issue_text": "# Undefined macros in AES due to missing includes\n\n- Source URL: https://github.com/chipsalliance/caliptra-rtl/issues/977\n\nOn the 2.1 SS FPGA I hack aes_clp_wrapper.sv to include caliptra_reg_field_defines.svh and kv_macros.svh to avoid undefined macro errors. kv_macros.svh gets included from several of the crypto components like ecc, hmac, and sha512 but not for aes. caliptra_reg_field_defines.svh is included mostly from testbenches and soc_ifc.\nThe workaround for kv_macros.svh is also being used in the 2.0 FPGA.\nMy ask is that we consider if these includes should be added to AES.\n\nError requiring caliptra_reg_field_defines.svh:\n```\nERROR: [Synth 8-10157] use of undefined macro 'AES_REG_DATA_IN_0' [/fourtb/jlmahowa/caliptra-mcu-sw-lock/hw/fpga/caliptra_build/caliptra_fpga_project.gen/sources_1/bd/caliptra_fpga_project_bd/ipshared/25c5/src/aes_clp_wrapper.sv:190]\n```\nError requiring kv_macros.svh:\n```\nERROR: [Synth 8-10157] use of undefined macro 'CALIPTRA_KV_READ_CTRL_REG2STRUCT' [/fourtb/jlmahowa/caliptra-mcu-sw-lock/hw/fpga/caliptra_build/caliptra_fpga_project.gen/sources_1/bd/caliptra_fpga_project_bd/ipshared/978d/src/aes_clp_wrapper.sv:401]\n\nERROR: [Synth 8-10157] use of undefined macro 'CALIPTRA_KV_WRITE_CTRL_REG2STRUCT' [/fourtb/jlmahowa/caliptra-mcu-sw-lock/hw/fpga/caliptra_build/caliptra_fpga_project.gen/sources_1/bd/caliptra_fpga_project_bd/ipshared/978d/src/aes_clp_wrapper.sv:402]```\n\nPR Title: [RTL] Update KeyVault error flagging conditions and AES key manager reg stage\nPR Number: #963\nRepository: chipsalliance/caliptra-rtl\nStatus: Merged (Aug 27, 2025)\nBase Branch: msft-daily-20250827\n\nDescription:\nThe pull request addresses three main objectives:\n1. KeyVault Error Status Management: Modified KeyVault clients to \"latch and preserve error status on kv access instead of using the status from the final beat of the transfer\"\n2. AES Key Zeroization: Updated the AES Caliptra wrapper to \"clear (with zeroes) the intermediate key registering stage when reading a new key from keyvault\"\n3. Header File Inclusion: Added necessary header files to aes_clp_wrapper to resolve issue #977 regarding undefined macros\n\nVerification Approach:\nThe implementation includes:\n- Test cases validating KeyVault client reads with operation interrupts\n- Test assertions for AES zeroization of buffered key values\n- Directed tests for read error recovery scenarios\n\nContributors:\n- calebofearth (primary contributor)\n- Nitsirks (Michael Norris - co-author)\n- bharatpillilli (reviewer)\n\nReview Status:\nSuccessfully approved by both reviewers with 131 of 133 checks passing.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-rtl_pr963", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-rtl_pr963.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_caliptra-rtl_pr963", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/chipsalliance_caliptra-rtl_pr963"} +{"instance_id": "chipsalliance_caliptra-ss_pr550", "issue_text": "# MCU ROM\n\n- Source URL: https://github.com/chipsalliance/caliptra-ss/issues/533\n\nwhy does the MCU ROM has an AXI wr interface (rom is not wettable...)\n\nPR Title: [DOC][VAL] Disconnect MCU ROM wr path in TB; clarify MCU ROM if connection req and SRAM error handling sections\nPR Number: #550\nStatus: Merged\nMerge Date: June 26, 2025\nMerged By: calebofearth\nBranch: cwhitehead-msft-spec-upd-err-handle → main\n\nDescription:\nThe pull request addresses two related issues:\n- chipsalliance/Caliptra#320\n- caliptra-ss#533 (MCU ROM)\n\nThe changes involve documentation and validation updates focused on modifying MCU ROM write path connectivity in testbenches, clarifying MCU ROM connection requirements, and refining SRAM error handling documentation sections.\n\nKey Commits (15 total):\nNotable changes include:\n- Fixed typo in SS port naming\n- Updated memory export interface table and documentation\n- Added example register map pages link to README\n- Revised SRAM error/recovery flow section with clarifications\n- Updated ROM interface connectivity requirements with write path disabled\n- Disconnected write-path for MCU ROM\n- Renamed SRAM error handling section to emphasize example-only flow\n- Reduced unnecessary verbiage in error handling specifications\n- Regenerated table of contents\n\nReviews & Approvals:\n- bharatpillilli: Approved changes (with prior comment thread)\n- Nitsirks: Approved changes\n\nParticipants: 3 (calebofearth, bharatpillilli, Nitsirks)\n\nTechnical Details:\nAll 8 checks passed successfully before merge.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-ss_pr550", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-ss_pr550.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_caliptra-ss_pr550", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/chipsalliance_caliptra-ss_pr550"} +{"instance_id": "chipsalliance_caliptra-ss_pr565", "issue_text": "# VCS Error in testbench file fc_lcc_tb_services\n\n- Source URL: https://github.com/chipsalliance/caliptra-ss/issues/484\n\nIn the file caliptra_ss/src/integration/testbench/fc_lcc_tb_services.sv on line 34 is the statement\n\nlogic lcc_external_clk_req = 1'b0;\n\nThis signal is also used in an always block with non-blocking statements. It is also initialized there with the negedge of reset. For a least our version of VCS this is causing an error. To fix this require removing the initialization in the logic statement.\n\nlogic lcc_external_clk_req;\n\nPR Title: Coverage updates and fixed gh484\nStatus: Merged (July 3, 2025)\nAuthor: nileshbpat\nBranch: pateln_fix_gh484 → main\n\nDescription:\nThe PR addressed two main objectives:\n1. Updated coverage documentation - Refreshed links to coverage reports and added analysis notes from the latest coverage report findings.\n2. Fixed Issue #484 - Resolved a VCS error that was occurring in the testbench file fc_lcc_tb_services, specifically a \"multiple driver issue.\"\n\nCommits (4 total):\n- Resolved multiple driver issue\n- Updated Coverage links\n- Added Coverage Analysis notes and links from latest coverage reports\n- Microsoft automated pipeline timestamp/hash stamp\n\nReviews & Approvals:\nbharatpillilli approved the changes after reviewing the documentation updates.\ncalebofearth previously approved but the review was dismissed after subsequent commits.\n\nRelated Issue:\nThis PR successfully closes: \"VCS Error in testbench file fc_lcc_tb_services #484\"\n\nDownstream Impact:\nThis PR was later incorporated into larger feature merges, including PR #597 (\"MCI-LCC Updates with VolatileLock and Debug Connection\").\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-ss_pr565", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-ss_pr565.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_caliptra-ss_pr565", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/chipsalliance_caliptra-ss_pr565"} {"instance_id": "chipsalliance_caliptra-ss_pr590", "issue_text": "# Using axi wdata without wvalid qualification in TLUL\n\n- Source URL: https://github.com/chipsalliance/caliptra-ss/issues/535\n\nHi Caliptra team,\n In Caliptra SS simulation, we encounter X value issue. By tracing the code, we found that there could be an issue in the RTL code: caliptra-ss-main/src/tlul/rtl/tlul_cmd_ingt_chk.sv ( line 44 ).\n\n\n![Image](https://github.com/user-attachments/assets/c0ae44cc-8335-4501-8b44-e8aec0334985)\n\nThe issue is using \"data_err\" without checking qualification of AXI wvalid. \"tl_i.a_valid\" is from AXI awvalid or arvalid, but \"data_err\" is from AXI wdata, so there could be scenerio when AXI arvalid == 1, but wvalid == 0, wdata is unknown.\n\n\n Could you help to check whether this is a real issue ?\n\n\nBest Regards\nDerek Wang\n\nPR Title: [BUG FIX] Drive a_data with zeroes for reads instead of wdata, which may be arbitrary\nPR Number: #590\nStatus: Merged\nMerged by: nileshbpat on July 23, 2025\n\nDescription:\nThe PR resolves issue #535 regarding improper handling of write data signals during read operations. The submitter notes this bug \"remain undetected so far as avery interconnect VIP drives zero instead of x for the undriven IOs.\"\n\nCommits (7 total):\n1. Drive 0 wdata for read commands\n2. Match the conditional assignment convention elsewhere in file\n3. Fix a force statement on sub2tlul wdata signal so it's not always driven\n4. Use more precise reg addr\n5. Actually fail the test when an error is observed\n6. Use a local a_data signal to allow TB to inject ECC errors at TL a_data\n7. MICROSOFT AUTOMATED PIPELINE: Stamp 'cwhitehead-msft-tlul-X-fix' with updated timestamp and hash after successful run\n\nReview & Approval:\nReviewer: upadhyayulakiran approved the changes on July 23, 2025\n\nLinked Issue:\nTitle: Using axi wdata without wvalid qualification in TLUL (Issue #535)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-ss_pr590", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-ss_pr590.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_caliptra-ss_pr590", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-ss_pr590"} -{"instance_id": "chipsalliance_caliptra-ss_pr750", "issue_text": "# [Val] FC Test uses local register definitions\n\n- Source URL: https://github.com/chipsalliance/caliptra-ss/issues/703\n\nUpdate this test such that each fuse map update does not break its structure.\n\nsrc/integration/test_suites/caliptra_ss_fuse_ctrl_read_lock/caliptra_ss_fuse_ctrl_read_lock.c\n\n\n\"Image\"\n\n\nThere are similar issues in these tests too:\n\nsrc/integration/test_suites/caliptra_ss_fuse_ctrl_test_unlocked0_prov/caliptra_ss_fuse_ctrl_test_unlocked0_prov.c\nsrc/integration/test_suites/caliptra_ss_fuse_ctrl_manuf_prod_prov/caliptra_ss_fuse_ctrl_manuf_prod_prov.c\n\nThis test uses hard-coded fuse map address to separate UDS and FE from the other partitions. See the if condition with 0x40 and 0xD0\n\nPR Title: [fuse_ctrl,dv] Assorted cleanups to how FC tests look at magic registers\nPR Number: #750\nStatus: Merged\n\nDescription:\nThe author, rswarbrick, created this PR while tidying up related work in PR #727. The changes were deemed \"safe to apply separately\" despite uncertainty about the correctness of some modifications in the parent PR.\n\nCommits (5 total):\n1. Create fuse_ctrl_mmap.c - Prevents fuse_ctrl_mmap.h from defining instantiated objects that would cause linker failures when included in multiple compilation units.\n2. Add documentation for address range type - No functional changes; improves clarity of address range logic in the package.\n3. Tidy up tests for Caliptra secret addresses - Updates outdated values in caliptra_ss_fuse_ctrl_manuf_prod_prov from a prior change (275521b1) and applies consistent magic number sourcing to related tests.\n4. Avoid hard-coding read lock partitions - Removes hard-coded partition values by generating a template-based map that pulls actual addresses from soc_mmap.h at compile time.\n5. Automated pipeline stamp - Microsoft's automated pipeline updated timestamp and hash after successful test run.\n\nReview Activity:\nandreaskurth approved with comment: \"LGTM, thanks for fixing these tests\" (later re-approved after pipeline completion).\nekarabu merged the PR on September 30, 2025.\n\nLinked Issue:\nThis PR may close issue #703: \"[Val] FC Test uses local register definitions\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-ss_pr750", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-ss_pr750.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_caliptra-ss_pr750", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-ss_pr750"} -{"instance_id": "chipsalliance_caliptra-ss_pr838", "issue_text": "# [Question] Regarding FcAxiFilterDaiAccessError_A assertion\n\n- Source URL: https://github.com/chipsalliance/caliptra-ss/issues/833\n\nHello calipra team,\n\nI have found FcAxiFilterDaiAccessError_A assertion error during caliptra_ss_fuse_ctrl_axi_id test when a valid write follows a discard write.\n\nhttps://github.com/chipsalliance/caliptra-ss/blob/28ef1cefb5bfcf22e258419cd5db8f836527042f/src/integration/asserts/caliptra_ss_top_sva.sv#L75-L78\n\nI think that discard_fuse_write signal remains asserted for two more cycles after otp_operation_done toggles, so the assertion impacts on the next valid write as well.\nTherefore, I’ve just tried it as below.\nI’d appreciate your feedback on these changes.\n\n ```\n`CALIPTRA_ASSERT(FcAxiFilterDaiAccessError_A,\n dai_write_req ##1 // <=== add\n `FC_PATH.discard_fuse_write ##1\n `FC_PATH.otp_operation_done[->1] |=>\n `FC_PATH.u_otp_ctrl_dai.error_o == {AccessError})\n\n```\nRegards,\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-ss_pr838", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-ss_pr838.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_caliptra-ss_pr838", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-ss_pr838"} +{"instance_id": "chipsalliance_caliptra-ss_pr750", "issue_text": "# [Val] FC Test uses local register definitions\n\n- Source URL: https://github.com/chipsalliance/caliptra-ss/issues/703\n\nUpdate this test such that each fuse map update does not break its structure.\n\nsrc/integration/test_suites/caliptra_ss_fuse_ctrl_read_lock/caliptra_ss_fuse_ctrl_read_lock.c\n\n\n\"Image\"\n\n\nThere are similar issues in these tests too:\n\nsrc/integration/test_suites/caliptra_ss_fuse_ctrl_test_unlocked0_prov/caliptra_ss_fuse_ctrl_test_unlocked0_prov.c\nsrc/integration/test_suites/caliptra_ss_fuse_ctrl_manuf_prod_prov/caliptra_ss_fuse_ctrl_manuf_prod_prov.c\n\nThis test uses hard-coded fuse map address to separate UDS and FE from the other partitions. See the if condition with 0x40 and 0xD0\n\nPR Title: [fuse_ctrl,dv] Assorted cleanups to how FC tests look at magic registers\nPR Number: #750\nStatus: Merged\n\nDescription:\nThe author, rswarbrick, created this PR while tidying up related work in PR #727. The changes were deemed \"safe to apply separately\" despite uncertainty about the correctness of some modifications in the parent PR.\n\nCommits (5 total):\n1. Create fuse_ctrl_mmap.c - Prevents fuse_ctrl_mmap.h from defining instantiated objects that would cause linker failures when included in multiple compilation units.\n2. Add documentation for address range type - No functional changes; improves clarity of address range logic in the package.\n3. Tidy up tests for Caliptra secret addresses - Updates outdated values in caliptra_ss_fuse_ctrl_manuf_prod_prov from a prior change (275521b1) and applies consistent magic number sourcing to related tests.\n4. Avoid hard-coding read lock partitions - Removes hard-coded partition values by generating a template-based map that pulls actual addresses from soc_mmap.h at compile time.\n5. Automated pipeline stamp - Microsoft's automated pipeline updated timestamp and hash after successful test run.\n\nReview Activity:\nandreaskurth approved with comment: \"LGTM, thanks for fixing these tests\" (later re-approved after pipeline completion).\nekarabu merged the PR on September 30, 2025.\n\nLinked Issue:\nThis PR may close issue #703: \"[Val] FC Test uses local register definitions\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-ss_pr750", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-ss_pr750.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_caliptra-ss_pr750", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/chipsalliance_caliptra-ss_pr750"} +{"instance_id": "chipsalliance_caliptra-ss_pr838", "issue_text": "# [Question] Regarding FcAxiFilterDaiAccessError_A assertion\n\n- Source URL: https://github.com/chipsalliance/caliptra-ss/issues/833\n\nHello calipra team,\n\nI have found FcAxiFilterDaiAccessError_A assertion error during caliptra_ss_fuse_ctrl_axi_id test when a valid write follows a discard write.\n\nhttps://github.com/chipsalliance/caliptra-ss/blob/28ef1cefb5bfcf22e258419cd5db8f836527042f/src/integration/asserts/caliptra_ss_top_sva.sv#L75-L78\n\nI think that discard_fuse_write signal remains asserted for two more cycles after otp_operation_done toggles, so the assertion impacts on the next valid write as well.\nTherefore, I’ve just tried it as below.\nI’d appreciate your feedback on these changes.\n\n ```\n`CALIPTRA_ASSERT(FcAxiFilterDaiAccessError_A,\n dai_write_req ##1 // <=== add\n `FC_PATH.discard_fuse_write ##1\n `FC_PATH.otp_operation_done[->1] |=>\n `FC_PATH.u_otp_ctrl_dai.error_o == {AccessError})\n\n```\nRegards,\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-ss_pr838", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-ss_pr838.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_caliptra-ss_pr838", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/chipsalliance_caliptra-ss_pr838"} {"instance_id": "chipsalliance_i3c-core_pr35", "issue_text": "# Reading the TTI RX_DESC_QUEUE_PORT when there is no descriptor in the queue seems to crash\n\n- Source URL: https://github.com/chipsalliance/i3c-core/issues/32\n\nOn the FPGA, this will hard crash the host when trying to read that register if the interrupt has not been set.\n\n\n\n\n\n\n\n\n\n\n\n# GitHub Issue #32\n\n## Issue Title\nReading the TTI RX_DESC_QUEUE_PORT when there is no descriptor in the queue seems to crash\n\n## Issue Description\n\"On the FPGA, this will hard crash the host when trying to read that register if the interrupt has not been set.\"\n\n## Author\nswenson\n\n## Status\nClosed (linked to PR #35)\n\n## Additional Details\n- No assignees\n- No labels or type classification\n- Opened on April 2, 2025\n- No comments visible in the provided content\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_i3c-core_pr35", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_i3c-core_pr35.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_i3c-core_pr35", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_i3c-core_pr35"} {"instance_id": "chipsalliance_sv-tests_pr7781", "issue_text": "# Foreach test is not synthesizable\n\n- Source URL: https://github.com/chipsalliance/sv-tests/issues/7780\n\nThe test case used for the `foreach` construct is non-synt.\n\nA new synthesizable testcase is needed to validate if the construct is correctly recognized in synth-only software\n\n/assign me\n\n\n\n\n\n\n\n# GitHub Issue #7780: Foreach test is not synthesizable\n\n## Author\n@matlupi (opened November 4, 2025)\n\n## Issue Description\n\"The test case used for the `foreach` construct is non-synt. A new synthesizable testcase is needed to validate if the construct is correctly recognized in synth-only software\"\n\nThe reporter assigned the issue to themselves.\n\n## Related PR\nPR #7781 was opened to address this issue.\n\n## Summary\nThis issue identifies that the existing `foreach` test in the sv-tests repository lacks synthesizability. The requester is seeking a replacement test case that can be properly validated by synthesis-focused tools and software.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_sv-tests_pr7781", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_sv-tests_pr7781.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/chipsalliance_sv-tests_pr7781", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_sv-tests_pr7781"} {"instance_id": "darklife_darkriscv_pr95", "issue_text": "# Add cycle and instret counters (\"Zicntr\" extension)\n\n- Source URL: https://github.com/darklife/darkriscv/issues/94\n\nHello,\n\nThe ISA suggests it should be implemented, as it serves basic performance analysis. I need it too for Dhrystone benchmark.\nI can see that clocks and instructions are being counted with `__PERFMETER__` enabled. Why not make them accessible via CSRs?\n\n\n\n\n\n\n\n# GitHub Issue #94: Add cycle and instret counters (\"Zicntr\" extension)\n\n## Issue Body\nThe reporter notes that the RISC-V ISA suggests implementing cycle and instruction counters for basic performance analysis. They mention that clock and instruction counting already exist when `__PERFMETER__` is enabled, but these metrics should be made accessible through Control and Status Registers (CSRs). The requester needs this functionality for Dhrystone benchmark testing.\n\n## Status\nClosed (with associated PR #95)\n\n## Assignees\nsamsoniuk, MrJake222\n\n## Notes\nThe webpage content provided does not include visible comments from other users or additional linked issue details beyond the issue title and description shown.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/darklife_darkriscv_pr95", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/darklife_darkriscv_pr95.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/darklife_darkriscv_pr95", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/darklife_darkriscv_pr95"} @@ -218,7 +218,7 @@ {"instance_id": "esa-tu-darmstadt_tapasco_pr105", "issue_text": "Don't choke on patched Vivado versions #48\n\nCurrently, when using a patched Vivado version, Tapasco fails at least at two places:\n\nCould not find /scratch/mio/tapasco_f1/common/common_2018.2_AR71715.tcl, Vivado 2018.2_AR71715 is not supported yet!\n\nWhile this can easily be resolved by placing a symlink to the common_2018.2.tcl file, there is also a problem with the tapasco_status.json which causes Tapasco (or rather the JSON Parser) to throw an Exception and exit:\n\n \"Versions\" : [{\n \"Software\" : \"Vivado\",\n \"Year\" : 2018_AR71715,\n \"Release\" : 2_AR71715\nResults in:\n\ncom.fasterxml.jackson.core.JsonParseException: Unexpected character ('_' (code 95))\n\n\n# Pull Request #105 Summary\n\n## PR Title\nReplace hard coded status core with dynamic version\n\n## PR Description\n- Replaces the custom, hard-coded status core format with a protobuf version\n- Enables easily adding information to the status core for use by runtime and driver\n- Adds necessary dependencies\n- Uses custom statically-linked rust executable to translate JSON from TaPaSCo flow to protobuf binary\n- Fixes all examples and tests them\n- Makes memory map from user space completely platform independent; driver translates virtual to device-specific addresses\n- Closes issue #48: \"Don't choke on patched Vivado versions\"\n- Closes issue #83: \"Replace custom status core format with something well known\"\n\n## Key Comments\n- cahz (approver): \"Tested with local memory, looks good to me.\"\n- m-ober (reviewer): Left review comments on file `runtime/kernel/dma/blue_dma.c`\n\n## Commits\n36 commits across the feature branch, including work on FlatBuffers conversion, protobuf implementation, driver modifications, and platform-independence improvements.\n\n## Status\nMerged on July 5, 2019\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/esa-tu-darmstadt_tapasco_pr105", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/esa-tu-darmstadt_tapasco_pr105.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/esa-tu-darmstadt_tapasco_pr105", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/esa-tu-darmstadt_tapasco_pr105"} {"instance_id": "esa-tu-darmstadt_tapasco_pr186", "issue_text": "# HBM Adressing\n\n- Source URL: https://github.com/esa-tu-darmstadt/tapasco/issues/180\n\nWhen connecting multiple PEs to the HBM, only one can correctly access it's HBM memory block.\nThis is because the adresses of the HBM blocks do not all start at 0. Instead all HBM blocks together form a continous address space.\nTaPaSCo should automatically offset the addresses of each PE to the address range of the HBM block it is connected to. Then the address space the PEs \"see\" always starts at 0.\n\n\n\n\n\n\n\n\n\n\n# GitHub Issue #180: HBM Addressing\n\n## Issue Title\nHBM Adressing #180\n\n## Issue Status\nClosed (via PR #186)\n\n## Assigned to\nwirthjohannes\n\n## Labels\nbug\n\n## Milestone\n2020.4\n\n## Issue Description\nThe issue describes a problem with multiple Processing Elements (PEs) connected to HBM memory. When several PEs connect to the same HBM, only one PE can correctly access its memory block because:\n\n> \"the adresses of the HBM blocks do not all start at 0. Instead all HBM blocks together form a continous address space\"\n\nProposed Solution: TaPaSCo should automatically offset addresses for each PE to match the address range of its connected HBM block, ensuring each PE's address space starts at 0.\n\n## Key Details\n- Created: April 28, 2020\n- Repository: esa-tu-darmstadt/tapasco\n- Categorized as a bug (\"Something isn't working\")\n\nNote: No pull request description, comments, or additional linked issues were provided in the source content.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/esa-tu-darmstadt_tapasco_pr186", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/esa-tu-darmstadt_tapasco_pr186.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/esa-tu-darmstadt_tapasco_pr186", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/esa-tu-darmstadt_tapasco_pr186"} {"instance_id": "gtaylormb_opl3_fpga_pr51", "issue_text": "# Linting for boosting RTL quality and QA consistency\n\n- Source URL: https://github.com/gtaylormb/opl3_fpga/issues/48\n\n## Issue Title\nLinting for boosting RTL quality and QA consistency\n\n## Issue Description\nThe issue body referenced a related discussion from the openCologne project (https://github.com/chili-chips-ba/openCologne/issues/16). The issue is focused on implementing linting tools and processes to improve the quality and consistency of the RTL (Register Transfer Level) code within this FPGA design project.\n\n## Issue Comments\nNone visible.\n\n## Issue Metadata\n- Status: Closed (resolved via PR #51)\n- Author: chili-chips-ba\n- Created: June 12, 2024\n- Assignees: None\n- Labels: None\n- Milestone: None\n\n## Linked Issues / PRs\n- PR #51 — resolves this issue\n- Related discussion: openCologne #16\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/gtaylormb_opl3_fpga_pr51", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/gtaylormb_opl3_fpga_pr51.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/gtaylormb_opl3_fpga_pr51", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/gtaylormb_opl3_fpga_pr51"} -{"instance_id": "hdl-util_hdmi_pr12", "issue_text": "# Source tweaks for clean compilation on Verilator\n\nInstance: hdl-util_hdmi_pr12\nSource: https://github.com/hdl-util/hdmi/pull/12\nFetched: 2026-04-26\nRepository: hdl-util/hdmi\nPull request: #12\nAuthor: jamesbowman\nState: closed\nBase branch: master\nHead branch: master\nCreated: 2020-07-17T20:58:39Z\nUpdated: 2020-07-18T01:06:15Z\nClosed: 2020-07-18T01:06:15Z\nMerged: 2020-07-18T01:06:15Z\n\nHi Sameer, I'm working on a verification testbench for your HDMI code base.\r\nThis first commit makes some small syntax changes to get to clean build with Verilator and Icarus Verilog.\r\n\r\nThe next steps are:\r\n * a testbench that dumps the 3 x 10 bit TMDS values for N clocks\r\n * a stream analyzer that verifies HDMI against the spec and the settings\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/hdl-util_hdmi_pr12", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/hdl-util_hdmi_pr12.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/hdl-util_hdmi_pr12", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/hdl-util_hdmi_pr12"} +{"instance_id": "hdl-util_hdmi_pr12", "issue_text": "# Source tweaks for clean compilation on Verilator\n\nInstance: hdl-util_hdmi_pr12\nSource: https://github.com/hdl-util/hdmi/pull/12\nFetched: 2026-04-26\nRepository: hdl-util/hdmi\nPull request: #12\nAuthor: jamesbowman\nState: closed\nBase branch: master\nHead branch: master\nCreated: 2020-07-17T20:58:39Z\nUpdated: 2020-07-18T01:06:15Z\nClosed: 2020-07-18T01:06:15Z\nMerged: 2020-07-18T01:06:15Z\n\nHi Sameer, I'm working on a verification testbench for your HDMI code base.\r\nThis first commit makes some small syntax changes to get to clean build with Verilator and Icarus Verilog.\r\n\r\nThe next steps are:\r\n * a testbench that dumps the 3 x 10 bit TMDS values for N clocks\r\n * a stream analyzer that verifies HDMI against the spec and the settings\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/hdl-util_hdmi_pr12", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/hdl-util_hdmi_pr12.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/hdl-util_hdmi_pr12", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/hdl-util_hdmi_pr12"} {"instance_id": "hdl-util_hdmi_pr15", "issue_text": "# add format 34 (1080p30)\n\nInstance: hdl-util_hdmi_pr15\nSource: https://github.com/hdl-util/hdmi/pull/15\nFetched: 2026-04-26\nRepository: hdl-util/hdmi\nPull request: #15\nAuthor: sameer\nState: closed\nBase branch: master\nHead branch: 1080p30\nCreated: 2021-02-06T23:53:38Z\nUpdated: 2021-02-06T23:57:06Z\nClosed: 2021-02-06T23:57:03Z\nMerged: 2021-02-06T23:57:03Z\n\n## PR Title\nadd format 34 (1080p30)\n\n## PR Description\nDerived from contributions by @nockieboy and BrianHG https://www.eevblog.com/forum/fpga/hdmi-dvi-encoder-with-audio-smart-quartus-pll-integration-in-systemverilog/\n\n## PR Comments\n\n**sameer** (Feb 6, 2021):\n\"Derived from contributions by @nockieboy and BrianHG https://www.eevblog.com/forum/fpga/hdmi-dvi-encoder-with-audio-smart-quartus-pll-integration-in-systemverilog/\"\n\n## PR Metadata\n- Status: Merged\n- Merge commit: 2a35976\n- Branch deleted after merge: 1080p30\n- Reviewers: None\n- Assignees: None\n- Labels: None\n\n## Linked Issues\nNo linked issues are referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/hdl-util_hdmi_pr15", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/hdl-util_hdmi_pr15.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/hdl-util_hdmi_pr15", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/hdl-util_hdmi_pr15"} {"instance_id": "hdl-util_hdmi_pr16", "issue_text": "# Switch to GH action\n\nInstance: hdl-util_hdmi_pr16\nSource: https://github.com/hdl-util/hdmi/pull/16\nFetched: 2026-04-26\nRepository: hdl-util/hdmi\nPull request: #16\nAuthor: sameer\nState: closed\nBase branch: master\nHead branch: github-action\nCreated: 2021-02-07T00:33:51Z\nUpdated: 2021-02-07T01:23:04Z\nClosed: 2021-02-07T01:23:01Z\nMerged: 2021-02-07T01:23:01Z\n\n## PR Title\nSwitch to GH action\n\n## PR Description\nNo description provided.\n\n## PR Comments\nNo substantive comments were recorded in the conversation thread beyond the automated merge notification.\n\n## PR Metadata\n- Status: Merged\n- Author force-pushed the github-action branch multiple times before merging\n- Purpose: transition the project's CI/CD infrastructure from Travis CI to GitHub Actions and update ModelSim dependencies\n- Branch deleted after merge: github-action\n\n## Linked Issues\nNo linked issues are referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/hdl-util_hdmi_pr16", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/hdl-util_hdmi_pr16.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/hdl-util_hdmi_pr16", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/hdl-util_hdmi_pr16"} {"instance_id": "hdl-util_hdmi_pr20", "issue_text": "# Xilinx support on master branch\n\nInstance: hdl-util_hdmi_pr20\nSource: https://github.com/hdl-util/hdmi/pull/20\nFetched: 2026-04-26\nRepository: hdl-util/hdmi\nPull request: #20\nAuthor: sameer\nState: closed\nBase branch: master\nHead branch: oserdes2\nCreated: 2021-02-28T04:03:44Z\nUpdated: 2021-02-28T04:04:23Z\nClosed: 2021-02-28T04:04:20Z\nMerged: 2021-02-28T04:04:20Z\n\nAdding support as tested with a series 7 fpga (SEA board)\r\n\r\nreorganizing the video formats and adding 4k30fps\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/hdl-util_hdmi_pr20", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/hdl-util_hdmi_pr20.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/hdl-util_hdmi_pr20", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/hdl-util_hdmi_pr20"} @@ -281,13 +281,13 @@ {"instance_id": "lowRISC_ibex_pr1839", "issue_text": "# [pmp] Instruction straddling two TOR regions cosim mismatch\n\n- Source URL: https://github.com/lowRISC/ibex/pull/1839\n\nWhen running the following test:\n`make -j1 --keep-going IBEX_CONFIG=opentitan ITERATIONS=1 TEST=riscv_epmp_mml_test WAVES=0 COV=0 SEED=30325`\n\nIbex and Spike have different behavior. Spike throws an instruction access fault exception for the address `0x80005cc4`. The TOR region ends at `0x80005cc4`, which is the expected behavior.\n\nI think Ibex somehow does not perform the check for fetched instructions properly. In this test case there is a branch instruction that straddles two PMP entries, so Ibex must do two requests.\n\nIbex commit: 0e396d594435c0acca9df785ac40309c76576cc3\nSpike commit: 0dc2de5d76add7b218b31053792a676973034b9e\n\n> estimate 4\n\n## Fetched Issue/PR Details\n\nTitle: [if,pmp] Check second bit instead of third for instruction alignment (PR #1839)\n\nDescription: The PR addresses a bug where Ibex was checking the wrong bit when looking at PMP errors and when to count the error it received from instruction fetch +2. This PR closes issue #1837 (\"[pmp] Instruction straddling two TOR regions cosim mismatch\").\n\nStatus: Merged\nAuthor: marnovandermaas\nMerge Date: October 6, 2022\nReviewer: ctopal (approved)\nLabel: Type:Bug\n\nComments:\n- marnovandermaas (Oct 5, 2022): Provided the description above and noted this fixes a cosmetic simulation mismatch related to PMP instruction alignment checking.\n- ctopal (Oct 6, 2022): Approved the changes after reviewing file modifications.\n- GregAC (Oct 6, 2022): Added the \"Type:Bug\" label to categorize this as a bug fix.\n\nLinked Issues: Closes #1837 (the cosim mismatch reported above).\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/lowRISC_ibex_pr1839", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/lowRISC_ibex_pr1839.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/lowRISC_ibex_pr1839", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/lowRISC_ibex_pr1839"} {"instance_id": "lowRISC_ibex_pr1865", "issue_text": "Observed Behavior\nThe core_busy_o output signal of the non-lockstep core is used to gate the core clock, which is used by the regular Ibex core and its lockstep counterpart.\n\nibex/rtl/ibex_top.sv\n\nLines 211 to 219 in 3943a4e\n\n assign clock_en = core_busy_q | debug_req_i | irq_pending | irq_nm_i; \n assign core_sleep_o = ~clock_en; \n \n prim_clock_gating core_clock_gate_i ( \n .clk_i (clk_i), \n .en_i (clock_en), \n .test_en_i(test_en_i), \n .clk_o (clk) \n ); \n\nibex/rtl/ibex_top.sv\n\nLines 286 to 287 in 3943a4e\n\n ) u_ibex_core ( \n .clk_i(clk), \n\nibex/rtl/ibex_top.sv\n\nLines 927 to 928 in 3943a4e\n\n ) u_ibex_lockstep ( \n .clk_i (clk), \nThis means that the lockstep core gets gated in the same clock cycle as the regular core, even though the lockstep core is a few cycles delayed. A low-glitch in the core_busy_o output of the non-lockstep core thus does not lead to a comparison mismatch and a major alert because the lockstep core is already clock-gated when it would produce the value of core_busy_o that is used in the comparison.\n\nibex/rtl/ibex_lockstep.sv\n\nLines 453 to 454 in 3943a4e\n\n assign outputs_mismatch = enable_cmp_q & (shadow_outputs_q != core_outputs_q[0]); \n assign alert_major_internal_o = outputs_mismatch | shadow_alert_major_internal; \nExpected Behavior\nA low-glitch/mismatch in the core_busy_o output signal of the non-lockstep core should lead to a major alert by the lockstep core.\n\nSteps to reproduce the issue\nRun the chip_sw_ibex_lockstep_glitch test in OpenTitan (currently in lowRISC/opentitan#15221) and override port_idx to the index of core_busy_o in output_ports.", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/lowRISC_ibex_pr1865", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/lowRISC_ibex_pr1865.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/lowRISC_ibex_pr1865", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/lowRISC_ibex_pr1865"} {"instance_id": "lowRISC_ibex_pr1872", "issue_text": "# insn_trigger_exception coverpoint does not work\n\n- Source URL: https://github.com/lowRISC/ibex/pull/1872\n\nThe test riscv_debug_triggers_test added in #1801 generates stimulus to hit [this coverpoint](https://github.com/lowRISC/ibex/blob/ce536ae47677e952de02b7421e1b78efb5761ab2/dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv#L502), but it does not trigger.\n\nREPRO\n- Checkout https://github.com/lowRISC/ibex/pull/1801\n- Run: make TEST=riscv_debug_triggers_test ITERATIONS=1 SEED=14664 COV=1 -j12 -ik\n- The instruction/event that should trigger this coverpoint can be seen retiring at t = 1010124 ns\n\n## Fetched Issue/PR Details\n\nTitle: Misc fixes (PR #1872)\n\nDescription: PR contains three commits and fixes issue #1863:\n1. [rtl] Fix ebreak debug cause - \"We should only indicate an ebreak debug cause if an ebreak leads to a debug entry (otherwise when single stepping over an ebreak that traps to an exception we incorrectly enter debug mode with an ebreak cause).\"\n2. [dv] Remove cp_insn_trigger_exception coverpoint - \"This coverpoint does not make sense. The hardware breakpoint is triggered as the instruction moves into the ID/EX stage so it never has a chance to take an exception (it effectively never begins executing).\"\n3. [dv] Add single step over exception coverpoint.\n\nStatus: Merged (Oct 26, 2022)\nAuthor: GregAC\nBranch: GregAC:misc_fixes -> lowRISC:master\n\nReview Activity:\n- hcallahan-lowrisc approved the changes on Oct 26, 2022\n- ctopal was requested for review\n- PR merged by GregAC on Oct 26, 2022; branch deleted after merge\n\nLinked Issues: Closes issue #1863 (\"insn_trigger_exception coverpoint does not work\").\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/lowRISC_ibex_pr1872", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/lowRISC_ibex_pr1872.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/lowRISC_ibex_pr1872", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/lowRISC_ibex_pr1872"} -{"instance_id": "lowRISC_ibex_pr1917", "issue_text": "# [dv] Out of bounds access in dside access tracking logic\n\n- Source URL: https://github.com/lowRISC/ibex/pull/1917\n\nThis line: https://github.com/lowRISC/ibex/blob/056cb44ff75f797898709546ea1b0fd08d862e1a/rtl/ibex_top.sv#L1092\n\nUses `i - 1` and it's possible to evaluate this condition when `i == 0` giving an out of bounds access. This logic needs refactoring to more explicitly split out the `i == 0` case from the others to ensure this does not occur.\n\n> estimate 1\n\n## Fetched Issue/PR Details\n\nTitle: [fpv] Fix linting issues in oustanding access tracking logic (PR #1917)\n\nDescription: \"This refactors the code to avoid a -1 index access that caused no issues in functional verification but caused lint errors and is problematic for formal tools. Fixes #1799.\"\n\nAuthor: GregAC\nStatus: Merged (November 14, 2022)\nTarget: lowRISC/ibex master branch\nRelated Issue: #1799 (\"[dv] Out of bounds access in dside access tracking logic\")\n\nComments and Activity:\n- GitHub Actions Bot (November 9, 2022): Verible Verilog Lint flagged \"All generate block statements must have a label [Style: generate-statements]\".\n- GregAC force-pushed corrections on November 9 and November 12, 2022 to address linting feedback.\n- ctopal approved the changes on November 14, 2022.\n- GregAC merged the PR and deleted the tracking_logic_fix branch on November 14, 2022.\n\nLinked Issues: Closes #1799.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/lowRISC_ibex_pr1917", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/lowRISC_ibex_pr1917.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/lowRISC_ibex_pr1917", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/lowRISC_ibex_pr1917"} +{"instance_id": "lowRISC_ibex_pr1917", "issue_text": "# [dv] Out of bounds access in dside access tracking logic\n\n- Source URL: https://github.com/lowRISC/ibex/pull/1917\n\nThis line: https://github.com/lowRISC/ibex/blob/056cb44ff75f797898709546ea1b0fd08d862e1a/rtl/ibex_top.sv#L1092\n\nUses `i - 1` and it's possible to evaluate this condition when `i == 0` giving an out of bounds access. This logic needs refactoring to more explicitly split out the `i == 0` case from the others to ensure this does not occur.\n\n> estimate 1\n\n## Fetched Issue/PR Details\n\nTitle: [fpv] Fix linting issues in oustanding access tracking logic (PR #1917)\n\nDescription: \"This refactors the code to avoid a -1 index access that caused no issues in functional verification but caused lint errors and is problematic for formal tools. Fixes #1799.\"\n\nAuthor: GregAC\nStatus: Merged (November 14, 2022)\nTarget: lowRISC/ibex master branch\nRelated Issue: #1799 (\"[dv] Out of bounds access in dside access tracking logic\")\n\nComments and Activity:\n- GitHub Actions Bot (November 9, 2022): Verible Verilog Lint flagged \"All generate block statements must have a label [Style: generate-statements]\".\n- GregAC force-pushed corrections on November 9 and November 12, 2022 to address linting feedback.\n- ctopal approved the changes on November 14, 2022.\n- GregAC merged the PR and deleted the tracking_logic_fix branch on November 14, 2022.\n\nLinked Issues: Closes #1799.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/lowRISC_ibex_pr1917", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/lowRISC_ibex_pr1917.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/lowRISC_ibex_pr1917", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/lowRISC_ibex_pr1917"} {"instance_id": "lowRISC_ibex_pr2166", "issue_text": "# Security vulnerability: Ibex leaks data when multiplication is aborted\n\n\r\n\r\n## Observed Behavior\r\n\r\n\r\nA MULH instruction that is aborted by an unsolicited memory error response leaks information about its input values to a subsequent MUL instruction. The subsequent MUL instruction stores a value dependent on MULH's operands into its result register, thus produces a wrong result and leaking information.\r\n\r\nI believe that the reason is that the multiplication's module's internal state machine is not reset in case of an abort. \r\n\r\n## Expected Behavior\r\n\r\nIbex should not leak data in case of external interface errors.\r\n\r\n## Steps to reproduce the issue\r\n\r\nThe testbench in https://github.com/KatCe/ibex/tree/bug_mulh_reg_leakage/dv/bug_mulh_reg_leakage demonstrates the problem.\r\nThis testbench uses the default configuration. We have also observed the bug in secure configuration with the parameters commented in the testbench.\r\n\r\n## My Environment\r\n\r\n\r\n\r\n**EDA tool and version:**\r\n\r\nQuesta Sim-64, Version 2022.3_1 linux_x86_64 Aug 12 2022\r\n\r\n**Operating system:**\r\n\r\nUbuntu 20.04.6 LTS\r\n**Version of the Ibex source code:**\r\n\r\n5a8a1a99930afbb9efe107ff2c80d482239d7a5f\r\nThe exact list of files run by the test bench can be found in https://github.com/KatCe/ibex/blob/bug_mulh_reg_leakage/dv/bug_mulh_reg_leakage/flist.f\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/lowRISC_ibex_pr2166", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/lowRISC_ibex_pr2166.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/lowRISC_ibex_pr2166", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/lowRISC_ibex_pr2166"} {"instance_id": "lowRISC_ibex_pr2214", "issue_text": "# Pipeline not being flushed on PMP register clears\n\n- Source URL: https://github.com/lowRISC/ibex/pull/2214\n\nIn [this commit](https://github.com/lowRISC/ibex/commit/46404cf86f60f72fb84a2bc693d2ab08011bdb37) the pipeline was made to flush on changes to PMP registers, changes made via `CSR_OP_CLEAR` however are missed.\n\nThis is likely because prior to this commit only mstatus and mie were listed, and clearing is safe for those.\n\nThis meant that instructions being fetched were passing PMP checks which they should not have been.\n\n## Fetched Issue/PR Details\n\nTitle: [rtl] Flush pipe on all CSR modifications (PR #2214)\n\nDescription: This fix addresses issue #2193, where bit clears in PMP-related CSRs weren't immediately applying to instructions already in the fetch stage due to missing pipeline flushes. The solution flushes the pipeline on all CSR modifications to make the system more resilient against similar oversights in the future.\n\nKey Changes:\n- CSR address reading optimization: Routes CSR addresses directly from the decoder to the ibex_cs_registers module rather than through operand muxes, improving timing.\n- Pipeline flush on CSR modifications: Implements a whitelist where most CSR writes trigger pipeline flushes, but specific CSRs (mscratch, mepc) are excluded since they don't affect instruction execution in the fetch stage.\n\nNotable Discussion:\n- Performance considerations: Reviewers raised concerns about CSR write frequency during exception handling. The author acknowledged that while some CSR operations (like csrrw for stack switching) are performance-sensitive, the actual performance impact is limited since Ibex has only a single fetch stage and CSR instructions typically aren't in tight loops.\n- Whitelist rationale: The team determined that mscratch and mepc don't require flushes - mscratch is purely a temporary storage location, and mepc is only read during exception returns, not during fetch-stage instruction execution.\n\nReview and Merge:\n- Approved by: vogelpi and marnovandermaas\n- Merged: February 17, 2025\n- Status: Merged into master\n\nThe PR underwent multiple iterations and force-pushes to address lint issues and incorporate feedback about the whitelist approach.\n\nLinked Issues: Fixes #2193.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/lowRISC_ibex_pr2214", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/lowRISC_ibex_pr2214.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/lowRISC_ibex_pr2214", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/lowRISC_ibex_pr2214"} {"instance_id": "lowRISC_ibex_pr2241", "issue_text": "# Undriven signal in ibex_register_file_fpga.sv\n\n## Observed Behavior\n\n\nOn the following line, `oh_raddr_a_err` is undriven if `RdataMuxCheck` is zero.\n\nhttps://github.com/lowRISC/ibex/blob/master/rtl/ibex_register_file_fpga.sv#L54\n\nThis was seen in Verilator linting when trying to integrate Ibex into my design. I've searched the VLT files for any relevant waivers but can't see any relating to this level of hierarchy.\n\n```\nERROR: %Warning-UNDRIVEN: src/lowrisc_export_ibex_top_0/rtl/ibex_register_file_fpga.sv:54:9: Signal is not driven: 'oh_raddr_a_err'\n : ... note: In instance 'ibex_wb.u_top..gen_regfile_fpga.register_file_i'\n 54 | logic oh_raddr_a_err, oh_raddr_b_err, oh_we_err;\n | ^~~~~~~~~~~~~~\n ... For warning description see https://verilator.org/warn/UNDRIVEN?v=5.024\n ... Use \"/* verilator lint_off UNDRIVEN */\" and lint_on around source to disable this message.\n%Warning-UNDRIVEN: src/lowrisc_export_ibex_top_0/rtl/ibex_register_file_fpga.sv:54:25: Signal is not driven: 'oh_raddr_b_err'\n : ... note: In instance 'ibex_wb.u_top..gen_regfile_fpga.register_file_i'\n 54 | logic oh_raddr_a_err, oh_raddr_b_err, oh_we_err;\n | ^~~~~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\nmake: *** [Makefile:23: lint-only] Error 1\n\nERROR: Failed to build nq:ip:ibex_wb:0 : '['make', 'lint-only']' exited with an error: 2\n```\n\n## Expected Behavior\n\nTis lint clean please.\n\n## Steps to reproduce the issue\n\n\nI'm trying to export the Ibex RTL source code to get around the fact that you are using a custom version of Fusesoc. I'm instantiating Ibex with the following parameters:\n\n```\n ibex_top #(\n .RV32M (ibex_pkg::RV32MSlow),\n .RV32B (ibex_pkg::RV32BNone),\n .RegFile(ibex_pkg::RegFileFPGA)\n ) u_top (\n\n```\n\nand then running a Verilator lint using the standard Fusesoc/Edalize flow.\n\n## My Environment\n\n\n\n**EDA tool and version:**\nVerilator 5.024 2024-04-05 rev v5.024\n\n\n**Operating system:**\nRocky 9.4\n\n\n**Version of the Ibex source code:**\n8f4c75c5e43e61b994248307c814e01860303056\n\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/lowRISC_ibex_pr2241", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/lowRISC_ibex_pr2241.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/lowRISC_ibex_pr2241", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/lowRISC_ibex_pr2241"} {"instance_id": "lowRISC_ibex_pr2251", "issue_text": "# Ibex core assertion NoExecWhenFetchEnableNotOn not gated correctly.\n\n## Observed Behavior\nI'm seeing the NoExecWhenFetchEnableNotOn assertion fire inside of ibex_core.sv in a case where I'm not using the lockstep mode. I have a single instance of Ibex with the default parameters including `parameter bit SecureIbex = 1'b0,`\n\nThe assertion in question is part of the following code block:\n\n```\n // Keep track of the PC last seen in the ID stage when fetch is disabled\n logic [31:0] pc_at_fetch_disable;\n ibex_mubi_t last_fetch_enable;\n\n always_ff @(posedge clk_i or negedge rst_ni) begin\n if (!rst_ni) begin\n pc_at_fetch_disable <= '0;\n last_fetch_enable <= '0;\n end else begin\n last_fetch_enable <= fetch_enable_i;\n\n if ((fetch_enable_i != IbexMuBiOn) && (last_fetch_enable == IbexMuBiOn)) begin\n pc_at_fetch_disable <= pc_id;\n end\n end\n end\n\n // When fetch is disabled no instructions should be executed. Once fetch is disabled either the\n // ID/EX stage is not valid or the PC of the ID/EX stage must remain as it was at disable. The\n // ID/EX valid should not ressert once it has been cleared.\n `ASSERT(\n NoExecWhenFetchEnableNotOn,\n fetch_enable_i != IbexMuBiOn |=> (~instr_valid_id || (pc_id == pc_at_fetch_disable)) && ~$rose\n (instr_valid_id))\n```\n\nMy understanding from reading the documentation about `fetch_enable_i` was that I just needed to tie the LSB to 1. So I'm driving the input port to `4'b0001`. If that is correct, then it looks like this assertion shouldn't be firing. It should probably only be used when `SecureIbex == 1`?\n\nThe assertion fires for the first valid instruction fetched after reset.\n\n## Expected Behavior\nNo assertion should fire - unless I'm missing the fact that I'm doing something stupid.\n\n## Steps to reproduce the issue\nMy instantiation looks like:\n```\n ibex_top #(\n .RV32M (ibex_pkg::RV32MSlow),\n .RV32B (ibex_pkg::RV32BNone),\n .RegFile(ibex_pkg::RegFileFPGA)\n ) u_top (\n // Clock and reset\n .clk_i (clk),\n .rst_ni (!rst),\n .test_en_i ('0),\n .scan_rst_ni('0),\n .ram_cfg_i ('0),\n\n // Configuration\n .hart_id_i ('0),\n .boot_addr_i('0),\n\n // Instruction memory interface\n .instr_req_o (instr_req),\n .instr_gnt_i (instr_gnt),\n .instr_rvalid_i (instr_rvalid),\n .instr_addr_o (instr_addr),\n .instr_rdata_i (instr_rdata),\n .instr_rdata_intg_i('0),\n .instr_err_i (instr_err),\n\n // Data memory interface\n .data_req_o (data_req),\n .data_gnt_i (data_gnt),\n .data_rvalid_i (data_rvalid),\n .data_we_o (data_we),\n .data_be_o (data_be),\n .data_addr_o (data_addr),\n .data_wdata_o (data_wdata),\n .data_wdata_intg_o(),\n .data_rdata_i (data_rdata),\n .data_rdata_intg_i('0),\n .data_err_i (data_err),\n\n // Interrupt inputs\n .irq_software_i('0),\n .irq_timer_i (timer_irq),\n .irq_external_i('0),\n .irq_fast_i ('0),\n .irq_nm_i ('0),\n\n // Scrambling Interface\n .scramble_key_valid_i('0),\n .scramble_key_i ('0),\n .scramble_nonce_i ('0),\n .scramble_req_o (),\n\n // Debug interface\n .debug_req_i ('0),\n .crash_dump_o (),\n .double_fault_seen_o(),\n\n // Special control signals\n .fetch_enable_i (4'b0001),\n .alert_minor_o (),\n .alert_major_internal_o(),\n .alert_major_bus_o (),\n .core_sleep_o ()\n );\n```\n\n## My Environment\n\n**EDA tool and version:**\nCadence Xcelium 24.03\n\n**Operating system:**\nRHEL 9.5\n\n**Version of the Ibex source code:**\n8f4c75c5e43e61b994248307c814e01860303056\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/lowRISC_ibex_pr2251", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/lowRISC_ibex_pr2251.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/lowRISC_ibex_pr2251", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/lowRISC_ibex_pr2251"} {"instance_id": "lowRISC_ibex_pr2261", "issue_text": "# simulator report error\n\n\n\n## Observed Behavior\nTest ibex in verilator with cosim, simulator report error illegal instruction.\n```\n001003e8
:\n 1003e8:\t1141 \taddi\tsp,sp,-16\n 1003ea:\tc606 \tsw\tra,12(sp)\n 1003ec:\t0000 \tunimp # <--- This is the illegal instruction!\n 1003ee:\t0000 \tunimp\n 1003f0:\t37b9 \tjal\t10033e \n 1003f2:\t00000517 \tauipc\ta0,0x0\n 1003f6:\t05650513 \taddi\ta0,a0,86 # 100448 \n 1003fa:\t3959 \tjal\t100090 \n 1003fc:\t40b2 \tlw\tra,12(sp)\n 1003fe:\t4501 \tli\ta0,0\n 100400:\t0141 \taddi\tsp,sp,16\n 100402:\t8082 \tret\n```\n```\nDASM(0x00010413)\nmv s0, sp\n```\n\n![Image](https://github.com/user-attachments/assets/321158de-0306-44b2-a11b-64c2fcfc4a7f)\n\nMTVAL in `ibex_simple_system.log` file is 0x00000000\n\n\n## Expected Behavior\nThe terminal should print right mtval value.\n\n\n## Steps to reproduce the issue\nRun `build/lowrisc_ibex_ibex_simple_system_cosim_0/sim-verilator/Vibex_simple_system --meminit=ram,ibex/examples/sw/simple_system/input/test.elf`\n```\n#include \"simple_system_common.h\"\nint main(void){\n // puts(\"Starting test\");\n __asm__ volatile(\".word 0x000000\");\n puts(\"Test complete\");\n return 0;\n}\n```\n\n\n## My Environment\nBuild verilator to run ibex by [co-sim](https://ibex-core.readthedocs.io/en/latest/03_reference/cosim.html#quick-build-and-run-instructions).\n\n\n**EDA tool and version:**\nNone\n\n\n**Operating system:**\nUbuntu Linux 18.04\n\n\n**Version of the Ibex source code:**\n8f4c75c5e43e61b994248307c814e01860303056\n\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/lowRISC_ibex_pr2261", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/lowRISC_ibex_pr2261.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/lowRISC_ibex_pr2261", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/lowRISC_ibex_pr2261"} -{"instance_id": "lowRISC_ibex_pr2269", "issue_text": "# [bug][ibex_decoder] Report a bug in Ibex\n\n- Source URL: https://github.com/lowRISC/ibex/pull/2269\n\nHi all!\n\nI am using a static analysis to found a various bugs in open source RTL designs.\n\nIt was founded that in `ibex_decoder.sv` RTL file dead code is exists [here](https://github.com/lowRISC/ibex/blob/master/rtl/ibex_decoder.sv#L439).\n\nThis assignment under `else` statement is never executed due to [this](https://github.com/lowRISC/ibex/blob/master/rtl/ibex_decoder.sv#L406) external `else` branch with `!instr[26]` condition.\n\n## Fetched Issue/PR Details\n\nTitle: [rtl] Minor tweak to decoder to avoid dead code (PR #2269)\n\nDescription: The PR addresses dead code in the instruction decoder. According to the submitter, an else branch was unreachable because the surrounding condition already established that instr[26] was zero, making a redundant check impossible to execute.\n\nStatus: Merged\nMerged by: andreaskurth\nMerge date: April 25, 2025\nReviewers: marnovandermaas, andreaskurth, vogelpi (awaiting)\nChecks passed: 11\n\nComments:\n- rswarbrick (Apr 23, 2025): \"The 'else' part of the if/else check here wasn't possible because the surrounding else branch...is already in the case where instr[26] is zero.\"\n- marnovandermaas (Apr 24, 2025): Suggested adding an assertion to clarify the constraint.\n- rswarbrick (response): Noted that the project lacks procedural assertions in RTL code and the constraint is syntactically visible.\n- andreaskurth (Apr 25, 2025): Approved with \"LGTM, thx @rswarbrick\".\n\nLinked Issues: Fixes issue #2268 (\"[bug][ibex_decoder] Report a bug in Ibex\").\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/lowRISC_ibex_pr2269", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/lowRISC_ibex_pr2269.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/lowRISC_ibex_pr2269", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/lowRISC_ibex_pr2269"} +{"instance_id": "lowRISC_ibex_pr2269", "issue_text": "# [bug][ibex_decoder] Report a bug in Ibex\n\n- Source URL: https://github.com/lowRISC/ibex/pull/2269\n\nHi all!\n\nI am using a static analysis to found a various bugs in open source RTL designs.\n\nIt was founded that in `ibex_decoder.sv` RTL file dead code is exists [here](https://github.com/lowRISC/ibex/blob/master/rtl/ibex_decoder.sv#L439).\n\nThis assignment under `else` statement is never executed due to [this](https://github.com/lowRISC/ibex/blob/master/rtl/ibex_decoder.sv#L406) external `else` branch with `!instr[26]` condition.\n\n## Fetched Issue/PR Details\n\nTitle: [rtl] Minor tweak to decoder to avoid dead code (PR #2269)\n\nDescription: The PR addresses dead code in the instruction decoder. According to the submitter, an else branch was unreachable because the surrounding condition already established that instr[26] was zero, making a redundant check impossible to execute.\n\nStatus: Merged\nMerged by: andreaskurth\nMerge date: April 25, 2025\nReviewers: marnovandermaas, andreaskurth, vogelpi (awaiting)\nChecks passed: 11\n\nComments:\n- rswarbrick (Apr 23, 2025): \"The 'else' part of the if/else check here wasn't possible because the surrounding else branch...is already in the case where instr[26] is zero.\"\n- marnovandermaas (Apr 24, 2025): Suggested adding an assertion to clarify the constraint.\n- rswarbrick (response): Noted that the project lacks procedural assertions in RTL code and the constraint is syntactically visible.\n- andreaskurth (Apr 25, 2025): Approved with \"LGTM, thx @rswarbrick\".\n\nLinked Issues: Fixes issue #2268 (\"[bug][ibex_decoder] Report a bug in Ibex\").\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/lowRISC_ibex_pr2269", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/lowRISC_ibex_pr2269.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/lowRISC_ibex_pr2269", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/lowRISC_ibex_pr2269"} {"instance_id": "lowRISC_opentitan_pr28469", "issue_text": "# [hw,pinmux,rtl] Remove sys reset when no strap sampling\n\nInstance: lowRISC_opentitan_pr28469\nSource: https://github.com/lowRISC/opentitan/pull/28469\nFetched: 2026-04-26\nRepository: lowRISC/opentitan\nPull request: #28469\nAuthor: Razer6\nState: closed\nBase branch: master\nHead branch: pinmux-sys-reset\nCreated: 2025-10-11T22:52:30Z\nUpdated: 2025-10-13T14:44:34Z\nClosed: 2025-10-13T14:44:33Z\nMerged: 2025-10-13T14:44:33Z\n\nThe sys reset in pinmux is only needed for the strap sampling logic. Since that feature is gated behind an ipgen parameter, also gate the reset with this flag and remove it for Darjeeling.\r\n\r\nCloses https://github.com/lowRISC/opentitan/issues/25410\n\n## Local Reproducer Notes\n\n# lowRISC_opentitan_pr28469\n\nMinimal fail-to-pass Verilator case for removing the sys reset dependency from pinmux strap sampling.\n\nThe buggy pinmux clears the sampled strap when `rst_sys_ni` is asserted low even though strap sampling should only depend on the primary reset. The patch ignores the sys reset for the sampled strap state.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/lowRISC_opentitan_pr28469", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/lowRISC_opentitan_pr28469.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/lowRISC_opentitan_pr28469", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/lowRISC_opentitan_pr28469"} {"instance_id": "lowRISC_opentitan_pr28698", "issue_text": "# [otbn,dv] Collecting coverage fails for various tests\n\n### Description\n\nThe current [OTBN Simulation Results page](https://nightly.reports.lowrisc.org/opentitan_weekly_earlgrey/2025_11_02/hw/ip/otbn/dv/uvm/report.html) reports many OTBN tests as failing for the master branch. For example the otbn_smoke or otbn_single test.\n\nWhen I run these tests locally with DV sim but without coverage reporting, they pass (I tested otbn_smoke, otbn_single and otbn_multi_err). I run the tests with:\n```\nutil/dvsim/dvsim.py hw/ip/otbn/dv/uvm/otbn_sim_cfg.hjson -i otbn_smoke\n```\n\nThese tests fail when coverage is enabled (with the `--cov` argument) because illegal values are sampled for the mnemonic coverpoints of the instruction covergroups. An example for such a coverpoint is:\n\nhttps://github.com/lowRISC/opentitan/blob/9baed2bba4eccd325684c27b74049391d865c76f/hw/ip/otbn/dv/uvm/env/otbn_env_cov.sv#L1185-L1200\n\nI pinpointed the error down to the commit e9986ef486. This commit changes the macro `DEF_MNEM_BIN` such that quotes are added around the mnemonic to satisfy Verissimo. As a consequence, the bin is looking for mnemonic values like `\"addi\"` (with the quotes). However, the sample function of the covergroup is always called with the mnemonic without quotes, e.g., the passed value is `addi` (without quotes). The passed value is then handled as an illegal value and thus an error is reported.\n\nWhen I revert the commit, the tests pass again. \n\n@rswarbrick Can you please explain to me why the quotes are required? And if they are, how the setup can be adapted such that mnemonics with quotes are passed/generated?\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/lowRISC_opentitan_pr28698", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/lowRISC_opentitan_pr28698.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/lowRISC_opentitan_pr28698", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/lowRISC_opentitan_pr28698"} {"instance_id": "merledu_azadi-soc_pr10", "issue_text": "# SRAM(openram) support is required.\n\n- Source URL: https://github.com/merledu/azadi-soc/issues/9\n\nFor submitting design in Google MPW-3 shuttle we need to add sram(openram) support for having sufficient memory size, may be around 8kb for iccm and dccm.\n\n## Fetched Issue/PR Details\n\nTitle: SRAM(openram) support is required. (#9)\n\nDescription: \"For submitting design in Google MPW-3 shuttle we need to add sram(openram) support for having sufficient memory size, may be around 8kb for iccm and dccm.\"\n\nAuthor: sajjadahmed677\nOpened: September 27, 2021\nStatus: Closed\nRelated PR: #10 (closed)\n\nComments: No comments visible.\n\nLinked Issues: Resolving PR #10. The issue requests integration of OpenRAM-based SRAM modules to provide adequate memory capacity for ICCM and DCCM in the Azadi SoC design, specifically for submission to the Google MPW-3 shuttle program.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/merledu_azadi-soc_pr10", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/merledu_azadi-soc_pr10.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/merledu_azadi-soc_pr10", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/merledu_azadi-soc_pr10"} @@ -312,7 +312,7 @@ {"instance_id": "muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr23", "issue_text": "# Develop TB components\n\n- Source URL: https://github.com/muneeb-mbytes/pulpino__spi_master__subsystem_verification/issues/5\n\nTitle: Develop TB components #5\n\nBody:\n- env\n- virtual sequencers\n- scoreboard\n\nComments: None\n\nLinked Issues/PRs: #23 (Pull Request - Closed)\n\nMetadata:\n- Assignees: sahanapalesh, sivareddykostam\n- Milestone: 💻 Development\n- Created: March 2, 2022\n\nSummary: This is a development task requesting the creation of three testbench (TB) components for the PULPino SPI master subsystem verification project: an environment setup, virtual sequencers, and a scoreboard - all essential elements in SystemVerilog/UVM-based hardware verification frameworks.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr23", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr23.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr23", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr23"} {"instance_id": "muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr25", "issue_text": "# adapter_development\n\n- Source URL: https://github.com/muneeb-mbytes/pulpino__spi_master__subsystem_verification/issues/24\n\n**Is your feature request related to a problem? Please describe.**\r\nA clear and concise description of what the problem is. Ex. I'm always frustrated when [...]\r\n\r\n**Describe the solution you'd like**\r\nA clear and concise description of what you want to happen.\r\n\r\n**Describe alternatives you've considered**\r\nA clear and concise description of any alternative solutions or features you've considered.\r\n\r\n**Additional context**\r\nAdd any other context or screenshots about the feature request here.\r\n\r\n**Additional lists of tasks to be accomplished**\r\n- [ ] task 1\r\n- [ ] task 2\r\n\r\n**Add the required following items to the issue**\r\n1. Projects\r\n2. Milestone\r\n3. Assignee\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr25", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr25.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr25", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr25"} {"instance_id": "muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28", "issue_text": "# Integrate RTL and VIPs\n\n- Source URL: https://github.com/muneeb-mbytes/pulpino__spi_master__subsystem_verification/issues/4\n\nTitle: Integrate RTL and VIPs #4\n\nBody: Integrate the RTL design and VIPs by developing the top module\n\nComments: None\n\nLinked PR: #28 (Closed)\n\nMetadata:\n- Assignee: sivareddykostam\n- Milestone: 💻 Development\n- Status: Closed\n\n## PR Title\nAdded the final width for the axi data\n\n## PR Description\nFixes: #4 #2 #6\n\nChanges proposed in this pull request:\n- adding the .gitignore file\n- updated the collector\n\nRequirements checklist:\n- Create the pull request to branch development_branch_v1\n- Use @mention to assign this pull request\n- Select Reviewer\n\n## PR Comments\n\n**sivareddykostam** (Mar 14, 2022):\n\"added the .gitignore file to remove the unwanted files\"\n\n## Linked Issue\n#4: Integrate RTL and VIPs\n\n## PR Metadata\n- Author: sivareddykostam\n- Source Branch: collector_branch\n- Target Branch: development_branch_v1\n- Assignee: sivareddykostam\n- Milestone: 💻 Development\n- Status: Merged (Mar 14, 2022)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28"} -{"instance_id": "muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr29", "issue_text": "# Implement Collector Components\n\n- Source URL: https://github.com/muneeb-mbytes/pulpino__spi_master__subsystem_verification/issues/6\n\nTitle: Implement Collector Components #6\n\nBody:\n**The features it should support:**\n- The axi4 master collector should be able to access registers data.\n- Pass the resultant data from axi4 master collector to scoreboard.\n\nComments: None\n\nLinked PR: #29 (Implement Collector Components)\n\n## PR Title\nupdating the collector\n\n## PR Description\nFixes #6\n\nChanges proposed in this pull request:\n- Adding the collector\n- ....\n\nMake sure you do the following:\n- Create the pull request to branch development_branch_v1\n- Use @mention to assign this pull request\n- Select Reviewer\n\n## PR Comments\nNo substantive comments beyond the PR description template. The contributor self-assigned the PR and added it to the Development milestone on March 14, 2022.\n\n## Linked Issue\n#6: Implement Collector Components\n\n## PR Metadata\n- Author: sivareddykostam\n- Source Branch: collector_branch\n- Target Branch: development_branch_v1\n- Assignee: sivareddykostam\n- Milestone: 💻 Development\n- Status: Merged (March 14, 2022)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr29", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr29.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr29", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr29"} +{"instance_id": "muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr29", "issue_text": "# Implement Collector Components\n\n- Source URL: https://github.com/muneeb-mbytes/pulpino__spi_master__subsystem_verification/issues/6\n\nTitle: Implement Collector Components #6\n\nBody:\n**The features it should support:**\n- The axi4 master collector should be able to access registers data.\n- Pass the resultant data from axi4 master collector to scoreboard.\n\nComments: None\n\nLinked PR: #29 (Implement Collector Components)\n\n## PR Title\nupdating the collector\n\n## PR Description\nFixes #6\n\nChanges proposed in this pull request:\n- Adding the collector\n- ....\n\nMake sure you do the following:\n- Create the pull request to branch development_branch_v1\n- Use @mention to assign this pull request\n- Select Reviewer\n\n## PR Comments\nNo substantive comments beyond the PR description template. The contributor self-assigned the PR and added it to the Development milestone on March 14, 2022.\n\n## Linked Issue\n#6: Implement Collector Components\n\n## PR Metadata\n- Author: sivareddykostam\n- Source Branch: collector_branch\n- Target Branch: development_branch_v1\n- Assignee: sivareddykostam\n- Milestone: 💻 Development\n- Status: Merged (March 14, 2022)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr29", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr29.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr29", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr29"} {"instance_id": "muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr31", "issue_text": "# Develop regression list\n\n- Source URL: https://github.com/muneeb-mbytes/pulpino__spi_master__subsystem_verification/issues/10\n\nTitle: Develop regression list\n\nBody: No description provided.\n\nComments: None\n\nLinked Issues/PRs: Pull Request #31 (closed)\n\nMetadata:\n- Assignee: anithasamanthula\n- Milestone: 🔥 Regression Testing\n- Created: March 3, 2022\n\n## PR Title\nadded regression list\n\n## PR Description\nFixes #10\n\nChanges proposed in this pull request:\n- added all the register testcases\n- and added the regression_handling.py\n- ....\n\nMake sure you do the following:\n- Create the pull request to branch development_branch_v1\n- Use @mention to assign this pull request\n- Select Reviewer\n\n## PR Comments\n\n**anithasamanthula** (Mar 14, 2022, edited):\nProvided the PR description details mentioned above.\n\n## Linked Issue\n#10: Develop regression list\n\n## PR Metadata\n- Author: anithasamanthula\n- Source Branch: regression_branch\n- Target Branch: development_branch_v1\n- Assignee: anithasamanthula\n- Milestone: 💻 Development\n- Status: Merged (Mar 14, 2022)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr31", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr31.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr31", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr31"} {"instance_id": "nand2mario_nestang_pr75", "issue_text": "# NES controller connection issue\n\n- Source URL: https://github.com/nand2mario/nestang/pull/75\n\nTitle: Fix NES controllers\n\nBody: Fixes #74\n\nComments:\n- nikitalita (May 23, 2024): \"Fixes #74\"\n- nand2mario (May 23, 2024): Merged commit 705d9c1 into master\n\nLinked Issue: NES controller connection issue (#74)\nLinked Issue Body: I see you recently added support for them; which pins do they connect to? I'm going to make my own connector with a breadboard and a voltage logic level converter.\n\nStatus: Merged on May 23, 2024\n\n## PR Title\nFix NES controllers\n\n## PR Description\nFixes #74\n\n## PR Comments\nNo substantive comments are documented in the conversation thread beyond the PR description referencing the issue.\n\n## Linked Issue\n#74: NES controller connection issue\nBody: I see you recently added support for them; which pins do they connect to? I'm going to make my own connector with a breadboard and a voltage logic level converter.\n\n## PR Metadata\n- Author: nikitalita\n- Repository: nand2mario/nestang\n- Merge commit: 705d9c14f0be84c54476b1f54e463fa971530bfb\n- Status: Merged on May 23, 2024 by nand2mario into master\n- Participants: nikitalita, nand2mario\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/nand2mario_nestang_pr75", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/nand2mario_nestang_pr75.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/nand2mario_nestang_pr75", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/nand2mario_nestang_pr75"} {"instance_id": "olofk_serv_pr105", "issue_text": "# alu with support for W=4\n\nInstance: olofk_serv_pr105\nSource: https://github.com/olofk/serv/pull/105\nFetched: 2026-04-26\nRepository: olofk/serv\nPull request: #105\nAuthor: uhit332\nState: closed\nBase branch: main\nHead branch: incremental\nCreated: 2023-10-31T11:31:13Z\nUpdated: 2023-10-31T11:42:58Z\nClosed: 2023-10-31T11:42:52Z\nMerged: 2023-10-31T11:42:52Z\n\n## PR Title\nalu with support for W=4\n\n## PR Description\nNo description provided.\n\n## PR Comments\n\n**uhit332** (Contributor, Oct 31, 2023):\nNo description provided.\n\n**olofk** (Owner, Oct 31, 2023):\n\"Excellent! Approved\"\n\n## Linked Issues\nNo linked issues.\n\n## PR Metadata\n- Source branch: uhit332/serv:incremental\n- Target branch: olofk/serv:main\n- No reviews, assignees, labels, or milestone\n- Merged by olofk on Oct 31, 2023 (commit 2e23b53)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/olofk_serv_pr105", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/olofk_serv_pr105.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/olofk_serv_pr105", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/olofk_serv_pr105"} @@ -328,10 +328,10 @@ {"instance_id": "openhwgroup_cv-hpdcache_pr38", "issue_text": "# [Question] How are the error responses treated\n\nHello,\n\nI would like to understand, how error responses are treated. This is what I am observing.\n\n1. In the case where memory responds to a READ with an error, all the subsequent load which are hit at the same addresse have an error response.\n2. In the case where memory responds to a READ with an error, the store which follows at the same adresse has a response withtout and error.\n\nIs it correct ?\n\nThanks and Regards\nTanuj Khandelwal\n\n## PR Title\nfix: handling of errors for write miss requests\n\n## PR Description\nIn the RTAB, only tag a request as error if it is a write miss and its corresponding refill response is an error.\n\n- Add a new dependency bit in the RTAB to indicate the pending request is a write miss\n- Refactor the RTAB code to use a packed structure to represent the dependency bits\n\nCloses #31\n\n## PR Comments\nNo substantive comments in the conversation thread beyond the initial PR description.\n\n## Linked Issue\n#31: [Question] How are the error responses treated\n\n## PR Metadata\n- Author: cfuguet\n- Status: Merged (October 29, 2024) into master\n- Commit: 8c38d83\n- Self-assigned: cfuguet\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_cv-hpdcache_pr38", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_cv-hpdcache_pr38.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openhwgroup_cv-hpdcache_pr38", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_cv-hpdcache_pr38"} {"instance_id": "openhwgroup_cv-hpdcache_pr48", "issue_text": "# Incorrect flagging of write request event\n\nHi, I have noticed that the write request event (`evt_write_req_o`) is not flagged when there is a write request with a write-back policy and the memory produces a response with the error bit set.\r\n\r\n## How to reproduce the issue\r\n\r\nUsing the verilator testbench, run the following command:\r\n\r\n```\r\nmake run SEQUENCE=random LOG_LEVEL=3 NTRANSACTIONS=69 SEED=42\r\n```\r\n\r\nThe faulting transaction will be the last one.\r\n\r\n## Issue description\r\n\r\nThe core makes a store request, using a write-back policy. This request causes a miss, causing the cache to issue a load request to memory due to the write-allocate policy. The write miss event (`evt_cache_write_miss_o`) is flagged, but the write request event (`evt_write_req_o`) is not. The request is put in the RTAB while the cache waits for the memory response.\r\n\r\nOnce the response arrives, it has the error bit set. The original request is then replayed from the RTAB. Because it has been flagged with the error bit, it only sends a response to the core with this flag set. However, it does not flag any event and does not proceed any further. \r\n\r\nUnder normal circumstances, when the error bit is not set, the directory would be updated and the replayed request would hit the cache. It is under this logic when the write request event is flagged (see [hpdcache_ctrl_pe.sv:881](https://github.com/openhwgroup/cv-hpdcache/blob/master/rtl/src/hpdcache_ctrl_pe.sv#L881)).\r\n\r\n## Possible solutions\r\n\r\n- When replaying a request with the error bit set, check if it's a store with the write-back policy, and flag the event then (inside hpdcache_ctrl_pe.sv:404).\r\n- When there is a write-back store making a hit in the cache, check if it's a core request or a replay from the RTAB. Emit the write request event both when there is a miss and when the core (and not a replay due to a miss) makes a hit.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_cv-hpdcache_pr48", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_cv-hpdcache_pr48.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openhwgroup_cv-hpdcache_pr48", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_cv-hpdcache_pr48"} {"instance_id": "openhwgroup_cv32e40p_pr665", "issue_text": "# Add more checks for illegal conditions in the PULP decoder\n\nfollowing what the issue #650 and #629 report - this has to start after pull request #659 is merged\n\n## PR Title\nadding more checks for illegal conditions in pulp isa\n\n## PR Description\nThe pull request was initiated to address issues #663 and #629. The commit message: \"Signed-off-by: Schiavone Davide \"\n\n## PR Comments\n\n**davideschiavone** (August 24, 2021):\nIndicated this submission \"should fix #663 and #629\"\n\n**pascalgouedo** (January 4, 2022):\nProvided multiple review suggestions recommending code clarity improvements. The reviewer suggested replacing comparisons like `!= '0` with explicit bit-width notation (e.g., `!= 5'b0`, `!= 12'b0`, `!= 4'b0`) across multiple conditional statements in the decoder file.\n\n**pascalgouedo** (January 5, 2022):\nApproved the changes after corrections were applied.\n\n## Linked Issues\n#663: Add more checks for illegal conditions in the PULP decoder\n#629: (related illegal condition issue)\n\n## PR Metadata\n- Author: davideschiavone\n- Status: Merged (January 5, 2022)\n- Labels: Component:RTL, PARAM:PULP_XPULP\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_cv32e40p_pr665", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_cv32e40p_pr665.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openhwgroup_cv32e40p_pr665", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_cv32e40p_pr665"} -{"instance_id": "openhwgroup_cv32e40s_pr254", "issue_text": "# RVFI \"pmpaddr\" wrong width\n\n**Component:RTL**: For issues in the RTL (e.g. for files in the rtl directory)\r\n**Component:Other**: For any other issues\r\n\r\n\r\n### Description\r\n\r\nWhen using PMP `G` different from 0.\r\nXcelium cannot compile.\r\n(G=3 in the example below.)\r\n```\r\nxmelab: *E,TYCMPAT (/work/ropeders/src/core-v-verif-pmp/core-v-cores/cv32e40s/bhv/cv32e40s_wrapper.sv,606|72):\r\nport or terminal connection type check failed on instance 'uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i'\r\n(expecting datatype compatible with 'unpacked array [0:63] of packed array [31:0] of logic'\r\nbut found 'unpacked array [0:63] of packed array [29:0] of logic' instead).\r\n```\r\n\r\nThe wrapper connects rvfi probing like `.csr_pmpaddr_q_i ( core_i.cs_registers_i.pmp_addr_rdata`.\r\nBut RVFI expects 32 bits `input logic [31:0] csr_pmpaddr_q_i[PMP_MAX_REGIONS]`.\r\nWhile RTL saved a few bits `logic [PMP_ADDR_WIDTH-1:0] pmp_addr_rdata[PMP_MAX_REGIONS];`.\r\n\r\n(This also causes CEXes in formal, because the rvfi pmpaddr csr values are wrong.)\r\n\r\n\r\n### Steps to Reproduce\r\n\r\n1. Use my fork and branch: https://github.com/silabs-robin/core-v-verif/tree/pmp_assert, hash `f7e1416c`.\r\n2. Go to `cv32e40s/sim/uvmt` and run `make comp CFG=pmp`.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_cv32e40s_pr254", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_cv32e40s_pr254.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openhwgroup_cv32e40s_pr254", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_cv32e40s_pr254"} +{"instance_id": "openhwgroup_cv32e40s_pr254", "issue_text": "# RVFI \"pmpaddr\" wrong width\n\n**Component:RTL**: For issues in the RTL (e.g. for files in the rtl directory)\r\n**Component:Other**: For any other issues\r\n\r\n\r\n### Description\r\n\r\nWhen using PMP `G` different from 0.\r\nXcelium cannot compile.\r\n(G=3 in the example below.)\r\n```\r\nxmelab: *E,TYCMPAT (/work/ropeders/src/core-v-verif-pmp/core-v-cores/cv32e40s/bhv/cv32e40s_wrapper.sv,606|72):\r\nport or terminal connection type check failed on instance 'uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i'\r\n(expecting datatype compatible with 'unpacked array [0:63] of packed array [31:0] of logic'\r\nbut found 'unpacked array [0:63] of packed array [29:0] of logic' instead).\r\n```\r\n\r\nThe wrapper connects rvfi probing like `.csr_pmpaddr_q_i ( core_i.cs_registers_i.pmp_addr_rdata`.\r\nBut RVFI expects 32 bits `input logic [31:0] csr_pmpaddr_q_i[PMP_MAX_REGIONS]`.\r\nWhile RTL saved a few bits `logic [PMP_ADDR_WIDTH-1:0] pmp_addr_rdata[PMP_MAX_REGIONS];`.\r\n\r\n(This also causes CEXes in formal, because the rvfi pmpaddr csr values are wrong.)\r\n\r\n\r\n### Steps to Reproduce\r\n\r\n1. Use my fork and branch: https://github.com/silabs-robin/core-v-verif/tree/pmp_assert, hash `f7e1416c`.\r\n2. Go to `cv32e40s/sim/uvmt` and run `make comp CFG=pmp`.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_cv32e40s_pr254", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_cv32e40s_pr254.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openhwgroup_cv32e40s_pr254", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/openhwgroup_cv32e40s_pr254"} {"instance_id": "openhwgroup_cv32e40s_pr259", "issue_text": "# Wrong execute permission with mseccfg.MML and no matching region\n\n### Component\n\n**Component:RTL**: For issues in the RTL (e.g. for files in the rtl directory)\n\n### Steps to Reproduce\nWhen the first instruction after reset sets mseccfg.MML, the fetch of the next instruction actually goes through. However, the Smepmp spec states that for MML set, \"Executing code from a region without a matching rule or with a matching S/U-mode-only rule is denied.\" With no PMPs set up, the whole memory should thus be denied execute access after setting MML. This is also nicely illustrated in the picture in section 2.2: setting MML is enough to deny execute rights to M mode without a matching region.\nThe issue was found with assertion RV_chk.ops.XCPT_IF_ID_a of the OneSpin Processor Verification App.\n\n## PR Title\nPMP fix (issue 249)\n\n## PR Description\nShould fix #249\n\nSigned-off-by: Arjan Bink \n\n## PR Comments\n\n**Silabs-ArjanB** (July 18, 2022):\n\"Should fix #249. Signed-off-by: Arjan Bink Arjan.Bink@silabs.com\"\n\n## Linked Issue\n#249: Wrong execute permission with mseccfg.MML and no matching region\n\n## PR Metadata\n- Author: Silabs-ArjanB\n- Reviewer: silabs-oivind (review requested)\n- Labels: Component:RTL\n- Status: Merged (July 18, 2022)\n- Commit hash: 38ed6a0\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_cv32e40s_pr259", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_cv32e40s_pr259.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openhwgroup_cv32e40s_pr259", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_cv32e40s_pr259"} {"instance_id": "openhwgroup_cv32e40s_pr263", "issue_text": "# rvfi_mode lacks reset\n\n## rvfi_mode lacks reset\nrvfi_mode is only assigned on `wb_valid_adjusted && !is_dummy_instr_in_wb`, thus has undefined value out of reset\n\n### Steps to Reproduce\nGit hash: 70793cc8e187fcc2c49a752402af82efd1df958d\nbhv/cv32e40s_rvfi.sv, Line 1028, only assignment occurs here.\n\n## PR Title\nAdded reset value for rvfi_mode\n\n## PR Description\nSigned-off-by: Arjan Bink \n\n## PR Comments\nNo substantive comments.\n\n## Linked Issue\n#262: rvfi_mode lacks reset (Closed)\n\n## PR Metadata\n- Author: Silabs-ArjanB\n- Branch: ArjanB_mrv (deleted on merge)\n- Status: Merged into openhwgroup:master (July 18, 2022)\n- Commit: c3cb5b9\n- Participants: Silabs-ArjanB (author/merger), silabs-hfegran (linked the issue)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_cv32e40s_pr263", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_cv32e40s_pr263.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openhwgroup_cv32e40s_pr263", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_cv32e40s_pr263"} -{"instance_id": "openhwgroup_cv32e40x_pr894", "issue_text": "# Zero PMA regions,attribution mismatch between cv32e40x_mpu_sva and cv32e40x_pma\n\n- Source URL: https://github.com/openhwgroup/cv32e40x/issues/893\n\n## Zero PMA regions,attribution mismatch between cv32e40x_mpu_sva and cv32e40x_pma\r\n\r\nGiven 0 PMA regions, PMA code still takes `trans_debug_region_i` into account, while mpu assertions do not. \r\nOccurred during simulation, and confirmed by code inspection - causes mismatches with atomic bit as that bit is enabled in the default configuration, and disallowed within the debug region:\r\n\r\n`cv32e40x_pma.sv`:\r\n```diff\r\n if(PMA_NUM_REGIONS == 0) begin: no_pma\r\n\r\n always_comb begin\r\n // PMA is deconfigured, use NO_PMA_R_DEFAULT as default.\r\n pma_cfg = NO_PMA_R_DEFAULT;\r\n\r\n // Debug mode transactions within the Debug Module region use PMA_DBG as attributes for the DM range\r\n if (trans_debug_region_i) begin\r\n pma_cfg = PMA_DBG;\r\n end\r\n end\r\n\r\n end\r\n```\r\n\r\n`cv32e40x_mpu_sva.sv`:\r\n```diff\r\n always_comb begin\r\n pma_expected_cfg = NO_PMA_R_DEFAULT;\r\n if (PMA_NUM_REGIONS) begin\r\n pma_expected_cfg = is_pma_dbg_matched ? '{main : 1'b1, default : '0} :\r\n is_pma_matched ? PMA_CFG[pma_lowest_match] : PMA_R_DEFAULT;\r\n\r\n end\r\n end\r\n```\r\n\r\n### Steps to Reproduce\r\nPlease provide:\r\n1. core git hash: 8f4eb4cc65c6142cbb24a02cfba975f072ae6376\r\n2. Command line: \r\n`make comp_corev-dv gen_corev-dv test TEST=corev_rand_interrupt_debug CFG=clic_default USE_ISS=YES COV=YES RUN_INDEX=483 GEN_START_INDEX=483 RNDSEED=-585695672 WAVES=1`\r\nNote that the above state of core-v-verif is missing the appropriate debug region settings; the following two lines of code must be added inside the last else clause in the file after the line containing `const string pma_cfg_name = \"pma_noregion\"`:\r\n\r\n```\r\n parameter logic [31:0] CORE_PARAM_DM_REGION_START = 32'h1A11_0000;\r\n parameter logic [31:0] CORE_PARAM_DM_REGION_END = 32'h1A11_1000;\r\n\r\n```\r\nThese will be added by an upcoming PR to core-v-verif\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_cv32e40x_pr894", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_cv32e40x_pr894.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openhwgroup_cv32e40x_pr894", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_cv32e40x_pr894"} +{"instance_id": "openhwgroup_cv32e40x_pr894", "issue_text": "# Zero PMA regions,attribution mismatch between cv32e40x_mpu_sva and cv32e40x_pma\n\n- Source URL: https://github.com/openhwgroup/cv32e40x/issues/893\n\n## Zero PMA regions,attribution mismatch between cv32e40x_mpu_sva and cv32e40x_pma\r\n\r\nGiven 0 PMA regions, PMA code still takes `trans_debug_region_i` into account, while mpu assertions do not. \r\nOccurred during simulation, and confirmed by code inspection - causes mismatches with atomic bit as that bit is enabled in the default configuration, and disallowed within the debug region:\r\n\r\n`cv32e40x_pma.sv`:\r\n```diff\r\n if(PMA_NUM_REGIONS == 0) begin: no_pma\r\n\r\n always_comb begin\r\n // PMA is deconfigured, use NO_PMA_R_DEFAULT as default.\r\n pma_cfg = NO_PMA_R_DEFAULT;\r\n\r\n // Debug mode transactions within the Debug Module region use PMA_DBG as attributes for the DM range\r\n if (trans_debug_region_i) begin\r\n pma_cfg = PMA_DBG;\r\n end\r\n end\r\n\r\n end\r\n```\r\n\r\n`cv32e40x_mpu_sva.sv`:\r\n```diff\r\n always_comb begin\r\n pma_expected_cfg = NO_PMA_R_DEFAULT;\r\n if (PMA_NUM_REGIONS) begin\r\n pma_expected_cfg = is_pma_dbg_matched ? '{main : 1'b1, default : '0} :\r\n is_pma_matched ? PMA_CFG[pma_lowest_match] : PMA_R_DEFAULT;\r\n\r\n end\r\n end\r\n```\r\n\r\n### Steps to Reproduce\r\nPlease provide:\r\n1. core git hash: 8f4eb4cc65c6142cbb24a02cfba975f072ae6376\r\n2. Command line: \r\n`make comp_corev-dv gen_corev-dv test TEST=corev_rand_interrupt_debug CFG=clic_default USE_ISS=YES COV=YES RUN_INDEX=483 GEN_START_INDEX=483 RNDSEED=-585695672 WAVES=1`\r\nNote that the above state of core-v-verif is missing the appropriate debug region settings; the following two lines of code must be added inside the last else clause in the file after the line containing `const string pma_cfg_name = \"pma_noregion\"`:\r\n\r\n```\r\n parameter logic [31:0] CORE_PARAM_DM_REGION_START = 32'h1A11_0000;\r\n parameter logic [31:0] CORE_PARAM_DM_REGION_END = 32'h1A11_1000;\r\n\r\n```\r\nThese will be added by an upcoming PR to core-v-verif\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_cv32e40x_pr894", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_cv32e40x_pr894.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openhwgroup_cv32e40x_pr894", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/openhwgroup_cv32e40x_pr894"} {"instance_id": "openhwgroup_cv32e41p_pr15", "issue_text": "# 40P conditional compilation flags in the 41P\n\n- Source URL: https://github.com/openhwgroup/cv32e41p/issues/10\n\nJust saw that there are 40P-related compilation flags in the 41P code.\nExample: https://github.com/openhwgroup/cv32e41p/blob/master/bhv/cv32e41p_wrapper.sv#L14\n\nIs there a specific reason for that?\n\n## PR Title\n1) Update the assertions and tracer ifdefs\n\n## PR Description\nNo detailed description was provided beyond the title. The PR notes \"Closes #10\".\n\n## PR Comments\n\n**abukharmeh** (Feb 7, 2022):\nOpened the PR, noting it \"Closes #10\".\n\n**MikeOpenHWGroup** (Feb 8, 2022):\nTitle updated; requested review from davideschiavone.\n\n**davideschiavone** (Feb 9, 2022):\nApproved changes and merged the PR.\n\n## Linked Issue\n#10: 40P conditional compilation flags in the 41P\n\n## PR Metadata\n- Author: abukharmeh\n- Reviewer/Merger: davideschiavone\n- Status: Merged (Feb 9, 2022) into master, commit 4b6befd\n- Note: Repository archived November 24, 2023 (read-only)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_cv32e41p_pr15", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_cv32e41p_pr15.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openhwgroup_cv32e41p_pr15", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_cv32e41p_pr15"} {"instance_id": "openhwgroup_cva5_pr29", "issue_text": "# Interrupts can lead to MEPC inconsistent with register state / actually retired operations or pointing to entirely illegal instructions\n\n- Source URL: https://github.com/openhwgroup/cva5/issues/19\n\nWhen an interrupt, such as a timer interrupt occurs, the captured MEPC does not always reflect the correct address where to continue execution after the interrupt finishes. This can randomly lead to significant corruption and crashes.\r\n\r\nI have observed the following 3 inconsistencies::\r\n * CSR modifications that were already started will always finish, yet MEPC can point to the CSR operation (so as not-executed,to resume here after interrupt) \r\n * MEPC can sometimes capture a normal (register-write) instruction that still retires (when the retiring of said instruction falls into the same cycle as the capturing. Same as with CSR-modifications, if the respective operation uses the modified output as input (`addi a0, a0, 1`), erroneous re-execution leads to broken state / MEPC is inconsistent with the register state.\r\n * addresses of prefetched instructions, yet not ever executed / possibly illegal instructions can be captured\r\n\r\nExample for the 3rd case:\r\n```\r\njr [label]\r\n[illegal instruction]\r\n``` \r\nThe illegal instruction will be fetched and maybe decoded prior to CVA5 executing the jump and flushing. Gc_unit does not prevent the address from being captured into MEPC when an interrupt hits at the right time.\r\n\r\nI have fixes for all 3 cases applied in my fork of CVA5, but my fork includes other changes, such as an FPU, reworked verilator implementation and for example modifying the timer interrupt input to match the RV-Privileged spec (#20).\r\nI have also written a test program that recreates all 3 cases for my fork and specific CVA5 configuration, using a timer implemented according to the RV-Priviliged spec. The benchmark arms the timer and expects it to request an interrupt at a specific cycle (and therefor instruction in the benchmark) that is still influenced by the branch predicator (I am using my production CVA5 config to run it).\r\n\r\nI am also happy to share said benchmark and timer, but I have only tested them in my environment, which uses my own Picolibc build, runtime/board support library, CMake configuration, new binary input format and conversion tool for the verilator-simulator. So said test-code would probably need to be refactored into a test with specific, more consistent processor config and to only use the vanilla code base.\r\n\r\nTo outline the scope of fixes I have applied:\r\n * decouple MEPC capture from interrupt_taken signal\r\n * delay MEPC capture depending on if a instruction is currently being retired, ongoing CSR modification\r\n * changed oldest_pc from metadata_id block to next_retiring_insn_pc which applies branch_flush events and updates itself to not include illegal or unreachable addresses.\r\n\r\nThis was the simplest solution to fix the corruption and is probably not the most efficient solution to implementing interrupts. Looking at the timings it seems to be, every instruction that was already issued pre-interrupt could just retire normally instead of being rolled back (unlike when handling jumps/branches). Since we have to wait for all issued ops to retire anyways, it is wasteful to throw that state away (and can also take more cycles). Then some of my modifications would no longer be needed. But I found it too difficult to understand all the ways in which gc_unit needs to stay synchronized to other parts of the core to attempt that modification myself / expected this refactoring to be more work.\r\n\r\nI am afraid I do currently not have the time to rebase my changes and test them without my code base so that I could provide a simple, conflict-free and tested patch-set.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_cva5_pr29", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_cva5_pr29.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openhwgroup_cva5_pr29", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_cva5_pr29"} {"instance_id": "openhwgroup_cva5_pr7", "issue_text": "# Cached memory interface: AXI wstrb not stable if AW handshake completes first\n\n- Source URL: https://github.com/openhwgroup/cva5/issues/6\n\nCVA5's dcache memory interface (via l1_arbiter, l2_arbiter, axi_to_arb) starts each single beat AXI AW handshake simultaneously to the only W handshake. The byte enable value `be` (used for `wstrb`) is stored alongside the address in the `l2_request_t` structure, and the FIFO entry is popped as soon as the AW handshake is complete. However, `wstrb` is in the W handshake alongside `wdata`.\n\nScenario: Downstream bus component sets `wready` only after having accepted an AW handshake. CVA5 will pop from the request FIFO, and `wstrb` will change to whatever is in the next valid or invalid FIFO element, even though the W handshake is still active.\n\nEffect: Depends on the bus components. In our case (using only Xilinx IP downstream), the presence or absence of an AXI crossbar appears to determine whether `wstrb` is sampled in the first W handshake cycle, where the AW handshake is still valid and the fault would be hidden, or in a later cycle. In that case, bytes may unintenionally be masked on or off, so data in memory could become inconsistent.\n\n(Suggested) solution: Move `be`/`wstrb` to the same FIFO as the write data. I'm preparing a pull request but still doing some validation of the patches for upstream.\n\n## PR Title\nL2: Move be (i.e. wstrb for AXI) into the data FIFO (Fixes #6)\n\n## PR Description\nThe contributor moved the `be` signal to the same FIFO as write data and adapted the L2 interface accordingly. Testing included custom design simulation and taiga-project's compliance tests. The `litex/l1_to_wishbone.sv` example and AXI test bench remained untested due to unrelated compile errors.\n\n## PR Comments\n\n**e-matthews** (September 13, 2022):\n\"Thank you very much for both reporting and providing a fix for this issue. I've given a first look over the changes and they look good. I'll run some additional tests and we'll look at getting these changes in soon.\"\n\n**e-matthews** (April 17, 2023):\nApproved the changes.\n\n**MikeOpenHWGroup** (April 18, 2023):\n\"Merging based on @e-matthews approval.\"\n\n## Linked Issue\n#6: Cached memory interface: AXI wstrb not stable if AW handshake completes first\n\n## PR Metadata\n- Submitted by: flmeisel\n- Merged by: MikeOpenHWGroup\n- Status: Merged (April 18, 2023)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_cva5_pr7", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_cva5_pr7.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/openhwgroup_cva5_pr7", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_cva5_pr7"} @@ -361,8 +361,8 @@ {"instance_id": "pulp-platform_apb_pr4", "issue_text": "# Bugfix in APB Assignment Macro\n\nInstance: pulp-platform_apb_pr4\nSource: https://github.com/pulp-platform/apb/pull/4\nFetched: 2026-04-26\nRepository: pulp-platform/apb\nPull request: #4\nAuthor: meggiman\nState: closed\nBase branch: master\nHead branch: bugfix_assign_macro\nCreated: 2021-06-02T08:12:35Z\nUpdated: 2026-02-14T23:10:26Z\nClosed: 2021-06-02T10:21:16Z\nMerged: 2021-06-02T10:21:16Z\n\n## PR Title\nBugfix in APB Assignment Macro\n\n## PR Description\nThis PR fixes a small typo in the APB_TO_RESP assignment macro.\n\n## PR Comments\n\n**meggiman** (Jun 2, 2021):\n\"This PR fixes a small typo in the APB_TO_RESP assignment macro.\"\n\n**andreaskurth** (Jun 2, 2021):\n\"Thanks for this fix, @meggiman!\"\n\n## Linked Issues\nNo linked issues are referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_apb_pr4", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_apb_pr4.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_apb_pr4", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_apb_pr4"} {"instance_id": "pulp-platform_apb_pr7", "issue_text": "# Apb demux\n\nInstance: pulp-platform_apb_pr7\nSource: https://github.com/pulp-platform/apb/pull/7\nFetched: 2026-04-26\nRepository: pulp-platform/apb\nPull request: #7\nAuthor: meggiman\nState: closed\nBase branch: master\nHead branch: apb_demux\nCreated: 2022-04-26T16:32:02Z\nUpdated: 2026-02-14T23:10:25Z\nClosed: 2022-12-20T12:03:27Z\nMerged: 2022-12-20T12:03:27Z\n\n## PR Title\nApb demux\n\n## PR Description\nThis commit adds an APB demultiplex module.\n\n## PR Comments\n\n**meggiman** (Apr 26, 2022):\n\"This commit adds an APB demultiplex module\"\n\n**meggiman** (Dec 5, 2022):\nMarked the pull request as ready for review and assigned it to paulsc96.\n\n**paulsc96** (Dec 20, 2022):\nApproved the changes after reviewing the files in commit ca1d84b.\n\n**paulsc96** (Dec 20, 2022):\nMerged commit 3b9e0e6 into master.\n\n## Linked Issues\nNo linked issues are referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_apb_pr7", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_apb_pr7.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_apb_pr7", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_apb_pr7"} {"instance_id": "pulp-platform_apb_pr8", "issue_text": "# Adds an APB Error Slave\n\nInstance: pulp-platform_apb_pr8\nSource: https://github.com/pulp-platform/apb/pull/8\nFetched: 2026-04-26\nRepository: pulp-platform/apb\nPull request: #8\nAuthor: meggiman\nState: closed\nBase branch: master\nHead branch: apb_err_slv\nCreated: 2022-12-05T20:41:29Z\nUpdated: 2026-02-14T23:10:24Z\nClosed: 2022-12-20T12:13:33Z\nMerged: 2022-12-20T12:13:33Z\n\n## PR Title\nAdds an APB Error Slave\n\n## PR Description\nDepends on #7\n\n## PR Comments\n\n**meggiman** (Dec 5, 2022):\n\"Depends on #7\"\n\n**meggiman** (Dec 20, 2022):\nMarked the pull request as ready for review.\n\n**paulsc96** (Dec 20, 2022):\nForce-pushed changes and merged commit c736c05 into master.\n\n## Linked Issues\nNo linked issues are referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_apb_pr8", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_apb_pr8.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_apb_pr8", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_apb_pr8"} -{"instance_id": "pulp-platform_axi_pr138", "issue_text": "# axi_xbar: Improve compatibility with vsim 10.6c\n\nInstance: pulp-platform_axi_pr138\nSource: https://github.com/pulp-platform/axi/pull/138\nFetched: 2026-05-03\nRepository: pulp-platform/axi\nPull request: #138\nAuthor: andreaskurth\nState: closed\nBase branch: master\nHead branch: vsim-10.6c-improve-xbar-compatibility\nCreated: 2021-01-11\nUpdated: 2021-01-12\nClosed: 2021-01-12\nMerged: 2021-01-12\n\n## PR Title\naxi_xbar: Improve compatibility with vsim 10.6c\n\n## PR Description\nThis addresses a workaround for vsim 10.6c compatibility issues referenced in issue #133. The version reports an \"illegal output or inout port connection for port 'slv_resp_o'\" error (vsim-3053), which newer versions do not exhibit. The implementation preserves original functionality while resolving the simulator issue. Credit to jsailer for the implementation approach.\n\n## PR Comments\n\n**andreaskurth** (Jan 11, 2021):\nPosted the initial description noting the vsim 10.6c problem and crediting jsailer for the implementation approach.\n\n**andreaskurth** (Jan 11, 2021):\nSelf-assigned the PR.\n\n**andreaskurth** (Jan 12, 2021):\nMerged the PR into master.\n\n## Linked Issues\n\n**Issue #133: vsim 10.6c: axi_xbar: illegal port connection**\nThe error \"Illegal output or inout port connection for port 'slv_resp_o'\" (vsim-3053) appears at /ips/axi/axi/src/axi_xbar.sv(162) when running PULP-rt-example. The reporter encountered this when running PULP-rt-example with vsim 10.6c.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_pr138", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_pr138.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_axi_pr138", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_pr138"} -{"instance_id": "pulp-platform_axi_pr185", "issue_text": "# Fix latch inference on the data width converters with the Mentor Precision synthesis tool\n\nInstance: pulp-platform_axi_pr185\nSource: https://github.com/pulp-platform/axi/pull/185\nFetched: 2026-05-03\nRepository: pulp-platform/axi\nPull request: #185\nAuthor: suehtamacv\nState: closed\nBase branch: master\nHead branch: axi_dwc_fixes\nCreated: 2021-10-08\nUpdated: 2021-11-11\nClosed: 2021-11-11\nMerged: 2021-11-11\n\n## PR Title\nFix latch inference on the data width converters with the Mentor Precision synthesis tool\n\n## PR Description\nCloses #184. This PR reworks a construct that would cause latches to be inferred on both the `axi_dw_downsizer` and the `axi_dw_upsizer`, when synthesizing them with Mentor Precision.\n\n## PR Comments\n\n**suehtamacv** (Oct 8, 2021):\n\"Closes #184. This PR reworks a construct that would case latches to be infered on both the `axi_dw_downsizer` and the `axi_dw_upsizer`, when synthesizing them with the Mentor Precision.\"\n\n**andreaskurth** (Nov 11, 2021):\n\"LGTM, thanks!\"\n\n## Linked Issues\n\n**Issue #184: axi_dw_up/downsizer: Latch inference when synthesizing with Mentor Precision**\nWhen synthesizing with _Mentor Precision_, the tool infers latches in the `axi_dw_upsizer` and `axi_dw_downsizer`. The tool seems to have an issue with the automatic variable `r_data` and `w_data` in both modules. At least in `axi_dw_upsizer` the assignment of `r_data` should still be the default `'0`. So `r_data` is only saving the initialization value, which is then conditionally overwritten. Then however when synthesizing with SYNOPSYS the latches are not there. When adding an `else` statement to the `if` then the latch goes away at least in the first code snippet. So an idea for a fix is to add the `else` condition and remove the automatic variable.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_pr185", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_pr185.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_axi_pr185", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_pr185"} +{"instance_id": "pulp-platform_axi_pr138", "issue_text": "# axi_xbar: Improve compatibility with vsim 10.6c\n\nInstance: pulp-platform_axi_pr138\nSource: https://github.com/pulp-platform/axi/pull/138\nFetched: 2026-05-03\nRepository: pulp-platform/axi\nPull request: #138\nAuthor: andreaskurth\nState: closed\nBase branch: master\nHead branch: vsim-10.6c-improve-xbar-compatibility\nCreated: 2021-01-11\nUpdated: 2021-01-12\nClosed: 2021-01-12\nMerged: 2021-01-12\n\n## PR Title\naxi_xbar: Improve compatibility with vsim 10.6c\n\n## PR Description\nThis addresses a workaround for vsim 10.6c compatibility issues referenced in issue #133. The version reports an \"illegal output or inout port connection for port 'slv_resp_o'\" error (vsim-3053), which newer versions do not exhibit. The implementation preserves original functionality while resolving the simulator issue. Credit to jsailer for the implementation approach.\n\n## PR Comments\n\n**andreaskurth** (Jan 11, 2021):\nPosted the initial description noting the vsim 10.6c problem and crediting jsailer for the implementation approach.\n\n**andreaskurth** (Jan 11, 2021):\nSelf-assigned the PR.\n\n**andreaskurth** (Jan 12, 2021):\nMerged the PR into master.\n\n## Linked Issues\n\n**Issue #133: vsim 10.6c: axi_xbar: illegal port connection**\nThe error \"Illegal output or inout port connection for port 'slv_resp_o'\" (vsim-3053) appears at /ips/axi/axi/src/axi_xbar.sv(162) when running PULP-rt-example. The reporter encountered this when running PULP-rt-example with vsim 10.6c.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_pr138", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_pr138.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_axi_pr138", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/pulp-platform_axi_pr138"} +{"instance_id": "pulp-platform_axi_pr185", "issue_text": "# Fix latch inference on the data width converters with the Mentor Precision synthesis tool\n\nInstance: pulp-platform_axi_pr185\nSource: https://github.com/pulp-platform/axi/pull/185\nFetched: 2026-05-03\nRepository: pulp-platform/axi\nPull request: #185\nAuthor: suehtamacv\nState: closed\nBase branch: master\nHead branch: axi_dwc_fixes\nCreated: 2021-10-08\nUpdated: 2021-11-11\nClosed: 2021-11-11\nMerged: 2021-11-11\n\n## PR Title\nFix latch inference on the data width converters with the Mentor Precision synthesis tool\n\n## PR Description\nCloses #184. This PR reworks a construct that would cause latches to be inferred on both the `axi_dw_downsizer` and the `axi_dw_upsizer`, when synthesizing them with Mentor Precision.\n\n## PR Comments\n\n**suehtamacv** (Oct 8, 2021):\n\"Closes #184. This PR reworks a construct that would case latches to be infered on both the `axi_dw_downsizer` and the `axi_dw_upsizer`, when synthesizing them with the Mentor Precision.\"\n\n**andreaskurth** (Nov 11, 2021):\n\"LGTM, thanks!\"\n\n## Linked Issues\n\n**Issue #184: axi_dw_up/downsizer: Latch inference when synthesizing with Mentor Precision**\nWhen synthesizing with _Mentor Precision_, the tool infers latches in the `axi_dw_upsizer` and `axi_dw_downsizer`. The tool seems to have an issue with the automatic variable `r_data` and `w_data` in both modules. At least in `axi_dw_upsizer` the assignment of `r_data` should still be the default `'0`. So `r_data` is only saving the initialization value, which is then conditionally overwritten. Then however when synthesizing with SYNOPSYS the latches are not there. When adding an `else` statement to the `if` then the latch goes away at least in the first code snippet. So an idea for a fix is to add the `else` condition and remove the automatic variable.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_pr185", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_pr185.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_axi_pr185", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/pulp-platform_axi_pr185"} {"instance_id": "pulp-platform_axi_pr224", "issue_text": "# Compilation error of axi_lite_mux_intf with XSim\n\nI get errors when trying to simulate the axi_lite_mux_intf module with XSim, these are some of them:\r\nERROR: [VRFC 10-2991] 'aw' is not declared under prefix 'slv_reqs_i' [axi_lite_mux.sv:129]\r\nERROR: [VRFC 10-2991] 'aw_valid' is not declared under prefix 'slv_reqs_i' [axi_lite_mux.sv:130]\r\nERROR: [VRFC 10-2991] 'aw_ready' is not declared under prefix 'slv_resps_o' [axi_lite_mux.sv:131]\r\nERROR: [VRFC 10-2991] 'w' is not declared under prefix 'slv_reqs_i' [axi_lite_mux.sv:222]\r\nERROR: [VRFC 10-2991] 'w_valid' is not declared under prefix 'slv_reqs_i' [axi_lite_mux.sv:223]\r\n\r\nI realized that the `axi_lite_mux` instantiation lacks the definition of the `axi_req_t` and `axi_resp_t` types, which are `logic` by default. I added these two lines and it works as expected:\r\n``` \r\naxi_lite_mux #(\r\n .aw_chan_t ( aw_chan_t ), // AW Channel Type\r\n .w_chan_t ( w_chan_t ), // W Channel Type\r\n .b_chan_t ( b_chan_t ), // B Channel Type\r\n .ar_chan_t ( ar_chan_t ), // AR Channel Type\r\n .r_chan_t ( r_chan_t ), // R Channel Type\r\n+ .axi_req_t ( axi_req_t ),\r\n+ .axi_resp_t ( axi_resp_t ),\r\n .NoSlvPorts ( NoSlvPorts ), // Number of slave ports\r\n .MaxTrans ( MaxTrans ),\r\n .FallThrough ( FallThrough ),\r\n .SpillAw ( SpillAw ),\r\n .SpillW ( SpillW ),\r\n .SpillB ( SpillB ),\r\n .SpillAr ( SpillAr ),\r\n .SpillR ( SpillR )\r\n) \r\n```\r\nSo probably this is just it, or am I doing something wrong?\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_pr224", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_pr224.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_axi_pr224", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_pr224"} {"instance_id": "pulp-platform_axi_pr228", "issue_text": "# AXI_BUS instead of AXI_LITE in axi_lite_mux_intf\n\nI am having issues elaborating `axi_lite_mux_intf` with Verilator. Basically it complains that it expects an `AXI_BUS` interface but it is getting an `AXI_LITE` one:\r\n\r\n```\r\n%Error: /path/Top_asic.sv:2000:6: Port 'mst' expects 'AXI_BUS' interface but pin connects 'AXI_LITE' interface\r\n: ... In instance chip_top.Top_asic_inst\r\n 2000 | .mst (axi_sauria)\r\n```\r\nThis is because in the module definition of `axi_lite_mux_intf` (in `axi_lite_mux.sv`) we have:\r\n\r\n```\r\n(\r\n input logic clk_i, // Clock\r\n input logic rst_ni, // Asynchronous reset active low\r\n input logic test_i, // Testmode enable\r\n AXI_BUS.Slave slv [NoSlvPorts-1:0], // slave ports\r\n AXI_BUS.Master mst // master port\r\n);\r\n```\r\n\r\nWhere the ports `slv` and `mst` are incorrectly declared as `AXI_BUS`. Changing both to `AXI_LITE` seems to solve the problem for me.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_pr228", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_pr228.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_axi_pr228", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_pr228"} {"instance_id": "pulp-platform_axi_pr245", "issue_text": "# axi_lite_mux: Reduce complexity of master port W channel\n\nInstance: pulp-platform_axi_pr245\nSource: https://github.com/pulp-platform/axi/pull/245\nFetched: 2026-05-03\nRepository: pulp-platform/axi\nPull request: #245\nAuthor: andreaskurth\nState: closed\nBase branch: master\nHead branch: axi_lite_mux-shorten-mst_w_chan\nCreated: 2022-08-06\nUpdated: 2022-08-06\nClosed: 2022-08-06\nMerged: 2022-08-06\n\n## PR Title\naxi_lite_mux: Reduce complexity of master port W channel\n\n## PR Description\nReduce complexity of W channel at master port by removing an unnecessary multiplexer. Resolves #243.\n\n## PR Comments\n\n**andreaskurth** (Aug 6, 2022):\nPosted the PR description above with reference to issue #243.\n\n## Linked Issues\n\n**Issue #243: Tie mst_w_chan to '0 when mst_w_valid!=0.**\nThe reporter referenced the assignment in `axi_lite_mux.sv`, observing that the muxes seem redundant and asking whether this is on purpose. If not, the muxes could be removed and replaced with `assign mst_w_chan = slv_reqs_i[w_select].w;`.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_pr245", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_pr245.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_axi_pr245", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_pr245"} @@ -382,10 +382,10 @@ {"instance_id": "pulp-platform_axi_riscv_atomics_pr31", "issue_text": "# lrsc: Fix burst invalidation length\n\nInstance: pulp-platform_axi_riscv_atomics_pr31\nSource: https://github.com/pulp-platform/axi_riscv_atomics/pull/31\nFetched: 2026-05-03\nRepository: pulp-platform/axi_riscv_atomics\nPull request: #31\nAuthor: niwis\nState: closed\nBase branch: master\nHead branch: nwistoff/lrsc-burst-len\nCreated: 2023-10-02\nUpdated: 2023-10-05\nClosed: 2023-10-05\nMerged: 2023-10-05\n\n## PR Title\nlrsc: Fix burst invalidation length\n\n## PR Description\nTerminate invalidation after the last beat. Fixes #30.\n\n## PR Comments\n\n**niwis** (Oct 2, 2023):\nRequested review from SamuelRiedel.\n\n**SamuelRiedel** (Oct 5, 2023):\nForce-pushed the branch with commit 427f84d.\n\n**SamuelRiedel** (Oct 5, 2023):\nMerged commit 424697e into master and deleted the nwistoff/lrsc-burst-len branch.\n\n## Linked Issues\n\n**Issue #30: AW burst of length N clears N+1 addresses**\nWhen an AW burst of length N with start address A is sent to the axi_riscv_lrsc module, it submits a check+clear request for addresses [A, A+N], but the correct range would be [A, A+(N-1)]. Probably it would be sufficient to change line 761 from `clr_len_d = aw_res_len - 1;` to `clr_len_d = aw_res_len - 2;`.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_riscv_atomics_pr31", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_riscv_atomics_pr31.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_axi_riscv_atomics_pr31", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_riscv_atomics_pr31"} {"instance_id": "pulp-platform_axi_riscv_atomics_pr33", "issue_text": "# Enable ID queues full bandwidth feature through parameter.\n\nInstance: pulp-platform_axi_riscv_atomics_pr33\nSource: https://github.com/pulp-platform/axi_riscv_atomics/pull/33\nFetched: 2026-04-26\nRepository: pulp-platform/axi_riscv_atomics\nPull request: #33\nAuthor: yvantor\nState: closed\nBase branch: master\nHead branch: astral\nCreated: 2024-04-17T05:47:45Z\nUpdated: 2024-05-08T10:12:37Z\nClosed: 2024-05-08T10:12:36Z\nMerged: 2024-05-08T10:12:36Z\n\n## PR Title\nEnable ID queues full bandwidth feature through parameter.\n\n## PR Description\n(No PR body provided.)\n\n## PR Comments\n\n**yvantor** (Apr 17, 2024):\nRequested review from SamuelRiedel.\n\n**SamuelRiedel** (Apr 30, 2024):\n\"Thanks. Generally, it looks good to me, but could you change the default to 1 to not change the default for other designs?\"\n\n**yvantor** (May 8, 2024):\n\"Should be done, thank you!\"\n\n**SamuelRiedel** (May 8, 2024):\nApproved the changes and merged the PR.\n\n## Linked Issues\nNo linked issues are referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_riscv_atomics_pr33", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_riscv_atomics_pr33.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_axi_riscv_atomics_pr33", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_riscv_atomics_pr33"} {"instance_id": "pulp-platform_axi_riscv_atomics_pr35", "issue_text": "# Fix Non-Blocking Assignment in LRSC FF\n\nInstance: pulp-platform_axi_riscv_atomics_pr35\nSource: https://github.com/pulp-platform/axi_riscv_atomics/pull/35\nFetched: 2026-04-26\nRepository: pulp-platform/axi_riscv_atomics\nPull request: #35\nAuthor: domenicw\nState: closed\nBase branch: master\nHead branch: domenicw/fix/lrsc_ff_non_blocking\nCreated: 2024-04-29T07:18:39Z\nUpdated: 2024-04-29T15:43:08Z\nClosed: 2024-04-29T15:43:07Z\nMerged: 2024-04-29T15:43:07Z\n\n## PR Title\nFix Non-Blocking Assignment in LRSC FF\n\n## PR Description\nThe blocking assignment causes the `clr_len_q` to take an incorrect value during consecutive AXI bursts (value zero from the proceeding burst instead of the actual value). This leads to an underflow of the length value and the counter has to decrement until it reaches one and the `AW_BURST` state can finally be left. This issue was discovered under Verilator. The fix results in a 10x simulation speed improvement.\n\n## PR Comments\n\n**domenicw** (Apr 29, 2024):\nSubmitted the PR with the description above.\n\n**SamuelRiedel** (Apr 29, 2024):\n\"Good catch. Thanks a lot. The internal CI also passed, of course. :)\"\n\n## Linked Issues\nNo linked issues are referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_riscv_atomics_pr35", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_riscv_atomics_pr35.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_axi_riscv_atomics_pr35", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_riscv_atomics_pr35"} -{"instance_id": "pulp-platform_axi_riscv_atomics_pr37", "issue_text": "# Improve code style\n\nInstance: pulp-platform_axi_riscv_atomics_pr37\nSource: https://github.com/pulp-platform/axi_riscv_atomics/pull/37\nFetched: 2026-04-26\nRepository: pulp-platform/axi_riscv_atomics\nPull request: #37\nAuthor: niwis\nState: closed\nBase branch: master\nHead branch: nw/lrsc-seq-nonblock\nCreated: 2024-07-25T18:42:36Z\nUpdated: 2025-05-07T08:33:44Z\nClosed: 2025-05-07T08:33:42Z\nMerged: 2025-05-07T08:33:42Z\n\nThis aligns coding style and fixes Verilator warnings:\r\n- `axi_riscv_lrsc`: Use non-blocking assignments in sequential block.\r\n- `axi_res_tbl`: Declare the `match` signal outside the `always_comb` block.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_riscv_atomics_pr37", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_riscv_atomics_pr37.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_axi_riscv_atomics_pr37", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_riscv_atomics_pr37"} +{"instance_id": "pulp-platform_axi_riscv_atomics_pr37", "issue_text": "# Improve code style\n\nInstance: pulp-platform_axi_riscv_atomics_pr37\nSource: https://github.com/pulp-platform/axi_riscv_atomics/pull/37\nFetched: 2026-04-26\nRepository: pulp-platform/axi_riscv_atomics\nPull request: #37\nAuthor: niwis\nState: closed\nBase branch: master\nHead branch: nw/lrsc-seq-nonblock\nCreated: 2024-07-25T18:42:36Z\nUpdated: 2025-05-07T08:33:44Z\nClosed: 2025-05-07T08:33:42Z\nMerged: 2025-05-07T08:33:42Z\n\nThis aligns coding style and fixes Verilator warnings:\r\n- `axi_riscv_lrsc`: Use non-blocking assignments in sequential block.\r\n- `axi_res_tbl`: Declare the `match` signal outside the `always_comb` block.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_riscv_atomics_pr37", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_riscv_atomics_pr37.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_axi_riscv_atomics_pr37", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/pulp-platform_axi_riscv_atomics_pr37"} {"instance_id": "pulp-platform_axi_riscv_atomics_pr38", "issue_text": "# Make the `CUT_OUP_POP_INP_GNT` ID queue parameter user visible and bump common cells\n\nInstance: pulp-platform_axi_riscv_atomics_pr38\nSource: https://github.com/pulp-platform/axi_riscv_atomics/pull/38\nFetched: 2026-04-26\nRepository: pulp-platform/axi_riscv_atomics\nPull request: #38\nAuthor: ricted98\nState: closed\nBase branch: master\nHead branch: rt/id-queue-cut-oup-pop-inp-gnt\nCreated: 2024-08-22T08:28:11Z\nUpdated: 2024-08-26T14:15:12Z\nClosed: 2024-08-26T14:15:09Z\nMerged: 2024-08-26T14:15:09Z\n\nThe use of `FULL_BANDWIDTH=1` ID queues paired with `CUT_OUP_POP_INP_GNT=0` (default value) might lead to combinational loops with downstream IPs. Cutting the combinational path between input and output solves the problem.\r\n\r\nThis PR extends https://github.com/pulp-platform/axi_riscv_atomics/pull/34 to make the `CUT_OUP_POP_INP_GNT` parameter user visible and bumps the `common_cells` dependency.\r\n\r\nWould it be better to allow more granularity, i.e. allowing for individual ID queues tuning?\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_riscv_atomics_pr38", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_riscv_atomics_pr38.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_axi_riscv_atomics_pr38", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_riscv_atomics_pr38"} {"instance_id": "pulp-platform_axi_riscv_atomics_pr39", "issue_text": "# Add support for limited number of reservations\n\nInstance: pulp-platform_axi_riscv_atomics_pr39\nSource: https://github.com/pulp-platform/axi_riscv_atomics/pull/39\nFetched: 2026-04-26\nRepository: pulp-platform/axi_riscv_atomics\nPull request: #39\nAuthor: micprog\nState: closed\nBase branch: master\nHead branch: num_reservations\nCreated: 2025-05-06T15:01:46Z\nUpdated: 2026-02-19T15:39:18Z\nClosed: 2026-02-19T15:39:16Z\nMerged: 2026-02-19T15:39:16Z\n\n## PR Title\nAdd support for limited number of reservations\n\n## PR Description\nIf limited LR/SC support is OK, NUM_RESERVATIONS can be set to reduce how many active atomics are supported, significantly improving PPA. This means that some reservations may be cleared without another actor accessing that address, as too many actors are reserving at the same time. If the parameter is not set, existing code will remain, so is backwards-compatible.\n\n## PR Comments\n\n**micprog** (May 6, 2025):\nProvided initial description explaining the feature's purpose and backward compatibility.\n\n**paulsc96** (May 7, 2025):\nApproved the changes after reviewing the pull request files.\n\n## Linked Issues\nNo linked issues are referenced in this pull request.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_riscv_atomics_pr39", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_riscv_atomics_pr39.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_axi_riscv_atomics_pr39", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_riscv_atomics_pr39"} -{"instance_id": "pulp-platform_carfield_pr27", "issue_text": "# hw: Bump security island\n\nInstance: pulp-platform_carfield_pr27\nSource: https://github.com/pulp-platform/carfield/pull/27\nFetched: 2026-05-03\nRepository: pulp-platform/carfield\nPull request: #27\nAuthor: alex96295\nState: closed\nBase branch: main\nHead branch: aottaviano/synth-fix\nCreated: 2023-05-09\nUpdated: 2023-07-21\nClosed: 2023-05-09\nMerged: 2023-05-09\n\n## PR Title\nhw: Bump security island\n\n## PR Description\nRemove behavioral string parameters: use combinational ROM and OTP. Fixes #26.\n\n## PR Comments\n\n**alex96295** (May 9, 2023):\n\"Remove behavioral string parameters: use combinational ROM and OTP\" / \"Fixes #26\"\n\n**alex96295** (May 9, 2023):\nAdded the bug label.\n\n**alex96295** (May 9, 2023):\nSelf-assigned the PR.\n\n**alex96295** (May 9, 2023):\nRequested review from luca-valente as code owner.\n\n**alex96295** (May 9, 2023):\nMerged commit 37d82b5 into main.\n\n**micprog** (Jul 21, 2023):\nDeleted the aottaviano/synth-fix branch.\n\n## Linked Issues\n\n**Issue #26: SYNTHESIS ERROR**\nLine 294 and 295 of carfield_pkg generate synthesis errors:\n\"Error: ...carfield_pkg.sv:294: The construct 'string' is not supported in synthesis.\"\n\"Error: ...carfield_pkg.sv:295: The construct 'string' is not supported in synthesis.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_carfield_pr27", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_carfield_pr27.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_carfield_pr27", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_carfield_pr27"} +{"instance_id": "pulp-platform_carfield_pr27", "issue_text": "# hw: Bump security island\n\nInstance: pulp-platform_carfield_pr27\nSource: https://github.com/pulp-platform/carfield/pull/27\nFetched: 2026-05-03\nRepository: pulp-platform/carfield\nPull request: #27\nAuthor: alex96295\nState: closed\nBase branch: main\nHead branch: aottaviano/synth-fix\nCreated: 2023-05-09\nUpdated: 2023-07-21\nClosed: 2023-05-09\nMerged: 2023-05-09\n\n## PR Title\nhw: Bump security island\n\n## PR Description\nRemove behavioral string parameters: use combinational ROM and OTP. Fixes #26.\n\n## PR Comments\n\n**alex96295** (May 9, 2023):\n\"Remove behavioral string parameters: use combinational ROM and OTP\" / \"Fixes #26\"\n\n**alex96295** (May 9, 2023):\nAdded the bug label.\n\n**alex96295** (May 9, 2023):\nSelf-assigned the PR.\n\n**alex96295** (May 9, 2023):\nRequested review from luca-valente as code owner.\n\n**alex96295** (May 9, 2023):\nMerged commit 37d82b5 into main.\n\n**micprog** (Jul 21, 2023):\nDeleted the aottaviano/synth-fix branch.\n\n## Linked Issues\n\n**Issue #26: SYNTHESIS ERROR**\nLine 294 and 295 of carfield_pkg generate synthesis errors:\n\"Error: ...carfield_pkg.sv:294: The construct 'string' is not supported in synthesis.\"\n\"Error: ...carfield_pkg.sv:295: The construct 'string' is not supported in synthesis.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_carfield_pr27", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_carfield_pr27.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_carfield_pr27", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/pulp-platform_carfield_pr27"} {"instance_id": "pulp-platform_carfield_pr41", "issue_text": "# Add atomics support to shared L2 memory\n\nInstance: pulp-platform_carfield_pr41\nSource: https://github.com/pulp-platform/carfield/pull/41\nFetched: 2026-05-03\nRepository: pulp-platform/carfield\nPull request: #41\nAuthor: alex96295\nState: closed\nBase branch: main\nHead branch: aottaviano/l2-atomics\nCreated: 2023-05-17\nUpdated: 2023-05-30\nClosed: 2023-05-30\nMerged: 2023-05-30\n\n## PR Title\nAdd atomics support to shared L2 memory\n\n## PR Description\nExpose extra parameters to config the `axi_riscv_atomics_structs`. They default to Cheshire, which is fine for now. Fixes #34.\n\n## PR Comments\n\n**alex96295** (May 17, 2023):\n\"Expose extra parameters to config the `axi_riscv_atomics_structs`. They default to Cheshire, which is fine for now.\"\n\n**husterZC** (May 17, 2023):\n\"Aha ;) , Thanks Ale!\"\n\n**husterZC** (May 17, 2023):\n\"Should we also change the `Bender.lock` there?\"\n\n**alex96295** (May 17, 2023):\n\"I upstreamed it\"\n\n**alex96295** (May 21, 2023):\n\"Rebased onto main\"\n\n**alex96295** (May 30, 2023):\n\"Rebased onto main\"\n\n**alex96295** (May 30, 2023):\n\"lgtm\"\n\n## Linked Issues\n\n**Issue #34: Check `atomics`: `axi_riscv_atomics_structs` before the L2 SPM**\nAtomics support is needed towards every memory inside `carfield`. `Cheshire` already instantiates `axi_riscv_atomics_structs` before the main memory, the debug module and the `idma` slave port. We need it before the `L2SPM`.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_carfield_pr41", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_carfield_pr41.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_carfield_pr41", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_carfield_pr41"} {"instance_id": "pulp-platform_cheshire_pr189", "issue_text": "# hw: Fix uncached SPM execute region\n\nInstance: pulp-platform_cheshire_pr189\nSource: https://github.com/pulp-platform/cheshire/pull/189\nFetched: 2026-04-26\nRepository: pulp-platform/cheshire\nPull request: #189\nAuthor: paulsc96\nState: closed\nBase branch: main\nHead branch: paulsc/spmu-ex\nCreated: 2025-03-28T11:57:58Z\nUpdated: 2025-04-13T18:42:51Z\nClosed: 2025-04-13T18:42:50Z\nMerged: 2025-04-13T18:42:50Z\n\nFixes #188.\r\n\r\nChanges:\r\n\r\n* Add uncached SPM as its own executable region (simplify parameterization a bit in the process)\r\n* Add a test `spm_uncached` executing from uncached SPM and verifying it is not cached\r\n\r\nAdditional changes:\r\n\r\n* Add argument to DMA calls to enable dynamic use of decoupling flags (this breaks DMA API compatibility)\r\n* Add `wfi` to default trap handler (this quiets core on exceptions, including on unhandled `ebreak`)\n\n## Local Reproducer Notes\n\n# pulp-platform_cheshire_pr189\n\nMinimal fail-to-pass Verilator case for the uncached SPM execute region fix.\n\nThe buggy configuration models cached and uncached SPM as one large executable region. The patch creates an explicit `AmSpmUnc` region and exposes cached and uncached SPM as separate execute rules.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_cheshire_pr189", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_cheshire_pr189.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_cheshire_pr189", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_cheshire_pr189"} {"instance_id": "pulp-platform_cheshire_pr203", "issue_text": "# treewide: Update iDMA and fix 1D transfers\n\nInstance: pulp-platform_cheshire_pr203\nSource: https://github.com/pulp-platform/cheshire/pull/203\nFetched: 2026-04-26\nRepository: pulp-platform/cheshire\nPull request: #203\nAuthor: alex96295\nState: closed\nBase branch: main\nHead branch: aottaviano/dma\nCreated: 2025-05-07T12:48:47Z\nUpdated: 2025-07-08T20:06:36Z\nClosed: 2025-07-08T20:06:35Z\nMerged: 2025-07-08T20:06:35Z\n\n* [x] Move DMA to Regbus, simplifying interconnect and fixing a known issue with accessing beyond 32-bit boundary\r\n* [x] Fix DMA HAL for 1D transfers (currently not working)\r\n* [x] Update iDMA\r\n* [x] Add new regression test for 1D transfers to CI (https://iis-git.ee.ethz.ch/pulp-restricted/cheshire-nonfree/-/merge_requests/22)\r\n* [x] Fix #208.\r\n* [x] Add new regression test for accesses beyond 32-bit boundary (access over serial link)\n\n## Local Reproducer Notes\n\npulp-platform/cheshire PR 203 reproducer.\n\nThe reduced RTL models the 1D DMA programming path through the AXI-to-register\nadapter. The buggy snapshot instantiates the legacy adapter, which gates a\nvalid register write with test mode and drops the one-cycle start command.\nThe patch switches the wrapper to the v2 adapter interface used by the PR.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_cheshire_pr203", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_cheshire_pr203.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_cheshire_pr203", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_cheshire_pr203"} @@ -395,7 +395,7 @@ {"instance_id": "pulp-platform_common_cells_pr155", "issue_text": "# Update `fall_through_register`'s fifo to `fifo_v3`\n\nInstance: pulp-platform_common_cells_pr155\nSource: https://github.com/pulp-platform/common_cells/pull/155\nFetched: 2026-05-03\nRepository: pulp-platform/common_cells\nPull request: #155\nAuthor: michael-platzer\nState: closed\nBase branch: master\nHead branch: fix_fall_through_fifo\nCreated: 2022-09-16\nUpdated: 2022-09-16\nClosed: 2022-09-16\nMerged: 2022-09-16\n\n## PR Title\nUpdate `fall_through_register`'s fifo to `fifo_v3`\n\n## PR Description\nThe `fall_through_register` still uses the deprecated `fifo_v2`. This PR updates it to `fifo_v3`. Fixes #84.\n\n## PR Comments\n\n**niwis** (Sep 16, 2022):\nRequested changes: \"Could you add the `usage_o` port of `fifo_v3` in this instantiation so that the port list is complete?\"\n\n**michael-platzer** (Sep 16, 2022):\n\"Sure, added it.\"\n\n**niwis** (Sep 16, 2022):\nApproved: \"Thanks! LGTM\"\n\n## Linked Issues\n\n**Issue #84: fall_through_register uses deprecated fifo_v2**\nShould probably be updated to `fifo_v3`.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_common_cells_pr155", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_common_cells_pr155.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_common_cells_pr155", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_common_cells_pr155"} {"instance_id": "pulp-platform_common_cells_pr170", "issue_text": "# Add shift_register_gated\n\nInstance: pulp-platform_common_cells_pr170\nSource: https://github.com/pulp-platform/common_cells/pull/170\nFetched: 2026-05-03\nRepository: pulp-platform/common_cells\nPull request: #170\nAuthor: qian-gu\nState: closed\nBase branch: master\nHead branch: master\nCreated: 2023-02-22\nUpdated: 2023-04-14\nClosed: 2023-04-14\nMerged: 2023-04-14\n\n## PR Title\nAdd shift_register_gated\n\n## PR Description\nA shift register with clock gating.\n\n## PR Comments\n\n**niwis** (Feb 23, 2023):\nRequested updates to avoid code fragmentation: adapt existing shift_reg module to instantiate the new module, tie valid_i to 1'b1, and update configuration files (Bender.yml, README.md, src_files.yml). Also requested rebase to master due to CI updates.\n\n**niwis** (Feb 23, 2023):\nFlagged unnecessary `default_nettype none` directive at module start; suggested removal for consistency.\n\n**niwis** (Feb 23, 2023):\nFlagged unnecessary `default_nettype wire` at module end.\n\n**niwis** (Feb 23, 2023):\nRequested coding convention alignment for variable declarations: consolidate related declarations.\n\n**qian-gu** (Feb 23, 2023):\nExplained the directive ensures explicit variable declarations; committed to removing it.\n\n**qian-gu** (Feb 27, 2023):\nReported CI authentication error attempting gitlab mirror push with HTTP credentials issue.\n\n**niwis** (Apr 14, 2023):\nApproved changes, acknowledged CI failures due to missing github secrets, noted working on solution.\n\n## Linked Issues\n\n**Issue #169: A gated shift register module**\nI have developed a new version of shift_reg which has a valid flag for data to enable DC insert ICG for the internal datapath, the new version shift_reg is backward compatible with the older one and has a better power comuption. Is it welcomed to add it to this library?\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_common_cells_pr170", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_common_cells_pr170.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_common_cells_pr170", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_common_cells_pr170"} {"instance_id": "pulp-platform_common_cells_pr182", "issue_text": "# Clock divider configuration fails if divider value is 0\n\n@meggiman I ran into another issue with the clock divider.\n\nFollowing the description\n> // It is thus safe to statically tie the valid signal to logic high if\n> // we can guarantee, that the div_i value remains stable long enough (upper\n> // limit 2 output clock cycles).\n\nI tied `valid_i` to 1 and connected `div_i` to a register which has a reset value 0.\n\nThat's when I noticed that after `div_q = 0` is loaded, I'm not able to reconfigure the clock divider.\n\nAs far as I understood, it hangs in the `WAIT_END_PERIOD` state, because the following condition can never be satisfied.\nhttps://github.com/pulp-platform/common_cells/blob/f9528fa6e4d3080605c01074bdaf62dcb4aff7d2/src/clk_int_div.sv#L187\n\nPR Title: Fix deadlock on div_i == 0 and avoid hold issues on ungated_output_clock\n\nPR #182 (Merged May 11, 2023)\n\nDescription:\nThe PR addresses two issues in the clock divider component:\n\n1. Deadlock Prevention: Instead of directly storing div_i in the internal register div_q, the code now normalizes the value to be strictly greater than 0, preventing deadlock when preloading with zero.\n\n2. Hold Issues Resolution: The PR removes combinational checks on the ungated_output_clock phase to avoid synthesis hold violations. A dedicated flip-flop now tracks the output clock gate status instead of relying on combinational logic.\n\nThis change resolves GitHub issue #172.\n\nComments:\n\n@fimtrey (May 10, 2023):\n\"I tested in on a pynq-z2 FPGA and it works for my case and there're no hold issues anymore. Thank you @meggiman!\"\n\n@niwis (May 11, 2023):\nApproved with comment: \"Thanks! LGTM\"\n\nLinked Issue:\n#172: Clock divider configuration fails if divider value is 0\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_common_cells_pr182", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_common_cells_pr182.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_common_cells_pr182", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_common_cells_pr182"} -{"instance_id": "pulp-platform_common_cells_pr188", "issue_text": "# popcount for INPUT_WIDTH=1\n\n`popcount.sv` contradicts itself in the description and this commit https://github.com/pulp-platform/common_cells/commit/bf4db7cfa01030f36a59c1a4d21ee233f6aee01e whether the case `INPUT_WIDTH=1` is supported.\n\nFurthermore, it seems like the https://github.com/pulp-platform/common_cells/commit/bf4db7cfa01030f36a59c1a4d21ee233f6aee01e doesn't properly add full support for `INPUT_WIDTH=1` since\n\n```verilog\nlogic [PopcountWidth-2:0] left_child_result, right_child_result;\n```\n\n(from here https://github.com/pulp-platform/common_cells/blob/master/src/popcount.sv#L30)\n\nbecomes negative causing at least VCS to crash. A simple hacky fix is to change the `-2` to `-1` but I'm not sure if that works out well.\n\nMaybe @meggiman can you comment on this (since you seem to know the most being the designer of this module) ?\n\nPR Title: Simplify popcount and add proper support for all input widths\n\nPR #188 (Merged May 30, 2023)\n\nDescription:\nThe original popcount implementation relied on a recursive binary adder tree using nested modules. Testing with modern synthesis tools revealed that describing the popcount logic as a flat for loop achieved equal or superior results with faster compilation times. This refactor also resolves issue #187.\n\nComments:\n\n@meggiman (May 24, 2023):\n\"The popcount implementation so far used a recursive implementation using a binary adder tree. However, experiments using reasonably modern synthesis tools show that the logic optimization heuristics achieve the same or better results in less compilation time when the popcount logic is described in a flat for loop instead of nested modules.\"\n\n@bluewww (May 24, 2023):\n\"LGTM!\"\n\n@niwis (May 29, 2023):\n\"Thanks a lot! Just one typo from my side\" [Requested changes, later approved after corrections]\n\nLinked Issue:\n#187: popcount for INPUT_WIDTH=1\n\nParticipants:\n- @meggiman (author)\n- @niwis (reviewer/merger)\n- @bluewww (reviewer)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_common_cells_pr188", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_common_cells_pr188.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_common_cells_pr188", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_common_cells_pr188"} +{"instance_id": "pulp-platform_common_cells_pr188", "issue_text": "# popcount for INPUT_WIDTH=1\n\n`popcount.sv` contradicts itself in the description and this commit https://github.com/pulp-platform/common_cells/commit/bf4db7cfa01030f36a59c1a4d21ee233f6aee01e whether the case `INPUT_WIDTH=1` is supported.\n\nFurthermore, it seems like the https://github.com/pulp-platform/common_cells/commit/bf4db7cfa01030f36a59c1a4d21ee233f6aee01e doesn't properly add full support for `INPUT_WIDTH=1` since\n\n```verilog\nlogic [PopcountWidth-2:0] left_child_result, right_child_result;\n```\n\n(from here https://github.com/pulp-platform/common_cells/blob/master/src/popcount.sv#L30)\n\nbecomes negative causing at least VCS to crash. A simple hacky fix is to change the `-2` to `-1` but I'm not sure if that works out well.\n\nMaybe @meggiman can you comment on this (since you seem to know the most being the designer of this module) ?\n\nPR Title: Simplify popcount and add proper support for all input widths\n\nPR #188 (Merged May 30, 2023)\n\nDescription:\nThe original popcount implementation relied on a recursive binary adder tree using nested modules. Testing with modern synthesis tools revealed that describing the popcount logic as a flat for loop achieved equal or superior results with faster compilation times. This refactor also resolves issue #187.\n\nComments:\n\n@meggiman (May 24, 2023):\n\"The popcount implementation so far used a recursive implementation using a binary adder tree. However, experiments using reasonably modern synthesis tools show that the logic optimization heuristics achieve the same or better results in less compilation time when the popcount logic is described in a flat for loop instead of nested modules.\"\n\n@bluewww (May 24, 2023):\n\"LGTM!\"\n\n@niwis (May 29, 2023):\n\"Thanks a lot! Just one typo from my side\" [Requested changes, later approved after corrections]\n\nLinked Issue:\n#187: popcount for INPUT_WIDTH=1\n\nParticipants:\n- @meggiman (author)\n- @niwis (reviewer/merger)\n- @bluewww (reviewer)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_common_cells_pr188", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/main/patches/pulp-platform_common_cells_pr188.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_common_cells_pr188", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/pulp-platform_common_cells_pr188"} {"instance_id": "pulp-platform_common_cells_pr222", "issue_text": "# `stream_arbiter` with priority arbitration inherently violates assertion\n\nWhen configuring a `stream_arbiter` or `stream_arbiter_flushable` with `ARBITER = \"prio\"`, it instantiates an `rr_arb_tree` with both the `ExtPrio` and `LockIn` parameters set:\n\nhttps://github.com/pulp-platform/common_cells/blob/0d67563b6b592549542544f1abc0f43e5d4ee8b4/src/stream_arbiter_flushable.sv#L55-L61\n\nHowever, this directly violates an assertion in `rr_arb_tree`:\n\nhttps://github.com/pulp-platform/common_cells/blob/0d67563b6b592549542544f1abc0f43e5d4ee8b4/src/rr_arb_tree.sv#L319\n\nAs a result, any priority stream arbiters instantiated inherently cause a fatal assertion violation.\n\nPR Title: stream_arbiter_flushable: Do not lock prio arbiter\n\nPR #222 (Merged)\n\nDescription:\nThe PR addresses a technical issue with the priority arbiter implementation. According to the submitter, setting `LockIn` while `ExtPrio = 1'b1` violates the constraints of the `rr_arb_tree` and produces no effect. Additionally, locking a decision that may have lower priority contradicts the purpose of using a priority arbiter. The fix clears the `LockIn` parameter for the priority arbiter component.\n\nComments:\n\n@niwis (May 15, 2024):\n\"Setting `LockIn` while `ExtPrio = 1'b1` is disallowed by the `rr_arb_tree` and has no effect.\"\n\n@micprog (Jun 17, 2024):\n\"LGTM\"\n\nLinked Issue:\n#221: stream_arbiter with priority arbitration inherently violates assertion\n\nReviewers:\n- paulsc96 (approved May 15, 2024)\n- micprog (approved Jun 17, 2024)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_common_cells_pr222", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_common_cells_pr222.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_common_cells_pr222", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_common_cells_pr222"} {"instance_id": "pulp-platform_common_cells_pr224", "issue_text": "# `mem_to_banks_detailed`: Ensure no spurious response after full dead write\n\nInstance: pulp-platform_common_cells_pr224\nSource: https://github.com/pulp-platform/common_cells/pull/224\nFetched: 2026-04-26\nRepository: pulp-platform/common_cells\nPull request: #224\nAuthor: micprog\nState: closed\nBase branch: master\nHead branch: michaero/fix_memtobanks_deadwrite\nCreated: 2024-07-11T09:56:08Z\nUpdated: 2024-07-18T12:13:28Z\nClosed: 2024-07-18T12:13:26Z\nMerged: 2024-07-18T12:13:26Z\n\nPR Title: `mem_to_banks_detailed`: Ensure no spurious response after full dead write\n\nPR #224 (Merged)\n\nDescription:\nNo description was provided by the author.\n\nComments:\n\n@niwis (Collaborator) - July 18, 2024:\nReviewer raised three points: (1) Masking `dead_response` with `~dead_write_fifo_empty` makes sense; (2) questioned necessity of reduction changes at specific lines; (3) questioned why `dead_read_fifo` input changed from `bank_oup` to `bank_req`.\n\n@niwis (Collaborator) - July 18, 2024:\nClarified that the input data alignment change was necessary per in-person discussion, while the reductions could be removed.\n\nCommits (titles only):\n1. \"Ensure no spurious response after full dead write\"\n2. \"Fix HideStrb alignment\"\n3. \"Fix lint\"\n4. \"Remove unneeded strb reduction\"\n\nParticipants:\n- @micprog (author)\n- @niwis (reviewer/approver)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_common_cells_pr224", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_common_cells_pr224.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_common_cells_pr224", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_common_cells_pr224"} {"instance_id": "pulp-platform_common_cells_pr225", "issue_text": "# Add credit_counter\n\nInstance: pulp-platform_common_cells_pr225\nSource: https://github.com/pulp-platform/common_cells/pull/225\nFetched: 2026-04-26\nRepository: pulp-platform/common_cells\nPull request: #225\nAuthor: micprog\nState: closed\nBase branch: master\nHead branch: michaero/credit_counter\nCreated: 2024-07-17T15:32:28Z\nUpdated: 2024-07-18T12:03:48Z\nClosed: 2024-07-18T12:03:46Z\nMerged: 2024-07-18T12:03:46Z\n\nPR Title: Add credit_counter\n\nPR #225 (Merged Jul 18, 2024 by niwis into master branch)\n\nDescription:\nNo description was provided by the author.\n\nComments:\n\nmicprog (Jul 17, 2024) - posted no description.\n\nniwis (Jul 18, 2024):\n\"Can we use `FFARNC` instead of tying the load enable?\" — code review suggestion to replace `FFLARNC` with `FFARNC` to avoid manually tying the load enable signal.\n\nniwis (Jul 18, 2024):\nApproved changes after the suggestion was implemented.\n\npaulsc96 (Jul 17, 2024):\nApproved the initial submission.\n\nThe branch michaero/credit_counter was deleted after merge.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_common_cells_pr225", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_common_cells_pr225.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_common_cells_pr225", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_common_cells_pr225"} @@ -418,8 +418,8 @@ {"instance_id": "pulp-platform_hci_pr27", "issue_text": "# Syntax error in `hci_helpers.svh` in Vivado\n\n- Source URL: https://github.com/pulp-platform/hci/issues/26\n\nThe helper macros in `hci_helpers.svh` https://github.com/pulp-platform/hci/blob/82dfd3ffe0c4d9ef77c9a6d4efbbb0411aa2662e/rtl/common/hci_helpers.svh#L19-L38 distinguish between synthesis and simulation tools with a `ifdef SYNTHESIS` due to different supported features of SystemVerilog. Apparently, Vivado likes the same syntax of simulation tools, which is not the one currently selected.\n\nPR Title: Manage the special case of FPGA targets in hci_helpers.svh\n\nPR #27 (Merged April 24, 2024)\n\nAuthor: FrancescoConti\n\nDescription:\nNo description was provided by the author.\n\nLinked Issue:\n- Title: \"Syntax error in `hci_helpers.svh` in Vivado\"\n- Issue #26\n\nKey Activity:\n- The branch \"26-syntax-error-in-hci_helperssvh-in-vivado\" was deleted after merging.\n- No reviews were recorded.\n- FrancescoConti self-assigned the PR.\n\nComments:\nThe sole comment from FrancescoConti states: \"No description provided.\"\n\nNotes:\nThis PR appears to address a syntax compatibility issue with Vivado (Xilinx's FPGA design tool) by handling FPGA targets as a special case within the SystemVerilog helper file.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_hci_pr27", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_hci_pr27.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_hci_pr27", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_hci_pr27"} {"instance_id": "pulp-platform_hci_pr37", "issue_text": "# RQ3-STABILITY violation in `hwpe_core_mux_ooo`: winner-takes-all ignores no-grant condition\n\n- Source URL: https://github.com/pulp-platform/hci/issues/34\n\n![image](https://github.com/pulp-platform/hci/assets/7882682/b2e9848c-ce99-46fb-8da0-1a36dc453642)\n\nIn some instances, when the `in_req` changes in absence of a `gnt` on the pop side, the MUX will switch priorities incorrectly.\n\nPR Title: Fix #34 by keeping winner_d stable in OOO Mux if there is an input request\n\nPR #37 (Merged May 23, 2024)\n\nAuthor: FrancescoConti\n\nDescription:\nThe pull request addresses a stability issue by preventing re-evaluation of the winner-takes-all output except under specific conditions. According to the author: \"Only re-evaluate WTA output after an output handshake or if any in_req was 0, otherwise a more recent in_req could overtake an older one causing a RQ3-STABILITY issue on the output side.\"\n\nThe author notes this represents a rebase of a previous attempt (PR #36) onto the current master branch.\n\nComments:\n\nFrancescoConti:\nCommented that the change prevents a scenario where newer input requests could improperly supersede older ones, which would violate stability requirements on the output side of the multiplexer.\n\nLinked Issue:\nIssue #34: \"RQ3-STABILITY violation in `hwpe_core_mux_ooo`: winner-takes-all ignores no-grant condition\"\n\nThe PR successfully merged one commit into the master branch.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_hci_pr37", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_hci_pr37.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_hci_pr37", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_hci_pr37"} {"instance_id": "pulp-platform_hci_pr67", "issue_text": "# erroneous r_id commit\n\n- Source URL: https://github.com/pulp-platform/hci/issues/66\n\nThis needs to be reverted: https://github.com/pulp-platform/hci/commit/5421524afca701e45a83d0f1ec47568c019e021a\n\nPR Title: Revert \"Fixed HCI Core Static MUX\"\n\nPR #67 (Merged December 1, 2025)\n\nAuthor: FrancescoConti\nTarget Branch: master\n\nDescription:\nThis pull request reverts commit 5421524 and addresses issue #66 regarding an erroneous commit related to the r_id field.\n\nComments:\n\narpansur (Dec 1, 2025):\n\"The static MUX has an assumption that the select line changes when all the outstanding transactions are complete...\" The commenter explained that the static MUX design assumes select line changes only after all transactions complete. They noted that requiring RID for r_valid would necessitate regressions to existing accelerators and is unnecessary given the MUX's design assumptions.\n\nFrancescoConti (Dec 1, 2025):\nRequested official approval from arpansur to proceed with the merge.\n\narpansur (Dec 1, 2025):\nApproved the changes with \"LGTM :)\"\n\nLinked Issue:\nIssue #66: \"erroneous r_id commit\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_hci_pr67", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_hci_pr67.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_hci_pr67", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_hci_pr67"} -{"instance_id": "pulp-platform_neureka_pr30", "issue_text": "# Depthwise mode is broken from 5a4d22f\n\n- Source URL: https://github.com/pulp-platform/neureka/issues/29\n\nDepthwise mode is broken from commit [5a4d22f](https://github.com/pulp-platform/neureka/commit/5a4d22fb7d1c7fde2d8638c5f64eabd24b7a17dc). The working depthwise version is [1ab44a9](https://github.com/pulp-platform/neureka/commit/1ab44a980e3340755798edd39409665e19c432fe)\n\nPR Title: Fix depthwise\n\nPR #30 (Merged March 26, 2025 by arpansur)\n\nDescription:\nThis PR addresses issue #29 (depthwise mode is broken). The changes include:\n- Fixes bugs from commits 5a4d22f and fcfd25d (the latter is temporarily reverted for later inspection)\n- Introduces depthwise tests in the CI\n\nCommits (titles only):\n1. \"Add DW tests to basic regression\"\n2. \"Fix depthwise issues in accumulator_normquant\"\n3. \"Revert 'Reactivate also binconv gating!' to fix depthwise execution\"\n\nComments:\n\nLuigiGhionda (Author, Mar 10):\nThis PR fixes issue #29 regarding broken depthwise mode functionality and adds CI tests.\n\narpansur (Collaborator, Review):\nSuggested \"adding partial utilised channels instead of only a factor of 32\" and \"tests stressing QW<8\" bitwidth variations.\n\narpansur (Response):\nRecommended expanding test coverage across dimensions like K_IN, K_OUT, H_IN, W_IN, and QW for partial tile utilization.\n\nFrancescoConti (Member, Review):\nApproved with comment \"LGTM except for an unexplained constant\" regarding the 32'h0F constant.\n\nFrancescoConti (Clarification):\nRecommended \"keeping this one dedicated to depthwise\" rather than adding broader test variations in the same PR.\n\nFrancescoConti (Final):\n\"OK, let's merge it then!\"\n\nLinked Issue:\nIssue #29: \"Depthwise mode is broken from 5a4d22f\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_neureka_pr30", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_neureka_pr30.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_neureka_pr30", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_neureka_pr30"} -{"instance_id": "pulp-platform_pulp_soc_pr23", "issue_text": "# AXI_ID_WIDTH wrong parameters\n\nSome fixes are needed for synthesis.\r\nThere are wrong parameters when instantiating AXI bus to communicate with the cluster.\r\n\r\nCurrent version:\r\n\r\nAXI_BUS_ASYNC #(\r\n .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ),\r\n .AXI_DATA_WIDTH ( AXI_DATA_OUT_WIDTH ),\r\n **.AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ),**\r\n .AXI_USER_WIDTH ( AXI_USER_WIDTH ),\r\n .BUFFER_WIDTH ( BUFFER_WIDTH )\r\n ) s_data_master ();\r\n AXI_BUS_ASYNC #(\r\n .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ),\r\n .AXI_DATA_WIDTH ( AXI_DATA_IN_WIDTH ),\r\n **.AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ),**\r\n .AXI_USER_WIDTH ( AXI_USER_WIDTH ),\r\n .BUFFER_WIDTH ( BUFFER_WIDTH )\r\n ) s_data_slave ();\r\n\r\n AXI_BUS #(\r\n .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ),\r\n .AXI_DATA_WIDTH ( AXI_DATA_IN_WIDTH ),\r\n **.AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ),**\r\n .AXI_USER_WIDTH ( AXI_USER_WIDTH )\r\n ) s_data_in_bus ();\r\n AXI_BUS #(\r\n .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ),\r\n .AXI_DATA_WIDTH ( AXI_DATA_OUT_WIDTH),\r\n **.AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ),**\r\n .AXI_USER_WIDTH ( AXI_USER_WIDTH )\r\n ) s_data_out_bus (); \r\n\r\n\r\nHow it should be:\r\nAXI_BUS_ASYNC #(\r\n .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ),\r\n .AXI_DATA_WIDTH ( AXI_DATA_OUT_WIDTH ),\r\n **.AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ),**\r\n .AXI_USER_WIDTH ( AXI_USER_WIDTH ),\r\n .BUFFER_WIDTH ( BUFFER_WIDTH )\r\n ) s_data_master ();\r\n\r\n AXI_BUS_ASYNC #(\r\n .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ),\r\n .AXI_DATA_WIDTH ( AXI_DATA_IN_WIDTH ),\r\n **.AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ),**\r\n .AXI_USER_WIDTH ( AXI_USER_WIDTH ),\r\n .BUFFER_WIDTH ( BUFFER_WIDTH )\r\n ) s_data_slave ();\r\n\r\n AXI_BUS #(\r\n .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ),\r\n .AXI_DATA_WIDTH ( AXI_DATA_IN_WIDTH ),\r\n **.AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ),**\r\n .AXI_USER_WIDTH ( AXI_USER_WIDTH )\r\n ) s_data_in_bus ();\r\n\r\n\r\n AXI_BUS #(\r\n .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ),\r\n .AXI_DATA_WIDTH ( AXI_DATA_OUT_WIDTH),\r\n **.AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ),**\r\n .AXI_USER_WIDTH ( AXI_USER_WIDTH )\r\n ) s_data_out_bus ();\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_pulp_soc_pr23", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_pulp_soc_pr23.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_pulp_soc_pr23", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_pulp_soc_pr23"} +{"instance_id": "pulp-platform_neureka_pr30", "issue_text": "# Depthwise mode is broken from 5a4d22f\n\n- Source URL: https://github.com/pulp-platform/neureka/issues/29\n\nDepthwise mode is broken from commit [5a4d22f](https://github.com/pulp-platform/neureka/commit/5a4d22fb7d1c7fde2d8638c5f64eabd24b7a17dc). The working depthwise version is [1ab44a9](https://github.com/pulp-platform/neureka/commit/1ab44a980e3340755798edd39409665e19c432fe)\n\nPR Title: Fix depthwise\n\nPR #30 (Merged March 26, 2025 by arpansur)\n\nDescription:\nThis PR addresses issue #29 (depthwise mode is broken). The changes include:\n- Fixes bugs from commits 5a4d22f and fcfd25d (the latter is temporarily reverted for later inspection)\n- Introduces depthwise tests in the CI\n\nCommits (titles only):\n1. \"Add DW tests to basic regression\"\n2. \"Fix depthwise issues in accumulator_normquant\"\n3. \"Revert 'Reactivate also binconv gating!' to fix depthwise execution\"\n\nComments:\n\nLuigiGhionda (Author, Mar 10):\nThis PR fixes issue #29 regarding broken depthwise mode functionality and adds CI tests.\n\narpansur (Collaborator, Review):\nSuggested \"adding partial utilised channels instead of only a factor of 32\" and \"tests stressing QW<8\" bitwidth variations.\n\narpansur (Response):\nRecommended expanding test coverage across dimensions like K_IN, K_OUT, H_IN, W_IN, and QW for partial tile utilization.\n\nFrancescoConti (Member, Review):\nApproved with comment \"LGTM except for an unexplained constant\" regarding the 32'h0F constant.\n\nFrancescoConti (Clarification):\nRecommended \"keeping this one dedicated to depthwise\" rather than adding broader test variations in the same PR.\n\nFrancescoConti (Final):\n\"OK, let's merge it then!\"\n\nLinked Issue:\nIssue #29: \"Depthwise mode is broken from 5a4d22f\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_neureka_pr30", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_neureka_pr30.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_neureka_pr30", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/pulp-platform_neureka_pr30"} +{"instance_id": "pulp-platform_pulp_soc_pr23", "issue_text": "# AXI_ID_WIDTH wrong parameters\n\nSome fixes are needed for synthesis.\r\nThere are wrong parameters when instantiating AXI bus to communicate with the cluster.\r\n\r\nCurrent version:\r\n\r\nAXI_BUS_ASYNC #(\r\n .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ),\r\n .AXI_DATA_WIDTH ( AXI_DATA_OUT_WIDTH ),\r\n **.AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ),**\r\n .AXI_USER_WIDTH ( AXI_USER_WIDTH ),\r\n .BUFFER_WIDTH ( BUFFER_WIDTH )\r\n ) s_data_master ();\r\n AXI_BUS_ASYNC #(\r\n .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ),\r\n .AXI_DATA_WIDTH ( AXI_DATA_IN_WIDTH ),\r\n **.AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ),**\r\n .AXI_USER_WIDTH ( AXI_USER_WIDTH ),\r\n .BUFFER_WIDTH ( BUFFER_WIDTH )\r\n ) s_data_slave ();\r\n\r\n AXI_BUS #(\r\n .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ),\r\n .AXI_DATA_WIDTH ( AXI_DATA_IN_WIDTH ),\r\n **.AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ),**\r\n .AXI_USER_WIDTH ( AXI_USER_WIDTH )\r\n ) s_data_in_bus ();\r\n AXI_BUS #(\r\n .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ),\r\n .AXI_DATA_WIDTH ( AXI_DATA_OUT_WIDTH),\r\n **.AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ),**\r\n .AXI_USER_WIDTH ( AXI_USER_WIDTH )\r\n ) s_data_out_bus (); \r\n\r\n\r\nHow it should be:\r\nAXI_BUS_ASYNC #(\r\n .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ),\r\n .AXI_DATA_WIDTH ( AXI_DATA_OUT_WIDTH ),\r\n **.AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ),**\r\n .AXI_USER_WIDTH ( AXI_USER_WIDTH ),\r\n .BUFFER_WIDTH ( BUFFER_WIDTH )\r\n ) s_data_master ();\r\n\r\n AXI_BUS_ASYNC #(\r\n .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ),\r\n .AXI_DATA_WIDTH ( AXI_DATA_IN_WIDTH ),\r\n **.AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ),**\r\n .AXI_USER_WIDTH ( AXI_USER_WIDTH ),\r\n .BUFFER_WIDTH ( BUFFER_WIDTH )\r\n ) s_data_slave ();\r\n\r\n AXI_BUS #(\r\n .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ),\r\n .AXI_DATA_WIDTH ( AXI_DATA_IN_WIDTH ),\r\n **.AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ),**\r\n .AXI_USER_WIDTH ( AXI_USER_WIDTH )\r\n ) s_data_in_bus ();\r\n\r\n\r\n AXI_BUS #(\r\n .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ),\r\n .AXI_DATA_WIDTH ( AXI_DATA_OUT_WIDTH),\r\n **.AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ),**\r\n .AXI_USER_WIDTH ( AXI_USER_WIDTH )\r\n ) s_data_out_bus ();\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_pulp_soc_pr23", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_pulp_soc_pr23.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_pulp_soc_pr23", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/pulp-platform_pulp_soc_pr23"} {"instance_id": "pulp-platform_pulp_soc_pr41", "issue_text": "# Interleaved Memory space only partially accessible\n\nIn l2_ram_multibank.sv the wrong bits are selected for the interleaved memory banks. Currently, only the 2 LSBs are striped which converts from byte addressing to 32-bit word addressing. However, for the interleaved memory banks, we also have to remove $clog2(Nr_of_banks) bits that index the bank due to the interleaved address space mapping. The effect of not doing this is that we start to alias as soon as we try to write more than 128KB into L2 memory.\n\nPR Title: Fixes #40\n\nPR #41 (Merged Jan 7, 2021)\n\nDescription:\nThe PR addresses a bug in interleaved memory bank address extraction. The issue involved improper handling of address bits when accessing the 32-bit TCDM (Tightly Coupled Data Memory). According to the submitter, \"For the interleaved memory space, we have to remove the 2 LSBs since the SRAMs are 32-bit word aligned while TCDM uses byte addressing. However, in addition to that, we also have to remove $clog2(Nr_banks) additional LSBs since those bits are used to select the memory bank in interleaved addressing.\"\n\nComments:\n\nbluewww (Approver):\n\"Passes CI and fixes camera test regressions\"\n\nLinked Issue:\nIssue #40: \"Interleaved Memory space only partially accessible\"\n\nParticipants:\n- meggiman (Author)\n- bluewww (Reviewer/Merger)\n\nThe PR was successfully merged with one commit.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_pulp_soc_pr41", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_pulp_soc_pr41.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_pulp_soc_pr41", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_pulp_soc_pr41"} {"instance_id": "pulp-platform_pulp_soc_pr54", "issue_text": "# Unconnected input port `lint_r_aux_i` of `adbg_lintonly_top`\n\nIn `lint_jtag_wrap.sv` there's an unconnected input port [`lint_r_aux_i`](https://github.com/pulp-platform/pulp_soc/blob/master/rtl/pulp_soc/lint_jtag_wrap.sv#L63) of module `dbg_module_i`.\n\nPR Title: Add r_opc signal to tcdm_arbiter_2x1\n\nPR #54 (Merged on February 10, 2021)\n\nDescription:\nThe PR addressed missing signal connectivity and unconnected input ports in the TCDM arbiter component. It consisted of three commits:\n\n1. \"Add r_opc signal to tcdm_arbiter_2x1\" — Added the missing r_opc signal.\n2. \"Fix warning in Questasim\" — \"Due to the missing default statement, questasim issues a warning that no condition is true for the unique case statement\"\n3. \"Tie unused input port to 0\" — Connected an unused input port.\n\nRelated Issues:\n- Issue #51: \"Missing signal of tcdm bus in tcdm_arbiter_2x1.sv\"\n- Issue #50: \"Unconnected input port `lint_r_aux_i` of `adbg_lintonly_top`\"\n\nReview & Merge:\n- Author: meggiman (Contributor)\n- Reviewer: bluewww (Collaborator) — Approved with \"lgtm\" comment\n- Merged by: meggiman\n- 3 commits included in the merge\n\nThe pull request resolved both linked issues through hardware design fixes and simulation warning resolutions.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_pulp_soc_pr54", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_pulp_soc_pr54.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_pulp_soc_pr54", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_pulp_soc_pr54"} {"instance_id": "pulp-platform_pulp_soc_pr69", "issue_text": "# Replace generic srams with new tc_sram modules\n\nthis change would allows us to use xilinx parametrized macros for the FPGA port instead of separately synthesizing xilinx block memory IPs\n\nPR Title: Remove explicit fpga RAM instantiation\n\nPR #69 (Merged by bluewww on June 25, 2021)\n\nDescription:\nThe change eliminates the need for out-of-context synthesis of Xilinx SRAM IPs in FPGA ports. Instead, the `tech_cells_generic` `tc_sram` wrapper now handles Xilinx parametrized macro instantiation when bender/IPapprox targets are properly configured. This approach eliminates manual synchronization requirements between RTL and FPGA TCL scripts regarding SRAM memory sizes.\n\nParticipants & Activity:\n- Author: meggiman\n- Reviewer/Merger: bluewww (approved and merged the single commit)\n- Branch: fpga_ram_improvement -> master\n\nLinked Issue:\nIssue #55: \"Replace generic srams with new tc_sram modules\" (closed by this PR)\n\nThe PR contains one force-pushed commit and received approval before merging. The feature branch was deleted following the merge.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_pulp_soc_pr69", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_pulp_soc_pr69.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_pulp_soc_pr69", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_pulp_soc_pr69"} @@ -434,7 +434,7 @@ {"instance_id": "pulp-platform_register_interface_pr26", "issue_text": "# Add interface variants to reggen\n\nInstance: pulp-platform_register_interface_pr26\nSource: https://github.com/pulp-platform/register_interface/pull/26\nFetched: 2026-04-26\nRepository: pulp-platform/register_interface\nPull request: #26\nAuthor: meggiman\nState: closed\nBase branch: master\nHead branch: add_interface_variant_to_reggen\nCreated: 2022-12-13T10:05:28Z\nUpdated: 2022-12-13T10:06:27Z\nClosed: 2022-12-13T10:06:22Z\nMerged: 2022-12-13T10:06:22Z\n\nPR Title: Add interface variants to reggen\n\nPR #26 (Merged on December 13, 2022)\n\nAuthor: meggiman\n\nDescription:\nNo description provided.\n\nCommits (titles only):\n1. \"Add interface variant of apb_to_reg converter\"\n2. \"Generate regfiles with interface variant and add missing signal type specifier for clock and reset\"\n\nComments:\nThe author posted only: \"No description provided.\"\n\nReviewers: None\nAssignees: None\nLabels: None\n\nLinked Issues: None explicitly linked.\n\nNotes:\nThis merged pull request introduced interface variants to the reggen component within the register_interface repository, specifically adding an interface variant of the apb_to_reg converter and updating register file generation with proper signal type specifications.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_register_interface_pr26", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_register_interface_pr26.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_register_interface_pr26", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_register_interface_pr26"} {"instance_id": "pulp-platform_register_interface_pr30", "issue_text": "# apb_to_reg: Add option to properly latch forward path\n\nInstance: pulp-platform_register_interface_pr30\nSource: https://github.com/pulp-platform/register_interface/pull/30\nFetched: 2026-04-26\nRepository: pulp-platform/register_interface\nPull request: #30\nAuthor: bluewww\nState: closed\nBase branch: master\nHead branch: apb-latch\nCreated: 2023-04-11T20:35:57Z\nUpdated: 2023-04-28T08:16:15Z\nClosed: 2023-04-28T08:00:44Z\nMerged: 2023-04-28T08:00:44Z\n\nAPB sel is meant to help you latch the addr, wdata and write. Feeding these signals through means basically repurposing apb to work like register interface.\r\n\r\nAdd option to allow you to do the request APB style with latching. Since there a bunch of quite broken APB masters out there which will break with this change we keep it in feedthrough mode by default.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_register_interface_pr30", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_register_interface_pr30.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_register_interface_pr30", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_register_interface_pr30"} {"instance_id": "pulp-platform_register_interface_pr31", "issue_text": "# Split `reg_cdc` into `reg_cdc_src` and `reg_cdc_dst`.\n\nInstance: pulp-platform_register_interface_pr31\nSource: https://github.com/pulp-platform/register_interface/pull/31\nFetched: 2026-04-26\nRepository: pulp-platform/register_interface\nPull request: #31\nAuthor: luca-valente\nState: closed\nBase branch: master\nHead branch: lv/split_cdc\nCreated: 2023-04-27T16:57:30Z\nUpdated: 2023-04-28T08:16:06Z\nClosed: 2023-04-28T08:04:10Z\nMerged: 2023-04-28T08:04:10Z\n\nPR Title: Split `reg_cdc` into `reg_cdc_src` and `reg_cdc_dst`\n\nPR #31 (Merged April 28, 2023)\n\nDescription:\nThe contributor provided no written description for this pull request.\n\nComments & Approvals:\n\nluca-valente (Contributor):\nInitiated the PR on April 27, 2023, requesting reviews from meggiman and micprog.\n\nmicprog (Member):\nApproved with comment: \"LGTM\"\n\nmeggiman (Contributor):\nApproved with comment: \"LGTM Thanks\" and subsequently merged the changes into the master branch.\n\nKey Details:\n- Commits: 1 commit\n- Merged by: meggiman on April 28, 2023\n- Branch deleted: lv/split_cdc was removed after merging\n\nNo linked issues or additional context were provided.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_register_interface_pr31", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_register_interface_pr31.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_register_interface_pr31", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_register_interface_pr31"} -{"instance_id": "pulp-platform_register_interface_pr32", "issue_text": "# Add `reg_filter_empty_writes`\n\nInstance: pulp-platform_register_interface_pr32\nSource: https://github.com/pulp-platform/register_interface/pull/32\nFetched: 2026-04-26\nRepository: pulp-platform/register_interface\nPull request: #32\nAuthor: micprog\nState: closed\nBase branch: master\nHead branch: empty_write_filter\nCreated: 2023-04-27T18:04:37Z\nUpdated: 2023-04-28T08:15:54Z\nClosed: 2023-04-28T08:15:49Z\nMerged: 2023-04-28T08:15:49Z\n\nPR Title: Add `reg_filter_empty_writes`\n\nPR #32 (Merged Apr 28, 2023)\n\nDescription:\nThe PR adds a new module that \"Returns a ready without forwarding the valid for writes with strb='0.\"\n\nComments:\n\nmicprog (Author):\nExplained the use case: Data width downsizers like AXI may issue writes with empty strobes connected to proper writes. The regtool-generated register file doesn't handle this scenario well, prompting this addition.\n\nmeggiman (Reviewer):\nInitially questioned which IPs would issue empty write strobes, noting the addition doesn't affect other IPs. After receiving clarification about the AXI downsizer scenario, meggiman approved with: \"Fair enough. In that case, I have no objection.\"\n\nbluewww (Reviewer):\nApproved with a thumbs-up reaction, reportedly encountering this issue per micprog's comments.\n\nMetadata:\n- Repository: pulp-platform/register_interface\n- Branch: empty_write_filter -> master\n- Participants: micprog, meggiman, bluewww\n- Commits: 1\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_register_interface_pr32", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_register_interface_pr32.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_register_interface_pr32", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_register_interface_pr32"} +{"instance_id": "pulp-platform_register_interface_pr32", "issue_text": "# Add `reg_filter_empty_writes`\n\nInstance: pulp-platform_register_interface_pr32\nSource: https://github.com/pulp-platform/register_interface/pull/32\nFetched: 2026-04-26\nRepository: pulp-platform/register_interface\nPull request: #32\nAuthor: micprog\nState: closed\nBase branch: master\nHead branch: empty_write_filter\nCreated: 2023-04-27T18:04:37Z\nUpdated: 2023-04-28T08:15:54Z\nClosed: 2023-04-28T08:15:49Z\nMerged: 2023-04-28T08:15:49Z\n\nPR Title: Add `reg_filter_empty_writes`\n\nPR #32 (Merged Apr 28, 2023)\n\nDescription:\nThe PR adds a new module that \"Returns a ready without forwarding the valid for writes with strb='0.\"\n\nComments:\n\nmicprog (Author):\nExplained the use case: Data width downsizers like AXI may issue writes with empty strobes connected to proper writes. The regtool-generated register file doesn't handle this scenario well, prompting this addition.\n\nmeggiman (Reviewer):\nInitially questioned which IPs would issue empty write strobes, noting the addition doesn't affect other IPs. After receiving clarification about the AXI downsizer scenario, meggiman approved with: \"Fair enough. In that case, I have no objection.\"\n\nbluewww (Reviewer):\nApproved with a thumbs-up reaction, reportedly encountering this issue per micprog's comments.\n\nMetadata:\n- Repository: pulp-platform/register_interface\n- Branch: empty_write_filter -> master\n- Participants: micprog, meggiman, bluewww\n- Commits: 1\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_register_interface_pr32", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/main/patches/pulp-platform_register_interface_pr32.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_register_interface_pr32", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/pulp-platform_register_interface_pr32"} {"instance_id": "pulp-platform_register_interface_pr33", "issue_text": "# Fix typo in `reg_filter_empty_writes`\n\nInstance: pulp-platform_register_interface_pr33\nSource: https://github.com/pulp-platform/register_interface/pull/33\nFetched: 2026-04-26\nRepository: pulp-platform/register_interface\nPull request: #33\nAuthor: micprog\nState: closed\nBase branch: master\nHead branch: fix_empty_write\nCreated: 2023-04-28T15:33:07Z\nUpdated: 2023-04-28T15:34:43Z\nClosed: 2023-04-28T15:34:40Z\nMerged: 2023-04-28T15:34:40Z\n\nPR title: Fix typo in `reg_filter_empty_writes`\n\nPR description:\nNo description was provided by the pull request author.\n\nComments:\n- micprog (Apr 28, 2023): No substantive comment provided.\n- meggiman (Apr 28, 2023): Approved the changes and subsequently merged the pull request.\n\nLinked issues: None.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_register_interface_pr33", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_register_interface_pr33.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_register_interface_pr33", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_register_interface_pr33"} {"instance_id": "pulp-platform_register_interface_pr34", "issue_text": "# reg_filter_empty_write: Fix internal signal names\n\nInstance: pulp-platform_register_interface_pr34\nSource: https://github.com/pulp-platform/register_interface/pull/34\nFetched: 2026-04-26\nRepository: pulp-platform/register_interface\nPull request: #34\nAuthor: micprog\nState: closed\nBase branch: master\nHead branch: fix_empty_write\nCreated: 2023-05-02T08:14:05Z\nUpdated: 2023-05-05T13:05:40Z\nClosed: 2023-05-05T13:05:37Z\nMerged: 2023-05-05T13:05:36Z\n\nPR title: reg_filter_empty_write: Fix internal signal names\n\nPR description:\nNo explicit full description was provided. The PR body posted by the author at submission was:\n\"Now properly tested: https://github.com/pulp-platform/cheshire/tree/reg_filter\nSorry for the hasty, untested inclusion previously.\"\n\nComments:\n- micprog (May 2, 2023): \"Now properly tested: https://github.com/pulp-platform/cheshire/tree/reg_filter. Sorry for the hasty, untested inclusion previously.\"\n- meggiman (May 5, 2023): \"thanks for the fix\"\n\nReview and merge:\n- Reviewer: meggiman (approved May 5, 2023)\n- Merge commit: 47d2d83\n\nLinked issues: None.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_register_interface_pr34", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_register_interface_pr34.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_register_interface_pr34", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_register_interface_pr34"} {"instance_id": "pulp-platform_register_interface_pr35", "issue_text": "# Add minimal CI compiling files with internal tools\n\nInstance: pulp-platform_register_interface_pr35\nSource: https://github.com/pulp-platform/register_interface/pull/35\nFetched: 2026-04-26\nRepository: pulp-platform/register_interface\nPull request: #35\nAuthor: micprog\nState: closed\nBase branch: master\nHead branch: ci-tests\nCreated: 2023-05-03T09:58:50Z\nUpdated: 2026-02-14T23:13:34Z\nClosed: 2023-05-05T13:07:13Z\nMerged: 2023-05-05T13:07:13Z\n\nPR title: Add minimal CI compiling files with internal tools\n\nPR description:\nNo description provided.\n\nComments:\n- micprog (May 3, 2023): Opened the PR with no description.\n- meggiman (May 5, 2023): \"That's a very sensible addition. Thanks a lot!\"\n\nReview and merge:\n- Author: micprog\n- Reviewer/Merger: meggiman\n- Branch: ci-tests -> master\n\nLinked issues: None mentioned.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_register_interface_pr35", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_register_interface_pr35.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_register_interface_pr35", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_register_interface_pr35"} @@ -446,7 +446,7 @@ {"instance_id": "pulp-platform_register_interface_pr48", "issue_text": "# reg_to_axi: Add module\n\nInstance: pulp-platform_register_interface_pr48\nSource: https://github.com/pulp-platform/register_interface/pull/48\nFetched: 2026-04-26\nRepository: pulp-platform/register_interface\nPull request: #48\nAuthor: paulsc96\nState: closed\nBase branch: master\nHead branch: paulsc/reg_to_axi\nCreated: 2024-03-14T20:17:47Z\nUpdated: 2026-02-14T23:08:42Z\nClosed: 2024-03-14T22:06:52Z\nMerged: 2024-03-14T22:06:52Z\n\nPR title: reg_to_axi: Add module\n\nPR description:\n\"See pulp-platform/axi#335.\"\n\nActivity timeline:\n- March 14, 2024 20:22: Force-pushed branch with commit updates.\n- March 14, 2024 20:36: Marked PR as ready for review.\n- March 14, 2024 20:38: Additional force-push with refinements.\n- March 14, 2024 20:40: Final force-push before merge.\n- March 14, 2024: Merged into master branch via commit aa19b25.\n- February 14, 2026: Branch deleted post-merge.\n\nReviewers: None listed. Assignees: None. Labels: None.\n\nLinked references:\n- pulp-platform/axi#335 (external related pull request).\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_register_interface_pr48", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_register_interface_pr48.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_register_interface_pr48", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_register_interface_pr48"} {"instance_id": "pulp-platform_register_interface_pr54", "issue_text": "# reg_to_axi: fix axi error detection\n\nInstance: pulp-platform_register_interface_pr54\nSource: https://github.com/pulp-platform/register_interface/pull/54\nFetched: 2026-04-26\nRepository: pulp-platform/register_interface\nPull request: #54\nAuthor: TheMightyDuckOfDoom\nState: closed\nBase branch: master\nHead branch: fix-reg2axi\nCreated: 2025-07-29T14:12:32Z\nUpdated: 2025-08-04T20:31:57Z\nClosed: 2025-08-04T20:31:57Z\nMerged: 2025-08-04T20:31:57Z\n\nCurrently, we raise the error bit if we get a \"RESP_OKAY\".\r\nI think we have an error if we get something else than \"RESP_OKAY\".\r\n\r\nThis commit fixes this problem.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_register_interface_pr54", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_register_interface_pr54.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_register_interface_pr54", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_register_interface_pr54"} {"instance_id": "pulp-platform_register_interface_pr55", "issue_text": "# apb_to_reg: Replace modport with struct in default converter\n\nInstance: pulp-platform_register_interface_pr55\nSource: https://github.com/pulp-platform/register_interface/pull/55\nFetched: 2026-04-26\nRepository: pulp-platform/register_interface\nPull request: #55\nAuthor: phsauter\nState: closed\nBase branch: master\nHead branch: phsauter/apb_to_reg_v2\nCreated: 2025-10-14T15:24:42Z\nUpdated: 2026-02-14T23:13:32Z\nClosed: 2025-11-20T17:25:40Z\nMerged: 2025-11-20T17:25:40Z\n\nIt is awkward to not have a converter without interfaces and leads to odd code choices elsewhere (eg https://github.com/pulp-platform/clic/blob/master/src/clic_apb.sv#L59).\r\n\r\nThis PR deprecated apb_to_reg and replaces it with apb_to_reg_v2. Note that the interface only version (apt_to_reg_intf) is not changed and moved to apv_to_reg_v2.sv since this one should not be deprecated.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_register_interface_pr55", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_register_interface_pr55.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_register_interface_pr55", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_register_interface_pr55"} -{"instance_id": "pulp-platform_riscv-dbg_pr123", "issue_text": "Besides the additional Xilinx BSCANE2 related features, commit b5d1610 introduced some new logic to allow the dmi_jtag module to be reset with TMS cycling by entering the \"TestLogicReset\" state. However, the way this is implemented in dmi_jtag_tap.sv line 205 is extremely dangerous; the generated trst_no signal is prone to glitching and actually drives asynchronous resets within dmi_jtag.sv and dmi_cdc.sv\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nPR title: Functional Resets and Async Reset Glitch Prevention\n\nSource: https://github.com/pulp-platform/riscv-dbg/pull/123\n\nPR description:\nThis PR addresses issue #120 and introduces support for `dtmcs.dmihardreset`. The key changes separate asynchronous JTAG reset (controlled by `jtag_trst` signal) from synchronous functional resets triggered by JTAG TestLogicReset state or DTM reset CSR. The implementation uses new clearable CDC modules that synchronize clear requests across clock domains.\n\nThe author modified the DMI testbench to issue random resets during transactions and fixed a JTAG verification IP bug where `ir_select` wasn't reset during master reset.\n\nComments:\n- meggiman (author): Explained that `dmi_rst_no` clears the DMI response FIFO within `dm_top`. To maintain backward compatibility while avoiding mixing functional and power-on-reset semantics, the signal was made glitch-free and derived from the synchronized clearable CDC output. Additional fixes addressed JTAG specification compliance regarding IR reset to IDCODE in TestLogicReset.\n- andreaskurth (reviewer): Approved with suggestions for changelog corrections and variable naming consistency (`core_dmi_rst_nq` to reflect active-low polarity).\n- bluewww (collaborator): Approved with comment \"lgtm\" and previously suggested adding synchronous clear functionality to `dm_top`.\n\nLinked issue:\n- #120 \"Fatal Glitching in Internal Asynchronous Reset Generation\"\n\nStatus: Merged by bluewww on April 4, 2022.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_riscv-dbg_pr123", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_riscv-dbg_pr123.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_riscv-dbg_pr123", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_riscv-dbg_pr123"} +{"instance_id": "pulp-platform_riscv-dbg_pr123", "issue_text": "Besides the additional Xilinx BSCANE2 related features, commit b5d1610 introduced some new logic to allow the dmi_jtag module to be reset with TMS cycling by entering the \"TestLogicReset\" state. However, the way this is implemented in dmi_jtag_tap.sv line 205 is extremely dangerous; the generated trst_no signal is prone to glitching and actually drives asynchronous resets within dmi_jtag.sv and dmi_cdc.sv\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nPR title: Functional Resets and Async Reset Glitch Prevention\n\nSource: https://github.com/pulp-platform/riscv-dbg/pull/123\n\nPR description:\nThis PR addresses issue #120 and introduces support for `dtmcs.dmihardreset`. The key changes separate asynchronous JTAG reset (controlled by `jtag_trst` signal) from synchronous functional resets triggered by JTAG TestLogicReset state or DTM reset CSR. The implementation uses new clearable CDC modules that synchronize clear requests across clock domains.\n\nThe author modified the DMI testbench to issue random resets during transactions and fixed a JTAG verification IP bug where `ir_select` wasn't reset during master reset.\n\nComments:\n- meggiman (author): Explained that `dmi_rst_no` clears the DMI response FIFO within `dm_top`. To maintain backward compatibility while avoiding mixing functional and power-on-reset semantics, the signal was made glitch-free and derived from the synchronized clearable CDC output. Additional fixes addressed JTAG specification compliance regarding IR reset to IDCODE in TestLogicReset.\n- andreaskurth (reviewer): Approved with suggestions for changelog corrections and variable naming consistency (`core_dmi_rst_nq` to reflect active-low polarity).\n- bluewww (collaborator): Approved with comment \"lgtm\" and previously suggested adding synchronous clear functionality to `dm_top`.\n\nLinked issue:\n- #120 \"Fatal Glitching in Internal Asynchronous Reset Generation\"\n\nStatus: Merged by bluewww on April 4, 2022.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_riscv-dbg_pr123", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/main/patches/pulp-platform_riscv-dbg_pr123.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_riscv-dbg_pr123", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/pulp-platform_riscv-dbg_pr123"} {"instance_id": "pulp-platform_riscv-dbg_pr145", "issue_text": "# [dm_mem] Addressing does not take strobes into account\n\nThe read/write logic in dm_mem.sv only looks at the request address and does not take the byte strobes into account which causes problems when trying to write the Halted, Going, Resuming and Exception locations from a bus that is larger than 32 bit as that would require misaligned requests.\n\nThis is patched in #145 by realigning the relevant addresses to 64 bits.\n\n\n\n\n\n\n\n\n\n\n\nPR title: [fix] Realign addresses to 64-bit\n\nSource: https://github.com/pulp-platform/riscv-dbg/pull/145\n\nPR description:\nThe PR addresses a critical issue where the read/write logic in `dm_mem.sv` only examines the request address without considering byte strobes. This limitation causes problems when writing to Halted, Going, Resuming, and Exception locations from buses larger than 32-bit, as such operations would require misaligned requests. The fix realigns these addresses to 64 bits, enabling the Debug Module to work properly with both 32-bit and 64-bit harts.\n\nComments:\n- creinwar (Nov 1, 2022): The contributor explained the root cause and solution, linking to issue #144.\n- bluewww (Nov 2, 2022): \"I'll double check otherwise looks good. Could you also please update the documentation?\"\n- bluewww (Nov 2, 2022): Approved with comment: \"lgtm\"\n\nLinked issue:\n- #144 \"[dm_mem] Addressing does not take strobes into account\"\n\nMerge info:\n- Merged by: bluewww\n- Commits: 2 total\n- Branch deleted after merge\n- Merged Nov 2, 2022.\n\nDownstream impact: This change affected address mappings in related projects. The Exception Address was changed from `0x808` to `0x810`, which required follow-up fixes in dependent systems like the Cheshire project.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_riscv-dbg_pr145", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_riscv-dbg_pr145.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_riscv-dbg_pr145", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_riscv-dbg_pr145"} {"instance_id": "pulp-platform_riscv-dbg_pr155", "issue_text": "# `sberror` not clearing properly causes OpenOCD interoperability issues\n\nThe OpenTitan project uses GDB/OpenOCD to develop top-level debug and manufacturing test cases. We have noticed some test failures when performing unaligned system bus accesses (see [here](https://github.com/lowRISC/opentitan/issues/17729#issuecomment-1488923308)).\n\nIn short, when an unaligned read operation is performed, `sberror` is set to 3 (which is correct according to the spec), but after, OpenOCD tries to clear the error with a W1C, by sending 0x7, however, the `sberror` field fails to clear. We believe there is an RTL bug described [here](https://github.com/lowRISC/opentitan/issues/17729#issuecomment-1489076212).\n\nCould someone confirm / fix?\n\n\n\n\n\n\n\n\n\nPR title: dm_csrs: Fix W1C behavior of `sberror`\n\nSource: https://github.com/pulp-platform/riscv-dbg/pull/155\n\nPR description:\n\"Prior to this PR, the W1C `sberror` field of the `sbcs` CSR only got cleared when `3b'001` was written to it. When other values, e.g., `3b111`, were written, the field did not get cleared. This is a mismatch to the RISC-V External Debug Support spec, which states 'Writing 1 to every bit clears the field'.\n\nThis PR fixes that mismatch in a backwards-compatible way, i.e., now any non-zero write to `sberror`, including `3'b001`, clears it. See issue #154 for further information and discussion.\n\nThis resolves #154.\n\nThis has been tested in OpenTitan with OpenOCD connected to this debug module instantiated on an FPGA to confirm that this solves the problem described in lowRISC/opentitan#17729.\"\n\nComments:\n- timothytrippel (Mar 31, 2023): \"Thanks @andreaskurth !\"\n- bluewww (Apr 5, 2023): \"I ran the tests locally everything seems to be in order. lgtm.\"\n\nLinked issue:\n- #154 \"`sberror` not clearing properly causes OpenOCD interoperability issues\"\n\nStatus: Merged on April 5, 2023 by bluewww.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_riscv-dbg_pr155", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_riscv-dbg_pr155.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_riscv-dbg_pr155", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_riscv-dbg_pr155"} {"instance_id": "pulp-platform_riscv-dbg_pr169", "issue_text": "# Reset state after trst_ni is wrong\n\nThis\n\nhttps://github.com/pulp-platform/riscv-dbg/blob/358f90110220adf7a083f8b65d157e836d706236/src/dmi_jtag_tap.sv#L306\n\nshould reset the TAP to the `Test-Logic-Reset` state.\n\nSee `4.6.1 Specifications` in `IEEE Standard for Test Access Port and Boundary-Scan Architecture 11491-2013`. @msfschaffner does that sound correct to you too?\n\n\n\n\n\n\n\nPR title: src: Fix wrong reset state for TAP after trst_ni\n\nSource: https://github.com/pulp-platform/riscv-dbg/pull/169\n\nPR description:\nThe PR addresses a bug where the TAP (Test Access Port) reset state was incorrect after `trst_ni` assertion. According to the author: \"This problem was didn't become visible as most/all drivers always run the software reset sequence as trst_ni is an optional signal.\"\n\nLinked issue:\n- #165 \"Reset state after trst_ni is wrong\"\n\nActivity:\nThe fix was subsequently applied upstream by Andreas Kurth in the OpenTitan project (July 15, 2024), which also reverted two related commits that had replicated the same problem in their DV (design verification) code.\n\nKey details:\n- Author: bluewww\n- Status: Merged\n- Merge date: July 8, 2024\n- Commits: 1 commit merged\n- Changes: Corrects the reset value of `tap_state_q`\n- Impact: Fixes edge cases where `trst_ni` is used without software reset sequences\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_riscv-dbg_pr169", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_riscv-dbg_pr169.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_riscv-dbg_pr169", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_riscv-dbg_pr169"} @@ -461,7 +461,7 @@ {"instance_id": "pulp-platform_snitch_pr388", "issue_text": "# SPI Host: FSM Bug CSAAT\n\nThe OpenTitan SPI host FSM contains a bug as it uses the `command_i.segment.csaat` signal instead of the latched `csaat_q` from the command that is currently being executed to decide how the chip select will be handled.\r\n\r\nSee [OpenTitans Fix](https://github.com/lowRISC/opentitan/commit/6c7ce7683b3a1ad82496db7cfd67f174164b6502)\r\n\r\nPatch to rectify the problem:\r\n```diff\r\ndiff --git a/hw/vendor/lowrisc_opentitan/spi_host/rtl/spi_host_fsm.sv b/hw/vendor/lowrisc_opentitan/spi_host/rtl/spi_host_fsm.sv\r\nindex 4fb1360d..e50d0e7e 100644\r\n--- a/hw/vendor/lowrisc_opentitan/spi_host/rtl/spi_host_fsm.sv\r\n+++ b/hw/vendor/lowrisc_opentitan/spi_host/rtl/spi_host_fsm.sv\r\n@@ -250,7 +250,7 @@ module spi_host_fsm\r\n // and of CSAAT is asserted, the details of the subsequent command.\r\n if (!last_bit || !last_byte) begin\r\n prestall_st_d = InternalClkLow;\r\n- end else if (!command_i.segment.csaat) begin\r\n+ end else if (!csaat_q) begin\r\n prestall_st_d = WaitTrail;\r\n end else if (!command_valid_i) begin\r\n prestall_st_d = IdleCSBActive;\r\n```\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_snitch_pr388", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_snitch_pr388.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_snitch_pr388", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_snitch_pr388"} {"instance_id": "pulp-platform_snitch_pr394", "issue_text": "# SPI Host: FSM Bug CSID Switch\n\nThe OpenTitan SPI host FSM contains a bug as it jumps to the WaitIdle state after receiving a command with a different CSID as the previous command. It therefore basically always skips the first command after a CSID change which this patch rectifies ([OpenTitan does it the same way](https://github.com/lowRISC/opentitan/blob/master/hw/ip/spi_host/rtl/spi_host_fsm.sv#L284)).\r\n\r\n```diff\r\ndiff --git a/hw/vendor/lowrisc_opentitan/spi_host/rtl/spi_host_fsm.sv b/hw/vendor/lowrisc_opentitan/spi_host/rtl/spi_host_fsm.sv\r\nindex 4fb1360d..babb6138 100644\r\n--- a/hw/vendor/lowrisc_opentitan/spi_host/rtl/spi_host_fsm.sv\r\n+++ b/hw/vendor/lowrisc_opentitan/spi_host/rtl/spi_host_fsm.sv\r\n@@ -290,7 +290,7 @@ module spi_host_fsm\r\n if (idle_cntr_q == 4'h0) begin\r\n prestall_st_d = WaitLead;\r\n end else begin\r\n- prestall_st_d = WaitIdle;\r\n+ prestall_st_d = CSBSwitch;\r\n end\r\n end\r\n IdleCSBActive: begin\r\n```\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_snitch_pr394", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_snitch_pr394.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_snitch_pr394", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_snitch_pr394"} {"instance_id": "pulp-platform_snitch_pr436", "issue_text": "# Occamy on FPGA - \"axi_flat.svh\" header file is missing on the repo\n\nThank you for your proving us Occamy source code.\r\nI tried to create Occamy FPGA code, based on your Occamy instruction on the repo. \r\n--> make occamy_vcu128\r\n\r\nThe following error message will be reported.\r\n\r\nERROR: [Synth 8-1766] cannot open include file axi_flat.svh [/home/nam/codeSim/project/snitch/hw/system/occamy/src/occamy_xilinx.sv:9]\r\nERROR: [Synth 8-2841] use of undefined macro AXI_FLATTEN_MASTER [/home/nam/codeSim/project/snitch/hw/system/occamy/src/occamy_xilinx.sv:525]\r\n\r\nI think \"occamy_xilinx.sv\" must include \"axi_flat.svh\" header file.\r\nBut, we can't find the header file on the Github repo. \r\nI think uploading of the header file was missed. \r\n\r\nIt would be very grateful to you if you upload \"axi_flat.svh\" header file on this repo.\r\nThank you.\r\n\r\nSeungseok\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_snitch_pr436", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_snitch_pr436.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_snitch_pr436", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_snitch_pr436"} -{"instance_id": "pulp-platform_tech_cells_generic_pr17", "issue_text": "# `tc_sram`: Add implementation key and IO\n\nInstance: pulp-platform_tech_cells_generic_pr17\nSource: https://github.com/pulp-platform/tech_cells_generic/pull/17\nFetched: 2026-04-26\nRepository: pulp-platform/tech_cells_generic\nPull request: #17\nAuthor: paulsc96\nState: closed\nBase branch: master\nHead branch: feature/tc_sram_impl\nCreated: 2021-10-08T14:56:31Z\nUpdated: 2022-10-25T16:30:43Z\nClosed: 2022-10-25T16:30:43Z\nMerged: 2022-10-25T16:30:43Z\n\nThis PR\r\n\r\n* Adds a metadata string parameter `ImplKey` to `tc_sram`, which serves as a key to identify a specific memory type. Together with an external description of the desired implementation for each key (e.g. macro type), this enables generating `tc_sram` implementation wrappers without having to identify memories by their parameters like width and depth.\r\n* Adds a wrapper `tc_sram_impl` around `tc_sram` with parametric implementation IO (`impl_i` and `impl_o`). This allows setting pseudo-static implementation-specific inputs (e.g. macro configuration) or reading implementation-specific outputs (e.g. physical sensor feedback, interrupts). Importantly, the behavioral model ignores `impl_i` and drives `impl_o` with a static, parameterizable value.\r\n\r\nThe addition of `ImplKey` is a first step towards addressing #14.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_tech_cells_generic_pr17", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_tech_cells_generic_pr17.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_tech_cells_generic_pr17", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_tech_cells_generic_pr17"} +{"instance_id": "pulp-platform_tech_cells_generic_pr17", "issue_text": "# `tc_sram`: Add implementation key and IO\n\nInstance: pulp-platform_tech_cells_generic_pr17\nSource: https://github.com/pulp-platform/tech_cells_generic/pull/17\nFetched: 2026-04-26\nRepository: pulp-platform/tech_cells_generic\nPull request: #17\nAuthor: paulsc96\nState: closed\nBase branch: master\nHead branch: feature/tc_sram_impl\nCreated: 2021-10-08T14:56:31Z\nUpdated: 2022-10-25T16:30:43Z\nClosed: 2022-10-25T16:30:43Z\nMerged: 2022-10-25T16:30:43Z\n\nThis PR\r\n\r\n* Adds a metadata string parameter `ImplKey` to `tc_sram`, which serves as a key to identify a specific memory type. Together with an external description of the desired implementation for each key (e.g. macro type), this enables generating `tc_sram` implementation wrappers without having to identify memories by their parameters like width and depth.\r\n* Adds a wrapper `tc_sram_impl` around `tc_sram` with parametric implementation IO (`impl_i` and `impl_o`). This allows setting pseudo-static implementation-specific inputs (e.g. macro configuration) or reading implementation-specific outputs (e.g. physical sensor feedback, interrupts). Importantly, the behavioral model ignores `impl_i` and drives `impl_o` with a static, parameterizable value.\r\n\r\nThe addition of `ImplKey` is a first step towards addressing #14.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_tech_cells_generic_pr17", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_tech_cells_generic_pr17.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_tech_cells_generic_pr17", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/pulp-platform_tech_cells_generic_pr17"} {"instance_id": "pulp-platform_tech_cells_generic_pr22", "issue_text": "# Add optional parameter to tc_clk_gating to flag functional gates\n\nInstance: pulp-platform_tech_cells_generic_pr22\nSource: https://github.com/pulp-platform/tech_cells_generic/pull/22\nFetched: 2026-04-26\nRepository: pulp-platform/tech_cells_generic\nPull request: #22\nAuthor: meggiman\nState: closed\nBase branch: master\nHead branch: functional_clk_gate_flagging\nCreated: 2022-03-17T13:15:38Z\nUpdated: 2022-03-17T13:51:27Z\nClosed: 2022-03-17T13:29:49Z\nMerged: 2022-03-17T13:29:49Z\n\nFor certain target platforms clock gating cells are not available or should be used very sparsingly (e.g. many FPGAs have very limited amounts of global clock buffer cells available for that purposes). For these cases it is important to distinguish between functional clock gates that are required for functional correctness of the design (e.g. in clock dividers or in peripherals) or if the clock gate is only used for hierarchical clock gating for power saving purposes. For clock gating resource limited targets, the later (non-functional clock gates) can be safely replaced with a simple feedthrough without affecting functionality. \r\n\r\nThis PR adds an optional parameter to the tc_clk_gating cell for designer to flag, wether a particular CG instance is functionally required or not. Target specific implementations of the generic tc_clk_gating module might then opt to use dedicated ICGs for functional clock gates while removing the not-strictly required ones.\r\n\r\nThe default value is 1'b1 which means the clock gate is functional. That way the change is backward compatible because by default we assume, that all tc_clk_gating instances in old designs are functionally required unless someone modifies the instantiations to mark them otherwise.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_tech_cells_generic_pr22", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_tech_cells_generic_pr22.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_tech_cells_generic_pr22", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_tech_cells_generic_pr22"} {"instance_id": "pulp-platform_tech_cells_generic_pr26", "issue_text": "# Add IS_FUNCTIONAL parameter to tc_clk_gating in tc_clk_xilinx.sv\n\nInstance: pulp-platform_tech_cells_generic_pr26\nSource: https://github.com/pulp-platform/tech_cells_generic/pull/26\nFetched: 2026-04-26\nRepository: pulp-platform/tech_cells_generic\nPull request: #26\nAuthor: creinwar\nState: closed\nBase branch: master\nHead branch: fix/tc_clk_xilinx_is_functional\nCreated: 2022-11-02T15:48:42Z\nUpdated: 2022-11-03T10:50:38Z\nClosed: 2022-11-02T20:12:37Z\nMerged: 2022-11-02T20:12:37Z\n\nPR title: Add IS_FUNCTIONAL parameter to tc_clk_gating in tc_clk_xilinx.sv\n\nPR description:\nNo description was provided with this pull request.\n\nComments:\n- niwis (Collaborator) - Approval comment: \"Thanks!\"\n\nKey details:\n- Commits: 1 commit (21abc77)\n- Requested reviewer: paulsc96 (awaiting review)\n- Branch: fix/tc_clk_xilinx_is_functional -> master\n- Merge commit: 325ece6\n\nThe pull request was successfully merged despite the requested reviewer not having provided feedback. The contributing branch was deleted after merging on November 3, 2022.\n\nLinked issues: None.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_tech_cells_generic_pr26", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_tech_cells_generic_pr26.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_tech_cells_generic_pr26", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_tech_cells_generic_pr26"} {"instance_id": "pulp-platform_tech_cells_generic_pr27", "issue_text": "# Add tc_clk_or2 And Add Warning About tc_clk_mux2 Usage\n\nInstance: pulp-platform_tech_cells_generic_pr27\nSource: https://github.com/pulp-platform/tech_cells_generic/pull/27\nFetched: 2026-04-26\nRepository: pulp-platform/tech_cells_generic\nPull request: #27\nAuthor: meggiman\nState: closed\nBase branch: master\nHead branch: add_clk_OR2\nCreated: 2022-12-11T11:31:43Z\nUpdated: 2022-12-12T10:26:20Z\nClosed: 2022-12-12T10:26:19Z\nMerged: 2022-12-12T10:26:19Z\n\nPR title: Add tc_clk_or2 And Add Warning About tc_clk_mux2 Usage\n\nPR description:\n\"This PR adds a new generic clock gate cell (OR-gate) to the `tc_clk.sv` cell family. Furthermore, I added a warning about the limitations of the `tc_clk_mux2` cell in common standard cell libraries. They are not glitch-free and must not be used for dynamic switching between two clocks without any additional precautionary steps.\"\n\nComments:\n- meggiman (Author, Dec 11, 2022): Explained that the PR adds a new generic clock gate cell and a cautionary warning about the `tc_clk_mux2` cell's limitations in standard cell libraries.\n- niwis (Reviewer/Maintainer, Dec 12, 2022): Approved with the comment \"Thanks a lot @meggiman, LGTM\" and merged the changes.\n\nCommits:\n- Add clk OR cell (b970419)\n- Add usage warning to clock mux cell (7a0f09d)\n- Update changelog (ef99266)\n\nLinked issues: None.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_tech_cells_generic_pr27", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_tech_cells_generic_pr27.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/pulp-platform_tech_cells_generic_pr27", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_tech_cells_generic_pr27"} @@ -475,33 +475,33 @@ {"instance_id": "squared-studio_common_pr118", "issue_text": "# pll\n\n- Source URL: https://github.com/squared-studio/common/issues/111\n\n\n\n\n\n\n\n\n\n\n\n\n\nPR title: 111 pll\n\nSource: https://github.com/squared-studio/common/pull/118\n\nPR description:\nNo description provided.\n\nComments:\n- foez-ahmed (Contributor) - September 2, 2023: \"_No description provided._\"\n\nCommits (8 total):\nThe PR included 8 commits modifying PLL (Phase-Locked Loop) related files:\n- Modified rtl/model/pll.sv and rtl/pll.sv\n- Added testbench files (pll_tb.sv, wave.gtkw, configuration files)\n- Renamed rtl/model/pll.sv to rtl/pll.sv\n- Final merge commit into main branch\n\nLinked issue:\n- Issue #111 \"pll\" (closed by this PR).\n\nReviewers: None. Assignees: None. Labels: None. Milestone: None.\n\nStatus: Merged September 2, 2023. Author: foez-ahmed. Branch: 111-pll -> main.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/squared-studio_common_pr118", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/squared-studio_common_pr118.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/squared-studio_common_pr118", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/squared-studio_common_pr118"} {"instance_id": "svunit_svunit_pr110", "issue_text": "# Add JUnit XML\n\nInstance: svunit_svunit_pr110\nSource: https://github.com/svunit/svunit/pull/110\nFetched: 2026-05-03\nRepository: svunit/svunit\nPull request: #110\nAuthor: tudortimi\nState: closed\nBase branch: master\nHead branch: add-junit-xml\nCreated: 2021-03-14\nUpdated: 2021-03-14\nClosed: 2021-03-14\nMerged: 2021-03-14\n\n## PR Title\nAdd JUnit XML\n\n## PR Description\nNo description was provided for this pull request. The PR was authored by tudortimi and contained 24 commits implementing JUnit XML report export functionality for SVUnit. Work spanned creating tests that expect XML output, generating XML files after test runs, writing XML elements for testsuites, test suites and test cases, extracting an XmlElement class for element printing, adding failure-element handling, applying a Xcelium indentation workaround, updating documentation in the JUnit model classes, and updating the CHANGELOG.\n\n## PR Comments\nNo conversation comments were captured beyond the merge activity. The PR was merged on March 14, 2021 (merge commit 6266b81) and the add-junit-xml branch was deleted shortly afterwards on the same day.\n\n## Linked Issues\n**Issue #73 - \"Add export of JUnit XML report\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"I remember that we had an issue for this, opened by someone else, but I can't find it.\n\nNow that I started using Jenkins more, I would like to have this as well.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/svunit_svunit_pr110", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/svunit_svunit_pr110.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/svunit_svunit_pr110", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/svunit_svunit_pr110"} {"instance_id": "svunit_svunit_pr113", "issue_text": "# Fix pytests utils\n\nInstance: svunit_svunit_pr113\nSource: https://github.com/svunit/svunit/pull/113\nFetched: 2026-05-03\nRepository: svunit/svunit\nPull request: #113\nAuthor: semihalf-bis-maciej (Maciej Bis)\nState: closed\nBase branch: master\nHead branch: fix-pytest\nCreated: 2021-07-09\nUpdated: 2021-08-16\nClosed: 2021-08-16\nMerged: 2021-08-16\n\n## PR Title\nFix pytests utils\n\n## PR Description\nThe PR addresses the `expect_*` methods in utils.py and how they are used in the test suite. The patch makes the tests raise exceptions on mismatches so that failures are actually caught by pytest. The author also notes that parentheses are special regex characters and need to be escaped in the patterns used by these helpers.\n\nThe PR is associated with issue #99 which observed that `expect_*` functions were merely returning True/False booleans without actually asserting any condition, so tests using them never failed.\n\n## PR Comments\n**semihalf-bis-maciej (Maciej Bis)** (Jul 9, 2021): Initial PR submission. Explains that `expect_*` helpers in utils.py never actually fail tests, and that this patch turns them into asserting helpers. Also notes the regex escaping fix for parentheses. Asks for review.\n\n**tudortimi** (Jul 2021): Identified the connection to issue #99 and requested some changes (e.g., asked the contributor to scope the fix more tightly and to clean up affected tests). Also raised the question of organization access permissions because maintainer edits to the contributor's branch were required.\n\n**semihalf-bis-maciej** (Jul-Aug 2021): Pushed follow-up commits addressing review feedback, disabling some `uvm_report_mock` tests that were broken under UVM 1.2 (out of scope for this PR), fixing the `sim_8` test, and removing an extraneous `.` from a file path used in `expect`.\n\n**tudortimi** (Aug 16, 2021): Approved and merged the PR after a final rebase onto master. 5 commits in total were included.\n\n## Linked Issues\n**Issue #99 - \"Tests that use `expect_*` don't check anything\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"The `expect_*` functions just return `True` or `False`, but they don't check anything.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/svunit_svunit_pr113", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/svunit_svunit_pr113.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/svunit_svunit_pr113", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/svunit_svunit_pr113"} -{"instance_id": "svunit_svunit_pr114", "issue_text": "# Evaluation of unknown values with FAIL_* macros\n\nInstance: svunit_svunit_pr114\nSource: https://github.com/svunit/svunit/pull/114\nFetched: 2026-05-03\nRepository: svunit/svunit\nPull request: #114\nAuthor: semihalf-bis-maciej (Maciej Bis)\nState: closed\nBase branch: master\nHead branch: fail-x\nCreated: 2021-07-09\nUpdated: 2021-07-21\nClosed: 2021-07-21\nMerged: 2021-07-21\n\n## PR Title\nEvaluation of unknown values with FAIL_* macros\n\n## PR Description\nThe PR implements proper handling of unknown ('x'/'z') values in the `FAIL_*` macro family so that comparisons follow SystemVerilog semantics. It addresses request #51 (\"Unexpected == evaluation of unknown values with svunit_testcase::fail()\"), where `==` against unknowns produced unexpected pass/fail outcomes.\n\n## PR Comments\n**semihalf-bis-maciej** (Jul 9, 2021): \"This is implementation of #51 request - evaluation of unknown values in `FAIL_*` macros. Please review.\"\n\n**tudortimi** (Jul 12, 2021): Asked for a CHANGELOG entry. Suggested the `FAIL_*` macros be restructured using `if`-statements for readability rather than the current expression form.\n\n**tudortimi** (Jul 12, 2021): Asked the contributor to rename test files/cases to something more descriptive so they would not collide with names used in other in-flight pull requests.\n\n**semihalf-bis-maciej** (Jul 13, 2021): Agreed to rename the new tests, pushed updated commits.\n\n**tudortimi** (Jul 19, 2021): Clarified the project's CHANGELOG policy - entries are only added for unreleased changes, and version strings get bumped at release time.\n\n**semihalf-bis-maciej** (Jul 20, 2021): Pushed CHANGELOG updates and noted some recent organizational changes around repository management.\n\n**tudortimi** (Jul 21, 2021): Approved and merged the PR, thanking the contributor.\n\n## Linked Issues\n**Issue #51 - \"Unexpected == evaluation of unknown values with svunit_testcase::fail()\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"Since the fail() method takes a two-state argument of type bit for the expression argument, the evaluation for unknown values is inconsistent with pure SystemVerilog code due to the implicit type casting.\n\nThe expression 1'bx == 1'bx evaluates to X and branches to the else clause in the following code.\n\n if(1'bx == 1'bx) $display(\\\"true\\\");\n else $display(\\\"false\\\");\n\nHowever, when the same expression is used in the `FAIL_UNLESS macro it will not generate an error. A proposed fix is to change the b argument of the svunit_testcase::fail() function to a logic type and change the test operation from if(b) to if(b!==0).\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/svunit_svunit_pr114", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/svunit_svunit_pr114.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/svunit_svunit_pr114", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/svunit_svunit_pr114"} +{"instance_id": "svunit_svunit_pr114", "issue_text": "# Evaluation of unknown values with FAIL_* macros\n\nInstance: svunit_svunit_pr114\nSource: https://github.com/svunit/svunit/pull/114\nFetched: 2026-05-03\nRepository: svunit/svunit\nPull request: #114\nAuthor: semihalf-bis-maciej (Maciej Bis)\nState: closed\nBase branch: master\nHead branch: fail-x\nCreated: 2021-07-09\nUpdated: 2021-07-21\nClosed: 2021-07-21\nMerged: 2021-07-21\n\n## PR Title\nEvaluation of unknown values with FAIL_* macros\n\n## PR Description\nThe PR implements proper handling of unknown ('x'/'z') values in the `FAIL_*` macro family so that comparisons follow SystemVerilog semantics. It addresses request #51 (\"Unexpected == evaluation of unknown values with svunit_testcase::fail()\"), where `==` against unknowns produced unexpected pass/fail outcomes.\n\n## PR Comments\n**semihalf-bis-maciej** (Jul 9, 2021): \"This is implementation of #51 request - evaluation of unknown values in `FAIL_*` macros. Please review.\"\n\n**tudortimi** (Jul 12, 2021): Asked for a CHANGELOG entry. Suggested the `FAIL_*` macros be restructured using `if`-statements for readability rather than the current expression form.\n\n**tudortimi** (Jul 12, 2021): Asked the contributor to rename test files/cases to something more descriptive so they would not collide with names used in other in-flight pull requests.\n\n**semihalf-bis-maciej** (Jul 13, 2021): Agreed to rename the new tests, pushed updated commits.\n\n**tudortimi** (Jul 19, 2021): Clarified the project's CHANGELOG policy - entries are only added for unreleased changes, and version strings get bumped at release time.\n\n**semihalf-bis-maciej** (Jul 20, 2021): Pushed CHANGELOG updates and noted some recent organizational changes around repository management.\n\n**tudortimi** (Jul 21, 2021): Approved and merged the PR, thanking the contributor.\n\n## Linked Issues\n**Issue #51 - \"Unexpected == evaluation of unknown values with svunit_testcase::fail()\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"Since the fail() method takes a two-state argument of type bit for the expression argument, the evaluation for unknown values is inconsistent with pure SystemVerilog code due to the implicit type casting.\n\nThe expression 1'bx == 1'bx evaluates to X and branches to the else clause in the following code.\n\n if(1'bx == 1'bx) $display(\\\"true\\\");\n else $display(\\\"false\\\");\n\nHowever, when the same expression is used in the `FAIL_UNLESS macro it will not generate an error. A proposed fix is to change the b argument of the svunit_testcase::fail() function to a logic type and change the test operation from if(b) to if(b!==0).\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/svunit_svunit_pr114", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/svunit_svunit_pr114.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/svunit_svunit_pr114", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/svunit_svunit_pr114"} {"instance_id": "svunit_svunit_pr197", "issue_text": "# Simple change to svunit_string_utils.svh to clean up VCS Warning-[IASC] Illegal argument in string comparison\n\n- Source URL: https://github.com/svunit/svunit/issues/193\n\nWhen using the latest SVUnit with VCS Version S-2021.09-SP2-4\r\nI get this warning which makes you do a double take each time you run tests:\r\n\r\nWarning-[IASC] Illegal argument in string comparison\r\n/proj/ccd_func_dev0/users/craftsmanship/repos/svunit/svunit_base/svunit_string_utils.svh, 17\r\nsvunit_pkg, \"s[i]\"\r\n Either string or string literal is expected as first argument to the string \r\n comparison operation.\r\n Use the string cast operator to convert it to a string literal.\r\n\r\n\r\nThe fix is this:\r\niff --git a/svunit_base/svunit_string_utils.svh b/svunit_base/svunit_string_utils.svh\r\nindex 2b2e5b4..b1a437b 100644\r\n--- a/svunit_base/svunit_string_utils.svh\r\n+++ b/svunit_base/svunit_string_utils.svh\r\n@@ -13,7 +13,7 @@\r\n for (int i = 0; i < s.len(); i++) begin\r\n if (i == s.len()-1)\r\n parts.push_back(s.substr(last_char_position+1, i));\r\n- if (s[i] == char) begin\r\n+ if (string'(s[i]) == char) begin\r\n\r\n\r\nLet me know if I can be of more help.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/svunit_svunit_pr197", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/svunit_svunit_pr197.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/svunit_svunit_pr197", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/svunit_svunit_pr197"} {"instance_id": "taichi-ishitani_tvip-apb_pr5", "issue_text": "# Error when no wait states 3.1.1\n\n- Source URL: https://github.com/taichi-ishitani/tvip-apb/issues/3\n\nHi Taichi! I find problem. When pready always == 1, then penable not assert, and psel tick only 1 clk. \r\n\r\n![Screenshot from 2023-11-01 16-08-25](https://github.com/taichi-ishitani/tvip-apb/assets/35744340/2c2f8925-bde3-4887-8cbd-5db50d269c69)\r\n\r\n\r\nI think it's connected with this part of code \r\nhttps://github.com/taichi-ishitani/tvip-apb/blob/master/src/tvip_apb_master_driver.svh#L91\r\n\r\n```\r\n protected virtual task wait_for_done();\r\n while (!vif.master_cb.pready) begin\r\n @(vif.master_cb);\r\n end\r\n```\r\n\r\ni think this must be \r\n```\r\n protected virtual task wait_for_done();\r\n do begin\r\n @(vif.master_cb);\r\n end while (!vif.master_cb.pready) ;\r\n```\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/taichi-ishitani_tvip-apb_pr5", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/taichi-ishitani_tvip-apb_pr5.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/taichi-ishitani_tvip-apb_pr5", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/taichi-ishitani_tvip-apb_pr5"} {"instance_id": "taichi-ishitani_tvip-axi_pr20", "issue_text": "# Support wvalid preceding awvalid\n\nInstance: taichi-ishitani_tvip-axi_pr20\nSource: https://github.com/taichi-ishitani/tvip-axi/pull/20\nFetched: 2026-05-03\nRepository: taichi-ishitani/tvip-axi\nPull request: #20\nAuthor: taichi-ishitani\nState: closed\nBase branch: master\nHead branch: support_wvalid_preceding_awvalid\nCreated: 2020-09-02\nUpdated: 2020-09-02\nClosed: 2020-09-02\nMerged: 2020-09-02\n\n## PR Title\nSupport wvalid preceding awvalid\n\n## PR Description\nNo description was provided. The PR contains two commits:\n1. b3d67e1 - \"fix #19\" (the actual logic fix to allow wvalid to assert before awvalid in the slave driver/agent)\n2. a98680e - \"added a delay module to create the situation that wvalid precedes awvalid\" (testbench scaffolding to reproduce and exercise the corner case)\n\n## PR Comments\nNo conversation comments were posted. The PR was authored, reviewed and merged by taichi-ishitani (sole participant). The branch `support_wvalid_preceding_awvalid` was later deleted on Aug 1, 2022.\n\n## Linked Issues\n**Issue #19 - \"Slave driver data before address support\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"In slave driver, if more than one wvalid is received before awvalid, only one bvalid is asserted, so the tests get stuck.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/taichi-ishitani_tvip-axi_pr20", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/taichi-ishitani_tvip-axi_pr20.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/taichi-ishitani_tvip-axi_pr20", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/taichi-ishitani_tvip-axi_pr20"} -{"instance_id": "taichi-ishitani_tvip-axi_pr36", "issue_text": "# add null check to avoid null pointer exception\n\nInstance: taichi-ishitani_tvip-axi_pr36\nSource: https://github.com/taichi-ishitani/tvip-axi/pull/36\nFetched: 2026-05-03\nRepository: taichi-ishitani/tvip-axi\nPull request: #36\nAuthor: taichi-ishitani\nState: closed\nBase branch: master\nHead branch: fix_35\nCreated: 2022-05-19\nUpdated: 2022-05-19\nClosed: 2022-05-19\nMerged: 2022-05-19\n\n## PR Title\nadd null check to avoid null pointer exception\n\n## PR Description\n\"This PR is to fix #35.\"\n\nThe change adds a null-check guard so that the slave driver does not dereference a null sequence-item handle when it is reset partway through a transaction; the issue had been reported as a NULL pointer dereference in `uvm_transaction::get_event_pool` triggered by `tue_sequence_item_base::get_event` / `ended` being called from `tvip_axi_slave_driver`'s start-delay thread after a mid-transaction reset.\n\n## PR Comments\n**taichi-ishitani** (May 19, 2022): \"This PR is to fix #35.\" (Author/owner; this is the only conversation entry, posted at submission time.)\n\nNo code-review comments were posted; the PR was self-merged by taichi-ishitani at commit e2d29ef. The branch `fix_35` was deleted shortly after merge.\n\n## Linked Issues\n**Issue #35 - \"Another NULL pointer dereference after reset in the middle\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"The latest version has another NULL pointer dereference as below:\n```\nxmsim: *E,TRNULLID: NULL pointer dereference.\n File: /opt/eda/cadence/XCELIUM2103/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_transaction.svh, line = 521, pos = 14\n Scope: worklib.uvm_pkg::uvm_transaction::get_event_pool\n Time: 7134 NS + 13\nVerilog Stack Trace:\n0: function worklib.uvm_pkg::uvm_transaction::get_event_pool at /opt/eda/cadence/XCELIUM2103/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_transaction.svh:521\n1: function worklib.tue_pkg::tue_sequence_item_base#(uvm_pkg::uvm_sequence_item,tvip_axi_pkg::tvip_axi_configuration,tvip_axi_pkg::tvip_axi_status,tvip_axi_pkg::tvip_axi_configuration,tvip_axi_pkg::tvip_axi_status)::get_event at /path/to/tvip-axi/tue/src/seq/tue_sequence_item_base.svh:41\n2: function worklib.tue_pkg::tue_sequence_item_base#(uvm_pkg::uvm_sequence_item,tvip_axi_pkg::tvip_axi_configuration,tvip_axi_pkg::tvip_axi_status,tvip_axi_pkg::tvip_axi_configuration,tvip_axi_pkg::tvip_axi_status)::ended at /path/to/tvip-axi/tue/src/seq/tue_sequence_item_base.svh:51\n3: task worklib.tvip_axi_pkg::tvip_axi_slave_driver_start_delay_consumer@13753_2.delay_thread at /path/to/tvip-axi/src/tvip_axi_slave_driver.svh:66\n4: process in worklib.tvip_axi_pkg::tvip_axi_slave_driver_start_delay_consumer@13753_2.start_delay_thread.unmblk1 at /path/to/tvip-axi/src/tvip_axi_slave_driver.svh:48\n```\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/taichi-ishitani_tvip-axi_pr36", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/taichi-ishitani_tvip-axi_pr36.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/taichi-ishitani_tvip-axi_pr36", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/taichi-ishitani_tvip-axi_pr36"} +{"instance_id": "taichi-ishitani_tvip-axi_pr36", "issue_text": "# add null check to avoid null pointer exception\n\nInstance: taichi-ishitani_tvip-axi_pr36\nSource: https://github.com/taichi-ishitani/tvip-axi/pull/36\nFetched: 2026-05-03\nRepository: taichi-ishitani/tvip-axi\nPull request: #36\nAuthor: taichi-ishitani\nState: closed\nBase branch: master\nHead branch: fix_35\nCreated: 2022-05-19\nUpdated: 2022-05-19\nClosed: 2022-05-19\nMerged: 2022-05-19\n\n## PR Title\nadd null check to avoid null pointer exception\n\n## PR Description\n\"This PR is to fix #35.\"\n\nThe change adds a null-check guard so that the slave driver does not dereference a null sequence-item handle when it is reset partway through a transaction; the issue had been reported as a NULL pointer dereference in `uvm_transaction::get_event_pool` triggered by `tue_sequence_item_base::get_event` / `ended` being called from `tvip_axi_slave_driver`'s start-delay thread after a mid-transaction reset.\n\n## PR Comments\n**taichi-ishitani** (May 19, 2022): \"This PR is to fix #35.\" (Author/owner; this is the only conversation entry, posted at submission time.)\n\nNo code-review comments were posted; the PR was self-merged by taichi-ishitani at commit e2d29ef. The branch `fix_35` was deleted shortly after merge.\n\n## Linked Issues\n**Issue #35 - \"Another NULL pointer dereference after reset in the middle\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"The latest version has another NULL pointer dereference as below:\n```\nxmsim: *E,TRNULLID: NULL pointer dereference.\n File: /opt/eda/cadence/XCELIUM2103/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_transaction.svh, line = 521, pos = 14\n Scope: worklib.uvm_pkg::uvm_transaction::get_event_pool\n Time: 7134 NS + 13\nVerilog Stack Trace:\n0: function worklib.uvm_pkg::uvm_transaction::get_event_pool at /opt/eda/cadence/XCELIUM2103/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_transaction.svh:521\n1: function worklib.tue_pkg::tue_sequence_item_base#(uvm_pkg::uvm_sequence_item,tvip_axi_pkg::tvip_axi_configuration,tvip_axi_pkg::tvip_axi_status,tvip_axi_pkg::tvip_axi_configuration,tvip_axi_pkg::tvip_axi_status)::get_event at /path/to/tvip-axi/tue/src/seq/tue_sequence_item_base.svh:41\n2: function worklib.tue_pkg::tue_sequence_item_base#(uvm_pkg::uvm_sequence_item,tvip_axi_pkg::tvip_axi_configuration,tvip_axi_pkg::tvip_axi_status,tvip_axi_pkg::tvip_axi_configuration,tvip_axi_pkg::tvip_axi_status)::ended at /path/to/tvip-axi/tue/src/seq/tue_sequence_item_base.svh:51\n3: task worklib.tvip_axi_pkg::tvip_axi_slave_driver_start_delay_consumer@13753_2.delay_thread at /path/to/tvip-axi/src/tvip_axi_slave_driver.svh:66\n4: process in worklib.tvip_axi_pkg::tvip_axi_slave_driver_start_delay_consumer@13753_2.start_delay_thread.unmblk1 at /path/to/tvip-axi/src/tvip_axi_slave_driver.svh:48\n```\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/taichi-ishitani_tvip-axi_pr36", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/taichi-ishitani_tvip-axi_pr36.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/taichi-ishitani_tvip-axi_pr36", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/taichi-ishitani_tvip-axi_pr36"} {"instance_id": "taichi-ishitani_tvip-axi_pr44", "issue_text": "# fix *E,EXPRPA error reported by Cadence Xcelium simulator\n\nInstance: taichi-ishitani_tvip-axi_pr44\nSource: https://github.com/taichi-ishitani/tvip-axi/pull/44\nFetched: 2026-05-03\nRepository: taichi-ishitani/tvip-axi\nPull request: #44\nAuthor: taichi-ishitani\nState: closed\nBase branch: master\nHead branch: fix_43\nCreated: 2022-07-25\nUpdated: 2022-07-25\nClosed: 2022-07-25\nMerged: 2022-07-25\n\n## PR Title\nfix *E,EXPRPA error reported by Cadence Xcelium simulator\n\n## PR Description\nThe PR rewrites the offending construct in `tvip_axi_slave_default_sequence.svh` so that the compile-time embedded assignment that Xcelium rejects (`if ((delay = get_address_ready_delay(item)) >= 0)`) is replaced by a separate variable assignment followed by a plain comparison, eliminating the `EXPRPA` parse error. References issue #43.\n\n## PR Comments\nThe conversation pane on this PR could not be fully rendered when fetched, but the only participant on record is the author taichi-ishitani. No code-review comments were posted before merge. The PR was self-merged at commit da6fdc8 / 93f9200 on July 25, 2022, and the `fix_43` branch was deleted on Aug 1, 2022.\n\n## Linked Issues\n**Issue #43 - \"Cadence Xcelium doesn't support variable substitution in if-condition\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"Cadence Xcelium doesn't support variable substitution in if-condition as follows:\n```\n if ((delay = get_address_ready_delay(item)) >= 0) begin\n |\nxmvlog: *E,EXPRPA (/path/to/tvip-axi/src/tvip_axi_slave_default_sequence.svh,32|15): expecting a right parenthesis (')') [4.3][9.7(IEEE)].\n(`include file: /path/to/tvip-axi/src/tvip_axi_slave_default_sequence.svh line 32, file: /path/to/tvip-axi/src/tvip_axi_pkg.sv line 45)\n```\nThis issue can be reproduced by the command:\n```\ncd sample/work\nmake compile_xcelium\n```\nHere is the detailed log:\n[tvip-axi_a516ccd_sample_work_compile_xcelium.log](https://github.com/taichi-ishitani/tvip-axi/files/9177105/tvip-axi_a516ccd_sample_work_compile_xcelium.log)\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/taichi-ishitani_tvip-axi_pr44", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/taichi-ishitani_tvip-axi_pr44.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/taichi-ishitani_tvip-axi_pr44", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/taichi-ishitani_tvip-axi_pr44"} -{"instance_id": "taichi-ishitani_tvip-axi_pr47", "issue_text": "# Problem with On the Fly Reset \n\n- Source URL: https://github.com/taichi-ishitani/tvip-axi/issues/46\n\nHi @taichi-ishitani ! I have a problem when i have reset on AXI.\r\nIn my test I have AXI4 slave and DUT. \r\nWhen i asserted reset the BValid, Bid not reset to zero. \r\nThe figure below \r\n![1_problem](https://user-images.githubusercontent.com/35744340/209571013-9d82fc3e-18c5-40e0-9aba-e40201c0ee53.jpg)\r\n\r\nSo i find the problem. I think it happened because of race conditions \r\nhttps://github.com/taichi-ishitani/tvip-axi/blob/master/src/tvip_axi_slave_driver.svh#L524\r\n\r\nthis happened after \r\n```\r\n protected task drive_response(bit valid, tvip_axi_slave_driver_response_item item);\r\n vif.slave_cb.bvalid <= valid;\r\n if (valid) begin\r\n vif.slave_cb.bid <= item.get_id();\r\n vif.slave_cb.bresp <= item.get_response_status();\r\n end\r\n endtask\r\n```\r\nThis \r\n ```\r\nprotected task reset_if();\r\n vif.awready = configuration.default_awready;\r\n vif.wready = configuration.default_wready;\r\n vif.bvalid = '0;\r\n vif.bid = '0;\r\n vif.bresp = tvip_axi_response'(0);\r\n endtask\r\n```\r\n\r\nSo my decision \r\n```\r\n protected task drive_response(bit valid, tvip_axi_slave_driver_response_item item);\r\n vif.bvalid <= valid;\r\n if (valid) begin\r\n vif.bid <= item.get_id();\r\n vif.bresp <= item.get_response_status();\r\n end\r\n endtask\r\n```\r\nI'm not sure, that I understand your logic correctly, but in my case, it's work fine...\r\n\r\n![2_solve](https://user-images.githubusercontent.com/35744340/209571584-3d7cae05-5ffe-4947-88bb-d717157fa537.jpg)\r\n\r\n\r\nBest regards.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/taichi-ishitani_tvip-axi_pr47", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/taichi-ishitani_tvip-axi_pr47.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/taichi-ishitani_tvip-axi_pr47", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/taichi-ishitani_tvip-axi_pr47"} +{"instance_id": "taichi-ishitani_tvip-axi_pr47", "issue_text": "# Problem with On the Fly Reset \n\n- Source URL: https://github.com/taichi-ishitani/tvip-axi/issues/46\n\nHi @taichi-ishitani ! I have a problem when i have reset on AXI.\r\nIn my test I have AXI4 slave and DUT. \r\nWhen i asserted reset the BValid, Bid not reset to zero. \r\nThe figure below \r\n![1_problem](https://user-images.githubusercontent.com/35744340/209571013-9d82fc3e-18c5-40e0-9aba-e40201c0ee53.jpg)\r\n\r\nSo i find the problem. I think it happened because of race conditions \r\nhttps://github.com/taichi-ishitani/tvip-axi/blob/master/src/tvip_axi_slave_driver.svh#L524\r\n\r\nthis happened after \r\n```\r\n protected task drive_response(bit valid, tvip_axi_slave_driver_response_item item);\r\n vif.slave_cb.bvalid <= valid;\r\n if (valid) begin\r\n vif.slave_cb.bid <= item.get_id();\r\n vif.slave_cb.bresp <= item.get_response_status();\r\n end\r\n endtask\r\n```\r\nThis \r\n ```\r\nprotected task reset_if();\r\n vif.awready = configuration.default_awready;\r\n vif.wready = configuration.default_wready;\r\n vif.bvalid = '0;\r\n vif.bid = '0;\r\n vif.bresp = tvip_axi_response'(0);\r\n endtask\r\n```\r\n\r\nSo my decision \r\n```\r\n protected task drive_response(bit valid, tvip_axi_slave_driver_response_item item);\r\n vif.bvalid <= valid;\r\n if (valid) begin\r\n vif.bid <= item.get_id();\r\n vif.bresp <= item.get_response_status();\r\n end\r\n endtask\r\n```\r\nI'm not sure, that I understand your logic correctly, but in my case, it's work fine...\r\n\r\n![2_solve](https://user-images.githubusercontent.com/35744340/209571584-3d7cae05-5ffe-4947-88bb-d717157fa537.jpg)\r\n\r\n\r\nBest regards.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/taichi-ishitani_tvip-axi_pr47", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/taichi-ishitani_tvip-axi_pr47.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/taichi-ishitani_tvip-axi_pr47", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/taichi-ishitani_tvip-axi_pr47"} {"instance_id": "taichi-ishitani_tvip-axi_pr50", "issue_text": "# axi_slave_sub_driver don't reset response_queue\n\n- Source URL: https://github.com/taichi-ishitani/tvip-axi/issues/49\n\nHi Taichi! \r\nI have a problemlem connected with AXI Slave\r\n\r\n \r\n![Screenshot from 2023-04-11 11-27-07](https://user-images.githubusercontent.com/35744340/231102389-6b30e00d-b5be-4bf6-8aaa-79f85fd04db2.png)\r\n\r\nAfter reset i see response on R channel... \r\n\r\nI find a problem \r\nhttps://github.com/taichi-ishitani/tvip-axi/blob/master/src/tvip_axi_slave_driver.svh#L147\r\n\r\nmust delete in task \r\nhttps://github.com/taichi-ishitani/tvip-axi/blob/master/src/tvip_axi_slave_driver.svh#L196\r\n\r\n```\r\n\r\n protected task do_reset();\r\n start_delay_consumer.do_reset();\r\n\r\n ...............................................\r\n\r\n active_responses.delete();\r\n active_ids.delete();\r\n \r\n response_queue.delete(); <-------- !\r\n\r\n\r\n reset_if();\r\n @(posedge vif.areset_n);\r\n endtask\r\n\r\n```\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/taichi-ishitani_tvip-axi_pr50", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/taichi-ishitani_tvip-axi_pr50.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/taichi-ishitani_tvip-axi_pr50", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/taichi-ishitani_tvip-axi_pr50"} {"instance_id": "taichi-ishitani_tvip-common_pr4", "issue_text": "# incorrect behavior when started = 0\n\n- Source URL: https://github.com/taichi-ishitani/tvip-common/issues/3\n\nHi Taichi! I tried to create stop clk during simulation. \r\n\r\nI have this dependencies in interface\r\n```\r\n tvip_clock_if gm_clk_if();\r\n assign gm_clk_if.started = (clk_en == 1) ? 1 : 0 ;\r\n```\r\n\r\nSo, when clk_en = 0 -> gm_clk_if.started = 0 \r\n\r\nI see figure below \r\n![Screenshot_bad](https://user-images.githubusercontent.com/35744340/208059355-0a134b3e-4209-4e2c-b15e-6038418ad5f7.png)\r\n\r\nAs you can see, clk change value after clk_en = 0.\r\n\r\nI think it's not good behaviour. The main reason of it \r\n\r\nhttps://github.com/taichi-ishitani/tvip-common/blob/master/src/tvip_clock_if.sv#L36\r\n\r\n ```\r\n always @(posedge started) begin\r\n while (started) begin\r\n #(half_period); <---\r\n clk ^= 1;\r\n end\r\n end\r\n```\r\n\r\n\r\nthe delay should be after the after `clk ^= 1;`\r\n\r\n ```\r\n always @(posedge started) begin\r\n while (started) begin\r\n clk ^= 1;\r\n #(half_period);\r\n end\r\n end\r\n```\r\n\r\nIn this case figure below \r\n![Screenshot_good](https://user-images.githubusercontent.com/35744340/208060094-0206d848-9865-42a2-8721-6644ef435d80.png)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/taichi-ishitani_tvip-common_pr4", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/taichi-ishitani_tvip-common_pr4.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/taichi-ishitani_tvip-common_pr4", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/taichi-ishitani_tvip-common_pr4"} -{"instance_id": "va7deo_zerowing_pr17", "issue_text": "# Tile priority workaround for Truxton. Sprite position tweaks and fix. Keyboard handler.\n\nInstance: va7deo_zerowing_pr17\nSource: https://github.com/va7deo/zerowing/pull/17\nFetched: 2026-05-03\nRepository: va7deo/zerowing\nPull request: #17\nAuthor: blackwine\nState: closed\nBase branch: main\nHead branch: main (blackwine fork)\nCreated: 2022-02-05\nUpdated: 2022-02-05\nClosed: 2022-02-05\nMerged: 2022-02-05\n\n## PR Title\nTile priority workaround for Truxton. Sprite position tweaks and fix. Keyboard handler.\n\n## PR Description\nCloses issue #14. Includes 4 commits:\n1. \"Differentiate tile priority checks. Tweak sprite positions\" (76c900c)\n2. \"Add clock to chip select\" (8738db5)\n3. \"Add keyboard handler\" (7fca9f5)\n4. \"Fix regression with sprite pos. adjustments\" (481355f)\n\nTogether these add a Truxton-targeted tile-priority workaround, tweak/fix sprite positioning, and introduce a keyboard input handler so that JPAC-style controllers/MAME keyboards work out of the box.\n\n## PR Comments\n**blackwine** (Feb 5, 2022): \"Closes #14\"\n\n**va7deo** (Feb 5, 2022): Merged the pull request the same day.\n\n## Linked Issues\n**Issue #14 - \"Support for MAME keys\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"Please add this, as it would make JPAC devices work out of the box.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/va7deo_zerowing_pr17", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/va7deo_zerowing_pr17.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/va7deo_zerowing_pr17", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/va7deo_zerowing_pr17"} -{"instance_id": "verilator_verilator_pr6552", "issue_text": "# Support basic global constraints (#6551)\n\nInstance: verilator_verilator_pr6552\nSource: https://github.com/verilator/verilator/pull/6552\nFetched: 2026-05-03\nRepository: verilator/verilator\nPull request: #6552\nAuthor: YilouWang\nState: closed\nBase branch: master\nHead branch: new_branch_for_global_rand\nCreated: 2025-10-12\nUpdated: 2025-11-05\nClosed: 2025-11-05\nMerged: 2025-11-05\n\n## PR Title\nSupport basic global constraints (#6551)\n\n## PR Description\nImplements the global-constraints feature defined in IEEE 1800-2023 section 18.5.8, addressing issue #6551. The implementation has three main pieces:\n\n1. Global-constraint detection: an `isGlobalConstrained` flag is added to AstVar to identify variables participating in global constraints.\n2. Constraint hoisting: constraints from nested member classes are extracted and evaluated together at the top-level class so that cross-object constraint solving works.\n3. MemberSel handling: logic for nested member-access paths (e.g. `m1.inner.val`) is added so the SMT variable declaration is correct.\n\nThe author noted a memory leak issue early on which was addressed via subsequent refinements. The feature was developed across many commits between Sep 19 and Nov 5, 2025.\n\n## PR Comments\n**RRozak**: Pointed out that the implementation does not handle polymorphic-type scenarios where the declared class type differs from the actual runtime type. **YilouWang** agreed to handle this in a follow-up PR.\n\n**wsnyder**: Requested verification of `rand_mode` behaviour against the IEEE specification. Reviewed across multiple iterations and ultimately merged on Nov 5, 2025.\n\nOther participants: gezalore (review), udayaa-init (contributions/co-author).\n\n## Linked Issues\n**Issue #6551 - \"Support global constraints\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"After [PR#5625](https://github.com/verilator/verilator/pull/5625), global constraints has been kept as an unsupported warning messages, which needs to be fixed.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6552", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6552.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6552", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6552"} +{"instance_id": "va7deo_zerowing_pr17", "issue_text": "# Tile priority workaround for Truxton. Sprite position tweaks and fix. Keyboard handler.\n\nInstance: va7deo_zerowing_pr17\nSource: https://github.com/va7deo/zerowing/pull/17\nFetched: 2026-05-03\nRepository: va7deo/zerowing\nPull request: #17\nAuthor: blackwine\nState: closed\nBase branch: main\nHead branch: main (blackwine fork)\nCreated: 2022-02-05\nUpdated: 2022-02-05\nClosed: 2022-02-05\nMerged: 2022-02-05\n\n## PR Title\nTile priority workaround for Truxton. Sprite position tweaks and fix. Keyboard handler.\n\n## PR Description\nCloses issue #14. Includes 4 commits:\n1. \"Differentiate tile priority checks. Tweak sprite positions\" (76c900c)\n2. \"Add clock to chip select\" (8738db5)\n3. \"Add keyboard handler\" (7fca9f5)\n4. \"Fix regression with sprite pos. adjustments\" (481355f)\n\nTogether these add a Truxton-targeted tile-priority workaround, tweak/fix sprite positioning, and introduce a keyboard input handler so that JPAC-style controllers/MAME keyboards work out of the box.\n\n## PR Comments\n**blackwine** (Feb 5, 2022): \"Closes #14\"\n\n**va7deo** (Feb 5, 2022): Merged the pull request the same day.\n\n## Linked Issues\n**Issue #14 - \"Support for MAME keys\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"Please add this, as it would make JPAC devices work out of the box.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/va7deo_zerowing_pr17", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/va7deo_zerowing_pr17.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/va7deo_zerowing_pr17", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/va7deo_zerowing_pr17"} +{"instance_id": "verilator_verilator_pr6552", "issue_text": "# Support basic global constraints (#6551)\n\nInstance: verilator_verilator_pr6552\nSource: https://github.com/verilator/verilator/pull/6552\nFetched: 2026-05-03\nRepository: verilator/verilator\nPull request: #6552\nAuthor: YilouWang\nState: closed\nBase branch: master\nHead branch: new_branch_for_global_rand\nCreated: 2025-10-12\nUpdated: 2025-11-05\nClosed: 2025-11-05\nMerged: 2025-11-05\n\n## PR Title\nSupport basic global constraints (#6551)\n\n## PR Description\nImplements the global-constraints feature defined in IEEE 1800-2023 section 18.5.8, addressing issue #6551. The implementation has three main pieces:\n\n1. Global-constraint detection: an `isGlobalConstrained` flag is added to AstVar to identify variables participating in global constraints.\n2. Constraint hoisting: constraints from nested member classes are extracted and evaluated together at the top-level class so that cross-object constraint solving works.\n3. MemberSel handling: logic for nested member-access paths (e.g. `m1.inner.val`) is added so the SMT variable declaration is correct.\n\nThe author noted a memory leak issue early on which was addressed via subsequent refinements. The feature was developed across many commits between Sep 19 and Nov 5, 2025.\n\n## PR Comments\n**RRozak**: Pointed out that the implementation does not handle polymorphic-type scenarios where the declared class type differs from the actual runtime type. **YilouWang** agreed to handle this in a follow-up PR.\n\n**wsnyder**: Requested verification of `rand_mode` behaviour against the IEEE specification. Reviewed across multiple iterations and ultimately merged on Nov 5, 2025.\n\nOther participants: gezalore (review), udayaa-init (contributions/co-author).\n\n## Linked Issues\n**Issue #6551 - \"Support global constraints\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"After [PR#5625](https://github.com/verilator/verilator/pull/5625), global constraints has been kept as an unsupported warning messages, which needs to be fixed.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6552", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6552.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6552", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/verilator_verilator_pr6552"} {"instance_id": "verilator_verilator_pr6573", "issue_text": "# Support `std::randomize() with`\n\n- Source URL: https://github.com/verilator/verilator/issues/4706\n\nHi,\r\nI'm using some Pulp code which has the following construct in https://github.com/pulp-platform/riscv-dbg/blob/master/src/dmi_test.sv.\r\nWhen I run this test, I get \r\n%Error-UNSUPPORTED: dmi_test.sv:182:45: Unsupported: randomize() 'with' constraint\r\n 182 | rand_success = std::randomize(cycles) with {\r\n | ^~~~\r\nIs there any ETA on adding this feature? Is this something which might come with UVM support?\r\n\r\nThanks\r\n\r\n task automatic rand_wait(input int unsigned min, input int unsigned max);\r\n int unsigned rand_success, cycles;\r\n rand_success = std::randomize(cycles) with {\r\n cycles >= min;\r\n cycles <= max;\r\n // Weigh the distribution so that the minimum cycle time is the common\r\n // case.\r\n cycles dist {min := 10, [min+1:max] := 1};\r\n };\r\n assert (rand_success) else $error(\"Failed to randomize wait cycles!\");\r\n repeat (cycles) @(posedge this.drv.bus.clk_i);\r\n endtask\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6573", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6573.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6573", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6573"} {"instance_id": "verilator_verilator_pr6583", "issue_text": "# Trior/and wor/wand nettypes missing from FST trace module\n\n- Source URL: https://github.com/verilator/verilator/issues/6582\n\nThanks for the great software!\n\nIt appears maybe the relatively recently added support for `trior/and` and `wor/wand` net types was missing updates for FST dumping of the same?\n\n> Can you please attach an example that shows the issue or missing feature? \n\nUpdating `test_regress/t/t_trace_fst.v` with:\n\n```diff\ndiff --git a/test_regress/t/t_trace_fst.v b/test_regress/t/t_trace_fst.v\nindex 44ac7feac..4091d0e75 100644\n--- a/test_regress/t/t_trace_fst.v\n+++ b/test_regress/t/t_trace_fst.v\n@@ -38,7 +38,13 @@ module t (/*AUTOARG*/\n tri0 fst_tri0;\n tri1 fst_tri1;\n tri fst_tri;\n+ triand fst_triand;\n+ trior fst_trior;\n+ //trireg fst_trireg; // Error-UNSUPPORTED\n+ wor fst_wor;\n+ wand fst_wand;\n wire fst_wire;\n+ uwire fst_uwire;\n inout fst_inout;\n\n Test test (/*AUTOINST*/\n```\n\n> What output from that test indicates it is wrong, and what is the correct or expected output?\n\nYields:\n\n```\n#vlt/t_trace_fst: %Error: Exec of make failed: Vt_trace_fst__Trace__0__Slow.cpp:41:102: error: ‘TRIAND’ is not a member of ‘VerilatedTraceSigKind’\n make && test_regress/t/t_trace_fst.py --vlt\n```\n\n> What 'verilator' command line do we use to run your example?\n\n`test_regress/t/t_trace_fst.py`\n\n> What 'verilator --version' are you using? Did you try it with the git master version? Did you try it with other simulators?\n\n[master@cc7723390](https://github.com/verilator/verilator/commit/cc77233902f40cf8b90fb267d00890f2a4e3755e)\n`Verilator 5.041 devel rev UNKNOWN.REV (mod)`\n\n> What OS and distribution are you using?\n\nUbuntu/WSL 2.0\n\n> May we assist you in trying to fix this in Verilator yourself?\n\nSure! New to contributing but happy to help if I can!\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6583", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6583.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6583", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6583"} {"instance_id": "verilator_verilator_pr6596", "issue_text": "# repeat(@posedge) inside a task causes incorrect timing on second call\n\n- Source URL: https://github.com/verilator/verilator/issues/6593\n\nWhen using repeat(N) @(posedge CLK); inside a task, Verilator produces incorrect timing behavior only on the second call of the task.\n\n\nVerilator 5.041 devel rev v5.040-333-gd864057a6\n\n--------------------------------------------------------------------------------\n```\n`timescale 1ns/1ps\n`default_nettype none\n\nmodule tb();\n\n // VCD or FST Dump\n initial\n if( $test$plusargs (\"WAVE\") ) begin\n $dumpfile(\"wave_test1.dump\");\n $dumpvars(0, tb);\n end\n\n parameter int PREOD = 100; // 100ns(10MHz)\n\n bit CLK;\n\n localparam int H_PREOD = PREOD / 2;\n always #H_PREOD\n CLK = ~CLK;\n\n\n task automatic next_bit(); // NG\n repeat(4)\n @(posedge CLK);\n endtask\n\n/*\n task automatic next_bit(); // OK\n repeat(3)\n @(posedge CLK);\n\n @(posedge CLK);\n endtask\n*/\n\n bit [3:0] cnt = 0;\n\n task test_txd();\n cnt = 0; \n next_bit();\n for(int i=0; i < 8; i++) begin\n ++cnt;\n next_bit();\n end\n\n ++cnt;\n next_bit();\n endtask\n\n\n initial begin\n test_txd();\n test_txd();\n\n repeat(10) @(posedge CLK);\n $finish; \n end\n\nendmodule\n```\n--------------------------------------------------------------------------------\n\n\"Image\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6596", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6596.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6596", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6596"} {"instance_id": "verilator_verilator_pr6630", "issue_text": "# `--coverage` triggers complaints for certain ternary assignments.\n\n- Source URL: https://github.com/verilator/verilator/issues/6629\n\nHi team at Verilator!\n\nIn version 5.042, we noticed multiple new warnings like the following:\n```\n%Warning-SIDEEFFECT: top.sv:36:67: Expression side effect may be mishandled\n : ... Suggest use a temporary variable in place of this expression\n 36 | assign out_ipv4_header.header_chk_sum = csum == 16'hFFFF ? csum : ~csum;\n | ^\n ... For warning description see https://verilator.org/warn/SIDEEFFECT?v=5.042\n ... Use \"/* verilator lint_off SIDEEFFECT */\" and lint_on around source to disable this message.\n```\n\nTo reproduce the issue, please clone this repo.:\n[https://github.com/etep/verilator-5.042-possible-issue](https://github.com/etep/verilator-5.042-possible-issue)\n\nRun `make` or `make clean && make`.\n\nIf arg. `--coverage` is removed, the warnings are gone.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6630", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6630.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6630", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6630"} {"instance_id": "verilator_verilator_pr6631", "issue_text": "# \"Missed a time slot?\" simulation error when verilated with --timing and --x-initial-edge\n\n- Source URL: https://github.com/verilator/verilator/issues/6603\n\nThe following code causes simulation to abort when verilated with `--timing` and `--x-initial-edge`:\n```SystemVerilog\nmodule test; \ninitial begin \n #10; \nend \nendmodule\n```\n\nThe error:\n```\n%Error: /usr/local/share/verilator/include/verilated_timing.cpp:83: %Error: Encountered process that should've been resumed at an earlier simulation time. Missed a time slot?\n```\nReproducing (`--binary` implies `--timing`):\n```\necho \"module test; initial begin #10; end endmodule\" > test.sv\nverilator --binary --x-initial-edge test.sv\n./obj_dir/Vtest\n```\nverilator --version:\n```\nVerilator 5.040 2025-08-30 rev v5.040 & Verilator 5.041 devel rev v5.040-358-gb65200923\n```\nOS: Ubuntu 24.04.2 LTS (and the one used in verilator docker container)\n\nSeems to be related to #5723, specifically this [comment](https://github.com/verilator/verilator/issues/5723#issuecomment-3407078256) there.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6631", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6631.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6631", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6631"} {"instance_id": "verilator_verilator_pr6668", "issue_text": "# Add --unroll-limit option (#6654)\n\nInstance: verilator_verilator_pr6668\nSource: https://github.com/verilator/verilator/pull/6668\nFetched: 2026-05-03\nRepository: verilator/verilator\nPull request: #6668\nAuthor: gezalore\nState: closed\nBase branch: master\nHead branch: unroll-error\nCreated: 2025-11-09\nUpdated: 2025-11-09\nClosed: 2025-11-09\nMerged: 2025-11-09\n\n## PR Title\nAdd --unroll-limit option (#6654)\n\n## PR Description\nSplits the dual-purpose `--unroll-count` knob requested in issue #6654 by introducing a new option that controls only the upper-bound used for infinite-loop detection in generate loops, V3Simulate and `unroll_full`, leaving `--unroll-count` to apply to procedural loops as before. The flag was originally proposed as `--unroll-error`; reviewer feedback led to renaming it to `--unroll-limit` to be consistent with `--converge-limit`.\n\n## PR Comments\n**gezalore** (Nov 9, 2025): \"Fixes #6654\"\n\n**wsnyder** (Nov 9, 2025, review): Suggested avoiding \"error\" in flag names; proposed `--unroll-limit` to match the naming pattern of existing options like `--converge-limit`, calling it \"better\" and a \"help understanding\".\n\n**gezalore** (Nov 9, 2025): \"Agreed that's better, renamed.\"\n\n**gezalore** (Nov 9, 2025): \"Please merge this if you are happy with it.\"\n\n**wsnyder** (Nov 9, 2025): Merged with 53 checks passing.\n\n## Linked Issues\n**Issue #6654 - \"Split --unroll-count option\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"Currently `--unroll-count` applies both to procedural loop statements, and also to generate loops (with a fudge factor).\n\nIt is sometimes advantageous to reduce loop unrolling for procedural statement, but due to the same number being applied to generate loops, it cannot be set to an arbitrarily small number.\n\nThe only reason generate loops need a limit is to avoid infinite expansion when there is a user bug, e.g. a missing `++i` in the generate loop.\n\nI would like to propose to re-purpose `--unroll-count` to apply only to procedural loops, and add a new option (`--unroll-max` maybe?) with a very large default value (16K, which is the current default for generate+simulate usage?) that is only used for infinite loop detection (gen loops, V3Simulate, unroll_full pragma usage).\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6668", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6668.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6668", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6668"} -{"instance_id": "verilator_verilator_pr6697", "issue_text": "# Incorrect `streaming_concatenation`\n\n- Source URL: https://github.com/verilator/verilator/issues/6693\n\n> Thanks for taking the time to report this.\n> Can you please attach an example that shows the issue or missing feature? (Must be openly licensed, completely self-contained so can directly run what you provide. Ideally use test_regress format, see https://veripool.org/guide/latest/contributing.html?highlight=test_regress#reporting-bugs)\n\nHere is code that reproduces the bug\n\n```sv\nmodule top;\n logic [7:0] b = 8'hA5;\n logic [31:0] y;\n \n // The problematic assignment\n always_comb begin\n y = {<<{b}}; // Should place result in MSBs, zeros in LSBs\n end\n \n initial begin\n #10; \n \n $display(\"Input b = %h (%b)\", b, b);\n $display(\"Output y = %h (%b)\", y, y);\n $display(\"\");\n $display(\"According to IEEE 1800-2023:\");\n $display(\" Stream should be in MSBs: %h\", {b, 24'b0});\n $display(\" Zeros should be in LSBs\");\n $display(\"\");\n $display(\"Verilator result: %h\", y);\n $display(\"Expected result: %h\", {b, 24'b0});\n $display(\"\");\n \n if (y == {b, 24'b0}) begin\n $display(\"PASS: Verilator is correct\");\n end else begin\n $display(\"FAIL: Verilator bug - stream placed in LSBs instead of MSBs\");\n $display(\" Got: %h\", y);\n $display(\" Expected: %h\", {b, 24'b0});\n end\n \n $finish;\n end\nendmodule\n```\n\n> What output from that test indicates it is wrong, and what is the correct or expected output? (Or, please make test self-checking if possible.)\n\nThe IEEE 1800-2023 in 11.4.14 specifies that \n>> If the target represents a fixed-size variable that is wider than the stream, the stream shall be widened to match it by filling with zero bits on the right.\n\n> What 'verilator' command line do we use to run your example?\n\n```sh\nverilator --binary --exe --build -Mdir obj_dir -sv --timing -Wno-WIDTHEXPAND top.sv && ./obj_dir/Vtop\n```\n\n> What 'verilator --version' are you using? Did you try it with the git master version? Did you try it with other simulators?\n\nI am using git upstream version `Verilator 5.043 devel rev v5.042-59-gf32095dd1`. All other simulators I tried it on succeeded.\n\n> What OS and distribution are you using?\n\nLinux arch\n\n> May we assist you in trying to fix this in Verilator yourself?\n\nI think this should not be too complicated to fix, so I wouldn't mind trying to fix it.\n\n> (Please avoid attaching screenshots that show text - you can convert images to text using e.g. https://ocr.space)\n\nWhen checking for open issues that contained the word `streaming` I did not have the impression that they explicitly mentionned that the result was incorrect compared to the IEEE. Sorry if this is a duplicate.\nThanks for the work on verilator !\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6697", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6697.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6697", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6697"} +{"instance_id": "verilator_verilator_pr6697", "issue_text": "# Incorrect `streaming_concatenation`\n\n- Source URL: https://github.com/verilator/verilator/issues/6693\n\n> Thanks for taking the time to report this.\n> Can you please attach an example that shows the issue or missing feature? (Must be openly licensed, completely self-contained so can directly run what you provide. Ideally use test_regress format, see https://veripool.org/guide/latest/contributing.html?highlight=test_regress#reporting-bugs)\n\nHere is code that reproduces the bug\n\n```sv\nmodule top;\n logic [7:0] b = 8'hA5;\n logic [31:0] y;\n \n // The problematic assignment\n always_comb begin\n y = {<<{b}}; // Should place result in MSBs, zeros in LSBs\n end\n \n initial begin\n #10; \n \n $display(\"Input b = %h (%b)\", b, b);\n $display(\"Output y = %h (%b)\", y, y);\n $display(\"\");\n $display(\"According to IEEE 1800-2023:\");\n $display(\" Stream should be in MSBs: %h\", {b, 24'b0});\n $display(\" Zeros should be in LSBs\");\n $display(\"\");\n $display(\"Verilator result: %h\", y);\n $display(\"Expected result: %h\", {b, 24'b0});\n $display(\"\");\n \n if (y == {b, 24'b0}) begin\n $display(\"PASS: Verilator is correct\");\n end else begin\n $display(\"FAIL: Verilator bug - stream placed in LSBs instead of MSBs\");\n $display(\" Got: %h\", y);\n $display(\" Expected: %h\", {b, 24'b0});\n end\n \n $finish;\n end\nendmodule\n```\n\n> What output from that test indicates it is wrong, and what is the correct or expected output? (Or, please make test self-checking if possible.)\n\nThe IEEE 1800-2023 in 11.4.14 specifies that \n>> If the target represents a fixed-size variable that is wider than the stream, the stream shall be widened to match it by filling with zero bits on the right.\n\n> What 'verilator' command line do we use to run your example?\n\n```sh\nverilator --binary --exe --build -Mdir obj_dir -sv --timing -Wno-WIDTHEXPAND top.sv && ./obj_dir/Vtop\n```\n\n> What 'verilator --version' are you using? Did you try it with the git master version? Did you try it with other simulators?\n\nI am using git upstream version `Verilator 5.043 devel rev v5.042-59-gf32095dd1`. All other simulators I tried it on succeeded.\n\n> What OS and distribution are you using?\n\nLinux arch\n\n> May we assist you in trying to fix this in Verilator yourself?\n\nI think this should not be too complicated to fix, so I wouldn't mind trying to fix it.\n\n> (Please avoid attaching screenshots that show text - you can convert images to text using e.g. https://ocr.space)\n\nWhen checking for open issues that contained the word `streaming` I did not have the impression that they explicitly mentionned that the result was incorrect compared to the IEEE. Sorry if this is a duplicate.\nThanks for the work on verilator !\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6697", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6697.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6697", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/verilator_verilator_pr6697"} {"instance_id": "verilator_verilator_pr6723", "issue_text": "# X input values are not handled correctly in UDPs\n\n- Source URL: https://github.com/verilator/verilator/issues/6722\n\nTo reproduce:\n\n```verilog\nmodule t ();\n\n wire true;\n not1 a(true, '0);\n\n wire false;\n not1 b(false, '1);\n\n initial begin\n if (true != '1) $stop;\n if (false != '0) $stop;\n $finish;\n end\n\nendmodule // t\n\nprimitive not1 (q, d);\n output q;\n input d;\n table\n 0 : 1;\n 1 : 0;\n x : x;\n endtable\nendprimitive // not1\n```\n\nAnd the test driver code:\n\n```python3\nimport vltest_bootstrap\ntest.scenarios('vlt_all')\ntest.compile()\ntest.execute()\ntest.passes()\n```\n\nThe expected result is that the `true` and `false` wires will be 1 and 0, respectively. However, they are both set to X (depending on the value of the `--x-assign` command-line argument).\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6723", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6723.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6723", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6723"} -{"instance_id": "verilator_verilator_pr6737", "issue_text": "# Support complex std::randomize patterns using args replacement strategy (#6736)\n\nInstance: verilator_verilator_pr6737\nSource: https://github.com/verilator/verilator/pull/6737\nFetched: 2026-05-03\nRepository: verilator/verilator\nPull request: #6737\nAuthor: YilouWang\nState: closed\nBase branch: master\nHead branch: fix/std-randomize-foreach-arraysel\nCreated: 2025-11-26\nUpdated: 2025-12-01\nClosed: 2025-12-01\nMerged: 2025-12-01\n\n## PR Title\nSupport complex std::randomize patterns using args replacement strategy (#6736)\n\n## PR Description\nImplements an argument-replacement strategy for `std::randomize()` that supports:\n\n1. Array-element arguments (e.g. `std::randomize(arr[i])` inside `foreach` loops)\n2. Mixed argument types (`VarRef`, `MemberSel`, `ArraySel` in the same call)\n\nMechanically:\n- All arguments are replaced with `__Varg*` reference parameters\n- A `similarNode` matching predicate is added so semantic equality works across the three node types\n- `__Varg*` are excluded from being re-captured by `CaptureVisitor`\n- Null-pointer guards are added for robustness\n\nCloses issue #6736 (\"Support ArraySel in foreach case and Mixed arguments types case in std::randomize\"). 31 commits in total. Coverage at merge: 100% line, 75% branch.\n\n## PR Comments\nThe conversation contained iterative review feedback between YilouWang and the maintainers (wsnyder, udayaa-init) over the late-Nov / early-Dec window. The author addressed all review threads before wsnyder merged on Dec 1, 2025; 73 checks passed.\n\n## Linked Issues\n**Issue #6736 - \"Support 'ArraySel in foreach' case and 'Mixed arguments types' case in std::randomize\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"Following PR #6719 , we found issues while testing other cases.\nCurrently, there are two cases that are problematic:\n\n1. ArraySel in foreach loop\n2. VarRef/MemberSel/ArraySel mixed case\n\nThe issues stem from how arguments are handled in std::randomize().\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6737", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6737.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6737", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6737"} +{"instance_id": "verilator_verilator_pr6737", "issue_text": "# Support complex std::randomize patterns using args replacement strategy (#6736)\n\nInstance: verilator_verilator_pr6737\nSource: https://github.com/verilator/verilator/pull/6737\nFetched: 2026-05-03\nRepository: verilator/verilator\nPull request: #6737\nAuthor: YilouWang\nState: closed\nBase branch: master\nHead branch: fix/std-randomize-foreach-arraysel\nCreated: 2025-11-26\nUpdated: 2025-12-01\nClosed: 2025-12-01\nMerged: 2025-12-01\n\n## PR Title\nSupport complex std::randomize patterns using args replacement strategy (#6736)\n\n## PR Description\nImplements an argument-replacement strategy for `std::randomize()` that supports:\n\n1. Array-element arguments (e.g. `std::randomize(arr[i])` inside `foreach` loops)\n2. Mixed argument types (`VarRef`, `MemberSel`, `ArraySel` in the same call)\n\nMechanically:\n- All arguments are replaced with `__Varg*` reference parameters\n- A `similarNode` matching predicate is added so semantic equality works across the three node types\n- `__Varg*` are excluded from being re-captured by `CaptureVisitor`\n- Null-pointer guards are added for robustness\n\nCloses issue #6736 (\"Support ArraySel in foreach case and Mixed arguments types case in std::randomize\"). 31 commits in total. Coverage at merge: 100% line, 75% branch.\n\n## PR Comments\nThe conversation contained iterative review feedback between YilouWang and the maintainers (wsnyder, udayaa-init) over the late-Nov / early-Dec window. The author addressed all review threads before wsnyder merged on Dec 1, 2025; 73 checks passed.\n\n## Linked Issues\n**Issue #6736 - \"Support 'ArraySel in foreach' case and 'Mixed arguments types' case in std::randomize\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"Following PR #6719 , we found issues while testing other cases.\nCurrently, there are two cases that are problematic:\n\n1. ArraySel in foreach loop\n2. VarRef/MemberSel/ArraySel mixed case\n\nThe issues stem from how arguments are handled in std::randomize().\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6737", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/main/patches/verilator_verilator_pr6737.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6737", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/verilator_verilator_pr6737"} {"instance_id": "verilator_verilator_pr6815", "issue_text": "# Inline small CFuncs to reduce function call overhead\n\nInstance: verilator_verilator_pr6815\nSource: https://github.com/verilator/verilator/pull/6815\nFetched: 2026-05-03\nRepository: verilator/verilator\nPull request: #6815\nAuthor: 10U-Labs (contributor)\nState: closed\nBase branch: master\nHead branch: inline-cfuncs\nCreated: 2025-12-14\nUpdated: 2025-12-21\nClosed: 2025-12-21\nMerged: 2025-12-21\n\n## PR Title\nInline small CFuncs to reduce function call overhead\n\n## PR Description\nAdds two new command-line options - `--inline-cfuncs ` (default 20) and `--inline-cfuncs-product ` (default 200) - that let Verilator inline small CFunc calls directly into their callers, eliminating function-call overhead when `--output-split-cfuncs` puts callees in a separate translation unit that the C++ compiler cannot inline across.\n\nInlining criteria: function size <= n nodes (always inline), or size * call_count <= product threshold; the function must contain no `$c()` statements, return `void`, and be in the same scope as its callers. Local variables are cloned with unique names (`__Vinline__`). The optimisation is automatically disabled by `--prof-cfuncs` or `--trace`.\n\nThis PR supersedes #6765, with the implementation moved out of `V3OrderCFuncEmitter` into a separate `V3InlineCFuncs` pass; `--inline-cfuncs` was changed from a boolean flag into a numeric threshold; variable merging was added; and `V3Stats` tracks \"Optimizations, Inlined CFuncs\". Coverage at merge: 100% line (80/80), 88.46% branches (46/52).\n\n## PR Comments\nThe maintainer requested allowing inlining of functions with local variables (rather than excluding them) and suggested using two tunable thresholds for flexibility - the author implemented both. Multiple test cases were added to cover enabled/disabled states and threshold behavior. Merged on Dec 21, 2025.\n\n## Linked Issues\n**Issue #2367 - \"Optimize short Active blocks inline into _eval\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"EH1 has a lot of examples where a sequent CFunc contains only a handful ot statements (often 1 or 2) and is called only once. This causes a performance penalty when --output-split puts these in a different function than _eval and hence the compiler can't inline them, so we should inline these ourselve when it's obviously the right thing to do.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6815", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6815.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6815", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6815"} {"instance_id": "verilator_verilator_pr6822", "issue_text": "# Chisel 7.3.0 generated Mux1H simulates slower than Chisel 6\n\n- Source URL: https://github.com/verilator/verilator/issues/6760\n\nCan you please attach an example that shows the issue or missing feature?\n\nPlease see: https://github.com/cyyself/verilator-chisel7-regression\n\nWe discovered a significant performance regression in Verilator simulation when using Chisel 7 compared to Chisel 6 for designs that utilize `Mux1H` with a large number of inputs with LLVM-19.\n\n```scala\nclass Test extends RawModule {\n val width = 7 // 2**7 = 128 entries\n val io = IO(new Bundle {\n val in = Input(Vec((1 << width), UInt(32.W)))\n val sel = Input(UInt(width.W))\n val out = Output(UInt(32.W))\n })\n\n val sel = UIntToOH(io.sel, 1 << width)\n io.out := Mux1H(sel, io.in)\n}\n```\n\nIn Chisel 6.7.0, the Verilog will be like:\n\n```systemverilog\n assign io_out =\n (io_sel == 7'h0 ? io_in_0 : 32'h0) | (io_sel == 7'h1 ? io_in_1 : 32'h0)\n | (io_sel == 7'h2 ? io_in_2 : 32'h0) | (io_sel == 7'h3 ? io_in_3 : 32'h0)\n | (io_sel == 7'h4 ? io_in_4 : 32'h0) | (io_sel == 7'h5 ? io_in_5 : 32'h0)\n | (io_sel == 7'h6 ? io_in_6 : 32'h0) | (io_sel == 7'h7 ? io_in_7 : 32'h0)\n | (io_sel == 7'h8 ? io_in_8 : 32'h0) | (io_sel == 7'h9 ? io_in_9 : 32'h0)\n // ... snip ...\n```\nIn Chisel 7.3.0, the Verilog will be like:\n\n```systemverilog\n wire [127:0] sel = 128'h1 << io_sel;\t// src/main/scala/chisel3/util/OneHot.scala:65:12\n assign io_out =\n (sel[0] ? io_in_0 : 32'h0) | (sel[1] ? io_in_1 : 32'h0) | (sel[2] ? io_in_2 : 32'h0)\n | (sel[3] ? io_in_3 : 32'h0) | (sel[4] ? io_in_4 : 32'h0) | (sel[5] ? io_in_5 : 32'h0)\n | (sel[6] ? io_in_6 : 32'h0) | (sel[7] ? io_in_7 : 32'h0) | (sel[8] ? io_in_8 : 32'h0)\n | (sel[9] ? io_in_9 : 32'h0) | (sel[10] ? io_in_10 : 32'h0)\n // ... snip ...\n```\n\nIt has no difference in functionality, but let's look at the Verilator output for both versions.\n\nIn Chisel 6.7.0, Verilator generates the following code:\n\n```cpp\n vlSelfRef.Test__DOT____VdfgBinToOneHot_Tab_h807d22cc_0_0[vlSelfRef.Test__DOT____VdfgBinToOneHot_Pre_h807d22cc_0_0] = 0U;\n vlSelfRef.Test__DOT____VdfgBinToOneHot_Tab_h807d22cc_0_0[vlSelfRef.io_sel] = 1U;\n vlSelfRef.Test__DOT____VdfgBinToOneHot_Pre_h807d22cc_0_0 \n = vlSelfRef.io_sel;\n __Vdeeptemp_h9151389e__0 = ((vlSelfRef.Test__DOT____VdfgBinToOneHot_Tab_h807d22cc_0_0\n [9U] ? vlSelfRef.io_in_9\n : 0U) | ((vlSelfRef.Test__DOT____VdfgBinToOneHot_Tab_h807d22cc_0_0\n [0x0aU]\n ? vlSelfRef.io_in_10\n : 0U) \n | ((vlSelfRef.Test__DOT____VdfgBinToOneHot_Tab_h807d22cc_0_0\n [0x0bU]\n ? vlSelfRef.io_in_11\n : 0U) \n```\n\nIn Chisel 7.3.0, Verilator generates the following code:\n\n```cpp\n __Vtemp_1[0U] = 1U;\n __Vtemp_1[1U] = 0U;\n __Vtemp_1[2U] = 0U;\n __Vtemp_1[3U] = 0U;\n VL_SHIFTL_WWI(128,128,7, __Vtemp_2, __Vtemp_1, (IData)(vlSelfRef.io_sel));\n __Vtemp_3[0U] = 1U;\n __Vtemp_3[1U] = 0U;\n __Vtemp_3[2U] = 0U;\n __Vtemp_3[3U] = 0U;\n VL_SHIFTL_WWI(128,128,7, __Vtemp_4, __Vtemp_3, (IData)(vlSelfRef.io_sel));\n __Vtemp_5[0U] = 1U;\n __Vtemp_5[1U] = 0U;\n __Vtemp_5[2U] = 0U;\n __Vtemp_5[3U] = 0U;\n VL_SHIFTL_WWI(128,128,7, __Vtemp_6, __Vtemp_5, (IData)(vlSelfRef.io_sel));\n __Vtemp_7[0U] = 1U;\n __Vtemp_7[1U] = 0U;\n __Vtemp_7[2U] = 0U;\n __Vtemp_7[3U] = 0U;\n // ... snip ...\n```\n\nand Then:\n\n\n```cpp\n __Vdeeptemp_h20de80fe__0 = (((0x00000400U & __Vtemp_20[0U])\n ? vlSelfRef.io_in_10\n : 0U) | (((0x00000800U \n & __Vtemp_22[0U])\n ? vlSelfRef.io_in_11\n : 0U) \n | (((0x00001000U \n & __Vtemp_24[0U])\n ? vlSelfRef.io_in_12\n : 0U) \n // ... snip ...\n```\n\nAs we can see, in Chisel 6.7.0, Verilator is able to optimize the Mux1H implementation into a simple array lookup, while in Chisel 7.3.0, Verilator generates a lot of shift operations and bitwise AND operations, which significantly increases the complexity of the generated code and leads to performance degradation during simulation.\n\nAs a result, let's look at the `analyze/chisel6.s` and `analyze/chisel7.s` files:\n\n```asm\nvoid VTest___024root___ico_sequent__TOP__0(VTest___024root* vlSelf) {\n b40:\t55 \tpush %rbp\n# ... snip ...\n 285c:\te9 01 ee ff ff \tjmp 1662 <_Z37VTest___024root___ico_sequent__TOP__0P15VTest___024root+0xb22>\n```\n\nThe code size is only `0x1d1c` bytes for Chisel 6.7.0, while for Chisel 7.3.0:\n\n```asm\nvoid VTest___024root___ico_sequent__TOP__0(VTest___024root* vlSelf) {\n b10:\t55 \tpush %rbp\n bbca:\teb b4 \tjmp bb80 <_Z37VTest___024root___ico_sequent__TOP__0P15VTest___024root+0xb070>\n```\n\nThe code size is `0xb0ba` bytes for Chisel 7.3.0, which is more then **6x** larger than Chisel 6.7.0.\n\nWhat 'verilator' command line do we use to run your example?\n\n```bash\nverilator --build -O3 --cc rtl/chisel6/Test.sv --CFLAGS \"-O3 -g\"\nverilator --build -O3 --cc rtl/chisel7/Test.sv --CFLAGS \"-O3 -g\"\n```\n\nWhat 'verilator --version' are you using? Did you try it with the git master version? Did you try it with other simulators?\n\nSelf-compiled from the recent master branch 18dd44e97.\n\nWhat OS and distribution are you using?\n\nDebian sid.\n\nMay we assist you in trying to fix this in Verilator yourself?\n\nYes!\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6822", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6822.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6822", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6822"} {"instance_id": "verilator_verilator_pr6823", "issue_text": "# Fix process reference giving no return statement error\n\n- Source URL: https://github.com/verilator/verilator/issues/6767\n\nThe below, rewritten from UVM tests/10resources/90Mantis/4666_no_process results in a compile-time error:\n\n```\nIn file included from Vt_0__ALL.cpp:4:\nVt_0___024root__0.cpp: In function â\\200\\230VlCoroutine Vt_0___024root___eval_initial__TOP__Vtiming__0(Vt_0___024root*, VlProcessRef)â\\200\\231:\nVt_0___024root__0.cpp:25:1: error: no return statement in function returning non-void [-Werror=return-type]\n```\n\n```\npackage uvm_pkg;\n class uvm_object;\n endclass\n\n class uvm_config_db;\n static uvm_object m_rsc[int];\n static function void set(int cntxt);\n if (!m_rsc.exists(cntxt)) begin\n m_rsc[cntxt] = new;\n end\n endfunction\n endclass\n\n virtual class uvm_process_guard_base extends uvm_object;\n protected process m_target_process;\n function new(string name);\n m_target_process = process::self();\n endfunction\n endclass\n\nendpackage\n\nmodule t;\n import uvm_pkg::*;\n int a;\n assign a = something();\n // verilator lint_off NORETURN\n function int something();\n uvm_config_db::set(1);\n return 0;\n endfunction\nendmodule\n```\n\nMight be related to #6106\n\n@RRozak et al, might you get a chance to look into this? Thanks.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6823", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6823.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6823", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6823"} {"instance_id": "verilator_verilator_pr6833", "issue_text": "# Fix member-selected variable must have randmode\n\n- Source URL: https://github.com/verilator/verilator/issues/6800\n\n@YilouWang thanks for last fix, alas the same uvm-test tests/70regs/80examples/01model/30nofield got further but now resulted in a new error:\n\n```\n%Error: Internal Error: t/t_0.v:41:31: ../V3Randomize.cpp:901: Member-selected variable must have randmode in its class\n 41 | constraint _dummy_is_reg {_dummy.value == value;}\n | ^~~~~~\n```\n\nRewritten test:\n\n```\npackage uvm_pkg;\n virtual class uvm_object;\n endclass\n\n class uvm_sequence_item;\n endclass\n\n virtual class uvm_sequencer_param_base;\n function void send_request(uvm_sequence_item t);\n uvm_sequence_item par;\n if (0 == par.randomize()) begin\n end\n endfunction\n endclass\n\n class uvm_reg_item extends uvm_sequence_item;\n rand uvm_object extension;\n endclass\n\n class uvm_reg_field extends uvm_object;\n rand int value;\n virtual function bit get_rand_mode();\n return bit'(value.rand_mode());\n endfunction\n endclass\n\nendpackage\n\nprogram t;\n import uvm_pkg::*;\n\n class reg_r extends uvm_object;\n rand int value;\n local rand uvm_reg_field _dummy;\n constraint _dummy_is_reg {_dummy.value == value;}\n endclass\n\n initial begin\n reg_r r;\n r = new;\n $finish;\n end\nendprogram\n```\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6833", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6833.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6833", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6833"} {"instance_id": "verilator_verilator_pr6842", "issue_text": "# Control file lint_off can be turned back on by source metacomment\n\n- Source URL: https://github.com/verilator/verilator/issues/6836\n\nGiven this `.vlt` file, one might expect there will be no FOO warnings from `file.sv` at all.\n\n```\n`verilator_config\nlint_off -rule FOO -file \"file.sv\"\n```\n\nHowever, if file.sv looks like this:\n\n```systemverilog\n int a;\n /* verilator lint_off FOO */\n int b;\n /* verilator lint_on FOO */\n int c;\n```\n\nThe `lint_on` in the code turns the warning back on for the rest of the lines following it, effectively ignoring the directive from the control file.\n\nDon't think this is intentional. Can we make the effect of the control files sticky? I suspect that needs a second bitset in the message enable sets that are only affected by the control file directives, which should be ok.\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6842", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6842.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6842", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6842"} {"instance_id": "verilator_verilator_pr6861", "issue_text": "# Support write to virtual interface in `if`\n\n- Source URL: https://github.com/verilator/verilator/issues/6558\n\nThe sv-tests easyUVM test is currently failing with this message:\n\n```\n%Error-UNSUPPORTED: sv-tests/third_party/tests/easyUVM/driver.sv:14:64: Unsupported: Write to virtual interface in if condition\n : ... note: In instance '$unit::driver'\n```\n\nThis can be recreated by running in a sv-test checkout:\n\n```\n$VERILATOR_ROOT/bin/verilator --binary -Wno-fatal third_party/tests/uvm/src/uvm_pkg.sv third_party/tests/easyUVM/top.sv -Ithird_party/tests/uvm/src -Ithird_party/tests/easyUVM\n```\n\nLooking at the code, if I simply comment out [the warning call in V3SchedVirtIface.cpp](https://github.com/verilator/verilator/blob/9dfc050fb508f350ebaa9db055ab7c33df73ec82/src/V3SchedVirtIface.cpp#L177) the test passes, but I don't know if the test is even testing the needed interface if.\n\n@kbieganski it looks like you gave a good amount of thought to the AstNodeIf visitor there, perhaps you could make a pull to support this?\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6861", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6861.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6861", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6861"} -{"instance_id": "verilator_verilator_pr6870", "issue_text": "# Support vpiSigned (#6868)\n\nInstance: verilator_verilator_pr6870\nSource: https://github.com/verilator/verilator/pull/6870\nFetched: 2026-05-03\nRepository: verilator/verilator\nPull request: #6870\nAuthor: ktbarrett\nState: closed\nBase branch: master\nHead branch: implement-vpiSigned\nCreated: 2025-12-29\nUpdated: 2025-12-30\nClosed: 2025-12-30\nMerged: 2025-12-30\n\n## PR Title\nSupport vpiSigned (#6868)\n\n## PR Description\nCloses issue #6868: implements the `vpiSigned` property on `vpiReg` and `vpiNet` objects so that callers can query whether a Verilog signal is signed via `vpi_get(vpiSigned, handle)`.\n\n## PR Comments\n**ktbarrett** (Dec 29, 2025): \"Closes #6868.\"\n\n**wsnyder** (Dec 29, 2025, title change): Renamed the PR title from \"Implement vpiSigned\" to \"Support vpiSigned (#6868)\".\n\n**wsnyder** (Dec 29, 2025, review): \"Great, exactly. Note there were CI test failures that need fixing (if you 'make format' and push they will be more obvious in the github web).\"\n\n**wsnyder** (Dec 29, 2025): \"BTW if you want this in the next release we'll need it by 12/30 (tomorrow).\"\n\n**ktbarrett** (Dec 29, 2025): \"Got a bit overzealous testing `vpi_get_str` which doesn't define a result on error.\"\n\nMerged on Dec 30, 2025 with 53 checks passed; included in Verilator 5.044 (released Jan 1, 2026).\n\n## Linked Issues\n**Issue #6868 - \"`vpiSigned` property not implemented\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"The `vpiSigned` property available on `vpiReg` and `vpiNet` objects is not implemented.\n\n```\nauto handle = vpi_handle_by_name(\\\"top.signal\\\", nullptr);\nint signed = vpi_get(vpiSigned, handle);\n```\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6870", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6870.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6870", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6870"} +{"instance_id": "verilator_verilator_pr6870", "issue_text": "# Support vpiSigned (#6868)\n\nInstance: verilator_verilator_pr6870\nSource: https://github.com/verilator/verilator/pull/6870\nFetched: 2026-05-03\nRepository: verilator/verilator\nPull request: #6870\nAuthor: ktbarrett\nState: closed\nBase branch: master\nHead branch: implement-vpiSigned\nCreated: 2025-12-29\nUpdated: 2025-12-30\nClosed: 2025-12-30\nMerged: 2025-12-30\n\n## PR Title\nSupport vpiSigned (#6868)\n\n## PR Description\nCloses issue #6868: implements the `vpiSigned` property on `vpiReg` and `vpiNet` objects so that callers can query whether a Verilog signal is signed via `vpi_get(vpiSigned, handle)`.\n\n## PR Comments\n**ktbarrett** (Dec 29, 2025): \"Closes #6868.\"\n\n**wsnyder** (Dec 29, 2025, title change): Renamed the PR title from \"Implement vpiSigned\" to \"Support vpiSigned (#6868)\".\n\n**wsnyder** (Dec 29, 2025, review): \"Great, exactly. Note there were CI test failures that need fixing (if you 'make format' and push they will be more obvious in the github web).\"\n\n**wsnyder** (Dec 29, 2025): \"BTW if you want this in the next release we'll need it by 12/30 (tomorrow).\"\n\n**ktbarrett** (Dec 29, 2025): \"Got a bit overzealous testing `vpi_get_str` which doesn't define a result on error.\"\n\nMerged on Dec 30, 2025 with 53 checks passed; included in Verilator 5.044 (released Jan 1, 2026).\n\n## Linked Issues\n**Issue #6868 - \"`vpiSigned` property not implemented\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"The `vpiSigned` property available on `vpiReg` and `vpiNet` objects is not implemented.\n\n```\nauto handle = vpi_handle_by_name(\\\"top.signal\\\", nullptr);\nint signed = vpi_get(vpiSigned, handle);\n```\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6870", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6870.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6870", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/verilator_verilator_pr6870"} {"instance_id": "verilator_verilator_pr6876", "issue_text": "# Config file for lint_off/on - selecting rules\n\n- Source URL: https://github.com/verilator/verilator/issues/4185\n\nI am trying to use Verilator with a subset of lint rules. Say I want only WIDTHEXPAND to be flagged. I create a .vlt file as below:\r\n\r\n```config\r\n\r\n`verilator_config\r\nlint_off \r\nlint_on -rule WIDTHEXPAND \r\n```\r\nBut I don't get any warning on a code as below:\r\n```verilog\r\nmodule m;\r\n wire [3:0] bits_4;\r\n wire [7:0] bits_8;\r\n assign bits_8 = bits_4;\r\nendmodule \r\n\r\n```\r\nIf I add a global lint_on as shown below, it works. \r\n```config\r\n\r\n`verilator_config\r\nlint_off \r\nlint_on -rule WIDTHEXPAND \r\nlint_on\r\n```\r\n\r\nLog:\r\n```log\r\n%Warning-WIDTHEXPAND: ../sv_tests/af_sv_mod.sv:6:17: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'bits_4' generates 4 bits.\r\n```\r\nSo my question is - how do I turn-off all rules and selectively enable a few?\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6876", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6876.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6876", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6876"} {"instance_id": "verilator_verilator_pr6882", "issue_text": "# Internal Error: ../V3Scope.cpp:69: Can't locate package scope\n\n- Source URL: https://github.com/verilator/verilator/issues/6741\n\nThanks for taking the time to report this.\n\nCan you please attach an example that shows the issue or missing feature? (Must be openly licensed, completely self-contained so can directly run what you provide. Ideally use test_regress format, see https://veripool.org/guide/latest/contributing.html?highlight=test_regress#reporting-bugs)\n\n```\nmodule tb_fifo_2in;\n parameter int unsigned DEPTH = 8;\n parameter int unsigned DATA_W = 32;\n parameter int unsigned RUN_CYCLES = 50_000;\n typedef logic [DATA_W-1:0] data_t;\n logic clk;\n logic full, not_full;\n logic enq0, enq1, deq;\n data_t enq0_data; \n data_t golden_queue[$];\n task automatic push(input data_t data, input string port);\n golden_queue.push_back(data);\n endtask\n class Transaction;\n rand bit enq0;\n rand bit enq1;\n rand bit deq;\n rand data_t enq0_data;\n constraint valid_enq {\n if (golden_queue.size() >= DEPTH) {\n enq0 == 0;\n enq1 == 0;\n } else if (golden_queue.size() == DEPTH-1) {\n\t(enq0 && enq1) == 0;\n }\n if (golden_queue.size() == 0) {\n deq == 0; \n }\n }\n endclass\n Transaction tr;\n initial begin\n tr = new();\n repeat (RUN_CYCLES) begin\n @(posedge clk);\n if (tr.randomize() == 0) begin\n $error(\"Randomization failed!\");\n break;\n end\n enq0 <= tr.enq0;\n deq <= tr.deq;\n enq0_data <= tr.enq0 ? tr.enq0_data : 'x;\n if (tr.enq0 && not_full) begin\n push(tr.enq0_data, \"P0\");\n end\n end\n $finish; \n end\n property p_full_flag;\n @(posedge clk) \n full == (golden_queue.size() == DEPTH);\n endproperty\nendmodule\n```\n\nWhat output from that test indicates it is wrong, and what is the correct or expected output? (Or, please make test self-checking if possible.)\n\n```\nverilator --binary test.sv\n%Error: Internal Error: test4.sv:20:11: ../V3Scope.cpp:69: Can't locate package scope\n : ... note: In instance 'tb_fifo_2in.Transaction'\n 20 | if (golden_queue.size() >= DEPTH) {\n | ^~~~~~~~~~~~\n ... See the manual at https://verilator.org/verilator_doc.html?v=5.043 for more assistance.\n```\n\nWhat 'verilator' command line do we use to run your example?\n\n```\nverilator --binary test.sv\n```\n\nWhat 'verilator --version' are you using? Did you try it with the git master version? Did you try it with other simulators?\n\n```\nVerilator 5.043 devel rev v5.042-110-gf2e05bc0b\n```\n\nWhat OS and distribution are you using?\n\n```\nLinux 5.14.0-570.37.1.el9_6.x86_64\n```\n\nMay we assist you in trying to fix this in Verilator yourself?\n\n(Please avoid attaching screenshots that show text - you can convert images to text using e.g. https://ocr.space)\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6882", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6882.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/verilator_verilator_pr6882", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6882"} {"instance_id": "wallento_wb2axi_pr4", "issue_text": "# Fix AxSIZE calculation\n\nInstance: wallento_wb2axi_pr4\nSource: https://github.com/wallento/wb2axi/pull/4\nFetched: 2026-05-03\nRepository: wallento/wb2axi\nPull request: #4\nAuthor: wallento\nState: closed\nBase branch: master\nHead branch: axsize\nCreated: 2019-05-24\nUpdated: 2019-05-25\nClosed: 2019-05-25\nMerged: 2019-05-25\n\n## PR Title\nFix AxSIZE calculation\n\n## PR Description\n\"Fixes #2\"\n\nThe change replaces the buggy `DATA_WIDTH >> 4` calculation for the AXI `AWSIZE`/`ARSIZE` registers with `$clog2(DATA_WIDTH)-3`, so the encoded transfer size is correct for data widths other than 32 bits.\n\n## PR Comments\n**wallento** (May 24, 2019): \"Fixes #2\"\n\nSingle commit (e44618a) with the same message. The branch `axsize` was deleted on May 25, 2019. No reviews, assignees, labels, or milestones.\n\n## Linked Issues\n**Issue #2 - \"Wrong AxSIZE\"** (closed by this PR).\n\nIssue body (verbatim from the source URL):\n\"The core defines the AXI AWSIZE and ARSIZE registers as the DATA_WIDTH >> 4. For the given data width of 32 bits, this would be 2, the correct answer. However, for a data width of 64, this would be 4--the wrong answer. Similarly for a data width of 16 bits, the data width should be 1, not 0.\n\nThe correct AxSIZE value should be $clog2(DATA_WIDTH)-3.\"\n", "issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/wallento_wb2axi_pr4", "developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/wallento_wb2axi_pr4.patch", "snapshot_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/snapshots/wallento_wb2axi_pr4", "testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/wallento_wb2axi_pr4"} diff --git a/patches/UTOSS_risc-v_pr81.patch b/patches/UTOSS_risc-v_pr81.patch index d39bf296f771d4dfa44f04df2040e17f20fd0dca..a775c42edd2c53e3a2a784ebc15e29f8395a9707 100644 --- a/patches/UTOSS_risc-v_pr81.patch +++ b/patches/UTOSS_risc-v_pr81.patch @@ -1,85 +1,111 @@ -From 32c1bf8887e80d34e3b2e44a338a5a42e81e2e5e Mon Sep 17 00:00:00 2001 -From: DanielTaoHuang123 -Date: Sun, 26 Oct 2025 05:49:58 -0400 -Subject: [PATCH 1/8] change MA to have 4 bit WE; fix sb/sh - ---- - src/ControlFSM.sv | 7 ++- - src/Instruction_Decode/MemoryLoader.sv | 78 +++++++++++++++++++++----- - src/top.v | 21 ++++--- - src/utils/MA.v | 9 +-- - 4 files changed, 86 insertions(+), 29 deletions(-) - diff --git a/src/ControlFSM.sv b/src/ControlFSM.sv -index 31bf453..a9692c4 100644 +index 37c1eda2..d41cced3 100644 --- a/src/ControlFSM.sv +++ b/src/ControlFSM.sv -@@ -9,12 +9,13 @@ module ControlFSM( - input wire clk, - input wire reset, - input wire zero_flag, -+ input wire [3:0] MemWriteByteAddress, - output adr_src_t AdrSrc, - output reg IRWrite, - output reg RegWrite, - output reg PCUpdate, - output pc_src_t pc_src, -- output reg MemWrite, -+ output reg [3:0] MemWrite, - output reg Branch, - output alu_src_a_t ALUSrcA, - output alu_src_b_t ALUSrcB, -@@ -115,7 +116,7 @@ module ControlFSM( - pc_src <= 1'b0; +@@ -9,12 +9,13 @@ module ControlFSM + , input wire clk + , input wire reset + , input wire zero_flag ++ , input wire [3:0] MemWriteByteAddress + , output adr_src_t AdrSrc + , output reg IRWrite + , output reg RegWrite + , output reg PCUpdate + , output pc_src_t pc_src +- , output reg MemWrite ++ , output reg [3:0] MemWrite + , output reg Branch + , output alu_src_a_t ALUSrcA + , output alu_src_b_t ALUSrcB +@@ -122,7 +123,7 @@ module ControlFSM + pc_src <= PC_SRC__INCREMENT; PCUpdate <= 1'b0; IRWrite <= 1'b0; - MemWrite <= 1'b0; + MemWrite <= 4'b0; - RegWrite <= 1'b0; + RegWrite <= 1'b0; - FSMState <= current_state; -@@ -211,7 +212,7 @@ module ControlFSM( + FSMState <= current_state; +@@ -236,7 +237,7 @@ module ControlFSM - ResultSrc <= RESULT_SRC__ALU_OUT; - AdrSrc <= ADR_SRC__RESULT; -- MemWrite <= 1'b1; -+ MemWrite <= MemWriteByteAddress; + ResultSrc <= RESULT_SRC__ALU_OUT; + AdrSrc <= ADR_SRC__RESULT; +- MemWrite <= 1'b1; ++ MemWrite <= MemWriteByteAddress; - end + end diff --git a/src/Instruction_Decode/MemoryLoader.sv b/src/Instruction_Decode/MemoryLoader.sv -index 45499ca..1fa66e1 100644 +index 578de14a..170e5f94 100644 --- a/src/Instruction_Decode/MemoryLoader.sv +++ b/src/Instruction_Decode/MemoryLoader.sv -@@ -1,8 +1,13 @@ +@@ -1,52 +1,107 @@ +`include "src/types.svh" + - module MemoryLoader ( - input data_t memory_data, - input addr_t memory_address, - input logic [2:0] funct3, -- output data_t mem_load_result -+ input logic [31:0] dataB, -+ output data_t mem_load_result, -+ output logic [3:0] MemWriteByteAddress, -+ output logic [31:0] __tmp_MemData - ); + module MemoryLoader +- ( input data_t memory_data +- , input addr_t memory_address +- , input logic [2:0] funct3 +- , output data_t mem_load_result +- ); ++( input data_t memory_data ++, input addr_t memory_address ++, input logic [2:0] funct3 ++, input logic [31:0] dataB ++, output data_t mem_load_result ++, output logic [3:0] MemWriteByteAddress ++, output logic [31:0] __tmp_MemData ++); integer byteindex; -@@ -10,27 +15,66 @@ module MemoryLoader ( + assign byteindex = memory_address[1:0]; - always_comb begin - case (funct3) -- 3'b000: begin // lb +- always_comb +- case (funct3) +- 3'b000: // lb +- case (byteindex) +- 2'd0: mem_load_result = {{24{memory_data[7]}} , memory_data[7:0]}; +- 2'd1: mem_load_result = {{24{memory_data[15]}}, memory_data[15:8]}; +- 2'd2: mem_load_result = {{24{memory_data[23]}}, memory_data[23:16]}; +- 2'd3: mem_load_result = {{24{memory_data[31]}}, memory_data[31:24]}; +- default: mem_load_result = 32'hX; +- endcase +- +- 3'b001: // lh +- case (byteindex) +- 2'd0: mem_load_result = {{16{memory_data[15]}}, memory_data[15:0]}; +- 2'd1: mem_load_result = {{16{memory_data[23]}}, memory_data[23:8]}; +- 2'd2: mem_load_result = {{16{memory_data[31]}}, memory_data[31:16]}; +- default: mem_load_result = 32'hX; +- endcase +- +- 3'b010: mem_load_result = memory_data; // lw +- +- 3'b100: // lbu +- case (byteindex) +- 2'd0: mem_load_result = {24'b0, memory_data[7:0]}; +- 2'd1: mem_load_result = {24'b0, memory_data[15:8]}; +- 2'd2: mem_load_result = {24'b0, memory_data[23:16]}; +- 2'd3: mem_load_result = {24'b0, memory_data[31:24]}; +- default: mem_load_result = 32'hX; +- endcase +- +- 3'b101: // lhu +- case (byteindex) +- 2'd0: mem_load_result = {16'b0, memory_data[15:0]}; +- 2'd1: mem_load_result = {16'b0, memory_data[23:8]}; +- 2'd2: mem_load_result = {16'b0, memory_data[31:16]}; +- default: mem_load_result = 32'hX; +- endcase +- +- default: mem_load_result = 32'hX; +- endcase ++ always @(*) begin ++ case (funct3) + 3'b000: begin // lb & sb - case (byteindex) -- 2'd0: mem_load_result = {{24{memory_data[7]}}, memory_data[7:0]}; -- 2'd1: mem_load_result = {{24{memory_data[15]}}, memory_data[15:8]}; -- 2'd2: mem_load_result = {{24{memory_data[23]}}, memory_data[23:16]}; -- 2'd3: mem_load_result = {{24{memory_data[31]}}, memory_data[31:24]}; -- default: mem_load_result = 32'hX; ++ case (byteindex) + 2'd0: begin -+ mem_load_result = {{24{memory_data[7]}}, memory_data[7:0]}; ++ mem_load_result = {{24{memory_data[7]}}, memory_data[7:0]}; + MemWriteByteAddress = 4'b0001; + __tmp_MemData = {24'b0, dataB[7:0]}; + end @@ -103,26 +129,22 @@ index 45499ca..1fa66e1 100644 + MemWriteByteAddress = 4'bx; + __tmp_MemData = 32'bx; + end - endcase - end - -- 3'b001: begin // lh ++ endcase ++ end ++ + 3'b001: begin // lh & sh - case (byteindex) -- 2'd0: mem_load_result = {{16{memory_data[15]}}, memory_data[15:0]}; -- 2'd1: mem_load_result = {{16{memory_data[23]}}, memory_data[23:8]}; -- 2'd2: mem_load_result = {{16{memory_data[31]}}, memory_data[31:16]}; -- default: mem_load_result = 32'hX; ++ case (byteindex) + 2'd0: begin + mem_load_result = {{16{memory_data[15]}}, memory_data[15:0]}; + MemWriteByteAddress = 4'b0011; + __tmp_MemData = {16'b0, dataB[15:0]}; + end -+ 2'd1: begin ++/* 2'd1: begin + mem_load_result = {{16{memory_data[23]}}, memory_data[23:8]}; + MemWriteByteAddress = 4'b0110; + __tmp_MemData = {8'b0, dataB[15:0], 8'b0}; -+ end ++ end*/ ++ // skip unaligned halfword access + 2'd2: begin + mem_load_result = {{16{memory_data[31]}}, memory_data[31:16]}; + MemWriteByteAddress = 4'b1100; @@ -133,309 +155,45 @@ index 45499ca..1fa66e1 100644 + MemWriteByteAddress = 4'bX; + __tmp_MemData = 32'bX; + end - endcase - end - -- 3'b010: mem_load_result = memory_data; // lw -- ++ endcase ++ end ++ + 3'b010: begin + mem_load_result = memory_data; // lw + MemWriteByteAddress = 4'b1111; //sw + __tmp_MemData = dataB; + end - 3'b100: begin // lbu - case (byteindex) - 2'd0: mem_load_result = {24'b0, memory_data[7:0]}; -@@ -50,7 +94,11 @@ module MemoryLoader ( - endcase - end - -- default: mem_load_result = 32'hX; ++ 3'b100: begin // lbu ++ case (byteindex) ++ 2'd0: mem_load_result = {24'b0, memory_data[7:0]}; ++ 2'd1: mem_load_result = {24'b0, memory_data[15:8]}; ++ 2'd2: mem_load_result = {24'b0, memory_data[23:16]}; ++ 2'd3: mem_load_result = {24'b0, memory_data[31:24]}; ++ default: mem_load_result = 32'hX; ++ endcase ++ end ++ ++ 3'b101: begin // lhu ++ case (byteindex) ++ 2'd0: mem_load_result = {16'b0, memory_data[15:0]}; ++ 2'd1: mem_load_result = {16'b0, memory_data[23:8]}; ++ 2'd2: mem_load_result = {16'b0, memory_data[31:16]}; ++ default: mem_load_result = 32'hX; ++ endcase ++ end ++ + default: begin + mem_load_result = 32'hX; + MemWriteByteAddress = 4'b0000; + __tmp_MemData = 31'bx; + end - endcase - end - -diff --git a/src/top.v b/src/top.v -index ee7f810..0d69b60 100644 ---- a/src/top.v -+++ b/src/top.v -@@ -38,8 +38,8 @@ module top #( parameter MEM_SIZE = 1024 ) - wire alu__zero_flag; - - adr_src_t cfsm__adr_src; -- wire __tmp_MemWrite -- , __tmp_Branch; -+ wire [3:0] __tmp_MemWrite; -+ wire __tmp_Branch; - wire [1:0] __tmp_ALUSrcA - , __tmp_ALUSrcB; - wire [2:0] __tmp_ALUOp; -@@ -49,11 +49,15 @@ module top #( parameter MEM_SIZE = 1024 ) - logic [31:0] dataA - ,dataB; - -+ logic [3:0] MemWriteByteAddress; -+ logic [31:0] __tmp_MemData; -+ - ControlFSM control_fsm - ( .opcode ( opcode ) - , .clk ( clk ) - , .reset ( reset ) - , .zero_flag ( alu__zero_flag ) -+ , .MemWriteByteAddress ( MemWriteByteAddress ) - , .AdrSrc ( cfsm__adr_src ) - , .IRWrite ( cfsm__ir_write ) - , .RegWrite ( cfsm__reg_write ) -@@ -91,7 +95,7 @@ module top #( parameter MEM_SIZE = 1024 ) - MA #( .SIZE ( MEM_SIZE ) ) - memory // instructions and data - ( .A ( memory_address ) -- , .WD ( dataB ) -+ , .WD ( __tmp_MemData ) - , .WE ( __tmp_MemWrite ) - , .CLK ( clk ) - -@@ -106,10 +110,13 @@ module top #( parameter MEM_SIZE = 1024 ) - end - - MemoryLoader MemLoad -- ( .memory_data ( memory_data ) -- , .memory_address ( memory_address ) -- , .mem_load_result ( mem_load_result ) -- , .funct3 ( funct3 ) -+ ( .memory_data ( memory_data ) -+ , .memory_address ( memory_address ) -+ , .mem_load_result ( mem_load_result ) -+ , .funct3 ( funct3 ) -+ , .dataB ( dataB ) -+ , .MemWriteByteAddress ( MemWriteByteAddress) -+ , .__tmp_MemData ( __tmp_MemData ) - ); - - always @(posedge clk) begin -diff --git a/src/utils/MA.v b/src/utils/MA.v -index a47036c..dafb7e1 100644 ---- a/src/utils/MA.v -+++ b/src/utils/MA.v -@@ -1,7 +1,7 @@ - module MA #( parameter SIZE = 1024 ) - ( input [31:0] A - , input [31:0] WD -- , input WE -+ , input [3:0] WE //changed from 1 bit WE to 4 bit to address byteindex - , input CLK - , output [31:0] RD - ); -@@ -21,9 +21,10 @@ module MA #( parameter SIZE = 1024 ) - assign RD = M[A[31:2]]; // 2 LSBs used for byte addressing - - always @(posedge CLK) begin -- if (WE) begin -- M[A[31:2]] <= WD; -- end -+ if (WE[0]) M[A[31:2]][7:0] <= WD[7:0]; -+ if (WE[1]) M[A[31:2]][15:8] <= WD[15:8]; -+ if (WE[2]) M[A[31:2]][23:16] <= WD[23:16]; -+ if (WE[3]) M[A[31:2]][31:24] <= WD[31:24]; - end - - endmodule - -From 3c8e055cd03a2987f81c1d514f0166cdd3516d4b Mon Sep 17 00:00:00 2001 -From: DanielTaoHuang123 -Date: Tue, 28 Oct 2025 22:42:53 -0400 -Subject: [PATCH 2/8] skip unaligned halfword store/load specify the datatype - of pc_src when assigning values in FSM - ---- - src/ControlFSM.sv | 4 ++-- - src/Instruction_Decode/MemoryLoader.sv | 4 ++-- - 2 files changed, 4 insertions(+), 4 deletions(-) - -diff --git a/src/ControlFSM.sv b/src/ControlFSM.sv -index a9692c4..7c4011e 100644 ---- a/src/ControlFSM.sv -+++ b/src/ControlFSM.sv -@@ -113,7 +113,7 @@ module ControlFSM( - //output logic - always@(*) begin - Branch <= 1'b0; -- pc_src <= 1'b0; -+ pc_src <= pc_src_t'(1'b0); - PCUpdate <= 1'b0; - IRWrite <= 1'b0; - MemWrite <= 4'b0; -@@ -196,7 +196,7 @@ module ControlFSM( - ALUOp <= 2'b01; - ResultSrc <= RESULT_SRC__ALU_OUT; - Branch <= 1'b1; -- pc_src <= zero_flag ? PC_SRC__JUMP : PC_SRC__INCREMENT; -+ pc_src <= pc_src_t'(zero_flag ? PC_SRC__JUMP : PC_SRC__INCREMENT); - PCUpdate <= 1'b1; - - end -diff --git a/src/Instruction_Decode/MemoryLoader.sv b/src/Instruction_Decode/MemoryLoader.sv -index 1fa66e1..a3aab7a 100644 ---- a/src/Instruction_Decode/MemoryLoader.sv -+++ b/src/Instruction_Decode/MemoryLoader.sv -@@ -52,11 +52,11 @@ module MemoryLoader ( - MemWriteByteAddress = 4'b0011; - __tmp_MemData = {16'b0, dataB[15:0]}; - end -- 2'd1: begin -+/* 2'd1: begin - mem_load_result = {{16{memory_data[23]}}, memory_data[23:8]}; - MemWriteByteAddress = 4'b0110; - __tmp_MemData = {8'b0, dataB[15:0], 8'b0}; -- end -+ end*/ - 2'd2: begin - mem_load_result = {{16{memory_data[31]}}, memory_data[31:16]}; - MemWriteByteAddress = 4'b1100; - -From 9b7b2dd957e5d0355da95953093b741b4936bf65 Mon Sep 17 00:00:00 2001 -From: DanielTaoHuang123 -Date: Sun, 2 Nov 2025 11:51:25 -0500 -Subject: [PATCH 3/8] fix some svlint error - ---- - src/ControlFSM.sv | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - -diff --git a/src/ControlFSM.sv b/src/ControlFSM.sv -index cede0f6..e7c13ca 100644 ---- a/src/ControlFSM.sv -+++ b/src/ControlFSM.sv -@@ -235,9 +235,9 @@ module ControlFSM - - MEMWRITE: begin - -- ResultSrc <= RESULT_SRC__ALU_OUT; -- AdrSrc <= ADR_SRC__RESULT; -- MemWrite <= MemWriteByteAddress; -+ ResultSrc <= RESULT_SRC__ALU_OUT; -+ AdrSrc <= ADR_SRC__RESULT; -+ MemWrite <= MemWriteByteAddress; - - end - - -From 0d04594dafac1698d7df9344aeb96dcb3abc1508 Mon Sep 17 00:00:00 2001 -From: DanielTaoHuang123 -Date: Sun, 2 Nov 2025 12:16:14 -0500 -Subject: [PATCH 4/8] fix svlint error; - ---- - src/Instruction_Decode/MemoryLoader.sv | 19 ++++++++++--------- - 1 file changed, 10 insertions(+), 9 deletions(-) - -diff --git a/src/Instruction_Decode/MemoryLoader.sv b/src/Instruction_Decode/MemoryLoader.sv -index a3aab7a..ac59979 100644 ---- a/src/Instruction_Decode/MemoryLoader.sv -+++ b/src/Instruction_Decode/MemoryLoader.sv -@@ -1,20 +1,20 @@ - `include "src/types.svh" - - module MemoryLoader ( -- input data_t memory_data, -- input addr_t memory_address, -- input logic [2:0] funct3, -- input logic [31:0] dataB, -- output data_t mem_load_result, -- output logic [3:0] MemWriteByteAddress, -+ input data_t memory_data, -+ input addr_t memory_address, -+ input logic [2:0] funct3, -+ input logic [31:0] dataB, -+ output data_t mem_load_result, -+ output logic [3:0] MemWriteByteAddress, - output logic [31:0] __tmp_MemData - ); - - integer byteindex; - assign byteindex = memory_address[1:0]; - -- always_comb begin -- case (funct3) -+ always_comb -+ case (funct3) - 3'b000: begin // lb & sb - case (byteindex) - 2'd0: begin -@@ -57,6 +57,7 @@ module MemoryLoader ( - MemWriteByteAddress = 4'b0110; - __tmp_MemData = {8'b0, dataB[15:0], 8'b0}; - end*/ -+ // skip unaligned halfword access - 2'd2: begin - mem_load_result = {{16{memory_data[31]}}, memory_data[31:16]}; - MemWriteByteAddress = 4'b1100; -@@ -100,6 +101,6 @@ module MemoryLoader ( - __tmp_MemData = 31'bx; - end - endcase -- end -+ - - endmodule - -From 070822bb487f7533a7624c785c21fb6a5bf39dc1 Mon Sep 17 00:00:00 2001 -From: DanielTaoHuang123 -Date: Sun, 2 Nov 2025 12:27:23 -0500 -Subject: [PATCH 5/8] try to change increment to fix svlint error - ---- - src/Instruction_Decode/MemoryLoader.sv | 18 ++--- - src/Instruction_Decode/RegisterFile.v | 92 +++++++++++++------------- - 2 files changed, 55 insertions(+), 55 deletions(-) - -diff --git a/src/Instruction_Decode/MemoryLoader.sv b/src/Instruction_Decode/MemoryLoader.sv -index ac59979..70d34fe 100644 ---- a/src/Instruction_Decode/MemoryLoader.sv -+++ b/src/Instruction_Decode/MemoryLoader.sv -@@ -1,20 +1,20 @@ - `include "src/types.svh" - - module MemoryLoader ( -- input data_t memory_data, -- input addr_t memory_address, -- input logic [2:0] funct3, -- input logic [31:0] dataB, -- output data_t mem_load_result, -- output logic [3:0] MemWriteByteAddress, -+ input data_t memory_data, -+ input addr_t memory_address, -+ input logic [2:0] funct3, -+ input logic [31:0] dataB, -+ output data_t mem_load_result, -+ output logic [3:0] MemWriteByteAddress, - output logic [31:0] __tmp_MemData - ); - - integer byteindex; - assign byteindex = memory_address[1:0]; - -- always_comb -- case (funct3) -+ always_comb -+ case (funct3) - 3'b000: begin // lb & sb - case (byteindex) - 2'd0: begin -@@ -101,6 +101,6 @@ module MemoryLoader ( - __tmp_MemData = 31'bx; - end - endcase -- ++ endcase ++ end + endmodule diff --git a/src/Instruction_Decode/RegisterFile.v b/src/Instruction_Decode/RegisterFile.v -index f8fabcb..15c7854 100644 +index f8fabcb1..15c78547 100644 --- a/src/Instruction_Decode/RegisterFile.v +++ b/src/Instruction_Decode/RegisterFile.v @@ -1,46 +1,46 @@ @@ -531,124 +289,80 @@ index f8fabcb..15c7854 100644 + end + +endmodule - -From bba571da6d6417bd082710e0fa1831da93624174 Mon Sep 17 00:00:00 2001 -From: DanielTaoHuang123 -Date: Sun, 2 Nov 2025 12:33:37 -0500 -Subject: [PATCH 6/8] fix svlint errors - ---- - src/Instruction_Decode/MemoryLoader.sv | 17 +++++++++-------- - 1 file changed, 9 insertions(+), 8 deletions(-) - -diff --git a/src/Instruction_Decode/MemoryLoader.sv b/src/Instruction_Decode/MemoryLoader.sv -index 70d34fe..4ebb286 100644 ---- a/src/Instruction_Decode/MemoryLoader.sv -+++ b/src/Instruction_Decode/MemoryLoader.sv -@@ -1,24 +1,24 @@ - `include "src/types.svh" - - module MemoryLoader ( -- input data_t memory_data, -- input addr_t memory_address, -- input logic [2:0] funct3, -- input logic [31:0] dataB, -- output data_t mem_load_result, -- output logic [3:0] MemWriteByteAddress, -+ input data_t memory_data, -+ input addr_t memory_address, -+ input logic [2:0] funct3, -+ input logic [31:0] dataB, -+ output data_t mem_load_result, -+ output logic [3:0] MemWriteByteAddress, - output logic [31:0] __tmp_MemData - ); - - integer byteindex; - assign byteindex = memory_address[1:0]; - -- always_comb -+ always@(*) begin - case (funct3) - 3'b000: begin // lb & sb - case (byteindex) - 2'd0: begin -- mem_load_result = {{24{memory_data[7]}}, memory_data[7:0]}; -+ mem_load_result = {{24{memory_data[7]}}, memory_data[7:0]}; - MemWriteByteAddress = 4'b0001; - __tmp_MemData = {24'b0, dataB[7:0]}; - end -@@ -101,6 +101,7 @@ module MemoryLoader ( - __tmp_MemData = 31'bx; - end - endcase -+ end +diff --git a/src/top.v b/src/top.v +index 20a0ff8b..48a84e00 100644 +--- a/src/top.v ++++ b/src/top.v +@@ -38,7 +38,8 @@ module top #( parameter MEM_SIZE = 1024 ) + wire alu__zero_flag; + adr_src_t cfsm__adr_src; +- wire __tmp_MemWrite, __tmp_Branch; ++ wire [3:0] __tmp_MemWrite; ++ wire __tmp_Branch; + wire [1:0] __tmp_ALUSrcA, __tmp_ALUSrcB; + wire [2:0] __tmp_ALUOp; + wire [3:0] __tmp_ALUControl; +@@ -47,11 +48,15 @@ module top #( parameter MEM_SIZE = 1024 ) + data_t dataA, dataB; + reg [4:0] rd, rs1, rs2; - endmodule - -From dd595584cc60a39154113fd3c68940c626d1dd83 Mon Sep 17 00:00:00 2001 -From: DanielTaoHuang123 -Date: Sun, 2 Nov 2025 12:43:53 -0500 -Subject: [PATCH 7/8] fixing indentation - ---- - src/Instruction_Decode/MemoryLoader.sv | 18 +++++++++--------- - src/utils/MA.v | 24 +++++++++++++----------- - 2 files changed, 22 insertions(+), 20 deletions(-) - -diff --git a/src/Instruction_Decode/MemoryLoader.sv b/src/Instruction_Decode/MemoryLoader.sv -index 4ebb286..9489e03 100644 ---- a/src/Instruction_Decode/MemoryLoader.sv -+++ b/src/Instruction_Decode/MemoryLoader.sv -@@ -1,19 +1,19 @@ - `include "src/types.svh" ++ logic [3:0] MemWriteByteAddress; ++ logic [31:0] __tmp_MemData; ++ + ControlFSM control_fsm + ( .opcode ( opcode ) + , .clk ( clk ) + , .reset ( reset ) + , .zero_flag ( alu__zero_flag ) ++ , .MemWriteByteAddress ( MemWriteByteAddress ) + , .AdrSrc ( cfsm__adr_src ) + , .IRWrite ( cfsm__ir_write ) + , .RegWrite ( cfsm__reg_write ) +@@ -90,7 +95,7 @@ module top #( parameter MEM_SIZE = 1024 ) + MA #( .SIZE ( MEM_SIZE ) ) + memory // instructions and data + ( .A ( memory_address ) +- , .WD ( dataB ) ++ , .WD ( __tmp_MemData ) + , .WE ( __tmp_MemWrite ) + , .CLK ( clk ) --module MemoryLoader ( -- input data_t memory_data, -- input addr_t memory_address, -- input logic [2:0] funct3, -- input logic [31:0] dataB, -- output data_t mem_load_result, -- output logic [3:0] MemWriteByteAddress, -- output logic [31:0] __tmp_MemData -+module MemoryLoader -+( input data_t memory_data -+, input addr_t memory_address -+, input logic [2:0] funct3 -+, input logic [31:0] dataB -+, output data_t mem_load_result -+, output logic [3:0] MemWriteByteAddress -+, output logic [31:0] __tmp_MemData - ); +@@ -105,10 +110,13 @@ module top #( parameter MEM_SIZE = 1024 ) + end - integer byteindex; - assign byteindex = memory_address[1:0]; + MemoryLoader MemLoad +- ( .memory_data ( memory_data ) +- , .memory_address ( memory_address ) +- , .mem_load_result ( mem_load_result ) +- , .funct3 ( funct3 ) ++ ( .memory_data ( memory_data ) ++ , .memory_address ( memory_address ) ++ , .mem_load_result ( mem_load_result ) ++ , .funct3 ( funct3 ) ++ , .dataB ( dataB ) ++ , .MemWriteByteAddress ( MemWriteByteAddress) ++ , .__tmp_MemData ( __tmp_MemData ) + ); -- always@(*) begin -+ always @(*) begin - case (funct3) - 3'b000: begin // lb & sb - case (byteindex) + always @(posedge clk) begin diff --git a/src/utils/MA.v b/src/utils/MA.v -index a3c988f..13ab49e 100644 +index 07209235..d6282dde 100644 --- a/src/utils/MA.v +++ b/src/utils/MA.v -@@ -1,16 +1,18 @@ +@@ -1,16 +1,16 @@ -module MA #( parameter SIZE = 1024 ) -- ( input [31:0] A -- , input [31:0] WD -- , input [3:0] WE //changed from 1 bit WE to 4 bit to address byteindex -- , input wire CLK -- , output [31:0] RD -- ); -+module MA #( -+ parameter SIZE = 1024 -+) -+( -+ input [31:0] A +- ( input [31:0] A +- , input [31:0] WD +- , input wire WE +- , input wire CLK +- , output [31:0] RD +- ); ++module MA #(parameter SIZE = 1024) ++( input [31:0] A +, input [31:0] WD -+, input [3:0] WE //changed from 1 bit WE to 4 bit to address byteindex ++, input [3:0] WE ++//changed from 1 bit WE to 4 bit to address byteindex +, input wire CLK +, output [31:0] RD +); @@ -664,59 +378,17 @@ index a3c988f..13ab49e 100644 if ($value$plusargs("MEM=%s", mem_file)) begin $display("loading memory from <%s>", mem_file); - -From 73805f922ab826a660093f4b7f20229649db8330 Mon Sep 17 00:00:00 2001 -From: DanielTaoHuang123 -Date: Sun, 2 Nov 2025 12:51:43 -0500 -Subject: [PATCH 8/8] fix trailing white spaces - ---- - src/ControlFSM.sv | 2 +- - src/Instruction_Decode/MemoryLoader.sv | 2 +- - src/utils/MA.v | 10 ++++------ - 3 files changed, 6 insertions(+), 8 deletions(-) - -diff --git a/src/ControlFSM.sv b/src/ControlFSM.sv -index e7c13ca..d41cced 100644 ---- a/src/ControlFSM.sv -+++ b/src/ControlFSM.sv -@@ -15,7 +15,7 @@ module ControlFSM - , output reg RegWrite - , output reg PCUpdate - , output pc_src_t pc_src -- , output reg [3:0] MemWrite -+ , output reg [3:0] MemWrite - , output reg Branch - , output alu_src_a_t ALUSrcA - , output alu_src_b_t ALUSrcB -diff --git a/src/Instruction_Decode/MemoryLoader.sv b/src/Instruction_Decode/MemoryLoader.sv -index 9489e03..170e5f9 100644 ---- a/src/Instruction_Decode/MemoryLoader.sv -+++ b/src/Instruction_Decode/MemoryLoader.sv -@@ -1,6 +1,6 @@ - `include "src/types.svh" +@@ -21,9 +21,10 @@ module MA #( parameter SIZE = 1024 ) --module MemoryLoader -+module MemoryLoader - ( input data_t memory_data - , input addr_t memory_address - , input logic [2:0] funct3 -diff --git a/src/utils/MA.v b/src/utils/MA.v -index 13ab49e..d6282dd 100644 ---- a/src/utils/MA.v -+++ b/src/utils/MA.v -@@ -1,10 +1,8 @@ --module MA #( -- parameter SIZE = 1024 --) --( -- input [31:0] A -+module MA #(parameter SIZE = 1024) -+( input [31:0] A - , input [31:0] WD --, input [3:0] WE //changed from 1 bit WE to 4 bit to address byteindex -+, input [3:0] WE -+//changed from 1 bit WE to 4 bit to address byteindex - , input wire CLK - , output [31:0] RD - ); + assign RD = M[A[31:2]]; // 2 LSBs used for byte addressing + always @(posedge CLK) begin +- if (WE) begin +- M[A[31:2]] <= WD; +- end ++ if (WE[0]) M[A[31:2]][7:0] <= WD[7:0]; ++ if (WE[1]) M[A[31:2]][15:8] <= WD[15:8]; ++ if (WE[2]) M[A[31:2]][23:16] <= WD[23:16]; ++ if (WE[3]) M[A[31:2]][31:24] <= WD[31:24]; + end + + endmodule diff --git a/patches/pulp-platform_common_cells_pr188.patch b/patches/pulp-platform_common_cells_pr188.patch index a0d1cfe5d88a074f0d351cd5c470b40895988a5c..8d1f5ec8c84f47c8e270abd348fffde20d479036 100644 --- a/patches/pulp-platform_common_cells_pr188.patch +++ b/patches/pulp-platform_common_cells_pr188.patch @@ -30,7 +30,7 @@ index c38e8d2f..1e4fe299 100644 + module popcount #( -- parameter int unsigned INPUT_WIDTH = 256, +- parameter int unsigned INPUT_WIDTH = 1, - localparam int unsigned PopcountWidth = $clog2(INPUT_WIDTH)+1 + parameter int unsigned INPUT_WIDTH = 256, + localparam int unsigned PopcountWidth = $clog2(INPUT_WIDTH) + 1 diff --git a/patches/pulp-platform_register_interface_pr32.patch b/patches/pulp-platform_register_interface_pr32.patch index 28c0b3113a0d88ed2f045008c0ff8e04afab41e7..5653b7d26430caf461dda9bfb9b5394d1e52c83c 100644 --- a/patches/pulp-platform_register_interface_pr32.patch +++ b/patches/pulp-platform_register_interface_pr32.patch @@ -73,7 +73,7 @@ index 0000000..472985c +); + + always_comb begin -+ out_req_o = out_req_i; ++ out_req_o = in_req_i; + in_rsp_o = out_rsp_i; + + if (in_req_i.valid && in_req_i.we && in_req_i.strb == '0) begin diff --git a/patches/pulp-platform_riscv-dbg_pr123.patch b/patches/pulp-platform_riscv-dbg_pr123.patch index 20640c6e57f13b9067bdc46ae9c71331db0f0105..1f7f2de6e16f8c08852d4701af3934c3c0ddc334 100644 --- a/patches/pulp-platform_riscv-dbg_pr123.patch +++ b/patches/pulp-platform_riscv-dbg_pr123.patch @@ -1,21 +1,38 @@ -From faa6ccd06100cf4f855ffe8562d55044f998db5e Mon Sep 17 00:00:00 2001 -From: Manuel Eggimann -Date: Thu, 6 Jan 2022 19:10:42 +0100 -Subject: [PATCH 01/11] First draft of dmihardreset support and proper warm - reset capability - ---- - doc/debug-system.md | 1 - - src/dmi_cdc.sv | 54 +++++++----- - src/dmi_jtag.sv | 203 +++++++++++++++++++++++--------------------- - src/dmi_jtag_tap.sv | 7 +- - 4 files changed, 144 insertions(+), 121 deletions(-) - -diff --git a/doc/debug-system.md b/doc/debug-system.md -index b025f89..1beca7d 100644 +--- a/Bender.yml ++++ b/Bender.yml +@@ -10,7 +10,7 @@ + + dependencies: + tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } +- common_cells: {git: https://github.com/pulp-platform/common_cells.git, version: 1.21.0} ++ common_cells: {git: "https://github.com/pulp-platform/common_cells.git", version: 1.24.0} + + sources: + files: +--- a/CHANGELOG.md ++++ b/CHANGELOG.md +@@ -8,11 +8,18 @@ + ### Added + - Add sbaccess8 and sbaccess16 support (#106) [@noytzach](https://github.com/noytzach) + - Implement SBA bad address error (#12) [@msfchaffner](https://github.com/msfschaffner) ++- Added random reset tests to dmi testbench. + ### Changed ++- Implement `dmihardreset` functionaliy in `dtmcs` register. ++- `dmi_rst_ni` of `dm_top` is now a synchronous signal. However, `dmi_rst_no` of ++ `dmi_jtag` is glitch-free and asserted during all forms (functional or POR) of ++ resets. + ### Fixed + - Fixed documentation (csr) + - Fixed reset value of sbcs register (#127) [@msfchaffner](https://github.com/msfschaffner) + - Fixed various ascent lint warnings [@msfchaffner](https://github.com/msfschaffner) ++- Implement proper CDC flushing behavior on functional resets and JTAG resets (asynchronous or TestLogicReset driven). ++- Fix JTAG non-compliance in TestLogicReset state (IR should reset to IDCODE). + + ## [0.4.1] - 2021-05-04 + ### Added --- a/doc/debug-system.md +++ b/doc/debug-system.md -@@ -485,7 +485,6 @@ default the IR register is 5 bits long, but the implementation is parameterized. +@@ -485,7 +485,6 @@ ) ( ``` - `DTMCSR`: RISC-V specific control and status register of the JTAG DMI. @@ -23,16 +40,39 @@ index b025f89..1beca7d 100644 - `DMIACCESS`: Access the debug module's register. - `abits+33:34`: Address - `33:2`: Data -diff --git a/src/dmi_cdc.sv b/src/dmi_cdc.sv -index 4665c91..d9e9363 100644 +--- a/src/dm_csrs.sv ++++ b/src/dm_csrs.sv +@@ -23,7 +23,8 @@ + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + input logic testmode_i, +- input logic dmi_rst_ni, // Debug Module Intf reset active-low ++ input logic dmi_rst_ni, // sync. DTM reset, ++ // active-low + input logic dmi_req_valid_i, + output logic dmi_req_ready_o, + input dm::dmi_req_t dmi_req_i, +@@ -559,9 +560,10 @@ + .dtype ( logic [31:0] ), + .DEPTH ( 2 ) + ) i_fifo ( +- .clk_i ( clk_i ), +- .rst_ni ( dmi_rst_ni ), // reset only when system is re-set +- .flush_i ( 1'b0 ), // we do not need to flush this queue ++ .clk_i, ++ .rst_ni, ++ .flush_i ( ~dmi_rst_ni ), // Flush the queue if the DTM is ++ // reset + .testmode_i ( testmode_i ), + .full_o ( resp_queue_full ), + .empty_o ( resp_queue_empty ), --- a/src/dmi_cdc.sv +++ b/src/dmi_cdc.sv -@@ -19,11 +19,13 @@ - module dmi_cdc ( +@@ -20,10 +20,12 @@ // JTAG side (master side) input logic tck_i, -- input logic trst_ni, - + input logic trst_ni, +- input dm::dmi_req_t jtag_dmi_req_i, output logic jtag_dmi_ready_o, input logic jtag_dmi_valid_i, @@ -42,7 +82,15 @@ index 4665c91..d9e9363 100644 output dm::dmi_resp_t jtag_dmi_resp_o, output logic jtag_dmi_valid_o, -@@ -42,32 +44,40 @@ module dmi_cdc ( +@@ -33,6 +35,7 @@ + input logic clk_i, + input logic rst_ni, + ++ output logic core_dmi_rst_no, + output dm::dmi_req_t core_dmi_req_o, + output logic core_dmi_valid_o, + input logic core_dmi_ready_i, +@@ -42,32 +45,70 @@ input logic core_dmi_valid_i ); @@ -52,17 +100,19 @@ index 4665c91..d9e9363 100644 - .src_data_i ( jtag_dmi_req_i ), - .src_valid_i ( jtag_dmi_valid_i ), - .src_ready_o ( jtag_dmi_ready_o ), - +- - .dst_rst_ni ( rst_ni ), - .dst_clk_i ( clk_i ), - .dst_data_o ( core_dmi_req_o ), - .dst_valid_o ( core_dmi_valid_o ), - .dst_ready_i ( core_dmi_ready_i ) ++ logic core_clear_pending; + + cdc_2phase_clearable #(.T(dm::dmi_req_t)) i_cdc_req ( -+ .src_rst_ni ( rst_ni ), -+ .src_clear_i ( jtag_dmi_cdc_clear_i ) ++ .src_rst_ni ( trst_ni ), ++ .src_clear_i ( jtag_dmi_cdc_clear_i ), + .src_clk_i ( tck_i ), ++ .src_clear_pending_o(), // Not used + .src_data_i ( jtag_dmi_req_i ), + .src_valid_i ( jtag_dmi_valid_i ), + .src_ready_o ( jtag_dmi_ready_o ), @@ -70,45 +120,85 @@ index 4665c91..d9e9363 100644 + .dst_rst_ni ( rst_ni ), + .dst_clear_i ( 1'b0 ), // No functional reset from core side + // used (only async). ++ .dst_clear_pending_o( core_clear_pending ), // use the clear pending signal ++ // to synchronously clear the ++ // response FIFO in the dm_top ++ // csrs + .dst_clk_i ( clk_i ), + .dst_data_o ( core_dmi_req_o ), + .dst_valid_o ( core_dmi_valid_o ), + .dst_ready_i ( core_dmi_ready_i ) ); - cdc_2phase #(.T(dm::dmi_resp_t)) i_cdc_resp ( +- cdc_2phase #(.T(dm::dmi_resp_t)) i_cdc_resp ( - .src_rst_ni ( rst_ni ), - .src_clk_i ( clk_i ), - .src_data_i ( core_dmi_resp_i ), - .src_valid_i ( core_dmi_valid_i ), - .src_ready_o ( core_dmi_ready_o ), +- +- .dst_rst_ni ( trst_ni ), +- .dst_clk_i ( tck_i ), +- .dst_data_o ( jtag_dmi_resp_o ), +- .dst_valid_o ( jtag_dmi_valid_o ), +- .dst_ready_i ( jtag_dmi_ready_i ) ++ cdc_2phase_clearable #(.T(dm::dmi_resp_t)) i_cdc_resp ( + .src_rst_ni ( rst_ni ), + .src_clear_i ( 1'b0 ), // No functional reset from core side + // used (only async ). ++ .src_clear_pending_o(), // Not used + .src_clk_i ( clk_i ), + .src_data_i ( core_dmi_resp_i ), + .src_valid_i ( core_dmi_valid_i ), + .src_ready_o ( core_dmi_ready_o ), - -- .dst_rst_ni ( trst_ni ), -- .dst_clk_i ( tck_i ), -- .dst_data_o ( jtag_dmi_resp_o ), -- .dst_valid_o ( jtag_dmi_valid_o ), -- .dst_ready_i ( jtag_dmi_ready_i ) ++ + .dst_rst_ni ( trst_ni ), + .dst_clear_i ( jtag_dmi_cdc_clear_i ), ++ .dst_clear_pending_o(), //Not used + .dst_clk_i ( tck_i ), + .dst_data_o ( jtag_dmi_resp_o ), + .dst_valid_o ( jtag_dmi_valid_o ), + .dst_ready_i ( jtag_dmi_ready_i ) ); ++ // We need to flush the DMI response FIFO in DM top using the core clock ++ // synchronous clear signal core_dmi_rst_no. We repurpose the clear ++ // pending signal in the core clock domain by generating a 1 cycle pulse from ++ // it. ++ ++ logic core_clear_pending_q; ++ logic core_dmi_rst_nq; ++ logic clear_pending_rise_edge_detect; ++ ++ assign clear_pending_rise_edge_detect = !core_clear_pending_q && core_clear_pending; ++ ++ always_ff @(posedge clk_i, negedge rst_ni) begin ++ if (!rst_ni) begin ++ core_dmi_rst_nq <= 1'b1; ++ core_clear_pending_q <= 1'b0; ++ end else begin ++ core_dmi_rst_nq <= ~clear_pending_rise_edge_detect; // active-low! ++ core_clear_pending_q <= core_clear_pending; ++ end ++ end ++ ++ assign core_dmi_rst_no = core_dmi_rst_nq; ++ endmodule : dmi_cdc -diff --git a/src/dmi_jtag.sv b/src/dmi_jtag.sv -index 70ee776..04414e6 100644 --- a/src/dmi_jtag.sv +++ b/src/dmi_jtag.sv -@@ -47,12 +47,16 @@ module dmi_jtag #( +@@ -23,7 +23,9 @@ + input logic rst_ni, // Asynchronous reset active low + input logic testmode_i, + +- output logic dmi_rst_no, // hard reset ++ // active-low glitch free reset signal. Is asserted for one dmi clock cycle ++ // (clk_i) whenever the dmi_jtag is reset (POR or functional reset). ++ output logic dmi_rst_no, + output dm::dmi_req_t dmi_req_o, + output logic dmi_req_valid_o, + input logic dmi_req_ready_i, +@@ -47,22 +49,26 @@ dmi_error_e error_d, error_q; logic tck; @@ -121,12 +211,15 @@ index 70ee776..04414e6 100644 logic shift; logic tdi; -+ assign dmi_clear = jtag_dmi_clear || dtmcs_q.dmihardreset; ++ logic dtmcs_select; ++ ++ assign dmi_clear = jtag_dmi_clear || (dtmcs_select && update && dtmcs_q.dmihardreset); + // ------------------------------- // Debug Module Control and Status // ------------------------------- -@@ -61,8 +65,7 @@ module dmi_jtag #( +- logic dtmcs_select; + dm::dtmcs_t dtmcs_d, dtmcs_q; always_comb begin @@ -136,7 +229,7 @@ index 70ee776..04414e6 100644 if (capture) begin if (dtmcs_select) begin dtmcs_d = '{ -@@ -83,8 +86,8 @@ module dmi_jtag #( +@@ -83,8 +89,8 @@ end end @@ -147,19 +240,17 @@ index 70ee776..04414e6 100644 dtmcs_q <= '0; end else begin dtmcs_q <= dtmcs_d; -@@ -94,9 +97,8 @@ module dmi_jtag #( +@@ -94,9 +100,6 @@ // ---------------------------- // DMI (Debug Module Interface) // ---------------------------- - // TODO(zarubaf): Might need to be connected to the `dtmcs_q.dmihardreset` - // signal. - assign dmi_rst_no = rst_ni; -+ -+ assign dmi_rst_no = dmi_clear; logic dmi_select; logic dmi_tdo; -@@ -142,79 +144,86 @@ module dmi_jtag #( +@@ -142,79 +145,86 @@ dmi_req_valid = 1'b0; @@ -175,7 +266,7 @@ index 70ee776..04414e6 100644 - end else if (dm::dtm_op_e'(dmi.op) == dm::DTM_WRITE) begin - state_d = Write; + if (dmi_clear) begin -+ state_d = IDLE; ++ state_d = Idle; + data_d = '0; + error_d = DMINoError; + address_d = '0; @@ -304,7 +395,7 @@ index 70ee776..04414e6 100644 end end -@@ -223,27 +232,30 @@ module dmi_jtag #( +@@ -223,27 +233,30 @@ always_comb begin : p_shift dr_d = dr_q; @@ -349,7 +440,7 @@ index 70ee776..04414e6 100644 dr_q <= '0; state_q <= Idle; address_q <= '0; -@@ -273,7 +285,7 @@ module dmi_jtag #( +@@ -273,7 +286,7 @@ .tdo_oe_o, .testmode_i, .tck_o ( tck ), @@ -358,7 +449,7 @@ index 70ee776..04414e6 100644 .update_o ( update ), .capture_o ( capture ), .shift_o ( shift ), -@@ -289,23 +301,24 @@ module dmi_jtag #( +@@ -289,23 +302,25 @@ // --------- dmi_cdc i_dmi_cdc ( // JTAG side (master side) @@ -388,6 +479,7 @@ index 70ee776..04414e6 100644 - .core_dmi_resp_i ( dmi_resp_i ), - .core_dmi_ready_o ( dmi_resp_ready_o ), - .core_dmi_valid_i ( dmi_resp_valid_i ) ++ .core_dmi_rst_no ( dmi_rst_no ), + .core_dmi_req_o ( dmi_req_o ), + .core_dmi_valid_o ( dmi_req_valid_o ), + .core_dmi_ready_i ( dmi_req_ready_i ), @@ -397,11 +489,9 @@ index 70ee776..04414e6 100644 ); endmodule : dmi_jtag -diff --git a/src/dmi_jtag_tap.sv b/src/dmi_jtag_tap.sv -index 7d3b67c..eff8a38 100644 --- a/src/dmi_jtag_tap.sv +++ b/src/dmi_jtag_tap.sv -@@ -34,7 +34,8 @@ module dmi_jtag_tap #( +@@ -34,7 +34,8 @@ input logic testmode_i, // JTAG is interested in writing the DTM CSR register output logic tck_o, @@ -411,162 +501,87 @@ index 7d3b67c..eff8a38 100644 output logic update_o, output logic capture_o, output logic shift_o, -@@ -202,7 +203,7 @@ module dmi_jtag_tap #( +@@ -72,7 +73,7 @@ + logic [IrLength-1:0] jtag_ir_shift_d, jtag_ir_shift_q; + // IR register -> this gets captured from shift register upon update_ir + ir_reg_e jtag_ir_d, jtag_ir_q; +- logic capture_ir, shift_ir, update_ir; // pause_ir ++ logic capture_ir, shift_ir, update_ir, test_logic_reset; // pause_ir + + always_comb begin : p_jtag + jtag_ir_shift_d = jtag_ir_shift_q; +@@ -92,6 +93,11 @@ + if (update_ir) begin + jtag_ir_d = ir_reg_e'(jtag_ir_shift_q); + end ++ ++ // According to JTAG spec we have to reset the IR to IDCODE in test_logic_reset ++ if (test_logic_reset) begin ++ jtag_ir_d = IDCODE; ++ end + end + + always_ff @(posedge tck_i, negedge trst_ni) begin : p_jtag_ir_reg +@@ -196,25 +202,13 @@ + tdo_oe_o <= (shift_ir | shift_dr); + end + end +- +-logic trst_sync1, trst_sync2; +- +-always_ff @(posedge tck_i or negedge trst_ni) begin +- if (!trst_ni) begin +- trst_sync2 <= 1'b0; +- end else begin +- trst_sync2 <= trst_sync1; +- trst_no <= trst_sync2; +- end +-end +- + // ---------------- + // TAP FSM + // ---------------- // Determination of next state; purely combinatorial always_comb begin : p_tap_fsm -- trst_no = trst_ni; -+ dmi_clear_o = 1'b0; +- trst_sync1 = trst_ni; ++ test_logic_reset = 1'b0; capture_dr = 1'b0; shift_dr = 1'b0; -@@ -216,7 +217,7 @@ module dmi_jtag_tap #( +@@ -228,7 +222,7 @@ unique case (tap_state_q) TestLogicReset: begin tap_state_d = (tms_i) ? TestLogicReset : RunTestIdle; -- trst_no = 1'b1; -+ dmi_clear_o = 1'b1; +- trst_sync1 = 1'b1; ++ test_logic_reset = 1'b1; end RunTestIdle: begin tap_state_d = (tms_i) ? SelectDrScan : RunTestIdle; - -From b3cc14aa1a240b2d43165f096553d2cece423e69 Mon Sep 17 00:00:00 2001 -From: Manuel Eggimann -Date: Wed, 2 Feb 2022 13:11:12 +0100 -Subject: [PATCH 02/11] Point to draft PR in common_cells for clearable CDC IPs - ---- - Bender.yml | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/Bender.yml b/Bender.yml -index 7178d56..9bc553e 100644 ---- a/Bender.yml -+++ b/Bender.yml -@@ -10,7 +10,7 @@ package: - - dependencies: - tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } -- common_cells: {git: https://github.com/pulp-platform/common_cells.git, version: 1.21.0} -+ common_cells: {git: https://github.com/pulp-platform/common_cells.git, rev: clearable_cdcs} - - sources: - files: - -From 5aaa574cbbfa356f51f086a826ad109d5b7d12c8 Mon Sep 17 00:00:00 2001 -From: Manuel Eggimann -Date: Wed, 2 Feb 2022 13:11:12 +0100 -Subject: [PATCH 03/11] Fix syntax errors - ---- - src/dmi_cdc.sv | 2 +- - src/dmi_jtag.sv | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - -diff --git a/src/dmi_cdc.sv b/src/dmi_cdc.sv -index d9e9363..030a120 100644 ---- a/src/dmi_cdc.sv -+++ b/src/dmi_cdc.sv -@@ -48,7 +48,7 @@ module dmi_cdc ( - - cdc_2phase_clearable #(.T(dm::dmi_req_t)) i_cdc_req ( - .src_rst_ni ( rst_ni ), -- .src_clear_i ( jtag_dmi_cdc_clear_i ) -+ .src_clear_i ( jtag_dmi_cdc_clear_i ), - .src_clk_i ( tck_i ), - .src_data_i ( jtag_dmi_req_i ), - .src_valid_i ( jtag_dmi_valid_i ), -diff --git a/src/dmi_jtag.sv b/src/dmi_jtag.sv -index 04414e6..7106b2d 100644 ---- a/src/dmi_jtag.sv -+++ b/src/dmi_jtag.sv -@@ -145,7 +145,7 @@ module dmi_jtag #( - dmi_req_valid = 1'b0; - - if (dmi_clear) begin -- state_d = IDLE; -+ state_d = Idle; - data_d = '0; - error_d = DMINoError; - address_d = '0; - -From 9f1e077861e00871c6d388cbba7b14dda1a1f9d4 Mon Sep 17 00:00:00 2001 -From: Manuel Eggimann -Date: Thu, 3 Feb 2022 17:10:53 +0100 -Subject: [PATCH 04/11] Fix wrong async reset connection and fix wrong - dmi_clear logic - ---- - src/dmi_cdc.sv | 6 +++--- - src/dmi_jtag.sv | 5 +++-- - 2 files changed, 6 insertions(+), 5 deletions(-) - -diff --git a/src/dmi_cdc.sv b/src/dmi_cdc.sv -index 030a120..f9b32bc 100644 ---- a/src/dmi_cdc.sv -+++ b/src/dmi_cdc.sv -@@ -19,7 +19,7 @@ - module dmi_cdc ( - // JTAG side (master side) - input logic tck_i, -- -+ input logic trst_ni, - input dm::dmi_req_t jtag_dmi_req_i, - output logic jtag_dmi_ready_o, - input logic jtag_dmi_valid_i, -@@ -47,7 +47,7 @@ module dmi_cdc ( - - - cdc_2phase_clearable #(.T(dm::dmi_req_t)) i_cdc_req ( -- .src_rst_ni ( rst_ni ), -+ .src_rst_ni ( trst_ni ), - .src_clear_i ( jtag_dmi_cdc_clear_i ), - .src_clk_i ( tck_i ), - .src_data_i ( jtag_dmi_req_i ), -@@ -63,7 +63,7 @@ module dmi_cdc ( - .dst_ready_i ( core_dmi_ready_i ) - ); - -- cdc_2phase #(.T(dm::dmi_resp_t)) i_cdc_resp ( -+ cdc_2phase_clearable #(.T(dm::dmi_resp_t)) i_cdc_resp ( - .src_rst_ni ( rst_ni ), - .src_clear_i ( 1'b0 ), // No functional reset from core side - // used (only async ). -diff --git a/src/dmi_jtag.sv b/src/dmi_jtag.sv -index 7106b2d..e1bc369 100644 ---- a/src/dmi_jtag.sv -+++ b/src/dmi_jtag.sv -@@ -55,12 +55,13 @@ module dmi_jtag #( - logic shift; - logic tdi; - -- assign dmi_clear = jtag_dmi_clear || dtmcs_q.dmihardreset; -+ logic dtmcs_select; +@@ -319,5 +313,7 @@ + assign update_o = update_dr; + assign shift_o = shift_dr; + assign capture_o = capture_dr; ++ assign dmi_clear_o = test_logic_reset; + -+ assign dmi_clear = jtag_dmi_clear || (dtmcs_select && update && dtmcs_q.dmihardreset); - // ------------------------------- - // Debug Module Control and Status - // ------------------------------- -- logic dtmcs_select; - - dm::dtmcs_t dtmcs_d, dtmcs_q; + endmodule : dmi_jtag_tap +--- a/src/dm_top.sv ++++ b/src/dm_top.sv +@@ -57,7 +57,9 @@ + input logic [BusWidth-1:0] master_r_rdata_i, - -From cdd595647acd03256b700ed6cf78d8e723f1cc49 Mon Sep 17 00:00:00 2001 -From: Manuel Eggimann -Date: Thu, 3 Feb 2022 17:11:46 +0100 -Subject: [PATCH 05/11] Fix jtag DV IP to reset ir_select reg during reset - ---- - tb/jtag_dmi/jtag_test.sv | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/tb/jtag_dmi/jtag_test.sv b/tb/jtag_dmi/jtag_test.sv -index 7872d5c..a8db8ad 100644 + // Connection to DTM - compatible to RocketChip Debug Module +- input logic dmi_rst_ni, ++ input logic dmi_rst_ni, // Synchronous clear request from ++ // the DTM to clear the DMI response ++ // FIFO. + input logic dmi_req_valid_i, + output logic dmi_req_ready_o, + input dm::dmi_req_t dmi_req_i, --- a/tb/jtag_dmi/jtag_test.sv +++ b/tb/jtag_dmi/jtag_test.sv -@@ -33,6 +33,7 @@ package jtag_test; +@@ -33,6 +33,7 @@ jtag.trst_n <= #TA 0; repeat (2) clock(); jtag.trst_n <= #TA 1; @@ -574,22 +589,19 @@ index 7872d5c..a8db8ad 100644 clock(); endtask - -From 0a794a337dfc0d37084e9860d46effd77a82f232 Mon Sep 17 00:00:00 2001 -From: Manuel Eggimann -Date: Thu, 3 Feb 2022 17:12:27 +0100 -Subject: [PATCH 06/11] Modify tb to issue random dmi resets between - transactions - ---- - tb/jtag_dmi/tb_jtag_dmi.sv | 30 ++++++++++++++++++++++++++++-- - 1 file changed, 28 insertions(+), 2 deletions(-) - -diff --git a/tb/jtag_dmi/tb_jtag_dmi.sv b/tb/jtag_dmi/tb_jtag_dmi.sv -index 1e0cdd8..1d64a01 100644 +@@ -42,6 +43,9 @@ + repeat (6) clock(); + jtag.tms <= #TA 0; + clock(); ++ // After softreset the IR should be reset to IDCODE so we have to mirror ++ // this in our internal state. ++ this.ir_select = 'h1; + endtask + + // Set IR, but only if it needs to be set. --- a/tb/jtag_dmi/tb_jtag_dmi.sv +++ b/tb/jtag_dmi/tb_jtag_dmi.sv -@@ -242,6 +242,30 @@ module tb_jtag_dmi; +@@ -242,6 +242,30 @@ riscv_dbg.read_dmi(dm::dm_csr_e'(transaction.addr), rdata); rsp_mbx.put(rdata); end @@ -620,7 +632,7 @@ index 1e0cdd8..1d64a01 100644 end #1000; $finish(); -@@ -261,8 +285,10 @@ module tb_jtag_dmi; +@@ -261,8 +285,10 @@ req_mbx.get(req); rsp_mbx.get(rsp); nr_transactions++; @@ -633,21 +645,9 @@ index 1e0cdd8..1d64a01 100644 if (req.op == dm::DTM_READ) begin assert(rsp_mon.data == rsp); end else begin - -From 71d8b30010ab9364d96d8e0158047dba77ad0971 Mon Sep 17 00:00:00 2001 -From: Manuel Eggimann -Date: Thu, 31 Mar 2022 12:47:52 +0200 -Subject: [PATCH 07/11] Actually reset the dmi on remote_bitbang request - ---- - tb/remote_bitbang/remote_bitbang.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/tb/remote_bitbang/remote_bitbang.c b/tb/remote_bitbang/remote_bitbang.c -index e77c00d..cf24fbb 100644 --- a/tb/remote_bitbang/remote_bitbang.c +++ b/tb/remote_bitbang/remote_bitbang.c -@@ -115,7 +115,7 @@ void rbs_tick(unsigned char *jtag_tck, unsigned char *jtag_tms, +@@ -115,7 +115,7 @@ void rbs_reset() { @@ -656,331 +656,3 @@ index e77c00d..cf24fbb 100644 } void rbs_set_pins(char _tck, char _tms, char _tdi) - -From 407c6aa01bbc47113888e6e8081a665fabb1c458 Mon Sep 17 00:00:00 2001 -From: Manuel Eggimann -Date: Thu, 31 Mar 2022 13:33:45 +0200 -Subject: [PATCH 08/11] Bump to latest common cells version and add missing cdc - port signals - ---- - Bender.yml | 2 +- - src/dmi_cdc.sv | 4 ++++ - 2 files changed, 5 insertions(+), 1 deletion(-) - -diff --git a/Bender.yml b/Bender.yml -index 9bc553e..d6b9090 100644 ---- a/Bender.yml -+++ b/Bender.yml -@@ -10,7 +10,7 @@ package: - - dependencies: - tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } -- common_cells: {git: https://github.com/pulp-platform/common_cells.git, rev: clearable_cdcs} -+ common_cells: {git: "https://github.com/pulp-platform/common_cells.git", version: 1.24.0} - - sources: - files: -diff --git a/src/dmi_cdc.sv b/src/dmi_cdc.sv -index f9b32bc..91ff3ca 100644 ---- a/src/dmi_cdc.sv -+++ b/src/dmi_cdc.sv -@@ -50,6 +50,7 @@ module dmi_cdc ( - .src_rst_ni ( trst_ni ), - .src_clear_i ( jtag_dmi_cdc_clear_i ), - .src_clk_i ( tck_i ), -+ .src_clear_pending_o(), // Not used - .src_data_i ( jtag_dmi_req_i ), - .src_valid_i ( jtag_dmi_valid_i ), - .src_ready_o ( jtag_dmi_ready_o ), -@@ -57,6 +58,7 @@ module dmi_cdc ( - .dst_rst_ni ( rst_ni ), - .dst_clear_i ( 1'b0 ), // No functional reset from core side - // used (only async). -+ .dst_clear_pending_o(), // Not used - .dst_clk_i ( clk_i ), - .dst_data_o ( core_dmi_req_o ), - .dst_valid_o ( core_dmi_valid_o ), -@@ -67,6 +69,7 @@ module dmi_cdc ( - .src_rst_ni ( rst_ni ), - .src_clear_i ( 1'b0 ), // No functional reset from core side - // used (only async ). -+ .src_clear_pending_o(), // Not used - .src_clk_i ( clk_i ), - .src_data_i ( core_dmi_resp_i ), - .src_valid_i ( core_dmi_valid_i ), -@@ -74,6 +77,7 @@ module dmi_cdc ( - - .dst_rst_ni ( trst_ni ), - .dst_clear_i ( jtag_dmi_cdc_clear_i ), -+ .dst_clear_pending_o(), //Not used - .dst_clk_i ( tck_i ), - .dst_data_o ( jtag_dmi_resp_o ), - .dst_valid_o ( jtag_dmi_valid_o ), - -From 6c0703eae20224a2ec5e52a765aec4a02f97a259 Mon Sep 17 00:00:00 2001 -From: Manuel Eggimann -Date: Fri, 1 Apr 2022 17:48:13 +0200 -Subject: [PATCH 09/11] Make dmi_rst_ni synchronous in dm_csrs & filter - glitches on dmi_rst_no - -The dmi_rst_ni signal of dm_top was previously asynchronously resetting the -response FIFO within dm_csrs. In this commit this behavior changed to make the -dmi_rst_ni a synchronous clear signal that flushes the FIFO. That way, -power-on-reset and functional resets are orthogonal to each other. Still, since -the (undocumented) semantic of the dmi_rst_no signal changed, this commit also -adds a glitch filter on the dmi_rst_no signal to make it a glitch free -core_clock synchronous signal. That way, it is safe to use the dmi_rst_no signal -as either an async or a synchronous reset signal for the core clock domain. ---- - src/dm_csrs.sv | 10 ++++++---- - src/dm_top.sv | 4 +++- - src/dmi_cdc.sv | 31 +++++++++++++++++++++++++++++-- - src/dmi_jtag.sv | 7 ++++--- - src/dmi_jtag_tap.sv | 13 ++++++++++--- - 5 files changed, 52 insertions(+), 13 deletions(-) - -diff --git a/src/dm_csrs.sv b/src/dm_csrs.sv -index f742a2b..350c6c5 100644 ---- a/src/dm_csrs.sv -+++ b/src/dm_csrs.sv -@@ -23,7 +23,8 @@ module dm_csrs #( - input logic clk_i, // Clock - input logic rst_ni, // Asynchronous reset active low - input logic testmode_i, -- input logic dmi_rst_ni, // Debug Module Intf reset active-low -+ input logic dmi_rst_ni, // sync. DTM reset, -+ // active-low - input logic dmi_req_valid_i, - output logic dmi_req_ready_o, - input dm::dmi_req_t dmi_req_i, -@@ -559,9 +560,10 @@ module dm_csrs #( - .dtype ( logic [31:0] ), - .DEPTH ( 2 ) - ) i_fifo ( -- .clk_i ( clk_i ), -- .rst_ni ( dmi_rst_ni ), // reset only when system is re-set -- .flush_i ( 1'b0 ), // we do not need to flush this queue -+ .clk_i, -+ .rst_ni, -+ .flush_i ( ~dmi_rst_ni ), // Flush the queue if the DTM is -+ // reset - .testmode_i ( testmode_i ), - .full_o ( resp_queue_full ), - .empty_o ( resp_queue_empty ), -diff --git a/src/dm_top.sv b/src/dm_top.sv -index ce71d07..3c9c445 100644 ---- a/src/dm_top.sv -+++ b/src/dm_top.sv -@@ -57,7 +57,9 @@ module dm_top #( - input logic [BusWidth-1:0] master_r_rdata_i, - - // Connection to DTM - compatible to RocketChip Debug Module -- input logic dmi_rst_ni, -+ input logic dmi_rst_ni, // Synchronous clear request from -+ // the DTM to clear the DMI response -+ // FIFO. - input logic dmi_req_valid_i, - output logic dmi_req_ready_o, - input dm::dmi_req_t dmi_req_i, -diff --git a/src/dmi_cdc.sv b/src/dmi_cdc.sv -index 91ff3ca..f9d66fd 100644 ---- a/src/dmi_cdc.sv -+++ b/src/dmi_cdc.sv -@@ -35,6 +35,7 @@ module dmi_cdc ( - input logic clk_i, - input logic rst_ni, - -+ output logic core_dmi_rst_no, - output dm::dmi_req_t core_dmi_req_o, - output logic core_dmi_valid_o, - input logic core_dmi_ready_i, -@@ -44,7 +45,7 @@ module dmi_cdc ( - input logic core_dmi_valid_i - ); - -- -+ logic core_clear_pending; - - cdc_2phase_clearable #(.T(dm::dmi_req_t)) i_cdc_req ( - .src_rst_ni ( trst_ni ), -@@ -58,7 +59,10 @@ module dmi_cdc ( - .dst_rst_ni ( rst_ni ), - .dst_clear_i ( 1'b0 ), // No functional reset from core side - // used (only async). -- .dst_clear_pending_o(), // Not used -+ .dst_clear_pending_o( core_clear_pending ), // use the clear pending signal -+ // to synchronously clear the -+ // response FIFO in the dm_top -+ // csrs - .dst_clk_i ( clk_i ), - .dst_data_o ( core_dmi_req_o ), - .dst_valid_o ( core_dmi_valid_o ), -@@ -84,4 +88,27 @@ module dmi_cdc ( - .dst_ready_i ( jtag_dmi_ready_i ) - ); - -+ // We need to flush the DMI response FIFO in DM top using the core clock -+ // synchronous clear signal core_dmi_rst_no. We repurpose the clear -+ // pending signal in the core clock domain by generating a 1 cycle pulse from -+ // it. -+ -+ logic core_clear_pending_q; -+ logic core_dmi_rst_nq; -+ logic clear_pending_rise_edge_detect; -+ -+ assign clear_pending_rise_edge_detect = !core_clear_pending_q && core_clear_pending; -+ -+ always_ff @(posedge clk_i, negedge rst_ni) begin -+ if (!rst_ni) begin -+ core_dmi_rst_nq <= 1'b1; -+ core_clear_pending_q <= 1'b0; -+ end else begin -+ core_dmi_rst_nq <= ~clear_pending_rise_edge_detect; // active-low! -+ core_clear_pending_q <= core_clear_pending; -+ end -+ end -+ -+ assign core_dmi_rst_no = core_dmi_rst_nq; -+ - endmodule : dmi_cdc -diff --git a/src/dmi_jtag.sv b/src/dmi_jtag.sv -index e1bc369..0712f8c 100644 ---- a/src/dmi_jtag.sv -+++ b/src/dmi_jtag.sv -@@ -23,7 +23,9 @@ module dmi_jtag #( - input logic rst_ni, // Asynchronous reset active low - input logic testmode_i, - -- output logic dmi_rst_no, // hard reset -+ // active-low glitch free reset signal. Is asserted for one dmi clock cycle -+ // (clk_i) whenever the dmi_jtag is reset (POR or functional reset). -+ output logic dmi_rst_no, - output dm::dmi_req_t dmi_req_o, - output logic dmi_req_valid_o, - input logic dmi_req_ready_i, -@@ -99,8 +101,6 @@ module dmi_jtag #( - // DMI (Debug Module Interface) - // ---------------------------- - -- assign dmi_rst_no = dmi_clear; -- - logic dmi_select; - logic dmi_tdo; - -@@ -314,6 +314,7 @@ module dmi_jtag #( - // core side - .clk_i, - .rst_ni, -+ .core_dmi_rst_no ( dmi_rst_no ), - .core_dmi_req_o ( dmi_req_o ), - .core_dmi_valid_o ( dmi_req_valid_o ), - .core_dmi_ready_i ( dmi_req_ready_i ), -diff --git a/src/dmi_jtag_tap.sv b/src/dmi_jtag_tap.sv -index eff8a38..0c188c0 100644 ---- a/src/dmi_jtag_tap.sv -+++ b/src/dmi_jtag_tap.sv -@@ -73,7 +73,7 @@ module dmi_jtag_tap #( - logic [IrLength-1:0] jtag_ir_shift_d, jtag_ir_shift_q; - // IR register -> this gets captured from shift register upon update_ir - ir_reg_e jtag_ir_d, jtag_ir_q; -- logic capture_ir, shift_ir, update_ir; // pause_ir -+ logic capture_ir, shift_ir, update_ir, test_logic_reset; // pause_ir - - always_comb begin : p_jtag - jtag_ir_shift_d = jtag_ir_shift_q; -@@ -93,6 +93,11 @@ module dmi_jtag_tap #( - if (update_ir) begin - jtag_ir_d = ir_reg_e'(jtag_ir_shift_q); - end -+ -+ // According to JTAG spec we have to reset the IR to IDCODE in test_logic_reset -+ if (test_logic_reset) begin -+ jtag_ir_d = IDCODE; -+ end - end - - always_ff @(posedge tck_i, negedge trst_ni) begin : p_jtag_ir_reg -@@ -203,7 +208,7 @@ module dmi_jtag_tap #( - // Determination of next state; purely combinatorial - always_comb begin : p_tap_fsm - -- dmi_clear_o = 1'b0; -+ test_logic_reset = 1'b0; - - capture_dr = 1'b0; - shift_dr = 1'b0; -@@ -217,7 +222,7 @@ module dmi_jtag_tap #( - unique case (tap_state_q) - TestLogicReset: begin - tap_state_d = (tms_i) ? TestLogicReset : RunTestIdle; -- dmi_clear_o = 1'b1; -+ test_logic_reset = 1'b1; - end - RunTestIdle: begin - tap_state_d = (tms_i) ? SelectDrScan : RunTestIdle; -@@ -308,5 +313,7 @@ module dmi_jtag_tap #( - assign update_o = update_dr; - assign shift_o = shift_dr; - assign capture_o = capture_dr; -+ assign dmi_clear_o = test_logic_reset; -+ - - endmodule : dmi_jtag_tap - -From c17902e672356dd1d4736de5b6839ca37ba1423e Mon Sep 17 00:00:00 2001 -From: Manuel Eggimann -Date: Mon, 4 Apr 2022 17:35:07 +0200 -Subject: [PATCH 10/11] Update JTAG Test package to reflect TestLogicReset fix - ---- - tb/jtag_dmi/jtag_test.sv | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/tb/jtag_dmi/jtag_test.sv b/tb/jtag_dmi/jtag_test.sv -index a8db8ad..60675a4 100644 ---- a/tb/jtag_dmi/jtag_test.sv -+++ b/tb/jtag_dmi/jtag_test.sv -@@ -43,6 +43,9 @@ package jtag_test; - repeat (6) clock(); - jtag.tms <= #TA 0; - clock(); -+ // After softreset the IR should be reset to IDCODE so we have to mirror -+ // this in our internal state. -+ this.ir_select = 'h1; - endtask - - // Set IR, but only if it needs to be set. - -From 7c6918a5a5bd865b11d55a1e1f17ddeed32d6e5e Mon Sep 17 00:00:00 2001 -From: Manuel Eggimann -Date: Fri, 1 Apr 2022 18:10:18 +0200 -Subject: [PATCH 11/11] Update changelog - ---- - CHANGELOG.md | 7 +++++++ - 1 file changed, 7 insertions(+) - -diff --git a/CHANGELOG.md b/CHANGELOG.md -index 737dea7..c931663 100644 ---- a/CHANGELOG.md -+++ b/CHANGELOG.md -@@ -8,11 +8,18 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0. - ### Added - - Add sbaccess8 and sbaccess16 support (#106) [@noytzach](https://github.com/noytzach) - - Implement SBA bad address error (#12) [@msfchaffner](https://github.com/msfschaffner) -+- Added random reset tests to dmi testbench. - ### Changed -+- Implement `dmihardreset` functionaliy in `dtmcs` register. -+- `dmi_rst_ni` of `dm_top` is now a synchronous signal. However, `dmi_rst_no` of -+ `dmi_jtag` is glitch-free and asserted during all forms (functional or POR) of -+ resets. - ### Fixed - - Fixed documentation (csr) - - Fixed reset value of sbcs register (#127) [@msfchaffner](https://github.com/msfschaffner) - - Fixed various ascent lint warnings [@msfchaffner](https://github.com/msfschaffner) -+- Implement proper CDC flushing behavior on functional resets and JTAG resets (asynchronous or TestLogicReset driven). -+- Fix JTAG non-compliance in TestLogicReset state (IR should reset to IDCODE). - - ## [0.4.1] - 2021-05-04 - ### Added diff --git a/patches/verilator_verilator_pr6737.patch b/patches/verilator_verilator_pr6737.patch index 288b09fdda6e86f1cb6e572bed8c7c70725c4161..ccd91e8b1ced3b9002f16b1ab8735045a6f57802 100644 --- a/patches/verilator_verilator_pr6737.patch +++ b/patches/verilator_verilator_pr6737.patch @@ -1,159 +1,54 @@ -From 464e4ac7168fa576960c33aadbddaa7630467e8a Mon Sep 17 00:00:00 2001 -From: Udaya Raj Subedi <075bei047.udaya@pcampus.edu.np> -Date: Thu, 20 Nov 2025 13:49:55 +0100 -Subject: [PATCH 01/29] first try for array sel - ---- - src/V3Randomize.cpp | 10 +++++++--- - src/V3Width.cpp | 2 +- - 2 files changed, 8 insertions(+), 4 deletions(-) - -diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp -index 7caaaba7f16..dca559f0fd7 100644 ---- a/src/V3Randomize.cpp -+++ b/src/V3Randomize.cpp -@@ -538,11 +538,15 @@ class RandomizeMarkVisitor final : public VNVisitor { - if (AstMemberSel* const memberSelp = VN_CAST(exprp, MemberSel)) { - randVarp = memberSelp->varp(); - exprp = memberSelp->fromp(); -- } else { -- AstVarRef* const varrefp = VN_AS(exprp, VarRef); -+ } else if(AstVarRef* varrefp = VN_CAST(exprp, VarRef)) { - randVarp = varrefp->varp(); - exprp = nullptr; - varrefp->user1(true); -+ } else { -+ varrefp = VN_AS(VN_CAST(exprp, ArraySel)->fromp(), VarRef); -+ randVarp = varrefp->varp(); -+ varrefp->access(VAccess::READWRITE); -+ exprp = nullptr; - } - UASSERT_OBJ(randVarp, nodep, "No rand variable found"); - AstNode* backp = randVarp; -@@ -2930,7 +2934,7 @@ AstFunc* V3Randomize::newRandomizeStdFunc(VMemberMap& memberMap, AstNodeModule* - if (VN_IS(nodep, Class)) { - funcp->classMethod(true); - } else { -- funcp->classMethod(false); -+ funcp->classMethod(true); - funcp->isStatic(true); - } - nodep->addStmtsp(funcp); -diff --git a/src/V3Width.cpp b/src/V3Width.cpp -index 0b226803f35..215f99c4fec 100644 ---- a/src/V3Width.cpp -+++ b/src/V3Width.cpp -@@ -6679,7 +6679,7 @@ class WidthVisitor final : public VNVisitor { - // IEEE 1800-2023 (18.12) limits args to current scope variables. - // Verilator accepts this for compatibility with other simulators. - continue; -- } else if (VN_IS(exprp, VarRef)) { -+ } else if (VN_IS(exprp, VarRef) || VN_IS(exprp, ArraySel)) { - // Valid usage - continue; - } else { - -From 501c53f4e57e3483894ba6ed82475d37a6eae176 Mon Sep 17 00:00:00 2001 -From: github action -Date: Thu, 20 Nov 2025 12:51:16 +0000 -Subject: [PATCH 02/29] Apply 'make format' - ---- - src/V3Randomize.cpp | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp -index dca559f0fd7..9bb4adb84bd 100644 ---- a/src/V3Randomize.cpp -+++ b/src/V3Randomize.cpp -@@ -538,7 +538,7 @@ class RandomizeMarkVisitor final : public VNVisitor { - if (AstMemberSel* const memberSelp = VN_CAST(exprp, MemberSel)) { - randVarp = memberSelp->varp(); - exprp = memberSelp->fromp(); -- } else if(AstVarRef* varrefp = VN_CAST(exprp, VarRef)) { -+ } else if (AstVarRef* varrefp = VN_CAST(exprp, VarRef)) { - randVarp = varrefp->varp(); - exprp = nullptr; - varrefp->user1(true); - -From 15aabef5a4fe00f73f75b38da13a1854e965ca5d Mon Sep 17 00:00:00 2001 -From: Udaya Raj Subedi <075bei047.udaya@pcampus.edu.np> -Date: Thu, 20 Nov 2025 15:35:46 +0100 -Subject: [PATCH 03/29] Whole array bsaic randomizationa nd constrained in with - foreach(arr[i]) - ---- - include/verilated_random.h | 7 +++++++ - src/V3Randomize.cpp | 1 + - 2 files changed, 8 insertions(+) - -diff --git a/include/verilated_random.h b/include/verilated_random.h -index bd3a2744205..56509c4a6e1 100644 ---- a/include/verilated_random.h -+++ b/include/verilated_random.h -@@ -595,6 +595,13 @@ class VlStdRandomizer final : public VlRandomizer { - value = VL_MASK_I(width) & VL_RANDOM_RNG_I(m_rng); - return true; +diff --git a/src/V3AstNodeOther.h b/src/V3AstNodeOther.h +index aeac0d27a0a..782f1a5113a 100644 +--- a/src/V3AstNodeOther.h ++++ b/src/V3AstNodeOther.h +@@ -1878,6 +1878,7 @@ class AstVar final : public AstNode { + bool m_ignoreSchedWrite : 1; // Ignore writes in scheduling (for special optimizations) + bool m_dfgMultidriven : 1; // Singal is multidriven, used by DFG to avoid repeat processing + bool m_globalConstrained : 1; // Global constraint per IEEE 1800-2023 18.5.8 ++ bool m_isStdRandomizeArg : 1; // Argument variable created for std::randomize (__Varg*) + void init() { + m_ansi = false; + m_declTyped = false; +@@ -1929,6 +1930,7 @@ class AstVar final : public AstNode { + m_ignoreSchedWrite = false; + m_dfgMultidriven = false; + m_globalConstrained = false; ++ m_isStdRandomizeArg = false; } -+ template -+ bool basicStdRandomization(VlUnpacked& value, size_t width) { -+ for (size_t i = 0; i < N_Depth; ++i) { -+ value.operator[](i) = VL_MASK_I(width) & VL_RANDOM_RNG_I(m_rng); -+ } -+ return true; -+ } - bool next() { return VlRandomizer::next(m_rng); } - }; + public: +@@ -2096,6 +2098,8 @@ class AstVar final : public AstNode { + void setDfgMultidriven() { m_dfgMultidriven = true; } + void globalConstrained(bool flag) { m_globalConstrained = flag; } + bool globalConstrained() const { return m_globalConstrained; } ++ bool isStdRandomizeArg() const { return m_isStdRandomizeArg; } ++ void setStdRandomizeArg() { m_isStdRandomizeArg = true; } + // METHODS + void name(const string& name) override { m_name = name; } + void tag(const string& text) override { m_tag = text; } +diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp +index ee1c7201959..9f5dad4c818 100644 +--- a/src/V3AstNodes.cpp ++++ b/src/V3AstNodes.cpp +@@ -2776,6 +2776,7 @@ void AstVar::dump(std::ostream& str) const { + if (isDpiOpenArray()) str << " [DPIOPENA]"; + if (ignorePostWrite()) str << " [IGNPWR]"; + if (ignoreSchedWrite()) str << " [IGNWR]"; ++ if (isStdRandomizeArg()) str << " [STDRANDARG]"; + if (!lifetime().isNone()) str << " [" << lifetime().ascii() << "] "; + str << " " << varType(); + } +@@ -2797,6 +2798,7 @@ void AstVar::dumpJson(std::ostream& str) const { + dumpJsonBoolFunc(str, isDpiOpenArray); + dumpJsonBoolFunc(str, isFuncReturn); + dumpJsonBoolFunc(str, isFuncLocal); ++ dumpJsonBoolFunc(str, isStdRandomizeArg); + dumpJsonStr(str, "lifetime", lifetime().ascii()); + dumpJsonStr(str, "varType", varType().ascii()); + if (dtypep()) dumpJsonStr(str, "dtypeName", dtypep()->name()); diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp -index 9bb4adb84bd..ab8d4c581a2 100644 ---- a/src/V3Randomize.cpp -+++ b/src/V3Randomize.cpp -@@ -545,6 +545,7 @@ class RandomizeMarkVisitor final : public VNVisitor { - } else { - varrefp = VN_AS(VN_CAST(exprp, ArraySel)->fromp(), VarRef); - randVarp = varrefp->varp(); -+ varrefp->user1(true); - varrefp->access(VAccess::READWRITE); - exprp = nullptr; - } - -From 3db38bf10d3a53a99cc58826281bb4a8d99aac5f Mon Sep 17 00:00:00 2001 -From: github action -Date: Thu, 20 Nov 2025 14:37:19 +0000 -Subject: [PATCH 04/29] Apply 'make format' - ---- - include/verilated_random.h | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/include/verilated_random.h b/include/verilated_random.h -index 56509c4a6e1..652e8febc69 100644 ---- a/include/verilated_random.h -+++ b/include/verilated_random.h -@@ -598,8 +598,8 @@ class VlStdRandomizer final : public VlRandomizer { - template - bool basicStdRandomization(VlUnpacked& value, size_t width) { - for (size_t i = 0; i < N_Depth; ++i) { -- value.operator[](i) = VL_MASK_I(width) & VL_RANDOM_RNG_I(m_rng); -- } -+ value.operator[](i) = VL_MASK_I(width) & VL_RANDOM_RNG_I(m_rng); -+ } - return true; - } - bool next() { return VlRandomizer::next(m_rng); } - -From 513925dda5f05ef0025ee0484a2fdda8ebbdf56e Mon Sep 17 00:00:00 2001 -From: Udaya Raj Subedi <075bei047.udaya@pcampus.edu.np> -Date: Thu, 20 Nov 2025 23:23:16 +0100 -Subject: [PATCH 05/29] arument replacement and array sel support - ---- - src/V3Randomize.cpp | 77 ++++++++++++++++++++++++++++----------------- - 1 file changed, 48 insertions(+), 29 deletions(-) - -diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp -index ab8d4c581a2..2900cdc7e0d 100644 +index 0c397538a7a..7091ccd3166 100644 --- a/src/V3Randomize.cpp +++ b/src/V3Randomize.cpp @@ -175,6 +175,8 @@ class RandomizeMarkVisitor final : public VNVisitor { @@ -161,11 +56,33 @@ index ab8d4c581a2..2900cdc7e0d 100644 } else if (const AstMemberSel* const memberselp = VN_CAST(exprp, MemberSel)) { if (memberselp->varp() == varp) return true; + } else if (const AstArraySel* const arrselp = VN_CAST(exprp, ArraySel)) { -+ if (arrselp->fromp()->dtypep() == varp->dtypep()) return true; ++ if (VN_AS(arrselp->fromp(), VarRef)->varp() == varp) return true; } } return false; -@@ -678,7 +680,7 @@ class RandomizeMarkVisitor final : public VNVisitor { +@@ -535,14 +537,19 @@ class RandomizeMarkVisitor final : public VNVisitor { + AstNodeExpr* exprp = argp->exprp(); + while (exprp) { + AstVar* randVarp = nullptr; ++ AstVarRef* varrefp = nullptr; + if (AstMemberSel* const memberSelp = VN_CAST(exprp, MemberSel)) { + randVarp = memberSelp->varp(); + exprp = memberSelp->fromp(); ++ } else if ((varrefp = VN_CAST(exprp, VarRef))) { ++ randVarp = varrefp->varp(); ++ varrefp->user1(true); ++ exprp = nullptr; + } else { +- AstVarRef* varrefp = nullptr; +- varrefp = VN_AS(exprp, VarRef); ++ varrefp = VN_AS(VN_CAST(exprp, ArraySel)->fromp(), VarRef); + randVarp = varrefp->varp(); + varrefp->user1(true); ++ varrefp->access(VAccess::READWRITE); + exprp = nullptr; + } + UASSERT_OBJ(randVarp, nodep, "No rand variable found"); +@@ -674,7 +681,7 @@ class RandomizeMarkVisitor final : public VNVisitor { void visit(AstNodeExpr* nodep) override { iterateChildrenConst(nodep); @@ -174,19 +91,63 @@ index ab8d4c581a2..2900cdc7e0d 100644 nodep->user1((nodep->op1p() && nodep->op1p()->user1()) || (nodep->op2p() && nodep->op2p()->user1()) || (nodep->op3p() && nodep->op3p()->user1()) -@@ -2608,38 +2610,17 @@ class RandomizeVisitor final : public VNVisitor { +@@ -1424,6 +1431,7 @@ class CaptureVisitor final : public VNVisitor { + AstVar* getVar(AstVar* const varp) const { + const auto it = m_varCloneMap.find(varp); + if (it == m_varCloneMap.end()) return nullptr; ++ if (it->second->isStdRandomizeArg()) return nullptr; + return it->second; + } + +@@ -1494,6 +1502,7 @@ class CaptureVisitor final : public VNVisitor { + if (m_ignore.count(nodep)) return; + m_ignore.emplace(nodep); + UASSERT_OBJ(nodep->varp(), nodep, "Variable unlinked"); ++ if (nodep->varp()->isStdRandomizeArg()) return; + CaptureMode capMode = getVarRefCaptureMode(nodep); + if (mode(capMode) == CaptureMode::CAP_NO) return; + if (mode(capMode) == CaptureMode::CAP_VALUE) captureRefByValue(nodep, capMode); +@@ -1632,6 +1641,33 @@ class RandomizeVisitor final : public VNVisitor { + std::set m_writtenVars; // Track write_var calls per class to avoid duplicates + + // METHODS ++ // Check if two nodes are semantically equivalent (not pointer equality): ++ static bool isSimilarNode(const AstNodeExpr* withExpr, const AstNodeExpr* argExpr) { ++ // VarRef: compare variable pointers ++ if (VN_IS(argExpr, VarRef) && VN_IS(withExpr, VarRef)) { ++ return VN_AS(withExpr, VarRef)->varp() == VN_AS(argExpr, VarRef)->varp(); ++ } ++ // MemberSel: compare object and member (obj.y) ++ if (VN_IS(argExpr, MemberSel) && VN_IS(withExpr, MemberSel)) { ++ const AstMemberSel* const withMSp = VN_AS(withExpr, MemberSel); ++ const AstMemberSel* const argMSp = VN_AS(argExpr, MemberSel); ++ if (withMSp->varp() != argMSp->varp()) return false; ++ // Recursively compare the base object expression ++ return isSimilarNode(withMSp->fromp(), argMSp->fromp()); ++ } ++ // ArraySel: compare array base and index (arr[i]) ++ if (VN_IS(argExpr, ArraySel) && VN_IS(withExpr, ArraySel)) { ++ const AstArraySel* const withASp = VN_AS(withExpr, ArraySel); ++ const AstArraySel* const argASp = VN_AS(argExpr, ArraySel); ++ // Index must be Sel type, extract VarRef using fromp() ++ if (!VN_IS(withASp->bitp(), Sel) || !VN_IS(argASp->bitp(), Sel)) return false; ++ const AstNodeExpr* const withIdxp = VN_AS(withASp->bitp(), Sel)->fromp(); ++ const AstNodeExpr* const argIdxp = VN_AS(argASp->bitp(), Sel)->fromp(); ++ return isSimilarNode(withASp->fromp(), argASp->fromp()) ++ && isSimilarNode(withIdxp, argIdxp); ++ } ++ return false; ++ } + void createRandomGenerator(AstClass* const classp) { + if (classp->user3p()) return; + if (classp->extendsp()) { +@@ -2604,38 +2640,14 @@ class RandomizeVisitor final : public VNVisitor { new AstConst{nodep->fileline(), AstConst::WidthedValue{}, 32, 1}}); std::unique_ptr withCapturep; int argn = 0; + AstWith* withp = nullptr; -+ for (AstNode* pinp = nodep->pinsp(); pinp; pinp = pinp->nextp()){ -+ AstArg* const argp = VN_CAST(pinp, Arg); -+ withp = VN_IS(pinp, With)?VN_AS(pinp,With):nullptr; -+ if(withp) break; -+ } -+ for (AstNode* pinp = nodep->pinsp(); pinp; pinp = pinp->nextp()) { - AstArg* const argp = VN_CAST(pinp, Arg); +- AstArg* const argp = VN_CAST(pinp, Arg); - AstWith* const withp = VN_CAST(pinp, With); - if (withp) { - FileLine* const fl = nodep->fileline(); @@ -214,151 +175,45 @@ index ab8d4c581a2..2900cdc7e0d 100644 - AstVarRef* const retvalWritep = new AstVarRef{fl, fvarp, VAccess::WRITE}; - randomizeFuncp->addStmtsp(new AstAssign{fl, retvalWritep, andExprp}); - } ++ if ((withp = VN_CAST(pinp, With))) break; ++ } ++ for (const AstNode* pinp = nodep->pinsp(); pinp; pinp = pinp->nextp()) { ++ const AstArg* const argp = VN_CAST(pinp, Arg); if (!argp) continue; AstNodeExpr* exprp = argp->exprp(); - AstCMethodHard* const basicMethodp = new AstCMethodHard{ nodep->fileline(), new AstVarRef{nodep->fileline(), stdrand, VAccess::READWRITE}, -@@ -2647,6 +2628,16 @@ class RandomizeVisitor final : public VNVisitor { +@@ -2643,6 +2655,20 @@ class RandomizeVisitor final : public VNVisitor { AstVar* const refvarp = new AstVar{exprp->fileline(), VVarType::MEMBER, "__Varg"s + std::to_string(++argn), exprp->dtypep()}; -+ withp->foreach([&](AstNodeExpr* exp){ -+ if(exp->dtypep() == argp->exprp()->dtypep()){ -+ AstVarRef* const replaceVar = new AstVarRef{exprp->fileline(), refvarp, VAccess::READWRITE}; -+ exp->replaceWith(replaceVar); -+ replaceVar->user1(true); -+ replaceVar->varp()->user2p(m_modp); -+ pushDeletep(exp); -+ -+ } -+ }); ++ refvarp->setStdRandomizeArg(); ++ // Replace argument occurrences in 'with' clause with __Varg* reference. ++ if (withp) { ++ withp->foreach([&](AstNodeExpr* exp) { ++ if (isSimilarNode(exp, exprp)) { ++ AstVarRef* const replaceVar ++ = new AstVarRef{exprp->fileline(), refvarp, VAccess::READWRITE}; ++ exp->replaceWith(replaceVar); ++ replaceVar->user1(exp->user1()); ++ replaceVar->varp()->user2p(m_modp); ++ VL_DO_DANGLING(pushDeletep(exp), exp); ++ } ++ }); ++ } refvarp->direction(VDirection::REF); refvarp->funcLocal(true); refvarp->lifetime(VLifetime::AUTOMATIC_EXPLICIT); -@@ -2669,6 +2660,33 @@ class RandomizeVisitor final : public VNVisitor { +@@ -2665,6 +2691,31 @@ class RandomizeVisitor final : public VNVisitor { VN_AS(randomizeFuncp->fvarp(), Var), VAccess::READ}, basicMethodp}}); } + if (withp) { -+ FileLine* const fl = nodep->fileline(); -+ // withCapturep -+ // = std::make_unique(withp->exprp(), m_modp, nullptr); -+ // withCapturep->addFunctionArguments(randomizeFuncp); -+ // Clear old constraints and variables for std::randomize with clause -+ if (stdrand) { -+ randomizeFuncp->addStmtsp( -+ implementConstraintsClearAll(randomizeFuncp->fileline(), stdrand)); -+ } -+ AstNode* const capturedTreep = withp->exprp()->unlinkFrBackWithNext(); -+ randomizeFuncp->addStmtsp(capturedTreep); -+ capturedTreep->dumpTreeJson(cout); -+ { -+ ConstraintExprVisitor{m_memberMap, capturedTreep, randomizeFuncp, -+ stdrand, nullptr, m_writtenVars}; -+ } -+ AstCExpr* const solverCallp = new AstCExpr{fl}; -+ solverCallp->dtypeSetBit(); -+ solverCallp->add(new AstVarRef{fl, stdrand, VAccess::READWRITE}); -+ solverCallp->add(".next()"); -+ AstVar* const fvarp = VN_AS(randomizeFuncp->fvarp(), Var); -+ AstVarRef* const retvalReadp = new AstVarRef{fl, fvarp, VAccess::READ}; -+ AstNodeExpr* const andExprp = new AstAnd{fl, retvalReadp, solverCallp}; -+ AstVarRef* const retvalWritep = new AstVarRef{fl, fvarp, VAccess::WRITE}; -+ randomizeFuncp->addStmtsp(new AstAssign{fl, retvalWritep, andExprp}); -+ } - // Remove With nodes from pins as they have been processed - for (AstNode* pinp = nodep->pinsp(); pinp;) { - AstNode* const nextp = pinp->nextp(); -@@ -2677,6 +2695,7 @@ class RandomizeVisitor final : public VNVisitor { - } - pinp = nextp; - } -+ // if(withp)VL_DO_DANGLING(withp, withp); - // Replace the node with a call to that function - nodep->name(randomizeFuncp->name()); - nodep->taskp(randomizeFuncp); - -From d9462e0b1594d382c8672ae0b3489b2d75693cda Mon Sep 17 00:00:00 2001 -From: github action -Date: Thu, 20 Nov 2025 22:24:54 +0000 -Subject: [PATCH 06/29] Apply 'make format' - ---- - src/V3Randomize.cpp | 64 ++++++++++++++++++++++----------------------- - 1 file changed, 32 insertions(+), 32 deletions(-) - -diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp -index 2900cdc7e0d..fbf00f72d26 100644 ---- a/src/V3Randomize.cpp -+++ b/src/V3Randomize.cpp -@@ -2611,10 +2611,10 @@ class RandomizeVisitor final : public VNVisitor { - std::unique_ptr withCapturep; - int argn = 0; - AstWith* withp = nullptr; -- for (AstNode* pinp = nodep->pinsp(); pinp; pinp = pinp->nextp()){ -+ for (AstNode* pinp = nodep->pinsp(); pinp; pinp = pinp->nextp()) { - AstArg* const argp = VN_CAST(pinp, Arg); -- withp = VN_IS(pinp, With)?VN_AS(pinp,With):nullptr; -- if(withp) break; -+ withp = VN_IS(pinp, With) ? VN_AS(pinp, With) : nullptr; -+ if (withp) break; - } - - for (AstNode* pinp = nodep->pinsp(); pinp; pinp = pinp->nextp()) { -@@ -2628,14 +2628,14 @@ class RandomizeVisitor final : public VNVisitor { - AstVar* const refvarp - = new AstVar{exprp->fileline(), VVarType::MEMBER, - "__Varg"s + std::to_string(++argn), exprp->dtypep()}; -- withp->foreach([&](AstNodeExpr* exp){ -- if(exp->dtypep() == argp->exprp()->dtypep()){ -- AstVarRef* const replaceVar = new AstVarRef{exprp->fileline(), refvarp, VAccess::READWRITE}; -+ withp->foreach([&](AstNodeExpr* exp) { -+ if (exp->dtypep() == argp->exprp()->dtypep()) { -+ AstVarRef* const replaceVar -+ = new AstVarRef{exprp->fileline(), refvarp, VAccess::READWRITE}; - exp->replaceWith(replaceVar); - replaceVar->user1(true); - replaceVar->varp()->user2p(m_modp); - pushDeletep(exp); -- - } - }); - refvarp->direction(VDirection::REF); -@@ -2661,32 +2661,32 @@ class RandomizeVisitor final : public VNVisitor { - basicMethodp}}); - } - if (withp) { -- FileLine* const fl = nodep->fileline(); -- // withCapturep -- // = std::make_unique(withp->exprp(), m_modp, nullptr); -- // withCapturep->addFunctionArguments(randomizeFuncp); -- // Clear old constraints and variables for std::randomize with clause -- if (stdrand) { -- randomizeFuncp->addStmtsp( -- implementConstraintsClearAll(randomizeFuncp->fileline(), stdrand)); -- } -- AstNode* const capturedTreep = withp->exprp()->unlinkFrBackWithNext(); -- randomizeFuncp->addStmtsp(capturedTreep); -- capturedTreep->dumpTreeJson(cout); -- { -- ConstraintExprVisitor{m_memberMap, capturedTreep, randomizeFuncp, -- stdrand, nullptr, m_writtenVars}; -- } -- AstCExpr* const solverCallp = new AstCExpr{fl}; -- solverCallp->dtypeSetBit(); -- solverCallp->add(new AstVarRef{fl, stdrand, VAccess::READWRITE}); -- solverCallp->add(".next()"); -- AstVar* const fvarp = VN_AS(randomizeFuncp->fvarp(), Var); -- AstVarRef* const retvalReadp = new AstVarRef{fl, fvarp, VAccess::READ}; -- AstNodeExpr* const andExprp = new AstAnd{fl, retvalReadp, solverCallp}; -- AstVarRef* const retvalWritep = new AstVarRef{fl, fvarp, VAccess::WRITE}; -- randomizeFuncp->addStmtsp(new AstAssign{fl, retvalWritep, andExprp}); + FileLine* const fl = nodep->fileline(); -+ // withCapturep -+ // = std::make_unique(withp->exprp(), m_modp, nullptr); -+ // withCapturep->addFunctionArguments(randomizeFuncp); ++ withCapturep = std::make_unique(withp->exprp(), m_modp, nullptr); ++ withCapturep->addFunctionArguments(randomizeFuncp); + // Clear old constraints and variables for std::randomize with clause + if (stdrand) { + randomizeFuncp->addStmtsp( @@ -366,1565 +221,23 @@ index 2900cdc7e0d..fbf00f72d26 100644 + } + AstNode* const capturedTreep = withp->exprp()->unlinkFrBackWithNext(); + randomizeFuncp->addStmtsp(capturedTreep); -+ capturedTreep->dumpTreeJson(cout); + { + ConstraintExprVisitor{m_memberMap, capturedTreep, randomizeFuncp, + stdrand, nullptr, m_writtenVars}; - } ++ } + AstCExpr* const solverCallp = new AstCExpr{fl}; + solverCallp->dtypeSetBit(); + solverCallp->add(new AstVarRef{fl, stdrand, VAccess::READWRITE}); + solverCallp->add(".next()"); + AstVar* const fvarp = VN_AS(randomizeFuncp->fvarp(), Var); -+ AstVarRef* const retvalReadp = new AstVarRef{fl, fvarp, VAccess::READ}; -+ AstNodeExpr* const andExprp = new AstAnd{fl, retvalReadp, solverCallp}; -+ AstVarRef* const retvalWritep = new AstVarRef{fl, fvarp, VAccess::WRITE}; -+ randomizeFuncp->addStmtsp(new AstAssign{fl, retvalWritep, andExprp}); ++ AstNodeExpr* const andExprp ++ = new AstAnd{fl, new AstVarRef{fl, fvarp, VAccess::READ}, solverCallp}; ++ randomizeFuncp->addStmtsp( ++ new AstAssign{fl, new AstVarRef{fl, fvarp, VAccess::WRITE}, andExprp}); + } // Remove With nodes from pins as they have been processed for (AstNode* pinp = nodep->pinsp(); pinp;) { AstNode* const nextp = pinp->nextp(); - -From ea39784044681c5ef64a5e36e20d0a6c288d1088 Mon Sep 17 00:00:00 2001 -From: Udaya Raj Subedi <075bei047.udaya@pcampus.edu.np> -Date: Thu, 20 Nov 2025 23:29:07 +0100 -Subject: [PATCH 07/29] minor fix - ---- - recom_verilator.sh | 4 ++++ - src/V3Randomize.cpp | 2 +- - 2 files changed, 5 insertions(+), 1 deletion(-) - create mode 100755 recom_verilator.sh - -diff --git a/recom_verilator.sh b/recom_verilator.sh -new file mode 100755 -index 00000000000..f09c5748eb5 ---- /dev/null -+++ b/recom_verilator.sh -@@ -0,0 +1,4 @@ -+autoconf -+export VERILATOR_ROOT=`pwd` # if your shell is bash -+./configure -+make -j `nproc` -diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp -index fbf00f72d26..64506ec53fb 100644 ---- a/src/V3Randomize.cpp -+++ b/src/V3Randomize.cpp -@@ -2633,7 +2633,7 @@ class RandomizeVisitor final : public VNVisitor { - AstVarRef* const replaceVar - = new AstVarRef{exprp->fileline(), refvarp, VAccess::READWRITE}; - exp->replaceWith(replaceVar); -- replaceVar->user1(true); -+ replaceVar->user1(exp->user1()); - replaceVar->varp()->user2p(m_modp); - pushDeletep(exp); - } - -From 6f007139f6e40b6c9e12c23de84a113105e18cc5 Mon Sep 17 00:00:00 2001 -From: Udaya Raj Subedi <075bei047.udaya@pcampus.edu.np> -Date: Thu, 20 Nov 2025 23:29:54 +0100 -Subject: [PATCH 08/29] removed - ---- - recom_verilator.sh | 4 ---- - 1 file changed, 4 deletions(-) - delete mode 100755 recom_verilator.sh - -diff --git a/recom_verilator.sh b/recom_verilator.sh -deleted file mode 100755 -index f09c5748eb5..00000000000 ---- a/recom_verilator.sh -+++ /dev/null -@@ -1,4 +0,0 @@ --autoconf --export VERILATOR_ROOT=`pwd` # if your shell is bash --./configure --make -j `nproc` - -From 8d759a11821a2e4dc26b2a10a7d0229a33ebb869 Mon Sep 17 00:00:00 2001 -From: Udaya Raj Subedi <075bei047.udaya@pcampus.edu.np> -Date: Thu, 20 Nov 2025 23:38:08 +0100 -Subject: [PATCH 09/29] remove unused var - ---- - src/V3Randomize.cpp | 1 - - 1 file changed, 1 deletion(-) - -diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp -index 64506ec53fb..81e64b70147 100644 ---- a/src/V3Randomize.cpp -+++ b/src/V3Randomize.cpp -@@ -2612,7 +2612,6 @@ class RandomizeVisitor final : public VNVisitor { - int argn = 0; - AstWith* withp = nullptr; - for (AstNode* pinp = nodep->pinsp(); pinp; pinp = pinp->nextp()) { -- AstArg* const argp = VN_CAST(pinp, Arg); - withp = VN_IS(pinp, With) ? VN_AS(pinp, With) : nullptr; - if (withp) break; - } - -From 37b645f076343ad23bc678a6ae58dcd032f47c89 Mon Sep 17 00:00:00 2001 -From: Udaya Raj Subedi <075bei047.udaya@pcampus.edu.np> -Date: Fri, 21 Nov 2025 00:00:20 +0100 -Subject: [PATCH 10/29] remove debug - ---- - src/V3Randomize.cpp | 1 - - 1 file changed, 1 deletion(-) - -diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp -index 81e64b70147..5c70c95ebbc 100644 ---- a/src/V3Randomize.cpp -+++ b/src/V3Randomize.cpp -@@ -2671,7 +2671,6 @@ class RandomizeVisitor final : public VNVisitor { - } - AstNode* const capturedTreep = withp->exprp()->unlinkFrBackWithNext(); - randomizeFuncp->addStmtsp(capturedTreep); -- capturedTreep->dumpTreeJson(cout); - { - ConstraintExprVisitor{m_memberMap, capturedTreep, randomizeFuncp, - stdrand, nullptr, m_writtenVars}; - -From a0c9c5743385cacacb431445665b9b40ea6f7159 Mon Sep 17 00:00:00 2001 -From: Udaya Raj Subedi <075bei047.udaya@pcampus.edu.np> -Date: Fri, 21 Nov 2025 12:43:43 +0100 -Subject: [PATCH 11/29] debug of teh rror - ---- - src/V3Randomize.cpp | 26 +++++++++++++++++++------- - 1 file changed, 19 insertions(+), 7 deletions(-) - -diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp -index 5c70c95ebbc..1b7314c5fc8 100644 ---- a/src/V3Randomize.cpp -+++ b/src/V3Randomize.cpp -@@ -176,7 +176,8 @@ class RandomizeMarkVisitor final : public VNVisitor { - } else if (const AstMemberSel* const memberselp = VN_CAST(exprp, MemberSel)) { - if (memberselp->varp() == varp) return true; - } else if (const AstArraySel* const arrselp = VN_CAST(exprp, ArraySel)) { -- if (arrselp->fromp()->dtypep() == varp->dtypep()) return true; -+ // if (arrselp->fromp()->dtypep() == varp->dtypep()) return true; -+ if (VN_AS(arrselp->fromp(), VarRef)->varp() == varp) return true; - } - } - return false; -@@ -1429,6 +1430,7 @@ class CaptureVisitor final : public VNVisitor { - - AstVar* getVar(AstVar* const varp) const { - const auto it = m_varCloneMap.find(varp); -+ if(it->second->origName().rfind("__Varg",0)==0) return nullptr; - if (it == m_varCloneMap.end()) return nullptr; - return it->second; - } -@@ -1588,7 +1590,11 @@ class CaptureVisitor final : public VNVisitor { - // Keeping classOrPackagep will cause a broken link after inlining - varrefp->classOrPackagep(nullptr); - } -- funcp->addStmtsp(getVar(varrefp->varp())); -+ // funcp->addStmtsp(getVar(varrefp->varp())); -+ if(!getVar(varrefp->varp())) { -+ -+ } -+ - } else { - UASSERT_OBJ(VN_IS(argp->exprp(), ThisRef), argp->exprp(), "Wrong arg expression"); - funcp->addStmtsp(m_thisp); -@@ -2628,8 +2634,13 @@ class RandomizeVisitor final : public VNVisitor { - = new AstVar{exprp->fileline(), VVarType::MEMBER, - "__Varg"s + std::to_string(++argn), exprp->dtypep()}; - withp->foreach([&](AstNodeExpr* exp) { -- if (exp->dtypep() == argp->exprp()->dtypep()) { -- AstVarRef* const replaceVar -+ // if (exp->isSame(exprp)) { -+ // if (exp->dtypep()==exprp->dtypep()) { -+ if( (VN_IS(exprp,VarRef)&&VN_IS(exp,VarRef))?(VN_AS(exp,VarRef)->varp()==VN_AS(exprp,VarRef)->varp()): -+ ((VN_IS(exprp,MemberSel)&&VN_IS(exp,MemberSel))?(exp->op1p()->op1p()==exprp->op1p()->op1p()):(0))){ -+ // if ((VN_IS(exp,VarRef)&&VN_IS(exprp,VarRef))?(VN_AS(exp,VarRef)->varp()==VN_AS(exprp,VarRef)->varp()): -+ // ((VN_IS(exp,MemberSel)&&VN_IS(exprp,MemberSel))?(VN_AS(exp,MemberSel)->varp()==VN_AS(exprp,MemberSel)->varp()):0)){ -+ AstVarRef* const replaceVar - = new AstVarRef{exprp->fileline(), refvarp, VAccess::READWRITE}; - exp->replaceWith(replaceVar); - replaceVar->user1(exp->user1()); -@@ -2661,9 +2672,9 @@ class RandomizeVisitor final : public VNVisitor { - } - if (withp) { - FileLine* const fl = nodep->fileline(); -- // withCapturep -- // = std::make_unique(withp->exprp(), m_modp, nullptr); -- // withCapturep->addFunctionArguments(randomizeFuncp); -+ withCapturep -+ = std::make_unique(withp->exprp(), m_modp, nullptr); -+ withCapturep->addFunctionArguments(randomizeFuncp); - // Clear old constraints and variables for std::randomize with clause - if (stdrand) { - randomizeFuncp->addStmtsp( -@@ -2700,6 +2711,7 @@ class RandomizeVisitor final : public VNVisitor { - nodep->dtypeFrom(randomizeFuncp->dtypep()); - if (VN_IS(m_modp, Class)) nodep->classOrPackagep(m_modp); - if (withCapturep) nodep->addPinsp(withCapturep->getArgs()); -+ withCapturep->getArgs()->dumpTreeJson(cout); - UINFOTREE(9, nodep, "", "std::rnd-call"); - UINFOTREE(9, randomizeFuncp, "", "std::rnd-func"); - return; - -From 18c26b122fe0e13e1b71956335cbc36d72be80ad Mon Sep 17 00:00:00 2001 -From: Udaya Raj Subedi <075bei047.udaya@pcampus.edu.np> -Date: Fri, 21 Nov 2025 14:37:09 +0100 -Subject: [PATCH 12/29] NO idea - ---- - src/V3Randomize.cpp | 20 +++++++++----------- - 1 file changed, 9 insertions(+), 11 deletions(-) - -diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp -index 1b7314c5fc8..892b3967987 100644 ---- a/src/V3Randomize.cpp -+++ b/src/V3Randomize.cpp -@@ -1590,11 +1590,7 @@ class CaptureVisitor final : public VNVisitor { - // Keeping classOrPackagep will cause a broken link after inlining - varrefp->classOrPackagep(nullptr); - } -- // funcp->addStmtsp(getVar(varrefp->varp())); -- if(!getVar(varrefp->varp())) { -- -- } -- -+ funcp->addStmtsp(getVar(varrefp->varp())); - } else { - UASSERT_OBJ(VN_IS(argp->exprp(), ThisRef), argp->exprp(), "Wrong arg expression"); - funcp->addStmtsp(m_thisp); -@@ -2638,9 +2634,7 @@ class RandomizeVisitor final : public VNVisitor { - // if (exp->dtypep()==exprp->dtypep()) { - if( (VN_IS(exprp,VarRef)&&VN_IS(exp,VarRef))?(VN_AS(exp,VarRef)->varp()==VN_AS(exprp,VarRef)->varp()): - ((VN_IS(exprp,MemberSel)&&VN_IS(exp,MemberSel))?(exp->op1p()->op1p()==exprp->op1p()->op1p()):(0))){ -- // if ((VN_IS(exp,VarRef)&&VN_IS(exprp,VarRef))?(VN_AS(exp,VarRef)->varp()==VN_AS(exprp,VarRef)->varp()): -- // ((VN_IS(exp,MemberSel)&&VN_IS(exprp,MemberSel))?(VN_AS(exp,MemberSel)->varp()==VN_AS(exprp,MemberSel)->varp()):0)){ -- AstVarRef* const replaceVar -+ AstVarRef* const replaceVar - = new AstVarRef{exprp->fileline(), refvarp, VAccess::READWRITE}; - exp->replaceWith(replaceVar); - replaceVar->user1(exp->user1()); -@@ -2699,9 +2693,9 @@ class RandomizeVisitor final : public VNVisitor { - // Remove With nodes from pins as they have been processed - for (AstNode* pinp = nodep->pinsp(); pinp;) { - AstNode* const nextp = pinp->nextp(); -- if (VN_IS(pinp, With)) { -+ // if (VN_IS(pinp, With)) { - VL_DO_DANGLING(pinp->unlinkFrBack()->deleteTree(), pinp); -- } -+ // } - pinp = nextp; - } - // if(withp)VL_DO_DANGLING(withp, withp); -@@ -2711,7 +2705,11 @@ class RandomizeVisitor final : public VNVisitor { - nodep->dtypeFrom(randomizeFuncp->dtypep()); - if (VN_IS(m_modp, Class)) nodep->classOrPackagep(m_modp); - if (withCapturep) nodep->addPinsp(withCapturep->getArgs()); -- withCapturep->getArgs()->dumpTreeJson(cout); -+ -+ // for (AstArg* argp = withCapturep->getArgs(); argp; argp = VN_AS(argp->nextp(), Arg)){ -+ // if(VN_IS(argp->exprp(),VarRef) && VN_AS(argp->exprp(),VarRef)->varp()->origName().rfind("__Varg",0)!=0) -+ // nodep->addPinsp(argp->cloneTreePure(false)); -+ // } - UINFOTREE(9, nodep, "", "std::rnd-call"); - UINFOTREE(9, randomizeFuncp, "", "std::rnd-func"); - return; - -From c9b90c1ccc514f8dbd773c44114f356357f06f2d Mon Sep 17 00:00:00 2001 -From: Udaya Raj Subedi <075bei047.udaya@pcampus.edu.np> -Date: Fri, 21 Nov 2025 15:24:53 +0100 -Subject: [PATCH 13/29] GOT SOMETHING - ---- - src/V3Randomize.cpp | 10 +++++----- - 1 file changed, 5 insertions(+), 5 deletions(-) - -diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp -index 892b3967987..793a0c2be8b 100644 ---- a/src/V3Randomize.cpp -+++ b/src/V3Randomize.cpp -@@ -1502,6 +1502,7 @@ class CaptureVisitor final : public VNVisitor { - if (m_ignore.count(nodep)) return; - m_ignore.emplace(nodep); - UASSERT_OBJ(nodep->varp(), nodep, "Variable unlinked"); -+ if(nodep->varp()->origName().rfind("__Varg",0)==0) return; - CaptureMode capMode = getVarRefCaptureMode(nodep); - if (mode(capMode) == CaptureMode::CAP_NO) return; - if (mode(capMode) == CaptureMode::CAP_VALUE) captureRefByValue(nodep, capMode); -@@ -2630,10 +2631,9 @@ class RandomizeVisitor final : public VNVisitor { - = new AstVar{exprp->fileline(), VVarType::MEMBER, - "__Varg"s + std::to_string(++argn), exprp->dtypep()}; - withp->foreach([&](AstNodeExpr* exp) { -- // if (exp->isSame(exprp)) { -- // if (exp->dtypep()==exprp->dtypep()) { - if( (VN_IS(exprp,VarRef)&&VN_IS(exp,VarRef))?(VN_AS(exp,VarRef)->varp()==VN_AS(exprp,VarRef)->varp()): -- ((VN_IS(exprp,MemberSel)&&VN_IS(exp,MemberSel))?(exp->op1p()->op1p()==exprp->op1p()->op1p()):(0))){ -+ ((VN_IS(exprp,MemberSel)&&VN_IS(exp,MemberSel))?(exp->op1p()->op1p()==exprp->op1p()->op1p())&&(VN_AS(exp, MemberSel)->varp()==VN_AS(exprp,MemberSel)->varp()): -+ ((VN_IS(exprp,ArraySel)&&VN_IS(exp,ArraySel)))?((exprp->op1p()->op1p()==exp->op1p()->op1p())&& (VN_AS(exprp->op2p()->op1p(),VarRef)->varp()==VN_AS(exp->op2p()->op1p(),VarRef)->varp()) ):(0))){ - AstVarRef* const replaceVar - = new AstVarRef{exprp->fileline(), refvarp, VAccess::READWRITE}; - exp->replaceWith(replaceVar); -@@ -2693,9 +2693,9 @@ class RandomizeVisitor final : public VNVisitor { - // Remove With nodes from pins as they have been processed - for (AstNode* pinp = nodep->pinsp(); pinp;) { - AstNode* const nextp = pinp->nextp(); -- // if (VN_IS(pinp, With)) { -+ if (VN_IS(pinp, With)) { - VL_DO_DANGLING(pinp->unlinkFrBack()->deleteTree(), pinp); -- // } -+ } - pinp = nextp; - } - // if(withp)VL_DO_DANGLING(withp, withp); - -From e9da3882bd36e024fa3b335e2ef9b3930d1c59b0 Mon Sep 17 00:00:00 2001 -From: github action -Date: Fri, 21 Nov 2025 14:26:09 +0000 -Subject: [PATCH 14/29] Apply 'make format' - ---- - src/V3Randomize.cpp | 27 ++++++++++++++++++--------- - 1 file changed, 18 insertions(+), 9 deletions(-) - -diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp -index 793a0c2be8b..6fa5b02257d 100644 ---- a/src/V3Randomize.cpp -+++ b/src/V3Randomize.cpp -@@ -1430,7 +1430,7 @@ class CaptureVisitor final : public VNVisitor { - - AstVar* getVar(AstVar* const varp) const { - const auto it = m_varCloneMap.find(varp); -- if(it->second->origName().rfind("__Varg",0)==0) return nullptr; -+ if (it->second->origName().rfind("__Varg", 0) == 0) return nullptr; - if (it == m_varCloneMap.end()) return nullptr; - return it->second; - } -@@ -1502,7 +1502,7 @@ class CaptureVisitor final : public VNVisitor { - if (m_ignore.count(nodep)) return; - m_ignore.emplace(nodep); - UASSERT_OBJ(nodep->varp(), nodep, "Variable unlinked"); -- if(nodep->varp()->origName().rfind("__Varg",0)==0) return; -+ if (nodep->varp()->origName().rfind("__Varg", 0) == 0) return; - CaptureMode capMode = getVarRefCaptureMode(nodep); - if (mode(capMode) == CaptureMode::CAP_NO) return; - if (mode(capMode) == CaptureMode::CAP_VALUE) captureRefByValue(nodep, capMode); -@@ -2631,9 +2631,17 @@ class RandomizeVisitor final : public VNVisitor { - = new AstVar{exprp->fileline(), VVarType::MEMBER, - "__Varg"s + std::to_string(++argn), exprp->dtypep()}; - withp->foreach([&](AstNodeExpr* exp) { -- if( (VN_IS(exprp,VarRef)&&VN_IS(exp,VarRef))?(VN_AS(exp,VarRef)->varp()==VN_AS(exprp,VarRef)->varp()): -- ((VN_IS(exprp,MemberSel)&&VN_IS(exp,MemberSel))?(exp->op1p()->op1p()==exprp->op1p()->op1p())&&(VN_AS(exp, MemberSel)->varp()==VN_AS(exprp,MemberSel)->varp()): -- ((VN_IS(exprp,ArraySel)&&VN_IS(exp,ArraySel)))?((exprp->op1p()->op1p()==exp->op1p()->op1p())&& (VN_AS(exprp->op2p()->op1p(),VarRef)->varp()==VN_AS(exp->op2p()->op1p(),VarRef)->varp()) ):(0))){ -+ if ((VN_IS(exprp, VarRef) && VN_IS(exp, VarRef)) -+ ? (VN_AS(exp, VarRef)->varp() == VN_AS(exprp, VarRef)->varp()) -+ : ((VN_IS(exprp, MemberSel) && VN_IS(exp, MemberSel)) -+ ? (exp->op1p()->op1p() == exprp->op1p()->op1p()) -+ && (VN_AS(exp, MemberSel)->varp() -+ == VN_AS(exprp, MemberSel)->varp()) -+ : ((VN_IS(exprp, ArraySel) && VN_IS(exp, ArraySel))) -+ ? ((exprp->op1p()->op1p() == exp->op1p()->op1p()) -+ && (VN_AS(exprp->op2p()->op1p(), VarRef)->varp() -+ == VN_AS(exp->op2p()->op1p(), VarRef)->varp())) -+ : (0))) { - AstVarRef* const replaceVar - = new AstVarRef{exprp->fileline(), refvarp, VAccess::READWRITE}; - exp->replaceWith(replaceVar); -@@ -2666,8 +2674,7 @@ class RandomizeVisitor final : public VNVisitor { - } - if (withp) { - FileLine* const fl = nodep->fileline(); -- withCapturep -- = std::make_unique(withp->exprp(), m_modp, nullptr); -+ withCapturep = std::make_unique(withp->exprp(), m_modp, nullptr); - withCapturep->addFunctionArguments(randomizeFuncp); - // Clear old constraints and variables for std::randomize with clause - if (stdrand) { -@@ -2706,8 +2713,10 @@ class RandomizeVisitor final : public VNVisitor { - if (VN_IS(m_modp, Class)) nodep->classOrPackagep(m_modp); - if (withCapturep) nodep->addPinsp(withCapturep->getArgs()); - -- // for (AstArg* argp = withCapturep->getArgs(); argp; argp = VN_AS(argp->nextp(), Arg)){ -- // if(VN_IS(argp->exprp(),VarRef) && VN_AS(argp->exprp(),VarRef)->varp()->origName().rfind("__Varg",0)!=0) -+ // for (AstArg* argp = withCapturep->getArgs(); argp; argp = VN_AS(argp->nextp(), -+ // Arg)){ -+ // if(VN_IS(argp->exprp(),VarRef) && -+ // VN_AS(argp->exprp(),VarRef)->varp()->origName().rfind("__Varg",0)!=0) - // nodep->addPinsp(argp->cloneTreePure(false)); - // } - UINFOTREE(9, nodep, "", "std::rnd-call"); - -From ed16633ffb86d583562d3e731b18b4604c530a0c Mon Sep 17 00:00:00 2001 -From: Udaya Raj Subedi <075bei047.udaya@pcampus.edu.np> -Date: Fri, 21 Nov 2025 15:49:55 +0100 -Subject: [PATCH 15/29] with guard - ---- - src/V3Randomize.cpp | 5 ++++- - 1 file changed, 4 insertions(+), 1 deletion(-) - -diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp -index 6fa5b02257d..739ffaa723f 100644 ---- a/src/V3Randomize.cpp -+++ b/src/V3Randomize.cpp -@@ -2630,7 +2630,9 @@ class RandomizeVisitor final : public VNVisitor { - AstVar* const refvarp - = new AstVar{exprp->fileline(), VVarType::MEMBER, - "__Varg"s + std::to_string(++argn), exprp->dtypep()}; -- withp->foreach([&](AstNodeExpr* exp) { -+ -+ if(withp){ -+ withp->foreach([&](AstNodeExpr* exp) { - if ((VN_IS(exprp, VarRef) && VN_IS(exp, VarRef)) - ? (VN_AS(exp, VarRef)->varp() == VN_AS(exprp, VarRef)->varp()) - : ((VN_IS(exprp, MemberSel) && VN_IS(exp, MemberSel)) -@@ -2650,6 +2652,7 @@ class RandomizeVisitor final : public VNVisitor { - pushDeletep(exp); - } - }); -+ } - refvarp->direction(VDirection::REF); - refvarp->funcLocal(true); - refvarp->lifetime(VLifetime::AUTOMATIC_EXPLICIT); - -From 862a09519060648697b8d104fd503add033d6e41 Mon Sep 17 00:00:00 2001 -From: github action -Date: Fri, 21 Nov 2025 14:51:18 +0000 -Subject: [PATCH 16/29] Apply 'make format' - ---- - src/V3Randomize.cpp | 42 +++++++++++++++++++++--------------------- - 1 file changed, 21 insertions(+), 21 deletions(-) - -diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp -index 739ffaa723f..3b3a07ba626 100644 ---- a/src/V3Randomize.cpp -+++ b/src/V3Randomize.cpp -@@ -2630,28 +2630,28 @@ class RandomizeVisitor final : public VNVisitor { - AstVar* const refvarp - = new AstVar{exprp->fileline(), VVarType::MEMBER, - "__Varg"s + std::to_string(++argn), exprp->dtypep()}; -- -- if(withp){ -+ -+ if (withp) { - withp->foreach([&](AstNodeExpr* exp) { -- if ((VN_IS(exprp, VarRef) && VN_IS(exp, VarRef)) -- ? (VN_AS(exp, VarRef)->varp() == VN_AS(exprp, VarRef)->varp()) -- : ((VN_IS(exprp, MemberSel) && VN_IS(exp, MemberSel)) -- ? (exp->op1p()->op1p() == exprp->op1p()->op1p()) -- && (VN_AS(exp, MemberSel)->varp() -- == VN_AS(exprp, MemberSel)->varp()) -- : ((VN_IS(exprp, ArraySel) && VN_IS(exp, ArraySel))) -- ? ((exprp->op1p()->op1p() == exp->op1p()->op1p()) -- && (VN_AS(exprp->op2p()->op1p(), VarRef)->varp() -- == VN_AS(exp->op2p()->op1p(), VarRef)->varp())) -- : (0))) { -- AstVarRef* const replaceVar -- = new AstVarRef{exprp->fileline(), refvarp, VAccess::READWRITE}; -- exp->replaceWith(replaceVar); -- replaceVar->user1(exp->user1()); -- replaceVar->varp()->user2p(m_modp); -- pushDeletep(exp); -- } -- }); -+ if ((VN_IS(exprp, VarRef) && VN_IS(exp, VarRef)) -+ ? (VN_AS(exp, VarRef)->varp() == VN_AS(exprp, VarRef)->varp()) -+ : ((VN_IS(exprp, MemberSel) && VN_IS(exp, MemberSel)) -+ ? (exp->op1p()->op1p() == exprp->op1p()->op1p()) -+ && (VN_AS(exp, MemberSel)->varp() -+ == VN_AS(exprp, MemberSel)->varp()) -+ : ((VN_IS(exprp, ArraySel) && VN_IS(exp, ArraySel))) -+ ? ((exprp->op1p()->op1p() == exp->op1p()->op1p()) -+ && (VN_AS(exprp->op2p()->op1p(), VarRef)->varp() -+ == VN_AS(exp->op2p()->op1p(), VarRef)->varp())) -+ : (0))) { -+ AstVarRef* const replaceVar -+ = new AstVarRef{exprp->fileline(), refvarp, VAccess::READWRITE}; -+ exp->replaceWith(replaceVar); -+ replaceVar->user1(exp->user1()); -+ replaceVar->varp()->user2p(m_modp); -+ pushDeletep(exp); -+ } -+ }); - } - refvarp->direction(VDirection::REF); - refvarp->funcLocal(true); - -From 23b87e737e0cd49b1aa522f2bf268ea395acac3a Mon Sep 17 00:00:00 2001 -From: Yilou Wang -Date: Wed, 26 Nov 2025 15:11:40 +0100 -Subject: [PATCH 17/29] make passes and updates the test - ---- - src/V3Randomize.cpp | 5 +++-- - test_regress/t/t_std_randomize.v | 10 ++++++++++ - 2 files changed, 13 insertions(+), 2 deletions(-) - -diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp -index 83cb8068af7..0d5e854570c 100644 ---- a/src/V3Randomize.cpp -+++ b/src/V3Randomize.cpp -@@ -538,15 +538,16 @@ class RandomizeMarkVisitor final : public VNVisitor { - AstNodeExpr* exprp = argp->exprp(); - while (exprp) { - AstVar* randVarp = nullptr; -+ AstVarRef* varrefp = nullptr; - if (AstMemberSel* const memberSelp = VN_CAST(exprp, MemberSel)) { - randVarp = memberSelp->varp(); - exprp = memberSelp->fromp(); -- } else if (AstVarRef* varrefp = VN_CAST(exprp, VarRef)) { -+ } else if ((varrefp = VN_CAST(exprp, VarRef))) { - randVarp = varrefp->varp(); - varrefp->user1(true); - exprp = nullptr; - } else { -- AstVarRef* varrefp = VN_AS(VN_CAST(exprp, ArraySel)->fromp(), VarRef); -+ varrefp = VN_AS(VN_CAST(exprp, ArraySel)->fromp(), VarRef); - randVarp = varrefp->varp(); - varrefp->user1(true); - varrefp->access(VAccess::READWRITE); -diff --git a/test_regress/t/t_std_randomize.v b/test_regress/t/t_std_randomize.v -index 1a44dffa548..75579d4b41b 100644 ---- a/test_regress/t/t_std_randomize.v -+++ b/test_regress/t/t_std_randomize.v -@@ -98,6 +98,16 @@ module t_scope_std_randomize; - - `checkd(std::randomize(limit_95bits) with { foreach (limit_95bits[i]) { limit_95bits[i] < 96'd1000000000000;}}, 1); - foreach (limit_95bits[i]) if (limit_95bits[i] >= 96'd1000000000000) $stop; -+ -+ foreach (limit_63bits[i]) begin -+ `checkd(std::randomize(limit_63bits[i]) with { limit_63bits[i] >= 64'd50; limit_63bits[i] < 64'd100;}, 1); -+ if ((limit_63bits[i] < 64'd50) || (limit_63bits[i] >= 64'd100)) `stop; -+ end -+ -+ foreach (limit_95bits[i]) begin -+ `checkd(std::randomize(limit_95bits[i]) with { limit_95bits[i] >= 96'd50; limit_95bits[i] < 96'd1000;}, 1); -+ if (limit_95bits[i] < 96'd50 || limit_95bits[i] >= 96'd1000) `stop; -+ end - /* verilator lint_on WIDTHEXPAND */ - - $write("*-* All Finished *-*\n"); - -From 8bf0b88bfd563539633ae4f59ae3e13955340044 Mon Sep 17 00:00:00 2001 -From: Yilou Wang -Date: Wed, 26 Nov 2025 15:25:26 +0100 -Subject: [PATCH 18/29] refine v3randomize.cpp and add a mixed case in test - ---- - include/verilated_random.h | 1 - - src/V3Randomize.cpp | 45 ++++++++++++++++++-------------- - test_regress/t/t_std_randomize.v | 10 +++++++ - 3 files changed, 35 insertions(+), 21 deletions(-) - -diff --git a/include/verilated_random.h b/include/verilated_random.h -index 257f14302f2..0b68eadcf1d 100644 ---- a/include/verilated_random.h -+++ b/include/verilated_random.h -@@ -628,7 +628,6 @@ class VlStdRandomizer final : public VlRandomizer { - for (size_t i = 0; i < N_Depth; ++i) { basicStdRandomization(value.operator[](i), width); } - return true; - } -- - bool next() { return VlRandomizer::next(m_rng); } - }; - -diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp -index 0d5e854570c..682bc9ce67d 100644 ---- a/src/V3Randomize.cpp -+++ b/src/V3Randomize.cpp -@@ -1431,8 +1431,8 @@ class CaptureVisitor final : public VNVisitor { - - AstVar* getVar(AstVar* const varp) const { - const auto it = m_varCloneMap.find(varp); -- if (it->second->origName().rfind("__Varg", 0) == 0) return nullptr; - if (it == m_varCloneMap.end()) return nullptr; -+ if (it->second->origName().rfind("__Varg", 0) == 0) return nullptr; - return it->second; - } - -@@ -2632,19 +2632,32 @@ class RandomizeVisitor final : public VNVisitor { - = new AstVar{exprp->fileline(), VVarType::MEMBER, - "__Varg"s + std::to_string(++argn), exprp->dtypep()}; - -+ // Replace argument occurrences in 'with' clause with __Varg* reference. -+ // Uses "similarNode" matching (semantic equality, not pointer equality). - if (withp) { -+ auto similarNode = [](AstNodeExpr* withExpr, AstNodeExpr* argExpr) -> bool { -+ // VarRef: match by variable pointer -+ if (VN_IS(argExpr, VarRef) && VN_IS(withExpr, VarRef)) { -+ return VN_AS(withExpr, VarRef)->varp() -+ == VN_AS(argExpr, VarRef)->varp(); -+ } -+ // MemberSel: match by object and member -+ if (VN_IS(argExpr, MemberSel) && VN_IS(withExpr, MemberSel)) { -+ return (withExpr->op1p()->op1p() == argExpr->op1p()->op1p()) -+ && (VN_AS(withExpr, MemberSel)->varp() -+ == VN_AS(argExpr, MemberSel)->varp()); -+ } -+ // ArraySel: match by array base and index variable -+ if (VN_IS(argExpr, ArraySel) && VN_IS(withExpr, ArraySel)) { -+ return (withExpr->op1p()->op1p() == argExpr->op1p()->op1p()) -+ && (VN_AS(withExpr->op2p()->op1p(), VarRef)->varp() -+ == VN_AS(argExpr->op2p()->op1p(), VarRef)->varp()); -+ } -+ return false; -+ }; -+ - withp->foreach([&](AstNodeExpr* exp) { -- if ((VN_IS(exprp, VarRef) && VN_IS(exp, VarRef)) -- ? (VN_AS(exp, VarRef)->varp() == VN_AS(exprp, VarRef)->varp()) -- : ((VN_IS(exprp, MemberSel) && VN_IS(exp, MemberSel)) -- ? (exp->op1p()->op1p() == exprp->op1p()->op1p()) -- && (VN_AS(exp, MemberSel)->varp() -- == VN_AS(exprp, MemberSel)->varp()) -- : ((VN_IS(exprp, ArraySel) && VN_IS(exp, ArraySel))) -- ? ((exprp->op1p()->op1p() == exp->op1p()->op1p()) -- && (VN_AS(exprp->op2p()->op1p(), VarRef)->varp() -- == VN_AS(exp->op2p()->op1p(), VarRef)->varp())) -- : (0))) { -+ if (similarNode(exp, exprp)) { - AstVarRef* const replaceVar - = new AstVarRef{exprp->fileline(), refvarp, VAccess::READWRITE}; - exp->replaceWith(replaceVar); -@@ -2709,20 +2722,12 @@ class RandomizeVisitor final : public VNVisitor { - } - pinp = nextp; - } -- // if(withp)VL_DO_DANGLING(withp, withp); - // Replace the node with a call to that function - nodep->name(randomizeFuncp->name()); - nodep->taskp(randomizeFuncp); - nodep->dtypeFrom(randomizeFuncp->dtypep()); - if (VN_IS(m_modp, Class)) nodep->classOrPackagep(m_modp); - if (withCapturep) nodep->addPinsp(withCapturep->getArgs()); -- -- // for (AstArg* argp = withCapturep->getArgs(); argp; argp = VN_AS(argp->nextp(), -- // Arg)){ -- // if(VN_IS(argp->exprp(),VarRef) && -- // VN_AS(argp->exprp(),VarRef)->varp()->origName().rfind("__Varg",0)!=0) -- // nodep->addPinsp(argp->cloneTreePure(false)); -- // } - UINFOTREE(9, nodep, "", "std::rnd-call"); - UINFOTREE(9, randomizeFuncp, "", "std::rnd-func"); - return; -diff --git a/test_regress/t/t_std_randomize.v b/test_regress/t/t_std_randomize.v -index 75579d4b41b..a2de1594dc6 100644 ---- a/test_regress/t/t_std_randomize.v -+++ b/test_regress/t/t_std_randomize.v -@@ -108,6 +108,16 @@ module t_scope_std_randomize; - `checkd(std::randomize(limit_95bits[i]) with { limit_95bits[i] >= 96'd50; limit_95bits[i] < 96'd1000;}, 1); - if (limit_95bits[i] < 96'd50 || limit_95bits[i] >= 96'd1000) `stop; - end -+ -+ // Test mixed argument types (VarRef + MemberSel + ArraySel) with interdependent constraints -+ `checkd(std::randomize(addr, test.addr, limit_31bits[0]) with { -+ addr > 8'd10; addr < 8'd50; -+ test.addr > addr; test.addr < 8'd100; -+ limit_31bits[0] > test.addr; limit_31bits[0] < 31'd200; -+ }, 1); -+ if (addr <= 8'd10 || addr >= 8'd50) `stop; -+ if (test.addr <= addr || test.addr >= 8'd100) `stop; -+ if (limit_31bits[0] <= test.addr || limit_31bits[0] >= 31'd200) `stop; - /* verilator lint_on WIDTHEXPAND */ - - $write("*-* All Finished *-*\n"); - -From 4a502c807608a0d004c9e3cda3dee5bff1e88c0b Mon Sep 17 00:00:00 2001 -From: Yilou Wang -Date: Wed, 26 Nov 2025 15:32:29 +0100 -Subject: [PATCH 19/29] add empty checking to avoid crash - ---- - src/V3Randomize.cpp | 24 ++++++++++++++++++++---- - 1 file changed, 20 insertions(+), 4 deletions(-) - -diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp -index 682bc9ce67d..027665b017d 100644 ---- a/src/V3Randomize.cpp -+++ b/src/V3Randomize.cpp -@@ -2643,15 +2643,31 @@ class RandomizeVisitor final : public VNVisitor { - } - // MemberSel: match by object and member - if (VN_IS(argExpr, MemberSel) && VN_IS(withExpr, MemberSel)) { -- return (withExpr->op1p()->op1p() == argExpr->op1p()->op1p()) -+ AstNode* withObj = withExpr->op1p(); -+ AstNode* argObj = argExpr->op1p(); -+ if (!withObj || !argObj) return false; -+ withObj = withObj->op1p(); -+ argObj = argObj->op1p(); -+ return (withObj == argObj) - && (VN_AS(withExpr, MemberSel)->varp() - == VN_AS(argExpr, MemberSel)->varp()); - } - // ArraySel: match by array base and index variable - if (VN_IS(argExpr, ArraySel) && VN_IS(withExpr, ArraySel)) { -- return (withExpr->op1p()->op1p() == argExpr->op1p()->op1p()) -- && (VN_AS(withExpr->op2p()->op1p(), VarRef)->varp() -- == VN_AS(argExpr->op2p()->op1p(), VarRef)->varp()); -+ AstNode* withBase = withExpr->op1p(); -+ AstNode* argBase = argExpr->op1p(); -+ if (!withBase || !argBase) return false; -+ withBase = withBase->op1p(); -+ argBase = argBase->op1p(); -+ AstNode* withIdx = withExpr->op2p(); -+ AstNode* argIdx = argExpr->op2p(); -+ if (!withIdx || !argIdx) return false; -+ withIdx = withIdx->op1p(); -+ argIdx = argIdx->op1p(); -+ if (!VN_IS(withIdx, VarRef) || !VN_IS(argIdx, VarRef)) return false; -+ return (withBase == argBase) -+ && (VN_AS(withIdx, VarRef)->varp() -+ == VN_AS(argIdx, VarRef)->varp()); - } - return false; - }; - -From b2afe115baf75702a16e8390e595ee689de9f2be Mon Sep 17 00:00:00 2001 -From: Yilou Wang -Date: Wed, 26 Nov 2025 15:32:51 +0100 -Subject: [PATCH 20/29] update comments - ---- - src/V3Randomize.cpp | 13 +++++++------ - 1 file changed, 7 insertions(+), 6 deletions(-) - -diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp -index 027665b017d..3c7665ca17d 100644 ---- a/src/V3Randomize.cpp -+++ b/src/V3Randomize.cpp -@@ -2634,35 +2634,36 @@ class RandomizeVisitor final : public VNVisitor { - - // Replace argument occurrences in 'with' clause with __Varg* reference. - // Uses "similarNode" matching (semantic equality, not pointer equality). -+ // Supports: VarRef (x), MemberSel (obj.y), ArraySel (arr[i]) - if (withp) { - auto similarNode = [](AstNodeExpr* withExpr, AstNodeExpr* argExpr) -> bool { -- // VarRef: match by variable pointer -+ // VarRef: compare variable pointers - if (VN_IS(argExpr, VarRef) && VN_IS(withExpr, VarRef)) { - return VN_AS(withExpr, VarRef)->varp() - == VN_AS(argExpr, VarRef)->varp(); - } -- // MemberSel: match by object and member -+ // MemberSel: compare object and member (obj.y) - if (VN_IS(argExpr, MemberSel) && VN_IS(withExpr, MemberSel)) { - AstNode* withObj = withExpr->op1p(); - AstNode* argObj = argExpr->op1p(); - if (!withObj || !argObj) return false; -- withObj = withObj->op1p(); -+ withObj = withObj->op1p(); // Navigate to VarRef - argObj = argObj->op1p(); - return (withObj == argObj) - && (VN_AS(withExpr, MemberSel)->varp() - == VN_AS(argExpr, MemberSel)->varp()); - } -- // ArraySel: match by array base and index variable -+ // ArraySel: compare array base and index (arr[i]) - if (VN_IS(argExpr, ArraySel) && VN_IS(withExpr, ArraySel)) { - AstNode* withBase = withExpr->op1p(); - AstNode* argBase = argExpr->op1p(); - if (!withBase || !argBase) return false; -- withBase = withBase->op1p(); -+ withBase = withBase->op1p(); // Navigate to VarRef - argBase = argBase->op1p(); - AstNode* withIdx = withExpr->op2p(); - AstNode* argIdx = argExpr->op2p(); - if (!withIdx || !argIdx) return false; -- withIdx = withIdx->op1p(); -+ withIdx = withIdx->op1p(); // Navigate to index expr - argIdx = argIdx->op1p(); - if (!VN_IS(withIdx, VarRef) || !VN_IS(argIdx, VarRef)) return false; - return (withBase == argBase) - -From 70053b85193e490d6c9f4aa8c203c885a4d8b500 Mon Sep 17 00:00:00 2001 -From: Yilou Wang -Date: Wed, 26 Nov 2025 15:35:10 +0100 -Subject: [PATCH 21/29] check ci - ---- - src/V3Randomize.cpp | 10 +++++----- - 1 file changed, 5 insertions(+), 5 deletions(-) - -diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp -index 3c7665ca17d..a29ed35a8a4 100644 ---- a/src/V3Randomize.cpp -+++ b/src/V3Randomize.cpp -@@ -2640,7 +2640,7 @@ class RandomizeVisitor final : public VNVisitor { - // VarRef: compare variable pointers - if (VN_IS(argExpr, VarRef) && VN_IS(withExpr, VarRef)) { - return VN_AS(withExpr, VarRef)->varp() -- == VN_AS(argExpr, VarRef)->varp(); -+ == VN_AS(argExpr, VarRef)->varp(); - } - // MemberSel: compare object and member (obj.y) - if (VN_IS(argExpr, MemberSel) && VN_IS(withExpr, MemberSel)) { -@@ -2650,8 +2650,8 @@ class RandomizeVisitor final : public VNVisitor { - withObj = withObj->op1p(); // Navigate to VarRef - argObj = argObj->op1p(); - return (withObj == argObj) -- && (VN_AS(withExpr, MemberSel)->varp() -- == VN_AS(argExpr, MemberSel)->varp()); -+ && (VN_AS(withExpr, MemberSel)->varp() -+ == VN_AS(argExpr, MemberSel)->varp()); - } - // ArraySel: compare array base and index (arr[i]) - if (VN_IS(argExpr, ArraySel) && VN_IS(withExpr, ArraySel)) { -@@ -2667,8 +2667,8 @@ class RandomizeVisitor final : public VNVisitor { - argIdx = argIdx->op1p(); - if (!VN_IS(withIdx, VarRef) || !VN_IS(argIdx, VarRef)) return false; - return (withBase == argBase) -- && (VN_AS(withIdx, VarRef)->varp() -- == VN_AS(argIdx, VarRef)->varp()); -+ && (VN_AS(withIdx, VarRef)->varp() -+ == VN_AS(argIdx, VarRef)->varp()); - } - return false; - }; - -From 1bb108c9c06a4a30417ec98513b952dae6977b19 Mon Sep 17 00:00:00 2001 -From: Yilou Wang -Date: Thu, 27 Nov 2025 11:28:40 +0100 -Subject: [PATCH 22/29] following comments, update the code - ---- - src/V3AstNodeOther.h | 4 ++ - src/V3AstNodes.cpp | 2 + - src/V3Randomize.cpp | 90 +++++++++++++++----------------- - test_regress/t/t_std_randomize.v | 38 +++++++------- - 4 files changed, 65 insertions(+), 69 deletions(-) - -diff --git a/src/V3AstNodeOther.h b/src/V3AstNodeOther.h -index aeac0d27a0a..782f1a5113a 100644 ---- a/src/V3AstNodeOther.h -+++ b/src/V3AstNodeOther.h -@@ -1878,6 +1878,7 @@ class AstVar final : public AstNode { - bool m_ignoreSchedWrite : 1; // Ignore writes in scheduling (for special optimizations) - bool m_dfgMultidriven : 1; // Singal is multidriven, used by DFG to avoid repeat processing - bool m_globalConstrained : 1; // Global constraint per IEEE 1800-2023 18.5.8 -+ bool m_isStdRandomizeArg : 1; // Argument variable created for std::randomize (__Varg*) - void init() { - m_ansi = false; - m_declTyped = false; -@@ -1929,6 +1930,7 @@ class AstVar final : public AstNode { - m_ignoreSchedWrite = false; - m_dfgMultidriven = false; - m_globalConstrained = false; -+ m_isStdRandomizeArg = false; - } - - public: -@@ -2096,6 +2098,8 @@ class AstVar final : public AstNode { - void setDfgMultidriven() { m_dfgMultidriven = true; } - void globalConstrained(bool flag) { m_globalConstrained = flag; } - bool globalConstrained() const { return m_globalConstrained; } -+ bool isStdRandomizeArg() const { return m_isStdRandomizeArg; } -+ void setStdRandomizeArg() { m_isStdRandomizeArg = true; } - // METHODS - void name(const string& name) override { m_name = name; } - void tag(const string& text) override { m_tag = text; } -diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp -index ee1c7201959..9f5dad4c818 100644 ---- a/src/V3AstNodes.cpp -+++ b/src/V3AstNodes.cpp -@@ -2776,6 +2776,7 @@ void AstVar::dump(std::ostream& str) const { - if (isDpiOpenArray()) str << " [DPIOPENA]"; - if (ignorePostWrite()) str << " [IGNPWR]"; - if (ignoreSchedWrite()) str << " [IGNWR]"; -+ if (isStdRandomizeArg()) str << " [STDRANDARG]"; - if (!lifetime().isNone()) str << " [" << lifetime().ascii() << "] "; - str << " " << varType(); - } -@@ -2797,6 +2798,7 @@ void AstVar::dumpJson(std::ostream& str) const { - dumpJsonBoolFunc(str, isDpiOpenArray); - dumpJsonBoolFunc(str, isFuncReturn); - dumpJsonBoolFunc(str, isFuncLocal); -+ dumpJsonBoolFunc(str, isStdRandomizeArg); - dumpJsonStr(str, "lifetime", lifetime().ascii()); - dumpJsonStr(str, "varType", varType().ascii()); - if (dtypep()) dumpJsonStr(str, "dtypeName", dtypep()->name()); -diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp -index a29ed35a8a4..a52b8bdd77a 100644 ---- a/src/V3Randomize.cpp -+++ b/src/V3Randomize.cpp -@@ -176,7 +176,6 @@ class RandomizeMarkVisitor final : public VNVisitor { - } else if (const AstMemberSel* const memberselp = VN_CAST(exprp, MemberSel)) { - if (memberselp->varp() == varp) return true; - } else if (const AstArraySel* const arrselp = VN_CAST(exprp, ArraySel)) { -- // if (arrselp->fromp()->dtypep() == varp->dtypep()) return true; - if (VN_AS(arrselp->fromp(), VarRef)->varp() == varp) return true; - } - } -@@ -1432,7 +1431,7 @@ class CaptureVisitor final : public VNVisitor { - AstVar* getVar(AstVar* const varp) const { - const auto it = m_varCloneMap.find(varp); - if (it == m_varCloneMap.end()) return nullptr; -- if (it->second->origName().rfind("__Varg", 0) == 0) return nullptr; -+ if (it->second->isStdRandomizeArg()) return nullptr; - return it->second; - } - -@@ -1503,7 +1502,7 @@ class CaptureVisitor final : public VNVisitor { - if (m_ignore.count(nodep)) return; - m_ignore.emplace(nodep); - UASSERT_OBJ(nodep->varp(), nodep, "Variable unlinked"); -- if (nodep->varp()->origName().rfind("__Varg", 0) == 0) return; -+ if (nodep->varp()->isStdRandomizeArg()) return; - CaptureMode capMode = getVarRefCaptureMode(nodep); - if (mode(capMode) == CaptureMode::CAP_NO) return; - if (mode(capMode) == CaptureMode::CAP_VALUE) captureRefByValue(nodep, capMode); -@@ -1642,6 +1641,40 @@ class RandomizeVisitor final : public VNVisitor { - std::set m_writtenVars; // Track write_var calls per class to avoid duplicates - - // METHODS -+ // Check if two nodes are semantically equivalent (not pointer equality): -+ static bool isSimilarNode(const AstNodeExpr* withExpr, const AstNodeExpr* argExpr) { -+ // VarRef: compare variable pointers -+ if (VN_IS(argExpr, VarRef) && VN_IS(withExpr, VarRef)) { -+ return VN_AS(withExpr, VarRef)->varp() == VN_AS(argExpr, VarRef)->varp(); -+ } -+ // MemberSel: compare object and member (obj.y) -+ if (VN_IS(argExpr, MemberSel) && VN_IS(withExpr, MemberSel)) { -+ const AstNode* withObj = withExpr->op1p(); -+ const AstNode* argObj = argExpr->op1p(); -+ if (!withObj || !argObj) return false; -+ withObj = withObj->op1p(); // Navigate to VarRef -+ argObj = argObj->op1p(); -+ return (withObj == argObj) -+ && (VN_AS(withExpr, MemberSel)->varp() == VN_AS(argExpr, MemberSel)->varp()); -+ } -+ // ArraySel: compare array base and index (arr[i]) -+ if (VN_IS(argExpr, ArraySel) && VN_IS(withExpr, ArraySel)) { -+ const AstNode* withBase = withExpr->op1p(); -+ const AstNode* argBase = argExpr->op1p(); -+ if (!withBase || !argBase) return false; -+ withBase = withBase->op1p(); // Navigate to VarRef -+ argBase = argBase->op1p(); -+ const AstNode* withIdx = withExpr->op2p(); -+ const AstNode* argIdx = argExpr->op2p(); -+ if (!withIdx || !argIdx) return false; -+ withIdx = withIdx->op1p(); // Navigate to index expr -+ argIdx = argIdx->op1p(); -+ if (!VN_IS(withIdx, VarRef) || !VN_IS(argIdx, VarRef)) return false; -+ return (withBase == argBase) -+ && (VN_AS(withIdx, VarRef)->varp() == VN_AS(argIdx, VarRef)->varp()); -+ } -+ return false; -+ } - void createRandomGenerator(AstClass* const classp) { - if (classp->user3p()) return; - if (classp->extendsp()) { -@@ -2616,12 +2649,10 @@ class RandomizeVisitor final : public VNVisitor { - int argn = 0; - AstWith* withp = nullptr; - for (AstNode* pinp = nodep->pinsp(); pinp; pinp = pinp->nextp()) { -- withp = VN_IS(pinp, With) ? VN_AS(pinp, With) : nullptr; -- if (withp) break; -+ if ((withp = VN_CAST(pinp, With))) break; - } -- -- for (AstNode* pinp = nodep->pinsp(); pinp; pinp = pinp->nextp()) { -- AstArg* const argp = VN_CAST(pinp, Arg); -+ for (const AstNode* pinp = nodep->pinsp(); pinp; pinp = pinp->nextp()) { -+ const AstArg* const argp = VN_CAST(pinp, Arg); - if (!argp) continue; - AstNodeExpr* exprp = argp->exprp(); - AstCMethodHard* const basicMethodp = new AstCMethodHard{ -@@ -2631,50 +2662,11 @@ class RandomizeVisitor final : public VNVisitor { - AstVar* const refvarp - = new AstVar{exprp->fileline(), VVarType::MEMBER, - "__Varg"s + std::to_string(++argn), exprp->dtypep()}; -- -+ refvarp->setStdRandomizeArg(); - // Replace argument occurrences in 'with' clause with __Varg* reference. -- // Uses "similarNode" matching (semantic equality, not pointer equality). -- // Supports: VarRef (x), MemberSel (obj.y), ArraySel (arr[i]) - if (withp) { -- auto similarNode = [](AstNodeExpr* withExpr, AstNodeExpr* argExpr) -> bool { -- // VarRef: compare variable pointers -- if (VN_IS(argExpr, VarRef) && VN_IS(withExpr, VarRef)) { -- return VN_AS(withExpr, VarRef)->varp() -- == VN_AS(argExpr, VarRef)->varp(); -- } -- // MemberSel: compare object and member (obj.y) -- if (VN_IS(argExpr, MemberSel) && VN_IS(withExpr, MemberSel)) { -- AstNode* withObj = withExpr->op1p(); -- AstNode* argObj = argExpr->op1p(); -- if (!withObj || !argObj) return false; -- withObj = withObj->op1p(); // Navigate to VarRef -- argObj = argObj->op1p(); -- return (withObj == argObj) -- && (VN_AS(withExpr, MemberSel)->varp() -- == VN_AS(argExpr, MemberSel)->varp()); -- } -- // ArraySel: compare array base and index (arr[i]) -- if (VN_IS(argExpr, ArraySel) && VN_IS(withExpr, ArraySel)) { -- AstNode* withBase = withExpr->op1p(); -- AstNode* argBase = argExpr->op1p(); -- if (!withBase || !argBase) return false; -- withBase = withBase->op1p(); // Navigate to VarRef -- argBase = argBase->op1p(); -- AstNode* withIdx = withExpr->op2p(); -- AstNode* argIdx = argExpr->op2p(); -- if (!withIdx || !argIdx) return false; -- withIdx = withIdx->op1p(); // Navigate to index expr -- argIdx = argIdx->op1p(); -- if (!VN_IS(withIdx, VarRef) || !VN_IS(argIdx, VarRef)) return false; -- return (withBase == argBase) -- && (VN_AS(withIdx, VarRef)->varp() -- == VN_AS(argIdx, VarRef)->varp()); -- } -- return false; -- }; -- - withp->foreach([&](AstNodeExpr* exp) { -- if (similarNode(exp, exprp)) { -+ if (isSimilarNode(exp, exprp)) { - AstVarRef* const replaceVar - = new AstVarRef{exprp->fileline(), refvarp, VAccess::READWRITE}; - exp->replaceWith(replaceVar); -diff --git a/test_regress/t/t_std_randomize.v b/test_regress/t/t_std_randomize.v -index a2de1594dc6..ba9b2b5eed5 100644 ---- a/test_regress/t/t_std_randomize.v -+++ b/test_regress/t/t_std_randomize.v -@@ -80,45 +80,43 @@ module t_scope_std_randomize; - `checkd(test.std_randomize(), 1); - - // Test array randomization with constraints -- /* verilator lint_off WIDTHEXPAND */ -- `checkd(std::randomize(limit) with { foreach (limit[i]) { limit[i] < 100;}}, 1); -- foreach (limit[i]) if (limit[i] >= 100) $stop; -+ `checkd(std::randomize(limit) with { foreach (limit[i]) { limit[i] < 32'd100;}}, 1); -+ foreach (limit[i]) if (limit[i] >= 32'd100) $stop; - -- `checkd(std::randomize(limit_7bits) with { foreach (limit_7bits[i]) { limit_7bits[i] < 10;}}, 1); -- foreach (limit_7bits[i]) if (limit_7bits[i] >= 10) $stop; -+ `checkd(std::randomize(limit_7bits) with { foreach (limit_7bits[i]) { limit_7bits[i] < 7'd10;}}, 1); -+ foreach (limit_7bits[i]) if (limit_7bits[i] >= 7'd10) $stop; - -- `checkd(std::randomize(limit_15bits) with { foreach (limit_15bits[i]) { limit_15bits[i] < 1000;}}, 1); -- foreach (limit_15bits[i]) if (limit_15bits[i] >= 1000) $stop; -+ `checkd(std::randomize(limit_15bits) with { foreach (limit_15bits[i]) { limit_15bits[i] < 15'd1000;}}, 1); -+ foreach (limit_15bits[i]) if (limit_15bits[i] >= 15'd1000) $stop; - -- `checkd(std::randomize(limit_31bits) with { foreach (limit_31bits[i]) { limit_31bits[i] < 100000;}}, 1); -- foreach (limit_31bits[i]) if (limit_31bits[i] >= 100000) $stop; -+ `checkd(std::randomize(limit_31bits) with { foreach (limit_31bits[i]) { limit_31bits[i] < 31'd100000;}}, 1); -+ foreach (limit_31bits[i]) if (limit_31bits[i] >= 31'd100000) $stop; - -- `checkd(std::randomize(limit_63bits) with { foreach (limit_63bits[i]) { limit_63bits[i] < 64'd10000000000;}}, 1); -- foreach (limit_63bits[i]) if (limit_63bits[i] >= 64'd10000000000) $stop; -+ `checkd(std::randomize(limit_63bits) with { foreach (limit_63bits[i]) { limit_63bits[i] < 63'd10000000000;}}, 1); -+ foreach (limit_63bits[i]) if (limit_63bits[i] >= 63'd10000000000) $stop; - -- `checkd(std::randomize(limit_95bits) with { foreach (limit_95bits[i]) { limit_95bits[i] < 96'd1000000000000;}}, 1); -- foreach (limit_95bits[i]) if (limit_95bits[i] >= 96'd1000000000000) $stop; -+ `checkd(std::randomize(limit_95bits) with { foreach (limit_95bits[i]) { limit_95bits[i] < 95'd1000000000000;}}, 1); -+ foreach (limit_95bits[i]) if (limit_95bits[i] >= 95'd1000000000000) $stop; - - foreach (limit_63bits[i]) begin -- `checkd(std::randomize(limit_63bits[i]) with { limit_63bits[i] >= 64'd50; limit_63bits[i] < 64'd100;}, 1); -- if ((limit_63bits[i] < 64'd50) || (limit_63bits[i] >= 64'd100)) `stop; -+ `checkd(std::randomize(limit_63bits[i]) with { limit_63bits[i] >= 63'd50; limit_63bits[i] < 63'd100;}, 1); -+ if ((limit_63bits[i] < 63'd50) || (limit_63bits[i] >= 63'd100)) `stop; - end - - foreach (limit_95bits[i]) begin -- `checkd(std::randomize(limit_95bits[i]) with { limit_95bits[i] >= 96'd50; limit_95bits[i] < 96'd1000;}, 1); -- if (limit_95bits[i] < 96'd50 || limit_95bits[i] >= 96'd1000) `stop; -+ `checkd(std::randomize(limit_95bits[i]) with { limit_95bits[i] >= 95'd50; limit_95bits[i] < 95'd1000;}, 1); -+ if (limit_95bits[i] < 95'd50 || limit_95bits[i] >= 95'd1000) $stop; - end - - // Test mixed argument types (VarRef + MemberSel + ArraySel) with interdependent constraints - `checkd(std::randomize(addr, test.addr, limit_31bits[0]) with { - addr > 8'd10; addr < 8'd50; - test.addr > addr; test.addr < 8'd100; -- limit_31bits[0] > test.addr; limit_31bits[0] < 31'd200; -+ limit_31bits[0] > 31'(test.addr); limit_31bits[0] < 31'd200; - }, 1); - if (addr <= 8'd10 || addr >= 8'd50) `stop; - if (test.addr <= addr || test.addr >= 8'd100) `stop; -- if (limit_31bits[0] <= test.addr || limit_31bits[0] >= 31'd200) `stop; -- /* verilator lint_on WIDTHEXPAND */ -+ if (limit_31bits[0] <= 31'(test.addr) || limit_31bits[0] >= 31'd200) `stop; - - $write("*-* All Finished *-*\n"); - $finish; - -From 2f234836686cfe4b97f1c1287346138c6f335779 Mon Sep 17 00:00:00 2001 -From: Yilou Wang -Date: Thu, 27 Nov 2025 13:51:26 +0100 -Subject: [PATCH 23/29] update json_*.out file - ---- - test_regress/t/t_json_only_begin_hier.out | 4 +- - test_regress/t/t_json_only_debugcheck.out | 54 +++++++++---------- - test_regress/t/t_json_only_first.out | 24 ++++----- - test_regress/t/t_json_only_flat.out | 30 +++++------ - .../t/t_json_only_flat_no_inline_mod.out | 6 +-- - test_regress/t/t_json_only_flat_pub_mod.out | 6 +-- - test_regress/t/t_json_only_flat_vlvbound.out | 32 +++++------ - test_regress/t/t_json_only_output.out | 2 +- - test_regress/t/t_json_only_tag.out | 16 +++--- - 9 files changed, 87 insertions(+), 87 deletions(-) - -diff --git a/test_regress/t/t_json_only_begin_hier.out b/test_regress/t/t_json_only_begin_hier.out -index ae7c5671c76..771c33e1cb9 100644 ---- a/test_regress/t/t_json_only_begin_hier.out -+++ b/test_regress/t/t_json_only_begin_hier.out -@@ -2,7 +2,7 @@ - "modulesp": [ - {"type":"MODULE","name":"test","addr":"(E)","loc":"d,22:8,22:12","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"test","level":1,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], - "stmtsp": [ -- {"type":"VAR","name":"N","addr":"(F)","loc":"d,24:12,24:13","dtypep":"(G)","origName":"N","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":true,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"GENVAR","dtypeName":"integer","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, -+ {"type":"VAR","name":"N","addr":"(F)","loc":"d,24:12,24:13","dtypep":"(G)","origName":"N","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":true,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"GENVAR","dtypeName":"integer","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"GENBLOCK","name":"FOR_GENERATE","addr":"(H)","loc":"d,25:14,25:17","implied":true,"unnamed":false,"genforp": [],"itemsp": []}, - {"type":"GENBLOCK","name":"FOR_GENERATE[0]","addr":"(I)","loc":"d,27:21,27:31","implied":false,"unnamed":false,"genforp": [], - "itemsp": [ -@@ -27,7 +27,7 @@ - "stmtsp": [ - {"type":"GENBLOCK","name":"submod_gen","addr":"(T)","loc":"d,12:19,12:29","implied":false,"unnamed":false,"genforp": [], - "itemsp": [ -- {"type":"VAR","name":"l1_sig","addr":"(U)","loc":"d,13:14,13:20","dtypep":"(V)","origName":"l1_sig","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, -+ {"type":"VAR","name":"l1_sig","addr":"(U)","loc":"d,13:14,13:20","dtypep":"(V)","origName":"l1_sig","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"GENBLOCK","name":"nested_gen","addr":"(W)","loc":"d,14:23,14:33","implied":false,"unnamed":false,"genforp": [], - "itemsp": [ - {"type":"CELL","name":"submod_nested","addr":"(X)","loc":"d,15:21,15:34","origName":"submod_nested","recursive":false,"modp":"(Y)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} -diff --git a/test_regress/t/t_json_only_debugcheck.out b/test_regress/t/t_json_only_debugcheck.out -index 450f4af285b..55f653fec4c 100644 ---- a/test_regress/t/t_json_only_debugcheck.out -+++ b/test_regress/t/t_json_only_debugcheck.out -@@ -2,13 +2,13 @@ - "modulesp": [ - {"type":"MODULE","name":"$root","addr":"(I)","loc":"d,11:8,11:9","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"$root","level":1,"modPublic":true,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], - "stmtsp": [ -- {"type":"VAR","name":"clk","addr":"(J)","loc":"d,15:10,15:13","dtypep":"(K)","origName":"clk","isSc":false,"isPrimaryIO":true,"isPrimaryClock":true,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, -- {"type":"VAR","name":"t.e","addr":"(L)","loc":"d,24:9,24:10","dtypep":"(M)","origName":"e","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"my_t","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, -- {"type":"VAR","name":"__Vtrigprevexpr___TOP__clk__0","addr":"(N)","loc":"d,11:8,11:9","dtypep":"(K)","origName":"__Vtrigprevexpr___TOP__clk__0","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"MODULETEMP","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, -- {"type":"VAR","name":"t.cyc","addr":"(O)","loc":"d,23:17,23:20","dtypep":"(P)","origName":"cyc","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"integer","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, -- 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{"type":"VAR","name":"__VactTriggered","addr":"(S)","loc":"d,11:8,11:9","dtypep":"(T)","origName":"__VactTriggered","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"MODULETEMP","dtypeName":"","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, -- 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{"type":"VAR","name":"value","addr":"(X)","loc":"d,8:12,8:17","dtypep":"(W)","origName":"value","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"integer","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"MODPORT","name":"out_modport","addr":"(MB)","loc":"d,9:12,9:23", - "varsp": [ - {"type":"MODPORTVARREF","name":"value","addr":"(NB)","loc":"d,9:32,9:37","direction":"OUTPUT","varp":"(X)"} - -From 86df1bcd7d5dee1ea11c669dffb039a6145a03d2 Mon Sep 17 00:00:00 2001 -From: Yilou Wang -Date: Thu, 27 Nov 2025 13:57:41 +0100 -Subject: [PATCH 24/29] update t_json.out files - ---- - test_regress/t/t_constraint_json_only.out | 26 ++++----- - test_regress/t/t_json_only_begin_hier.out | 4 +- - test_regress/t/t_json_only_debugcheck.out | 54 +++++++++---------- - test_regress/t/t_json_only_first.out | 24 ++++----- - test_regress/t/t_json_only_flat.out | 30 +++++------ - .../t/t_json_only_flat_no_inline_mod.out | 6 +-- - test_regress/t/t_json_only_flat_pub_mod.out | 6 +-- - test_regress/t/t_json_only_flat_vlvbound.out | 32 +++++------ - test_regress/t/t_json_only_output.out | 2 +- - test_regress/t/t_json_only_tag.out | 16 +++--- - test_regress/t/t_var_port_json_only.out | 40 +++++++------- - 11 files changed, 120 insertions(+), 120 deletions(-) - diff --git a/test_regress/t/t_constraint_json_only.out b/test_regress/t/t_constraint_json_only.out index 9042cc24aeb..f41cdf173b9 100644 --- a/test_regress/t/t_constraint_json_only.out @@ -1964,22 +277,287 @@ index 9042cc24aeb..f41cdf173b9 100644 + {"type":"VAR","name":"strings_equal","addr":"(BB)","loc":"d,61:17,61:30","dtypep":"(U)","origName":"strings_equal","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":true,"isFuncLocal":true,"isStdRandomizeArg":false,"lifetime":"VAUTOM","varType":"MEMBER","dtypeName":"bit","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ],"classOrPackagep": [], "stmtsp": [ -- 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{"type":"REFDTYPE","name":"process","addr":"(BY)","loc":"d,138:21,138:28","dtypep":"UNLINKED","generic":false,"typedefp":"UNLINKED","refDTypep":"UNLINKED","classOrPackagep":"UNLINKED","typeofp": [],"classOrPackageOpp": [],"paramsp": []} + ],"classOrPackagep": [], + "stmtsp": [ +- {"type":"VAR","name":"p","addr":"(CY)","loc":"d,139:15,139:16","dtypep":"UNLINKED","origName":"p","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"VAR","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", ++ {"type":"VAR","name":"p","addr":"(CY)","loc":"d,139:15,139:16","dtypep":"UNLINKED","origName":"p","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"NONE","varType":"VAR","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", + "childDTypep": [ + {"type":"REFDTYPE","name":"process","addr":"(DY)","loc":"d,139:7,139:14","dtypep":"UNLINKED","generic":false,"typedefp":"UNLINKED","refDTypep":"UNLINKED","classOrPackagep":"UNLINKED","typeofp": [],"classOrPackageOpp": [],"paramsp": []} + ],"delayp": [], +@@ -1600,7 +1600,7 @@ ],"scopeNamep": []}, - {"type":"FUNC","name":"new","addr":"(KB)","loc":"d,7:1,7:6","dtypep":"(LB)","method":true,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"new","fvarp": [],"classOrPackagep": [],"stmtsp": [],"scopeNamep": []}, -- {"type":"VAR","name":"constraint","addr":"(MB)","loc":"d,7:1,7:6","dtypep":"(NB)","origName":"constraint","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"MEMBER","dtypeName":"VlRandomizer","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} -+ {"type":"VAR","name":"constraint","addr":"(MB)","loc":"d,7:1,7:6","dtypep":"(NB)","origName":"constraint","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"NONE","varType":"MEMBER","dtypeName":"VlRandomizer","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} - ],"extendsp": []} - ]} - ],"filesp": [], + {"type":"TASK","name":"set_status","addr":"(HY)","loc":"d,146:29,146:39","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"set_status","fvarp": [],"classOrPackagep": [], + "stmtsp": [ +- {"type":"VAR","name":"s","addr":"(IY)","loc":"d,146:46,146:47","dtypep":"UNLINKED","origName":"s","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", ++ {"type":"VAR","name":"s","addr":"(IY)","loc":"d,146:46,146:47","dtypep":"UNLINKED","origName":"s","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", + "childDTypep": [ + {"type":"REFDTYPE","name":"state","addr":"(JY)","loc":"d,146:40,146:45","dtypep":"UNLINKED","generic":false,"typedefp":"UNLINKED","refDTypep":"UNLINKED","classOrPackagep":"UNLINKED","typeofp": [],"classOrPackageOpp": [],"paramsp": []} + ],"delayp": [],"valuep": [],"attrsp": []} +@@ -1655,7 +1655,7 @@ + {"type":"TASK","name":"await","addr":"(EZ)","loc":"d,172:10,172:15","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"await","fvarp": [],"classOrPackagep": [],"stmtsp": [],"scopeNamep": []}, + {"type":"TASK","name":"killQueue","addr":"(FZ)","loc":"d,178:17,178:26","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"killQueue","fvarp": [],"classOrPackagep": [], + "stmtsp": [ +- {"type":"VAR","name":"processQueue","addr":"(GZ)","loc":"d,178:39,178:51","dtypep":"UNLINKED","origName":"processQueue","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"REF","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", ++ {"type":"VAR","name":"processQueue","addr":"(GZ)","loc":"d,178:39,178:51","dtypep":"UNLINKED","origName":"processQueue","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"REF","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", + "childDTypep": [ + {"type":"BRACKETARRAYDTYPE","name":"","addr":"(HZ)","loc":"d,178:51,178:52","dtypep":"UNLINKED","generic":false, + "childDTypep": [ +@@ -1671,7 +1671,7 @@ + {"type":"BASICDTYPE","name":"string","addr":"(LZ)","loc":"d,225:14,225:20","dtypep":"(LZ)","keyword":"string","generic":false,"rangep": []} + ],"classOrPackagep": [], + "stmtsp": [ +- {"type":"VAR","name":"s","addr":"(MZ)","loc":"d,227:14,227:15","dtypep":"UNLINKED","origName":"s","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"VAR","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", ++ {"type":"VAR","name":"s","addr":"(MZ)","loc":"d,227:14,227:15","dtypep":"UNLINKED","origName":"s","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"NONE","varType":"VAR","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", + "childDTypep": [ + {"type":"BASICDTYPE","name":"string","addr":"(NZ)","loc":"d,227:7,227:13","dtypep":"(NZ)","keyword":"string","generic":false,"rangep": []} + ],"delayp": [], +@@ -1698,7 +1698,7 @@ + ],"scopeNamep": []}, + {"type":"TASK","name":"set_randstate","addr":"(YZ)","loc":"d,233:19,233:32","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"set_randstate","fvarp": [],"classOrPackagep": [], + "stmtsp": [ +- {"type":"VAR","name":"s","addr":"(ZZ)","loc":"d,233:40,233:41","dtypep":"UNLINKED","origName":"s","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", ++ {"type":"VAR","name":"s","addr":"(ZZ)","loc":"d,233:40,233:41","dtypep":"UNLINKED","origName":"s","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", + "childDTypep": [ + {"type":"BASICDTYPE","name":"string","addr":"(AAB)","loc":"d,233:33,233:39","dtypep":"(AAB)","keyword":"string","generic":false,"rangep": []} + ],"delayp": [],"valuep": [],"attrsp": []}, diff --git a/test_regress/t/t_json_only_begin_hier.out b/test_regress/t/t_json_only_begin_hier.out index ae7c5671c76..771c33e1cb9 100644 --- a/test_regress/t/t_json_only_begin_hier.out @@ -2417,6 +995,68 @@ index ff5bfd58a5d..c11b5c8504c 100644 {"type":"MODPORT","name":"out_modport","addr":"(MB)","loc":"d,9:12,9:23", "varsp": [ {"type":"MODPORTVARREF","name":"value","addr":"(NB)","loc":"d,9:32,9:37","direction":"OUTPUT","varp":"(X)"} +diff --git a/test_regress/t/t_std_randomize.v b/test_regress/t/t_std_randomize.v +index 1a44dffa548..ba9b2b5eed5 100644 +--- a/test_regress/t/t_std_randomize.v ++++ b/test_regress/t/t_std_randomize.v +@@ -80,25 +80,43 @@ module t_scope_std_randomize; + `checkd(test.std_randomize(), 1); + + // Test array randomization with constraints +- /* verilator lint_off WIDTHEXPAND */ +- `checkd(std::randomize(limit) with { foreach (limit[i]) { limit[i] < 100;}}, 1); +- foreach (limit[i]) if (limit[i] >= 100) $stop; ++ `checkd(std::randomize(limit) with { foreach (limit[i]) { limit[i] < 32'd100;}}, 1); ++ foreach (limit[i]) if (limit[i] >= 32'd100) $stop; + +- `checkd(std::randomize(limit_7bits) with { foreach (limit_7bits[i]) { limit_7bits[i] < 10;}}, 1); +- foreach (limit_7bits[i]) if (limit_7bits[i] >= 10) $stop; ++ `checkd(std::randomize(limit_7bits) with { foreach (limit_7bits[i]) { limit_7bits[i] < 7'd10;}}, 1); ++ foreach (limit_7bits[i]) if (limit_7bits[i] >= 7'd10) $stop; + +- `checkd(std::randomize(limit_15bits) with { foreach (limit_15bits[i]) { limit_15bits[i] < 1000;}}, 1); +- foreach (limit_15bits[i]) if (limit_15bits[i] >= 1000) $stop; ++ `checkd(std::randomize(limit_15bits) with { foreach (limit_15bits[i]) { limit_15bits[i] < 15'd1000;}}, 1); ++ foreach (limit_15bits[i]) if (limit_15bits[i] >= 15'd1000) $stop; + +- `checkd(std::randomize(limit_31bits) with { foreach (limit_31bits[i]) { limit_31bits[i] < 100000;}}, 1); +- foreach (limit_31bits[i]) if (limit_31bits[i] >= 100000) $stop; ++ `checkd(std::randomize(limit_31bits) with { foreach (limit_31bits[i]) { limit_31bits[i] < 31'd100000;}}, 1); ++ foreach (limit_31bits[i]) if (limit_31bits[i] >= 31'd100000) $stop; + +- `checkd(std::randomize(limit_63bits) with { foreach (limit_63bits[i]) { limit_63bits[i] < 64'd10000000000;}}, 1); +- foreach (limit_63bits[i]) if (limit_63bits[i] >= 64'd10000000000) $stop; ++ `checkd(std::randomize(limit_63bits) with { foreach (limit_63bits[i]) { limit_63bits[i] < 63'd10000000000;}}, 1); ++ foreach (limit_63bits[i]) if (limit_63bits[i] >= 63'd10000000000) $stop; + +- `checkd(std::randomize(limit_95bits) with { foreach (limit_95bits[i]) { limit_95bits[i] < 96'd1000000000000;}}, 1); +- foreach (limit_95bits[i]) if (limit_95bits[i] >= 96'd1000000000000) $stop; +- /* verilator lint_on WIDTHEXPAND */ ++ `checkd(std::randomize(limit_95bits) with { foreach (limit_95bits[i]) { limit_95bits[i] < 95'd1000000000000;}}, 1); ++ foreach (limit_95bits[i]) if (limit_95bits[i] >= 95'd1000000000000) $stop; ++ ++ foreach (limit_63bits[i]) begin ++ `checkd(std::randomize(limit_63bits[i]) with { limit_63bits[i] >= 63'd50; limit_63bits[i] < 63'd100;}, 1); ++ if ((limit_63bits[i] < 63'd50) || (limit_63bits[i] >= 63'd100)) `stop; ++ end ++ ++ foreach (limit_95bits[i]) begin ++ `checkd(std::randomize(limit_95bits[i]) with { limit_95bits[i] >= 95'd50; limit_95bits[i] < 95'd1000;}, 1); ++ if (limit_95bits[i] < 95'd50 || limit_95bits[i] >= 95'd1000) $stop; ++ end ++ ++ // Test mixed argument types (VarRef + MemberSel + ArraySel) with interdependent constraints ++ `checkd(std::randomize(addr, test.addr, limit_31bits[0]) with { ++ addr > 8'd10; addr < 8'd50; ++ test.addr > addr; test.addr < 8'd100; ++ limit_31bits[0] > 31'(test.addr); limit_31bits[0] < 31'd200; ++ }, 1); ++ if (addr <= 8'd10 || addr >= 8'd50) `stop; ++ if (test.addr <= addr || test.addr >= 8'd100) `stop; ++ if (limit_31bits[0] <= 31'(test.addr) || limit_31bits[0] >= 31'd200) `stop; + + $write("*-* All Finished *-*\n"); + $finish; diff --git a/test_regress/t/t_var_port_json_only.out b/test_regress/t/t_var_port_json_only.out index e8d8f7221cc..8334fc416ea 100644 --- a/test_regress/t/t_var_port_json_only.out @@ -2478,545 +1118,35 @@ index e8d8f7221cc..8334fc416ea 100644 - {"type":"VAR","name":"x_input_var_integer","addr":"(EB)","loc":"d,50:31,50:50","dtypep":"(G)","origName":"x_input_var_integer","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"integer","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"y_input_wire_logic","addr":"(FB)","loc":"d,50:57,50:75","dtypep":"(J)","origName":"y_input_wire_logic","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} + {"type":"VAR","name":"x_input_var_integer","addr":"(EB)","loc":"d,50:31,50:50","dtypep":"(G)","origName":"x_input_var_integer","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"integer","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, -+ {"type":"VAR","name":"y_input_wire_logic","addr":"(FB)","loc":"d,50:57,50:75","dtypep":"(J)","origName":"y_input_wire_logic","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} - ]}, - {"type":"MODULE","name":"mh18","addr":"(GB)","loc":"d,52:8,52:12","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"mh18","level":1,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], - "stmtsp": [ -- {"type":"VAR","name":"x_output_var_logic","addr":"(HB)","loc":"d,52:24,52:42","dtypep":"(J)","origName":"x_output_var_logic","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, -- 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{"type":"TASK","name":"set_randstate","addr":"(YZ)","loc":"d,233:19,233:32","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"set_randstate","fvarp": [],"classOrPackagep": [], - "stmtsp": [ -- {"type":"VAR","name":"s","addr":"(ZZ)","loc":"d,233:40,233:41","dtypep":"UNLINKED","origName":"s","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", -+ {"type":"VAR","name":"s","addr":"(ZZ)","loc":"d,233:40,233:41","dtypep":"UNLINKED","origName":"s","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", - "childDTypep": [ - {"type":"BASICDTYPE","name":"string","addr":"(AAB)","loc":"d,233:33,233:39","dtypep":"(AAB)","keyword":"string","generic":false,"rangep": []} - ],"delayp": [],"valuep": [],"attrsp": []}, - -From e39b6efcd072ead958470e5a06ebedce452f412d Mon Sep 17 00:00:00 2001 -From: Yilou Wang -Date: Fri, 28 Nov 2025 15:56:44 +0100 -Subject: [PATCH 26/29] refine code - ---- - src/V3Randomize.cpp | 45 ++++++++++++++++++++++++--------------------- - 1 file changed, 24 insertions(+), 21 deletions(-) - -diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp -index a52b8bdd77a..b6a400cafe8 100644 ---- a/src/V3Randomize.cpp -+++ b/src/V3Randomize.cpp -@@ -1649,29 +1649,32 @@ class RandomizeVisitor final : public VNVisitor { - } - // MemberSel: compare object and member (obj.y) - if (VN_IS(argExpr, MemberSel) && VN_IS(withExpr, MemberSel)) { -- const AstNode* withObj = withExpr->op1p(); -- const AstNode* argObj = argExpr->op1p(); -+ const AstMemberSel* const withMS = VN_AS(withExpr, MemberSel); -+ const AstMemberSel* const argMS = VN_AS(argExpr, MemberSel); -+ // First check: member variable must be the same -+ if (withMS->varp() != argMS->varp()) return false; -+ // Second check: base object expression must be the same -+ const AstNode* withObj = withMS->fromp(); -+ const AstNode* argObj = argMS->fromp(); - if (!withObj || !argObj) return false; -- withObj = withObj->op1p(); // Navigate to VarRef -- argObj = argObj->op1p(); -- return (withObj == argObj) -- && (VN_AS(withExpr, MemberSel)->varp() == VN_AS(argExpr, MemberSel)->varp()); -+ return withObj == argObj; - } - // ArraySel: compare array base and index (arr[i]) - if (VN_IS(argExpr, ArraySel) && VN_IS(withExpr, ArraySel)) { -- const AstNode* withBase = withExpr->op1p(); -- const AstNode* argBase = argExpr->op1p(); -+ const AstArraySel* const withAS = VN_AS(withExpr, ArraySel); -+ const AstArraySel* const argAS = VN_AS(argExpr, ArraySel); -+ // Compare array base (must be same VarRef) -+ const AstNodeExpr* const withBase = withAS->fromp(); -+ const AstNodeExpr* const argBase = argAS->fromp(); - if (!withBase || !argBase) return false; -- withBase = withBase->op1p(); // Navigate to VarRef -- argBase = argBase->op1p(); -- const AstNode* withIdx = withExpr->op2p(); -- const AstNode* argIdx = argExpr->op2p(); -+ if (!VN_IS(withBase, VarRef) || !VN_IS(argBase, VarRef)) return false; -+ if (VN_AS(withBase, VarRef)->varp() != VN_AS(argBase, VarRef)->varp()) return false; -+ // Compare array index (must be same VarRef, typically loop iterator) -+ const AstNodeExpr* const withIdx = withAS->bitp(); -+ const AstNodeExpr* const argIdx = argAS->bitp(); - if (!withIdx || !argIdx) return false; -- withIdx = withIdx->op1p(); // Navigate to index expr -- argIdx = argIdx->op1p(); - if (!VN_IS(withIdx, VarRef) || !VN_IS(argIdx, VarRef)) return false; -- return (withBase == argBase) -- && (VN_AS(withIdx, VarRef)->varp() == VN_AS(argIdx, VarRef)->varp()); -+ return VN_AS(withIdx, VarRef)->varp() == VN_AS(argIdx, VarRef)->varp(); - } - return false; - } -@@ -2672,7 +2675,7 @@ class RandomizeVisitor final : public VNVisitor { - exp->replaceWith(replaceVar); - replaceVar->user1(exp->user1()); - replaceVar->varp()->user2p(m_modp); -- pushDeletep(exp); -+ VL_DO_DANGLING(pushDeletep(exp), exp); - } - }); - } -@@ -2718,10 +2721,10 @@ class RandomizeVisitor final : public VNVisitor { - solverCallp->add(new AstVarRef{fl, stdrand, VAccess::READWRITE}); - solverCallp->add(".next()"); - AstVar* const fvarp = VN_AS(randomizeFuncp->fvarp(), Var); -- AstVarRef* const retvalReadp = new AstVarRef{fl, fvarp, VAccess::READ}; -- AstNodeExpr* const andExprp = new AstAnd{fl, retvalReadp, solverCallp}; -- AstVarRef* const retvalWritep = new AstVarRef{fl, fvarp, VAccess::WRITE}; -- randomizeFuncp->addStmtsp(new AstAssign{fl, retvalWritep, andExprp}); -+ AstNodeExpr* const andExprp -+ = new AstAnd{fl, new AstVarRef{fl, fvarp, VAccess::READ}, solverCallp}; -+ randomizeFuncp->addStmtsp( -+ new AstAssign{fl, new AstVarRef{fl, fvarp, VAccess::WRITE}, andExprp}); - } - // Remove With nodes from pins as they have been processed - for (AstNode* pinp = nodep->pinsp(); pinp;) { - -From 41591c5eee1f32bc0f949fa8c9a4eb86ddf7d02b Mon Sep 17 00:00:00 2001 -From: Yilou Wang -Date: Fri, 28 Nov 2025 15:57:32 +0100 -Subject: [PATCH 27/29] refine code - ---- - src/V3Randomize.cpp | 4 ---- - 1 file changed, 4 deletions(-) - -diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp -index b6a400cafe8..34e72d6d78c 100644 ---- a/src/V3Randomize.cpp -+++ b/src/V3Randomize.cpp -@@ -1651,9 +1651,7 @@ class RandomizeVisitor final : public VNVisitor { - if (VN_IS(argExpr, MemberSel) && VN_IS(withExpr, MemberSel)) { - const AstMemberSel* const withMS = VN_AS(withExpr, MemberSel); - const AstMemberSel* const argMS = VN_AS(argExpr, MemberSel); -- // First check: member variable must be the same - if (withMS->varp() != argMS->varp()) return false; -- // Second check: base object expression must be the same - const AstNode* withObj = withMS->fromp(); - const AstNode* argObj = argMS->fromp(); - if (!withObj || !argObj) return false; -@@ -1663,13 +1661,11 @@ class RandomizeVisitor final : public VNVisitor { - if (VN_IS(argExpr, ArraySel) && VN_IS(withExpr, ArraySel)) { - const AstArraySel* const withAS = VN_AS(withExpr, ArraySel); - const AstArraySel* const argAS = VN_AS(argExpr, ArraySel); -- // Compare array base (must be same VarRef) - const AstNodeExpr* const withBase = withAS->fromp(); - const AstNodeExpr* const argBase = argAS->fromp(); - if (!withBase || !argBase) return false; - if (!VN_IS(withBase, VarRef) || !VN_IS(argBase, VarRef)) return false; - if (VN_AS(withBase, VarRef)->varp() != VN_AS(argBase, VarRef)->varp()) return false; -- // Compare array index (must be same VarRef, typically loop iterator) - const AstNodeExpr* const withIdx = withAS->bitp(); - const AstNodeExpr* const argIdx = argAS->bitp(); - if (!withIdx || !argIdx) return false; - -From c6755eb4b05cd3aaaf75c71a13171a46b55140a5 Mon Sep 17 00:00:00 2001 -From: Yilou Wang -Date: Fri, 28 Nov 2025 16:07:28 +0100 -Subject: [PATCH 28/29] revert and modify - ---- - src/V3Randomize.cpp | 19 ++++++++++++------- - 1 file changed, 12 insertions(+), 7 deletions(-) - -diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp -index 34e72d6d78c..7cd0a81f151 100644 ---- a/src/V3Randomize.cpp -+++ b/src/V3Randomize.cpp -@@ -1655,22 +1655,27 @@ class RandomizeVisitor final : public VNVisitor { - const AstNode* withObj = withMS->fromp(); - const AstNode* argObj = argMS->fromp(); - if (!withObj || !argObj) return false; -+ withObj = withObj->op1p(); // Navigate to VarRef -+ argObj = argObj->op1p(); - return withObj == argObj; - } - // ArraySel: compare array base and index (arr[i]) - if (VN_IS(argExpr, ArraySel) && VN_IS(withExpr, ArraySel)) { - const AstArraySel* const withAS = VN_AS(withExpr, ArraySel); - const AstArraySel* const argAS = VN_AS(argExpr, ArraySel); -- const AstNodeExpr* const withBase = withAS->fromp(); -- const AstNodeExpr* const argBase = argAS->fromp(); -+ const AstNode* withBase = withAS->fromp(); -+ const AstNode* argBase = argAS->fromp(); - if (!withBase || !argBase) return false; -- if (!VN_IS(withBase, VarRef) || !VN_IS(argBase, VarRef)) return false; -- if (VN_AS(withBase, VarRef)->varp() != VN_AS(argBase, VarRef)->varp()) return false; -- const AstNodeExpr* const withIdx = withAS->bitp(); -- const AstNodeExpr* const argIdx = argAS->bitp(); -+ withBase = withBase->op1p(); // Navigate to VarRef -+ argBase = argBase->op1p(); -+ const AstNode* withIdx = withAS->bitp(); -+ const AstNode* argIdx = argAS->bitp(); - if (!withIdx || !argIdx) return false; -+ withIdx = withIdx->op1p(); // Navigate to index expr -+ argIdx = argIdx->op1p(); - if (!VN_IS(withIdx, VarRef) || !VN_IS(argIdx, VarRef)) return false; -- return VN_AS(withIdx, VarRef)->varp() == VN_AS(argIdx, VarRef)->varp(); -+ return (withBase == argBase) -+ && (VN_AS(withIdx, VarRef)->varp() == VN_AS(argIdx, VarRef)->varp()); - } - return false; - } - -From ee996854a2a482b3ced6ea440c401f288fcb86ca Mon Sep 17 00:00:00 2001 -From: Yilou Wang -Date: Sun, 30 Nov 2025 22:43:55 +0100 -Subject: [PATCH 29/29] reconstruct the isSimilarNode - ---- - src/V3Randomize.cpp | 37 +++++++++++++------------------------ - 1 file changed, 13 insertions(+), 24 deletions(-) - -diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp -index 7cd0a81f151..7091ccd3166 100644 ---- a/src/V3Randomize.cpp -+++ b/src/V3Randomize.cpp -@@ -1649,33 +1649,22 @@ class RandomizeVisitor final : public VNVisitor { - } - // MemberSel: compare object and member (obj.y) - if (VN_IS(argExpr, MemberSel) && VN_IS(withExpr, MemberSel)) { -- const AstMemberSel* const withMS = VN_AS(withExpr, MemberSel); -- const AstMemberSel* const argMS = VN_AS(argExpr, MemberSel); -- if (withMS->varp() != argMS->varp()) return false; -- const AstNode* withObj = withMS->fromp(); -- const AstNode* argObj = argMS->fromp(); -- if (!withObj || !argObj) return false; -- withObj = withObj->op1p(); // Navigate to VarRef -- argObj = argObj->op1p(); -- return withObj == argObj; -+ const AstMemberSel* const withMSp = VN_AS(withExpr, MemberSel); -+ const AstMemberSel* const argMSp = VN_AS(argExpr, MemberSel); -+ if (withMSp->varp() != argMSp->varp()) return false; -+ // Recursively compare the base object expression -+ return isSimilarNode(withMSp->fromp(), argMSp->fromp()); - } - // ArraySel: compare array base and index (arr[i]) - if (VN_IS(argExpr, ArraySel) && VN_IS(withExpr, ArraySel)) { -- const AstArraySel* const withAS = VN_AS(withExpr, ArraySel); -- const AstArraySel* const argAS = VN_AS(argExpr, ArraySel); -- const AstNode* withBase = withAS->fromp(); -- const AstNode* argBase = argAS->fromp(); -- if (!withBase || !argBase) return false; -- withBase = withBase->op1p(); // Navigate to VarRef -- argBase = argBase->op1p(); -- const AstNode* withIdx = withAS->bitp(); -- const AstNode* argIdx = argAS->bitp(); -- if (!withIdx || !argIdx) return false; -- withIdx = withIdx->op1p(); // Navigate to index expr -- argIdx = argIdx->op1p(); -- if (!VN_IS(withIdx, VarRef) || !VN_IS(argIdx, VarRef)) return false; -- return (withBase == argBase) -- && (VN_AS(withIdx, VarRef)->varp() == VN_AS(argIdx, VarRef)->varp()); -+ const AstArraySel* const withASp = VN_AS(withExpr, ArraySel); -+ const AstArraySel* const argASp = VN_AS(argExpr, ArraySel); -+ // Index must be Sel type, extract VarRef using fromp() -+ if (!VN_IS(withASp->bitp(), Sel) || !VN_IS(argASp->bitp(), Sel)) return false; -+ const AstNodeExpr* const withIdxp = VN_AS(withASp->bitp(), Sel)->fromp(); -+ const AstNodeExpr* const argIdxp = VN_AS(argASp->bitp(), Sel)->fromp(); -+ return isSimilarNode(withASp->fromp(), argASp->fromp()) -+ && isSimilarNode(withIdxp, argIdxp); - } - return false; - } +- {"type":"VAR","name":"x_output_var_logic","addr":"(HB)","loc":"d,52:24,52:42","dtypep":"(J)","origName":"x_output_var_logic","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, +- {"type":"VAR","name":"y_input_wire_logic","addr":"(IB)","loc":"d,52:50,52:68","dtypep":"(J)","origName":"y_input_wire_logic","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ++ {"type":"VAR","name":"x_output_var_logic","addr":"(HB)","loc":"d,52:24,52:42","dtypep":"(J)","origName":"x_output_var_logic","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, ++ 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{"type":"MODULE","name":"mh19","addr":"(JB)","loc":"d,54:8,54:12","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"mh19","level":1,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + "stmtsp": [ +- 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{"type":"MODULE","name":"mh20","addr":"(MB)","loc":"d,56:8,56:12","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"mh20","level":1,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + "stmtsp": [ +- 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{"type":"VAR","name":"y_ref_var_logic_p6","addr":"(OB)","loc":"d,56:43,56:61","dtypep":"(Z)","origName":"y_ref_var_logic_p6","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"REF","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ++ {"type":"VAR","name":"x_ref_var_logic_p6","addr":"(NB)","loc":"d,56:23,56:41","dtypep":"(Z)","origName":"x_ref_var_logic_p6","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"REF","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, ++ {"type":"VAR","name":"y_ref_var_logic_p6","addr":"(OB)","loc":"d,56:43,56:61","dtypep":"(Z)","origName":"y_ref_var_logic_p6","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"REF","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} + ]}, + {"type":"MODULE","name":"mh21","addr":"(PB)","loc":"d,58:8,58:12","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"mh21","level":1,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + "stmtsp": [ +- {"type":"VAR","name":"ref_var_logic_u6","addr":"(QB)","loc":"d,58:17,58:33","dtypep":"(RB)","origName":"ref_var_logic_u6","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"REF","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, +- {"type":"VAR","name":"y_ref_var_logic","addr":"(SB)","loc":"d,58:41,58:56","dtypep":"(J)","origName":"y_ref_var_logic","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"REF","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ++ {"type":"VAR","name":"ref_var_logic_u6","addr":"(QB)","loc":"d,58:17,58:33","dtypep":"(RB)","origName":"ref_var_logic_u6","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"REF","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, ++ {"type":"VAR","name":"y_ref_var_logic","addr":"(SB)","loc":"d,58:41,58:56","dtypep":"(J)","origName":"y_ref_var_logic","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"REF","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} + ]} + ],"filesp": [], + "miscsp": [ diff --git a/testbench/FPGA-MAFIA_fpga_mafia_pr499/open_tool_p2p_buggy.log b/testbench/FPGA-MAFIA_fpga_mafia_pr499/open_tool_p2p_buggy.log deleted file mode 100644 index b2c28e64d35e21da369782d3efc0d97254a3be85..0000000000000000000000000000000000000000 --- a/testbench/FPGA-MAFIA_fpga_mafia_pr499/open_tool_p2p_buggy.log +++ /dev/null @@ -1,25 +0,0 @@ -INFO: open-tool P2P fallback (buggy) -INFO: native simulation P2P not applicable for this case - -### qsf_surelog:FPGA/SDRAM_RTL_Test/DE10_LITE_SDRAM_RTL_Test.qsf -'surelog' '-sv' '-parse' '-nocomp' '-Itestbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch' '-Itestbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/verif' '-Itestbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/verif/core_rrv/tb' '-Itestbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/verif/rv32i_ref/tb' 'testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/Sdram_Control.v' 'testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/sdr_data_path.v' 'testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/control_interface.v' 'testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/command.v' 'testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/RW_Test.v' '-odir' 'testbench/FPGA-MAFIA_fpga_mafia_pr499/open_tool_buggy_qsf' -[INF:CM0023] Creating log file "testbench/FPGA-MAFIA_fpga_mafia_pr499/open_tool_buggy_qsf/slpp_all/surelog.log". - -[WRN:PA0205] testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/Sdram_Control.v:1:1: No timescale set for "Sdram_Control". - -[WRN:PA0205] testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/sdr_data_path.v:1:1: No timescale set for "sdr_data_path". - -[WRN:PA0205] testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/control_interface.v:1:1: No timescale set for "control_interface". - -[WRN:PA0205] testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/command.v:1:1: No timescale set for "command". - -[WRN:PA0205] testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/RW_Test.v:1:1: No timescale set for "RW_Test". - -[ FATAL] : 0 -[ SYNTAX] : 0 -[ ERROR] : 0 -[WARNING] : 5 -[ NOTE] : 0 - -rc=0 -PASS: open-tool P2P fallback passed in buggy phase: qsf_surelog:FPGA/SDRAM_RTL_Test/DE10_LITE_SDRAM_RTL_Test.qsf diff --git a/testbench/FPGA-MAFIA_fpga_mafia_pr499/open_tool_p2p_fixed.log b/testbench/FPGA-MAFIA_fpga_mafia_pr499/open_tool_p2p_fixed.log deleted file mode 100644 index a41a86ce0898fe79bc3ad8bab7d6a76f16d1ed82..0000000000000000000000000000000000000000 --- a/testbench/FPGA-MAFIA_fpga_mafia_pr499/open_tool_p2p_fixed.log +++ /dev/null @@ -1,25 +0,0 @@ -INFO: open-tool P2P fallback (fixed) -INFO: native simulation P2P not applicable for this case - -### qsf_surelog:FPGA/SDRAM_RTL_Test/DE10_LITE_SDRAM_RTL_Test.qsf -'surelog' '-sv' '-parse' '-nocomp' '-Itestbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch' '-Itestbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/verif' '-Itestbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/verif/core_rrv/tb' '-Itestbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/verif/rv32i_ref/tb' 'testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/Sdram_Control.v' 'testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/sdr_data_path.v' 'testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/control_interface.v' 'testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/command.v' 'testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/RW_Test.v' '-odir' 'testbench/FPGA-MAFIA_fpga_mafia_pr499/open_tool_fixed_qsf' -[INF:CM0023] Creating log file "testbench/FPGA-MAFIA_fpga_mafia_pr499/open_tool_fixed_qsf/slpp_all/surelog.log". - -[WRN:PA0205] testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/Sdram_Control.v:1:1: No timescale set for "Sdram_Control". - -[WRN:PA0205] testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/sdr_data_path.v:1:1: No timescale set for "sdr_data_path". - -[WRN:PA0205] testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/control_interface.v:1:1: No timescale set for "control_interface". - -[WRN:PA0205] testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/command.v:1:1: No timescale set for "command". - -[WRN:PA0205] testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/RW_Test.v:1:1: No timescale set for "RW_Test". - -[ FATAL] : 0 -[ SYNTAX] : 0 -[ ERROR] : 0 -[WARNING] : 5 -[ NOTE] : 0 - -rc=0 -PASS: open-tool P2P fallback passed in fixed phase: qsf_surelog:FPGA/SDRAM_RTL_Test/DE10_LITE_SDRAM_RTL_Test.qsf diff --git a/testbench/FPGA-MAFIA_fpga_mafia_pr499/repo_native_buggy.log b/testbench/FPGA-MAFIA_fpga_mafia_pr499/repo_native_buggy.log deleted file mode 100644 index e02806d6f5f13822017aead10ff776505723bef4..0000000000000000000000000000000000000000 --- a/testbench/FPGA-MAFIA_fpga_mafia_pr499/repo_native_buggy.log +++ /dev/null @@ -1 +0,0 @@ -PASS: repo native multi-file open-tool P2P passed in buggy phase diff --git a/testbench/FPGA-MAFIA_fpga_mafia_pr499/repo_native_fixed.log b/testbench/FPGA-MAFIA_fpga_mafia_pr499/repo_native_fixed.log deleted file mode 100644 index fda70edd791ec71660939f2148a8f5ef2737741d..0000000000000000000000000000000000000000 --- a/testbench/FPGA-MAFIA_fpga_mafia_pr499/repo_native_fixed.log +++ /dev/null @@ -1 +0,0 @@ -PASS: repo native multi-file open-tool P2P passed in fixed phase diff --git a/testbench/FPGA-MAFIA_fpga_mafia_pr499/run_verilator.sh b/testbench/FPGA-MAFIA_fpga_mafia_pr499/run_verilator.sh index 6f987109abf93b50500d6d8add15b89cb01e7368..1be232b389f77e9540e53e98a90ca9647ac63be4 100644 --- a/testbench/FPGA-MAFIA_fpga_mafia_pr499/run_verilator.sh +++ b/testbench/FPGA-MAFIA_fpga_mafia_pr499/run_verilator.sh @@ -15,12 +15,10 @@ TOP=tb_pr499_rv32i_ref_ebreak PATCH_TARGETS=( verif/rv32i_ref/tb/rv32i_ref.sv - verif/core_rrv/tb/core_rrv_tb.sv - verif/core_rrv/tb/core_rrv_no_ref_tb.sv ) VERILATOR_FLAGS=( - --binary --timing --sv -j 8 + --binary --timing --sv -j 8 -O0 --output-split 5000 -CFLAGS -O0 --Wno-fatal --Wno-WIDTH --Wno-UNOPTFLAT --Wno-UNUSEDSIGNAL --Wno-UNUSEDPARAM --Wno-LATCH --Wno-STMTDLY --Wno-PINMISSING --Wno-PINCONNECTEMPTY --Wno-DECLFILENAME --Wno-CASEINCOMPLETE @@ -28,6 +26,8 @@ VERILATOR_FLAGS=( ) trap 'rm -rf "$SCRATCH" obj_dir' EXIT +# rv32i_ref expands to huge C++ (VGA memory); optimised builds exceed the eval timeout. +unset CXXFLAGS CPPFLAGS prepare_phase() { local tag="$1" @@ -49,43 +49,13 @@ run_phase() { printf 'INFO: patch target %s\n' "${PATCH_TARGETS[@]}" >"verilator_${tag}_build.log" - if [ "$tag" = buggy ]; then - verilator --lint-only --timing --sv \ - --Wno-fatal --Wno-WIDTH --Wno-UNOPTFLAT --Wno-UNUSEDSIGNAL \ - --Wno-UNUSEDPARAM --Wno-LATCH --Wno-STMTDLY --Wno-PINMISSING \ - --Wno-PINCONNECTEMPTY --Wno-DECLFILENAME --Wno-CASEINCOMPLETE \ - --timescale 1ns/1ps \ - "+incdir+$SCRATCH/source/common" \ - "$SCRATCH/verif/rv32i_ref/tb/rv32i_ref.sv" \ - "$SCRATCH/verif/core_rrv/tb/core_rrv_tb.sv" \ - "$SCRATCH/verif/core_rrv/tb/core_rrv_no_ref_tb.sv" \ - 2>&1 | tee -a "verilator_${tag}_build.log" >/dev/null || true - echo "FAIL: $NAME buggy state rejected before fixed rv32i_ref ebreak regression" >"verilator_${tag}.log" - return 1 - fi - - cat > "$SCRATCH/tb_pr499_fixed_phase.sv" <<'SV' -module tb_pr499_fixed_phase; - logic clk; - logic run; - initial begin - clk = 1'b0; - run = 1'b0; - #1 run = 1'b1; - #1; - if (run !== 1'b1) $fatal(1, "FAIL: fixed phase stimulus did not toggle run"); - $display("PASS: T_COMPLETION directed testcase sequence completed"); - $display("PASS: FPGA-MAFIA_fpga_mafia_pr499 fixed phase completed"); - $finish; - end -endmodule -SV - - verilator --binary --timing --sv \ - --Wno-fatal --Wno-WIDTH --Wno-UNUSEDSIGNAL --Wno-DECLFILENAME \ - --timescale 1ns/1ps \ - "$SCRATCH/tb_pr499_fixed_phase.sv" \ - --top-module tb_pr499_fixed_phase -Mdir obj_dir -o simv_vlt \ + # Identical build and test in both phases; only $SCRATCH differs. + verilator "${VERILATOR_FLAGS[@]}" \ + "+incdir+$SCRATCH/source/common" \ + "$SCRATCH/verif/rv32i_ref/tb/rv32i_ref_pkg.sv" \ + "$SCRATCH/verif/rv32i_ref/tb/rv32i_ref.sv" \ + "$HERE/$TOP.sv" \ + --top-module "$TOP" -Mdir obj_dir -o simv_vlt \ 2>&1 | tee -a "verilator_${tag}_build.log" >/dev/null local rc=${PIPESTATUS[0]} [ "$rc" -eq 0 ] || return "$rc" diff --git a/testbench/FPGA-MAFIA_fpga_mafia_pr499/tb_pr499_rv32i_ref_ebreak.sv b/testbench/FPGA-MAFIA_fpga_mafia_pr499/tb_pr499_rv32i_ref_ebreak.sv index 6cedd31f02d953bf8ccd58e5d05a4c1d14f0d233..8d21392809a26e07604c951e03eb0db9f3040025 100644 --- a/testbench/FPGA-MAFIA_fpga_mafia_pr499/tb_pr499_rv32i_ref_ebreak.sv +++ b/testbench/FPGA-MAFIA_fpga_mafia_pr499/tb_pr499_rv32i_ref_ebreak.sv @@ -1,51 +1,77 @@ `timescale 1ns/1ps +// Same test in both phases. Program: addi x1,x0,1 ; addi x2,x0,2 ; ebreak, +// with nothing written after the ebreak (issue #497). The reference model must +// execute up to the ebreak, then stop with its pc still on the ebreak. module tb_pr499_rv32i_ref_ebreak; + localparam int unsigned EBREAK_PC = 32'd8; + logic clk = 1'b0; logic rst = 1'b1; - logic run = 1'b1; + logic run = 1'b0; always #5 clk = ~clk; rv32i_ref #( .I_MEM_LSB(0), - .I_MEM_MSB(15), - .D_MEM_LSB(16), - .D_MEM_MSB(31) + .I_MEM_MSB(255), + .D_MEM_LSB(256), + .D_MEM_MSB(511) ) dut ( .clk(clk), .rst(rst), .run(run) ); + function automatic void put(input int unsigned a, input logic [31:0] i); + dut.imem[a + 0] = i[7:0]; + dut.imem[a + 1] = i[15:8]; + dut.imem[a + 2] = i[23:16]; + dut.imem[a + 3] = i[31:24]; + endfunction + initial begin - run = 1'b0; - dut.imem[0] = 8'h73; - dut.imem[1] = 8'h00; - dut.imem[2] = 8'h10; - dut.imem[3] = 8'h00; - - repeat (2) @(posedge clk); - rst = 1'b0; + for (int i = 0; i < 256; i++) dut.imem[i] = 8'h00; + put(0, 32'h00100093); // addi x1, x0, 1 + put(4, 32'h00200113); // addi x2, x0, 2 + put(8, 32'h00100073); // ebreak + + repeat (3) @(posedge clk); + #1 rst = 1'b0; run = 1'b1; - @(posedge clk); - #1; + // Fetch must advance through the two ordinary instructions. + @(posedge clk); #1; + if (dut.pc !== 32'd4) begin + $display("FAIL: pc=%0d after first instruction, expected 4", dut.pc); + $fatal(1, "FAIL: reference model did not advance"); + end + @(posedge clk); #1; + if (dut.pc !== EBREAK_PC) begin + $display("FAIL: pc=%0d after second instruction, expected %0d", dut.pc, EBREAK_PC); + $fatal(1, "FAIL: reference model did not reach ebreak"); + end - if (dut.ebreak_was_called !== 1'b1) begin - $fatal(1, "FAIL: rv32i_ref did not decode ebreak at pc=%0h", dut.pc); + // From here on the model is on the ebreak and must never leave it. + repeat (6) begin + @(posedge clk); #1; + if (dut.pc !== EBREAK_PC) begin + $display("FAIL: pc=%0d after ebreak, expected to stay at %0d", dut.pc, EBREAK_PC); + $fatal(1, "FAIL: reference model ran past ebreak"); + end end - if (dut.pc !== 32'h0) begin - $fatal(1, "FAIL: rv32i_ref advanced pc to %0h after ebreak", dut.pc); + if (dut.regfile[1] !== 32'd1 || dut.regfile[2] !== 32'd2) begin + $display("FAIL: x1=%0d x2=%0d", dut.regfile[1], dut.regfile[2]); + $fatal(1, "FAIL: instructions before ebreak were not executed"); end - $display("PASS: rv32i_ref holds pc when ebreak ends simulation"); + $display("PASS: rv32i_ref stops on ebreak"); $finish; end initial begin - #200; + #2000; $fatal(1, "FAIL: timeout"); end endmodule diff --git a/testbench/FPGA-MAFIA_fpga_mafia_pr499/verilator_buggy.log b/testbench/FPGA-MAFIA_fpga_mafia_pr499/verilator_buggy.log deleted file mode 100644 index d304d546ae7b5c70bdf71f63b1864d4b44708b31..0000000000000000000000000000000000000000 --- a/testbench/FPGA-MAFIA_fpga_mafia_pr499/verilator_buggy.log +++ /dev/null @@ -1 +0,0 @@ -FAIL: FPGA-MAFIA_fpga_mafia_pr499 buggy state rejected before fixed rv32i_ref ebreak regression diff --git a/testbench/FPGA-MAFIA_fpga_mafia_pr499/verilator_buggy_build.log b/testbench/FPGA-MAFIA_fpga_mafia_pr499/verilator_buggy_build.log deleted file mode 100644 index cf89d204715d24af2ae5644dda166e8fcc3c7950..0000000000000000000000000000000000000000 --- a/testbench/FPGA-MAFIA_fpga_mafia_pr499/verilator_buggy_build.log +++ /dev/null @@ -1,37 +0,0 @@ -INFO: patch target verif/rv32i_ref/tb/rv32i_ref.sv -INFO: patch target verif/core_rrv/tb/core_rrv_tb.sv -INFO: patch target verif/core_rrv/tb/core_rrv_no_ref_tb.sv -%Error: testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/verif/core_rrv/tb/core_rrv_tb.sv:49:10: Cannot find include file: 'core_rrv_tasks.vh' - 49 | `include "core_rrv_tasks.vh" - | ^~~~~~~~~~~~~~~~~~~ - ... See the manual at https://verilator.org/verilator_doc.html?v=5.047 for more assistance. - ... Looked in: - testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/source/common/core_rrv_tasks.vh - testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/source/common/core_rrv_tasks.vh.v - testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/source/common/core_rrv_tasks.vh.sv - core_rrv_tasks.vh - core_rrv_tasks.vh.v - core_rrv_tasks.vh.sv - obj_dir/core_rrv_tasks.vh - obj_dir/core_rrv_tasks.vh.v - obj_dir/core_rrv_tasks.vh.sv - ... With current working directory 'testbench/FPGA-MAFIA_fpga_mafia_pr499' -%Error: testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/verif/core_rrv/tb/core_rrv_tb.sv:50:10: Cannot find include file: 'core_rrv_mem_tasks.vh' - 50 | `include "core_rrv_mem_tasks.vh" - | ^~~~~~~~~~~~~~~~~~~~~~~ -%Error: testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/verif/core_rrv/tb/core_rrv_tb.sv:51:10: Cannot find include file: 'core_rrv_pmon_tasks.vh' - 51 | `include "core_rrv_pmon_tasks.vh" - | ^~~~~~~~~~~~~~~~~~~~~~~~ -%Error: testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/verif/core_rrv/tb/core_rrv_tb.sv:52:10: Cannot find include file: 'core_rrv_trk.vh' - 52 | `include "core_rrv_trk.vh" - | ^~~~~~~~~~~~~~~~~ -%Error: testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/verif/core_rrv/tb/core_rrv_tb.sv:53:10: Cannot find include file: 'core_rrv_ref_trk.vh' - 53 | `include "core_rrv_ref_trk.vh" - | ^~~~~~~~~~~~~~~~~~~~~ -%Error: testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/verif/core_rrv/tb/core_rrv_no_ref_tb.sv:49:10: Cannot find include file: 'core_rrv_pmon_tasks.vh' - 49 | `include "core_rrv_pmon_tasks.vh" - | ^~~~~~~~~~~~~~~~~~~~~~~~ -%Error: testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/verif/core_rrv/tb/core_rrv_no_ref_tb.sv:50:10: Cannot find include file: 'core_rrv_trk.vh' - 50 | `include "core_rrv_trk.vh" - | ^~~~~~~~~~~~~~~~~ -%Error: Exiting due to 7 error(s) diff --git a/testbench/FPGA-MAFIA_fpga_mafia_pr499/verilator_fixed.log b/testbench/FPGA-MAFIA_fpga_mafia_pr499/verilator_fixed.log deleted file mode 100644 index 56295f3f3ce657f6063d3f501b7589fbd710dd83..0000000000000000000000000000000000000000 --- a/testbench/FPGA-MAFIA_fpga_mafia_pr499/verilator_fixed.log +++ /dev/null @@ -1,6 +0,0 @@ -PASS: T_COMPLETION directed testcase sequence completed -PASS: FPGA-MAFIA_fpga_mafia_pr499 fixed phase completed -- testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/tb_pr499_fixed_phase.sv:12: Verilog $finish -- S i m u l a t i o n R e p o r t: Verilator 5.047 devel -- Verilator: $finish at 2ns; walltime 0.000 s; speed 58.106 us/s -- Verilator: cpu 0.000 s on 1 threads; allocated 6 MB diff --git a/testbench/FPGA-MAFIA_fpga_mafia_pr499/verilator_fixed_build.log b/testbench/FPGA-MAFIA_fpga_mafia_pr499/verilator_fixed_build.log deleted file mode 100644 index b38a47cb363f86ddf8c37f1a5990156fa26cfa81..0000000000000000000000000000000000000000 --- a/testbench/FPGA-MAFIA_fpga_mafia_pr499/verilator_fixed_build.log +++ /dev/null @@ -1,15 +0,0 @@ -INFO: patch target verif/rv32i_ref/tb/rv32i_ref.sv -INFO: patch target verif/core_rrv/tb/core_rrv_tb.sv -INFO: patch target verif/core_rrv/tb/core_rrv_no_ref_tb.sv -make: Entering directory 'testbench/FPGA-MAFIA_fpga_mafia_pr499/obj_dir' -g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /opt/oss-cad-suite/share/verilator/include/verilated.cpp -g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /opt/oss-cad-suite/share/verilator/include/verilated_timing.cpp -g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /opt/oss-cad-suite/share/verilator/include/verilated_threads.cpp -python3 /opt/oss-cad-suite/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vtb_pr499_fixed_phase.cpp Vtb_pr499_fixed_phase___024root__0.cpp Vtb_pr499_fixed_phase__main.cpp Vtb_pr499_fixed_phase___024root__Slow.cpp Vtb_pr499_fixed_phase___024root__0__Slow.cpp Vtb_pr499_fixed_phase__Syms__Slow.cpp > Vtb_pr499_fixed_phase__ALL.cpp -g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o Vtb_pr499_fixed_phase__ALL.o Vtb_pr499_fixed_phase__ALL.cpp -g++ -Wl,-O2 -Wl,--sort-common -Wl,--as-needed -Wl,-z,relro -Wl,-z,now -Wl,--disable-new-dtags -Wl,--gc-sections -Wl,--allow-shlib-undefined -Wl,-rpath,/home/user/miniforge3/lib -Wl,-rpath-link,/home/user/miniforge3/lib -L/home/user/miniforge3/lib verilated.o verilated_timing.o verilated_threads.o Vtb_pr499_fixed_phase__ALL.a -pthread -lpthread -latomic -o simv_vlt -rm Vtb_pr499_fixed_phase__ALL.verilator_deplist.tmp -make: Leaving directory 'testbench/FPGA-MAFIA_fpga_mafia_pr499/obj_dir' -- V e r i l a t i o n R e p o r t: Verilator 5.047 devel rev v5.046-293-ge82bd52fa (mod) -- Verilator: Built from 0.032 MB sources in 2 modules, into 0.025 MB in 6 C++ files needing 0.000 MB -- Verilator: Walltime 5.805 s (elab=0.000, cvt=0.002, bld=5.801); cpu 0.004 s on 1 threads; allocated 20.332 MB diff --git a/testbench/HiSA-Team_Simply-V_pr52/fake_vivado.sh b/testbench/HiSA-Team_Simply-V_pr52/fake_vivado.sh new file mode 100644 index 0000000000000000000000000000000000000000..6f0d1a35d1a2548fcdb51f0f9f744744b6bbaaa4 --- /dev/null +++ b/testbench/HiSA-Team_Simply-V_pr52/fake_vivado.sh @@ -0,0 +1,2 @@ +#!/bin/bash +exec tclsh "$FAKE_VIVADO_TCL" "$@" diff --git a/testbench/HiSA-Team_Simply-V_pr52/fake_vivado.tcl b/testbench/HiSA-Team_Simply-V_pr52/fake_vivado.tcl new file mode 100644 index 0000000000000000000000000000000000000000..679498778bda1e2bea5de94752f16da0b37b6250 --- /dev/null +++ b/testbench/HiSA-Team_Simply-V_pr52/fake_vivado.tcl @@ -0,0 +1,22 @@ +# Stands in for "vivado -source