| INFO: open-tool P2P fallback (fixed) | |
| ### native_sim:multimedia_repo_tb | |
| 'sh' '-c' 'iverilog -g2012 -Wall -o native_probe.vvp VerilogHDL_Practice/CH3/wire_and_or.v VerilogHDL_Practice/CH3/wire_and_or_test.v && timeout 20 vvp -n native_probe.vvp' | |
| warning: Some design elements have no explicit time unit and/or | |
| : time precision. This may cause confusing timing results. | |
| : Affected design elements are: | |
| : -- module wire_and_or declared here: VerilogHDL_Practice/CH3/wire_and_or.v:1 | |
| VerilogHDL_Practice/CH3/wire_and_or_test.v:31: $stop called at 400000 (1ps) | |
| rc=0 | |
| PASS: native simulation P2P passed in fixed phase: multimedia_repo_tb | |