| PASS: op module arithmetic/bit operations verified | |
| - testbench/Multimedia-Processing_Digital-Logic-Design_pr60/tb_op_verilator.sv:26: Verilog $finish | |
| PASS: op module arithmetic/bit operations verified | |
| - testbench/Multimedia-Processing_Digital-Logic-Design_pr60/tb_op_verilator.sv:26: Verilog $finish | |