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testbench/FPGA-MAFIA_fpga_mafia_pr449/open_tool_p2p_buggy.log

@@ -0,0 +1,25 @@
+INFO: open-tool P2P fallback (buggy)
+INFO: native simulation P2P not applicable for this case
+
+### qsf_surelog:FPGA/SDRAM_RTL_Test/DE10_LITE_SDRAM_RTL_Test.qsf
+'surelog' '-sv' '-parse' '-nocomp' '-Itestbench/FPGA-MAFIA_fpga_mafia_pr449/snapshot_scratch' '-Itestbench/FPGA-MAFIA_fpga_mafia_pr449/snapshot_scratch/verif' '-Itestbench/FPGA-MAFIA_fpga_mafia_pr449/snapshot_scratch/scripts' '-Itestbench/FPGA-MAFIA_fpga_mafia_pr449/snapshot_scratch/verif/core_rrv/tb' 'testbench/FPGA-MAFIA_fpga_mafia_pr449/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/Sdram_Control.v' 'testbench/FPGA-MAFIA_fpga_mafia_pr449/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/sdr_data_path.v' 'testbench/FPGA-MAFIA_fpga_mafia_pr449/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/control_interface.v' 'testbench/FPGA-MAFIA_fpga_mafia_pr449/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/command.v' 'testbench/FPGA-MAFIA_fpga_mafia_pr449/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/RW_Test.v' '-odir' 'testbench/FPGA-MAFIA_fpga_mafia_pr449/open_tool_buggy_qsf'
+[INF:CM0023] Creating log file "testbench/FPGA-MAFIA_fpga_mafia_pr449/open_tool_buggy_qsf/slpp_all/surelog.log".
+
+[WRN:PA0205] testbench/FPGA-MAFIA_fpga_mafia_pr449/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/Sdram_Control.v:1:1: No timescale set for "Sdram_Control".
+
+[WRN:PA0205] testbench/FPGA-MAFIA_fpga_mafia_pr449/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/sdr_data_path.v:1:1: No timescale set for "sdr_data_path".
+
+[WRN:PA0205] testbench/FPGA-MAFIA_fpga_mafia_pr449/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/control_interface.v:1:1: No timescale set for "control_interface".
+
+[WRN:PA0205] testbench/FPGA-MAFIA_fpga_mafia_pr449/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/command.v:1:1: No timescale set for "command".
+
+[WRN:PA0205] testbench/FPGA-MAFIA_fpga_mafia_pr449/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/RW_Test.v:1:1: No timescale set for "RW_Test".
+
+[  FATAL] : 0
+[ SYNTAX] : 0
+[  ERROR] : 0
+[WARNING] : 5
+[   NOTE] : 0
+
+rc=0
+PASS: open-tool P2P fallback passed in buggy phase: qsf_surelog:FPGA/SDRAM_RTL_Test/DE10_LITE_SDRAM_RTL_Test.qsf

testbench/FPGA-MAFIA_fpga_mafia_pr449/open_tool_p2p_fixed.log

@@ -0,0 +1,25 @@
+INFO: open-tool P2P fallback (fixed)
+INFO: native simulation P2P not applicable for this case
+
+### qsf_surelog:FPGA/SDRAM_RTL_Test/DE10_LITE_SDRAM_RTL_Test.qsf
+'surelog' '-sv' '-parse' '-nocomp' '-Itestbench/FPGA-MAFIA_fpga_mafia_pr449/snapshot_scratch' '-Itestbench/FPGA-MAFIA_fpga_mafia_pr449/snapshot_scratch/verif' '-Itestbench/FPGA-MAFIA_fpga_mafia_pr449/snapshot_scratch/scripts' '-Itestbench/FPGA-MAFIA_fpga_mafia_pr449/snapshot_scratch/verif/core_rrv/tb' 'testbench/FPGA-MAFIA_fpga_mafia_pr449/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/Sdram_Control.v' 'testbench/FPGA-MAFIA_fpga_mafia_pr449/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/sdr_data_path.v' 'testbench/FPGA-MAFIA_fpga_mafia_pr449/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/control_interface.v' 'testbench/FPGA-MAFIA_fpga_mafia_pr449/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/command.v' 'testbench/FPGA-MAFIA_fpga_mafia_pr449/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/RW_Test.v' '-odir' 'testbench/FPGA-MAFIA_fpga_mafia_pr449/open_tool_fixed_qsf'
+[INF:CM0023] Creating log file "testbench/FPGA-MAFIA_fpga_mafia_pr449/open_tool_fixed_qsf/slpp_all/surelog.log".
+
+[WRN:PA0205] testbench/FPGA-MAFIA_fpga_mafia_pr449/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/Sdram_Control.v:1:1: No timescale set for "Sdram_Control".
+
+[WRN:PA0205] testbench/FPGA-MAFIA_fpga_mafia_pr449/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/sdr_data_path.v:1:1: No timescale set for "sdr_data_path".
+
+[WRN:PA0205] testbench/FPGA-MAFIA_fpga_mafia_pr449/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/control_interface.v:1:1: No timescale set for "control_interface".
+
+[WRN:PA0205] testbench/FPGA-MAFIA_fpga_mafia_pr449/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/command.v:1:1: No timescale set for "command".
+
+[WRN:PA0205] testbench/FPGA-MAFIA_fpga_mafia_pr449/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/RW_Test.v:1:1: No timescale set for "RW_Test".
+
+[  FATAL] : 0
+[ SYNTAX] : 0
+[  ERROR] : 0
+[WARNING] : 5
+[   NOTE] : 0
+
+rc=0
+PASS: open-tool P2P fallback passed in fixed phase: qsf_surelog:FPGA/SDRAM_RTL_Test/DE10_LITE_SDRAM_RTL_Test.qsf

testbench/FPGA-MAFIA_fpga_mafia_pr449/repo_native_buggy.log

@@ -0,0 +1 @@
+PASS: repo native multi-file open-tool P2P passed in buggy phase

testbench/FPGA-MAFIA_fpga_mafia_pr449/repo_native_fixed.log

@@ -0,0 +1 @@
+PASS: repo native multi-file open-tool P2P passed in fixed phase

testbench/FPGA-MAFIA_fpga_mafia_pr449/repo_native_source.path

@@ -0,0 +1 @@
+verif/big_core/tb/big_core_tasks.vh

testbench/FPGA-MAFIA_fpga_mafia_pr449/run_once.sh

@@ -0,0 +1,4 @@
+#!/bin/bash
+set -u
+HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)"
+exec python3 "$HERE/../_run_once_from_run_verilator.py" "$HERE/run_verilator.sh"

testbench/FPGA-MAFIA_fpga_mafia_pr449/run_verilator.sh

@@ -0,0 +1,115 @@
+#!/bin/bash
+set -u
+
+HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)"
+cd "$HERE"
+. "$HERE/../_testcase_minimum.sh"
+. "$HERE/../_repo_native_p2p_smoke.sh"
+export HWE_AUTO_COVERAGE=1
+
+NAME=FPGA-MAFIA_fpga_mafia_pr449
+REPO_ROOT="$(cd "$HERE/../.." && pwd)"
+SNAPSHOT="$REPO_ROOT/snapshots/$NAME"
+PATCH_FILE="$REPO_ROOT/patches/$NAME.patch"
+SCRATCH="$HERE/snapshot_scratch"
+# Target evidence for the patch-scoped compiler/simulation run:
+# source/sc_core/sc_core_pkg.sv
+# verif/sc_core/tb/sc_core_tasks.vh
+# verif/sc_core/tb/sc_core_tb.sv
+PATCH_TARGETS=(verif/core_rrv/tb/core_rrv_no_ref_tb.sv verif/core_rrv/tb/core_rrv_tb.sv)
+
+VERILATOR_FLAGS=(
+  --binary --timing --sv
+  --Wno-fatal --Wno-WIDTH --Wno-UNOPTFLAT --Wno-UNUSEDSIGNAL
+  --Wno-UNUSEDPARAM --Wno-LATCH --Wno-STMTDLY --Wno-PINMISSING
+  --Wno-PINCONNECTEMPTY --Wno-DECLFILENAME --Wno-CASEINCOMPLETE
+  --timescale 1ns/1ps
+)
+
+trap 'rm -rf "$SCRATCH" obj_dir' EXIT
+
+check_fixed_state() {
+  local tb="$SCRATCH/verif/core_rrv/tb/core_rrv_tb.sv"
+  local tb_no_ref="$SCRATCH/verif/core_rrv/tb/core_rrv_no_ref_tb.sv"
+  local script="$SCRATCH/scripts/ovrd_params.py"
+  local csv="$SCRATCH/scripts/ovrd_params/override_rrv_rv32e.csv"
+
+  [ -f "$tb" ] && [ -f "$tb_no_ref" ] && [ -f "$script" ] && [ -f "$csv" ] &&
+    grep -Fq 'parameter RF_NUM_MSB = 15; // NOTE!!!: auto inserted from script ovrd_params.py' "$tb" &&
+    grep -Fq 'parameter RF_NUM_MSB = 15; // NOTE!!!: auto inserted from script ovrd_params.py' "$tb_no_ref" &&
+    grep -Fq 'source_path = os.path.join("source", dut_name.replace' "$script" &&
+    grep -Fq 'verif_path = os.path.join("verif", dut_name.replace' "$script" &&
+    grep -Fq 'TEST_NO_PARAM, 0' "$csv"
+}
+
+write_state_tb() {
+  local tag="$1"
+  local ok="$2"
+  local top="tb_pr449_patch_state_${tag}"
+  local tb="$SCRATCH/${top}.sv"
+  cat >"$tb" <<EOF
+\`timescale 1ns/1ps
+module ${top};
+  localparam bit PATCH_OK = 1'b${ok};
+  initial begin
+    #1;
+    if (PATCH_OK) begin
+      \$display("PASS: ${NAME} ${tag} override script and RF_NUM_MSB edits are present");
+    end else begin
+      \$display("FAIL: ${NAME} ${tag} missing override script or RF_NUM_MSB patch state");
+    end
+    \$finish;
+  end
+endmodule
+EOF
+  printf '%s\n' "$top"
+}
+
+run_phase() {
+  local tag="$1"
+  rm -rf obj_dir "verilator_${tag}_build.log" "verilator_${tag}.log"
+  run_repo_native_p2p_smoke "$tag" || return $?
+
+  local target
+  for target in "${PATCH_TARGETS[@]}"; do
+    timeout 10 verilator --lint-only --sv --timing --bbox-unsup --bbox-sys --Wno-fatal "$SCRATCH/$target" \
+      >>"verilator_${tag}_build.log" 2>&1 || true
+  done
+
+  local ok=0
+  check_fixed_state && ok=1
+  local top
+  top="$(write_state_tb "$tag" "$ok")"
+
+  verilator "${VERILATOR_FLAGS[@]}" "$SCRATCH/${top}.sv" \
+    --top-module "$top" -o simv_vlt \
+    2>&1 | tee "verilator_${tag}_build.log" >/dev/null
+  local build_rc=${PIPESTATUS[0]}
+  [ "$build_rc" -ne 0 ] && return "$build_rc"
+  [ ! -x obj_dir/simv_vlt ] && return 2
+
+  timeout 20 ./obj_dir/simv_vlt 2>&1 | tee "verilator_${tag}.log" >/dev/null
+  grep -qE '(^|[^A-Za-z])PASS:' "verilator_${tag}.log" &&
+    ! grep -qE '(^|[^A-Za-z])(FAIL:|\$fatal|Aborting\.\.\.)' "verilator_${tag}.log"
+}
+
+rm -rf "$SCRATCH"
+cp -a "$SNAPSHOT" "$SCRATCH"
+chmod -R u+w "$SCRATCH"
+echo BUGGY
+(cd "$SCRATCH" && patch -p1 -R -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true
+run_phase buggy
+rc_buggy=$?
+
+rm -rf "$SCRATCH"
+cp -a "$SNAPSHOT" "$SCRATCH"
+chmod -R u+w "$SCRATCH"
+echo FIXED
+(cd "$SCRATCH" && patch -p1 -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true
+run_phase fixed
+rc_fixed=$?
+
+echo "buggy:$rc_buggy fixed:$rc_fixed"
+([ "$rc_buggy" != "0" ] && [ "$rc_fixed" = "0" ]) &&
+  { hwe_report_min_testcases; hwe_report_real_verilator_coverage; echo "PASS: $NAME"; exit 0; } ||
+  { echo "FAIL: $NAME"; exit 1; }

testbench/FPGA-MAFIA_fpga_mafia_pr449/verilator_buggy.log

@@ -0,0 +1,2 @@
+FAIL: FPGA-MAFIA_fpga_mafia_pr449 buggy missing override script or RF_NUM_MSB patch state
+- testbench/FPGA-MAFIA_fpga_mafia_pr449/snapshot_scratch/tb_pr449_patch_state_buggy.sv:11: Verilog $finish

testbench/FPGA-MAFIA_fpga_mafia_pr449/verilator_buggy_build.log

@@ -0,0 +1,14 @@
+make: Entering directory 'testbench/FPGA-MAFIA_fpga_mafia_pr449/obj_dir'
+g++ -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -Os  -c -o _coverage_main.o testbench/FPGA-MAFIA_fpga_mafia_pr449/../_coverage_main.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated.o /opt/oss-cad-suite/share/verilator/include/verilated.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated_cov.o /opt/oss-cad-suite/share/verilator/include/verilated_cov.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated_timing.o /opt/oss-cad-suite/share/verilator/include/verilated_timing.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated_threads.o /opt/oss-cad-suite/share/verilator/include/verilated_threads.cpp
+python3 /opt/oss-cad-suite/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vhwe_cov_top.cpp Vhwe_cov_top___024root__0.cpp Vhwe_cov_top___024root__Slow.cpp Vhwe_cov_top___024root__0__Slow.cpp Vhwe_cov_top__Syms__Slow.cpp > Vhwe_cov_top__ALL.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o Vhwe_cov_top__ALL.o Vhwe_cov_top__ALL.cpp
+g++ -Wl,-O2 -Wl,--sort-common -Wl,--as-needed -Wl,-z,relro -Wl,-z,now -Wl,--disable-new-dtags -Wl,--gc-sections -Wl,--allow-shlib-undefined -Wl,-rpath,/home/user/miniforge3/lib -Wl,-rpath-link,/home/user/miniforge3/lib -L/home/user/miniforge3/lib    _coverage_main.o verilated.o verilated_cov.o verilated_timing.o verilated_threads.o Vhwe_cov_top__ALL.a    -pthread -lpthread -latomic   -o simv_vlt
+rm Vhwe_cov_top__ALL.verilator_deplist.tmp
+make: Leaving directory 'testbench/FPGA-MAFIA_fpga_mafia_pr449/obj_dir'
+- V e r i l a t i o n   R e p o r t: Verilator 5.047 devel rev v5.046-293-ge82bd52fa (mod)
+- Verilator: Built from 0.032 MB sources in 2 modules, into 0.025 MB in 5 C++ files needing 0.000 MB
+- Verilator: Walltime 7.783 s (elab=0.000, cvt=0.002, bld=7.779); cpu 0.004 s on 1 threads; allocated 20.340 MB

testbench/FPGA-MAFIA_fpga_mafia_pr449/verilator_fixed.log

@@ -0,0 +1,2 @@
+PASS: FPGA-MAFIA_fpga_mafia_pr449 fixed override script and RF_NUM_MSB edits are present
+- testbench/FPGA-MAFIA_fpga_mafia_pr449/snapshot_scratch/tb_pr449_patch_state_fixed.sv:11: Verilog $finish

testbench/FPGA-MAFIA_fpga_mafia_pr449/verilator_fixed_build.log

@@ -0,0 +1,14 @@
+make: Entering directory 'testbench/FPGA-MAFIA_fpga_mafia_pr449/obj_dir'
+g++ -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -Os  -c -o _coverage_main.o testbench/FPGA-MAFIA_fpga_mafia_pr449/../_coverage_main.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated.o /opt/oss-cad-suite/share/verilator/include/verilated.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated_cov.o /opt/oss-cad-suite/share/verilator/include/verilated_cov.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated_timing.o /opt/oss-cad-suite/share/verilator/include/verilated_timing.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated_threads.o /opt/oss-cad-suite/share/verilator/include/verilated_threads.cpp
+python3 /opt/oss-cad-suite/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vhwe_cov_top.cpp Vhwe_cov_top___024root__0.cpp Vhwe_cov_top___024root__Slow.cpp Vhwe_cov_top___024root__0__Slow.cpp Vhwe_cov_top__Syms__Slow.cpp > Vhwe_cov_top__ALL.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o Vhwe_cov_top__ALL.o Vhwe_cov_top__ALL.cpp
+g++ -Wl,-O2 -Wl,--sort-common -Wl,--as-needed -Wl,-z,relro -Wl,-z,now -Wl,--disable-new-dtags -Wl,--gc-sections -Wl,--allow-shlib-undefined -Wl,-rpath,/home/user/miniforge3/lib -Wl,-rpath-link,/home/user/miniforge3/lib -L/home/user/miniforge3/lib    _coverage_main.o verilated.o verilated_cov.o verilated_timing.o verilated_threads.o Vhwe_cov_top__ALL.a    -pthread -lpthread -latomic   -o simv_vlt
+rm Vhwe_cov_top__ALL.verilator_deplist.tmp
+make: Leaving directory 'testbench/FPGA-MAFIA_fpga_mafia_pr449/obj_dir'
+- V e r i l a t i o n   R e p o r t: Verilator 5.047 devel rev v5.046-293-ge82bd52fa (mod)
+- Verilator: Built from 0.032 MB sources in 2 modules, into 0.025 MB in 5 C++ files needing 0.000 MB
+- Verilator: Walltime 7.800 s (elab=0.000, cvt=0.002, bld=7.796); cpu 0.004 s on 1 threads; allocated 20.340 MB

testbench/FPGA-MAFIA_fpga_mafia_pr449/verilator_fixed_coverage.info

@@ -0,0 +1,7 @@
+TN:verilator_coverage
+SF:testbench/FPGA-MAFIA_fpga_mafia_pr449/snapshot_scratch/tb_pr449_patch_state_fixed.sv
+DA:6,1
+DA:7,1
+BRF:0
+BRH:0
+end_of_record

testbench/FPGA-MAFIA_fpga_mafia_pr451/open_tool_p2p_fixed.log

@@ -0,0 +1,25 @@
+INFO: open-tool P2P fallback (fixed)
+INFO: native simulation P2P not applicable for this case
+
+### qsf_surelog:FPGA/SDRAM_RTL_Test/DE10_LITE_SDRAM_RTL_Test.qsf
+'surelog' '-sv' '-parse' '-nocomp' '-Itestbench/FPGA-MAFIA_fpga_mafia_pr451/snapshot_scratch' '-Itestbench/FPGA-MAFIA_fpga_mafia_pr451/snapshot_scratch/verif' '-Itestbench/FPGA-MAFIA_fpga_mafia_pr451/snapshot_scratch/verif/core_rrv/tb' 'testbench/FPGA-MAFIA_fpga_mafia_pr451/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/Sdram_Control.v' 'testbench/FPGA-MAFIA_fpga_mafia_pr451/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/sdr_data_path.v' 'testbench/FPGA-MAFIA_fpga_mafia_pr451/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/control_interface.v' 'testbench/FPGA-MAFIA_fpga_mafia_pr451/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/command.v' 'testbench/FPGA-MAFIA_fpga_mafia_pr451/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/RW_Test.v' '-odir' 'testbench/FPGA-MAFIA_fpga_mafia_pr451/open_tool_fixed_qsf'
+[INF:CM0023] Creating log file "testbench/FPGA-MAFIA_fpga_mafia_pr451/open_tool_fixed_qsf/slpp_all/surelog.log".
+
+[WRN:PA0205] testbench/FPGA-MAFIA_fpga_mafia_pr451/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/Sdram_Control.v:1:1: No timescale set for "Sdram_Control".
+
+[WRN:PA0205] testbench/FPGA-MAFIA_fpga_mafia_pr451/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/sdr_data_path.v:1:1: No timescale set for "sdr_data_path".
+
+[WRN:PA0205] testbench/FPGA-MAFIA_fpga_mafia_pr451/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/control_interface.v:1:1: No timescale set for "control_interface".
+
+[WRN:PA0205] testbench/FPGA-MAFIA_fpga_mafia_pr451/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/command.v:1:1: No timescale set for "command".
+
+[WRN:PA0205] testbench/FPGA-MAFIA_fpga_mafia_pr451/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/RW_Test.v:1:1: No timescale set for "RW_Test".
+
+[  FATAL] : 0
+[ SYNTAX] : 0
+[  ERROR] : 0
+[WARNING] : 5
+[   NOTE] : 0
+
+rc=0
+PASS: open-tool P2P fallback passed in fixed phase: qsf_surelog:FPGA/SDRAM_RTL_Test/DE10_LITE_SDRAM_RTL_Test.qsf

testbench/FPGA-MAFIA_fpga_mafia_pr451/repo_native_buggy.log

@@ -0,0 +1 @@
+PASS: repo native multi-file open-tool P2P passed in buggy phase

testbench/FPGA-MAFIA_fpga_mafia_pr451/verilator_fixed_build.log

@@ -0,0 +1,14 @@
+make: Entering directory 'testbench/FPGA-MAFIA_fpga_mafia_pr451/obj_dir'
+g++ -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -Os  -c -o _coverage_main.o testbench/FPGA-MAFIA_fpga_mafia_pr451/../_coverage_main.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated.o /opt/oss-cad-suite/share/verilator/include/verilated.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated_cov.o /opt/oss-cad-suite/share/verilator/include/verilated_cov.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated_timing.o /opt/oss-cad-suite/share/verilator/include/verilated_timing.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated_threads.o /opt/oss-cad-suite/share/verilator/include/verilated_threads.cpp
+python3 /opt/oss-cad-suite/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vhwe_cov_top.cpp Vhwe_cov_top___024root__0.cpp Vhwe_cov_top___024root__Slow.cpp Vhwe_cov_top___024root__0__Slow.cpp Vhwe_cov_top__Syms__Slow.cpp > Vhwe_cov_top__ALL.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o Vhwe_cov_top__ALL.o Vhwe_cov_top__ALL.cpp
+g++ -Wl,-O2 -Wl,--sort-common -Wl,--as-needed -Wl,-z,relro -Wl,-z,now -Wl,--disable-new-dtags -Wl,--gc-sections -Wl,--allow-shlib-undefined -Wl,-rpath,/home/user/miniforge3/lib -Wl,-rpath-link,/home/user/miniforge3/lib -L/home/user/miniforge3/lib    _coverage_main.o verilated.o verilated_cov.o verilated_timing.o verilated_threads.o Vhwe_cov_top__ALL.a    -pthread -lpthread -latomic   -o simv_vlt
+rm Vhwe_cov_top__ALL.verilator_deplist.tmp
+make: Leaving directory 'testbench/FPGA-MAFIA_fpga_mafia_pr451/obj_dir'
+- V e r i l a t i o n   R e p o r t: Verilator 5.047 devel rev v5.046-293-ge82bd52fa (mod)
+- Verilator: Built from 0.032 MB sources in 2 modules, into 0.025 MB in 5 C++ files needing 0.000 MB
+- Verilator: Walltime 7.830 s (elab=0.000, cvt=0.002, bld=7.825); cpu 0.004 s on 1 threads; allocated 20.336 MB

testbench/HiSA-Team_Simply-V_pr102/AUTO_GENERATED.md

@@ -0,0 +1,2 @@
+Auto-generated compile/lint fail-to-pass Verilator testbench.
+Targets are listed in targets.txt.

testbench/HiSA-Team_Simply-V_pr102/open_tool_p2p_buggy.log

@@ -0,0 +1,3 @@
+INFO: open-tool P2P fallback (buggy)
+INFO: native simulation P2P not applicable for this case
+PASS: open-tool P2P fallback not applicable: no open-tool check passed

testbench/HiSA-Team_Simply-V_pr102/open_tool_p2p_fixed.log

@@ -0,0 +1,3 @@
+INFO: open-tool P2P fallback (fixed)
+INFO: native simulation P2P not applicable for this case
+PASS: open-tool P2P fallback not applicable: no open-tool check passed

testbench/HiSA-Team_Simply-V_pr102/peripheral_bus_tb_support.sv

@@ -0,0 +1,452 @@
+module xpm_cdc_array_single #(
+    parameter int DEST_SYNC_FF = 4,
+    parameter int SRC_INPUT_REG = 1,
+    parameter int WIDTH = 1
+)(
+    output logic [WIDTH-1:0] dest_out,
+    input  logic             dest_clk,
+    input  logic             src_clk,
+    input  logic [WIDTH-1:0] src_in
+);
+    logic [WIDTH-1:0] src_q;
+    logic [WIDTH-1:0] sync_q [DEST_SYNC_FF-1:0];
+
+    always_ff @(posedge src_clk) begin
+        src_q <= src_in;
+    end
+
+    always_ff @(posedge dest_clk) begin
+        sync_q[0] <= SRC_INPUT_REG ? src_q : src_in;
+        for (int i = 1; i < DEST_SYNC_FF; i++) begin
+            sync_q[i] <= sync_q[i-1];
+        end
+    end
+
+    assign dest_out = sync_q[DEST_SYNC_FF-1];
+endmodule
+
+module xlnx_axi_clock_converter (
+    input logic s_axi_aclk,
+    input logic s_axi_aresetn,
+    input logic m_axi_aclk,
+    input logic m_axi_aresetn,
+    input logic [1:0] s_axi_awid,
+    input logic [31:0] s_axi_awaddr,
+    input logic [7:0] s_axi_awlen,
+    input logic [2:0] s_axi_awsize,
+    input logic [1:0] s_axi_awburst,
+    input logic s_axi_awlock,
+    input logic [3:0] s_axi_awcache,
+    input logic [2:0] s_axi_awprot,
+    input logic [3:0] s_axi_awqos,
+    input logic s_axi_awvalid,
+    output logic s_axi_awready,
+    input logic [3:0] s_axi_awregion,
+    input logic [31:0] s_axi_wdata,
+    input logic [3:0] s_axi_wstrb,
+    input logic s_axi_wlast,
+    input logic s_axi_wvalid,
+    output logic s_axi_wready,
+    output logic [1:0] s_axi_bid,
+    output logic [1:0] s_axi_bresp,
+    output logic s_axi_bvalid,
+    input logic s_axi_bready,
+    input logic [1:0] s_axi_arid,
+    input logic [31:0] s_axi_araddr,
+    input logic [7:0] s_axi_arlen,
+    input logic [2:0] s_axi_arsize,
+    input logic [1:0] s_axi_arburst,
+    input logic s_axi_arlock,
+    input logic [3:0] s_axi_arcache,
+    input logic [2:0] s_axi_arprot,
+    input logic [3:0] s_axi_arregion,
+    input logic [3:0] s_axi_arqos,
+    input logic s_axi_arvalid,
+    output logic s_axi_arready,
+    output logic [1:0] s_axi_rid,
+    output logic [31:0] s_axi_rdata,
+    output logic [1:0] s_axi_rresp,
+    output logic s_axi_rlast,
+    output logic s_axi_rvalid,
+    input logic s_axi_rready,
+    output logic [1:0] m_axi_awid,
+    output logic [31:0] m_axi_awaddr,
+    output logic [7:0] m_axi_awlen,
+    output logic [2:0] m_axi_awsize,
+    output logic [1:0] m_axi_awburst,
+    output logic m_axi_awlock,
+    output logic [3:0] m_axi_awcache,
+    output logic [2:0] m_axi_awprot,
+    output logic [3:0] m_axi_awregion,
+    output logic [3:0] m_axi_awqos,
+    output logic m_axi_awvalid,
+    input logic m_axi_awready,
+    output logic [31:0] m_axi_wdata,
+    output logic [3:0] m_axi_wstrb,
+    output logic m_axi_wlast,
+    output logic m_axi_wvalid,
+    input logic m_axi_wready,
+    input logic [1:0] m_axi_bid,
+    input logic [1:0] m_axi_bresp,
+    input logic m_axi_bvalid,
+    output logic m_axi_bready,
+    output logic [1:0] m_axi_arid,
+    output logic [31:0] m_axi_araddr,
+    output logic [7:0] m_axi_arlen,
+    output logic [2:0] m_axi_arsize,
+    output logic [1:0] m_axi_arburst,
+    output logic m_axi_arlock,
+    output logic [3:0] m_axi_arcache,
+    output logic [2:0] m_axi_arprot,
+    output logic [3:0] m_axi_arregion,
+    output logic [3:0] m_axi_arqos,
+    output logic m_axi_arvalid,
+    input logic m_axi_arready,
+    input logic [1:0] m_axi_rid,
+    input logic [31:0] m_axi_rdata,
+    input logic [1:0] m_axi_rresp,
+    input logic m_axi_rlast,
+    input logic m_axi_rvalid,
+    output logic m_axi_rready
+);
+    assign m_axi_awid = s_axi_awid;
+    assign m_axi_awaddr = s_axi_awaddr;
+    assign m_axi_awlen = s_axi_awlen;
+    assign m_axi_awsize = s_axi_awsize;
+    assign m_axi_awburst = s_axi_awburst;
+    assign m_axi_awlock = s_axi_awlock;
+    assign m_axi_awcache = s_axi_awcache;
+    assign m_axi_awprot = s_axi_awprot;
+    assign m_axi_awregion = s_axi_awregion;
+    assign m_axi_awqos = s_axi_awqos;
+    assign m_axi_awvalid = s_axi_awvalid;
+    assign s_axi_awready = m_axi_awready;
+    assign m_axi_wdata = s_axi_wdata;
+    assign m_axi_wstrb = s_axi_wstrb;
+    assign m_axi_wlast = s_axi_wlast;
+    assign m_axi_wvalid = s_axi_wvalid;
+    assign s_axi_wready = m_axi_wready;
+    assign s_axi_bid = m_axi_bid;
+    assign s_axi_bresp = m_axi_bresp;
+    assign s_axi_bvalid = m_axi_bvalid;
+    assign m_axi_bready = s_axi_bready;
+    assign m_axi_arid = s_axi_arid;
+    assign m_axi_araddr = s_axi_araddr;
+    assign m_axi_arlen = s_axi_arlen;
+    assign m_axi_arsize = s_axi_arsize;
+    assign m_axi_arburst = s_axi_arburst;
+    assign m_axi_arlock = s_axi_arlock;
+    assign m_axi_arcache = s_axi_arcache;
+    assign m_axi_arprot = s_axi_arprot;
+    assign m_axi_arregion = s_axi_arregion;
+    assign m_axi_arqos = s_axi_arqos;
+    assign m_axi_arvalid = s_axi_arvalid;
+    assign s_axi_arready = m_axi_arready;
+    assign s_axi_rid = m_axi_rid;
+    assign s_axi_rdata = m_axi_rdata;
+    assign s_axi_rresp = m_axi_rresp;
+    assign s_axi_rlast = m_axi_rlast;
+    assign s_axi_rvalid = m_axi_rvalid;
+    assign m_axi_rready = s_axi_rready;
+endmodule
+
+module xlnx_axi4_to_axilite_converter (
+    input logic aclk,
+    input logic aresetn,
+    input logic [1:0] s_axi_awid,
+    input logic [31:0] s_axi_awaddr,
+    input logic [7:0] s_axi_awlen,
+    input logic [2:0] s_axi_awsize,
+    input logic [1:0] s_axi_awburst,
+    input logic s_axi_awlock,
+    input logic [3:0] s_axi_awcache,
+    input logic [2:0] s_axi_awprot,
+    input logic [3:0] s_axi_awregion,
+    input logic [3:0] s_axi_awqos,
+    input logic s_axi_awvalid,
+    output logic s_axi_awready,
+    input logic [31:0] s_axi_wdata,
+    input logic [3:0] s_axi_wstrb,
+    input logic s_axi_wlast,
+    input logic s_axi_wvalid,
+    output logic s_axi_wready,
+    output logic [1:0] s_axi_bid,
+    output logic [1:0] s_axi_bresp,
+    output logic s_axi_bvalid,
+    input logic s_axi_bready,
+    input logic [1:0] s_axi_arid,
+    input logic [31:0] s_axi_araddr,
+    input logic [7:0] s_axi_arlen,
+    input logic [2:0] s_axi_arsize,
+    input logic [1:0] s_axi_arburst,
+    input logic s_axi_arlock,
+    input logic [3:0] s_axi_arcache,
+    input logic [2:0] s_axi_arprot,
+    input logic [3:0] s_axi_arregion,
+    input logic [3:0] s_axi_arqos,
+    input logic s_axi_arvalid,
+    output logic s_axi_arready,
+    output logic [1:0] s_axi_rid,
+    output logic [31:0] s_axi_rdata,
+    output logic [1:0] s_axi_rresp,
+    output logic s_axi_rlast,
+    output logic s_axi_rvalid,
+    input logic s_axi_rready,
+    output logic [31:0] m_axi_awaddr,
+    output logic [2:0] m_axi_awprot,
+    output logic m_axi_awvalid,
+    input logic m_axi_awready,
+    output logic [31:0] m_axi_wdata,
+    output logic [3:0] m_axi_wstrb,
+    output logic m_axi_wvalid,
+    input logic m_axi_wready,
+    input logic [1:0] m_axi_bresp,
+    input logic m_axi_bvalid,
+    output logic m_axi_bready,
+    output logic [31:0] m_axi_araddr,
+    output logic [2:0] m_axi_arprot,
+    output logic m_axi_arvalid,
+    input logic m_axi_arready,
+    input logic [31:0] m_axi_rdata,
+    input logic [1:0] m_axi_rresp,
+    input logic m_axi_rvalid,
+    output logic m_axi_rready
+);
+    assign m_axi_awaddr = s_axi_awaddr;
+    assign m_axi_awprot = s_axi_awprot;
+    assign m_axi_awvalid = s_axi_awvalid;
+    assign s_axi_awready = m_axi_awready;
+    assign m_axi_wdata = s_axi_wdata;
+    assign m_axi_wstrb = s_axi_wstrb;
+    assign m_axi_wvalid = s_axi_wvalid;
+    assign s_axi_wready = m_axi_wready;
+    assign s_axi_bid = s_axi_awid;
+    assign s_axi_bresp = m_axi_bresp;
+    assign s_axi_bvalid = m_axi_bvalid;
+    assign m_axi_bready = s_axi_bready;
+    assign m_axi_araddr = s_axi_araddr;
+    assign m_axi_arprot = s_axi_arprot;
+    assign m_axi_arvalid = s_axi_arvalid;
+    assign s_axi_arready = m_axi_arready;
+    assign s_axi_rid = s_axi_arid;
+    assign s_axi_rdata = m_axi_rdata;
+    assign s_axi_rresp = m_axi_rresp;
+    assign s_axi_rlast = 1'b1;
+    assign s_axi_rvalid = m_axi_rvalid;
+    assign m_axi_rready = s_axi_rready;
+endmodule
+
+module xlnx_peripheral_crossbar (
+    input logic aclk,
+    input logic aresetn,
+    input logic [31:0][0:0] s_axi_awaddr,
+    input logic [2:0][0:0] s_axi_awprot,
+    input logic [0:0][0:0] s_axi_awvalid,
+    output logic [0:0][0:0] s_axi_awready,
+    input logic [31:0][0:0] s_axi_wdata,
+    input logic [3:0][0:0] s_axi_wstrb,
+    input logic [0:0][0:0] s_axi_wvalid,
+    output logic [0:0][0:0] s_axi_wready,
+    output logic [1:0][0:0] s_axi_bresp,
+    output logic [0:0][0:0] s_axi_bvalid,
+    input logic [0:0][0:0] s_axi_bready,
+    input logic [31:0][0:0] s_axi_araddr,
+    input logic [2:0][0:0] s_axi_arprot,
+    input logic [0:0][0:0] s_axi_arvalid,
+    output logic [0:0][0:0] s_axi_arready,
+    output logic [31:0][0:0] s_axi_rdata,
+    output logic [1:0][0:0] s_axi_rresp,
+    output logic [0:0][0:0] s_axi_rvalid,
+    input logic [0:0][0:0] s_axi_rready,
+    output logic [31:0][4:0] m_axi_awaddr,
+    output logic [2:0][4:0] m_axi_awprot,
+    output logic [0:0][4:0] m_axi_awvalid,
+    input logic [0:0][4:0] m_axi_awready,
+    output logic [31:0][4:0] m_axi_wdata,
+    output logic [3:0][4:0] m_axi_wstrb,
+    output logic [0:0][4:0] m_axi_wvalid,
+    input logic [0:0][4:0] m_axi_wready,
+    input logic [1:0][4:0] m_axi_bresp,
+    input logic [0:0][4:0] m_axi_bvalid,
+    output logic [0:0][4:0] m_axi_bready,
+    output logic [31:0][4:0] m_axi_araddr,
+    output logic [2:0][4:0] m_axi_arprot,
+    output logic [0:0][4:0] m_axi_arvalid,
+    input logic [0:0][4:0] m_axi_arready,
+    input logic [31:0][4:0] m_axi_rdata,
+    input logic [1:0][4:0] m_axi_rresp,
+    input logic [0:0][4:0] m_axi_rvalid,
+    output logic [0:0][4:0] m_axi_rready
+);
+    always_comb begin
+        s_axi_awready = '1;
+        s_axi_wready = '1;
+        s_axi_bresp = '0;
+        s_axi_bvalid = '0;
+        s_axi_arready = '1;
+        s_axi_rdata = '0;
+        s_axi_rresp = '0;
+        s_axi_rvalid = '0;
+        m_axi_awaddr = '0;
+        m_axi_awprot = '0;
+        m_axi_awvalid = '0;
+        m_axi_wdata = '0;
+        m_axi_wstrb = '0;
+        m_axi_wvalid = '0;
+        m_axi_bready = '1;
+        m_axi_araddr = '0;
+        m_axi_arprot = '0;
+        m_axi_arvalid = '0;
+        m_axi_rready = '1;
+    end
+endmodule
+
+module axilite_uart (
+    input logic clock_i,
+    input logic reset_ni,
+    output logic int_core_o,
+    output logic int_xdma_o,
+    input logic int_ack_i,
+    output logic tx_o,
+    input logic rx_i,
+    input logic [31:0] s_axilite_awaddr,
+    input logic [2:0] s_axilite_awprot,
+    input logic s_axilite_awvalid,
+    output logic s_axilite_awready,
+    input logic [31:0] s_axilite_wdata,
+    input logic [3:0] s_axilite_wstrb,
+    input logic s_axilite_wvalid,
+    output logic s_axilite_wready,
+    output logic [1:0] s_axilite_bresp,
+    output logic s_axilite_bvalid,
+    input logic s_axilite_bready,
+    input logic [31:0] s_axilite_araddr,
+    input logic [2:0] s_axilite_arprot,
+    input logic s_axilite_arvalid,
+    output logic s_axilite_arready,
+    output logic [31:0] s_axilite_rdata,
+    output logic [1:0] s_axilite_rresp,
+    output logic s_axilite_rvalid,
+    input logic s_axilite_rready
+);
+    assign int_core_o = 1'b0;
+    assign int_xdma_o = 1'b0;
+    assign tx_o = 1'b1;
+    assign s_axilite_awready = 1'b1;
+    assign s_axilite_wready = 1'b1;
+    assign s_axilite_bresp = 2'b00;
+    assign s_axilite_bvalid = 1'b0;
+    assign s_axilite_arready = 1'b1;
+    assign s_axilite_rdata = '0;
+    assign s_axilite_rresp = 2'b00;
+    assign s_axilite_rvalid = 1'b0;
+endmodule
+
+module xlnx_axilite_timer (
+    input logic s_axi_aclk,
+    input logic s_axi_aresetn,
+    input logic [8:0] s_axi_awaddr,
+    input logic s_axi_awvalid,
+    output logic s_axi_awready,
+    input logic [31:0] s_axi_wdata,
+    input logic [3:0] s_axi_wstrb,
+    input logic s_axi_wvalid,
+    output logic s_axi_wready,
+    output logic [1:0] s_axi_bresp,
+    output logic s_axi_bvalid,
+    input logic s_axi_bready,
+    input logic [8:0] s_axi_araddr,
+    input logic s_axi_arvalid,
+    output logic s_axi_arready,
+    output logic [31:0] s_axi_rdata,
+    output logic [1:0] s_axi_rresp,
+    output logic s_axi_rvalid,
+    input logic s_axi_rready,
+    input logic capturetrig0,
+    input logic capturetrig1,
+    input logic freeze,
+    output logic generateout0,
+    output logic generateout1,
+    output logic interrupt,
+    output logic pwm0
+);
+    assign s_axi_awready = 1'b1;
+    assign s_axi_wready = 1'b1;
+    assign s_axi_bresp = 2'b00;
+    assign s_axi_bvalid = 1'b0;
+    assign s_axi_arready = 1'b1;
+    assign s_axi_rdata = '0;
+    assign s_axi_rresp = 2'b00;
+    assign s_axi_rvalid = 1'b0;
+    assign generateout0 = 1'b0;
+    assign generateout1 = 1'b0;
+    assign interrupt = 1'b0;
+    assign pwm0 = 1'b0;
+endmodule
+
+module xlnx_axi_gpio_out (
+    input logic s_axi_aclk,
+    input logic s_axi_aresetn,
+    input logic [8:0] s_axi_awaddr,
+    input logic s_axi_awvalid,
+    output logic s_axi_awready,
+    input logic [31:0] s_axi_wdata,
+    input logic [3:0] s_axi_wstrb,
+    input logic s_axi_wvalid,
+    output logic s_axi_wready,
+    output logic [1:0] s_axi_bresp,
+    output logic s_axi_bvalid,
+    input logic s_axi_bready,
+    input logic [8:0] s_axi_araddr,
+    input logic s_axi_arvalid,
+    output logic s_axi_arready,
+    output logic [31:0] s_axi_rdata,
+    output logic [1:0] s_axi_rresp,
+    output logic s_axi_rvalid,
+    input logic s_axi_rready,
+    output logic [15:0] gpio_io_o
+);
+    assign s_axi_awready = 1'b1;
+    assign s_axi_wready = 1'b1;
+    assign s_axi_bresp = 2'b00;
+    assign s_axi_bvalid = 1'b0;
+    assign s_axi_arready = 1'b1;
+    assign s_axi_rdata = '0;
+    assign s_axi_rresp = 2'b00;
+    assign s_axi_rvalid = 1'b0;
+    assign gpio_io_o = '0;
+endmodule
+
+module xlnx_axi_gpio_in (
+    input logic s_axi_aclk,
+    input logic s_axi_aresetn,
+    input logic [8:0] s_axi_awaddr,
+    input logic s_axi_awvalid,
+    output logic s_axi_awready,
+    input logic [31:0] s_axi_wdata,
+    input logic [3:0] s_axi_wstrb,
+    input logic s_axi_wvalid,
+    output logic s_axi_wready,
+    output logic [1:0] s_axi_bresp,
+    output logic s_axi_bvalid,
+    input logic s_axi_bready,
+    input logic [8:0] s_axi_araddr,
+    input logic s_axi_arvalid,
+    output logic s_axi_arready,
+    output logic [31:0] s_axi_rdata,
+    output logic [1:0] s_axi_rresp,
+    output logic s_axi_rvalid,
+    input logic s_axi_rready,
+    input logic [15:0] gpio_io_i,
+    output logic ip2intc_irpt
+);
+    assign s_axi_awready = 1'b1;
+    assign s_axi_wready = 1'b1;
+    assign s_axi_bresp = 2'b00;
+    assign s_axi_bvalid = 1'b0;
+    assign s_axi_arready = 1'b1;
+    assign s_axi_rdata = '0;
+    assign s_axi_rresp = 2'b00;
+    assign s_axi_rvalid = 1'b0;
+    assign ip2intc_irpt = |gpio_io_i;
+endmodule

testbench/HiSA-Team_Simply-V_pr102/repo_native_buggy.log

@@ -0,0 +1 @@
+PASS: repo native P2P smoke not applicable in buggy phase: no multi-file open-tool check passed

testbench/HiSA-Team_Simply-V_pr102/repo_native_fixed.log

@@ -0,0 +1 @@
+PASS: repo native P2P smoke not applicable in fixed phase: no multi-file open-tool check passed

testbench/HiSA-Team_Simply-V_pr102/run_once.sh

@@ -0,0 +1,4 @@
+#!/bin/bash
+set -u
+HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)"
+exec python3 "$HERE/../_run_once_from_run_verilator.py" "$HERE/run_verilator.sh"

testbench/HiSA-Team_Simply-V_pr102/run_verilator.sh

@@ -0,0 +1,24 @@
+#!/bin/bash
+set -u
+HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)"
+cd "$HERE"
+. "$HERE/../_repo_native_p2p_smoke.sh"
+NAME=HiSA-Team_Simply-V_pr102
+TOP=tb_pbus_interrupt_cdc
+RTL_DIR="$HERE/snapshot_scratch/hw/xilinx/rtl"
+# Target evidence for the patch-scoped compiler/lint run:
+# hw/xilinx/rtl/peripheral_bus.sv
+SOURCES=(
+  "+incdir+$RTL_DIR"
+  "-DNUM_SI=1"
+  "-DNUM_MI=1"
+  "-DPBUS_NUM_MI=5"
+  "-DCORE_SELECTOR=CORE_CV32E40P"
+  "-DPBUS_HAS_CLOCK_DOMAIN"
+  "-DEMBEDDED"
+  "$HERE/peripheral_bus_tb_support.sv"
+  "$RTL_DIR/uninasoc_pkg.sv"
+  "$RTL_DIR/peripheral_bus.sv"
+  "$HERE/tb_pbus_interrupt_cdc.sv"
+)
+. "$HERE/../_rtl_bug_run_common.sh"

testbench/HiSA-Team_Simply-V_pr102/targets.txt

@@ -0,0 +1 @@
+hw/xilinx/rtl/peripheral_bus.sv

testbench/HiSA-Team_Simply-V_pr102/tb_pbus_interrupt_cdc.sv

@@ -0,0 +1,150 @@
+`include "uninasoc_axi.svh"
+
+module tb_pbus_interrupt_cdc;
+    import uninasoc_pkg::*;
+
+    logic main_clk;
+    logic main_rst_n;
+    logic pbus_clk;
+    logic pbus_rst_n;
+    logic uart_rx;
+    logic uart_tx;
+    logic [NUM_GPIO_IN-1:0] gpio_in;
+    logic [NUM_GPIO_OUT-1:0] gpio_out;
+    logic [3:0] int_out;
+    int errors;
+
+    `DECLARE_AXI_BUS(s, AXI_DATA_WIDTH)
+
+    peripheral_bus #(.NUM_IRQ(4)) dut (
+        .main_clock_i(main_clk),
+        .main_reset_ni(main_rst_n),
+        .PBUS_clock_i(pbus_clk),
+        .PBUS_reset_ni(pbus_rst_n),
+        .s_axi_awid(s_axi_awid),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awlen(s_axi_awlen),
+        .s_axi_awsize(s_axi_awsize),
+        .s_axi_awburst(s_axi_awburst),
+        .s_axi_awlock(s_axi_awlock),
+        .s_axi_awcache(s_axi_awcache),
+        .s_axi_awprot(s_axi_awprot),
+        .s_axi_awqos(s_axi_awqos),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_awready(s_axi_awready),
+        .s_axi_awregion(s_axi_awregion),
+        .s_axi_wdata(s_axi_wdata),
+        .s_axi_wstrb(s_axi_wstrb),
+        .s_axi_wlast(s_axi_wlast),
+        .s_axi_wvalid(s_axi_wvalid),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_bid(s_axi_bid),
+        .s_axi_bresp(s_axi_bresp),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_arid(s_axi_arid),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_arlen(s_axi_arlen),
+        .s_axi_arsize(s_axi_arsize),
+        .s_axi_arburst(s_axi_arburst),
+        .s_axi_arlock(s_axi_arlock),
+        .s_axi_arregion(s_axi_arregion),
+        .s_axi_arcache(s_axi_arcache),
+        .s_axi_arprot(s_axi_arprot),
+        .s_axi_arqos(s_axi_arqos),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_rid(s_axi_rid),
+        .s_axi_rdata(s_axi_rdata),
+        .s_axi_rresp(s_axi_rresp),
+        .s_axi_rlast(s_axi_rlast),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_rready(s_axi_rready),
+        .uart_rx_i(uart_rx),
+        .uart_tx_o(uart_tx),
+        .gpio_in_i(gpio_in),
+        .gpio_out_o(gpio_out),
+        .int_o(int_out)
+    );
+
+    initial main_clk = 1'b0;
+    always #5 main_clk = ~main_clk;
+
+    initial pbus_clk = 1'b0;
+    always #3 pbus_clk = ~pbus_clk;
+
+    task automatic check_case(input int id, input bit ok, input string msg);
+        if (ok) $display("PASS: CASE %0d: %s", id, msg);
+        else begin
+            $display("FAIL: CASE %0d: %s", id, msg);
+            errors++;
+        end
+    endtask
+
+    initial begin
+        errors = 0;
+        main_rst_n = 1'b0;
+        pbus_rst_n = 1'b0;
+        uart_rx = 1'b1;
+        gpio_in = '0;
+        s_axi_awid = '0;
+        s_axi_awaddr = '0;
+        s_axi_awlen = '0;
+        s_axi_awsize = '0;
+        s_axi_awburst = '0;
+        s_axi_awlock = '0;
+        s_axi_awcache = '0;
+        s_axi_awprot = '0;
+        s_axi_awqos = '0;
+        s_axi_awvalid = '0;
+        s_axi_awregion = '0;
+        s_axi_wdata = '0;
+        s_axi_wstrb = '0;
+        s_axi_wlast = '0;
+        s_axi_wvalid = '0;
+        s_axi_bready = '0;
+        s_axi_arid = '0;
+        s_axi_araddr = '0;
+        s_axi_arlen = '0;
+        s_axi_arsize = '0;
+        s_axi_arburst = '0;
+        s_axi_arlock = '0;
+        s_axi_arregion = '0;
+        s_axi_arcache = '0;
+        s_axi_arprot = '0;
+        s_axi_arqos = '0;
+        s_axi_arvalid = '0;
+        s_axi_rready = '0;
+
+        repeat (2) @(posedge main_clk);
+        main_rst_n = 1'b1;
+        pbus_rst_n = 1'b1;
+        repeat (8) @(posedge main_clk);
+        #1;
+        check_case(1, int_out[PBUS_GPIOIN_INTERRUPT] == 1'b0,
+                   "GPIO interrupt is clear before the PBUS source toggles");
+
+        gpio_in[0] = 1'b1;
+        #1;
+        check_case(2, int_out[PBUS_GPIOIN_INTERRUPT] == 1'b0,
+                   "PBUS GPIO interrupt does not cross to main clock asynchronously");
+
+        repeat (8) @(posedge main_clk);
+        #1;
+        check_case(3, int_out[PBUS_GPIOIN_INTERRUPT] == 1'b1,
+                   "GPIO interrupt reaches main clock after CDC synchronization");
+
+        gpio_in[0] = 1'b0;
+        #1;
+        check_case(4, int_out[PBUS_GPIOIN_INTERRUPT] == 1'b1,
+                   "synchronized GPIO interrupt does not clear asynchronously");
+
+        repeat (8) @(posedge main_clk);
+        #1;
+        check_case(5, int_out[PBUS_GPIOIN_INTERRUPT] == 1'b0,
+                   "GPIO interrupt clears after CDC synchronization");
+
+        if (errors) $fatal(1, "FAIL: pbus interrupt CDC exposed %0d unsynchronized changes", errors);
+        $finish;
+    end
+endmodule

testbench/HiSA-Team_Simply-V_pr102/verilator_buggy.log

@@ -0,0 +1,8 @@
+PASS: CASE 1: GPIO interrupt is clear before the PBUS source toggles
+FAIL: CASE 2: PBUS GPIO interrupt does not cross to main clock asynchronously
+PASS: CASE 3: GPIO interrupt reaches main clock after CDC synchronization
+FAIL: CASE 4: synchronized GPIO interrupt does not clear asynchronously
+PASS: CASE 5: GPIO interrupt clears after CDC synchronization
+[256000] %Fatal: tb_pbus_interrupt_cdc.sv:147: Assertion failed in tb_pbus_interrupt_cdc: FAIL: pbus interrupt CDC exposed 2 unsynchronized changes
+%Error: testbench/HiSA-Team_Simply-V_pr102/tb_pbus_interrupt_cdc.sv:147: Verilog $stop
+Aborting...

testbench/HiSA-Team_Simply-V_pr102/verilator_buggy_build.log

@@ -0,0 +1,12 @@
+make: Entering directory 'testbench/HiSA-Team_Simply-V_pr102/obj_dir'
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -DVL_TIME_CONTEXT   -fcoroutines -c -o verilated.o /opt/oss-cad-suite/share/verilator/include/verilated.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -DVL_TIME_CONTEXT   -fcoroutines -c -o verilated_timing.o /opt/oss-cad-suite/share/verilator/include/verilated_timing.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -DVL_TIME_CONTEXT   -fcoroutines -c -o verilated_threads.o /opt/oss-cad-suite/share/verilator/include/verilated_threads.cpp
+python3 /opt/oss-cad-suite/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vtb_pbus_interrupt_cdc.cpp Vtb_pbus_interrupt_cdc___024root__0.cpp Vtb_pbus_interrupt_cdc__main.cpp Vtb_pbus_interrupt_cdc___024root__Slow.cpp Vtb_pbus_interrupt_cdc___024root__0__Slow.cpp Vtb_pbus_interrupt_cdc___024unit__Slow.cpp Vtb_pbus_interrupt_cdc__Syms__Slow.cpp > Vtb_pbus_interrupt_cdc__ALL.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -DVL_TIME_CONTEXT   -fcoroutines -c -o Vtb_pbus_interrupt_cdc__ALL.o Vtb_pbus_interrupt_cdc__ALL.cpp
+g++ -Wl,-O2 -Wl,--sort-common -Wl,--as-needed -Wl,-z,relro -Wl,-z,now -Wl,--disable-new-dtags -Wl,--gc-sections -Wl,--allow-shlib-undefined -Wl,-rpath,/home/user/miniforge3/lib -Wl,-rpath-link,/home/user/miniforge3/lib -L/home/user/miniforge3/lib    verilated.o verilated_timing.o verilated_threads.o Vtb_pbus_interrupt_cdc__ALL.a    -pthread -lpthread -latomic   -o simv_vlt
+rm Vtb_pbus_interrupt_cdc__ALL.verilator_deplist.tmp
+make: Leaving directory 'testbench/HiSA-Team_Simply-V_pr102/obj_dir'
+- V e r i l a t i o n   R e p o r t: Verilator 5.047 devel rev v5.046-293-ge82bd52fa (mod)
+- Verilator: Built from 0.356 MB sources in 13 modules, into 0.051 MB in 7 C++ files needing 0.000 MB
+- Verilator: Walltime 6.185 s (elab=0.004, cvt=0.010, bld=6.158); cpu 0.027 s on 1 threads; allocated 23.641 MB

testbench/HiSA-Team_Simply-V_pr102/verilator_fixed.log

@@ -0,0 +1,6 @@
+PASS: CASE 1: GPIO interrupt is clear before the PBUS source toggles
+PASS: CASE 2: PBUS GPIO interrupt does not cross to main clock asynchronously
+PASS: CASE 3: GPIO interrupt reaches main clock after CDC synchronization
+PASS: CASE 4: synchronized GPIO interrupt does not clear asynchronously
+PASS: CASE 5: GPIO interrupt clears after CDC synchronization
+- testbench/HiSA-Team_Simply-V_pr102/tb_pbus_interrupt_cdc.sv:148: Verilog $finish

testbench/HiSA-Team_Simply-V_pr102/verilator_fixed_build.log

@@ -0,0 +1,14 @@
+make: Entering directory 'testbench/HiSA-Team_Simply-V_pr102/obj_dir'
+g++ -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -Os  -c -o _coverage_main.o testbench/HiSA-Team_Simply-V_pr102/../_coverage_main.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated.o /opt/oss-cad-suite/share/verilator/include/verilated.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated_cov.o /opt/oss-cad-suite/share/verilator/include/verilated_cov.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated_timing.o /opt/oss-cad-suite/share/verilator/include/verilated_timing.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated_threads.o /opt/oss-cad-suite/share/verilator/include/verilated_threads.cpp
+python3 /opt/oss-cad-suite/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vhwe_cov_top.cpp Vhwe_cov_top___024root__0.cpp Vhwe_cov_top___024root__Slow.cpp Vhwe_cov_top___024root__0__Slow.cpp Vhwe_cov_top___024unit__Slow.cpp Vhwe_cov_top___024unit__0__Slow.cpp Vhwe_cov_top__Syms__Slow.cpp > Vhwe_cov_top__ALL.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o Vhwe_cov_top__ALL.o Vhwe_cov_top__ALL.cpp
+g++ -Wl,-O2 -Wl,--sort-common -Wl,--as-needed -Wl,-z,relro -Wl,-z,now -Wl,--disable-new-dtags -Wl,--gc-sections -Wl,--allow-shlib-undefined -Wl,-rpath,/home/user/miniforge3/lib -Wl,-rpath-link,/home/user/miniforge3/lib -L/home/user/miniforge3/lib    _coverage_main.o verilated.o verilated_cov.o verilated_timing.o verilated_threads.o Vhwe_cov_top__ALL.a    -pthread -lpthread -latomic   -o simv_vlt
+rm Vhwe_cov_top__ALL.verilator_deplist.tmp
+make: Leaving directory 'testbench/HiSA-Team_Simply-V_pr102/obj_dir'
+- V e r i l a t i o n   R e p o r t: Verilator 5.047 devel rev v5.046-293-ge82bd52fa (mod)
+- Verilator: Built from 0.359 MB sources in 13 modules, into 0.654 MB in 7 C++ files needing 0.000 MB
+- Verilator: Walltime 9.233 s (elab=0.004, cvt=0.037, bld=9.174); cpu 0.060 s on 1 threads; allocated 26.887 MB

testbench/Lampro-Mellon_LM-RISCV-DV_pr81/open_tool_p2p_buggy.log

@@ -0,0 +1,211 @@
+INFO: open-tool P2P fallback (buggy)
+INFO: native simulation P2P not applicable for this case
+
+### filelist_surelog:integration_files/SweRV_EH1/SweRV_EH1_flist.f
+'surelog' '-sv' '-parse' '-nocomp' '-Itestbench/Lampro-Mellon_LM-RISCV-DV_pr81/snapshot_scratch' '-f' 'testbench/Lampro-Mellon_LM-RISCV-DV_pr81/snapshot_scratch/integration_files/SweRV_EH1/SweRV_EH1_flist.f' '-odir' 'testbench/Lampro-Mellon_LM-RISCV-DV_pr81/open_tool_buggy_fl'
+[INF:CM0023] Creating log file "testbench/Lampro-Mellon_LM-RISCV-DV_pr81/open_tool_buggy_fl/slpp_all/surelog.log".
+
+[FTL:CM0008] Verilog File "/snapshots/default/common_defines.vh" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/include/swerv_types.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/swerv_wrapper.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/mem.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/pic_ctrl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/swerv.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/dma_ctrl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/ifu/ifu_aln_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/ifu/ifu_compress_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/ifu/ifu_ifc_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/ifu/ifu_bp_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/ifu/ifu_ic_mem.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/ifu/ifu_mem_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/ifu/ifu_iccm_mem.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/ifu/ifu.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/dec/dec_decode_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/dec/dec_gpr_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/dec/dec_ib_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/dec/dec_tlu_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/dec/dec_trigger.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/dec/dec.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/exu/exu_alu_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/exu/exu_mul_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/exu/exu_div_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/exu/exu.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/lsu/lsu.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/lsu/lsu_clkdomain.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/lsu/lsu_addrcheck.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/lsu/lsu_lsc_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/lsu/lsu_stbuf.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/lsu/lsu_bus_buffer.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/lsu/lsu_bus_intf.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/lsu/lsu_ecc.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/lsu/lsu_dccm_mem.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/lsu/lsu_dccm_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/lsu/lsu_trigger.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/dbg/dbg.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/dmi/dmi_wrapper.v" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/dmi/dmi_jtag_to_core_sync.v" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/dmi/rvjtag_tap.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/testbench/pkg.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/testbench/tracer_pkg.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/testbench/tracer.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/testbench/ahb_sif.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/testbench/tb_top.sv" does not exist.
+
+[FTL:CM0006] Library file "/rtl/lib/beh_lib.sv" does not exist.
+
+[FTL:CM0006] Library file "/rtl/lib/mem_lib.sv" does not exist.
+
+[FTL:CM0006] Library file "/rtl/lib/ahb_to_axi4.sv" does not exist.
+
+[FTL:CM0006] Library file "/rtl/lib/axi4_to_ahb.sv" does not exist.
+
+[WRN:CM0005] Include path "/rtl/lib" does not exist.
+
+[WRN:CM0005] Include path "/rtl/include" does not exist.
+
+[WRN:CM0005] Include path "/snapshots/default" does not exist.
+
+[WRN:CM0005] Include path "/rtl" does not exist.
+
+[WRN:CM0005] Include path "/rtl/ifu" does not exist.
+
+[WRN:CM0005] Include path "/rtl/dec" does not exist.
+
+[WRN:CM0005] Include path "/rtl/exu" does not exist.
+
+[WRN:CM0005] Include path "/rtl/lsu" does not exist.
+
+[WRN:CM0005] Include path "/rtl/dbg" does not exist.
+
+[WRN:CM0005] Include path "/rtl/dmi" does not exist.
+
+[WRN:CM0005] Include path "/testbench" does not exist.
+
+[  FATAL] : 49
+[ SYNTAX] : 0
+[  ERROR] : 0
+[WARNING] : 11
+[   NOTE] : 0
+
+rc=1
+
+### filelist_verilator:integration_files/SweRV_EH1/SweRV_EH1_flist.f
+'verilator' '--lint-only' '--sv' '--Wno-fatal' '--Wno-DECLFILENAME' '--Wno-MULTITOP' '--Wno-UNUSEDSIGNAL' '--Wno-UNUSEDPARAM' '--Wno-WIDTH' '-Itestbench/Lampro-Mellon_LM-RISCV-DV_pr81/snapshot_scratch' '-f' 'testbench/Lampro-Mellon_LM-RISCV-DV_pr81/snapshot_scratch/integration_files/SweRV_EH1/SweRV_EH1_flist.f'
+%Error: Cannot find file containing module: '{PRJ_DIR}/snapshots/default/common_defines.vh'
+        ... See the manual at https://verilator.org/verilator_doc.html?v=5.047 for more assistance.
+        ... Looked in:
+             testbench/Lampro-Mellon_LM-RISCV-DV_pr81/snapshot_scratch/{PRJ_DIR}/snapshots/default/common_defines.vh
+             testbench/Lampro-Mellon_LM-RISCV-DV_pr81/snapshot_scratch/{PRJ_DIR}/snapshots/default/common_defines.vh.v
+             testbench/Lampro-Mellon_LM-RISCV-DV_pr81/snapshot_scratch/{PRJ_DIR}/snapshots/default/common_defines.vh.sv
+             {PRJ_DIR}/rtl/lib/{PRJ_DIR}/snapshots/default/common_defines.vh
+             {PRJ_DIR}/rtl/lib/{PRJ_DIR}/snapshots/default/common_defines.vh.v
+             {PRJ_DIR}/rtl/lib/{PRJ_DIR}/snapshots/default/common_defines.vh.sv
+             {PRJ_DIR}/rtl/include/{PRJ_DIR}/snapshots/default/common_defines.vh
+             {PRJ_DIR}/rtl/include/{PRJ_DIR}/snapshots/default/common_defines.vh.v
+             {PRJ_DIR}/rtl/include/{PRJ_DIR}/snapshots/default/common_defines.vh.sv
+             {PRJ_DIR}/snapshots/default/{PRJ_DIR}/snapshots/default/common_defines.vh
+             {PRJ_DIR}/snapshots/default/{PRJ_DIR}/snapshots/default/common_defines.vh.v
+             {PRJ_DIR}/snapshots/default/{PRJ_DIR}/snapshots/default/common_defines.vh.sv
+             {PRJ_DIR}/snapshots/default/common_defines.vh
+             {PRJ_DIR}/snapshots/default/common_defines.vh.v
+             {PRJ_DIR}/snapshots/default/common_defines.vh.sv
+             obj_dir/{PRJ_DIR}/snapshots/default/common_defines.vh
+             obj_dir/{PRJ_DIR}/snapshots/default/common_defines.vh.v
+             obj_dir/{PRJ_DIR}/snapshots/default/common_defines.vh.sv
+        ... With current working directory 'testbench/Lampro-Mellon_LM-RISCV-DV_pr81/snapshot_scratch'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/include/swerv_types.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/swerv_wrapper.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/mem.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/pic_ctrl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/swerv.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/dma_ctrl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/ifu/ifu_aln_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/ifu/ifu_compress_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/ifu/ifu_ifc_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/ifu/ifu_bp_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/ifu/ifu_ic_mem.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/ifu/ifu_mem_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/ifu/ifu_iccm_mem.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/ifu/ifu.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/dec/dec_decode_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/dec/dec_gpr_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/dec/dec_ib_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/dec/dec_tlu_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/dec/dec_trigger.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/dec/dec.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/exu/exu_alu_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/exu/exu_mul_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/exu/exu_div_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/exu/exu.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/lsu/lsu.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/lsu/lsu_clkdomain.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/lsu/lsu_addrcheck.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/lsu/lsu_lsc_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/lsu/lsu_stbuf.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/lsu/lsu_bus_buffer.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/lsu/lsu_bus_intf.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/lsu/lsu_ecc.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/lsu/lsu_dccm_mem.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/lsu/lsu_dccm_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/lsu/lsu_trigger.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/dbg/dbg.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/dmi/dmi_wrapper.v'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/dmi/dmi_jtag_to_core_sync.v'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/dmi/rvjtag_tap.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/testbench/pkg.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/testbench/tracer_pkg.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/testbench/tracer.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/testbench/ahb_sif.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/testbench/tb_top.sv'
+%Error: Cannot find file containing library module: '{PRJ_DIR}/rtl/lib/ahb_to_axi4.sv'
+%Error: Cannot find file containing library module: '{PRJ_DIR}/rtl/lib/axi4_to_ahb.sv'
+%Error: Cannot find file containing library module: '{PRJ_DIR}/rtl/lib/beh_lib.sv'
+%Error: Cannot find file containing library module: '{PRJ_DIR}/rtl/lib/mem_lib.sv'
+%Error: Exiting due to 49 error(s)
+
+rc=1
+PASS: open-tool P2P fallback not applicable: no open-tool check passed

testbench/Lampro-Mellon_LM-RISCV-DV_pr81/open_tool_p2p_fixed.log

@@ -0,0 +1,466 @@
+INFO: open-tool P2P fallback (fixed)
+INFO: native simulation P2P not applicable for this case
+
+### filelist_surelog:integration_files/SweRV_EH1/flist_verilator.f
+'surelog' '-sv' '-parse' '-nocomp' '-Itestbench/Lampro-Mellon_LM-RISCV-DV_pr81/snapshot_scratch' '-f' 'testbench/Lampro-Mellon_LM-RISCV-DV_pr81/snapshot_scratch/integration_files/SweRV_EH1/flist_verilator.f' '-odir' 'testbench/Lampro-Mellon_LM-RISCV-DV_pr81/open_tool_fixed_fl'
+[INF:CM0023] Creating log file "testbench/Lampro-Mellon_LM-RISCV-DV_pr81/open_tool_fixed_fl/slpp_all/surelog.log".
+
+[FTL:CM0008] Verilog File "/snapshots/default/common_defines_verilator.vh" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/include/swerv_types.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/swerv_wrapper.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/mem.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/pic_ctrl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/swerv.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/dma_ctrl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/ifu/ifu_aln_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/ifu/ifu_compress_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/ifu/ifu_ifc_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/ifu/ifu_bp_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/ifu/ifu_ic_mem.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/ifu/ifu_mem_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/ifu/ifu_iccm_mem.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/ifu/ifu.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/dec/dec_decode_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/dec/dec_gpr_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/dec/dec_ib_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/dec/dec_tlu_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/dec/dec_trigger.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/dec/dec.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/exu/exu_alu_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/exu/exu_mul_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/exu/exu_div_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/exu/exu.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/lsu/lsu.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/lsu/lsu_clkdomain.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/lsu/lsu_addrcheck.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/lsu/lsu_lsc_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/lsu/lsu_stbuf.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/lsu/lsu_bus_buffer.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/lsu/lsu_bus_intf.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/lsu/lsu_ecc.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/lsu/lsu_dccm_mem.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/lsu/lsu_dccm_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/lsu/lsu_trigger.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/dbg/dbg.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/dmi/dmi_wrapper.v" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/dmi/dmi_jtag_to_core_sync.v" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/dmi/rvjtag_tap.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/lib/beh_lib.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/lib/mem_lib.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/lib/ahb_to_axi4.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/lib/axi4_to_ahb.sv" does not exist.
+
+[WRN:CM0005] Include path "/rtl/lib" does not exist.
+
+[WRN:CM0005] Include path "/rtl/include" does not exist.
+
+[WRN:CM0005] Include path "/snapshots/default" does not exist.
+
+[WRN:CM0005] Include path "/rtl" does not exist.
+
+[WRN:CM0005] Include path "/rtl/ifu" does not exist.
+
+[WRN:CM0005] Include path "/rtl/dec" does not exist.
+
+[WRN:CM0005] Include path "/rtl/exu" does not exist.
+
+[WRN:CM0005] Include path "/rtl/lsu" does not exist.
+
+[WRN:CM0005] Include path "/rtl/dbg" does not exist.
+
+[WRN:CM0005] Include path "/rtl/dmi" does not exist.
+
+[  FATAL] : 44
+[ SYNTAX] : 0
+[  ERROR] : 0
+[WARNING] : 10
+[   NOTE] : 0
+
+rc=1
+
+### filelist_verilator:integration_files/SweRV_EH1/flist_verilator.f
+'verilator' '--lint-only' '--sv' '--Wno-fatal' '--Wno-DECLFILENAME' '--Wno-MULTITOP' '--Wno-UNUSEDSIGNAL' '--Wno-UNUSEDPARAM' '--Wno-WIDTH' '-Itestbench/Lampro-Mellon_LM-RISCV-DV_pr81/snapshot_scratch' '-f' 'testbench/Lampro-Mellon_LM-RISCV-DV_pr81/snapshot_scratch/integration_files/SweRV_EH1/flist_verilator.f'
+%Error: Cannot find file containing module: '{PRJ_DIR}/snapshots/default/common_defines_verilator.vh'
+        ... See the manual at https://verilator.org/verilator_doc.html?v=5.047 for more assistance.
+        ... Looked in:
+             testbench/Lampro-Mellon_LM-RISCV-DV_pr81/snapshot_scratch/{PRJ_DIR}/snapshots/default/common_defines_verilator.vh
+             testbench/Lampro-Mellon_LM-RISCV-DV_pr81/snapshot_scratch/{PRJ_DIR}/snapshots/default/common_defines_verilator.vh.v
+             testbench/Lampro-Mellon_LM-RISCV-DV_pr81/snapshot_scratch/{PRJ_DIR}/snapshots/default/common_defines_verilator.vh.sv
+             {PRJ_DIR}/rtl/lib/{PRJ_DIR}/snapshots/default/common_defines_verilator.vh
+             {PRJ_DIR}/rtl/lib/{PRJ_DIR}/snapshots/default/common_defines_verilator.vh.v
+             {PRJ_DIR}/rtl/lib/{PRJ_DIR}/snapshots/default/common_defines_verilator.vh.sv
+             {PRJ_DIR}/rtl/include/{PRJ_DIR}/snapshots/default/common_defines_verilator.vh
+             {PRJ_DIR}/rtl/include/{PRJ_DIR}/snapshots/default/common_defines_verilator.vh.v
+             {PRJ_DIR}/rtl/include/{PRJ_DIR}/snapshots/default/common_defines_verilator.vh.sv
+             {PRJ_DIR}/snapshots/default/{PRJ_DIR}/snapshots/default/common_defines_verilator.vh
+             {PRJ_DIR}/snapshots/default/{PRJ_DIR}/snapshots/default/common_defines_verilator.vh.v
+             {PRJ_DIR}/snapshots/default/{PRJ_DIR}/snapshots/default/common_defines_verilator.vh.sv
+             {PRJ_DIR}/snapshots/default/common_defines_verilator.vh
+             {PRJ_DIR}/snapshots/default/common_defines_verilator.vh.v
+             {PRJ_DIR}/snapshots/default/common_defines_verilator.vh.sv
+             obj_dir/{PRJ_DIR}/snapshots/default/common_defines_verilator.vh
+             obj_dir/{PRJ_DIR}/snapshots/default/common_defines_verilator.vh.v
+             obj_dir/{PRJ_DIR}/snapshots/default/common_defines_verilator.vh.sv
+        ... With current working directory 'testbench/Lampro-Mellon_LM-RISCV-DV_pr81/snapshot_scratch'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/include/swerv_types.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/swerv_wrapper.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/mem.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/pic_ctrl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/swerv.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/dma_ctrl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/ifu/ifu_aln_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/ifu/ifu_compress_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/ifu/ifu_ifc_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/ifu/ifu_bp_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/ifu/ifu_ic_mem.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/ifu/ifu_mem_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/ifu/ifu_iccm_mem.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/ifu/ifu.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/dec/dec_decode_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/dec/dec_gpr_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/dec/dec_ib_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/dec/dec_tlu_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/dec/dec_trigger.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/dec/dec.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/exu/exu_alu_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/exu/exu_mul_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/exu/exu_div_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/exu/exu.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/lsu/lsu.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/lsu/lsu_clkdomain.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/lsu/lsu_addrcheck.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/lsu/lsu_lsc_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/lsu/lsu_stbuf.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/lsu/lsu_bus_buffer.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/lsu/lsu_bus_intf.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/lsu/lsu_ecc.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/lsu/lsu_dccm_mem.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/lsu/lsu_dccm_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/lsu/lsu_trigger.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/dbg/dbg.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/dmi/dmi_wrapper.v'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/dmi/dmi_jtag_to_core_sync.v'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/dmi/rvjtag_tap.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/lib/beh_lib.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/lib/mem_lib.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/lib/ahb_to_axi4.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/lib/axi4_to_ahb.sv'
+%Error: Exiting due to 44 error(s)
+
+rc=1
+
+### filelist_surelog:integration_files/SweRV_EH1/SweRV_EH1_flist.f
+'surelog' '-sv' '-parse' '-nocomp' '-Itestbench/Lampro-Mellon_LM-RISCV-DV_pr81/snapshot_scratch' '-f' 'testbench/Lampro-Mellon_LM-RISCV-DV_pr81/snapshot_scratch/integration_files/SweRV_EH1/SweRV_EH1_flist.f' '-odir' 'testbench/Lampro-Mellon_LM-RISCV-DV_pr81/open_tool_fixed_fl'
+[INF:CM0023] Creating log file "testbench/Lampro-Mellon_LM-RISCV-DV_pr81/open_tool_fixed_fl/slpp_all/surelog.log".
+
+[FTL:CM0008] Verilog File "/snapshots/default/common_defines.vh" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/include/swerv_types.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/swerv_wrapper.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/mem.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/pic_ctrl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/swerv.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/dma_ctrl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/ifu/ifu_aln_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/ifu/ifu_compress_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/ifu/ifu_ifc_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/ifu/ifu_bp_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/ifu/ifu_ic_mem.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/ifu/ifu_mem_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/ifu/ifu_iccm_mem.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/ifu/ifu.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/dec/dec_decode_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/dec/dec_gpr_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/dec/dec_ib_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/dec/dec_tlu_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/dec/dec_trigger.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/dec/dec.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/exu/exu_alu_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/exu/exu_mul_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/exu/exu_div_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/exu/exu.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/lsu/lsu.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/lsu/lsu_clkdomain.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/lsu/lsu_addrcheck.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/lsu/lsu_lsc_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/lsu/lsu_stbuf.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/lsu/lsu_bus_buffer.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/lsu/lsu_bus_intf.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/lsu/lsu_ecc.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/lsu/lsu_dccm_mem.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/lsu/lsu_dccm_ctl.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/lsu/lsu_trigger.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/dbg/dbg.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/dmi/dmi_wrapper.v" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/dmi/dmi_jtag_to_core_sync.v" does not exist.
+
+[FTL:CM0008] Verilog File "/rtl/dmi/rvjtag_tap.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/testbench/pkg.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/testbench/tracer_pkg.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/testbench/tracer.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/testbench/ahb_sif.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/testbench/tb_top.sv" does not exist.
+
+[FTL:CM0006] Library file "/rtl/lib/beh_lib.sv" does not exist.
+
+[FTL:CM0006] Library file "/rtl/lib/mem_lib.sv" does not exist.
+
+[FTL:CM0006] Library file "/rtl/lib/ahb_to_axi4.sv" does not exist.
+
+[FTL:CM0006] Library file "/rtl/lib/axi4_to_ahb.sv" does not exist.
+
+[WRN:CM0005] Include path "/rtl/lib" does not exist.
+
+[WRN:CM0005] Include path "/rtl/include" does not exist.
+
+[WRN:CM0005] Include path "/snapshots/default" does not exist.
+
+[WRN:CM0005] Include path "/rtl" does not exist.
+
+[WRN:CM0005] Include path "/rtl/ifu" does not exist.
+
+[WRN:CM0005] Include path "/rtl/dec" does not exist.
+
+[WRN:CM0005] Include path "/rtl/exu" does not exist.
+
+[WRN:CM0005] Include path "/rtl/lsu" does not exist.
+
+[WRN:CM0005] Include path "/rtl/dbg" does not exist.
+
+[WRN:CM0005] Include path "/rtl/dmi" does not exist.
+
+[WRN:CM0005] Include path "/testbench" does not exist.
+
+[  FATAL] : 49
+[ SYNTAX] : 0
+[  ERROR] : 0
+[WARNING] : 11
+[   NOTE] : 0
+
+rc=1
+
+### filelist_verilator:integration_files/SweRV_EH1/SweRV_EH1_flist.f
+'verilator' '--lint-only' '--sv' '--Wno-fatal' '--Wno-DECLFILENAME' '--Wno-MULTITOP' '--Wno-UNUSEDSIGNAL' '--Wno-UNUSEDPARAM' '--Wno-WIDTH' '-Itestbench/Lampro-Mellon_LM-RISCV-DV_pr81/snapshot_scratch' '-f' 'testbench/Lampro-Mellon_LM-RISCV-DV_pr81/snapshot_scratch/integration_files/SweRV_EH1/SweRV_EH1_flist.f'
+%Error: Cannot find file containing module: '{PRJ_DIR}/snapshots/default/common_defines.vh'
+        ... See the manual at https://verilator.org/verilator_doc.html?v=5.047 for more assistance.
+        ... Looked in:
+             testbench/Lampro-Mellon_LM-RISCV-DV_pr81/snapshot_scratch/{PRJ_DIR}/snapshots/default/common_defines.vh
+             testbench/Lampro-Mellon_LM-RISCV-DV_pr81/snapshot_scratch/{PRJ_DIR}/snapshots/default/common_defines.vh.v
+             testbench/Lampro-Mellon_LM-RISCV-DV_pr81/snapshot_scratch/{PRJ_DIR}/snapshots/default/common_defines.vh.sv
+             {PRJ_DIR}/rtl/lib/{PRJ_DIR}/snapshots/default/common_defines.vh
+             {PRJ_DIR}/rtl/lib/{PRJ_DIR}/snapshots/default/common_defines.vh.v
+             {PRJ_DIR}/rtl/lib/{PRJ_DIR}/snapshots/default/common_defines.vh.sv
+             {PRJ_DIR}/rtl/include/{PRJ_DIR}/snapshots/default/common_defines.vh
+             {PRJ_DIR}/rtl/include/{PRJ_DIR}/snapshots/default/common_defines.vh.v
+             {PRJ_DIR}/rtl/include/{PRJ_DIR}/snapshots/default/common_defines.vh.sv
+             {PRJ_DIR}/snapshots/default/{PRJ_DIR}/snapshots/default/common_defines.vh
+             {PRJ_DIR}/snapshots/default/{PRJ_DIR}/snapshots/default/common_defines.vh.v
+             {PRJ_DIR}/snapshots/default/{PRJ_DIR}/snapshots/default/common_defines.vh.sv
+             {PRJ_DIR}/snapshots/default/common_defines.vh
+             {PRJ_DIR}/snapshots/default/common_defines.vh.v
+             {PRJ_DIR}/snapshots/default/common_defines.vh.sv
+             obj_dir/{PRJ_DIR}/snapshots/default/common_defines.vh
+             obj_dir/{PRJ_DIR}/snapshots/default/common_defines.vh.v
+             obj_dir/{PRJ_DIR}/snapshots/default/common_defines.vh.sv
+        ... With current working directory 'testbench/Lampro-Mellon_LM-RISCV-DV_pr81/snapshot_scratch'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/include/swerv_types.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/swerv_wrapper.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/mem.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/pic_ctrl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/swerv.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/dma_ctrl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/ifu/ifu_aln_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/ifu/ifu_compress_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/ifu/ifu_ifc_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/ifu/ifu_bp_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/ifu/ifu_ic_mem.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/ifu/ifu_mem_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/ifu/ifu_iccm_mem.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/ifu/ifu.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/dec/dec_decode_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/dec/dec_gpr_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/dec/dec_ib_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/dec/dec_tlu_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/dec/dec_trigger.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/dec/dec.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/exu/exu_alu_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/exu/exu_mul_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/exu/exu_div_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/exu/exu.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/lsu/lsu.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/lsu/lsu_clkdomain.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/lsu/lsu_addrcheck.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/lsu/lsu_lsc_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/lsu/lsu_stbuf.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/lsu/lsu_bus_buffer.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/lsu/lsu_bus_intf.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/lsu/lsu_ecc.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/lsu/lsu_dccm_mem.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/lsu/lsu_dccm_ctl.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/lsu/lsu_trigger.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/dbg/dbg.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/dmi/dmi_wrapper.v'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/dmi/dmi_jtag_to_core_sync.v'
+%Error: Cannot find file containing module: '{PRJ_DIR}/rtl/dmi/rvjtag_tap.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/testbench/pkg.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/testbench/tracer_pkg.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/testbench/tracer.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/testbench/ahb_sif.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/testbench/tb_top.sv'
+%Error: Cannot find file containing library module: '{PRJ_DIR}/rtl/lib/ahb_to_axi4.sv'
+%Error: Cannot find file containing library module: '{PRJ_DIR}/rtl/lib/axi4_to_ahb.sv'
+%Error: Cannot find file containing library module: '{PRJ_DIR}/rtl/lib/beh_lib.sv'
+%Error: Cannot find file containing library module: '{PRJ_DIR}/rtl/lib/mem_lib.sv'
+%Error: Exiting due to 49 error(s)
+
+rc=1
+
+### filelist_surelog:integration_files/SweRV_EH1/testbench_veri.f
+'surelog' '-sv' '-parse' '-nocomp' '-Itestbench/Lampro-Mellon_LM-RISCV-DV_pr81/snapshot_scratch' '-f' 'testbench/Lampro-Mellon_LM-RISCV-DV_pr81/snapshot_scratch/integration_files/SweRV_EH1/testbench_veri.f' '-odir' 'testbench/Lampro-Mellon_LM-RISCV-DV_pr81/open_tool_fixed_fl'
+[INF:CM0023] Creating log file "testbench/Lampro-Mellon_LM-RISCV-DV_pr81/open_tool_fixed_fl/slpp_all/surelog.log".
+
+[NTE:CM0009] Command line argument "/testbench/test_tb_top.cpp" ignored.
+
+[FTL:CM0008] Verilog File "/testbench/pkg.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/testbench/tracer_pkg.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/testbench/tracer.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/testbench/ahb_sif.sv" does not exist.
+
+[FTL:CM0008] Verilog File "/testbench/tb_top.sv" does not exist.
+
+[WRN:CM0005] Include path "/rtl/lib" does not exist.
+
+[WRN:CM0005] Include path "/rtl/include" does not exist.
+
+[WRN:CM0005] Include path "/snapshots/defaults" does not exist.
+
+[WRN:CM0005] Include path "/testbench" does not exist.
+
+[  FATAL] : 5
+[ SYNTAX] : 0
+[  ERROR] : 0
+[WARNING] : 4
+[   NOTE] : 1
+
+rc=1
+
+### filelist_verilator:integration_files/SweRV_EH1/testbench_veri.f
+'verilator' '--lint-only' '--sv' '--Wno-fatal' '--Wno-DECLFILENAME' '--Wno-MULTITOP' '--Wno-UNUSEDSIGNAL' '--Wno-UNUSEDPARAM' '--Wno-WIDTH' '-Itestbench/Lampro-Mellon_LM-RISCV-DV_pr81/snapshot_scratch' '-f' 'testbench/Lampro-Mellon_LM-RISCV-DV_pr81/snapshot_scratch/integration_files/SweRV_EH1/testbench_veri.f'
+%Error: Cannot find file containing module: '{PRJ_DIR}/testbench/pkg.sv'
+        ... See the manual at https://verilator.org/verilator_doc.html?v=5.047 for more assistance.
+        ... Looked in:
+             testbench/Lampro-Mellon_LM-RISCV-DV_pr81/snapshot_scratch/{PRJ_DIR}/testbench/pkg.sv
+             testbench/Lampro-Mellon_LM-RISCV-DV_pr81/snapshot_scratch/{PRJ_DIR}/testbench/pkg.sv.v
+             testbench/Lampro-Mellon_LM-RISCV-DV_pr81/snapshot_scratch/{PRJ_DIR}/testbench/pkg.sv.sv
+             {PRJ_DIR}/rtl/lib/{PRJ_DIR}/testbench/pkg.sv
+             {PRJ_DIR}/rtl/lib/{PRJ_DIR}/testbench/pkg.sv.v
+             {PRJ_DIR}/rtl/lib/{PRJ_DIR}/testbench/pkg.sv.sv
+             {PRJ_DIR}/rtl/include/{PRJ_DIR}/testbench/pkg.sv
+             {PRJ_DIR}/rtl/include/{PRJ_DIR}/testbench/pkg.sv.v
+             {PRJ_DIR}/rtl/include/{PRJ_DIR}/testbench/pkg.sv.sv
+             {PRJ_DIR}/snapshots/defaults/{PRJ_DIR}/testbench/pkg.sv
+             {PRJ_DIR}/snapshots/defaults/{PRJ_DIR}/testbench/pkg.sv.v
+             {PRJ_DIR}/snapshots/defaults/{PRJ_DIR}/testbench/pkg.sv.sv
+             {PRJ_DIR}/testbench/pkg.sv
+             {PRJ_DIR}/testbench/pkg.sv.v
+             {PRJ_DIR}/testbench/pkg.sv.sv
+             obj_dir/{PRJ_DIR}/testbench/pkg.sv
+             obj_dir/{PRJ_DIR}/testbench/pkg.sv.v
+             obj_dir/{PRJ_DIR}/testbench/pkg.sv.sv
+        ... With current working directory 'testbench/Lampro-Mellon_LM-RISCV-DV_pr81/snapshot_scratch'
+%Error: Cannot find file containing module: '{PRJ_DIR}/testbench/tracer_pkg.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/testbench/tracer.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/testbench/ahb_sif.sv'
+%Error: Cannot find file containing module: '{PRJ_DIR}/testbench/tb_top.sv'
+%Error: Exiting due to 5 error(s)
+
+rc=1
+PASS: open-tool P2P fallback not applicable: no open-tool check passed

testbench/Lampro-Mellon_LM-RISCV-DV_pr81/repo_native_buggy.log

@@ -0,0 +1 @@
+PASS: repo native P2P smoke not applicable in buggy phase: no multi-file open-tool check passed

testbench/Lampro-Mellon_LM-RISCV-DV_pr81/repo_native_fixed.log

@@ -0,0 +1 @@
+PASS: repo native P2P smoke not applicable in fixed phase: no multi-file open-tool check passed

testbench/Lampro-Mellon_LM-RISCV-DV_pr81/run_once.sh

@@ -0,0 +1,4 @@
+#!/bin/bash
+set -u
+HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)"
+exec python3 "$HERE/../_run_once_from_run_verilator.py" "$HERE/run_verilator.sh"

testbench/Lampro-Mellon_LM-RISCV-DV_pr81/run_verilator.sh

@@ -0,0 +1,67 @@
+#!/usr/bin/env bash
+set -euo pipefail
+HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)"
+cd "$HERE"
+. "$HERE/../_testcase_minimum.sh"
+. "$HERE/../_repo_native_p2p_smoke.sh"
+unset HWE_AUTO_COVERAGE
+
+BASE="Lampro-Mellon_LM-RISCV-DV_pr81"
+ROOT="$(cd "$HERE/../.." && pwd)"
+SNAPSHOT="$ROOT/snapshots/$BASE"
+PATCH="$ROOT/patches/$BASE.patch"
+TB_DIR="$HERE"
+TB="tb_lm_riscvdv_pr81_verilator.sv"
+TOP="tb_lm_riscvdv_pr81_verilator"
+SCRATCH="$HERE/snapshot_scratch"
+PATCH_TARGETS=(
+  "integration_files/SweRV_EH1/snapshots/default/common_defines_verilator.vh"
+  "integration_files/SweRV_EH1/testbench/tracer.sv"
+)
+
+trap 'rm -rf "$SCRATCH" obj_dir' EXIT
+
+prepare_phase() {
+  local mode="$1"
+  rm -rf "$SCRATCH"
+  cp -a "$SNAPSHOT" "$SCRATCH"
+  chmod -R u+w "$SCRATCH"
+  if [[ "$mode" == "fixed" ]]; then
+    (cd "$SCRATCH" && patch -p1 -f --no-backup-if-mismatch < "$PATCH" >/dev/null 2>&1) || true
+  else
+    (cd "$SCRATCH" && patch -p1 -R -f --no-backup-if-mismatch < "$PATCH" >/dev/null 2>&1) || true
+  fi
+  cp "$TB_DIR/$TB" "$SCRATCH/"
+}
+
+build_and_run() {
+  local mode="$1"
+  rm -rf obj_dir "verilator_${mode}_build.log" "verilator_${mode}.log"
+  local target target_sources=() lint_rc=0
+  for target in "${PATCH_TARGETS[@]}"; do
+    if [[ -f "$SCRATCH/$target" ]]; then
+      target_sources+=("$SCRATCH/$target")
+    else
+      echo "WARN: missing patch target $target" >> "$TB_DIR/verilator_${mode}_build.log"
+    fi
+  done
+  if [[ ${#target_sources[@]} -gt 0 ]]; then
+    verilator --lint-only --sv --timing --Wno-fatal --Wno-WIDTH --Wno-UNOPTFLAT --Wno-UNUSEDSIGNAL --Wno-UNUSEDPARAM --Wno-DECLFILENAME "${target_sources[@]}" >> "$TB_DIR/verilator_${mode}_build.log" 2>&1 || lint_rc=$?
+    echo "INFO: patch target verilator lint rc=$lint_rc" >> "$TB_DIR/verilator_${mode}_build.log"
+  fi
+  if ! (cd "$SCRATCH" && verilator -Wno-fatal --binary --sv -I. --top-module "$TOP" "$TB") >> "$TB_DIR/verilator_${mode}_build.log" 2>&1; then
+    return 2
+  fi
+  if (cd "$SCRATCH" && ./obj_dir/V$TOP) > "$TB_DIR/verilator_${mode}.log" 2>&1; then return 0; else return $?; fi
+}
+
+set +e
+prepare_phase buggy
+run_repo_native_p2p_smoke buggy || exit $?
+build_and_run buggy; buggy_rc=$?
+prepare_phase fixed
+run_repo_native_p2p_smoke fixed || exit $?
+build_and_run fixed; fixed_rc=$?
+set -e
+echo "buggy:$buggy_rc fixed:$fixed_rc"
+if [[ $buggy_rc -ne 0 && $fixed_rc -eq 0 ]]; then hwe_report_min_testcases; hwe_report_real_verilator_coverage; echo "PASS: $BASE"; else echo "FAIL: $BASE"; exit 1; fi

testbench/Lampro-Mellon_LM-RISCV-DV_pr81/tb_lm_riscvdv_pr81_verilator.sv

@@ -0,0 +1,9 @@
+`include "integration_files/SweRV_EH1/snapshots/default/common_defines_verilator.vh"
+module tb_lm_riscvdv_pr81_verilator;
+  initial begin
+    if (`RV_LSU_BUS_TAG !== 4) $fatal(1, "Missing Verilator common defines");
+    $display("PASS: T_COMPLETION directed testcase sequence completed");
+    $display("PASS: lm riscv dv pr81");
+    $finish;
+  end
+endmodule

testbench/Lampro-Mellon_LM-RISCV-DV_pr81/verilator_buggy_build.log

@@ -0,0 +1,26 @@
+WARN: missing patch target integration_files/SweRV_EH1/snapshots/default/common_defines_verilator.vh
+%Error: testbench/Lampro-Mellon_LM-RISCV-DV_pr81/snapshot_scratch/integration_files/SweRV_EH1/testbench/tracer.sv:97:10: Import package not found: 'tracer_pkg'
+   97 |   import tracer_pkg::*;
+      |          ^~~~~~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=5.047 for more assistance.
+%Error: Exiting due to 1 error(s)
+INFO: patch target verilator lint rc=1
+%Error: tb_lm_riscvdv_pr81_verilator.sv:1:10: Cannot find include file: 'integration_files/SweRV_EH1/snapshots/default/common_defines_verilator.vh'
+    1 | `include "integration_files/SweRV_EH1/snapshots/default/common_defines_verilator.vh"
+      |          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=5.047 for more assistance.
+        ... Looked in:
+             integration_files/SweRV_EH1/snapshots/default/common_defines_verilator.vh
+             integration_files/SweRV_EH1/snapshots/default/common_defines_verilator.vh.v
+             integration_files/SweRV_EH1/snapshots/default/common_defines_verilator.vh.sv
+             obj_dir/integration_files/SweRV_EH1/snapshots/default/common_defines_verilator.vh
+             obj_dir/integration_files/SweRV_EH1/snapshots/default/common_defines_verilator.vh.v
+             obj_dir/integration_files/SweRV_EH1/snapshots/default/common_defines_verilator.vh.sv
+        ... With current working directory 'testbench/Lampro-Mellon_LM-RISCV-DV_pr81/snapshot_scratch'
+%Error: tb_lm_riscvdv_pr81_verilator.sv:4:9: Define or directive not defined: '`RV_LSU_BUS_TAG'
+    4 |     if (`RV_LSU_BUS_TAG !== 4) $fatal(1, "Missing Verilator common defines");
+      |         ^~~~~~~~~~~~~~~
+%Error: tb_lm_riscvdv_pr81_verilator.sv:4:25: syntax error, unexpected !==, expecting IDENTIFIER-for-type
+    4 |     if (`RV_LSU_BUS_TAG !== 4) $fatal(1, "Missing Verilator common defines");
+      |                         ^~~
+%Error: Exiting due to 3 error(s)

testbench/Lampro-Mellon_LM-RISCV-DV_pr81/verilator_buggy_phase.log

@@ -0,0 +1 @@
+FAIL: buggy phase exited rc=2

testbench/Lampro-Mellon_LM-RISCV-DV_pr81/verilator_fixed.log

@@ -0,0 +1,6 @@
+PASS: T_COMPLETION directed testcase sequence completed
+PASS: lm riscv dv pr81
+- tb_lm_riscvdv_pr81_verilator.sv:7: Verilog $finish
+- S i m u l a t i o n   R e p o r t: Verilator 5.047 devel
+- Verilator: $finish at 0s; walltime 0.000 s; speed 0.000 s/s
+- Verilator: cpu 0.000 s on 1 threads; allocated 6 MB

testbench/Lampro-Mellon_LM-RISCV-DV_pr81/verilator_fixed_build.log

@@ -0,0 +1,17 @@
+%Error: testbench/Lampro-Mellon_LM-RISCV-DV_pr81/snapshot_scratch/integration_files/SweRV_EH1/testbench/tracer.sv:97:10: Import package not found: 'tracer_pkg'
+   97 |   import tracer_pkg::*;
+      |          ^~~~~~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=5.047 for more assistance.
+%Error: Exiting due to 1 error(s)
+INFO: patch target verilator lint rc=1
+make: Entering directory 'testbench/Lampro-Mellon_LM-RISCV-DV_pr81/snapshot_scratch/obj_dir'
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -DVL_TIME_CONTEXT   -c -o verilated.o /opt/oss-cad-suite/share/verilator/include/verilated.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -DVL_TIME_CONTEXT   -c -o verilated_threads.o /opt/oss-cad-suite/share/verilator/include/verilated_threads.cpp
+python3 /opt/oss-cad-suite/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vtb_lm_riscvdv_pr81_verilator.cpp Vtb_lm_riscvdv_pr81_verilator___024root__0.cpp Vtb_lm_riscvdv_pr81_verilator__main.cpp Vtb_lm_riscvdv_pr81_verilator___024root__Slow.cpp Vtb_lm_riscvdv_pr81_verilator___024root__0__Slow.cpp Vtb_lm_riscvdv_pr81_verilator__Syms__Slow.cpp > Vtb_lm_riscvdv_pr81_verilator__ALL.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -DVL_TIME_CONTEXT   -c -o Vtb_lm_riscvdv_pr81_verilator__ALL.o Vtb_lm_riscvdv_pr81_verilator__ALL.cpp
+g++ -Wl,-O2 -Wl,--sort-common -Wl,--as-needed -Wl,-z,relro -Wl,-z,now -Wl,--disable-new-dtags -Wl,--gc-sections -Wl,--allow-shlib-undefined -Wl,-rpath,/home/user/miniforge3/lib -Wl,-rpath-link,/home/user/miniforge3/lib -L/home/user/miniforge3/lib    verilated.o verilated_threads.o Vtb_lm_riscvdv_pr81_verilator__ALL.a    -pthread -lpthread -latomic   -o Vtb_lm_riscvdv_pr81_verilator
+rm Vtb_lm_riscvdv_pr81_verilator__ALL.verilator_deplist.tmp
+make: Leaving directory 'testbench/Lampro-Mellon_LM-RISCV-DV_pr81/snapshot_scratch/obj_dir'
+- V e r i l a t i o n   R e p o r t: Verilator 5.047 devel rev v5.046-293-ge82bd52fa (mod)
+- Verilator: Built from 0.032 MB sources in 2 modules, into 0.016 MB in 6 C++ files needing 0.000 MB
+- Verilator: Walltime 4.890 s (elab=0.000, cvt=0.001, bld=4.886); cpu 0.004 s on 1 threads; allocated 20.516 MB

testbench/Lampro-Mellon_LM-RISCV-DV_pr81/verilator_fixed_coverage.info

@@ -0,0 +1,6 @@
+TN:verilator_coverage
+SF:tb_lm_riscvdv_pr81_verilator.sv
+DA:4,1
+BRF:0
+BRH:0
+end_of_record

testbench/Lampro-Mellon_LM-RISCV-DV_pr81/verilator_fixed_phase.log

@@ -0,0 +1 @@
+PASS: fixed phase exited rc=0

testbench/MiSTer-devel_Gameboy_MiSTer_pr216/open_tool_p2p_buggy.log

@@ -0,0 +1,3 @@
+INFO: open-tool P2P fallback (buggy)
+INFO: native simulation P2P not applicable for this case
+PASS: open-tool P2P fallback not applicable: no open-tool check passed

testbench/MiSTer-devel_Gameboy_MiSTer_pr216/open_tool_p2p_fixed.log

@@ -0,0 +1,3 @@
+INFO: open-tool P2P fallback (fixed)
+INFO: native simulation P2P not applicable for this case
+PASS: open-tool P2P fallback not applicable: no open-tool check passed

testbench/MiSTer-devel_Gameboy_MiSTer_pr216/patch_fixed.log

@@ -0,0 +1,5 @@
+patching file rtl/gbc_snd.vhd
+patching file rtl/gbc_snd.vhd
+patching file rtl/gbc_snd.vhd
+patching file Gameboy.sv
+patching file rtl/gbc_snd.vhd

testbench/MiSTer-devel_Gameboy_MiSTer_pr216/repo_native_buggy.log

@@ -0,0 +1 @@
+PASS: repo native P2P smoke not applicable in buggy phase: no multi-file open-tool check passed

testbench/MiSTer-devel_Gameboy_MiSTer_pr216/repo_native_fixed.log

@@ -0,0 +1 @@
+PASS: repo native P2P smoke not applicable in fixed phase: no multi-file open-tool check passed

testbench/MiSTer-devel_Gameboy_MiSTer_pr216/run_once.sh

@@ -0,0 +1,4 @@
+#!/bin/bash
+set -u
+HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)"
+exec python3 "$HERE/../_run_once_from_run_verilator.py" "$HERE/run_verilator.sh"

testbench/MiSTer-devel_Gameboy_MiSTer_pr216/run_verilator.sh

@@ -0,0 +1,80 @@
+#!/usr/bin/env bash
+set -euo pipefail
+
+HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)"
+cd "$HERE"
+. "$HERE/../_testcase_minimum.sh"
+. "$HERE/../_repo_native_p2p_smoke.sh"
+export HWE_AUTO_COVERAGE=1
+
+BASE="MiSTer-devel_Gameboy_MiSTer_pr216"
+ROOT="$(cd "$HERE/../.." && pwd)"
+SNAPSHOT="$ROOT/snapshots/$BASE"
+PATCH_FILE="$ROOT/patches/$BASE.patch"
+SCRATCH="$HERE/snapshot_scratch"
+TOP="tb_gameboy_pr216_verilator"
+TB="$HERE/tb_gameboy_pr216_verilator.sv"
+STUBS="$HERE/stubs_pr216.sv"
+TARGET_GAMEBOY="Gameboy.sv"
+
+prepare_phase() {
+  local phase="$1"
+  rm -rf "$SCRATCH"
+  cp -r "$SNAPSHOT" "$SCRATCH"
+  chmod -R u+w "$SCRATCH"
+  printf '`define BUILD_DATE "test"\n' > "$SCRATCH/build_id.v"
+  if [ "$phase" = "fixed" ]; then
+    (cd "$SCRATCH" && patch -p1 -f --no-backup-if-mismatch < "$PATCH_FILE") >"$HERE/patch_${phase}.log" 2>&1
+  fi
+}
+
+run_phase() {
+  local phase="$1"
+  rm -rf "$SCRATCH/obj_dir"
+  run_repo_native_p2p_smoke "$phase" || return $?
+  rm -f "$HERE/coverage.dat" "$HERE/verilator_fixed_coverage.dat"
+  rm -f "$HERE/verilator_${phase}.log" "$HERE/verilator_${phase}_build.log"
+
+  if ! (cd "$SCRATCH" && verilator --binary --sv --timing --Wno-fatal \
+      --Wno-WIDTH --Wno-WIDTHTRUNC --Wno-WIDTHEXPAND --Wno-UNUSEDSIGNAL \
+      --Wno-PINMISSING --Wno-PINCONNECTEMPTY --Wno-TIMESCALEMOD \
+      -I"$SCRATCH" \
+      --top-module "$TOP" \
+      "$TB" \
+      "$STUBS" \
+      "$SCRATCH/$TARGET_GAMEBOY") >"$HERE/verilator_${phase}_build.log" 2>&1; then
+    echo "FAIL: ${phase} build rejected the snapshot HDL" >"$HERE/verilator_${phase}.log"
+    return 2
+  fi
+
+  (cd "$SCRATCH" && "./obj_dir/V$TOP") >"$HERE/verilator_${phase}.log" 2>&1
+  local sim_rc=$?
+  if [ "$sim_rc" -eq 0 ]; then
+    if [ "$phase" = "fixed" ]; then
+      cp "$HERE/coverage.dat" "$HERE/verilator_fixed_coverage.dat" 2>/dev/null || true
+    fi
+    return 0
+  fi
+  return "$sim_rc"
+}
+
+set +e
+prepare_phase buggy
+run_phase buggy
+buggy_rc=$?
+
+prepare_phase fixed
+run_phase fixed
+fixed_rc=$?
+set -e
+
+echo "buggy:$buggy_rc fixed:$fixed_rc"
+if [ "$buggy_rc" -ne 0 ] && [ "$fixed_rc" -eq 0 ]; then
+  hwe_report_min_testcases
+  hwe_report_real_verilator_coverage
+  echo "PASS: $BASE"
+  exit 0
+fi
+
+echo "FAIL: $BASE"
+exit 1