| {"id": "brv-gl-03", "family": "crossarch_equivalence", "tier": "medium", "instruction": "BLOCK-A and BLOCK-B below are scrubbed disassembly of two single functions from production Debian/Ubuntu glibc 2.39 cross-toolchain builds (AArch64, RISC-V, MIPS64r6 n64, PowerPC64 little-endian). Each block header names its ISA. Branch-target symbol labels and numeric relocation comments were removed; MIPS blocks keep objdump linear order including branch-delay-slot placement; 64-bit constants appear as multi-instruction immediate-materialization chains (lui/ori/addi/dsll sequences). Decide whether the two blocks are implementations of the SAME function from this closed set: strcmp, strlen, memchr, floor, ceil, trunc, fabs, sqrt. Answer exactly {\"same\":true,\"symbol\":\"<name>\"} or {\"same\":false}.", "input": "BLOCK-A (AArch64):\n9bfc4: sub x10, x1, x0\n9bfc8: mov x8, #0x101010101010101\n9bfcc: and x6, x0, #0x7\n9bfd0: tst x10, #0x7\n9bfd4: b.ne 9c054\n9bfd8: cbnz x6, 9c030\n9bfdc: nop\n9bfe0: ldr x3, [x0, x10]\n9bfe4: ldr x2, [x0], #8\n9bfe8: sub x4, x2, x8\n9bfec: orr x6, x2, #0x7f7f7f7f7f7f7f7f\n9bff0: bics x4, x4, x6\n9bff4: ccmp x2, x3, #0x0, eq\n9bff8: b.eq 9bfe0\n9bffc: eor x5, x2, x3\n9c000: orr x6, x5, x4\n9c004: rev x6, x6\n9c008: rev x2, x2\n9c00c: rev x3, x3\n9c010: clz x9, x6\n9c014: lsl x2, x2, x9\n9c018: lsl x3, x3, x9\n9c01c: lsr x2, x2, #56\n9c020: sub x0, x2, x3, lsr #56\n\nBLOCK-B (MIPS64):\nd8270: or t0,a0,a1\nd8274: andi t0,t0,0x3\nd8278: bnez t0,d83f4\nd827c: lui t8,0x101\nd8280: ori t8,t8,0x101\nd8284: lui t9,0x7f7f\nd8288: ori t9,t9,0x7f7f\nd828c: lw v0,0(a0)\nd8290: lw v1,0(a1)\nd8294: subu t0,v0,t8\nd8298: bne v0,v1,d839c\nd829c: nor t1,v0,t9\nd82a0: and t0,t0,t1\nd82a4: bnez t0,d8394\nd82a8: nop\nd82ac: lw v0,4(a0)\nd82b0: lw v1,4(a1)\nd82b4: subu t0,v0,t8\nd82b8: bne v0,v1,d839c\nd82bc: nor t1,v0,t9\nd82c0: and t0,t0,t1\nd82c4: bnez t0,d8394\nd82c8: nop\nd82cc: lw v0,8(a0)\nd82d0: lw v1,8(a1)\nd82d4: subu t0,v0,t8", "answer": "{\"same\": true, \"symbol\": \"strcmp\"}", "verify": "detailed rubric", "provenance": {"binary": "/usr/aarch64-linux-gnu/lib/libc.so.6 ; /usr/mips64el-linux-gnuabi64/lib/libc.so.6", "sha256_16": "101106b8ae666012 ; 29e42020c092abb1", "addr": "0x9bfc4 ; 0xd8270", "arch": "AArch64 ; MIPS R3000"}, "license": "(c) Samuel Anttila / RE-Lab - commercial license on purchase"} | |
| {"id": "brv-ag-10", "family": "agentic_flag_hunt", "tier": "hard", "instruction": "You have the binary hightwist in your working directory (x86-64 static ELF, symbols stripped). Find the exact argv[1] that makes it print OK. Use any static-analysis tools available; you may also execute it.", "input": "binary file: hightwist", "answer": "Vyrtane_2cK9", "verify": "exact argv match; program prints OK", "provenance": {"binary": "bins/hightwist", "sha256_16": "24ea8b38101e457e", "arch": "x86-64"}, "license": "(c) Samuel Anttila / RE-Lab - commercial license on purchase"} | |
| {"id": "brv-gl-19", "family": "func_summary", "tier": "medium", "instruction": "The block below is scrubbed disassembly of one function from AArch64 glibc 2.39 (libc.so.6) at 0x9dd60. Symbol labels and numeric comments removed. Summarize precisely what this function does and name it: give the exact exported symbol, or for an IFUNC resolver the symbol whose implementation it selects.", "input": "9dd60: adrp x2, 1af000\n9dd64: ldr x2, [x2, #3728]\n9dd68: stp x29, x30, [sp, #-16]!\n9dd6c: adrp x1, a2000\n9dd70: mov x29, sp\n9dd74: ldr x2, [x2, #552]\n9dd78: add x1, x1, #0xd40\n9dd7c: adrp x0, a2000\n9dd80: add x0, x0, #0xc00\n9dd84: ldp x29, x30, [sp], #16\n9dd88: tst x2, #0x40000\n9dd8c: csel x0, x0, x1, eq\n9dd90: ret", "answer": "IFUNC resolver for strlen (exported symbol strlen is an STT_GNU_IFUNC; this runs once at load time, it contains no string code). It loads GLRO(dl_hwcap) from the loader's _rtld_global_ro block (adrp + ldr [x2,#3728], then ldr [x2,#552]), tests bit 0x40000 = HWCAP_ASIMD (1<<14) with tst, and returns via csel one of two candidate function addresses built by adrp/add: 0xa2c00 when the ASIMD bit is set, 0xa2d40 otherwise - i.e. the ASIMD strlen variant versus the generic fallback (variant names __strlen_asimd/__strlen_generic are glibc-internal and not in symtab).", "verify": "detailed rubric", "provenance": {"binary": "/usr/aarch64-linux-gnu/lib/libc.so.6", "sha256_16": "101106b8ae666012", "addr": "0x9dd60", "arch": "AArch64"}, "license": "(c) Samuel Anttila / RE-Lab - commercial license on purchase"} | |
| {"id": "brv-relf-012", "family": "func_id_exact", "tier": "hard", "instruction": "This is Ghidra x86-64 disassembly (excerpt) of one function from libz.so.1. Identify the exact symbol name of this function.", "input": "0x106be6: LEA RAX, [RCX + 0x15b0]\n...\n0x106c20: MOVZX EAX, byte ptr [R8] ; 16-byte unrolled sum chain\n0x106c37: ADD RAX, R15\n0x106c44: ADD R14, RAX\n0x106c51: ADD R13, R14\n0x106c61: ADD R12, R13\n... (running s2 as sum of running s1 over 16 bytes) ...\n0x106cf9: JNZ 0x00106c20\n0x106cff: MOV RAX, 0xf00e10d2fc5cd ; Barrett magic for 65521\n0x106d11: MUL R15\n0x106d17: SUB RAX, RDX\n0x106d1a: SHR RAX, 0x1\n0x106d1d: ADD RDX, RAX\n0x106d20: SHR RDX, 0xf\n0x106d24: IMUL RAX, RDX, 0xfff1 ; q*65521\n0x106d2b: SUB R15, RAX ; s1 -= q*MOD\n0x106d38: MUL RDI ; same reduction for s2\n...\n0x106ed9: CMP R15, 0xfff0\n0x106ee0: LEA RAX, [R15 + -0xfff1]\n0x106ef5: CMOVA R15, RAX ; conditional subtract once\n...\n0x106d82: SHL RAX, 0x10\n0x106d87: OR RAX, R15 ; return (s2<<16)|s1", "answer": "adler32_z", "verify": "exact symbol match after normalization (case-insensitive, ignore version suffixes).", "provenance": {"binary": "bins/libz.so.1", "sha256_16": "f61677c7bdb7c2aa", "addr": "0x6ba0", "size": 1716}, "license": "(c) Samuel Anttila / RE-Lab - commercial license on purchase"} | |
| {"id": "funcidmc-a6d1ab7099b62132-4f70", "family": "func_id_mc", "tier": "medium", "instruction": "Identify the function from its disassembly. Reply with the correct option.", "input": " 4f70:\tf3 0f 1e fa \tendbr64\n 4f74:\t55 \tpush %rbp\n 4f75:\t48 89 e5 \tmov %rsp,%rbp\n 4f78:\t53 \tpush %rbx\n 4f79:\t48 81 ec 00 10 00 00 \tsub $0x1000,%rsp\n 4f80:\t48 83 0c 24 00 \torq $0x0,(%rsp)\n 4f85:\t48 81 ec e8 00 00 00 \tsub $0xe8,%rsp\n 4f8c:\t48 89 8d 58 ff ff ff \tmov %rcx,-0xa8(%rbp)\n 4f93:\t4c 89 85 60 ff ff ff \tmov %r8,-0xa0(%rbp)\n 4f9a:\t4c 89 8d 68 ff ff ff \tmov %r9,-0x98(%rbp)\n 4fa1:\t84 c0 \ttest %al,%al\n 4fa3:\t74 23 \tje 4fc8 <...>\n 4fa5:\t0f 29 85 70 ff ff ff \tmovaps %xmm0,-0x90(%rbp)\n 4fac:\t0f 29 4d 80 \tmovaps %xmm1,-0x80(%rbp)\n 4fb0:\t0f 29 55 90 \tmovaps %xmm2,-0x70(%rbp)\n 4fb4:\t0f 29 5d a0 \tmovaps %xmm3,-0x60(%rbp)\n 4fb8:\t0f 29 65 b0 \tmovaps %xmm4,-0x50(%rbp)\n 4fbc:\t0f 29 6d c0 \tmovaps %xmm5,-0x40(%rbp)\n 4fc0:\t0f 29 75 d0 \tmovaps %xmm6,-0x30(%rbp)\n 4fc4:\t0f 29 7d e0 \tmovaps %xmm7,-0x20(%rbp)\n 4fc8:\t64 48 8b 04 25 28 00 \tmov %fs:0x28,%rax\n 4fcf:\t00 00 \n 4fd1:\t48 89 85 38 ff ff ff \tmov %rax,-0xc8(%rbp)\n 4fd8:\t31 c0 \txor %eax,%eax\n 4fda:\t85 fe \ttest %edi,%esi\n 4fdc:\t75 22 \tjne 5000 <...>\n 4fde:\t48 8b 85 38 ff ff ff \tmov -0xc8(%rbp),%rax\n 4fe5:\t64 48 2b 04 25 28 00 \tsub %fs:0x28,%rax\n 4fec:\t00 00 \n 4fee:\t0f 85 80 00 00 00 \tjne 5074 <...>\n 4ff4:\t48 8b 5d f8 \tmov -0x8(%rbp),%rbx\n 4ff8:\tc9 \tleave\n 4ff9:\tc3 \tret\n 4ffa:\t66 0f 1f 44 00 00 \tnopw 0x0(%rax,%rax,1)\n 5000:\t48 8d 45 10 \tlea 0x10(%rbp),%rax\n 5004:\t49 89 d0 \tmov %rdx,%r8\n 5007:\t48 8d 9d 30 ef ff ff \tlea -0x10d0(%rbp),%rbx\n 500e:\tb9 00 10 00 00 \tmov $0x1000,%ecx\n 5013:\t48 89 85 18 ef ff ff \tmov %rax,-0x10e8(%rbp)\n 501a:\t4c 8d 8d 10 ef ff ff \tlea -0x10f0(%rbp),%r9\n 5021:\tba 02 00 00 00 \tmov $0x2,%edx\n 5026:\t48 89 df \tmov %rbx,%rdi\n 5029:\t48 8d 85 40 ff ff ff \tlea -0xc0(%rbp),%rax\n 5030:\tbe 00 10 00 00 \tmov $0x1000,%esi\n 5035:\tc7 85 10 ef ff ff 18 \tmovl $0x18,-0x10f0(%rbp)\n 503c:\t00 00 00 \n 503f:\tc7 85 14 ef ff ff 30 \tmovl $0x30,-0x10ec(%rbp)\n 5046:\t00 00 00 \n 5049:\t48 89 85 20 ef ff ff \tmov %rax,-0x10e0(%rbp)\n 5050:\te8 ab e2 ff ff \tcall 3300 <...>\n 5055:\t3d fd 0f 00 00 \tcmp $0xffd,%eax\n 505a:\t76 07 \tjbe 5063 <...>\n 505c:\tc6 85 2e ff ff ff 0a \tmovb $0xa,-0xd2(%rbp)\n 5063:\t48 8b 05 56 9f 00 00 \tmov 0x9f56(%rip),%rax # efc0 <...>\n 506a:\t48 89 df \tmov %rbx,%rdi\n 506d:\tff 10 \tcall *(%rax)\n 506f:\te9 6a ff ff ff \tjmp 4fde <...>\n 5074:\te8 c7 e1 ff ff \tcall 3240 <...>", "answer": {"correct": "lutil_debug", "options": ["ber_bvreplace_x", "ber_get_bitstringa", "ber_strndup", "lutil_debug"]}, "verify": "exact option match", "provenance": {"binary": "liblber.so.2.0.200", "sha256_16": "a6d1ab7099b62132", "addr": "0x4f70", "size": 265}, "license": "(c) RE-Lab — commercial license on purchase"} | |
| {"id": "brv-xarch-011", "family": "arch_semantics_qa", "tier": "medium", "instruction": "AArch64: x0 is a 64-bit value and w1 an unsigned count. What does this three-instruction function compute? Derivable from the shown instructions only.", "input": "neg w1, w1\nror x0, x0, x1\nret", "answer": "It rotates x0 left by the amount in w1. AArch64 ror normalizes its shift amount modulo the register width (64), so rotating right by (-r mod 64) equals rotating left by r; neg first forms the two's-complement of the count (and zeroes the upper half of x1, which is irrelevant since only the low 6 bits steer ror). Net: return rotl64(x0, w1) - a rotate-left implemented as a single ror with a negated shift.", "verify": "detailed rubric", "provenance": {"binary": "bins/xhash-aarch64", "sha256_16": "02c89b8c70ab496a", "addr": "0x400834", "arch": "AArch64"}, "license": "(c) Samuel Anttila / RE-Lab - commercial license on purchase"} | |
| {"id": "brv-isa-14", "family": "isa_semantics_qa", "tier": "medium", "instruction": "RISC-V fragment; on entry a0 holds the argument. State what value ends up in a0 at ret, derived from the shown instructions only.", "input": "mv a5,a0\nli a0,0\nbeqz a5,L1\nL0:\naddiw a4,a5,-1\nand a5,a5,a4\nsext.w a5,a5\naddiw a0,a0,1\nbnez a5,L0\nret\nL1:\nret", "answer": "a0 = number of set bits (population count) of the low 32 bits of the original a0. mv copies the argument into a5 and li zeroes the counter a0; the loop body addiw -1 / and implements x &= x-1 (clears the lowest set bit), sext.w re-sign-extends to keep beqz/bnez correct on 32-bit values, and addiw +1 increments the counter each iteration until a5 becomes zero. The beqz guard handles input 0. Net: Kernighan's popcount loop; return value in a0.", "verify": "detailed rubric", "provenance": {"binary": "bins/xrot-riscv64", "sha256_16": "ccd3e8a49afbbb6d", "addr": "0x105b8", "arch": "RISC-V"}, "license": "(c) Samuel Anttila / RE-Lab - commercial license on purchase"} | |
| {"id": "brv-repe-013", "family": "pe_structure_qa", "tier": "easy", "instruction": "From this PE header excerpt, answer: (1) 32-bit or 64-bit and how you know, (2) EXE or DLL and which field says the intended environment, (3) which linker/toolchain family produced it.", "input": "File header: Machine=0x8664, NumberOfSections=6. Optional header: Magic=0x20B, MajorLinkerVersion=14, MinorLinkerVersion=51, AddressOfEntryPoint RVA=0x1820, ImageBase=0x140000000, SizeOfImage=0x28000, Subsystem=3.", "answer": "(1) 64-bit: Magic 0x20B is PE32+ and Machine 0x8664 is IMAGE_FILE_MACHINE_AMD64. (2) Console-subsystem image: Subsystem=3 is IMAGE_SUBSYSTEM_WINDOWS_CUI, i.e. a text-mode program (console executables are EXEs; the preferred ImageBase 0x140000000 is the MSVC x64 default). (3) Linker version 14.51 belongs to Microsoft's link.exe from the Visual Studio 2022 (MSVC v14x) toolset — same family as the .CRT$/MSVC CRT strings also present in such images.", "verify": "exact field match", "provenance": {"binary": "bins/decoder-x64.exe", "sha256_16": "14870d2ab2c9a5fb", "addr": "0x140000118"}, "license": "(c) Samuel Anttila / RE-Lab - commercial license on purchase"} | |
| {"id": "brv-repe-003", "family": "pe_import_reasoning", "tier": "medium", "instruction": "Given this Windows x64 executable's import table and application strings, what is the program most likely doing? Justify from imports/strings; flag what the evidence does not support.", "input": "Imports (all from KERNEL32.dll): GetCommandLineA/W, GetStdHandle, WriteConsoleW, WriteFile, ExitProcess, HeapAlloc/HeapFree/VirtualProtect, LoadLibraryExW/GetProcAddress, standard CRT startup/unwind/locale helpers. No other DLL is imported. Selected strings: \"usage: vmcheck <input>\", \"accepted\", \"rejected\".", "answer": "A one-argument accept/reject gate: `prog <input>` prints either \"accepted\" or \"rejected\"; with no argument it prints the usage line. The binary vocabulary accepted/rejected plus a single <input> parameter indicates a boolean validator over the argument string, decided entirely in-process: the KERNEL32-only import set excludes the usual system-query APIs one might expect for a 'VM check' (no Advapi32 registry, no WMI/Fastprox, no SETUPAPI/IPHLPAPI, no GPU/display APIs), so any 'virtual machine' semantics implied by the name must be implemented with in-process code (e.g. CPUID-style probing or pure computation on <input>), not OS queries. Observation: console CLI, single arg, binary verdict. Inference beyond evidence: what property is being checked.", "verify": "detailed rubric", "provenance": {"binary": "bins/vmcheck-x64.exe", "sha256_16": "24edb05e228ecd29", "addr": "0x140010380"}, "license": "(c) Samuel Anttila / RE-Lab - commercial license on purchase"} | |