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You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
// Designed by: Amir Yazdanbakhsh
// Date: March 26th - 2015
// Alternative Computing Technologies Lab.
// Georgia Institute of Technology
#include "stdlib.h"
#include <fstream>
#include <iostream>
#include <cstddef>
// Cuda Libraries
#include <cuda_runtime_api.h>
#include <cuda.h>
#define EPSILON 1e-12 // EPSILON represents the error buffer used to denote a hit
using namespace std;
__device__ bool newComputeIntervals(float vv0, float vv1, float vv2, float d0, float d1, float d2, float d0d1, float d0d2, float abc[3], float x0x1[2])
{
if (d0d1 > 0.0f) {
// d0d2 <= 0 --> i.e. d0, d1 are on the same side, d2 on the other or on the plane
abc[0] = vv2;
abc[1] = (vv0 - vv2) * d2;
abc[2] = (vv1 - vv2) * d2;
x0x1[0] = d2 - d0;
x0x1[1] = d2 - d1;
} else if (d0d2 > 0.0f) {
// d0d1 <= 0
abc[0] = vv1;
abc[1] = (vv0 - vv1) * d1;
abc[2] = (vv2 - vv1) * d1;
x0x1[0] = d1 - d0;
x0x1[1] = d1 - d2;
} else if (d1 * d2 > 0.0f || d0 != 0.0f) {
// d0d1 <= 0 or d0 != 0
abc[0] = vv0;
abc[1] = (vv1 - vv0) * d0;
abc[2] = (vv2 - vv0) * d0;
x0x1[0] = d0 - d1;
x0x1[1] = d0 - d2;
} else if (d1 != 0.0f) {
abc[0] = vv1;
abc[1] = (vv0 - vv1) * d1;
abc[2] = (vv2 - vv1) * d1;
x0x1[0] = d1 - d0;
x0x1[1] = d1 - d2;
} else if (d2 != 0.0f) {
abc[0] = vv2;
abc[1] = (vv0 - vv2) * d2;
abc[2] = (vv1 - vv2) * d2;
x0x1[0] = d2 - d0;
x0x1[1] = d2 - d1;
} else {
// Triangles are coplanar
return true;
}
return false;
}
__device__ bool edgeEdgeTest(float v0[3], float u0[3], float u1[3], int i0, int i1, float Ax, float Ay)
{
float Bx = u0[i0] - u1[i0];
float By = u0[i1] - u1[i1];
float Cx = v0[i0] - u0[i0];
float Cy = v0[i1] - u0[i1];
float f = Ay * Bx - Ax * By;
float d = By * Cx - Bx * Cy;
if ((f > 0 && d >= 0 && d <= f) || (f < 0 && d <= 0 && d >= f)) {
float e = Ax * Cy - Ay * Cx;
if (f > 0) {
if (e >= 0 && e <= f)
return true;
} else {
if (e <= 0 && e >= f)
return true;
}
}
return false;
}
__device__ bool pointInTri(float V0[3], float U0[3], float U1[3], float U2[3], int i0, int i1)
{
// Check if V0 is inside triangle (U0,U1,U2)
float a, b, c, d0, d1, d2;
a = U1[i1] - U0[i1];
b = -(U1[i0] - U0[i0]);
c = -a * U0[i0] - b * U0[i1];
d0 = a * V0[i0] + b * V0[i1] + c;
a = U2[i1] - U1[i1];
b = -(U2[i0] - U1[i0]);
c = -a * U1[i0] - b * U1[i1];
d1 = a * V0[i0] + b * V0[i1] + c;
a = U0[i1] - U2[i1];
b = -(U0[i0] - U2[i0]);
c = -a * U2[i0] - b * U2[i1];
d2 = a * V0[i0] + b * V0[i1] + c;
if ((d0 * d1) > 0.0 && (d0 * d2) > 0.0)
return true;
return false;
}
__device__ bool coplanarTriTri(float n[3], float v0[3], float v1[3], float v2[3], float u0[3], float u1[3], float u2[3])
{
float a[3];
short i0, i1;
a[0] = abs(n[0]);
a[1] = abs(n[1]);
a[2] = abs(n[2]);
if (a[0] > a[1]) {
if (a[0] > a[2]) {
i0 = 1;
i1 = 2;
} else {
i0 = 0;
i1 = 1;
}
} else {
if (a[2] > a[1]) {
i0 = 0;
i1 = 1;
} else {
i0 = 0;
i1 = 2;
}
}
// Test all edges of triangle 1 against edges of triangle 2
float aX = v1[i0] - v0[i0];
float aY = v1[i1] - v0[i1];
float bX = v2[i0] - v1[i0];
float bY = v2[i1] - v1[i1];
float cX = v0[i0] - v2[i0];
float cY = v0[i1] - v2[i1];
if ( edgeEdgeTest(v0, u0, u1, i0, i1, aX, aY) || edgeEdgeTest(v0, u1, u2, i0, i1, aX, aY) || edgeEdgeTest(v0, u2, u0, i0, i1, aX, aY) ||
edgeEdgeTest(v1, u0, u1, i0, i1, bX, bY) || edgeEdgeTest(v1, u1, u2, i0, i1, bX, bY) || edgeEdgeTest(v1, u2, u0, i0, i1, bX, bY) ||
edgeEdgeTest(v2, u0, u1, i0, i1, cX, cY) || edgeEdgeTest(v2, u1, u2, i0, i1, cX, cY) || edgeEdgeTest(v2, u2, u0, i0, i1, cX, cY) )
return true;
// Finally, test if either triangle is totally contained in the other
if (pointInTri(v0, u0, u1, u2, i0, i1) || pointInTri(u0, v0, v1, v2, i0, i1))
return true;
return false;
}
__device__ bool jmeint_kernel_impl(float v0[3], float v1[3], float v2[3], float u0[3], float u1[3], float u2[3])
{
float e1[3], e2[3], n1[3], n2[3], d[3];
float d1, d2;
float du0, du1, du2, dv0, dv1, dv2;
float du0du1, du0du2, dv0dv1, dv0dv2;
float isect1[2];
float isect2[2];
short index;
float vp0, vp1, vp2;
float up0, up1, up2;
float bb, cc, max;
float xx, yy, xxyy, tmp;
// Compute plane equation of triangle (v0,v1,v2)
e1[0] = v1[0] - v0[0];
e1[1] = v1[1] - v0[1];
e1[2] = v1[2] - v0[2];
e2[0] = v2[0] - v0[0];
e2[1] = v2[1] - v0[1];
e2[2] = v2[2] - v0[2];
// Cross product: n1 = e1 x e2
n1[0] = (e1[1] * e2[2]) - (e1[2] * e2[1]);
n1[1] = (e1[2] * e2[0]) - (e1[0] * e2[2]);
n1[2] = (e1[0] * e2[1]) - (e1[1] * e2[0]);
// Plane equation 1: n1.X + d1 = 0
d1 = -(n1[0] * v0[0] + n1[1] * v0[1] + n1[2] * v0[2]);
// Put u0,u1,u2 into plane equation 1 to compute signed distances to the plane
du0 = (n1[0] * u0[0] + n1[1] * u0[1] + n1[2] * u0[2]) + d1;
du1 = (n1[0] * u1[0] + n1[1] * u1[1] + n1[2] * u1[2]) + d1;
du2 = (n1[0] * u2[0] + n1[1] * u2[1] + n1[2] * u2[2]) + d1;
// Coplanarity robustness check
if ((du0 > 0 && du0 < EPSILON) || (du0 < 0 && du0 > EPSILON))
du0 = 0.0f;
if ((du1 > 0 && du1 < EPSILON) || (du1 < 0 && du1 > EPSILON))
du1 = 0.0f;
if ((du2 > 0 && du2 < EPSILON) || (du2 < 0 && du2 > EPSILON))
du2 = 0.0f;
du0du1 = du0 * du1;
du0du2 = du0 * du2;
if (du0du1 > 0.0f && du0du2 > 0.0f) {
// All 3 have same sign and their values are not equal to 0 --> no intersection
return false;
}
// Compute plane equation of triangle (u0,u1,u2)
e1[0] = u1[0] - u0[0];
e1[1] = u1[1] - u0[1];
e1[2] = u1[2] - u0[2];
e2[0] = u2[0] - u0[0];
e2[1] = u2[1] - u0[1];
e2[2] = u2[2] - u0[2];
// Cross product: n2 = e1 x e2
n2[0] = (e1[1] * e2[2]) - (e1[2] * e2[1]);
n2[1] = (e1[2] * e2[0]) - (e1[0] * e2[2]);
n2[2] = (e1[0] * e2[1]) - (e1[1] * e2[0]);
// Plane equation 2: n2.X + d2 = 0
d2 = -(n2[0] * u0[0] + n2[1] * u0[1] + n2[2] * u0[2]);
// Put v0,v1,v2 into plane equation 2 to compute signed distances to the plane
dv0 = (n2[0] * v0[0] + n2[1] * v0[1] + n2[2] * v0[2]) + d2;
dv1 = (n2[0] * v1[0] + n2[1] * v1[1] + n2[2] * v1[2]) + d2;
dv2 = (n2[0] * v2[0] + n2[1] * v2[1] + n2[2] * v2[2]) + d2;
// Coplanarity robustness check
if ((dv0 > 0 && dv0 < EPSILON) || (dv0 < 0 && dv0 > EPSILON))
dv0 = 0.0f;
if ((dv1 > 0 && dv1 < EPSILON) || (dv1 < 0 && dv1 > EPSILON))
dv1 = 0.0f;
if ((dv2 > 0 && dv2 < EPSILON) || (dv2 < 0 && dv2 > EPSILON))
dv2 = 0.0f;
dv0dv1 = dv0 * dv1;
dv0dv2 = dv0 * dv2;
if (dv0dv1 > 0.0f && dv0dv2 > 0.0f) {
// All 3 have same sign and their values are not equal to 0 --> no intersection
return false;
}
// Compute direction of intersection line --> cross product: d = n1 x n2
d[0] = (n1[1] * n2[2]) - (n1[2] * n2[1]);
d[1] = (n1[2] * n2[0]) - (n1[0] * n2[2]);
d[2] = (n1[0] * n2[1]) - (n1[1] * n2[0]);
// Compute and index to the largest component of d
index = 0;
max = abs(d[0]);
bb = abs(d[1]);
cc = abs(d[2]);
if (bb > max) {
max = bb;
index = 1;
}
if (cc > max) {
max = cc;
vp0 = v0[2];
vp1 = v1[2];
vp2 = v2[2];
up0 = u0[2];
up1 = u1[2];
up2 = u2[2];
} else if (index == 1) {
vp0 = v0[1];
vp1 = v1[1];
vp2 = v2[1];
up0 = u0[1];
up1 = u1[1];
up2 = u2[1];
} else {
vp0 = v0[0];
vp1 = v1[0];
vp2 = v2[0];
up0 = u0[0];
up1 = u1[0];
up2 = u2[0];
}
// Compute interval for triangle 1
float abc[3];
float x0x1[2];
if (newComputeIntervals(vp0, vp1, vp2, dv0, dv1, dv2, dv0dv1, dv0dv2, abc, x0x1)) {
return coplanarTriTri(n1, v0, v1, v2, u0, u1, u2);
}
// Compute interval for triangle 2
float def[3];
float y0y1[2];
if (newComputeIntervals(up0, up1, up2, du0, du1, du2, du0du1, du0du2, def, y0y1)) {
return coplanarTriTri(n1, v0, v1, v2, u0, u1, u2);
}
xx = x0x1[0] * x0x1[1];
yy = y0y1[0] * y0y1[1];
xxyy = xx * yy;
tmp = abc[0] * xxyy;
isect1[0] = tmp + abc[1] * x0x1[1] * yy;
isect1[1] = tmp + abc[2] * x0x1[0] * yy;
tmp = def[0] * xxyy;
isect2[0] = tmp + def[1] * xx * y0y1[1];
isect2[1] = tmp + def[2] * xx * y0y1[0];
// Sort isect1 and isect2
if (isect1[0] > isect1[1]) {
float f = isect1[0];
isect1[0] = isect1[1];
isect1[1] = f;
}
if (isect2[0] > isect2[1]) {
float f = isect2[0];
isect2[0] = isect2[1];
isect2[1] = f;
}
if (isect1[1] < isect2[0] || isect2[1] < isect1[0])
{
return false;
}
return true;
}
__global__ void jmeint_kernel(float *v0_d, float *v1_d, float *v2_d, float *u0_d, float*u1_d, float*u2_d, bool* intersect_d, int size)
{
int blockId = blockIdx.x + blockIdx.y * gridDim.x;
int idx = blockId * (blockDim.x * blockDim.y) + (threadIdx.y * blockDim.x) + threadIdx.x;
float v0[3];
float v1[3];
float v2[3];
float u0[3];
float u1[3];
float u2[3];
if(idx < size)
{
v0[0] = v0_d[idx * 3 + 0];
v0[1] = v0_d[idx * 3 + 1];
v0[2] = v0_d[idx * 3 + 2];
v1[0] = v1_d[idx * 3 + 0];
v1[1] = v1_d[idx * 3 + 1];
v1[2] = v1_d[idx * 3 + 2];
v2[0] = v2_d[idx * 3 + 0];
v2[1] = v2_d[idx * 3 + 1];
v2[2] = v2_d[idx * 3 + 2];
u0[0] = u0_d[idx * 3 + 0];
u0[1] = u0_d[idx * 3 + 1];
u0[2] = u0_d[idx * 3 + 2];
u1[0] = u1_d[idx * 3 + 0];
u1[1] = u1_d[idx * 3 + 1];
u1[2] = u1_d[idx * 3 + 2];
u2[0] = u2_d[idx * 3 + 0];
u2[1] = u2_d[idx * 3 + 1];
u2[2] = u2_d[idx * 3 + 2];
#if defined(orig_code)
intersect_d[idx] = jmeint_kernel_impl(v0, v1, v2, u0, u1, u2);
#endif
}
}
int main(int argc, char* argv[])
{
if(argc != 3)
{
std::cerr << "Usage: ./jmeint.out <input file locations> <output file>" << std::endl;
exit(EXIT_FAILURE);
}
float (*v0)[3];
float (*v1)[3];
float (*v2)[3];
float (*u0)[3];
float (*u1)[3];
float (*u2)[3];
bool *intersect;
cudaError_t cudaStatus;
int data_size = 0;
// process the files
ifstream locations_in_file (argv[1]);
ofstream intersect_out_file (argv[2]);
if(locations_in_file.is_open())
{
locations_in_file >> data_size;
std::cout << "# Data Size = " << data_size << std::endl;
}
intersect = new (nothrow) bool[data_size];
// allocate the memory
v0 = new (nothrow) float[data_size][3];
if(v0 == NULL)
{
std::cerr << "Memory allocation fails!!!" << std::endl;
exit(EXIT_FAILURE);
}
// allocate the memory
v1 = new (nothrow) float[data_size][3];
if(v1 == NULL)
{
std::cerr << "Memory allocation fails!!!" << std::endl;
exit(EXIT_FAILURE);
}
// allocate the memory
v2 = new (nothrow) float[data_size][3];
if(v2 == NULL)
{
std::cerr << "Memory allocation fails!!!" << std::endl;
exit(EXIT_FAILURE);
}
// allocate the memory
u0 = new (nothrow) float[data_size][3];
if(u0 == NULL)
{
std::cerr << "Memory allocation fails!!!" << std::endl;
exit(EXIT_FAILURE);
}
// allocate the memory
u1 = new (nothrow) float[data_size][3];
if(u1 == NULL)
{
std::cerr << "Memory allocation fails!!!" << std::endl;
exit(EXIT_FAILURE);
}
// allocate the memory
u2 = new (nothrow) float[data_size][3];
if(u2 == NULL)
{
std::cerr << "Memory allocation fails!!!" << std::endl;
exit(EXIT_FAILURE);
}
// Prepare
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// add data to the arrays
int loc_index = 0;
while(loc_index < data_size)
{
locations_in_file >> v0[loc_index][0] >> v0[loc_index][1] >> v0[loc_index][2]
>> v1[loc_index][0] >> v1[loc_index][1] >> v1[loc_index][2]
>> v2[loc_index][0] >> v2[loc_index][1] >> v2[loc_index][2]
>> u0[loc_index][0] >> u0[loc_index][1] >> u0[loc_index][2]
>> u1[loc_index][0] >> u1[loc_index][1] >> u1[loc_index][2]
>> u2[loc_index][0] >> u2[loc_index][1] >> u2[loc_index][2];
loc_index++;
}
std::cout << "# Coordinates are read from file..." << std::endl;
// memory allocations on the host
float *v0_d;
float *v1_d;
float *v2_d;
float *u0_d;
float *u1_d;
float *u2_d;
bool *intersect_d;
cudaMalloc((void**) &v0_d, data_size * 3 * sizeof(float));
cudaMalloc((void**) &v1_d, data_size * 3 * sizeof(float));
cudaMalloc((void**) &v2_d, data_size * 3 * sizeof(float));
cudaMalloc((void**) &u0_d, data_size * 3 * sizeof(float));
cudaMalloc((void**) &u1_d, data_size * 3 * sizeof(float));
cudaMalloc((void**) &u2_d, data_size * 3 * sizeof(float));
cudaMalloc((void**) &intersect_d, data_size * sizeof(bool));
std::cout << "# Memory allocation on GPU is done..." << std::endl;
cudaMemcpy(v0_d, v0, data_size * 3 * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(v1_d, v1, data_size * 3 * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(v2_d, v2, data_size * 3 * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(u0_d, u0, data_size * 3 * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(u1_d, u1, data_size * 3 * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(u2_d, u2, data_size * 3 * sizeof(float), cudaMemcpyHostToDevice);
std::cout << "# Data are transfered to GPU..." << std::endl;
dim3 dimBlock ( 512, 1 );
dim3 dimGrid ( data_size / 512, 1 );
cudaEventRecord(start, 0);
#pragma parrot.start("jmeint_kernel")
jmeint_kernel<<<dimGrid, dimBlock>>>(v0_d, v1_d, v2_d, u0_d, u1_d, u2_d, intersect_d, data_size);
#pragma parrot.end("jmeint_kernel")
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
std::cout << "Something was wrong! Error code: " << cudaStatus << std::endl;
}
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
std::cout << "# Elapsed Time in `jmeint` kernel = " << elapsedTime << std::endl;
std::cout << "# GPU computation is done ..." << std::endl;
cudaMemcpy(intersect, intersect_d, data_size * sizeof(bool), cudaMemcpyDeviceToHost);
for(int i = 0; i < data_size; i++)
{
intersect_out_file << intersect[i];
intersect_out_file << std::endl;
}
// close files
locations_in_file.close();
intersect_out_file.close();
// de-allocate the memory
delete[] v0;
delete[] v1;
delete[] v2;
delete[] u0;
delete[] u1;
delete[] u2;
delete[] intersect;
// de-allocate cuda memory
cudaFree(v0_d);
cudaFree(v1_d);
cudaFree(v2_d);
cudaFree(u0_d);
cudaFree(u1_d);
cudaFree(u2_d);
cudaFree(intersect_d);
std::cout << "Thank you..." << std::endl;
}
|
code for sm_80
Function : _Z13jmeint_kernelPfS_S_S_S_S_Pbi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
// Designed by: Amir Yazdanbakhsh
// Date: March 26th - 2015
// Alternative Computing Technologies Lab.
// Georgia Institute of Technology
#include "stdlib.h"
#include <fstream>
#include <iostream>
#include <cstddef>
// Cuda Libraries
#include <cuda_runtime_api.h>
#include <cuda.h>
#define EPSILON 1e-12 // EPSILON represents the error buffer used to denote a hit
using namespace std;
__device__ bool newComputeIntervals(float vv0, float vv1, float vv2, float d0, float d1, float d2, float d0d1, float d0d2, float abc[3], float x0x1[2])
{
if (d0d1 > 0.0f) {
// d0d2 <= 0 --> i.e. d0, d1 are on the same side, d2 on the other or on the plane
abc[0] = vv2;
abc[1] = (vv0 - vv2) * d2;
abc[2] = (vv1 - vv2) * d2;
x0x1[0] = d2 - d0;
x0x1[1] = d2 - d1;
} else if (d0d2 > 0.0f) {
// d0d1 <= 0
abc[0] = vv1;
abc[1] = (vv0 - vv1) * d1;
abc[2] = (vv2 - vv1) * d1;
x0x1[0] = d1 - d0;
x0x1[1] = d1 - d2;
} else if (d1 * d2 > 0.0f || d0 != 0.0f) {
// d0d1 <= 0 or d0 != 0
abc[0] = vv0;
abc[1] = (vv1 - vv0) * d0;
abc[2] = (vv2 - vv0) * d0;
x0x1[0] = d0 - d1;
x0x1[1] = d0 - d2;
} else if (d1 != 0.0f) {
abc[0] = vv1;
abc[1] = (vv0 - vv1) * d1;
abc[2] = (vv2 - vv1) * d1;
x0x1[0] = d1 - d0;
x0x1[1] = d1 - d2;
} else if (d2 != 0.0f) {
abc[0] = vv2;
abc[1] = (vv0 - vv2) * d2;
abc[2] = (vv1 - vv2) * d2;
x0x1[0] = d2 - d0;
x0x1[1] = d2 - d1;
} else {
// Triangles are coplanar
return true;
}
return false;
}
__device__ bool edgeEdgeTest(float v0[3], float u0[3], float u1[3], int i0, int i1, float Ax, float Ay)
{
float Bx = u0[i0] - u1[i0];
float By = u0[i1] - u1[i1];
float Cx = v0[i0] - u0[i0];
float Cy = v0[i1] - u0[i1];
float f = Ay * Bx - Ax * By;
float d = By * Cx - Bx * Cy;
if ((f > 0 && d >= 0 && d <= f) || (f < 0 && d <= 0 && d >= f)) {
float e = Ax * Cy - Ay * Cx;
if (f > 0) {
if (e >= 0 && e <= f)
return true;
} else {
if (e <= 0 && e >= f)
return true;
}
}
return false;
}
__device__ bool pointInTri(float V0[3], float U0[3], float U1[3], float U2[3], int i0, int i1)
{
// Check if V0 is inside triangle (U0,U1,U2)
float a, b, c, d0, d1, d2;
a = U1[i1] - U0[i1];
b = -(U1[i0] - U0[i0]);
c = -a * U0[i0] - b * U0[i1];
d0 = a * V0[i0] + b * V0[i1] + c;
a = U2[i1] - U1[i1];
b = -(U2[i0] - U1[i0]);
c = -a * U1[i0] - b * U1[i1];
d1 = a * V0[i0] + b * V0[i1] + c;
a = U0[i1] - U2[i1];
b = -(U0[i0] - U2[i0]);
c = -a * U2[i0] - b * U2[i1];
d2 = a * V0[i0] + b * V0[i1] + c;
if ((d0 * d1) > 0.0 && (d0 * d2) > 0.0)
return true;
return false;
}
__device__ bool coplanarTriTri(float n[3], float v0[3], float v1[3], float v2[3], float u0[3], float u1[3], float u2[3])
{
float a[3];
short i0, i1;
a[0] = abs(n[0]);
a[1] = abs(n[1]);
a[2] = abs(n[2]);
if (a[0] > a[1]) {
if (a[0] > a[2]) {
i0 = 1;
i1 = 2;
} else {
i0 = 0;
i1 = 1;
}
} else {
if (a[2] > a[1]) {
i0 = 0;
i1 = 1;
} else {
i0 = 0;
i1 = 2;
}
}
// Test all edges of triangle 1 against edges of triangle 2
float aX = v1[i0] - v0[i0];
float aY = v1[i1] - v0[i1];
float bX = v2[i0] - v1[i0];
float bY = v2[i1] - v1[i1];
float cX = v0[i0] - v2[i0];
float cY = v0[i1] - v2[i1];
if ( edgeEdgeTest(v0, u0, u1, i0, i1, aX, aY) || edgeEdgeTest(v0, u1, u2, i0, i1, aX, aY) || edgeEdgeTest(v0, u2, u0, i0, i1, aX, aY) ||
edgeEdgeTest(v1, u0, u1, i0, i1, bX, bY) || edgeEdgeTest(v1, u1, u2, i0, i1, bX, bY) || edgeEdgeTest(v1, u2, u0, i0, i1, bX, bY) ||
edgeEdgeTest(v2, u0, u1, i0, i1, cX, cY) || edgeEdgeTest(v2, u1, u2, i0, i1, cX, cY) || edgeEdgeTest(v2, u2, u0, i0, i1, cX, cY) )
return true;
// Finally, test if either triangle is totally contained in the other
if (pointInTri(v0, u0, u1, u2, i0, i1) || pointInTri(u0, v0, v1, v2, i0, i1))
return true;
return false;
}
__device__ bool jmeint_kernel_impl(float v0[3], float v1[3], float v2[3], float u0[3], float u1[3], float u2[3])
{
float e1[3], e2[3], n1[3], n2[3], d[3];
float d1, d2;
float du0, du1, du2, dv0, dv1, dv2;
float du0du1, du0du2, dv0dv1, dv0dv2;
float isect1[2];
float isect2[2];
short index;
float vp0, vp1, vp2;
float up0, up1, up2;
float bb, cc, max;
float xx, yy, xxyy, tmp;
// Compute plane equation of triangle (v0,v1,v2)
e1[0] = v1[0] - v0[0];
e1[1] = v1[1] - v0[1];
e1[2] = v1[2] - v0[2];
e2[0] = v2[0] - v0[0];
e2[1] = v2[1] - v0[1];
e2[2] = v2[2] - v0[2];
// Cross product: n1 = e1 x e2
n1[0] = (e1[1] * e2[2]) - (e1[2] * e2[1]);
n1[1] = (e1[2] * e2[0]) - (e1[0] * e2[2]);
n1[2] = (e1[0] * e2[1]) - (e1[1] * e2[0]);
// Plane equation 1: n1.X + d1 = 0
d1 = -(n1[0] * v0[0] + n1[1] * v0[1] + n1[2] * v0[2]);
// Put u0,u1,u2 into plane equation 1 to compute signed distances to the plane
du0 = (n1[0] * u0[0] + n1[1] * u0[1] + n1[2] * u0[2]) + d1;
du1 = (n1[0] * u1[0] + n1[1] * u1[1] + n1[2] * u1[2]) + d1;
du2 = (n1[0] * u2[0] + n1[1] * u2[1] + n1[2] * u2[2]) + d1;
// Coplanarity robustness check
if ((du0 > 0 && du0 < EPSILON) || (du0 < 0 && du0 > EPSILON))
du0 = 0.0f;
if ((du1 > 0 && du1 < EPSILON) || (du1 < 0 && du1 > EPSILON))
du1 = 0.0f;
if ((du2 > 0 && du2 < EPSILON) || (du2 < 0 && du2 > EPSILON))
du2 = 0.0f;
du0du1 = du0 * du1;
du0du2 = du0 * du2;
if (du0du1 > 0.0f && du0du2 > 0.0f) {
// All 3 have same sign and their values are not equal to 0 --> no intersection
return false;
}
// Compute plane equation of triangle (u0,u1,u2)
e1[0] = u1[0] - u0[0];
e1[1] = u1[1] - u0[1];
e1[2] = u1[2] - u0[2];
e2[0] = u2[0] - u0[0];
e2[1] = u2[1] - u0[1];
e2[2] = u2[2] - u0[2];
// Cross product: n2 = e1 x e2
n2[0] = (e1[1] * e2[2]) - (e1[2] * e2[1]);
n2[1] = (e1[2] * e2[0]) - (e1[0] * e2[2]);
n2[2] = (e1[0] * e2[1]) - (e1[1] * e2[0]);
// Plane equation 2: n2.X + d2 = 0
d2 = -(n2[0] * u0[0] + n2[1] * u0[1] + n2[2] * u0[2]);
// Put v0,v1,v2 into plane equation 2 to compute signed distances to the plane
dv0 = (n2[0] * v0[0] + n2[1] * v0[1] + n2[2] * v0[2]) + d2;
dv1 = (n2[0] * v1[0] + n2[1] * v1[1] + n2[2] * v1[2]) + d2;
dv2 = (n2[0] * v2[0] + n2[1] * v2[1] + n2[2] * v2[2]) + d2;
// Coplanarity robustness check
if ((dv0 > 0 && dv0 < EPSILON) || (dv0 < 0 && dv0 > EPSILON))
dv0 = 0.0f;
if ((dv1 > 0 && dv1 < EPSILON) || (dv1 < 0 && dv1 > EPSILON))
dv1 = 0.0f;
if ((dv2 > 0 && dv2 < EPSILON) || (dv2 < 0 && dv2 > EPSILON))
dv2 = 0.0f;
dv0dv1 = dv0 * dv1;
dv0dv2 = dv0 * dv2;
if (dv0dv1 > 0.0f && dv0dv2 > 0.0f) {
// All 3 have same sign and their values are not equal to 0 --> no intersection
return false;
}
// Compute direction of intersection line --> cross product: d = n1 x n2
d[0] = (n1[1] * n2[2]) - (n1[2] * n2[1]);
d[1] = (n1[2] * n2[0]) - (n1[0] * n2[2]);
d[2] = (n1[0] * n2[1]) - (n1[1] * n2[0]);
// Compute and index to the largest component of d
index = 0;
max = abs(d[0]);
bb = abs(d[1]);
cc = abs(d[2]);
if (bb > max) {
max = bb;
index = 1;
}
if (cc > max) {
max = cc;
vp0 = v0[2];
vp1 = v1[2];
vp2 = v2[2];
up0 = u0[2];
up1 = u1[2];
up2 = u2[2];
} else if (index == 1) {
vp0 = v0[1];
vp1 = v1[1];
vp2 = v2[1];
up0 = u0[1];
up1 = u1[1];
up2 = u2[1];
} else {
vp0 = v0[0];
vp1 = v1[0];
vp2 = v2[0];
up0 = u0[0];
up1 = u1[0];
up2 = u2[0];
}
// Compute interval for triangle 1
float abc[3];
float x0x1[2];
if (newComputeIntervals(vp0, vp1, vp2, dv0, dv1, dv2, dv0dv1, dv0dv2, abc, x0x1)) {
return coplanarTriTri(n1, v0, v1, v2, u0, u1, u2);
}
// Compute interval for triangle 2
float def[3];
float y0y1[2];
if (newComputeIntervals(up0, up1, up2, du0, du1, du2, du0du1, du0du2, def, y0y1)) {
return coplanarTriTri(n1, v0, v1, v2, u0, u1, u2);
}
xx = x0x1[0] * x0x1[1];
yy = y0y1[0] * y0y1[1];
xxyy = xx * yy;
tmp = abc[0] * xxyy;
isect1[0] = tmp + abc[1] * x0x1[1] * yy;
isect1[1] = tmp + abc[2] * x0x1[0] * yy;
tmp = def[0] * xxyy;
isect2[0] = tmp + def[1] * xx * y0y1[1];
isect2[1] = tmp + def[2] * xx * y0y1[0];
// Sort isect1 and isect2
if (isect1[0] > isect1[1]) {
float f = isect1[0];
isect1[0] = isect1[1];
isect1[1] = f;
}
if (isect2[0] > isect2[1]) {
float f = isect2[0];
isect2[0] = isect2[1];
isect2[1] = f;
}
if (isect1[1] < isect2[0] || isect2[1] < isect1[0])
{
return false;
}
return true;
}
__global__ void jmeint_kernel(float *v0_d, float *v1_d, float *v2_d, float *u0_d, float*u1_d, float*u2_d, bool* intersect_d, int size)
{
int blockId = blockIdx.x + blockIdx.y * gridDim.x;
int idx = blockId * (blockDim.x * blockDim.y) + (threadIdx.y * blockDim.x) + threadIdx.x;
float v0[3];
float v1[3];
float v2[3];
float u0[3];
float u1[3];
float u2[3];
if(idx < size)
{
v0[0] = v0_d[idx * 3 + 0];
v0[1] = v0_d[idx * 3 + 1];
v0[2] = v0_d[idx * 3 + 2];
v1[0] = v1_d[idx * 3 + 0];
v1[1] = v1_d[idx * 3 + 1];
v1[2] = v1_d[idx * 3 + 2];
v2[0] = v2_d[idx * 3 + 0];
v2[1] = v2_d[idx * 3 + 1];
v2[2] = v2_d[idx * 3 + 2];
u0[0] = u0_d[idx * 3 + 0];
u0[1] = u0_d[idx * 3 + 1];
u0[2] = u0_d[idx * 3 + 2];
u1[0] = u1_d[idx * 3 + 0];
u1[1] = u1_d[idx * 3 + 1];
u1[2] = u1_d[idx * 3 + 2];
u2[0] = u2_d[idx * 3 + 0];
u2[1] = u2_d[idx * 3 + 1];
u2[2] = u2_d[idx * 3 + 2];
#if defined(orig_code)
intersect_d[idx] = jmeint_kernel_impl(v0, v1, v2, u0, u1, u2);
#endif
}
}
int main(int argc, char* argv[])
{
if(argc != 3)
{
std::cerr << "Usage: ./jmeint.out <input file locations> <output file>" << std::endl;
exit(EXIT_FAILURE);
}
float (*v0)[3];
float (*v1)[3];
float (*v2)[3];
float (*u0)[3];
float (*u1)[3];
float (*u2)[3];
bool *intersect;
cudaError_t cudaStatus;
int data_size = 0;
// process the files
ifstream locations_in_file (argv[1]);
ofstream intersect_out_file (argv[2]);
if(locations_in_file.is_open())
{
locations_in_file >> data_size;
std::cout << "# Data Size = " << data_size << std::endl;
}
intersect = new (nothrow) bool[data_size];
// allocate the memory
v0 = new (nothrow) float[data_size][3];
if(v0 == NULL)
{
std::cerr << "Memory allocation fails!!!" << std::endl;
exit(EXIT_FAILURE);
}
// allocate the memory
v1 = new (nothrow) float[data_size][3];
if(v1 == NULL)
{
std::cerr << "Memory allocation fails!!!" << std::endl;
exit(EXIT_FAILURE);
}
// allocate the memory
v2 = new (nothrow) float[data_size][3];
if(v2 == NULL)
{
std::cerr << "Memory allocation fails!!!" << std::endl;
exit(EXIT_FAILURE);
}
// allocate the memory
u0 = new (nothrow) float[data_size][3];
if(u0 == NULL)
{
std::cerr << "Memory allocation fails!!!" << std::endl;
exit(EXIT_FAILURE);
}
// allocate the memory
u1 = new (nothrow) float[data_size][3];
if(u1 == NULL)
{
std::cerr << "Memory allocation fails!!!" << std::endl;
exit(EXIT_FAILURE);
}
// allocate the memory
u2 = new (nothrow) float[data_size][3];
if(u2 == NULL)
{
std::cerr << "Memory allocation fails!!!" << std::endl;
exit(EXIT_FAILURE);
}
// Prepare
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// add data to the arrays
int loc_index = 0;
while(loc_index < data_size)
{
locations_in_file >> v0[loc_index][0] >> v0[loc_index][1] >> v0[loc_index][2]
>> v1[loc_index][0] >> v1[loc_index][1] >> v1[loc_index][2]
>> v2[loc_index][0] >> v2[loc_index][1] >> v2[loc_index][2]
>> u0[loc_index][0] >> u0[loc_index][1] >> u0[loc_index][2]
>> u1[loc_index][0] >> u1[loc_index][1] >> u1[loc_index][2]
>> u2[loc_index][0] >> u2[loc_index][1] >> u2[loc_index][2];
loc_index++;
}
std::cout << "# Coordinates are read from file..." << std::endl;
// memory allocations on the host
float *v0_d;
float *v1_d;
float *v2_d;
float *u0_d;
float *u1_d;
float *u2_d;
bool *intersect_d;
cudaMalloc((void**) &v0_d, data_size * 3 * sizeof(float));
cudaMalloc((void**) &v1_d, data_size * 3 * sizeof(float));
cudaMalloc((void**) &v2_d, data_size * 3 * sizeof(float));
cudaMalloc((void**) &u0_d, data_size * 3 * sizeof(float));
cudaMalloc((void**) &u1_d, data_size * 3 * sizeof(float));
cudaMalloc((void**) &u2_d, data_size * 3 * sizeof(float));
cudaMalloc((void**) &intersect_d, data_size * sizeof(bool));
std::cout << "# Memory allocation on GPU is done..." << std::endl;
cudaMemcpy(v0_d, v0, data_size * 3 * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(v1_d, v1, data_size * 3 * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(v2_d, v2, data_size * 3 * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(u0_d, u0, data_size * 3 * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(u1_d, u1, data_size * 3 * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(u2_d, u2, data_size * 3 * sizeof(float), cudaMemcpyHostToDevice);
std::cout << "# Data are transfered to GPU..." << std::endl;
dim3 dimBlock ( 512, 1 );
dim3 dimGrid ( data_size / 512, 1 );
cudaEventRecord(start, 0);
#pragma parrot.start("jmeint_kernel")
jmeint_kernel<<<dimGrid, dimBlock>>>(v0_d, v1_d, v2_d, u0_d, u1_d, u2_d, intersect_d, data_size);
#pragma parrot.end("jmeint_kernel")
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
std::cout << "Something was wrong! Error code: " << cudaStatus << std::endl;
}
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
std::cout << "# Elapsed Time in `jmeint` kernel = " << elapsedTime << std::endl;
std::cout << "# GPU computation is done ..." << std::endl;
cudaMemcpy(intersect, intersect_d, data_size * sizeof(bool), cudaMemcpyDeviceToHost);
for(int i = 0; i < data_size; i++)
{
intersect_out_file << intersect[i];
intersect_out_file << std::endl;
}
// close files
locations_in_file.close();
intersect_out_file.close();
// de-allocate the memory
delete[] v0;
delete[] v1;
delete[] v2;
delete[] u0;
delete[] u1;
delete[] u2;
delete[] intersect;
// de-allocate cuda memory
cudaFree(v0_d);
cudaFree(v1_d);
cudaFree(v2_d);
cudaFree(u0_d);
cudaFree(u1_d);
cudaFree(u2_d);
cudaFree(intersect_d);
std::cout << "Thank you..." << std::endl;
}
|
.file "tmpxft_0013a166_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3808:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3808:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z19newComputeIntervalsffffffffPfS_
.type _Z19newComputeIntervalsffffffffPfS_, @function
_Z19newComputeIntervalsffffffffPfS_:
.LFB3800:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3800:
.size _Z19newComputeIntervalsffffffffPfS_, .-_Z19newComputeIntervalsffffffffPfS_
.globl _Z12edgeEdgeTestPfS_S_iiff
.type _Z12edgeEdgeTestPfS_S_iiff, @function
_Z12edgeEdgeTestPfS_S_iiff:
.LFB3801:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3801:
.size _Z12edgeEdgeTestPfS_S_iiff, .-_Z12edgeEdgeTestPfS_S_iiff
.globl _Z10pointInTriPfS_S_S_ii
.type _Z10pointInTriPfS_S_S_ii, @function
_Z10pointInTriPfS_S_S_ii:
.LFB3802:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3802:
.size _Z10pointInTriPfS_S_S_ii, .-_Z10pointInTriPfS_S_S_ii
.globl _Z14coplanarTriTriPfS_S_S_S_S_S_
.type _Z14coplanarTriTriPfS_S_S_S_S_S_, @function
_Z14coplanarTriTriPfS_S_S_S_S_S_:
.LFB3803:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3803:
.size _Z14coplanarTriTriPfS_S_S_S_S_S_, .-_Z14coplanarTriTriPfS_S_S_S_S_S_
.globl _Z18jmeint_kernel_implPfS_S_S_S_S_
.type _Z18jmeint_kernel_implPfS_S_S_S_S_, @function
_Z18jmeint_kernel_implPfS_S_S_S_S_:
.LFB3804:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3804:
.size _Z18jmeint_kernel_implPfS_S_S_S_S_, .-_Z18jmeint_kernel_implPfS_S_S_S_S_
.globl _Z46__device_stub__Z13jmeint_kernelPfS_S_S_S_S_PbiPfS_S_S_S_S_Pbi
.type _Z46__device_stub__Z13jmeint_kernelPfS_S_S_S_S_PbiPfS_S_S_S_S_Pbi, @function
_Z46__device_stub__Z13jmeint_kernelPfS_S_S_S_S_PbiPfS_S_S_S_S_Pbi:
.LFB3830:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 224(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 232(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z13jmeint_kernelPfS_S_S_S_S_Pbi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3830:
.size _Z46__device_stub__Z13jmeint_kernelPfS_S_S_S_S_PbiPfS_S_S_S_S_Pbi, .-_Z46__device_stub__Z13jmeint_kernelPfS_S_S_S_S_PbiPfS_S_S_S_S_Pbi
.globl _Z13jmeint_kernelPfS_S_S_S_S_Pbi
.type _Z13jmeint_kernelPfS_S_S_S_S_Pbi, @function
_Z13jmeint_kernelPfS_S_S_S_S_Pbi:
.LFB3831:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z46__device_stub__Z13jmeint_kernelPfS_S_S_S_S_PbiPfS_S_S_S_S_Pbi
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3831:
.size _Z13jmeint_kernelPfS_S_S_S_S_Pbi, .-_Z13jmeint_kernelPfS_S_S_S_S_Pbi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z13jmeint_kernelPfS_S_S_S_S_Pbi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3833:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13jmeint_kernelPfS_S_S_S_S_Pbi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3833:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.8
.align 8
.LC1:
.string "Usage: ./jmeint.out <input file locations> <output file>"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "# Data Size = "
.LC3:
.string "Memory allocation fails!!!"
.section .rodata.str1.8
.align 8
.LC4:
.string "# Coordinates are read from file..."
.align 8
.LC5:
.string "# Memory allocation on GPU is done..."
.align 8
.LC6:
.string "# Data are transfered to GPU..."
.align 8
.LC7:
.string "Something was wrong! Error code: "
.align 8
.LC8:
.string "# Elapsed Time in `jmeint` kernel = "
.section .rodata.str1.1
.LC9:
.string "# GPU computation is done ..."
.LC10:
.string "Thank you..."
.text
.globl main
.type main, @function
main:
.LFB3805:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3805
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $1224, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
cmpl $3, %edi
jne .L77
movq %rsi, %rbx
movl $0, -1192(%rbp)
movq 8(%rsi), %rsi
leaq -576(%rbp), %rdi
movl $8, %edx
.LEHB0:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE0:
movq 16(%rbx), %rsi
leaq -1088(%rbp), %rdi
movl $16, %edx
.LEHB1:
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE1:
jmp .L78
.L77:
leaq .LC1(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
.LEHB2:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE2:
movl $1, %edi
call exit@PLT
.L78:
leaq -456(%rbp), %rdi
call _ZNKSt12__basic_fileIcE7is_openEv@PLT
testb %al, %al
je .L25
leaq -1192(%rbp), %rsi
leaq -576(%rbp), %rdi
.LEHB3:
call _ZNSirsERi@PLT
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl -1192(%rbp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L25:
movslq -1192(%rbp), %rdi
leaq _ZSt7nothrow(%rip), %rsi
call _ZnamRKSt9nothrow_t@PLT
movq %rax, -1248(%rbp)
movslq -1192(%rbp), %rax
movabsq $768614336404564650, %rdx
cmpq %rax, %rdx
jb .L26
leaq (%rax,%rax,2), %rdi
salq $2, %rdi
leaq _ZSt7nothrow(%rip), %rsi
call _ZnamRKSt9nothrow_t@PLT
movq %rax, %r15
testq %rax, %rax
je .L79
movslq -1192(%rbp), %rax
movabsq $768614336404564650, %rdx
cmpq %rax, %rdx
jb .L30
leaq (%rax,%rax,2), %rdi
salq $2, %rdi
leaq _ZSt7nothrow(%rip), %rsi
call _ZnamRKSt9nothrow_t@PLT
movq %rax, %r14
testq %rax, %rax
je .L80
movslq -1192(%rbp), %rax
movabsq $768614336404564650, %rdx
cmpq %rax, %rdx
jb .L34
leaq (%rax,%rax,2), %rdi
salq $2, %rdi
leaq _ZSt7nothrow(%rip), %rsi
call _ZnamRKSt9nothrow_t@PLT
movq %rax, %r13
testq %rax, %rax
je .L81
movslq -1192(%rbp), %rax
movabsq $768614336404564650, %rdx
cmpq %rax, %rdx
jb .L38
leaq (%rax,%rax,2), %rdi
salq $2, %rdi
leaq _ZSt7nothrow(%rip), %rsi
call _ZnamRKSt9nothrow_t@PLT
movq %rax, -1216(%rbp)
testq %rax, %rax
je .L82
movslq -1192(%rbp), %rax
movabsq $768614336404564650, %rdx
cmpq %rax, %rdx
jb .L42
leaq (%rax,%rax,2), %rdi
salq $2, %rdi
leaq _ZSt7nothrow(%rip), %rsi
call _ZnamRKSt9nothrow_t@PLT
movq %rax, -1224(%rbp)
testq %rax, %rax
je .L83
movslq -1192(%rbp), %rax
movabsq $768614336404564650, %rdx
cmpq %rax, %rdx
jb .L46
leaq (%rax,%rax,2), %rdi
salq $2, %rdi
leaq _ZSt7nothrow(%rip), %rsi
call _ZnamRKSt9nothrow_t@PLT
movq %rax, -1232(%rbp)
testq %rax, %rax
je .L84
leaq -1184(%rbp), %rdi
call cudaEventCreate@PLT
jmp .L85
.L26:
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L29
call __stack_chk_fail@PLT
.L29:
call __cxa_throw_bad_array_new_length@PLT
.L79:
leaq .LC3(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L30:
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L33
call __stack_chk_fail@PLT
.L33:
call __cxa_throw_bad_array_new_length@PLT
.L80:
leaq .LC3(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L34:
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L37
call __stack_chk_fail@PLT
.L37:
call __cxa_throw_bad_array_new_length@PLT
.L81:
leaq .LC3(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L38:
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L41
call __stack_chk_fail@PLT
.L41:
call __cxa_throw_bad_array_new_length@PLT
.L82:
leaq .LC3(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L42:
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L45
call __stack_chk_fail@PLT
.L45:
call __cxa_throw_bad_array_new_length@PLT
.L83:
leaq .LC3(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L46:
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L49
call __stack_chk_fail@PLT
.L49:
call __cxa_throw_bad_array_new_length@PLT
.L84:
leaq .LC3(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L85:
leaq -1176(%rbp), %rdi
call cudaEventCreate@PLT
cmpl $0, -1192(%rbp)
jle .L50
movl $4, %ebx
movq $8, -1208(%rbp)
movl $0, %r12d
movl $0, -1236(%rbp)
leaq -576(%rbp), %rax
movq %rax, -1256(%rbp)
jmp .L51
.L86:
movq %rax, %rdi
leaq (%r15,%rbx), %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
movq %rax, %rdi
movq -1208(%rbp), %rax
leaq (%r15,%rax), %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
movq %rax, %rdi
leaq (%r12,%r14), %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
movq %rax, %rdi
leaq (%r14,%rbx), %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
movq %rax, %rdi
movq -1208(%rbp), %rax
leaq (%r14,%rax), %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
movq %rax, %rdi
leaq (%r12,%r13), %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
movq %rax, %rdi
leaq 0(%r13,%rbx), %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
movq %rax, %rdi
movq -1208(%rbp), %rax
leaq 0(%r13,%rax), %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
movq %rax, %rdi
movq -1216(%rbp), %rcx
leaq (%r12,%rcx), %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
movq %rax, %rdi
movq -1216(%rbp), %rcx
leaq (%rcx,%rbx), %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
movq %rax, %rdi
movq -1216(%rbp), %rcx
movq -1208(%rbp), %rax
leaq (%rcx,%rax), %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
movq %rax, %rdi
movq -1224(%rbp), %rcx
leaq (%r12,%rcx), %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
movq %rax, %rdi
movq -1224(%rbp), %rcx
leaq (%rcx,%rbx), %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
movq %rax, %rdi
movq -1224(%rbp), %rcx
movq -1208(%rbp), %rax
leaq (%rcx,%rax), %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
movq %rax, %rdi
movq -1232(%rbp), %rdx
leaq (%r12,%rdx), %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
movq %rax, %rdi
movq -1232(%rbp), %rdx
leaq (%rdx,%rbx), %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
movq %rax, %rdi
movq -1232(%rbp), %rdx
movq -1208(%rbp), %rax
leaq (%rdx,%rax), %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
addl $1, -1236(%rbp)
movl -1236(%rbp), %ecx
addq $12, %r12
addq $12, -1208(%rbp)
addq $12, %rbx
cmpl %ecx, -1192(%rbp)
jle .L50
.L51:
leaq (%r12,%r15), %rsi
movq -1256(%rbp), %rdi
call _ZNSi10_M_extractIfEERSiRT_@PLT
jmp .L86
.L50:
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl -1192(%rbp), %eax
leal (%rax,%rax,2), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq -1168(%rbp), %rdi
call cudaMalloc@PLT
movl -1192(%rbp), %eax
leal (%rax,%rax,2), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq -1160(%rbp), %rdi
call cudaMalloc@PLT
movl -1192(%rbp), %eax
leal (%rax,%rax,2), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq -1152(%rbp), %rdi
call cudaMalloc@PLT
movl -1192(%rbp), %eax
leal (%rax,%rax,2), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq -1144(%rbp), %rdi
call cudaMalloc@PLT
movl -1192(%rbp), %eax
leal (%rax,%rax,2), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq -1136(%rbp), %rdi
call cudaMalloc@PLT
movl -1192(%rbp), %eax
leal (%rax,%rax,2), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq -1128(%rbp), %rdi
call cudaMalloc@PLT
movslq -1192(%rbp), %rsi
leaq -1120(%rbp), %rdi
call cudaMalloc@PLT
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl -1192(%rbp), %eax
leal (%rax,%rax,2), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r15, %rsi
movq -1168(%rbp), %rdi
call cudaMemcpy@PLT
movl -1192(%rbp), %eax
leal (%rax,%rax,2), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r14, %rsi
movq -1160(%rbp), %rdi
call cudaMemcpy@PLT
movl -1192(%rbp), %eax
leal (%rax,%rax,2), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r13, %rsi
movq -1152(%rbp), %rdi
call cudaMemcpy@PLT
movl -1192(%rbp), %eax
leal (%rax,%rax,2), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq -1216(%rbp), %rsi
movq -1144(%rbp), %rdi
call cudaMemcpy@PLT
movl -1192(%rbp), %eax
leal (%rax,%rax,2), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq -1224(%rbp), %rsi
movq -1136(%rbp), %rdi
call cudaMemcpy@PLT
movl -1192(%rbp), %eax
leal (%rax,%rax,2), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq -1232(%rbp), %rsi
movq -1128(%rbp), %rdi
call cudaMemcpy@PLT
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $512, -1112(%rbp)
movl $1, -1108(%rbp)
movl $1, -1104(%rbp)
movl -1192(%rbp), %edx
leal 511(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $9, %eax
movl %eax, -1100(%rbp)
movl $1, -1096(%rbp)
movl $1, -1092(%rbp)
movl $0, %esi
movq -1184(%rbp), %rdi
call cudaEventRecord@PLT
movl -1104(%rbp), %ecx
movl $0, %r9d
movl $0, %r8d
movq -1112(%rbp), %rdx
movq -1100(%rbp), %rdi
movl -1092(%rbp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L52
movl -1192(%rbp), %eax
pushq %rax
pushq -1120(%rbp)
movq -1128(%rbp), %r9
movq -1136(%rbp), %r8
movq -1144(%rbp), %rcx
movq -1152(%rbp), %rdx
movq -1160(%rbp), %rsi
movq -1168(%rbp), %rdi
.cfi_escape 0x2e,0x10
call _Z46__device_stub__Z13jmeint_kernelPfS_S_S_S_S_PbiPfS_S_S_S_S_Pbi
addq $16, %rsp
.L52:
.cfi_escape 0x2e,0
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
je .L53
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L53:
movl $0, %esi
movq -1176(%rbp), %rdi
call cudaEventRecord@PLT
movq -1176(%rbp), %rdi
call cudaEventSynchronize@PLT
leaq -1188(%rbp), %rdi
movq -1176(%rbp), %rdx
movq -1184(%rbp), %rsi
call cudaEventElapsedTime@PLT
movq -1184(%rbp), %rdi
call cudaEventDestroy@PLT
movq -1176(%rbp), %rdi
call cudaEventDestroy@PLT
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd -1188(%rbp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC9(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movslq -1192(%rbp), %rdx
movl $2, %ecx
movq -1120(%rbp), %rsi
movq -1248(%rbp), %rdi
call cudaMemcpy@PLT
cmpl $0, -1192(%rbp)
jle .L54
movq $0, -1208(%rbp)
leaq -1088(%rbp), %r12
jmp .L59
.L90:
movq -1088(%rbp), %rax
movq -24(%rax), %rax
movq -848(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L87
cmpb $0, 56(%rbx)
je .L57
movzbl 67(%rbx), %esi
.L58:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
jmp .L88
.L87:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L89
call _ZSt16__throw_bad_castv@PLT
.L66:
endbr64
movq %rax, %rbx
leaq -1088(%rbp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
.L62:
leaq -576(%rbp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L63
call __stack_chk_fail@PLT
.L89:
call __stack_chk_fail@PLT
.L57:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L58
.L88:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, -1208(%rbp)
movq -1208(%rbp), %rax
cmpl %eax, -1192(%rbp)
jle .L54
.L59:
movq -1248(%rbp), %rax
movq -1208(%rbp), %rbx
movzbl (%rax,%rbx), %esi
movq %r12, %rdi
call _ZNSo9_M_insertIbEERSoT_@PLT
jmp .L90
.L54:
leaq -576(%rbp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv@PLT
leaq -1088(%rbp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
movq %r15, %rdi
call _ZdaPv@PLT
movq %r14, %rdi
call _ZdaPv@PLT
movq %r13, %rdi
call _ZdaPv@PLT
movq -1216(%rbp), %rdi
call _ZdaPv@PLT
movq -1224(%rbp), %rdi
call _ZdaPv@PLT
movq -1232(%rbp), %rdi
call _ZdaPv@PLT
movq -1248(%rbp), %rax
testq %rax, %rax
je .L60
movq %rax, %rdi
call _ZdaPv@PLT
.L60:
movq -1168(%rbp), %rdi
call cudaFree@PLT
movq -1160(%rbp), %rdi
call cudaFree@PLT
movq -1152(%rbp), %rdi
call cudaFree@PLT
movq -1144(%rbp), %rdi
call cudaFree@PLT
movq -1136(%rbp), %rdi
call cudaFree@PLT
movq -1128(%rbp), %rdi
call cudaFree@PLT
movq -1120(%rbp), %rdi
call cudaFree@PLT
leaq .LC10(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE3:
leaq -1088(%rbp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
leaq -576(%rbp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L91
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L65:
.cfi_restore_state
endbr64
movq %rax, %rbx
jmp .L62
.L63:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L91:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3805:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3805:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3805-.LLSDACSB3805
.LLSDACSB3805:
.uleb128 .LEHB0-.LFB3805
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3805
.uleb128 .LEHE1-.LEHB1
.uleb128 .L65-.LFB3805
.uleb128 0
.uleb128 .LEHB2-.LFB3805
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB3805
.uleb128 .LEHE3-.LEHB3
.uleb128 .L66-.LFB3805
.uleb128 0
.uleb128 .LEHB4-.LFB3805
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE3805:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
// Designed by: Amir Yazdanbakhsh
// Date: March 26th - 2015
// Alternative Computing Technologies Lab.
// Georgia Institute of Technology
#include "stdlib.h"
#include <fstream>
#include <iostream>
#include <cstddef>
// Cuda Libraries
#include <cuda_runtime_api.h>
#include <cuda.h>
#define EPSILON 1e-12 // EPSILON represents the error buffer used to denote a hit
using namespace std;
__device__ bool newComputeIntervals(float vv0, float vv1, float vv2, float d0, float d1, float d2, float d0d1, float d0d2, float abc[3], float x0x1[2])
{
if (d0d1 > 0.0f) {
// d0d2 <= 0 --> i.e. d0, d1 are on the same side, d2 on the other or on the plane
abc[0] = vv2;
abc[1] = (vv0 - vv2) * d2;
abc[2] = (vv1 - vv2) * d2;
x0x1[0] = d2 - d0;
x0x1[1] = d2 - d1;
} else if (d0d2 > 0.0f) {
// d0d1 <= 0
abc[0] = vv1;
abc[1] = (vv0 - vv1) * d1;
abc[2] = (vv2 - vv1) * d1;
x0x1[0] = d1 - d0;
x0x1[1] = d1 - d2;
} else if (d1 * d2 > 0.0f || d0 != 0.0f) {
// d0d1 <= 0 or d0 != 0
abc[0] = vv0;
abc[1] = (vv1 - vv0) * d0;
abc[2] = (vv2 - vv0) * d0;
x0x1[0] = d0 - d1;
x0x1[1] = d0 - d2;
} else if (d1 != 0.0f) {
abc[0] = vv1;
abc[1] = (vv0 - vv1) * d1;
abc[2] = (vv2 - vv1) * d1;
x0x1[0] = d1 - d0;
x0x1[1] = d1 - d2;
} else if (d2 != 0.0f) {
abc[0] = vv2;
abc[1] = (vv0 - vv2) * d2;
abc[2] = (vv1 - vv2) * d2;
x0x1[0] = d2 - d0;
x0x1[1] = d2 - d1;
} else {
// Triangles are coplanar
return true;
}
return false;
}
__device__ bool edgeEdgeTest(float v0[3], float u0[3], float u1[3], int i0, int i1, float Ax, float Ay)
{
float Bx = u0[i0] - u1[i0];
float By = u0[i1] - u1[i1];
float Cx = v0[i0] - u0[i0];
float Cy = v0[i1] - u0[i1];
float f = Ay * Bx - Ax * By;
float d = By * Cx - Bx * Cy;
if ((f > 0 && d >= 0 && d <= f) || (f < 0 && d <= 0 && d >= f)) {
float e = Ax * Cy - Ay * Cx;
if (f > 0) {
if (e >= 0 && e <= f)
return true;
} else {
if (e <= 0 && e >= f)
return true;
}
}
return false;
}
__device__ bool pointInTri(float V0[3], float U0[3], float U1[3], float U2[3], int i0, int i1)
{
// Check if V0 is inside triangle (U0,U1,U2)
float a, b, c, d0, d1, d2;
a = U1[i1] - U0[i1];
b = -(U1[i0] - U0[i0]);
c = -a * U0[i0] - b * U0[i1];
d0 = a * V0[i0] + b * V0[i1] + c;
a = U2[i1] - U1[i1];
b = -(U2[i0] - U1[i0]);
c = -a * U1[i0] - b * U1[i1];
d1 = a * V0[i0] + b * V0[i1] + c;
a = U0[i1] - U2[i1];
b = -(U0[i0] - U2[i0]);
c = -a * U2[i0] - b * U2[i1];
d2 = a * V0[i0] + b * V0[i1] + c;
if ((d0 * d1) > 0.0 && (d0 * d2) > 0.0)
return true;
return false;
}
__device__ bool coplanarTriTri(float n[3], float v0[3], float v1[3], float v2[3], float u0[3], float u1[3], float u2[3])
{
float a[3];
short i0, i1;
a[0] = abs(n[0]);
a[1] = abs(n[1]);
a[2] = abs(n[2]);
if (a[0] > a[1]) {
if (a[0] > a[2]) {
i0 = 1;
i1 = 2;
} else {
i0 = 0;
i1 = 1;
}
} else {
if (a[2] > a[1]) {
i0 = 0;
i1 = 1;
} else {
i0 = 0;
i1 = 2;
}
}
// Test all edges of triangle 1 against edges of triangle 2
float aX = v1[i0] - v0[i0];
float aY = v1[i1] - v0[i1];
float bX = v2[i0] - v1[i0];
float bY = v2[i1] - v1[i1];
float cX = v0[i0] - v2[i0];
float cY = v0[i1] - v2[i1];
if ( edgeEdgeTest(v0, u0, u1, i0, i1, aX, aY) || edgeEdgeTest(v0, u1, u2, i0, i1, aX, aY) || edgeEdgeTest(v0, u2, u0, i0, i1, aX, aY) ||
edgeEdgeTest(v1, u0, u1, i0, i1, bX, bY) || edgeEdgeTest(v1, u1, u2, i0, i1, bX, bY) || edgeEdgeTest(v1, u2, u0, i0, i1, bX, bY) ||
edgeEdgeTest(v2, u0, u1, i0, i1, cX, cY) || edgeEdgeTest(v2, u1, u2, i0, i1, cX, cY) || edgeEdgeTest(v2, u2, u0, i0, i1, cX, cY) )
return true;
// Finally, test if either triangle is totally contained in the other
if (pointInTri(v0, u0, u1, u2, i0, i1) || pointInTri(u0, v0, v1, v2, i0, i1))
return true;
return false;
}
__device__ bool jmeint_kernel_impl(float v0[3], float v1[3], float v2[3], float u0[3], float u1[3], float u2[3])
{
float e1[3], e2[3], n1[3], n2[3], d[3];
float d1, d2;
float du0, du1, du2, dv0, dv1, dv2;
float du0du1, du0du2, dv0dv1, dv0dv2;
float isect1[2];
float isect2[2];
short index;
float vp0, vp1, vp2;
float up0, up1, up2;
float bb, cc, max;
float xx, yy, xxyy, tmp;
// Compute plane equation of triangle (v0,v1,v2)
e1[0] = v1[0] - v0[0];
e1[1] = v1[1] - v0[1];
e1[2] = v1[2] - v0[2];
e2[0] = v2[0] - v0[0];
e2[1] = v2[1] - v0[1];
e2[2] = v2[2] - v0[2];
// Cross product: n1 = e1 x e2
n1[0] = (e1[1] * e2[2]) - (e1[2] * e2[1]);
n1[1] = (e1[2] * e2[0]) - (e1[0] * e2[2]);
n1[2] = (e1[0] * e2[1]) - (e1[1] * e2[0]);
// Plane equation 1: n1.X + d1 = 0
d1 = -(n1[0] * v0[0] + n1[1] * v0[1] + n1[2] * v0[2]);
// Put u0,u1,u2 into plane equation 1 to compute signed distances to the plane
du0 = (n1[0] * u0[0] + n1[1] * u0[1] + n1[2] * u0[2]) + d1;
du1 = (n1[0] * u1[0] + n1[1] * u1[1] + n1[2] * u1[2]) + d1;
du2 = (n1[0] * u2[0] + n1[1] * u2[1] + n1[2] * u2[2]) + d1;
// Coplanarity robustness check
if ((du0 > 0 && du0 < EPSILON) || (du0 < 0 && du0 > EPSILON))
du0 = 0.0f;
if ((du1 > 0 && du1 < EPSILON) || (du1 < 0 && du1 > EPSILON))
du1 = 0.0f;
if ((du2 > 0 && du2 < EPSILON) || (du2 < 0 && du2 > EPSILON))
du2 = 0.0f;
du0du1 = du0 * du1;
du0du2 = du0 * du2;
if (du0du1 > 0.0f && du0du2 > 0.0f) {
// All 3 have same sign and their values are not equal to 0 --> no intersection
return false;
}
// Compute plane equation of triangle (u0,u1,u2)
e1[0] = u1[0] - u0[0];
e1[1] = u1[1] - u0[1];
e1[2] = u1[2] - u0[2];
e2[0] = u2[0] - u0[0];
e2[1] = u2[1] - u0[1];
e2[2] = u2[2] - u0[2];
// Cross product: n2 = e1 x e2
n2[0] = (e1[1] * e2[2]) - (e1[2] * e2[1]);
n2[1] = (e1[2] * e2[0]) - (e1[0] * e2[2]);
n2[2] = (e1[0] * e2[1]) - (e1[1] * e2[0]);
// Plane equation 2: n2.X + d2 = 0
d2 = -(n2[0] * u0[0] + n2[1] * u0[1] + n2[2] * u0[2]);
// Put v0,v1,v2 into plane equation 2 to compute signed distances to the plane
dv0 = (n2[0] * v0[0] + n2[1] * v0[1] + n2[2] * v0[2]) + d2;
dv1 = (n2[0] * v1[0] + n2[1] * v1[1] + n2[2] * v1[2]) + d2;
dv2 = (n2[0] * v2[0] + n2[1] * v2[1] + n2[2] * v2[2]) + d2;
// Coplanarity robustness check
if ((dv0 > 0 && dv0 < EPSILON) || (dv0 < 0 && dv0 > EPSILON))
dv0 = 0.0f;
if ((dv1 > 0 && dv1 < EPSILON) || (dv1 < 0 && dv1 > EPSILON))
dv1 = 0.0f;
if ((dv2 > 0 && dv2 < EPSILON) || (dv2 < 0 && dv2 > EPSILON))
dv2 = 0.0f;
dv0dv1 = dv0 * dv1;
dv0dv2 = dv0 * dv2;
if (dv0dv1 > 0.0f && dv0dv2 > 0.0f) {
// All 3 have same sign and their values are not equal to 0 --> no intersection
return false;
}
// Compute direction of intersection line --> cross product: d = n1 x n2
d[0] = (n1[1] * n2[2]) - (n1[2] * n2[1]);
d[1] = (n1[2] * n2[0]) - (n1[0] * n2[2]);
d[2] = (n1[0] * n2[1]) - (n1[1] * n2[0]);
// Compute and index to the largest component of d
index = 0;
max = abs(d[0]);
bb = abs(d[1]);
cc = abs(d[2]);
if (bb > max) {
max = bb;
index = 1;
}
if (cc > max) {
max = cc;
vp0 = v0[2];
vp1 = v1[2];
vp2 = v2[2];
up0 = u0[2];
up1 = u1[2];
up2 = u2[2];
} else if (index == 1) {
vp0 = v0[1];
vp1 = v1[1];
vp2 = v2[1];
up0 = u0[1];
up1 = u1[1];
up2 = u2[1];
} else {
vp0 = v0[0];
vp1 = v1[0];
vp2 = v2[0];
up0 = u0[0];
up1 = u1[0];
up2 = u2[0];
}
// Compute interval for triangle 1
float abc[3];
float x0x1[2];
if (newComputeIntervals(vp0, vp1, vp2, dv0, dv1, dv2, dv0dv1, dv0dv2, abc, x0x1)) {
return coplanarTriTri(n1, v0, v1, v2, u0, u1, u2);
}
// Compute interval for triangle 2
float def[3];
float y0y1[2];
if (newComputeIntervals(up0, up1, up2, du0, du1, du2, du0du1, du0du2, def, y0y1)) {
return coplanarTriTri(n1, v0, v1, v2, u0, u1, u2);
}
xx = x0x1[0] * x0x1[1];
yy = y0y1[0] * y0y1[1];
xxyy = xx * yy;
tmp = abc[0] * xxyy;
isect1[0] = tmp + abc[1] * x0x1[1] * yy;
isect1[1] = tmp + abc[2] * x0x1[0] * yy;
tmp = def[0] * xxyy;
isect2[0] = tmp + def[1] * xx * y0y1[1];
isect2[1] = tmp + def[2] * xx * y0y1[0];
// Sort isect1 and isect2
if (isect1[0] > isect1[1]) {
float f = isect1[0];
isect1[0] = isect1[1];
isect1[1] = f;
}
if (isect2[0] > isect2[1]) {
float f = isect2[0];
isect2[0] = isect2[1];
isect2[1] = f;
}
if (isect1[1] < isect2[0] || isect2[1] < isect1[0])
{
return false;
}
return true;
}
__global__ void jmeint_kernel(float *v0_d, float *v1_d, float *v2_d, float *u0_d, float*u1_d, float*u2_d, bool* intersect_d, int size)
{
int blockId = blockIdx.x + blockIdx.y * gridDim.x;
int idx = blockId * (blockDim.x * blockDim.y) + (threadIdx.y * blockDim.x) + threadIdx.x;
float v0[3];
float v1[3];
float v2[3];
float u0[3];
float u1[3];
float u2[3];
if(idx < size)
{
v0[0] = v0_d[idx * 3 + 0];
v0[1] = v0_d[idx * 3 + 1];
v0[2] = v0_d[idx * 3 + 2];
v1[0] = v1_d[idx * 3 + 0];
v1[1] = v1_d[idx * 3 + 1];
v1[2] = v1_d[idx * 3 + 2];
v2[0] = v2_d[idx * 3 + 0];
v2[1] = v2_d[idx * 3 + 1];
v2[2] = v2_d[idx * 3 + 2];
u0[0] = u0_d[idx * 3 + 0];
u0[1] = u0_d[idx * 3 + 1];
u0[2] = u0_d[idx * 3 + 2];
u1[0] = u1_d[idx * 3 + 0];
u1[1] = u1_d[idx * 3 + 1];
u1[2] = u1_d[idx * 3 + 2];
u2[0] = u2_d[idx * 3 + 0];
u2[1] = u2_d[idx * 3 + 1];
u2[2] = u2_d[idx * 3 + 2];
#if defined(orig_code)
intersect_d[idx] = jmeint_kernel_impl(v0, v1, v2, u0, u1, u2);
#endif
}
}
int main(int argc, char* argv[])
{
if(argc != 3)
{
std::cerr << "Usage: ./jmeint.out <input file locations> <output file>" << std::endl;
exit(EXIT_FAILURE);
}
float (*v0)[3];
float (*v1)[3];
float (*v2)[3];
float (*u0)[3];
float (*u1)[3];
float (*u2)[3];
bool *intersect;
cudaError_t cudaStatus;
int data_size = 0;
// process the files
ifstream locations_in_file (argv[1]);
ofstream intersect_out_file (argv[2]);
if(locations_in_file.is_open())
{
locations_in_file >> data_size;
std::cout << "# Data Size = " << data_size << std::endl;
}
intersect = new (nothrow) bool[data_size];
// allocate the memory
v0 = new (nothrow) float[data_size][3];
if(v0 == NULL)
{
std::cerr << "Memory allocation fails!!!" << std::endl;
exit(EXIT_FAILURE);
}
// allocate the memory
v1 = new (nothrow) float[data_size][3];
if(v1 == NULL)
{
std::cerr << "Memory allocation fails!!!" << std::endl;
exit(EXIT_FAILURE);
}
// allocate the memory
v2 = new (nothrow) float[data_size][3];
if(v2 == NULL)
{
std::cerr << "Memory allocation fails!!!" << std::endl;
exit(EXIT_FAILURE);
}
// allocate the memory
u0 = new (nothrow) float[data_size][3];
if(u0 == NULL)
{
std::cerr << "Memory allocation fails!!!" << std::endl;
exit(EXIT_FAILURE);
}
// allocate the memory
u1 = new (nothrow) float[data_size][3];
if(u1 == NULL)
{
std::cerr << "Memory allocation fails!!!" << std::endl;
exit(EXIT_FAILURE);
}
// allocate the memory
u2 = new (nothrow) float[data_size][3];
if(u2 == NULL)
{
std::cerr << "Memory allocation fails!!!" << std::endl;
exit(EXIT_FAILURE);
}
// Prepare
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// add data to the arrays
int loc_index = 0;
while(loc_index < data_size)
{
locations_in_file >> v0[loc_index][0] >> v0[loc_index][1] >> v0[loc_index][2]
>> v1[loc_index][0] >> v1[loc_index][1] >> v1[loc_index][2]
>> v2[loc_index][0] >> v2[loc_index][1] >> v2[loc_index][2]
>> u0[loc_index][0] >> u0[loc_index][1] >> u0[loc_index][2]
>> u1[loc_index][0] >> u1[loc_index][1] >> u1[loc_index][2]
>> u2[loc_index][0] >> u2[loc_index][1] >> u2[loc_index][2];
loc_index++;
}
std::cout << "# Coordinates are read from file..." << std::endl;
// memory allocations on the host
float *v0_d;
float *v1_d;
float *v2_d;
float *u0_d;
float *u1_d;
float *u2_d;
bool *intersect_d;
cudaMalloc((void**) &v0_d, data_size * 3 * sizeof(float));
cudaMalloc((void**) &v1_d, data_size * 3 * sizeof(float));
cudaMalloc((void**) &v2_d, data_size * 3 * sizeof(float));
cudaMalloc((void**) &u0_d, data_size * 3 * sizeof(float));
cudaMalloc((void**) &u1_d, data_size * 3 * sizeof(float));
cudaMalloc((void**) &u2_d, data_size * 3 * sizeof(float));
cudaMalloc((void**) &intersect_d, data_size * sizeof(bool));
std::cout << "# Memory allocation on GPU is done..." << std::endl;
cudaMemcpy(v0_d, v0, data_size * 3 * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(v1_d, v1, data_size * 3 * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(v2_d, v2, data_size * 3 * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(u0_d, u0, data_size * 3 * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(u1_d, u1, data_size * 3 * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(u2_d, u2, data_size * 3 * sizeof(float), cudaMemcpyHostToDevice);
std::cout << "# Data are transfered to GPU..." << std::endl;
dim3 dimBlock ( 512, 1 );
dim3 dimGrid ( data_size / 512, 1 );
cudaEventRecord(start, 0);
#pragma parrot.start("jmeint_kernel")
jmeint_kernel<<<dimGrid, dimBlock>>>(v0_d, v1_d, v2_d, u0_d, u1_d, u2_d, intersect_d, data_size);
#pragma parrot.end("jmeint_kernel")
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
std::cout << "Something was wrong! Error code: " << cudaStatus << std::endl;
}
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
std::cout << "# Elapsed Time in `jmeint` kernel = " << elapsedTime << std::endl;
std::cout << "# GPU computation is done ..." << std::endl;
cudaMemcpy(intersect, intersect_d, data_size * sizeof(bool), cudaMemcpyDeviceToHost);
for(int i = 0; i < data_size; i++)
{
intersect_out_file << intersect[i];
intersect_out_file << std::endl;
}
// close files
locations_in_file.close();
intersect_out_file.close();
// de-allocate the memory
delete[] v0;
delete[] v1;
delete[] v2;
delete[] u0;
delete[] u1;
delete[] u2;
delete[] intersect;
// de-allocate cuda memory
cudaFree(v0_d);
cudaFree(v1_d);
cudaFree(v2_d);
cudaFree(u0_d);
cudaFree(u1_d);
cudaFree(u2_d);
cudaFree(intersect_d);
std::cout << "Thank you..." << std::endl;
}
|
// Designed by: Amir Yazdanbakhsh
// Date: March 26th - 2015
// Alternative Computing Technologies Lab.
// Georgia Institute of Technology
#include "stdlib.h"
#include <fstream>
#include <iostream>
#include <cstddef>
// Cuda Libraries
#include <hip/hip_runtime_api.h>
#include <hip/hip_runtime.h>
#define EPSILON 1e-12 // EPSILON represents the error buffer used to denote a hit
using namespace std;
__device__ bool newComputeIntervals(float vv0, float vv1, float vv2, float d0, float d1, float d2, float d0d1, float d0d2, float abc[3], float x0x1[2])
{
if (d0d1 > 0.0f) {
// d0d2 <= 0 --> i.e. d0, d1 are on the same side, d2 on the other or on the plane
abc[0] = vv2;
abc[1] = (vv0 - vv2) * d2;
abc[2] = (vv1 - vv2) * d2;
x0x1[0] = d2 - d0;
x0x1[1] = d2 - d1;
} else if (d0d2 > 0.0f) {
// d0d1 <= 0
abc[0] = vv1;
abc[1] = (vv0 - vv1) * d1;
abc[2] = (vv2 - vv1) * d1;
x0x1[0] = d1 - d0;
x0x1[1] = d1 - d2;
} else if (d1 * d2 > 0.0f || d0 != 0.0f) {
// d0d1 <= 0 or d0 != 0
abc[0] = vv0;
abc[1] = (vv1 - vv0) * d0;
abc[2] = (vv2 - vv0) * d0;
x0x1[0] = d0 - d1;
x0x1[1] = d0 - d2;
} else if (d1 != 0.0f) {
abc[0] = vv1;
abc[1] = (vv0 - vv1) * d1;
abc[2] = (vv2 - vv1) * d1;
x0x1[0] = d1 - d0;
x0x1[1] = d1 - d2;
} else if (d2 != 0.0f) {
abc[0] = vv2;
abc[1] = (vv0 - vv2) * d2;
abc[2] = (vv1 - vv2) * d2;
x0x1[0] = d2 - d0;
x0x1[1] = d2 - d1;
} else {
// Triangles are coplanar
return true;
}
return false;
}
__device__ bool edgeEdgeTest(float v0[3], float u0[3], float u1[3], int i0, int i1, float Ax, float Ay)
{
float Bx = u0[i0] - u1[i0];
float By = u0[i1] - u1[i1];
float Cx = v0[i0] - u0[i0];
float Cy = v0[i1] - u0[i1];
float f = Ay * Bx - Ax * By;
float d = By * Cx - Bx * Cy;
if ((f > 0 && d >= 0 && d <= f) || (f < 0 && d <= 0 && d >= f)) {
float e = Ax * Cy - Ay * Cx;
if (f > 0) {
if (e >= 0 && e <= f)
return true;
} else {
if (e <= 0 && e >= f)
return true;
}
}
return false;
}
__device__ bool pointInTri(float V0[3], float U0[3], float U1[3], float U2[3], int i0, int i1)
{
// Check if V0 is inside triangle (U0,U1,U2)
float a, b, c, d0, d1, d2;
a = U1[i1] - U0[i1];
b = -(U1[i0] - U0[i0]);
c = -a * U0[i0] - b * U0[i1];
d0 = a * V0[i0] + b * V0[i1] + c;
a = U2[i1] - U1[i1];
b = -(U2[i0] - U1[i0]);
c = -a * U1[i0] - b * U1[i1];
d1 = a * V0[i0] + b * V0[i1] + c;
a = U0[i1] - U2[i1];
b = -(U0[i0] - U2[i0]);
c = -a * U2[i0] - b * U2[i1];
d2 = a * V0[i0] + b * V0[i1] + c;
if ((d0 * d1) > 0.0 && (d0 * d2) > 0.0)
return true;
return false;
}
__device__ bool coplanarTriTri(float n[3], float v0[3], float v1[3], float v2[3], float u0[3], float u1[3], float u2[3])
{
float a[3];
short i0, i1;
a[0] = abs(n[0]);
a[1] = abs(n[1]);
a[2] = abs(n[2]);
if (a[0] > a[1]) {
if (a[0] > a[2]) {
i0 = 1;
i1 = 2;
} else {
i0 = 0;
i1 = 1;
}
} else {
if (a[2] > a[1]) {
i0 = 0;
i1 = 1;
} else {
i0 = 0;
i1 = 2;
}
}
// Test all edges of triangle 1 against edges of triangle 2
float aX = v1[i0] - v0[i0];
float aY = v1[i1] - v0[i1];
float bX = v2[i0] - v1[i0];
float bY = v2[i1] - v1[i1];
float cX = v0[i0] - v2[i0];
float cY = v0[i1] - v2[i1];
if ( edgeEdgeTest(v0, u0, u1, i0, i1, aX, aY) || edgeEdgeTest(v0, u1, u2, i0, i1, aX, aY) || edgeEdgeTest(v0, u2, u0, i0, i1, aX, aY) ||
edgeEdgeTest(v1, u0, u1, i0, i1, bX, bY) || edgeEdgeTest(v1, u1, u2, i0, i1, bX, bY) || edgeEdgeTest(v1, u2, u0, i0, i1, bX, bY) ||
edgeEdgeTest(v2, u0, u1, i0, i1, cX, cY) || edgeEdgeTest(v2, u1, u2, i0, i1, cX, cY) || edgeEdgeTest(v2, u2, u0, i0, i1, cX, cY) )
return true;
// Finally, test if either triangle is totally contained in the other
if (pointInTri(v0, u0, u1, u2, i0, i1) || pointInTri(u0, v0, v1, v2, i0, i1))
return true;
return false;
}
__device__ bool jmeint_kernel_impl(float v0[3], float v1[3], float v2[3], float u0[3], float u1[3], float u2[3])
{
float e1[3], e2[3], n1[3], n2[3], d[3];
float d1, d2;
float du0, du1, du2, dv0, dv1, dv2;
float du0du1, du0du2, dv0dv1, dv0dv2;
float isect1[2];
float isect2[2];
short index;
float vp0, vp1, vp2;
float up0, up1, up2;
float bb, cc, max;
float xx, yy, xxyy, tmp;
// Compute plane equation of triangle (v0,v1,v2)
e1[0] = v1[0] - v0[0];
e1[1] = v1[1] - v0[1];
e1[2] = v1[2] - v0[2];
e2[0] = v2[0] - v0[0];
e2[1] = v2[1] - v0[1];
e2[2] = v2[2] - v0[2];
// Cross product: n1 = e1 x e2
n1[0] = (e1[1] * e2[2]) - (e1[2] * e2[1]);
n1[1] = (e1[2] * e2[0]) - (e1[0] * e2[2]);
n1[2] = (e1[0] * e2[1]) - (e1[1] * e2[0]);
// Plane equation 1: n1.X + d1 = 0
d1 = -(n1[0] * v0[0] + n1[1] * v0[1] + n1[2] * v0[2]);
// Put u0,u1,u2 into plane equation 1 to compute signed distances to the plane
du0 = (n1[0] * u0[0] + n1[1] * u0[1] + n1[2] * u0[2]) + d1;
du1 = (n1[0] * u1[0] + n1[1] * u1[1] + n1[2] * u1[2]) + d1;
du2 = (n1[0] * u2[0] + n1[1] * u2[1] + n1[2] * u2[2]) + d1;
// Coplanarity robustness check
if ((du0 > 0 && du0 < EPSILON) || (du0 < 0 && du0 > EPSILON))
du0 = 0.0f;
if ((du1 > 0 && du1 < EPSILON) || (du1 < 0 && du1 > EPSILON))
du1 = 0.0f;
if ((du2 > 0 && du2 < EPSILON) || (du2 < 0 && du2 > EPSILON))
du2 = 0.0f;
du0du1 = du0 * du1;
du0du2 = du0 * du2;
if (du0du1 > 0.0f && du0du2 > 0.0f) {
// All 3 have same sign and their values are not equal to 0 --> no intersection
return false;
}
// Compute plane equation of triangle (u0,u1,u2)
e1[0] = u1[0] - u0[0];
e1[1] = u1[1] - u0[1];
e1[2] = u1[2] - u0[2];
e2[0] = u2[0] - u0[0];
e2[1] = u2[1] - u0[1];
e2[2] = u2[2] - u0[2];
// Cross product: n2 = e1 x e2
n2[0] = (e1[1] * e2[2]) - (e1[2] * e2[1]);
n2[1] = (e1[2] * e2[0]) - (e1[0] * e2[2]);
n2[2] = (e1[0] * e2[1]) - (e1[1] * e2[0]);
// Plane equation 2: n2.X + d2 = 0
d2 = -(n2[0] * u0[0] + n2[1] * u0[1] + n2[2] * u0[2]);
// Put v0,v1,v2 into plane equation 2 to compute signed distances to the plane
dv0 = (n2[0] * v0[0] + n2[1] * v0[1] + n2[2] * v0[2]) + d2;
dv1 = (n2[0] * v1[0] + n2[1] * v1[1] + n2[2] * v1[2]) + d2;
dv2 = (n2[0] * v2[0] + n2[1] * v2[1] + n2[2] * v2[2]) + d2;
// Coplanarity robustness check
if ((dv0 > 0 && dv0 < EPSILON) || (dv0 < 0 && dv0 > EPSILON))
dv0 = 0.0f;
if ((dv1 > 0 && dv1 < EPSILON) || (dv1 < 0 && dv1 > EPSILON))
dv1 = 0.0f;
if ((dv2 > 0 && dv2 < EPSILON) || (dv2 < 0 && dv2 > EPSILON))
dv2 = 0.0f;
dv0dv1 = dv0 * dv1;
dv0dv2 = dv0 * dv2;
if (dv0dv1 > 0.0f && dv0dv2 > 0.0f) {
// All 3 have same sign and their values are not equal to 0 --> no intersection
return false;
}
// Compute direction of intersection line --> cross product: d = n1 x n2
d[0] = (n1[1] * n2[2]) - (n1[2] * n2[1]);
d[1] = (n1[2] * n2[0]) - (n1[0] * n2[2]);
d[2] = (n1[0] * n2[1]) - (n1[1] * n2[0]);
// Compute and index to the largest component of d
index = 0;
max = abs(d[0]);
bb = abs(d[1]);
cc = abs(d[2]);
if (bb > max) {
max = bb;
index = 1;
}
if (cc > max) {
max = cc;
vp0 = v0[2];
vp1 = v1[2];
vp2 = v2[2];
up0 = u0[2];
up1 = u1[2];
up2 = u2[2];
} else if (index == 1) {
vp0 = v0[1];
vp1 = v1[1];
vp2 = v2[1];
up0 = u0[1];
up1 = u1[1];
up2 = u2[1];
} else {
vp0 = v0[0];
vp1 = v1[0];
vp2 = v2[0];
up0 = u0[0];
up1 = u1[0];
up2 = u2[0];
}
// Compute interval for triangle 1
float abc[3];
float x0x1[2];
if (newComputeIntervals(vp0, vp1, vp2, dv0, dv1, dv2, dv0dv1, dv0dv2, abc, x0x1)) {
return coplanarTriTri(n1, v0, v1, v2, u0, u1, u2);
}
// Compute interval for triangle 2
float def[3];
float y0y1[2];
if (newComputeIntervals(up0, up1, up2, du0, du1, du2, du0du1, du0du2, def, y0y1)) {
return coplanarTriTri(n1, v0, v1, v2, u0, u1, u2);
}
xx = x0x1[0] * x0x1[1];
yy = y0y1[0] * y0y1[1];
xxyy = xx * yy;
tmp = abc[0] * xxyy;
isect1[0] = tmp + abc[1] * x0x1[1] * yy;
isect1[1] = tmp + abc[2] * x0x1[0] * yy;
tmp = def[0] * xxyy;
isect2[0] = tmp + def[1] * xx * y0y1[1];
isect2[1] = tmp + def[2] * xx * y0y1[0];
// Sort isect1 and isect2
if (isect1[0] > isect1[1]) {
float f = isect1[0];
isect1[0] = isect1[1];
isect1[1] = f;
}
if (isect2[0] > isect2[1]) {
float f = isect2[0];
isect2[0] = isect2[1];
isect2[1] = f;
}
if (isect1[1] < isect2[0] || isect2[1] < isect1[0])
{
return false;
}
return true;
}
__global__ void jmeint_kernel(float *v0_d, float *v1_d, float *v2_d, float *u0_d, float*u1_d, float*u2_d, bool* intersect_d, int size)
{
int blockId = blockIdx.x + blockIdx.y * gridDim.x;
int idx = blockId * (blockDim.x * blockDim.y) + (threadIdx.y * blockDim.x) + threadIdx.x;
float v0[3];
float v1[3];
float v2[3];
float u0[3];
float u1[3];
float u2[3];
if(idx < size)
{
v0[0] = v0_d[idx * 3 + 0];
v0[1] = v0_d[idx * 3 + 1];
v0[2] = v0_d[idx * 3 + 2];
v1[0] = v1_d[idx * 3 + 0];
v1[1] = v1_d[idx * 3 + 1];
v1[2] = v1_d[idx * 3 + 2];
v2[0] = v2_d[idx * 3 + 0];
v2[1] = v2_d[idx * 3 + 1];
v2[2] = v2_d[idx * 3 + 2];
u0[0] = u0_d[idx * 3 + 0];
u0[1] = u0_d[idx * 3 + 1];
u0[2] = u0_d[idx * 3 + 2];
u1[0] = u1_d[idx * 3 + 0];
u1[1] = u1_d[idx * 3 + 1];
u1[2] = u1_d[idx * 3 + 2];
u2[0] = u2_d[idx * 3 + 0];
u2[1] = u2_d[idx * 3 + 1];
u2[2] = u2_d[idx * 3 + 2];
#if defined(orig_code)
intersect_d[idx] = jmeint_kernel_impl(v0, v1, v2, u0, u1, u2);
#endif
}
}
int main(int argc, char* argv[])
{
if(argc != 3)
{
std::cerr << "Usage: ./jmeint.out <input file locations> <output file>" << std::endl;
exit(EXIT_FAILURE);
}
float (*v0)[3];
float (*v1)[3];
float (*v2)[3];
float (*u0)[3];
float (*u1)[3];
float (*u2)[3];
bool *intersect;
hipError_t cudaStatus;
int data_size = 0;
// process the files
ifstream locations_in_file (argv[1]);
ofstream intersect_out_file (argv[2]);
if(locations_in_file.is_open())
{
locations_in_file >> data_size;
std::cout << "# Data Size = " << data_size << std::endl;
}
intersect = new (nothrow) bool[data_size];
// allocate the memory
v0 = new (nothrow) float[data_size][3];
if(v0 == NULL)
{
std::cerr << "Memory allocation fails!!!" << std::endl;
exit(EXIT_FAILURE);
}
// allocate the memory
v1 = new (nothrow) float[data_size][3];
if(v1 == NULL)
{
std::cerr << "Memory allocation fails!!!" << std::endl;
exit(EXIT_FAILURE);
}
// allocate the memory
v2 = new (nothrow) float[data_size][3];
if(v2 == NULL)
{
std::cerr << "Memory allocation fails!!!" << std::endl;
exit(EXIT_FAILURE);
}
// allocate the memory
u0 = new (nothrow) float[data_size][3];
if(u0 == NULL)
{
std::cerr << "Memory allocation fails!!!" << std::endl;
exit(EXIT_FAILURE);
}
// allocate the memory
u1 = new (nothrow) float[data_size][3];
if(u1 == NULL)
{
std::cerr << "Memory allocation fails!!!" << std::endl;
exit(EXIT_FAILURE);
}
// allocate the memory
u2 = new (nothrow) float[data_size][3];
if(u2 == NULL)
{
std::cerr << "Memory allocation fails!!!" << std::endl;
exit(EXIT_FAILURE);
}
// Prepare
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// add data to the arrays
int loc_index = 0;
while(loc_index < data_size)
{
locations_in_file >> v0[loc_index][0] >> v0[loc_index][1] >> v0[loc_index][2]
>> v1[loc_index][0] >> v1[loc_index][1] >> v1[loc_index][2]
>> v2[loc_index][0] >> v2[loc_index][1] >> v2[loc_index][2]
>> u0[loc_index][0] >> u0[loc_index][1] >> u0[loc_index][2]
>> u1[loc_index][0] >> u1[loc_index][1] >> u1[loc_index][2]
>> u2[loc_index][0] >> u2[loc_index][1] >> u2[loc_index][2];
loc_index++;
}
std::cout << "# Coordinates are read from file..." << std::endl;
// memory allocations on the host
float *v0_d;
float *v1_d;
float *v2_d;
float *u0_d;
float *u1_d;
float *u2_d;
bool *intersect_d;
hipMalloc((void**) &v0_d, data_size * 3 * sizeof(float));
hipMalloc((void**) &v1_d, data_size * 3 * sizeof(float));
hipMalloc((void**) &v2_d, data_size * 3 * sizeof(float));
hipMalloc((void**) &u0_d, data_size * 3 * sizeof(float));
hipMalloc((void**) &u1_d, data_size * 3 * sizeof(float));
hipMalloc((void**) &u2_d, data_size * 3 * sizeof(float));
hipMalloc((void**) &intersect_d, data_size * sizeof(bool));
std::cout << "# Memory allocation on GPU is done..." << std::endl;
hipMemcpy(v0_d, v0, data_size * 3 * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(v1_d, v1, data_size * 3 * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(v2_d, v2, data_size * 3 * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(u0_d, u0, data_size * 3 * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(u1_d, u1, data_size * 3 * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(u2_d, u2, data_size * 3 * sizeof(float), hipMemcpyHostToDevice);
std::cout << "# Data are transfered to GPU..." << std::endl;
dim3 dimBlock ( 512, 1 );
dim3 dimGrid ( data_size / 512, 1 );
hipEventRecord(start, 0);
#pragma parrot.start("jmeint_kernel")
jmeint_kernel<<<dimGrid, dimBlock>>>(v0_d, v1_d, v2_d, u0_d, u1_d, u2_d, intersect_d, data_size);
#pragma parrot.end("jmeint_kernel")
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
std::cout << "Something was wrong! Error code: " << cudaStatus << std::endl;
}
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
std::cout << "# Elapsed Time in `jmeint` kernel = " << elapsedTime << std::endl;
std::cout << "# GPU computation is done ..." << std::endl;
hipMemcpy(intersect, intersect_d, data_size * sizeof(bool), hipMemcpyDeviceToHost);
for(int i = 0; i < data_size; i++)
{
intersect_out_file << intersect[i];
intersect_out_file << std::endl;
}
// close files
locations_in_file.close();
intersect_out_file.close();
// de-allocate the memory
delete[] v0;
delete[] v1;
delete[] v2;
delete[] u0;
delete[] u1;
delete[] u2;
delete[] intersect;
// de-allocate cuda memory
hipFree(v0_d);
hipFree(v1_d);
hipFree(v2_d);
hipFree(u0_d);
hipFree(u1_d);
hipFree(u2_d);
hipFree(intersect_d);
std::cout << "Thank you..." << std::endl;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
// Designed by: Amir Yazdanbakhsh
// Date: March 26th - 2015
// Alternative Computing Technologies Lab.
// Georgia Institute of Technology
#include "stdlib.h"
#include <fstream>
#include <iostream>
#include <cstddef>
// Cuda Libraries
#include <hip/hip_runtime_api.h>
#include <hip/hip_runtime.h>
#define EPSILON 1e-12 // EPSILON represents the error buffer used to denote a hit
using namespace std;
__device__ bool newComputeIntervals(float vv0, float vv1, float vv2, float d0, float d1, float d2, float d0d1, float d0d2, float abc[3], float x0x1[2])
{
if (d0d1 > 0.0f) {
// d0d2 <= 0 --> i.e. d0, d1 are on the same side, d2 on the other or on the plane
abc[0] = vv2;
abc[1] = (vv0 - vv2) * d2;
abc[2] = (vv1 - vv2) * d2;
x0x1[0] = d2 - d0;
x0x1[1] = d2 - d1;
} else if (d0d2 > 0.0f) {
// d0d1 <= 0
abc[0] = vv1;
abc[1] = (vv0 - vv1) * d1;
abc[2] = (vv2 - vv1) * d1;
x0x1[0] = d1 - d0;
x0x1[1] = d1 - d2;
} else if (d1 * d2 > 0.0f || d0 != 0.0f) {
// d0d1 <= 0 or d0 != 0
abc[0] = vv0;
abc[1] = (vv1 - vv0) * d0;
abc[2] = (vv2 - vv0) * d0;
x0x1[0] = d0 - d1;
x0x1[1] = d0 - d2;
} else if (d1 != 0.0f) {
abc[0] = vv1;
abc[1] = (vv0 - vv1) * d1;
abc[2] = (vv2 - vv1) * d1;
x0x1[0] = d1 - d0;
x0x1[1] = d1 - d2;
} else if (d2 != 0.0f) {
abc[0] = vv2;
abc[1] = (vv0 - vv2) * d2;
abc[2] = (vv1 - vv2) * d2;
x0x1[0] = d2 - d0;
x0x1[1] = d2 - d1;
} else {
// Triangles are coplanar
return true;
}
return false;
}
__device__ bool edgeEdgeTest(float v0[3], float u0[3], float u1[3], int i0, int i1, float Ax, float Ay)
{
float Bx = u0[i0] - u1[i0];
float By = u0[i1] - u1[i1];
float Cx = v0[i0] - u0[i0];
float Cy = v0[i1] - u0[i1];
float f = Ay * Bx - Ax * By;
float d = By * Cx - Bx * Cy;
if ((f > 0 && d >= 0 && d <= f) || (f < 0 && d <= 0 && d >= f)) {
float e = Ax * Cy - Ay * Cx;
if (f > 0) {
if (e >= 0 && e <= f)
return true;
} else {
if (e <= 0 && e >= f)
return true;
}
}
return false;
}
__device__ bool pointInTri(float V0[3], float U0[3], float U1[3], float U2[3], int i0, int i1)
{
// Check if V0 is inside triangle (U0,U1,U2)
float a, b, c, d0, d1, d2;
a = U1[i1] - U0[i1];
b = -(U1[i0] - U0[i0]);
c = -a * U0[i0] - b * U0[i1];
d0 = a * V0[i0] + b * V0[i1] + c;
a = U2[i1] - U1[i1];
b = -(U2[i0] - U1[i0]);
c = -a * U1[i0] - b * U1[i1];
d1 = a * V0[i0] + b * V0[i1] + c;
a = U0[i1] - U2[i1];
b = -(U0[i0] - U2[i0]);
c = -a * U2[i0] - b * U2[i1];
d2 = a * V0[i0] + b * V0[i1] + c;
if ((d0 * d1) > 0.0 && (d0 * d2) > 0.0)
return true;
return false;
}
__device__ bool coplanarTriTri(float n[3], float v0[3], float v1[3], float v2[3], float u0[3], float u1[3], float u2[3])
{
float a[3];
short i0, i1;
a[0] = abs(n[0]);
a[1] = abs(n[1]);
a[2] = abs(n[2]);
if (a[0] > a[1]) {
if (a[0] > a[2]) {
i0 = 1;
i1 = 2;
} else {
i0 = 0;
i1 = 1;
}
} else {
if (a[2] > a[1]) {
i0 = 0;
i1 = 1;
} else {
i0 = 0;
i1 = 2;
}
}
// Test all edges of triangle 1 against edges of triangle 2
float aX = v1[i0] - v0[i0];
float aY = v1[i1] - v0[i1];
float bX = v2[i0] - v1[i0];
float bY = v2[i1] - v1[i1];
float cX = v0[i0] - v2[i0];
float cY = v0[i1] - v2[i1];
if ( edgeEdgeTest(v0, u0, u1, i0, i1, aX, aY) || edgeEdgeTest(v0, u1, u2, i0, i1, aX, aY) || edgeEdgeTest(v0, u2, u0, i0, i1, aX, aY) ||
edgeEdgeTest(v1, u0, u1, i0, i1, bX, bY) || edgeEdgeTest(v1, u1, u2, i0, i1, bX, bY) || edgeEdgeTest(v1, u2, u0, i0, i1, bX, bY) ||
edgeEdgeTest(v2, u0, u1, i0, i1, cX, cY) || edgeEdgeTest(v2, u1, u2, i0, i1, cX, cY) || edgeEdgeTest(v2, u2, u0, i0, i1, cX, cY) )
return true;
// Finally, test if either triangle is totally contained in the other
if (pointInTri(v0, u0, u1, u2, i0, i1) || pointInTri(u0, v0, v1, v2, i0, i1))
return true;
return false;
}
__device__ bool jmeint_kernel_impl(float v0[3], float v1[3], float v2[3], float u0[3], float u1[3], float u2[3])
{
float e1[3], e2[3], n1[3], n2[3], d[3];
float d1, d2;
float du0, du1, du2, dv0, dv1, dv2;
float du0du1, du0du2, dv0dv1, dv0dv2;
float isect1[2];
float isect2[2];
short index;
float vp0, vp1, vp2;
float up0, up1, up2;
float bb, cc, max;
float xx, yy, xxyy, tmp;
// Compute plane equation of triangle (v0,v1,v2)
e1[0] = v1[0] - v0[0];
e1[1] = v1[1] - v0[1];
e1[2] = v1[2] - v0[2];
e2[0] = v2[0] - v0[0];
e2[1] = v2[1] - v0[1];
e2[2] = v2[2] - v0[2];
// Cross product: n1 = e1 x e2
n1[0] = (e1[1] * e2[2]) - (e1[2] * e2[1]);
n1[1] = (e1[2] * e2[0]) - (e1[0] * e2[2]);
n1[2] = (e1[0] * e2[1]) - (e1[1] * e2[0]);
// Plane equation 1: n1.X + d1 = 0
d1 = -(n1[0] * v0[0] + n1[1] * v0[1] + n1[2] * v0[2]);
// Put u0,u1,u2 into plane equation 1 to compute signed distances to the plane
du0 = (n1[0] * u0[0] + n1[1] * u0[1] + n1[2] * u0[2]) + d1;
du1 = (n1[0] * u1[0] + n1[1] * u1[1] + n1[2] * u1[2]) + d1;
du2 = (n1[0] * u2[0] + n1[1] * u2[1] + n1[2] * u2[2]) + d1;
// Coplanarity robustness check
if ((du0 > 0 && du0 < EPSILON) || (du0 < 0 && du0 > EPSILON))
du0 = 0.0f;
if ((du1 > 0 && du1 < EPSILON) || (du1 < 0 && du1 > EPSILON))
du1 = 0.0f;
if ((du2 > 0 && du2 < EPSILON) || (du2 < 0 && du2 > EPSILON))
du2 = 0.0f;
du0du1 = du0 * du1;
du0du2 = du0 * du2;
if (du0du1 > 0.0f && du0du2 > 0.0f) {
// All 3 have same sign and their values are not equal to 0 --> no intersection
return false;
}
// Compute plane equation of triangle (u0,u1,u2)
e1[0] = u1[0] - u0[0];
e1[1] = u1[1] - u0[1];
e1[2] = u1[2] - u0[2];
e2[0] = u2[0] - u0[0];
e2[1] = u2[1] - u0[1];
e2[2] = u2[2] - u0[2];
// Cross product: n2 = e1 x e2
n2[0] = (e1[1] * e2[2]) - (e1[2] * e2[1]);
n2[1] = (e1[2] * e2[0]) - (e1[0] * e2[2]);
n2[2] = (e1[0] * e2[1]) - (e1[1] * e2[0]);
// Plane equation 2: n2.X + d2 = 0
d2 = -(n2[0] * u0[0] + n2[1] * u0[1] + n2[2] * u0[2]);
// Put v0,v1,v2 into plane equation 2 to compute signed distances to the plane
dv0 = (n2[0] * v0[0] + n2[1] * v0[1] + n2[2] * v0[2]) + d2;
dv1 = (n2[0] * v1[0] + n2[1] * v1[1] + n2[2] * v1[2]) + d2;
dv2 = (n2[0] * v2[0] + n2[1] * v2[1] + n2[2] * v2[2]) + d2;
// Coplanarity robustness check
if ((dv0 > 0 && dv0 < EPSILON) || (dv0 < 0 && dv0 > EPSILON))
dv0 = 0.0f;
if ((dv1 > 0 && dv1 < EPSILON) || (dv1 < 0 && dv1 > EPSILON))
dv1 = 0.0f;
if ((dv2 > 0 && dv2 < EPSILON) || (dv2 < 0 && dv2 > EPSILON))
dv2 = 0.0f;
dv0dv1 = dv0 * dv1;
dv0dv2 = dv0 * dv2;
if (dv0dv1 > 0.0f && dv0dv2 > 0.0f) {
// All 3 have same sign and their values are not equal to 0 --> no intersection
return false;
}
// Compute direction of intersection line --> cross product: d = n1 x n2
d[0] = (n1[1] * n2[2]) - (n1[2] * n2[1]);
d[1] = (n1[2] * n2[0]) - (n1[0] * n2[2]);
d[2] = (n1[0] * n2[1]) - (n1[1] * n2[0]);
// Compute and index to the largest component of d
index = 0;
max = abs(d[0]);
bb = abs(d[1]);
cc = abs(d[2]);
if (bb > max) {
max = bb;
index = 1;
}
if (cc > max) {
max = cc;
vp0 = v0[2];
vp1 = v1[2];
vp2 = v2[2];
up0 = u0[2];
up1 = u1[2];
up2 = u2[2];
} else if (index == 1) {
vp0 = v0[1];
vp1 = v1[1];
vp2 = v2[1];
up0 = u0[1];
up1 = u1[1];
up2 = u2[1];
} else {
vp0 = v0[0];
vp1 = v1[0];
vp2 = v2[0];
up0 = u0[0];
up1 = u1[0];
up2 = u2[0];
}
// Compute interval for triangle 1
float abc[3];
float x0x1[2];
if (newComputeIntervals(vp0, vp1, vp2, dv0, dv1, dv2, dv0dv1, dv0dv2, abc, x0x1)) {
return coplanarTriTri(n1, v0, v1, v2, u0, u1, u2);
}
// Compute interval for triangle 2
float def[3];
float y0y1[2];
if (newComputeIntervals(up0, up1, up2, du0, du1, du2, du0du1, du0du2, def, y0y1)) {
return coplanarTriTri(n1, v0, v1, v2, u0, u1, u2);
}
xx = x0x1[0] * x0x1[1];
yy = y0y1[0] * y0y1[1];
xxyy = xx * yy;
tmp = abc[0] * xxyy;
isect1[0] = tmp + abc[1] * x0x1[1] * yy;
isect1[1] = tmp + abc[2] * x0x1[0] * yy;
tmp = def[0] * xxyy;
isect2[0] = tmp + def[1] * xx * y0y1[1];
isect2[1] = tmp + def[2] * xx * y0y1[0];
// Sort isect1 and isect2
if (isect1[0] > isect1[1]) {
float f = isect1[0];
isect1[0] = isect1[1];
isect1[1] = f;
}
if (isect2[0] > isect2[1]) {
float f = isect2[0];
isect2[0] = isect2[1];
isect2[1] = f;
}
if (isect1[1] < isect2[0] || isect2[1] < isect1[0])
{
return false;
}
return true;
}
__global__ void jmeint_kernel(float *v0_d, float *v1_d, float *v2_d, float *u0_d, float*u1_d, float*u2_d, bool* intersect_d, int size)
{
int blockId = blockIdx.x + blockIdx.y * gridDim.x;
int idx = blockId * (blockDim.x * blockDim.y) + (threadIdx.y * blockDim.x) + threadIdx.x;
float v0[3];
float v1[3];
float v2[3];
float u0[3];
float u1[3];
float u2[3];
if(idx < size)
{
v0[0] = v0_d[idx * 3 + 0];
v0[1] = v0_d[idx * 3 + 1];
v0[2] = v0_d[idx * 3 + 2];
v1[0] = v1_d[idx * 3 + 0];
v1[1] = v1_d[idx * 3 + 1];
v1[2] = v1_d[idx * 3 + 2];
v2[0] = v2_d[idx * 3 + 0];
v2[1] = v2_d[idx * 3 + 1];
v2[2] = v2_d[idx * 3 + 2];
u0[0] = u0_d[idx * 3 + 0];
u0[1] = u0_d[idx * 3 + 1];
u0[2] = u0_d[idx * 3 + 2];
u1[0] = u1_d[idx * 3 + 0];
u1[1] = u1_d[idx * 3 + 1];
u1[2] = u1_d[idx * 3 + 2];
u2[0] = u2_d[idx * 3 + 0];
u2[1] = u2_d[idx * 3 + 1];
u2[2] = u2_d[idx * 3 + 2];
#if defined(orig_code)
intersect_d[idx] = jmeint_kernel_impl(v0, v1, v2, u0, u1, u2);
#endif
}
}
int main(int argc, char* argv[])
{
if(argc != 3)
{
std::cerr << "Usage: ./jmeint.out <input file locations> <output file>" << std::endl;
exit(EXIT_FAILURE);
}
float (*v0)[3];
float (*v1)[3];
float (*v2)[3];
float (*u0)[3];
float (*u1)[3];
float (*u2)[3];
bool *intersect;
hipError_t cudaStatus;
int data_size = 0;
// process the files
ifstream locations_in_file (argv[1]);
ofstream intersect_out_file (argv[2]);
if(locations_in_file.is_open())
{
locations_in_file >> data_size;
std::cout << "# Data Size = " << data_size << std::endl;
}
intersect = new (nothrow) bool[data_size];
// allocate the memory
v0 = new (nothrow) float[data_size][3];
if(v0 == NULL)
{
std::cerr << "Memory allocation fails!!!" << std::endl;
exit(EXIT_FAILURE);
}
// allocate the memory
v1 = new (nothrow) float[data_size][3];
if(v1 == NULL)
{
std::cerr << "Memory allocation fails!!!" << std::endl;
exit(EXIT_FAILURE);
}
// allocate the memory
v2 = new (nothrow) float[data_size][3];
if(v2 == NULL)
{
std::cerr << "Memory allocation fails!!!" << std::endl;
exit(EXIT_FAILURE);
}
// allocate the memory
u0 = new (nothrow) float[data_size][3];
if(u0 == NULL)
{
std::cerr << "Memory allocation fails!!!" << std::endl;
exit(EXIT_FAILURE);
}
// allocate the memory
u1 = new (nothrow) float[data_size][3];
if(u1 == NULL)
{
std::cerr << "Memory allocation fails!!!" << std::endl;
exit(EXIT_FAILURE);
}
// allocate the memory
u2 = new (nothrow) float[data_size][3];
if(u2 == NULL)
{
std::cerr << "Memory allocation fails!!!" << std::endl;
exit(EXIT_FAILURE);
}
// Prepare
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// add data to the arrays
int loc_index = 0;
while(loc_index < data_size)
{
locations_in_file >> v0[loc_index][0] >> v0[loc_index][1] >> v0[loc_index][2]
>> v1[loc_index][0] >> v1[loc_index][1] >> v1[loc_index][2]
>> v2[loc_index][0] >> v2[loc_index][1] >> v2[loc_index][2]
>> u0[loc_index][0] >> u0[loc_index][1] >> u0[loc_index][2]
>> u1[loc_index][0] >> u1[loc_index][1] >> u1[loc_index][2]
>> u2[loc_index][0] >> u2[loc_index][1] >> u2[loc_index][2];
loc_index++;
}
std::cout << "# Coordinates are read from file..." << std::endl;
// memory allocations on the host
float *v0_d;
float *v1_d;
float *v2_d;
float *u0_d;
float *u1_d;
float *u2_d;
bool *intersect_d;
hipMalloc((void**) &v0_d, data_size * 3 * sizeof(float));
hipMalloc((void**) &v1_d, data_size * 3 * sizeof(float));
hipMalloc((void**) &v2_d, data_size * 3 * sizeof(float));
hipMalloc((void**) &u0_d, data_size * 3 * sizeof(float));
hipMalloc((void**) &u1_d, data_size * 3 * sizeof(float));
hipMalloc((void**) &u2_d, data_size * 3 * sizeof(float));
hipMalloc((void**) &intersect_d, data_size * sizeof(bool));
std::cout << "# Memory allocation on GPU is done..." << std::endl;
hipMemcpy(v0_d, v0, data_size * 3 * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(v1_d, v1, data_size * 3 * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(v2_d, v2, data_size * 3 * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(u0_d, u0, data_size * 3 * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(u1_d, u1, data_size * 3 * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(u2_d, u2, data_size * 3 * sizeof(float), hipMemcpyHostToDevice);
std::cout << "# Data are transfered to GPU..." << std::endl;
dim3 dimBlock ( 512, 1 );
dim3 dimGrid ( data_size / 512, 1 );
hipEventRecord(start, 0);
#pragma parrot.start("jmeint_kernel")
jmeint_kernel<<<dimGrid, dimBlock>>>(v0_d, v1_d, v2_d, u0_d, u1_d, u2_d, intersect_d, data_size);
#pragma parrot.end("jmeint_kernel")
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
std::cout << "Something was wrong! Error code: " << cudaStatus << std::endl;
}
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
std::cout << "# Elapsed Time in `jmeint` kernel = " << elapsedTime << std::endl;
std::cout << "# GPU computation is done ..." << std::endl;
hipMemcpy(intersect, intersect_d, data_size * sizeof(bool), hipMemcpyDeviceToHost);
for(int i = 0; i < data_size; i++)
{
intersect_out_file << intersect[i];
intersect_out_file << std::endl;
}
// close files
locations_in_file.close();
intersect_out_file.close();
// de-allocate the memory
delete[] v0;
delete[] v1;
delete[] v2;
delete[] u0;
delete[] u1;
delete[] u2;
delete[] intersect;
// de-allocate cuda memory
hipFree(v0_d);
hipFree(v1_d);
hipFree(v2_d);
hipFree(u0_d);
hipFree(u1_d);
hipFree(u2_d);
hipFree(intersect_d);
std::cout << "Thank you..." << std::endl;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13jmeint_kernelPfS_S_S_S_S_Pbi
.globl _Z13jmeint_kernelPfS_S_S_S_S_Pbi
.p2align 8
.type _Z13jmeint_kernelPfS_S_S_S_S_Pbi,@function
_Z13jmeint_kernelPfS_S_S_S_S_Pbi:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13jmeint_kernelPfS_S_S_S_S_Pbi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 60
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13jmeint_kernelPfS_S_S_S_S_Pbi, .Lfunc_end0-_Z13jmeint_kernelPfS_S_S_S_S_Pbi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 60
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13jmeint_kernelPfS_S_S_S_S_Pbi
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z13jmeint_kernelPfS_S_S_S_S_Pbi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z13jmeint_kernelPfS_S_S_S_S_Pbi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13jmeint_kernelPfS_S_S_S_S_Pbi
.globl _Z13jmeint_kernelPfS_S_S_S_S_Pbi
.p2align 8
.type _Z13jmeint_kernelPfS_S_S_S_S_Pbi,@function
_Z13jmeint_kernelPfS_S_S_S_S_Pbi:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13jmeint_kernelPfS_S_S_S_S_Pbi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 60
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13jmeint_kernelPfS_S_S_S_S_Pbi, .Lfunc_end0-_Z13jmeint_kernelPfS_S_S_S_S_Pbi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 60
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13jmeint_kernelPfS_S_S_S_S_Pbi
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z13jmeint_kernelPfS_S_S_S_S_Pbi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <stdio.h>
#include <stdlib.h>
__global__ void calculate(int *d_buffer){
int ix = blockIdx.x*blockDim.x + threadIdx.x;
d_buffer[ix] += d_buffer[ix];
__syncthreads();
}
__global__ void compute1(int *d_buffer){
int ix = blockIdx.x*blockDim.x + threadIdx.x;
d_buffer[ix] = d_buffer[ix]*2;
__syncthreads();
}
__global__ void compute2(int *d_buffer){
int ix = blockIdx.x*blockDim.x + threadIdx.x;
d_buffer[ix] = d_buffer[ix]*10;
__syncthreads();
}
int main(int argc, char *argv[]){
int *matriz_1,*matriz_2,*h_matriz;
int N,i,j,iter;
int loop;
//dimensão da matriz
N = atoi(argv[1]);
//numero de iterações
iter = atoi(argv[2]);
loop = atoi(argv[3]);
h_matriz = (int*) malloc(sizeof(int)*N*N);
cudaMalloc(&matriz_1,sizeof(int)*N*N);
for(i=0;i<N;i++){
for(j=0;j<N;j++){
h_matriz[i*N+j] = (i*N+j)+1;
}
}
cudaMemcpy(matriz_1,h_matriz,N*N*sizeof(int),cudaMemcpyHostToDevice);
dim3 grid, block;
block.x = 1024;
grid.x = (N + block.x - 1) / block.x;
for(i=0;i<iter;i++){
for(j=0;j<loop;j++){
calculate<<<grid,block>>>(matriz_1);
}
for(j=0;j<loop;j++){
compute1<<<grid,block>>>(matriz_1);
}
for(j=0;j<loop;j++){
compute2<<<grid,block>>>(matriz_1);
}
}
return 0;
}
|
code for sm_80
Function : _Z8compute2Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0080*/ IMAD R5, R0, 0xa, RZ ; /* 0x0000000a00057824 */
/* 0x004fca00078e02ff */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*00a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8compute1Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0080*/ SHF.L.U32 R5, R0, 0x1, RZ ; /* 0x0000000100057819 */
/* 0x004fca00000006ff */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*00a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9calculatePi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0080*/ SHF.L.U32 R5, R0, 0x1, RZ ; /* 0x0000000100057819 */
/* 0x004fca00000006ff */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*00a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
#include <stdlib.h>
__global__ void calculate(int *d_buffer){
int ix = blockIdx.x*blockDim.x + threadIdx.x;
d_buffer[ix] += d_buffer[ix];
__syncthreads();
}
__global__ void compute1(int *d_buffer){
int ix = blockIdx.x*blockDim.x + threadIdx.x;
d_buffer[ix] = d_buffer[ix]*2;
__syncthreads();
}
__global__ void compute2(int *d_buffer){
int ix = blockIdx.x*blockDim.x + threadIdx.x;
d_buffer[ix] = d_buffer[ix]*10;
__syncthreads();
}
int main(int argc, char *argv[]){
int *matriz_1,*matriz_2,*h_matriz;
int N,i,j,iter;
int loop;
//dimensão da matriz
N = atoi(argv[1]);
//numero de iterações
iter = atoi(argv[2]);
loop = atoi(argv[3]);
h_matriz = (int*) malloc(sizeof(int)*N*N);
cudaMalloc(&matriz_1,sizeof(int)*N*N);
for(i=0;i<N;i++){
for(j=0;j<N;j++){
h_matriz[i*N+j] = (i*N+j)+1;
}
}
cudaMemcpy(matriz_1,h_matriz,N*N*sizeof(int),cudaMemcpyHostToDevice);
dim3 grid, block;
block.x = 1024;
grid.x = (N + block.x - 1) / block.x;
for(i=0;i<iter;i++){
for(j=0;j<loop;j++){
calculate<<<grid,block>>>(matriz_1);
}
for(j=0;j<loop;j++){
compute1<<<grid,block>>>(matriz_1);
}
for(j=0;j<loop;j++){
compute2<<<grid,block>>>(matriz_1);
}
}
return 0;
}
|
.file "tmpxft_001204e4_00000000-6_teste.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z9calculatePiPi
.type _Z28__device_stub__Z9calculatePiPi, @function
_Z28__device_stub__Z9calculatePiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9calculatePi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z9calculatePiPi, .-_Z28__device_stub__Z9calculatePiPi
.globl _Z9calculatePi
.type _Z9calculatePi, @function
_Z9calculatePi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z9calculatePiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9calculatePi, .-_Z9calculatePi
.globl _Z27__device_stub__Z8compute1PiPi
.type _Z27__device_stub__Z8compute1PiPi, @function
_Z27__device_stub__Z8compute1PiPi:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8compute1Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z27__device_stub__Z8compute1PiPi, .-_Z27__device_stub__Z8compute1PiPi
.globl _Z8compute1Pi
.type _Z8compute1Pi, @function
_Z8compute1Pi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z8compute1PiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z8compute1Pi, .-_Z8compute1Pi
.globl _Z27__device_stub__Z8compute2PiPi
.type _Z27__device_stub__Z8compute2PiPi, @function
_Z27__device_stub__Z8compute2PiPi:
.LFB2086:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8compute2Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z27__device_stub__Z8compute2PiPi, .-_Z27__device_stub__Z8compute2PiPi
.globl _Z8compute2Pi
.type _Z8compute2Pi, @function
_Z8compute2Pi:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z8compute2PiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z8compute2Pi, .-_Z8compute2Pi
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movl %eax, %r14d
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 8(%rsp)
movl %eax, %r13d
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebx
movslq %r12d, %rbp
movq %rbp, %r15
imulq %rbp, %r15
salq $2, %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, (%rsp)
leaq 24(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
testl %r12d, %r12d
jle .L28
movl %r12d, %r9d
salq $2, %rbp
movq (%rsp), %r8
leal 1(%r12), %ecx
movl $1, %edi
movl $0, %esi
.L29:
movq %r8, %rdx
movl %edi, %eax
.L30:
movl %eax, (%rdx)
addl $1, %eax
addq $4, %rdx
cmpl %ecx, %eax
jne .L30
addl $1, %esi
addl %r9d, %edi
addq %rbp, %r8
addl %r9d, %ecx
cmpl %r14d, %esi
jne .L29
.L28:
movl $1, %ecx
movq %r15, %rdx
movq (%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
addl $1023, %r12d
shrl $10, %r12d
movl %r12d, 32(%rsp)
movl $0, %r12d
cmpl $0, 8(%rsp)
jg .L31
.L32:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L50
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
addl $1, %ebp
cmpl %ebx, %ebp
je .L51
.L34:
movl $1024, 44(%rsp)
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L33
movq 24(%rsp), %rdi
call _Z28__device_stub__Z9calculatePiPi
jmp .L33
.L51:
movl $0, %ebp
jmp .L36
.L35:
addl $1, %ebp
cmpl %ebx, %ebp
je .L52
.L36:
movl $1024, 44(%rsp)
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L35
movq 24(%rsp), %rdi
call _Z27__device_stub__Z8compute1PiPi
jmp .L35
.L52:
movl $0, %ebp
jmp .L38
.L37:
addl $1, %ebp
cmpl %ebx, %ebp
je .L39
.L38:
movl $1024, 44(%rsp)
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L37
movq 24(%rsp), %rdi
call _Z27__device_stub__Z8compute2PiPi
jmp .L37
.L39:
addl $1, %r12d
cmpl %r13d, %r12d
je .L32
.L31:
movl $0, %ebp
testl %ebx, %ebx
jg .L34
jmp .L39
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8compute2Pi"
.LC1:
.string "_Z8compute1Pi"
.LC2:
.string "_Z9calculatePi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8compute2Pi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8compute1Pi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z9calculatePi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
#include <stdlib.h>
__global__ void calculate(int *d_buffer){
int ix = blockIdx.x*blockDim.x + threadIdx.x;
d_buffer[ix] += d_buffer[ix];
__syncthreads();
}
__global__ void compute1(int *d_buffer){
int ix = blockIdx.x*blockDim.x + threadIdx.x;
d_buffer[ix] = d_buffer[ix]*2;
__syncthreads();
}
__global__ void compute2(int *d_buffer){
int ix = blockIdx.x*blockDim.x + threadIdx.x;
d_buffer[ix] = d_buffer[ix]*10;
__syncthreads();
}
int main(int argc, char *argv[]){
int *matriz_1,*matriz_2,*h_matriz;
int N,i,j,iter;
int loop;
//dimensão da matriz
N = atoi(argv[1]);
//numero de iterações
iter = atoi(argv[2]);
loop = atoi(argv[3]);
h_matriz = (int*) malloc(sizeof(int)*N*N);
cudaMalloc(&matriz_1,sizeof(int)*N*N);
for(i=0;i<N;i++){
for(j=0;j<N;j++){
h_matriz[i*N+j] = (i*N+j)+1;
}
}
cudaMemcpy(matriz_1,h_matriz,N*N*sizeof(int),cudaMemcpyHostToDevice);
dim3 grid, block;
block.x = 1024;
grid.x = (N + block.x - 1) / block.x;
for(i=0;i<iter;i++){
for(j=0;j<loop;j++){
calculate<<<grid,block>>>(matriz_1);
}
for(j=0;j<loop;j++){
compute1<<<grid,block>>>(matriz_1);
}
for(j=0;j<loop;j++){
compute2<<<grid,block>>>(matriz_1);
}
}
return 0;
}
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void calculate(int *d_buffer){
int ix = blockIdx.x*blockDim.x + threadIdx.x;
d_buffer[ix] += d_buffer[ix];
__syncthreads();
}
__global__ void compute1(int *d_buffer){
int ix = blockIdx.x*blockDim.x + threadIdx.x;
d_buffer[ix] = d_buffer[ix]*2;
__syncthreads();
}
__global__ void compute2(int *d_buffer){
int ix = blockIdx.x*blockDim.x + threadIdx.x;
d_buffer[ix] = d_buffer[ix]*10;
__syncthreads();
}
int main(int argc, char *argv[]){
int *matriz_1,*matriz_2,*h_matriz;
int N,i,j,iter;
int loop;
//dimensão da matriz
N = atoi(argv[1]);
//numero de iterações
iter = atoi(argv[2]);
loop = atoi(argv[3]);
h_matriz = (int*) malloc(sizeof(int)*N*N);
hipMalloc(&matriz_1,sizeof(int)*N*N);
for(i=0;i<N;i++){
for(j=0;j<N;j++){
h_matriz[i*N+j] = (i*N+j)+1;
}
}
hipMemcpy(matriz_1,h_matriz,N*N*sizeof(int),hipMemcpyHostToDevice);
dim3 grid, block;
block.x = 1024;
grid.x = (N + block.x - 1) / block.x;
for(i=0;i<iter;i++){
for(j=0;j<loop;j++){
calculate<<<grid,block>>>(matriz_1);
}
for(j=0;j<loop;j++){
compute1<<<grid,block>>>(matriz_1);
}
for(j=0;j<loop;j++){
compute2<<<grid,block>>>(matriz_1);
}
}
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void calculate(int *d_buffer){
int ix = blockIdx.x*blockDim.x + threadIdx.x;
d_buffer[ix] += d_buffer[ix];
__syncthreads();
}
__global__ void compute1(int *d_buffer){
int ix = blockIdx.x*blockDim.x + threadIdx.x;
d_buffer[ix] = d_buffer[ix]*2;
__syncthreads();
}
__global__ void compute2(int *d_buffer){
int ix = blockIdx.x*blockDim.x + threadIdx.x;
d_buffer[ix] = d_buffer[ix]*10;
__syncthreads();
}
int main(int argc, char *argv[]){
int *matriz_1,*matriz_2,*h_matriz;
int N,i,j,iter;
int loop;
//dimensão da matriz
N = atoi(argv[1]);
//numero de iterações
iter = atoi(argv[2]);
loop = atoi(argv[3]);
h_matriz = (int*) malloc(sizeof(int)*N*N);
hipMalloc(&matriz_1,sizeof(int)*N*N);
for(i=0;i<N;i++){
for(j=0;j<N;j++){
h_matriz[i*N+j] = (i*N+j)+1;
}
}
hipMemcpy(matriz_1,h_matriz,N*N*sizeof(int),hipMemcpyHostToDevice);
dim3 grid, block;
block.x = 1024;
grid.x = (N + block.x - 1) / block.x;
for(i=0;i<iter;i++){
for(j=0;j<loop;j++){
calculate<<<grid,block>>>(matriz_1);
}
for(j=0;j<loop;j++){
compute1<<<grid,block>>>(matriz_1);
}
for(j=0;j<loop;j++){
compute2<<<grid,block>>>(matriz_1);
}
}
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9calculatePi
.globl _Z9calculatePi
.p2align 8
.type _Z9calculatePi,@function
_Z9calculatePi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v2, 1, v2
global_store_b32 v[0:1], v2, off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9calculatePi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9calculatePi, .Lfunc_end0-_Z9calculatePi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8compute1Pi
.globl _Z8compute1Pi
.p2align 8
.type _Z8compute1Pi,@function
_Z8compute1Pi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v2, 1, v2
global_store_b32 v[0:1], v2, off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8compute1Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z8compute1Pi, .Lfunc_end1-_Z8compute1Pi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8compute2Pi
.globl _Z8compute2Pi
.p2align 8
.type _Z8compute2Pi,@function
_Z8compute2Pi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v2, 10
global_store_b32 v[0:1], v2, off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8compute2Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z8compute2Pi, .Lfunc_end2-_Z8compute2Pi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9calculatePi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9calculatePi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8compute1Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8compute1Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8compute2Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8compute2Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void calculate(int *d_buffer){
int ix = blockIdx.x*blockDim.x + threadIdx.x;
d_buffer[ix] += d_buffer[ix];
__syncthreads();
}
__global__ void compute1(int *d_buffer){
int ix = blockIdx.x*blockDim.x + threadIdx.x;
d_buffer[ix] = d_buffer[ix]*2;
__syncthreads();
}
__global__ void compute2(int *d_buffer){
int ix = blockIdx.x*blockDim.x + threadIdx.x;
d_buffer[ix] = d_buffer[ix]*10;
__syncthreads();
}
int main(int argc, char *argv[]){
int *matriz_1,*matriz_2,*h_matriz;
int N,i,j,iter;
int loop;
//dimensão da matriz
N = atoi(argv[1]);
//numero de iterações
iter = atoi(argv[2]);
loop = atoi(argv[3]);
h_matriz = (int*) malloc(sizeof(int)*N*N);
hipMalloc(&matriz_1,sizeof(int)*N*N);
for(i=0;i<N;i++){
for(j=0;j<N;j++){
h_matriz[i*N+j] = (i*N+j)+1;
}
}
hipMemcpy(matriz_1,h_matriz,N*N*sizeof(int),hipMemcpyHostToDevice);
dim3 grid, block;
block.x = 1024;
grid.x = (N + block.x - 1) / block.x;
for(i=0;i<iter;i++){
for(j=0;j<loop;j++){
calculate<<<grid,block>>>(matriz_1);
}
for(j=0;j<loop;j++){
compute1<<<grid,block>>>(matriz_1);
}
for(j=0;j<loop;j++){
compute2<<<grid,block>>>(matriz_1);
}
}
return 0;
}
|
.text
.file "teste.hip"
.globl _Z24__device_stub__calculatePi # -- Begin function _Z24__device_stub__calculatePi
.p2align 4, 0x90
.type _Z24__device_stub__calculatePi,@function
_Z24__device_stub__calculatePi: # @_Z24__device_stub__calculatePi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z9calculatePi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z24__device_stub__calculatePi, .Lfunc_end0-_Z24__device_stub__calculatePi
.cfi_endproc
# -- End function
.globl _Z23__device_stub__compute1Pi # -- Begin function _Z23__device_stub__compute1Pi
.p2align 4, 0x90
.type _Z23__device_stub__compute1Pi,@function
_Z23__device_stub__compute1Pi: # @_Z23__device_stub__compute1Pi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z8compute1Pi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z23__device_stub__compute1Pi, .Lfunc_end1-_Z23__device_stub__compute1Pi
.cfi_endproc
# -- End function
.globl _Z23__device_stub__compute2Pi # -- Begin function _Z23__device_stub__compute2Pi
.p2align 4, 0x90
.type _Z23__device_stub__compute2Pi,@function
_Z23__device_stub__compute2Pi: # @_Z23__device_stub__compute2Pi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z8compute2Pi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z23__device_stub__compute2Pi, .Lfunc_end2-_Z23__device_stub__compute2Pi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movq 8(%rsi), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 88(%rsp) # 8-byte Spill
movq 24(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 64(%rsp) # 8-byte Spill
movslq %ebx, %r13
movq %r13, %r15
imulq %r13, %r15
shlq $2, %r15
movq %r15, %rdi
callq malloc
movq %rax, %r14
leaq 40(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %r13d, %r13d
jle .LBB3_5
# %bb.1: # %.preheader94.lr.ph
movl %ebx, %eax
movl $1, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_2: # %.preheader94
# =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
movl %r12d, %esi
leaq (%r14,%rsi,4), %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB3_3: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rcx,%rdi), %r8d
movl %r8d, (%rsi,%rdi,4)
incq %rdi
cmpq %rdi, %rax
jne .LBB3_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
incq %rdx
addq %rbx, %rcx
addl %ebx, %r12d
cmpq %rax, %rdx
jne .LBB3_2
.LBB3_5: # %._crit_edge97
movq 40(%rsp), %rdi
movl %ebx, %edx
imull %edx, %edx
shlq $2, %rdx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
cmpl $0, 88(%rsp) # 4-byte Folded Reload
jle .LBB3_14
# %bb.6: # %.preheader93.lr.ph
movabsq $4294968320, %r15 # imm = 0x100000400
leal 1023(%rbx), %eax
shrl $10, %eax
leaq (%rax,%r15), %r12
addq $-1024, %r12 # imm = 0xFC00
xorl %eax, %eax
leaq 80(%rsp), %rbx
leaq 72(%rsp), %r14
leaq 48(%rsp), %r13
jmp .LBB3_7
.p2align 4, 0x90
.LBB3_13: # %._crit_edge104
# in Loop: Header=BB3_7 Depth=1
movq 96(%rsp), %rax # 8-byte Reload
incl %eax
cmpl 88(%rsp), %eax # 4-byte Folded Reload
je .LBB3_14
.LBB3_7: # %.preheader93
# =>This Loop Header: Depth=1
# Child Loop BB3_15 Depth 2
# Child Loop BB3_18 Depth 2
# Child Loop BB3_10 Depth 2
movq %rax, 96(%rsp) # 8-byte Spill
movq 64(%rsp), %rax # 8-byte Reload
movl %eax, %ebp
testl %eax, %eax
jg .LBB3_15
.LBB3_8: # %.preheader92
# in Loop: Header=BB3_7 Depth=1
movq 64(%rsp), %rax # 8-byte Reload
movl %eax, %ebp
testl %eax, %eax
jg .LBB3_18
.LBB3_9: # %.preheader
# in Loop: Header=BB3_7 Depth=1
movq 64(%rsp), %rax # 8-byte Reload
movl %eax, %ebp
testl %eax, %eax
jg .LBB3_10
jmp .LBB3_13
.p2align 4, 0x90
.LBB3_17: # in Loop: Header=BB3_15 Depth=2
decl %ebp
je .LBB3_8
.LBB3_15: # %.lr.ph99
# Parent Loop BB3_7 Depth=1
# => This Inner Loop Header: Depth=2
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_17
# %bb.16: # in Loop: Header=BB3_15 Depth=2
movq 40(%rsp), %rax
movq %rax, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 48(%rsp)
leaq 16(%rsp), %rdi
movq %rsp, %rsi
movq %rbx, %rdx
movq %r14, %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
movl $_Z9calculatePi, %edi
movq %r13, %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_17
.p2align 4, 0x90
.LBB3_20: # in Loop: Header=BB3_18 Depth=2
decl %ebp
je .LBB3_9
.LBB3_18: # %.lr.ph101
# Parent Loop BB3_7 Depth=1
# => This Inner Loop Header: Depth=2
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_20
# %bb.19: # in Loop: Header=BB3_18 Depth=2
movq 40(%rsp), %rax
movq %rax, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 48(%rsp)
leaq 16(%rsp), %rdi
movq %rsp, %rsi
movq %rbx, %rdx
movq %r14, %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
movl $_Z8compute1Pi, %edi
movq %r13, %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_20
.p2align 4, 0x90
.LBB3_12: # in Loop: Header=BB3_10 Depth=2
decl %ebp
je .LBB3_13
.LBB3_10: # %.lr.ph103
# Parent Loop BB3_7 Depth=1
# => This Inner Loop Header: Depth=2
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_12
# %bb.11: # in Loop: Header=BB3_10 Depth=2
movq 40(%rsp), %rax
movq %rax, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 48(%rsp)
leaq 16(%rsp), %rdi
movq %rsp, %rsi
movq %rbx, %rdx
movq %r14, %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
movl $_Z8compute2Pi, %edi
movq %r13, %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_12
.LBB3_14: # %._crit_edge106
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9calculatePi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8compute1Pi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8compute2Pi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9calculatePi,@object # @_Z9calculatePi
.section .rodata,"a",@progbits
.globl _Z9calculatePi
.p2align 3, 0x0
_Z9calculatePi:
.quad _Z24__device_stub__calculatePi
.size _Z9calculatePi, 8
.type _Z8compute1Pi,@object # @_Z8compute1Pi
.globl _Z8compute1Pi
.p2align 3, 0x0
_Z8compute1Pi:
.quad _Z23__device_stub__compute1Pi
.size _Z8compute1Pi, 8
.type _Z8compute2Pi,@object # @_Z8compute2Pi
.globl _Z8compute2Pi
.p2align 3, 0x0
_Z8compute2Pi:
.quad _Z23__device_stub__compute2Pi
.size _Z8compute2Pi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9calculatePi"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z8compute1Pi"
.size .L__unnamed_2, 14
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z8compute2Pi"
.size .L__unnamed_3, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__calculatePi
.addrsig_sym _Z23__device_stub__compute1Pi
.addrsig_sym _Z23__device_stub__compute2Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9calculatePi
.addrsig_sym _Z8compute1Pi
.addrsig_sym _Z8compute2Pi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z8compute2Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0080*/ IMAD R5, R0, 0xa, RZ ; /* 0x0000000a00057824 */
/* 0x004fca00078e02ff */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*00a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8compute1Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0080*/ SHF.L.U32 R5, R0, 0x1, RZ ; /* 0x0000000100057819 */
/* 0x004fca00000006ff */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*00a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9calculatePi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0080*/ SHF.L.U32 R5, R0, 0x1, RZ ; /* 0x0000000100057819 */
/* 0x004fca00000006ff */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*00a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9calculatePi
.globl _Z9calculatePi
.p2align 8
.type _Z9calculatePi,@function
_Z9calculatePi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v2, 1, v2
global_store_b32 v[0:1], v2, off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9calculatePi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9calculatePi, .Lfunc_end0-_Z9calculatePi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8compute1Pi
.globl _Z8compute1Pi
.p2align 8
.type _Z8compute1Pi,@function
_Z8compute1Pi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v2, 1, v2
global_store_b32 v[0:1], v2, off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8compute1Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z8compute1Pi, .Lfunc_end1-_Z8compute1Pi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8compute2Pi
.globl _Z8compute2Pi
.p2align 8
.type _Z8compute2Pi,@function
_Z8compute2Pi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v2, 10
global_store_b32 v[0:1], v2, off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8compute2Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z8compute2Pi, .Lfunc_end2-_Z8compute2Pi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9calculatePi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9calculatePi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8compute1Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8compute1Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8compute2Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8compute2Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_001204e4_00000000-6_teste.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z9calculatePiPi
.type _Z28__device_stub__Z9calculatePiPi, @function
_Z28__device_stub__Z9calculatePiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9calculatePi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z9calculatePiPi, .-_Z28__device_stub__Z9calculatePiPi
.globl _Z9calculatePi
.type _Z9calculatePi, @function
_Z9calculatePi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z9calculatePiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9calculatePi, .-_Z9calculatePi
.globl _Z27__device_stub__Z8compute1PiPi
.type _Z27__device_stub__Z8compute1PiPi, @function
_Z27__device_stub__Z8compute1PiPi:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8compute1Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z27__device_stub__Z8compute1PiPi, .-_Z27__device_stub__Z8compute1PiPi
.globl _Z8compute1Pi
.type _Z8compute1Pi, @function
_Z8compute1Pi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z8compute1PiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z8compute1Pi, .-_Z8compute1Pi
.globl _Z27__device_stub__Z8compute2PiPi
.type _Z27__device_stub__Z8compute2PiPi, @function
_Z27__device_stub__Z8compute2PiPi:
.LFB2086:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8compute2Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z27__device_stub__Z8compute2PiPi, .-_Z27__device_stub__Z8compute2PiPi
.globl _Z8compute2Pi
.type _Z8compute2Pi, @function
_Z8compute2Pi:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z8compute2PiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z8compute2Pi, .-_Z8compute2Pi
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movl %eax, %r14d
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 8(%rsp)
movl %eax, %r13d
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebx
movslq %r12d, %rbp
movq %rbp, %r15
imulq %rbp, %r15
salq $2, %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, (%rsp)
leaq 24(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
testl %r12d, %r12d
jle .L28
movl %r12d, %r9d
salq $2, %rbp
movq (%rsp), %r8
leal 1(%r12), %ecx
movl $1, %edi
movl $0, %esi
.L29:
movq %r8, %rdx
movl %edi, %eax
.L30:
movl %eax, (%rdx)
addl $1, %eax
addq $4, %rdx
cmpl %ecx, %eax
jne .L30
addl $1, %esi
addl %r9d, %edi
addq %rbp, %r8
addl %r9d, %ecx
cmpl %r14d, %esi
jne .L29
.L28:
movl $1, %ecx
movq %r15, %rdx
movq (%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
addl $1023, %r12d
shrl $10, %r12d
movl %r12d, 32(%rsp)
movl $0, %r12d
cmpl $0, 8(%rsp)
jg .L31
.L32:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L50
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
addl $1, %ebp
cmpl %ebx, %ebp
je .L51
.L34:
movl $1024, 44(%rsp)
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L33
movq 24(%rsp), %rdi
call _Z28__device_stub__Z9calculatePiPi
jmp .L33
.L51:
movl $0, %ebp
jmp .L36
.L35:
addl $1, %ebp
cmpl %ebx, %ebp
je .L52
.L36:
movl $1024, 44(%rsp)
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L35
movq 24(%rsp), %rdi
call _Z27__device_stub__Z8compute1PiPi
jmp .L35
.L52:
movl $0, %ebp
jmp .L38
.L37:
addl $1, %ebp
cmpl %ebx, %ebp
je .L39
.L38:
movl $1024, 44(%rsp)
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L37
movq 24(%rsp), %rdi
call _Z27__device_stub__Z8compute2PiPi
jmp .L37
.L39:
addl $1, %r12d
cmpl %r13d, %r12d
je .L32
.L31:
movl $0, %ebp
testl %ebx, %ebx
jg .L34
jmp .L39
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8compute2Pi"
.LC1:
.string "_Z8compute1Pi"
.LC2:
.string "_Z9calculatePi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8compute2Pi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8compute1Pi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z9calculatePi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "teste.hip"
.globl _Z24__device_stub__calculatePi # -- Begin function _Z24__device_stub__calculatePi
.p2align 4, 0x90
.type _Z24__device_stub__calculatePi,@function
_Z24__device_stub__calculatePi: # @_Z24__device_stub__calculatePi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z9calculatePi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z24__device_stub__calculatePi, .Lfunc_end0-_Z24__device_stub__calculatePi
.cfi_endproc
# -- End function
.globl _Z23__device_stub__compute1Pi # -- Begin function _Z23__device_stub__compute1Pi
.p2align 4, 0x90
.type _Z23__device_stub__compute1Pi,@function
_Z23__device_stub__compute1Pi: # @_Z23__device_stub__compute1Pi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z8compute1Pi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z23__device_stub__compute1Pi, .Lfunc_end1-_Z23__device_stub__compute1Pi
.cfi_endproc
# -- End function
.globl _Z23__device_stub__compute2Pi # -- Begin function _Z23__device_stub__compute2Pi
.p2align 4, 0x90
.type _Z23__device_stub__compute2Pi,@function
_Z23__device_stub__compute2Pi: # @_Z23__device_stub__compute2Pi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z8compute2Pi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z23__device_stub__compute2Pi, .Lfunc_end2-_Z23__device_stub__compute2Pi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movq 8(%rsi), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 88(%rsp) # 8-byte Spill
movq 24(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 64(%rsp) # 8-byte Spill
movslq %ebx, %r13
movq %r13, %r15
imulq %r13, %r15
shlq $2, %r15
movq %r15, %rdi
callq malloc
movq %rax, %r14
leaq 40(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %r13d, %r13d
jle .LBB3_5
# %bb.1: # %.preheader94.lr.ph
movl %ebx, %eax
movl $1, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_2: # %.preheader94
# =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
movl %r12d, %esi
leaq (%r14,%rsi,4), %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB3_3: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rcx,%rdi), %r8d
movl %r8d, (%rsi,%rdi,4)
incq %rdi
cmpq %rdi, %rax
jne .LBB3_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
incq %rdx
addq %rbx, %rcx
addl %ebx, %r12d
cmpq %rax, %rdx
jne .LBB3_2
.LBB3_5: # %._crit_edge97
movq 40(%rsp), %rdi
movl %ebx, %edx
imull %edx, %edx
shlq $2, %rdx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
cmpl $0, 88(%rsp) # 4-byte Folded Reload
jle .LBB3_14
# %bb.6: # %.preheader93.lr.ph
movabsq $4294968320, %r15 # imm = 0x100000400
leal 1023(%rbx), %eax
shrl $10, %eax
leaq (%rax,%r15), %r12
addq $-1024, %r12 # imm = 0xFC00
xorl %eax, %eax
leaq 80(%rsp), %rbx
leaq 72(%rsp), %r14
leaq 48(%rsp), %r13
jmp .LBB3_7
.p2align 4, 0x90
.LBB3_13: # %._crit_edge104
# in Loop: Header=BB3_7 Depth=1
movq 96(%rsp), %rax # 8-byte Reload
incl %eax
cmpl 88(%rsp), %eax # 4-byte Folded Reload
je .LBB3_14
.LBB3_7: # %.preheader93
# =>This Loop Header: Depth=1
# Child Loop BB3_15 Depth 2
# Child Loop BB3_18 Depth 2
# Child Loop BB3_10 Depth 2
movq %rax, 96(%rsp) # 8-byte Spill
movq 64(%rsp), %rax # 8-byte Reload
movl %eax, %ebp
testl %eax, %eax
jg .LBB3_15
.LBB3_8: # %.preheader92
# in Loop: Header=BB3_7 Depth=1
movq 64(%rsp), %rax # 8-byte Reload
movl %eax, %ebp
testl %eax, %eax
jg .LBB3_18
.LBB3_9: # %.preheader
# in Loop: Header=BB3_7 Depth=1
movq 64(%rsp), %rax # 8-byte Reload
movl %eax, %ebp
testl %eax, %eax
jg .LBB3_10
jmp .LBB3_13
.p2align 4, 0x90
.LBB3_17: # in Loop: Header=BB3_15 Depth=2
decl %ebp
je .LBB3_8
.LBB3_15: # %.lr.ph99
# Parent Loop BB3_7 Depth=1
# => This Inner Loop Header: Depth=2
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_17
# %bb.16: # in Loop: Header=BB3_15 Depth=2
movq 40(%rsp), %rax
movq %rax, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 48(%rsp)
leaq 16(%rsp), %rdi
movq %rsp, %rsi
movq %rbx, %rdx
movq %r14, %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
movl $_Z9calculatePi, %edi
movq %r13, %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_17
.p2align 4, 0x90
.LBB3_20: # in Loop: Header=BB3_18 Depth=2
decl %ebp
je .LBB3_9
.LBB3_18: # %.lr.ph101
# Parent Loop BB3_7 Depth=1
# => This Inner Loop Header: Depth=2
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_20
# %bb.19: # in Loop: Header=BB3_18 Depth=2
movq 40(%rsp), %rax
movq %rax, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 48(%rsp)
leaq 16(%rsp), %rdi
movq %rsp, %rsi
movq %rbx, %rdx
movq %r14, %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
movl $_Z8compute1Pi, %edi
movq %r13, %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_20
.p2align 4, 0x90
.LBB3_12: # in Loop: Header=BB3_10 Depth=2
decl %ebp
je .LBB3_13
.LBB3_10: # %.lr.ph103
# Parent Loop BB3_7 Depth=1
# => This Inner Loop Header: Depth=2
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_12
# %bb.11: # in Loop: Header=BB3_10 Depth=2
movq 40(%rsp), %rax
movq %rax, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 48(%rsp)
leaq 16(%rsp), %rdi
movq %rsp, %rsi
movq %rbx, %rdx
movq %r14, %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
movl $_Z8compute2Pi, %edi
movq %r13, %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_12
.LBB3_14: # %._crit_edge106
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9calculatePi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8compute1Pi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8compute2Pi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9calculatePi,@object # @_Z9calculatePi
.section .rodata,"a",@progbits
.globl _Z9calculatePi
.p2align 3, 0x0
_Z9calculatePi:
.quad _Z24__device_stub__calculatePi
.size _Z9calculatePi, 8
.type _Z8compute1Pi,@object # @_Z8compute1Pi
.globl _Z8compute1Pi
.p2align 3, 0x0
_Z8compute1Pi:
.quad _Z23__device_stub__compute1Pi
.size _Z8compute1Pi, 8
.type _Z8compute2Pi,@object # @_Z8compute2Pi
.globl _Z8compute2Pi
.p2align 3, 0x0
_Z8compute2Pi:
.quad _Z23__device_stub__compute2Pi
.size _Z8compute2Pi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9calculatePi"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z8compute1Pi"
.size .L__unnamed_2, 14
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z8compute2Pi"
.size .L__unnamed_3, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__calculatePi
.addrsig_sym _Z23__device_stub__compute1Pi
.addrsig_sym _Z23__device_stub__compute2Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9calculatePi
.addrsig_sym _Z8compute1Pi
.addrsig_sym _Z8compute2Pi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
__global__ void sigmoidf(float* X, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
X[x] = 1 / (1 + expf(-X[x]));
}
__global__ void sigmoid(double* X, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
X[x] = 1 / (1 + exp(-X[x]));
}
__global__ void myTanhf(float* X, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
X[x] = tanhf(X[x]);
}
__global__ void myTanh(double* X, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
X[x] = tanh(X[x]);
}
__global__ void clipf(float* X, const float min, const float max, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
X[x] = fmaxf(fminf(X[x], max), min);
}
__global__ void clip(double* X, const double min, const double max, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
X[x] = fmax(fmin(X[x], max), min);
}
__global__ void inplaceReluDerivativef(float* X, float* Y, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
if(X[x] == 0)
Y[x] = 0;
}
__global__ void inplaceReluDerivative(double* X, double* Y, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
if(X[x] == 0)
Y[x] = 0;
}
__global__ void squaredErrorf(float* X, float* Y, float* Z, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
Z[x] = powf((X[x] - Y[x]), 2);
}
__global__ void squaredError(double* X, double* Y, double* Z, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
Z[x] = pow((X[x] - Y[x]), 2);
}
__global__ void logLossf(float* X, float* Y,float* out, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
out[x] = X[x] * logf(Y[x]);
}
__global__ void logLoss(double* X, float* Y,double* out, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
out[x] = X[x] * log(Y[x]);
}
__global__ void binaryLogLossf(float* X, float* Y,float* out, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
out[x] = X[x] * logf(Y[x]) + (1 - X[x]) * logf(1 - Y[x]);
}
__global__ void binaryLogLoss(double* X, float* Y,double* out, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
out[x] = X[x] * log(Y[x]) + (1 - X[x]) * log(1 - Y[x]);
}
|
.file "tmpxft_00085866_00000000-6__base.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z8sigmoidfPfiPfi
.type _Z28__device_stub__Z8sigmoidfPfiPfi, @function
_Z28__device_stub__Z8sigmoidfPfiPfi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8sigmoidfPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z8sigmoidfPfiPfi, .-_Z28__device_stub__Z8sigmoidfPfiPfi
.globl _Z8sigmoidfPfi
.type _Z8sigmoidfPfi, @function
_Z8sigmoidfPfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z8sigmoidfPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8sigmoidfPfi, .-_Z8sigmoidfPfi
.globl _Z27__device_stub__Z7sigmoidPdiPdi
.type _Z27__device_stub__Z7sigmoidPdiPdi, @function
_Z27__device_stub__Z7sigmoidPdiPdi:
.LFB2053:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7sigmoidPdi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z27__device_stub__Z7sigmoidPdiPdi, .-_Z27__device_stub__Z7sigmoidPdiPdi
.globl _Z7sigmoidPdi
.type _Z7sigmoidPdi, @function
_Z7sigmoidPdi:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z7sigmoidPdiPdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z7sigmoidPdi, .-_Z7sigmoidPdi
.globl _Z27__device_stub__Z7myTanhfPfiPfi
.type _Z27__device_stub__Z7myTanhfPfiPfi, @function
_Z27__device_stub__Z7myTanhfPfiPfi:
.LFB2055:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7myTanhfPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z27__device_stub__Z7myTanhfPfiPfi, .-_Z27__device_stub__Z7myTanhfPfiPfi
.globl _Z7myTanhfPfi
.type _Z7myTanhfPfi, @function
_Z7myTanhfPfi:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z7myTanhfPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z7myTanhfPfi, .-_Z7myTanhfPfi
.globl _Z26__device_stub__Z6myTanhPdiPdi
.type _Z26__device_stub__Z6myTanhPdiPdi, @function
_Z26__device_stub__Z6myTanhPdiPdi:
.LFB2057:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6myTanhPdi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z26__device_stub__Z6myTanhPdiPdi, .-_Z26__device_stub__Z6myTanhPdiPdi
.globl _Z6myTanhPdi
.type _Z6myTanhPdi, @function
_Z6myTanhPdi:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6myTanhPdiPdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z6myTanhPdi, .-_Z6myTanhPdi
.globl _Z27__device_stub__Z5clipfPfffiPfffi
.type _Z27__device_stub__Z5clipfPfffiPfffi, @function
_Z27__device_stub__Z5clipfPfffiPfffi:
.LFB2059:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movl %esi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5clipfPfffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z27__device_stub__Z5clipfPfffiPfffi, .-_Z27__device_stub__Z5clipfPfffiPfffi
.globl _Z5clipfPfffi
.type _Z5clipfPfffi, @function
_Z5clipfPfffi:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z5clipfPfffiPfffi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z5clipfPfffi, .-_Z5clipfPfffi
.globl _Z26__device_stub__Z4clipPdddiPdddi
.type _Z26__device_stub__Z4clipPdddiPdddi, @function
_Z26__device_stub__Z4clipPdddiPdddi:
.LFB2061:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movsd %xmm0, 16(%rsp)
movsd %xmm1, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4clipPdddi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z26__device_stub__Z4clipPdddiPdddi, .-_Z26__device_stub__Z4clipPdddiPdddi
.globl _Z4clipPdddi
.type _Z4clipPdddi, @function
_Z4clipPdddi:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z4clipPdddiPdddi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z4clipPdddi, .-_Z4clipPdddi
.globl _Z45__device_stub__Z22inplaceReluDerivativefPfS_iPfS_i
.type _Z45__device_stub__Z22inplaceReluDerivativefPfS_iPfS_i, @function
_Z45__device_stub__Z22inplaceReluDerivativefPfS_iPfS_i:
.LFB2063:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L55
.L51:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L56
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22inplaceReluDerivativefPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L51
.L56:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size _Z45__device_stub__Z22inplaceReluDerivativefPfS_iPfS_i, .-_Z45__device_stub__Z22inplaceReluDerivativefPfS_iPfS_i
.globl _Z22inplaceReluDerivativefPfS_i
.type _Z22inplaceReluDerivativefPfS_i, @function
_Z22inplaceReluDerivativefPfS_i:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z22inplaceReluDerivativefPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _Z22inplaceReluDerivativefPfS_i, .-_Z22inplaceReluDerivativefPfS_i
.globl _Z44__device_stub__Z21inplaceReluDerivativePdS_iPdS_i
.type _Z44__device_stub__Z21inplaceReluDerivativePdS_iPdS_i, @function
_Z44__device_stub__Z21inplaceReluDerivativePdS_iPdS_i:
.LFB2065:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L63
.L59:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L64
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L63:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21inplaceReluDerivativePdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L59
.L64:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2065:
.size _Z44__device_stub__Z21inplaceReluDerivativePdS_iPdS_i, .-_Z44__device_stub__Z21inplaceReluDerivativePdS_iPdS_i
.globl _Z21inplaceReluDerivativePdS_i
.type _Z21inplaceReluDerivativePdS_i, @function
_Z21inplaceReluDerivativePdS_i:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z21inplaceReluDerivativePdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _Z21inplaceReluDerivativePdS_i, .-_Z21inplaceReluDerivativePdS_i
.globl _Z38__device_stub__Z13squaredErrorfPfS_S_iPfS_S_i
.type _Z38__device_stub__Z13squaredErrorfPfS_S_iPfS_S_i, @function
_Z38__device_stub__Z13squaredErrorfPfS_S_iPfS_S_i:
.LFB2067:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L71
.L67:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L72
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L71:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13squaredErrorfPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L67
.L72:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2067:
.size _Z38__device_stub__Z13squaredErrorfPfS_S_iPfS_S_i, .-_Z38__device_stub__Z13squaredErrorfPfS_S_iPfS_S_i
.globl _Z13squaredErrorfPfS_S_i
.type _Z13squaredErrorfPfS_S_i, @function
_Z13squaredErrorfPfS_S_i:
.LFB2068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13squaredErrorfPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2068:
.size _Z13squaredErrorfPfS_S_i, .-_Z13squaredErrorfPfS_S_i
.globl _Z37__device_stub__Z12squaredErrorPdS_S_iPdS_S_i
.type _Z37__device_stub__Z12squaredErrorPdS_S_iPdS_S_i, @function
_Z37__device_stub__Z12squaredErrorPdS_S_iPdS_S_i:
.LFB2069:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L79
.L75:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L80
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L79:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12squaredErrorPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L75
.L80:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2069:
.size _Z37__device_stub__Z12squaredErrorPdS_S_iPdS_S_i, .-_Z37__device_stub__Z12squaredErrorPdS_S_iPdS_S_i
.globl _Z12squaredErrorPdS_S_i
.type _Z12squaredErrorPdS_S_i, @function
_Z12squaredErrorPdS_S_i:
.LFB2070:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12squaredErrorPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2070:
.size _Z12squaredErrorPdS_S_i, .-_Z12squaredErrorPdS_S_i
.globl _Z32__device_stub__Z8logLossfPfS_S_iPfS_S_i
.type _Z32__device_stub__Z8logLossfPfS_S_iPfS_S_i, @function
_Z32__device_stub__Z8logLossfPfS_S_iPfS_S_i:
.LFB2071:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L87
.L83:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L88
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L87:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8logLossfPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L83
.L88:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2071:
.size _Z32__device_stub__Z8logLossfPfS_S_iPfS_S_i, .-_Z32__device_stub__Z8logLossfPfS_S_iPfS_S_i
.globl _Z8logLossfPfS_S_i
.type _Z8logLossfPfS_S_i, @function
_Z8logLossfPfS_S_i:
.LFB2072:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8logLossfPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2072:
.size _Z8logLossfPfS_S_i, .-_Z8logLossfPfS_S_i
.globl _Z31__device_stub__Z7logLossPdPfS_iPdPfS_i
.type _Z31__device_stub__Z7logLossPdPfS_iPdPfS_i, @function
_Z31__device_stub__Z7logLossPdPfS_iPdPfS_i:
.LFB2073:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L95
.L91:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L96
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L95:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7logLossPdPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L91
.L96:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2073:
.size _Z31__device_stub__Z7logLossPdPfS_iPdPfS_i, .-_Z31__device_stub__Z7logLossPdPfS_iPdPfS_i
.globl _Z7logLossPdPfS_i
.type _Z7logLossPdPfS_i, @function
_Z7logLossPdPfS_i:
.LFB2074:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z7logLossPdPfS_iPdPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2074:
.size _Z7logLossPdPfS_i, .-_Z7logLossPdPfS_i
.globl _Z39__device_stub__Z14binaryLogLossfPfS_S_iPfS_S_i
.type _Z39__device_stub__Z14binaryLogLossfPfS_S_iPfS_S_i, @function
_Z39__device_stub__Z14binaryLogLossfPfS_S_iPfS_S_i:
.LFB2075:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L103
.L99:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L104
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L103:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14binaryLogLossfPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L99
.L104:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2075:
.size _Z39__device_stub__Z14binaryLogLossfPfS_S_iPfS_S_i, .-_Z39__device_stub__Z14binaryLogLossfPfS_S_iPfS_S_i
.globl _Z14binaryLogLossfPfS_S_i
.type _Z14binaryLogLossfPfS_S_i, @function
_Z14binaryLogLossfPfS_S_i:
.LFB2076:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14binaryLogLossfPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2076:
.size _Z14binaryLogLossfPfS_S_i, .-_Z14binaryLogLossfPfS_S_i
.globl _Z38__device_stub__Z13binaryLogLossPdPfS_iPdPfS_i
.type _Z38__device_stub__Z13binaryLogLossPdPfS_iPdPfS_i, @function
_Z38__device_stub__Z13binaryLogLossPdPfS_iPdPfS_i:
.LFB2077:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L111
.L107:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L112
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L111:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13binaryLogLossPdPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L107
.L112:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2077:
.size _Z38__device_stub__Z13binaryLogLossPdPfS_iPdPfS_i, .-_Z38__device_stub__Z13binaryLogLossPdPfS_iPdPfS_i
.globl _Z13binaryLogLossPdPfS_i
.type _Z13binaryLogLossPdPfS_i, @function
_Z13binaryLogLossPdPfS_i:
.LFB2078:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13binaryLogLossPdPfS_iPdPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2078:
.size _Z13binaryLogLossPdPfS_i, .-_Z13binaryLogLossPdPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13binaryLogLossPdPfS_i"
.LC1:
.string "_Z14binaryLogLossfPfS_S_i"
.LC2:
.string "_Z7logLossPdPfS_i"
.LC3:
.string "_Z8logLossfPfS_S_i"
.LC4:
.string "_Z12squaredErrorPdS_S_i"
.LC5:
.string "_Z13squaredErrorfPfS_S_i"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "_Z21inplaceReluDerivativePdS_i"
.align 8
.LC7:
.string "_Z22inplaceReluDerivativefPfS_i"
.section .rodata.str1.1
.LC8:
.string "_Z4clipPdddi"
.LC9:
.string "_Z5clipfPfffi"
.LC10:
.string "_Z6myTanhPdi"
.LC11:
.string "_Z7myTanhfPfi"
.LC12:
.string "_Z7sigmoidPdi"
.LC13:
.string "_Z8sigmoidfPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2080:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13binaryLogLossPdPfS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14binaryLogLossfPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z7logLossPdPfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z8logLossfPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z12squaredErrorPdS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z13squaredErrorfPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z21inplaceReluDerivativePdS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z22inplaceReluDerivativefPfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z4clipPdddi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z5clipfPfffi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z6myTanhPdi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z7myTanhfPfi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z7sigmoidPdi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z8sigmoidfPfi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2080:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
__global__ void sigmoidf(float* X, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
X[x] = 1 / (1 + expf(-X[x]));
}
__global__ void sigmoid(double* X, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
X[x] = 1 / (1 + exp(-X[x]));
}
__global__ void myTanhf(float* X, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
X[x] = tanhf(X[x]);
}
__global__ void myTanh(double* X, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
X[x] = tanh(X[x]);
}
__global__ void clipf(float* X, const float min, const float max, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
X[x] = fmaxf(fminf(X[x], max), min);
}
__global__ void clip(double* X, const double min, const double max, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
X[x] = fmax(fmin(X[x], max), min);
}
__global__ void inplaceReluDerivativef(float* X, float* Y, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
if(X[x] == 0)
Y[x] = 0;
}
__global__ void inplaceReluDerivative(double* X, double* Y, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
if(X[x] == 0)
Y[x] = 0;
}
__global__ void squaredErrorf(float* X, float* Y, float* Z, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
Z[x] = powf((X[x] - Y[x]), 2);
}
__global__ void squaredError(double* X, double* Y, double* Z, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
Z[x] = pow((X[x] - Y[x]), 2);
}
__global__ void logLossf(float* X, float* Y,float* out, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
out[x] = X[x] * logf(Y[x]);
}
__global__ void logLoss(double* X, float* Y,double* out, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
out[x] = X[x] * log(Y[x]);
}
__global__ void binaryLogLossf(float* X, float* Y,float* out, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
out[x] = X[x] * logf(Y[x]) + (1 - X[x]) * logf(1 - Y[x]);
}
__global__ void binaryLogLoss(double* X, float* Y,double* out, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
out[x] = X[x] * log(Y[x]) + (1 - X[x]) * log(1 - Y[x]);
}
|
#include <hip/hip_runtime.h>
__global__ void sigmoidf(float* X, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
X[x] = 1 / (1 + expf(-X[x]));
}
__global__ void sigmoid(double* X, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
X[x] = 1 / (1 + exp(-X[x]));
}
__global__ void myTanhf(float* X, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
X[x] = tanhf(X[x]);
}
__global__ void myTanh(double* X, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
X[x] = tanh(X[x]);
}
__global__ void clipf(float* X, const float min, const float max, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
X[x] = fmaxf(fminf(X[x], max), min);
}
__global__ void clip(double* X, const double min, const double max, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
X[x] = fmax(fmin(X[x], max), min);
}
__global__ void inplaceReluDerivativef(float* X, float* Y, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
if(X[x] == 0)
Y[x] = 0;
}
__global__ void inplaceReluDerivative(double* X, double* Y, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
if(X[x] == 0)
Y[x] = 0;
}
__global__ void squaredErrorf(float* X, float* Y, float* Z, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
Z[x] = powf((X[x] - Y[x]), 2);
}
__global__ void squaredError(double* X, double* Y, double* Z, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
Z[x] = pow((X[x] - Y[x]), 2);
}
__global__ void logLossf(float* X, float* Y,float* out, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
out[x] = X[x] * logf(Y[x]);
}
__global__ void logLoss(double* X, float* Y,double* out, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
out[x] = X[x] * log(Y[x]);
}
__global__ void binaryLogLossf(float* X, float* Y,float* out, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
out[x] = X[x] * logf(Y[x]) + (1 - X[x]) * logf(1 - Y[x]);
}
__global__ void binaryLogLoss(double* X, float* Y,double* out, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
out[x] = X[x] * log(Y[x]) + (1 - X[x]) * log(1 - Y[x]);
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
__global__ void sigmoidf(float* X, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
X[x] = 1 / (1 + expf(-X[x]));
}
__global__ void sigmoid(double* X, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
X[x] = 1 / (1 + exp(-X[x]));
}
__global__ void myTanhf(float* X, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
X[x] = tanhf(X[x]);
}
__global__ void myTanh(double* X, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
X[x] = tanh(X[x]);
}
__global__ void clipf(float* X, const float min, const float max, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
X[x] = fmaxf(fminf(X[x], max), min);
}
__global__ void clip(double* X, const double min, const double max, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
X[x] = fmax(fmin(X[x], max), min);
}
__global__ void inplaceReluDerivativef(float* X, float* Y, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
if(X[x] == 0)
Y[x] = 0;
}
__global__ void inplaceReluDerivative(double* X, double* Y, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
if(X[x] == 0)
Y[x] = 0;
}
__global__ void squaredErrorf(float* X, float* Y, float* Z, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
Z[x] = powf((X[x] - Y[x]), 2);
}
__global__ void squaredError(double* X, double* Y, double* Z, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
Z[x] = pow((X[x] - Y[x]), 2);
}
__global__ void logLossf(float* X, float* Y,float* out, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
out[x] = X[x] * logf(Y[x]);
}
__global__ void logLoss(double* X, float* Y,double* out, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
out[x] = X[x] * log(Y[x]);
}
__global__ void binaryLogLossf(float* X, float* Y,float* out, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
out[x] = X[x] * logf(Y[x]) + (1 - X[x]) * logf(1 - Y[x]);
}
__global__ void binaryLogLoss(double* X, float* Y,double* out, int size) {
const unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
if(x >= size) return;
out[x] = X[x] * log(Y[x]) + (1 - X[x]) * log(1 - Y[x]);
}
|
.text
.file "_base.hip"
.globl _Z23__device_stub__sigmoidfPfi # -- Begin function _Z23__device_stub__sigmoidfPfi
.p2align 4, 0x90
.type _Z23__device_stub__sigmoidfPfi,@function
_Z23__device_stub__sigmoidfPfi: # @_Z23__device_stub__sigmoidfPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8sigmoidfPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__sigmoidfPfi, .Lfunc_end0-_Z23__device_stub__sigmoidfPfi
.cfi_endproc
# -- End function
.globl _Z22__device_stub__sigmoidPdi # -- Begin function _Z22__device_stub__sigmoidPdi
.p2align 4, 0x90
.type _Z22__device_stub__sigmoidPdi,@function
_Z22__device_stub__sigmoidPdi: # @_Z22__device_stub__sigmoidPdi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7sigmoidPdi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z22__device_stub__sigmoidPdi, .Lfunc_end1-_Z22__device_stub__sigmoidPdi
.cfi_endproc
# -- End function
.globl _Z22__device_stub__myTanhfPfi # -- Begin function _Z22__device_stub__myTanhfPfi
.p2align 4, 0x90
.type _Z22__device_stub__myTanhfPfi,@function
_Z22__device_stub__myTanhfPfi: # @_Z22__device_stub__myTanhfPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7myTanhfPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z22__device_stub__myTanhfPfi, .Lfunc_end2-_Z22__device_stub__myTanhfPfi
.cfi_endproc
# -- End function
.globl _Z21__device_stub__myTanhPdi # -- Begin function _Z21__device_stub__myTanhPdi
.p2align 4, 0x90
.type _Z21__device_stub__myTanhPdi,@function
_Z21__device_stub__myTanhPdi: # @_Z21__device_stub__myTanhPdi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6myTanhPdi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z21__device_stub__myTanhPdi, .Lfunc_end3-_Z21__device_stub__myTanhPdi
.cfi_endproc
# -- End function
.globl _Z20__device_stub__clipfPfffi # -- Begin function _Z20__device_stub__clipfPfffi
.p2align 4, 0x90
.type _Z20__device_stub__clipfPfffi,@function
_Z20__device_stub__clipfPfffi: # @_Z20__device_stub__clipfPfffi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movl %esi, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5clipfPfffi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z20__device_stub__clipfPfffi, .Lfunc_end4-_Z20__device_stub__clipfPfffi
.cfi_endproc
# -- End function
.globl _Z19__device_stub__clipPdddi # -- Begin function _Z19__device_stub__clipPdddi
.p2align 4, 0x90
.type _Z19__device_stub__clipPdddi,@function
_Z19__device_stub__clipPdddi: # @_Z19__device_stub__clipPdddi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movsd %xmm0, 64(%rsp)
movsd %xmm1, 56(%rsp)
movl %esi, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4clipPdddi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end5:
.size _Z19__device_stub__clipPdddi, .Lfunc_end5-_Z19__device_stub__clipPdddi
.cfi_endproc
# -- End function
.globl _Z37__device_stub__inplaceReluDerivativefPfS_i # -- Begin function _Z37__device_stub__inplaceReluDerivativefPfS_i
.p2align 4, 0x90
.type _Z37__device_stub__inplaceReluDerivativefPfS_i,@function
_Z37__device_stub__inplaceReluDerivativefPfS_i: # @_Z37__device_stub__inplaceReluDerivativefPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22inplaceReluDerivativefPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end6:
.size _Z37__device_stub__inplaceReluDerivativefPfS_i, .Lfunc_end6-_Z37__device_stub__inplaceReluDerivativefPfS_i
.cfi_endproc
# -- End function
.globl _Z36__device_stub__inplaceReluDerivativePdS_i # -- Begin function _Z36__device_stub__inplaceReluDerivativePdS_i
.p2align 4, 0x90
.type _Z36__device_stub__inplaceReluDerivativePdS_i,@function
_Z36__device_stub__inplaceReluDerivativePdS_i: # @_Z36__device_stub__inplaceReluDerivativePdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21inplaceReluDerivativePdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end7:
.size _Z36__device_stub__inplaceReluDerivativePdS_i, .Lfunc_end7-_Z36__device_stub__inplaceReluDerivativePdS_i
.cfi_endproc
# -- End function
.globl _Z28__device_stub__squaredErrorfPfS_S_i # -- Begin function _Z28__device_stub__squaredErrorfPfS_S_i
.p2align 4, 0x90
.type _Z28__device_stub__squaredErrorfPfS_S_i,@function
_Z28__device_stub__squaredErrorfPfS_S_i: # @_Z28__device_stub__squaredErrorfPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13squaredErrorfPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end8:
.size _Z28__device_stub__squaredErrorfPfS_S_i, .Lfunc_end8-_Z28__device_stub__squaredErrorfPfS_S_i
.cfi_endproc
# -- End function
.globl _Z27__device_stub__squaredErrorPdS_S_i # -- Begin function _Z27__device_stub__squaredErrorPdS_S_i
.p2align 4, 0x90
.type _Z27__device_stub__squaredErrorPdS_S_i,@function
_Z27__device_stub__squaredErrorPdS_S_i: # @_Z27__device_stub__squaredErrorPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12squaredErrorPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end9:
.size _Z27__device_stub__squaredErrorPdS_S_i, .Lfunc_end9-_Z27__device_stub__squaredErrorPdS_S_i
.cfi_endproc
# -- End function
.globl _Z23__device_stub__logLossfPfS_S_i # -- Begin function _Z23__device_stub__logLossfPfS_S_i
.p2align 4, 0x90
.type _Z23__device_stub__logLossfPfS_S_i,@function
_Z23__device_stub__logLossfPfS_S_i: # @_Z23__device_stub__logLossfPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8logLossfPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end10:
.size _Z23__device_stub__logLossfPfS_S_i, .Lfunc_end10-_Z23__device_stub__logLossfPfS_S_i
.cfi_endproc
# -- End function
.globl _Z22__device_stub__logLossPdPfS_i # -- Begin function _Z22__device_stub__logLossPdPfS_i
.p2align 4, 0x90
.type _Z22__device_stub__logLossPdPfS_i,@function
_Z22__device_stub__logLossPdPfS_i: # @_Z22__device_stub__logLossPdPfS_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7logLossPdPfS_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end11:
.size _Z22__device_stub__logLossPdPfS_i, .Lfunc_end11-_Z22__device_stub__logLossPdPfS_i
.cfi_endproc
# -- End function
.globl _Z29__device_stub__binaryLogLossfPfS_S_i # -- Begin function _Z29__device_stub__binaryLogLossfPfS_S_i
.p2align 4, 0x90
.type _Z29__device_stub__binaryLogLossfPfS_S_i,@function
_Z29__device_stub__binaryLogLossfPfS_S_i: # @_Z29__device_stub__binaryLogLossfPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14binaryLogLossfPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end12:
.size _Z29__device_stub__binaryLogLossfPfS_S_i, .Lfunc_end12-_Z29__device_stub__binaryLogLossfPfS_S_i
.cfi_endproc
# -- End function
.globl _Z28__device_stub__binaryLogLossPdPfS_i # -- Begin function _Z28__device_stub__binaryLogLossPdPfS_i
.p2align 4, 0x90
.type _Z28__device_stub__binaryLogLossPdPfS_i,@function
_Z28__device_stub__binaryLogLossPdPfS_i: # @_Z28__device_stub__binaryLogLossPdPfS_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13binaryLogLossPdPfS_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end13:
.size _Z28__device_stub__binaryLogLossPdPfS_i, .Lfunc_end13-_Z28__device_stub__binaryLogLossPdPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB14_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB14_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8sigmoidfPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7sigmoidPdi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7myTanhfPfi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6myTanhPdi, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5clipfPfffi, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4clipPdddi, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22inplaceReluDerivativefPfS_i, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21inplaceReluDerivativePdS_i, %esi
movl $.L__unnamed_8, %edx
movl $.L__unnamed_8, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13squaredErrorfPfS_S_i, %esi
movl $.L__unnamed_9, %edx
movl $.L__unnamed_9, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12squaredErrorPdS_S_i, %esi
movl $.L__unnamed_10, %edx
movl $.L__unnamed_10, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8logLossfPfS_S_i, %esi
movl $.L__unnamed_11, %edx
movl $.L__unnamed_11, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7logLossPdPfS_i, %esi
movl $.L__unnamed_12, %edx
movl $.L__unnamed_12, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14binaryLogLossfPfS_S_i, %esi
movl $.L__unnamed_13, %edx
movl $.L__unnamed_13, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13binaryLogLossPdPfS_i, %esi
movl $.L__unnamed_14, %edx
movl $.L__unnamed_14, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end14:
.size __hip_module_ctor, .Lfunc_end14-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB15_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB15_2:
retq
.Lfunc_end15:
.size __hip_module_dtor, .Lfunc_end15-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8sigmoidfPfi,@object # @_Z8sigmoidfPfi
.section .rodata,"a",@progbits
.globl _Z8sigmoidfPfi
.p2align 3, 0x0
_Z8sigmoidfPfi:
.quad _Z23__device_stub__sigmoidfPfi
.size _Z8sigmoidfPfi, 8
.type _Z7sigmoidPdi,@object # @_Z7sigmoidPdi
.globl _Z7sigmoidPdi
.p2align 3, 0x0
_Z7sigmoidPdi:
.quad _Z22__device_stub__sigmoidPdi
.size _Z7sigmoidPdi, 8
.type _Z7myTanhfPfi,@object # @_Z7myTanhfPfi
.globl _Z7myTanhfPfi
.p2align 3, 0x0
_Z7myTanhfPfi:
.quad _Z22__device_stub__myTanhfPfi
.size _Z7myTanhfPfi, 8
.type _Z6myTanhPdi,@object # @_Z6myTanhPdi
.globl _Z6myTanhPdi
.p2align 3, 0x0
_Z6myTanhPdi:
.quad _Z21__device_stub__myTanhPdi
.size _Z6myTanhPdi, 8
.type _Z5clipfPfffi,@object # @_Z5clipfPfffi
.globl _Z5clipfPfffi
.p2align 3, 0x0
_Z5clipfPfffi:
.quad _Z20__device_stub__clipfPfffi
.size _Z5clipfPfffi, 8
.type _Z4clipPdddi,@object # @_Z4clipPdddi
.globl _Z4clipPdddi
.p2align 3, 0x0
_Z4clipPdddi:
.quad _Z19__device_stub__clipPdddi
.size _Z4clipPdddi, 8
.type _Z22inplaceReluDerivativefPfS_i,@object # @_Z22inplaceReluDerivativefPfS_i
.globl _Z22inplaceReluDerivativefPfS_i
.p2align 3, 0x0
_Z22inplaceReluDerivativefPfS_i:
.quad _Z37__device_stub__inplaceReluDerivativefPfS_i
.size _Z22inplaceReluDerivativefPfS_i, 8
.type _Z21inplaceReluDerivativePdS_i,@object # @_Z21inplaceReluDerivativePdS_i
.globl _Z21inplaceReluDerivativePdS_i
.p2align 3, 0x0
_Z21inplaceReluDerivativePdS_i:
.quad _Z36__device_stub__inplaceReluDerivativePdS_i
.size _Z21inplaceReluDerivativePdS_i, 8
.type _Z13squaredErrorfPfS_S_i,@object # @_Z13squaredErrorfPfS_S_i
.globl _Z13squaredErrorfPfS_S_i
.p2align 3, 0x0
_Z13squaredErrorfPfS_S_i:
.quad _Z28__device_stub__squaredErrorfPfS_S_i
.size _Z13squaredErrorfPfS_S_i, 8
.type _Z12squaredErrorPdS_S_i,@object # @_Z12squaredErrorPdS_S_i
.globl _Z12squaredErrorPdS_S_i
.p2align 3, 0x0
_Z12squaredErrorPdS_S_i:
.quad _Z27__device_stub__squaredErrorPdS_S_i
.size _Z12squaredErrorPdS_S_i, 8
.type _Z8logLossfPfS_S_i,@object # @_Z8logLossfPfS_S_i
.globl _Z8logLossfPfS_S_i
.p2align 3, 0x0
_Z8logLossfPfS_S_i:
.quad _Z23__device_stub__logLossfPfS_S_i
.size _Z8logLossfPfS_S_i, 8
.type _Z7logLossPdPfS_i,@object # @_Z7logLossPdPfS_i
.globl _Z7logLossPdPfS_i
.p2align 3, 0x0
_Z7logLossPdPfS_i:
.quad _Z22__device_stub__logLossPdPfS_i
.size _Z7logLossPdPfS_i, 8
.type _Z14binaryLogLossfPfS_S_i,@object # @_Z14binaryLogLossfPfS_S_i
.globl _Z14binaryLogLossfPfS_S_i
.p2align 3, 0x0
_Z14binaryLogLossfPfS_S_i:
.quad _Z29__device_stub__binaryLogLossfPfS_S_i
.size _Z14binaryLogLossfPfS_S_i, 8
.type _Z13binaryLogLossPdPfS_i,@object # @_Z13binaryLogLossPdPfS_i
.globl _Z13binaryLogLossPdPfS_i
.p2align 3, 0x0
_Z13binaryLogLossPdPfS_i:
.quad _Z28__device_stub__binaryLogLossPdPfS_i
.size _Z13binaryLogLossPdPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8sigmoidfPfi"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7sigmoidPdi"
.size .L__unnamed_2, 14
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z7myTanhfPfi"
.size .L__unnamed_3, 14
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z6myTanhPdi"
.size .L__unnamed_4, 13
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z5clipfPfffi"
.size .L__unnamed_5, 14
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_Z4clipPdddi"
.size .L__unnamed_6, 13
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "_Z22inplaceReluDerivativefPfS_i"
.size .L__unnamed_7, 32
.type .L__unnamed_8,@object # @7
.L__unnamed_8:
.asciz "_Z21inplaceReluDerivativePdS_i"
.size .L__unnamed_8, 31
.type .L__unnamed_9,@object # @8
.L__unnamed_9:
.asciz "_Z13squaredErrorfPfS_S_i"
.size .L__unnamed_9, 25
.type .L__unnamed_10,@object # @9
.L__unnamed_10:
.asciz "_Z12squaredErrorPdS_S_i"
.size .L__unnamed_10, 24
.type .L__unnamed_11,@object # @10
.L__unnamed_11:
.asciz "_Z8logLossfPfS_S_i"
.size .L__unnamed_11, 19
.type .L__unnamed_12,@object # @11
.L__unnamed_12:
.asciz "_Z7logLossPdPfS_i"
.size .L__unnamed_12, 18
.type .L__unnamed_13,@object # @12
.L__unnamed_13:
.asciz "_Z14binaryLogLossfPfS_S_i"
.size .L__unnamed_13, 26
.type .L__unnamed_14,@object # @13
.L__unnamed_14:
.asciz "_Z13binaryLogLossPdPfS_i"
.size .L__unnamed_14, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__sigmoidfPfi
.addrsig_sym _Z22__device_stub__sigmoidPdi
.addrsig_sym _Z22__device_stub__myTanhfPfi
.addrsig_sym _Z21__device_stub__myTanhPdi
.addrsig_sym _Z20__device_stub__clipfPfffi
.addrsig_sym _Z19__device_stub__clipPdddi
.addrsig_sym _Z37__device_stub__inplaceReluDerivativefPfS_i
.addrsig_sym _Z36__device_stub__inplaceReluDerivativePdS_i
.addrsig_sym _Z28__device_stub__squaredErrorfPfS_S_i
.addrsig_sym _Z27__device_stub__squaredErrorPdS_S_i
.addrsig_sym _Z23__device_stub__logLossfPfS_S_i
.addrsig_sym _Z22__device_stub__logLossPdPfS_i
.addrsig_sym _Z29__device_stub__binaryLogLossfPfS_S_i
.addrsig_sym _Z28__device_stub__binaryLogLossPdPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8sigmoidfPfi
.addrsig_sym _Z7sigmoidPdi
.addrsig_sym _Z7myTanhfPfi
.addrsig_sym _Z6myTanhPdi
.addrsig_sym _Z5clipfPfffi
.addrsig_sym _Z4clipPdddi
.addrsig_sym _Z22inplaceReluDerivativefPfS_i
.addrsig_sym _Z21inplaceReluDerivativePdS_i
.addrsig_sym _Z13squaredErrorfPfS_S_i
.addrsig_sym _Z12squaredErrorPdS_S_i
.addrsig_sym _Z8logLossfPfS_S_i
.addrsig_sym _Z7logLossPdPfS_i
.addrsig_sym _Z14binaryLogLossfPfS_S_i
.addrsig_sym _Z13binaryLogLossPdPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include<stdlib.h>
#include<iostream>
#include<cmath>
#include<fstream>
#include<chrono>
//shared host/device constants
int gridWidth,gridHeight,gridDepth,blockWidth,blockHeight,blockDepth,gridWidthBlocks,gridHeightBlocks,gridDepthBlocks,gridArea;
__constant__ int gridWidth_d,gridHeight_d,gridDepth_d,blockWidth_d,blockHeight_d,blockDepth_d,gridWidthBlocks_d,gridHeightBlocks_d,gridDepthBlocks_d;
//host only constants
int timeSteps;
__device__ int arrayPos(const int &x,const int &y,const int &z){
return (z*gridWidth_d*gridHeight_d)+(y*gridWidth_d)+x;
}
__global__ void solver(bool *grid,bool *grid1){
int xpos = (blockIdx.x*blockWidth_d)+threadIdx.x;
int ypos = (blockIdx.y*blockHeight_d)+threadIdx.y;
int zpos = (blockIdx.z*blockDepth_d)+threadIdx.z;
if(xpos>0 && xpos<gridWidth_d-1 && ypos>0 && ypos<gridHeight_d-1 && zpos>0 && zpos<gridDepth_d-1){
int neighbors = grid[arrayPos(xpos+1,ypos,zpos)]+grid[arrayPos(xpos-1,ypos,zpos)]
+grid[arrayPos(xpos,ypos+1,zpos)]+grid[arrayPos(xpos,ypos-1,zpos)]
+grid[arrayPos(xpos,ypos,zpos+1)]+grid[arrayPos(xpos,ypos,zpos-1)];
if(grid[arrayPos(xpos,ypos,zpos)]){
if(neighbors<2 || neighbors>3){
grid1[arrayPos(xpos,ypos,zpos)] = false;
}else{
grid1[arrayPos(xpos,ypos,zpos)] = true;
}
}else{
if(neighbors==3){
grid1[arrayPos(xpos,ypos,zpos)] = true;
}else{
grid1[arrayPos(xpos,ypos,zpos)] = false;
}
}
}
}
//helper function to read grid from a text file
void readTextRepr(const std::string& filename,bool *array){
std::ifstream file(filename);
std::string str;
int index=0;
while(std::getline(file,str)){
if(str!="---"){
for(int i=0;i<str.length();i++){
//stop reading if file is greater than arrayLength
if(index<gridArea){
if(str[i]!='\n'){
if(str[i]=='#'){
array[index]=true;
}else{
array[index]=false;
}
index++;
}
}
}
}
}
//fill in excess space with falses if file is too short
if(index<gridArea){
for(int i=index;i<gridArea;i++){
array[index]=false;
}
}
}
//helper function to write grid to a text file
void writeTextRepr(const std::string& filename,bool *array){
std::ofstream file(filename);
for(int i=0;i<gridArea;i++){
if(array[i]){
file<<'#';
}else{
file<<' ';
}
if((i+1)%gridWidth==0){
file<<'\n';
}
if((i+1)%(gridWidth*gridHeight)==0){
file<<"---\n";
}
}
}
int main(int argc, const char * argv[]){
//start clock
auto startTime = std::chrono::high_resolution_clock::now();
//input and output files
std::string inFile = "in.txt";
std::string outFile = "out.txt";
//time of simulation
timeSteps = 1;
//dimensions of the grid
gridWidth = 16;
gridHeight = 16;
gridDepth = 16;
/*
Speed testing with varying grid and block sizes, using both 3D and 2D kernel implementations
16x16x16 grid, 2mil steps:
3D Kernel
16x16x1 = 18921ms
8x8x16 = 21150ms
8x8x8 = 19432ms
4x4x4 = 21614ms
2x2x2 = 24362ms
2D Kernel
16x16 = 19389ms
8x8 = 19425ms
4x4 = 19992ms
64x64x64 grid, 2mil steps:
3D Kernel
16x16x1 = 44162ms
8x8x8 = 61221ms
8x8x4 = 62442ms
2D Kernel
16x16 = 47543ms
2048x2048x128 grid, 100 steps:
3D Kernel
16x16x1 = 15065ms
8x8x8 = 18386ms
The fastest block size across both small and large grids appears to be 16x16x1, using the 3D kernel
*/
blockWidth = 16;
blockHeight = 16;
blockDepth = 1;
//handle command line arguments
int optionLen = 0;
for(int i=1;i<argc;i+=optionLen){
printf("%d",i);
if(strcmp(argv[i],"-i")==0){
optionLen = 2;
if(i+optionLen<=argc){
inFile = argv[i+1];
}else{
printf("Error: Missing arguments for -i\n");
return 1;
}
}else if(strcmp(argv[i],"-o")==0){
optionLen = 2;
if(i+optionLen<=argc){
outFile = argv[i+1];
}else{
printf("Error: Missing arguments for -o\n");
return 1;
}
}else if(strcmp(argv[i],"-t")==0){
optionLen = 2;
if(i+optionLen<=argc){
timeSteps = strtol(argv[i+1],NULL,10);
}else{
printf("Error: Missing arguments for -t\n");
return 1;
}
}else if(strcmp(argv[i],"-g")==0){
optionLen = 4;
if(i+optionLen<=argc){
gridWidth = strtol(argv[i+1],NULL,10);
gridHeight = strtol(argv[i+2],NULL,10);
gridDepth = strtol(argv[i+3],NULL,10);
}else{
printf("Error: Missing arguments for -g\n");
return 1;
}
}else if(strcmp(argv[i],"-b")==0){
optionLen = 4;
if(i+optionLen<=argc){
blockWidth = strtol(argv[i+1],NULL,10);
blockHeight = strtol(argv[i+2],NULL,10);
blockDepth = strtol(argv[i+3],NULL,10);
}else{
printf("Error: Missing arguments for -b\n");
return 1;
}
}else{
printf("Error: Parameters must be of form:\n");
printf("./game [-i infile] [-o outfile] [-t timesteps] [-g griddimensions] [-b blockdimensions]\n");
return 1;
}
}
//derived values
gridWidthBlocks = std::ceil((float)gridWidth/(float)blockWidth);
gridHeightBlocks = std::ceil((float)gridHeight/(float)blockHeight);
gridDepthBlocks = std::ceil((float)gridDepth/(float)blockDepth);
gridArea = gridWidth*gridHeight*gridDepth;
std::cout << "In file = " << inFile << "\n";
std::cout << "Out file = " << outFile << "\n";
printf("Time steps = %d\n",timeSteps);
printf("Grid dimensions = %dx%dx%d\n",gridWidth,gridHeight,gridDepth);
printf("Block dimensions = %dx%dx%d\n",blockWidth,blockHeight,blockDepth);
printf("Grid in blocks = %dx%dx%d\n",gridWidthBlocks,gridHeightBlocks,gridDepthBlocks);
printf("...");
//set device symbols to dimensions of grid,block,etc.
cudaMemcpyToSymbol(*(&gridWidth_d),&gridWidth,sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(*(&gridHeight_d),&gridHeight,sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(*(&gridDepth_d),&gridDepth,sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(*(&blockWidth_d),&blockWidth,sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(*(&blockHeight_d),&blockHeight,sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(*(&blockDepth_d),&blockDepth,sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(*(&gridWidthBlocks_d),&gridWidthBlocks,sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(*(&gridHeightBlocks_d),&gridHeightBlocks,sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(*(&gridDepthBlocks_d),&gridDepthBlocks,sizeof(int),0,cudaMemcpyHostToDevice);
dim3 numBlocks(gridWidthBlocks,gridHeightBlocks,gridDepthBlocks);
dim3 blockSize(blockWidth,blockHeight,blockDepth);
size_t gridSize = gridWidth*gridHeight*gridDepth;
//device+host grid arrays
bool *grid_h;
bool *grid_d,*grid1_d;
//allocate host memory
grid_h = (bool *)calloc(gridSize,sizeof(bool));
//allocate device memory
cudaMalloc((void **)&grid_d, gridSize);
cudaMalloc((void **)&grid1_d, gridSize);
//load grid
readTextRepr(inFile,grid_h);
//only copy first grid to device, second one is computed by kernel
cudaMemcpy(grid_d,grid_h,gridSize,cudaMemcpyHostToDevice);
for(int i=0;i<timeSteps;i++){
solver<<<numBlocks,blockSize>>>(grid_d,grid1_d);
cudaDeviceSynchronize();
std::swap(grid_d,grid1_d);
cudaError_t error = cudaGetLastError();
if(error != cudaSuccess){
std::cout << cudaGetErrorString(error) << std::endl;
}
}
//only copy first grid to host, since it was computed and then swapped by kernel
cudaMemcpy(grid_h,grid_d,gridSize,cudaMemcpyDeviceToHost);
//output grid
writeTextRepr(outFile,grid_h);
//free host memory
free(grid_h);
//free device memory
cudaFree(grid_d);
cudaFree(grid1_d);
//end clock
auto endTime = std::chrono::high_resolution_clock::now();
auto timePassed = std::chrono::duration_cast<std::chrono::milliseconds>(endTime-startTime).count();
printf("Ran in %ld ms\n",timePassed);
return 0;
}
|
code for sm_80
Function : _Z6solverPbS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002200 */
/*0040*/ S2R R5, SR_CTAID.Z ; /* 0x0000000000057919 */
/* 0x000ea20000002700 */
/*0050*/ IMAD R2, R2, c[0x3][0xc], R3 ; /* 0x00c0030002027a24 */
/* 0x001fc600078e0203 */
/*0060*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002600 */
/*0070*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*0080*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0090*/ ULDC UR4, c[0x3][0x0] ; /* 0x00c0000000047ab9 */
/* 0x006fe20000000800 */
/*00a0*/ IMAD R3, R3, c[0x3][0x10], R0 ; /* 0x00c0040003037a24 */
/* 0x001fe200078e0200 */
/*00b0*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*00c0*/ S2R R0, SR_TID.Z ; /* 0x0000000000007919 */
/* 0x000e2a0000002300 */
/*00d0*/ ISETP.GE.AND P0, PT, R2, UR4, PT ; /* 0x0000000402007c0c */
/* 0x000fc8000bf06270 */
/*00e0*/ ISETP.LT.OR P0, PT, R3, 0x1, P0 ; /* 0x000000010300780c */
/* 0x000fda0000701670 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0100*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x3][0x4] ; /* 0x00c00100ff077624 */
/* 0x000fe400078e00ff */
/*0110*/ IMAD R0, R5, c[0x3][0x14], R0 ; /* 0x00c0050005007a24 */
/* 0x001fc600078e0200 */
/*0120*/ IADD3 R4, R7, -0x1, RZ ; /* 0xffffffff07047810 */
/* 0x000fc80007ffe0ff */
/*0130*/ ISETP.GE.AND P0, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x000fc80003f06270 */
/*0140*/ ISETP.LT.OR P0, PT, R0, 0x1, P0 ; /* 0x000000010000780c */
/* 0x000fda0000701670 */
/*0150*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0160*/ ULDC UR4, c[0x3][0x8] ; /* 0x00c0020000047ab9 */
/* 0x000fe40000000800 */
/*0170*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fcc000fffe03f */
/*0180*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0190*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD R4, R0.reuse, R7, c[0x3][0x4] ; /* 0x00c0010000047624 */
/* 0x040fe200078e0207 */
/*01b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*01c0*/ IMAD.MOV R7, RZ, RZ, -c[0x3][0x4] ; /* 0x80c00100ff077624 */
/* 0x000fe400078e02ff */
/*01d0*/ IMAD R5, R0, c[0x3][0x4], R3 ; /* 0x00c0010000057a24 */
/* 0x000fe400078e0203 */
/*01e0*/ IMAD R6, R7, 0x2, R4 ; /* 0x0000000207067824 */
/* 0x000fe400078e0204 */
/*01f0*/ IMAD R0, R5.reuse, c[0x3][0x0], R2 ; /* 0x00c0000005007a24 */
/* 0x040fe200078e0202 */
/*0200*/ IADD3 R7, R5, 0x1, RZ ; /* 0x0000000105077810 */
/* 0x000fe20007ffe0ff */
/*0210*/ IMAD.IADD R11, R3, 0x1, R6 ; /* 0x00000001030b7824 */
/* 0x000fe200078e0206 */
/*0220*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe20007ffe0ff */
/*0230*/ IMAD.IADD R9, R3, 0x1, R4 ; /* 0x0000000103097824 */
/* 0x000fe200078e0204 */
/*0240*/ SHF.R.S32.HI R16, RZ, 0x1f, R0 ; /* 0x0000001fff107819 */
/* 0x000fe20000011400 */
/*0250*/ IMAD R3, R7, c[0x3][0x0], R2.reuse ; /* 0x00c0000007037a24 */
/* 0x100fe200078e0202 */
/*0260*/ IADD3 R6, P1, R0, c[0x0][0x160], RZ ; /* 0x0000580000067a10 */
/* 0x000fe20007f3e0ff */
/*0270*/ IMAD R12, R9, c[0x3][0x0], R2 ; /* 0x00c00000090c7a24 */
/* 0x000fc400078e0202 */
/*0280*/ IMAD R4, R5, c[0x3][0x0], R2.reuse ; /* 0x00c0000005047a24 */
/* 0x100fe200078e0202 */
/*0290*/ IADD3.X R7, R16, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590010077a10 */
/* 0x000fe20000ffe4ff */
/*02a0*/ IMAD R13, R11, c[0x3][0x0], R2 ; /* 0x00c000000b0d7a24 */
/* 0x000fe200078e0202 */
/*02b0*/ IADD3 R10, P0, R3.reuse, c[0x0][0x160], RZ ; /* 0x00005800030a7a10 */
/* 0x040fe40007f1e0ff */
/*02c0*/ IADD3 R8, P1, R4, c[0x0][0x160], RZ ; /* 0x0000580004087a10 */
/* 0x000fe20007f3e0ff */
/*02d0*/ LDG.E.U8 R15, [R6.64] ; /* 0x00000004060f7981 */
/* 0x000ea2000c1e1100 */
/*02e0*/ IADD3 R2, P2, R12, c[0x0][0x160], RZ ; /* 0x000058000c027a10 */
/* 0x000fe40007f5e0ff */
/*02f0*/ LEA.HI.X.SX32 R11, R3, c[0x0][0x164], 0x1, P0 ; /* 0x00005900030b7a11 */
/* 0x000fe200000f0eff */
/*0300*/ LDG.E.S8 R5, [R6.64+0x1] ; /* 0x0000010406057981 */
/* 0x000ee2000c1e1300 */
/*0310*/ LEA.HI.X.SX32 R9, R4, c[0x0][0x164], 0x1, P1 ; /* 0x0000590004097a11 */
/* 0x000fc400008f0eff */
/*0320*/ LEA.HI.X.SX32 R3, R12, c[0x0][0x164], 0x1, P2 ; /* 0x000059000c037a11 */
/* 0x000fe200010f0eff */
/*0330*/ LDG.E.S8 R14, [R6.64+-0x1] ; /* 0xffffff04060e7981 */
/* 0x000ee2000c1e1300 */
/*0340*/ IADD3 R12, P0, R13, c[0x0][0x160], RZ ; /* 0x000058000d0c7a10 */
/* 0x000fc60007f1e0ff */
/*0350*/ LDG.E.S8 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ee2000c1e1300 */
/*0360*/ LEA.HI.X.SX32 R13, R13, c[0x0][0x164], 0x1, P0 ; /* 0x000059000d0d7a11 */
/* 0x000fc600000f0eff */
/*0370*/ LDG.E.S8 R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000f28000c1e1300 */
/*0380*/ LDG.E.S8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000f28000c1e1300 */
/*0390*/ LDG.E.S8 R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000f62000c1e1300 */
/*03a0*/ IADD3 R4, P1, R0, c[0x0][0x168], RZ ; /* 0x00005a0000047a10 */
/* 0x000fe40007f3e0ff */
/*03b0*/ ISETP.NE.AND P0, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x004fc40003f05270 */
/*03c0*/ IADD3 R14, R10, R14, R5 ; /* 0x0000000e0a0e7210 */
/* 0x008fe40007ffe005 */
/*03d0*/ IADD3.X R5, R16, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0010057a10 */
/* 0x000fe40000ffe4ff */
/*03e0*/ IADD3 R14, R2, R14, R9 ; /* 0x0000000e020e7210 */
/* 0x010fca0007ffe009 */
/*03f0*/ IMAD.IADD R14, R14, 0x1, R13 ; /* 0x000000010e0e7824 */
/* 0x020fe400078e020d */
/*0400*/ @!P0 BRA 0x480 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*0410*/ LOP3.LUT R14, R14, 0xfffffffe, RZ, 0xc0, !PT ; /* 0xfffffffe0e0e7812 */
/* 0x000fc800078ec0ff */
/*0420*/ ISETP.NE.AND P0, PT, R14, 0x2, PT ; /* 0x000000020e00780c */
/* 0x000fda0003f05270 */
/*0430*/ @P0 STG.E.U8 [R4.64], RZ ; /* 0x000000ff04000986 */
/* 0x0001e2000c101104 */
/*0440*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0450*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fca00078e00ff */
/*0460*/ STG.E.U8 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x000fe2000c101104 */
/*0470*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0480*/ ISETP.NE.AND P0, PT, R14, 0x3, PT ; /* 0x000000030e00780c */
/* 0x000fda0003f05270 */
/*0490*/ @P0 STG.E.U8 [R4.64], RZ ; /* 0x000000ff04000986 */
/* 0x0001e2000c101104 */
/*04a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*04b0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fca00078e00ff */
/*04c0*/ STG.E.U8 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x000fe2000c101104 */
/*04d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04e0*/ BRA 0x4e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include<stdlib.h>
#include<iostream>
#include<cmath>
#include<fstream>
#include<chrono>
//shared host/device constants
int gridWidth,gridHeight,gridDepth,blockWidth,blockHeight,blockDepth,gridWidthBlocks,gridHeightBlocks,gridDepthBlocks,gridArea;
__constant__ int gridWidth_d,gridHeight_d,gridDepth_d,blockWidth_d,blockHeight_d,blockDepth_d,gridWidthBlocks_d,gridHeightBlocks_d,gridDepthBlocks_d;
//host only constants
int timeSteps;
__device__ int arrayPos(const int &x,const int &y,const int &z){
return (z*gridWidth_d*gridHeight_d)+(y*gridWidth_d)+x;
}
__global__ void solver(bool *grid,bool *grid1){
int xpos = (blockIdx.x*blockWidth_d)+threadIdx.x;
int ypos = (blockIdx.y*blockHeight_d)+threadIdx.y;
int zpos = (blockIdx.z*blockDepth_d)+threadIdx.z;
if(xpos>0 && xpos<gridWidth_d-1 && ypos>0 && ypos<gridHeight_d-1 && zpos>0 && zpos<gridDepth_d-1){
int neighbors = grid[arrayPos(xpos+1,ypos,zpos)]+grid[arrayPos(xpos-1,ypos,zpos)]
+grid[arrayPos(xpos,ypos+1,zpos)]+grid[arrayPos(xpos,ypos-1,zpos)]
+grid[arrayPos(xpos,ypos,zpos+1)]+grid[arrayPos(xpos,ypos,zpos-1)];
if(grid[arrayPos(xpos,ypos,zpos)]){
if(neighbors<2 || neighbors>3){
grid1[arrayPos(xpos,ypos,zpos)] = false;
}else{
grid1[arrayPos(xpos,ypos,zpos)] = true;
}
}else{
if(neighbors==3){
grid1[arrayPos(xpos,ypos,zpos)] = true;
}else{
grid1[arrayPos(xpos,ypos,zpos)] = false;
}
}
}
}
//helper function to read grid from a text file
void readTextRepr(const std::string& filename,bool *array){
std::ifstream file(filename);
std::string str;
int index=0;
while(std::getline(file,str)){
if(str!="---"){
for(int i=0;i<str.length();i++){
//stop reading if file is greater than arrayLength
if(index<gridArea){
if(str[i]!='\n'){
if(str[i]=='#'){
array[index]=true;
}else{
array[index]=false;
}
index++;
}
}
}
}
}
//fill in excess space with falses if file is too short
if(index<gridArea){
for(int i=index;i<gridArea;i++){
array[index]=false;
}
}
}
//helper function to write grid to a text file
void writeTextRepr(const std::string& filename,bool *array){
std::ofstream file(filename);
for(int i=0;i<gridArea;i++){
if(array[i]){
file<<'#';
}else{
file<<' ';
}
if((i+1)%gridWidth==0){
file<<'\n';
}
if((i+1)%(gridWidth*gridHeight)==0){
file<<"---\n";
}
}
}
int main(int argc, const char * argv[]){
//start clock
auto startTime = std::chrono::high_resolution_clock::now();
//input and output files
std::string inFile = "in.txt";
std::string outFile = "out.txt";
//time of simulation
timeSteps = 1;
//dimensions of the grid
gridWidth = 16;
gridHeight = 16;
gridDepth = 16;
/*
Speed testing with varying grid and block sizes, using both 3D and 2D kernel implementations
16x16x16 grid, 2mil steps:
3D Kernel
16x16x1 = 18921ms
8x8x16 = 21150ms
8x8x8 = 19432ms
4x4x4 = 21614ms
2x2x2 = 24362ms
2D Kernel
16x16 = 19389ms
8x8 = 19425ms
4x4 = 19992ms
64x64x64 grid, 2mil steps:
3D Kernel
16x16x1 = 44162ms
8x8x8 = 61221ms
8x8x4 = 62442ms
2D Kernel
16x16 = 47543ms
2048x2048x128 grid, 100 steps:
3D Kernel
16x16x1 = 15065ms
8x8x8 = 18386ms
The fastest block size across both small and large grids appears to be 16x16x1, using the 3D kernel
*/
blockWidth = 16;
blockHeight = 16;
blockDepth = 1;
//handle command line arguments
int optionLen = 0;
for(int i=1;i<argc;i+=optionLen){
printf("%d",i);
if(strcmp(argv[i],"-i")==0){
optionLen = 2;
if(i+optionLen<=argc){
inFile = argv[i+1];
}else{
printf("Error: Missing arguments for -i\n");
return 1;
}
}else if(strcmp(argv[i],"-o")==0){
optionLen = 2;
if(i+optionLen<=argc){
outFile = argv[i+1];
}else{
printf("Error: Missing arguments for -o\n");
return 1;
}
}else if(strcmp(argv[i],"-t")==0){
optionLen = 2;
if(i+optionLen<=argc){
timeSteps = strtol(argv[i+1],NULL,10);
}else{
printf("Error: Missing arguments for -t\n");
return 1;
}
}else if(strcmp(argv[i],"-g")==0){
optionLen = 4;
if(i+optionLen<=argc){
gridWidth = strtol(argv[i+1],NULL,10);
gridHeight = strtol(argv[i+2],NULL,10);
gridDepth = strtol(argv[i+3],NULL,10);
}else{
printf("Error: Missing arguments for -g\n");
return 1;
}
}else if(strcmp(argv[i],"-b")==0){
optionLen = 4;
if(i+optionLen<=argc){
blockWidth = strtol(argv[i+1],NULL,10);
blockHeight = strtol(argv[i+2],NULL,10);
blockDepth = strtol(argv[i+3],NULL,10);
}else{
printf("Error: Missing arguments for -b\n");
return 1;
}
}else{
printf("Error: Parameters must be of form:\n");
printf("./game [-i infile] [-o outfile] [-t timesteps] [-g griddimensions] [-b blockdimensions]\n");
return 1;
}
}
//derived values
gridWidthBlocks = std::ceil((float)gridWidth/(float)blockWidth);
gridHeightBlocks = std::ceil((float)gridHeight/(float)blockHeight);
gridDepthBlocks = std::ceil((float)gridDepth/(float)blockDepth);
gridArea = gridWidth*gridHeight*gridDepth;
std::cout << "In file = " << inFile << "\n";
std::cout << "Out file = " << outFile << "\n";
printf("Time steps = %d\n",timeSteps);
printf("Grid dimensions = %dx%dx%d\n",gridWidth,gridHeight,gridDepth);
printf("Block dimensions = %dx%dx%d\n",blockWidth,blockHeight,blockDepth);
printf("Grid in blocks = %dx%dx%d\n",gridWidthBlocks,gridHeightBlocks,gridDepthBlocks);
printf("...");
//set device symbols to dimensions of grid,block,etc.
cudaMemcpyToSymbol(*(&gridWidth_d),&gridWidth,sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(*(&gridHeight_d),&gridHeight,sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(*(&gridDepth_d),&gridDepth,sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(*(&blockWidth_d),&blockWidth,sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(*(&blockHeight_d),&blockHeight,sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(*(&blockDepth_d),&blockDepth,sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(*(&gridWidthBlocks_d),&gridWidthBlocks,sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(*(&gridHeightBlocks_d),&gridHeightBlocks,sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(*(&gridDepthBlocks_d),&gridDepthBlocks,sizeof(int),0,cudaMemcpyHostToDevice);
dim3 numBlocks(gridWidthBlocks,gridHeightBlocks,gridDepthBlocks);
dim3 blockSize(blockWidth,blockHeight,blockDepth);
size_t gridSize = gridWidth*gridHeight*gridDepth;
//device+host grid arrays
bool *grid_h;
bool *grid_d,*grid1_d;
//allocate host memory
grid_h = (bool *)calloc(gridSize,sizeof(bool));
//allocate device memory
cudaMalloc((void **)&grid_d, gridSize);
cudaMalloc((void **)&grid1_d, gridSize);
//load grid
readTextRepr(inFile,grid_h);
//only copy first grid to device, second one is computed by kernel
cudaMemcpy(grid_d,grid_h,gridSize,cudaMemcpyHostToDevice);
for(int i=0;i<timeSteps;i++){
solver<<<numBlocks,blockSize>>>(grid_d,grid1_d);
cudaDeviceSynchronize();
std::swap(grid_d,grid1_d);
cudaError_t error = cudaGetLastError();
if(error != cudaSuccess){
std::cout << cudaGetErrorString(error) << std::endl;
}
}
//only copy first grid to host, since it was computed and then swapped by kernel
cudaMemcpy(grid_h,grid_d,gridSize,cudaMemcpyDeviceToHost);
//output grid
writeTextRepr(outFile,grid_h);
//free host memory
free(grid_h);
//free device memory
cudaFree(grid_d);
cudaFree(grid1_d);
//end clock
auto endTime = std::chrono::high_resolution_clock::now();
auto timePassed = std::chrono::duration_cast<std::chrono::milliseconds>(endTime-startTime).count();
printf("Ran in %ld ms\n",timePassed);
return 0;
}
|
.file "tmpxft_001a94bc_00000000-6_game.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3909:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3909:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8arrayPosRKiS0_S0_
.type _Z8arrayPosRKiS0_S0_, @function
_Z8arrayPosRKiS0_S0_:
.LFB3899:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3899:
.size _Z8arrayPosRKiS0_S0_, .-_Z8arrayPosRKiS0_S0_
.globl _Z27__device_stub__Z6solverPbS_PbS_
.type _Z27__device_stub__Z6solverPbS_PbS_, @function
_Z27__device_stub__Z6solverPbS_PbS_:
.LFB3931:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6solverPbS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3931:
.size _Z27__device_stub__Z6solverPbS_PbS_, .-_Z27__device_stub__Z6solverPbS_PbS_
.globl _Z6solverPbS_
.type _Z6solverPbS_, @function
_Z6solverPbS_:
.LFB3932:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6solverPbS_PbS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3932:
.size _Z6solverPbS_, .-_Z6solverPbS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6solverPbS_"
.LC1:
.string "gridWidth_d"
.LC2:
.string "gridHeight_d"
.LC3:
.string "gridDepth_d"
.LC4:
.string "blockWidth_d"
.LC5:
.string "blockHeight_d"
.LC6:
.string "blockDepth_d"
.LC7:
.string "gridWidthBlocks_d"
.LC8:
.string "gridHeightBlocks_d"
.LC9:
.string "gridDepthBlocks_d"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3934:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6solverPbS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL11gridWidth_d(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL12gridHeight_d(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL11gridDepth_d(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL12blockWidth_d(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13blockHeight_d(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL12blockDepth_d(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17gridWidthBlocks_d(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL18gridHeightBlocks_d(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17gridDepthBlocks_d(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3934:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.str1.8,"aMS",@progbits,1
.align 8
.LC10:
.string "basic_string: construction from null is not valid"
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC5IS3_EEPKcRKS3_,comdat
.align 2
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_:
.LFB4301:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 16(%rdi), %r12
movq %r12, (%rdi)
testq %rsi, %rsi
je .L24
movq %rdi, %rbx
movq %rsi, %r13
movq %rsi, %rdi
call strlen@PLT
movq %rax, %rbp
movq %rax, (%rsp)
cmpq $15, %rax
ja .L25
cmpq $1, %rax
jne .L20
movzbl 0(%r13), %eax
movb %al, 16(%rbx)
.L21:
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rdx
movb $0, (%rdx,%rax)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L27
leaq .LC10(%rip), %rdi
call _ZSt19__throw_logic_errorPKc@PLT
.L27:
call __stack_chk_fail@PLT
.L25:
movq %rsp, %rsi
movl $0, %edx
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
movq %rax, %r12
movq %rax, (%rbx)
movq (%rsp), %rax
movq %rax, 16(%rbx)
.L19:
movq %rbp, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memcpy@PLT
jmp .L21
.L20:
testq %rax, %rax
je .L21
jmp .L19
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4301:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.set _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.section .rodata.str1.1
.LC11:
.string "---"
.text
.globl _Z12readTextReprRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPb
.type _Z12readTextReprRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPb, @function
_Z12readTextReprRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPb:
.LFB3900:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3900
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $568, %rsp
.cfi_def_cfa_offset 624
movq %rdi, %rbx
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 552(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rbp
leaq 288(%rsp), %rdi
call _ZNSt8ios_baseC2Ev@PLT
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 288(%rsp)
movq $0, 504(%rsp)
movb $0, 512(%rsp)
movb $0, 513(%rsp)
movq $0, 520(%rsp)
movq $0, 528(%rsp)
movq $0, 536(%rsp)
movq $0, 544(%rsp)
movq 8+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %r13
movq %r13, 32(%rsp)
movq 16+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %r14
movq -24(%r13), %rax
movq %r14, 32(%rsp,%rax)
movq $0, 40(%rsp)
movq 32(%rsp), %rax
movq %rbp, %rdi
addq -24(%rax), %rdi
movl $0, %esi
.LEHB0:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE0:
leaq 24+_ZTVSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 32(%rsp)
leaq 40(%rax), %rax
movq %rax, 288(%rsp)
leaq 48(%rsp), %rdi
.LEHB1:
call _ZNSt13basic_filebufIcSt11char_traitsIcEEC1Ev@PLT
.LEHE1:
leaq 48(%rsp), %rsi
leaq 288(%rsp), %rdi
.LEHB2:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
movq (%rbx), %rsi
leaq 48(%rsp), %rdi
movl $8, %edx
call _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
testq %rax, %rax
je .L67
movq 32(%rsp), %rax
movq -24(%rax), %rax
leaq 32(%rsp,%rax), %rdi
movl $0, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L30
.L67:
movq 32(%rsp), %rax
movq -24(%rax), %rax
leaq 32(%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $4, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
.LEHE2:
.L30:
leaq 16(%rsp), %rax
movq %rax, (%rsp)
movq $0, 8(%rsp)
movb $0, 16(%rsp)
movl $0, %ebx
leaq .LC11(%rip), %rbp
jmp .L37
.L60:
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt13basic_filebufIcSt11char_traitsIcEED1Ev@PLT
.L33:
movq %r13, 32(%rsp)
movq -24(%r13), %rax
movq %r14, 32(%rsp,%rax)
movq $0, 40(%rsp)
.L34:
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 288(%rsp)
leaq 288(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 552(%rsp), %rax
subq %fs:40, %rax
je .L35
call __stack_chk_fail@PLT
.L59:
endbr64
movq %rax, %rbx
jmp .L33
.L58:
endbr64
movq %rax, %rbx
jmp .L34
.L35:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L73:
movl $3, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call memcmp@PLT
testl %eax, %eax
jne .L38
.L37:
movq 32(%rsp), %rax
movq -24(%rax), %rax
movq 272(%rsp,%rax), %r15
testq %r15, %r15
je .L68
cmpb $0, 56(%r15)
je .L46
movzbl 67(%r15), %edx
.L47:
movsbl %dl, %edx
movq %rsp, %rsi
leaq 32(%rsp), %rdi
.LEHB4:
call _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_@PLT
jmp .L69
.L70:
movslq %ebx, %rdx
movb $1, (%r12,%rdx)
.L42:
addl $1, %ebx
.L40:
addq $1, %rax
cmpq %r15, %rax
je .L37
.L43:
cmpl %ebx, gridArea(%rip)
jle .L40
movzbl (%rax), %edx
cmpb $10, %dl
je .L40
cmpb $35, %dl
je .L70
movslq %ebx, %rdx
movb $0, (%r12,%rdx)
jmp .L42
.L68:
movq 552(%rsp), %rax
subq %fs:40, %rax
jne .L71
call _ZSt16__throw_bad_castv@PLT
.L57:
endbr64
movq %rax, %rbx
movq %rsp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 32(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 552(%rsp), %rax
subq %fs:40, %rax
je .L55
call __stack_chk_fail@PLT
.L71:
call __stack_chk_fail@PLT
.L46:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
.LEHE4:
movl %eax, %edx
jmp .L47
.L69:
movq (%rax), %rdx
movq -24(%rdx), %rdx
testb $5, 32(%rax,%rdx)
jne .L72
movq 8(%rsp), %r15
cmpq $3, %r15
je .L73
testq %r15, %r15
je .L37
.L38:
movq (%rsp), %rax
addq %rax, %r15
jmp .L43
.L72:
cmpl %ebx, gridArea(%rip)
jle .L49
movl %ebx, %eax
movslq %ebx, %rbx
.L50:
movb $0, (%r12,%rbx)
addl $1, %eax
cmpl %eax, gridArea(%rip)
jg .L50
.L49:
movq (%rsp), %rdi
leaq 16(%rsp), %rax
cmpq %rax, %rdi
je .L51
movq 16(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L51:
leaq 24+_ZTVSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 32(%rsp)
leaq 40(%rax), %rax
movq %rax, 288(%rsp)
leaq 16+_ZTVSt13basic_filebufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 48(%rsp)
leaq 48(%rsp), %rdi
.LEHB5:
call _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv@PLT
.LEHE5:
jmp .L53
.L61:
endbr64
movq %rax, %rdi
call __cxa_begin_catch@PLT
call __cxa_end_catch@PLT
.L53:
leaq 152(%rsp), %rdi
call _ZNSt12__basic_fileIcED1Ev@PLT
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 48(%rsp)
leaq 104(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
movq %r13, 32(%rsp)
movq -24(%r13), %rax
movq %r14, 32(%rsp,%rax)
movq $0, 40(%rsp)
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 288(%rsp)
leaq 288(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 552(%rsp), %rax
subq %fs:40, %rax
jne .L74
addq $568, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
movq %rbx, %rdi
.LEHB6:
call _Unwind_Resume@PLT
.LEHE6:
.L74:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3900:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.align 4
.LLSDA3900:
.byte 0xff
.byte 0x9b
.uleb128 .LLSDATT3900-.LLSDATTD3900
.LLSDATTD3900:
.byte 0x1
.uleb128 .LLSDACSE3900-.LLSDACSB3900
.LLSDACSB3900:
.uleb128 .LEHB0-.LFB3900
.uleb128 .LEHE0-.LEHB0
.uleb128 .L58-.LFB3900
.uleb128 0
.uleb128 .LEHB1-.LFB3900
.uleb128 .LEHE1-.LEHB1
.uleb128 .L59-.LFB3900
.uleb128 0
.uleb128 .LEHB2-.LFB3900
.uleb128 .LEHE2-.LEHB2
.uleb128 .L60-.LFB3900
.uleb128 0
.uleb128 .LEHB3-.LFB3900
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.uleb128 .LEHB4-.LFB3900
.uleb128 .LEHE4-.LEHB4
.uleb128 .L57-.LFB3900
.uleb128 0
.uleb128 .LEHB5-.LFB3900
.uleb128 .LEHE5-.LEHB5
.uleb128 .L61-.LFB3900
.uleb128 0x1
.uleb128 .LEHB6-.LFB3900
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.LLSDACSE3900:
.byte 0x1
.byte 0
.align 4
.long 0
.LLSDATT3900:
.text
.size _Z12readTextReprRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPb, .-_Z12readTextReprRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPb
.section .rodata.str1.1
.LC12:
.string "---\n"
.text
.globl _Z13writeTextReprRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPb
.type _Z13writeTextReprRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPb, @function
_Z13writeTextReprRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPb:
.LFB3902:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3902
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $544, %rsp
.cfi_def_cfa_offset 592
movq %rdi, %rbx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 536(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %r13
leaq 264(%rsp), %rdi
call _ZNSt8ios_baseC2Ev@PLT
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 264(%rsp)
movq $0, 480(%rsp)
movb $0, 488(%rsp)
movb $0, 489(%rsp)
movq $0, 496(%rsp)
movq $0, 504(%rsp)
movq $0, 512(%rsp)
movq $0, 520(%rsp)
movq 8+_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %r12
movq %r12, 16(%rsp)
movq 16+_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %r14
movq -24(%r12), %rax
movq %r14, 16(%rsp,%rax)
movq 16(%rsp), %rax
movq %r13, %rdi
addq -24(%rax), %rdi
movl $0, %esi
.LEHB7:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE7:
leaq 24+_ZTVSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 16(%rsp)
leaq 40(%rax), %rax
movq %rax, 264(%rsp)
leaq 24(%rsp), %rdi
.LEHB8:
call _ZNSt13basic_filebufIcSt11char_traitsIcEEC1Ev@PLT
.LEHE8:
leaq 24(%rsp), %rsi
leaq 264(%rsp), %rdi
.LEHB9:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
movq (%rbx), %rsi
leaq 24(%rsp), %rdi
movl $16, %edx
call _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
testq %rax, %rax
je .L109
movq 16(%rsp), %rax
movq -24(%rax), %rax
leaq 16(%rsp,%rax), %rdi
movl $0, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L79
.L109:
movq 16(%rsp), %rax
movq -24(%rax), %rax
leaq 16(%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $4, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
.LEHE9:
.L79:
movl $0, %ebx
leaq .LC12(%rip), %r13
cmpl $0, gridArea(%rip)
jg .L94
.L78:
leaq 24+_ZTVSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 16(%rsp)
leaq 40(%rax), %rax
movq %rax, 264(%rsp)
leaq 16+_ZTVSt13basic_filebufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 24(%rsp)
leaq 24(%rsp), %rdi
.LEHB10:
call _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv@PLT
.LEHE10:
jmp .L96
.L103:
endbr64
movq %rax, %rbx
leaq 24(%rsp), %rdi
call _ZNSt13basic_filebufIcSt11char_traitsIcEED1Ev@PLT
.L81:
movq %r12, 16(%rsp)
movq -24(%r12), %rax
movq %r14, 16(%rsp,%rax)
.L82:
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 264(%rsp)
leaq 264(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 536(%rsp), %rax
subq %fs:40, %rax
je .L83
call __stack_chk_fail@PLT
.L102:
endbr64
movq %rax, %rbx
jmp .L81
.L101:
endbr64
movq %rax, %rbx
jmp .L82
.L83:
movq %rbx, %rdi
.LEHB11:
call _Unwind_Resume@PLT
.LEHE11:
.L85:
leaq 16(%rsp), %rdi
movl $35, %esi
.LEHB12:
call _ZNSo3putEc@PLT
jmp .L87
.L84:
movb $32, 14(%rsp)
movq 16(%rsp), %rax
movq -24(%rax), %rax
cmpq $0, 32(%rsp,%rax)
je .L88
leaq 14(%rsp), %rsi
leaq 16(%rsp), %rdi
movl $1, %edx
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L87
.L88:
leaq 16(%rsp), %rdi
movl $32, %esi
call _ZNSo3putEc@PLT
.L87:
addl $1, %ebx
movl %ebx, %eax
cltd
idivl gridWidth(%rip)
testl %edx, %edx
je .L110
.L90:
movl gridWidth(%rip), %ecx
imull gridHeight(%rip), %ecx
movl %ebx, %eax
cltd
idivl %ecx
testl %edx, %edx
je .L111
.L93:
addq $1, %rbp
cmpl gridArea(%rip), %ebx
jge .L78
.L94:
cmpb $0, 0(%rbp)
je .L84
movb $35, 13(%rsp)
movq 16(%rsp), %rax
movq -24(%rax), %rax
cmpq $0, 32(%rsp,%rax)
je .L85
leaq 13(%rsp), %rsi
leaq 16(%rsp), %rdi
movl $1, %edx
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L87
.L110:
movb $10, 15(%rsp)
movq 16(%rsp), %rax
movq -24(%rax), %rax
cmpq $0, 32(%rsp,%rax)
je .L91
leaq 15(%rsp), %rsi
leaq 16(%rsp), %rdi
movl $1, %edx
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L90
.L91:
leaq 16(%rsp), %rdi
movl $10, %esi
call _ZNSo3putEc@PLT
jmp .L90
.L111:
leaq 16(%rsp), %rdi
movl $4, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.LEHE12:
jmp .L93
.L104:
endbr64
movq %rax, %rdi
call __cxa_begin_catch@PLT
call __cxa_end_catch@PLT
.L96:
leaq 128(%rsp), %rdi
call _ZNSt12__basic_fileIcED1Ev@PLT
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 24(%rsp)
leaq 80(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
movq %r12, 16(%rsp)
movq -24(%r12), %rax
movq %r14, 16(%rsp,%rax)
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 264(%rsp)
leaq 264(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 536(%rsp), %rax
subq %fs:40, %rax
jne .L112
addq $544, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L100:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 16(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 536(%rsp), %rax
subq %fs:40, %rax
je .L98
call __stack_chk_fail@PLT
.L98:
movq %rbx, %rdi
.LEHB13:
call _Unwind_Resume@PLT
.LEHE13:
.L112:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3902:
.section .gcc_except_table
.align 4
.LLSDA3902:
.byte 0xff
.byte 0x9b
.uleb128 .LLSDATT3902-.LLSDATTD3902
.LLSDATTD3902:
.byte 0x1
.uleb128 .LLSDACSE3902-.LLSDACSB3902
.LLSDACSB3902:
.uleb128 .LEHB7-.LFB3902
.uleb128 .LEHE7-.LEHB7
.uleb128 .L101-.LFB3902
.uleb128 0
.uleb128 .LEHB8-.LFB3902
.uleb128 .LEHE8-.LEHB8
.uleb128 .L102-.LFB3902
.uleb128 0
.uleb128 .LEHB9-.LFB3902
.uleb128 .LEHE9-.LEHB9
.uleb128 .L103-.LFB3902
.uleb128 0
.uleb128 .LEHB10-.LFB3902
.uleb128 .LEHE10-.LEHB10
.uleb128 .L104-.LFB3902
.uleb128 0x1
.uleb128 .LEHB11-.LFB3902
.uleb128 .LEHE11-.LEHB11
.uleb128 0
.uleb128 0
.uleb128 .LEHB12-.LFB3902
.uleb128 .LEHE12-.LEHB12
.uleb128 .L100-.LFB3902
.uleb128 0
.uleb128 .LEHB13-.LFB3902
.uleb128 .LEHE13-.LEHB13
.uleb128 0
.uleb128 0
.LLSDACSE3902:
.byte 0x1
.byte 0
.align 4
.long 0
.LLSDATT3902:
.text
.size _Z13writeTextReprRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPb, .-_Z13writeTextReprRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPb
.section .rodata.str1.1
.LC13:
.string "in.txt"
.LC14:
.string "out.txt"
.LC15:
.string "%d"
.LC16:
.string "-i"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC17:
.string "Error: Missing arguments for -i\n"
.section .rodata.str1.1
.LC18:
.string "-o"
.section .rodata.str1.8
.align 8
.LC19:
.string "Error: Missing arguments for -o\n"
.section .rodata.str1.1
.LC20:
.string "-t"
.section .rodata.str1.8
.align 8
.LC21:
.string "Error: Missing arguments for -t\n"
.section .rodata.str1.1
.LC22:
.string "-g"
.section .rodata.str1.8
.align 8
.LC23:
.string "Error: Missing arguments for -g\n"
.section .rodata.str1.1
.LC24:
.string "-b"
.section .rodata.str1.8
.align 8
.LC25:
.string "Error: Missing arguments for -b\n"
.align 8
.LC26:
.string "Error: Parameters must be of form:\n"
.align 8
.LC27:
.string "./game [-i infile] [-o outfile] [-t timesteps] [-g griddimensions] [-b blockdimensions]\n"
.section .rodata.str1.1
.LC28:
.string "In file = "
.LC29:
.string "\n"
.LC30:
.string "Out file = "
.LC31:
.string "Time steps = %d\n"
.LC32:
.string "Grid dimensions = %dx%dx%d\n"
.LC33:
.string "Block dimensions = %dx%dx%d\n"
.LC34:
.string "Grid in blocks = %dx%dx%d\n"
.LC35:
.string "..."
.LC36:
.string "Ran in %ld ms\n"
.text
.globl main
.type main, @function
main:
.LFB3903:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3903
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movl %edi, %r14d
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, 8(%rsp)
leaq 52(%rsp), %rbx
leaq 64(%rsp), %rdi
movq %rbx, %rdx
leaq .LC13(%rip), %rsi
.LEHB14:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE14:
leaq 96(%rsp), %rdi
movq %rbx, %rdx
leaq .LC14(%rip), %rsi
.LEHB15:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE15:
movl $1, timeSteps(%rip)
movl $16, gridWidth(%rip)
movl $16, gridHeight(%rip)
movl $16, gridDepth(%rip)
movl $16, blockWidth(%rip)
movl $16, blockHeight(%rip)
movl $1, blockDepth(%rip)
cmpl $1, %r14d
jle .L114
movl $1, %ebx
leaq .LC16(%rip), %r15
jmp .L127
.L166:
movslq %ebx, %rax
leaq 0(,%rax,8), %r13
movq (%r12,%rax,8), %rbp
movq %r15, %rsi
movq %rbp, %rdi
call strcmp@PLT
testl %eax, %eax
jne .L115
leal 2(%rbx), %eax
cmpl %r14d, %eax
jg .L116
movq 8(%r12,%r13), %rbp
movq %rbp, %rdi
call strlen@PLT
movq %rax, %r8
leaq 64(%rsp), %rdi
movq %rbp, %rcx
movq 72(%rsp), %rdx
movl $0, %esi
.LEHB16:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm@PLT
jmp .L158
.L116:
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L159
.L115:
leaq .LC18(%rip), %rsi
movq %rbp, %rdi
call strcmp@PLT
testl %eax, %eax
jne .L119
leal 2(%rbx), %eax
cmpl %r14d, %eax
jg .L120
movq 8(%r12,%r13), %rbp
movq %rbp, %rdi
call strlen@PLT
movq %rax, %r8
leaq 96(%rsp), %rdi
movq %rbp, %rcx
movq 104(%rsp), %rdx
movl $0, %esi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm@PLT
jmp .L160
.L120:
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L161
.L119:
leaq .LC20(%rip), %rsi
movq %rbp, %rdi
call strcmp@PLT
testl %eax, %eax
jne .L121
leal 2(%rbx), %eax
cmpl %r14d, %eax
jg .L122
movq 8(%r12,%r13), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, timeSteps(%rip)
movl $2, %eax
jmp .L117
.L122:
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L162
.L121:
leaq .LC22(%rip), %rsi
movq %rbp, %rdi
call strcmp@PLT
testl %eax, %eax
jne .L123
leal 4(%rbx), %eax
cmpl %r14d, %eax
jg .L124
movq 8(%r12,%r13), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, gridWidth(%rip)
movq 16(%r12,%r13), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, gridHeight(%rip)
movq 24(%r12,%r13), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, gridDepth(%rip)
movl $4, %eax
jmp .L117
.L124:
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L163
.L123:
leaq .LC24(%rip), %rsi
movq %rbp, %rdi
call strcmp@PLT
testl %eax, %eax
jne .L125
leal 4(%rbx), %eax
cmpl %r14d, %eax
jg .L126
movq 8(%r12,%r13), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, blockWidth(%rip)
movq 16(%r12,%r13), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, blockHeight(%rip)
movq 24(%r12,%r13), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, blockDepth(%rip)
movl $4, %eax
jmp .L117
.L126:
leaq .LC25(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L164
.L125:
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC27(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L165
.L158:
movl $2, %eax
.L117:
addl %eax, %ebx
cmpl %ebx, %r14d
jle .L114
.L127:
movl %ebx, %edx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L166
.L160:
movl $2, %eax
jmp .L117
.L114:
movl gridWidth(%rip), %ebx
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl blockWidth(%rip), %xmm1
divss %xmm1, %xmm0
call ceilf@PLT
cvttss2sil %xmm0, %eax
movl %eax, gridWidthBlocks(%rip)
movl gridHeight(%rip), %r12d
pxor %xmm0, %xmm0
cvtsi2ssl %r12d, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl blockHeight(%rip), %xmm1
divss %xmm1, %xmm0
call ceilf@PLT
cvttss2sil %xmm0, %eax
movl %eax, gridHeightBlocks(%rip)
movl gridDepth(%rip), %ebp
pxor %xmm0, %xmm0
cvtsi2ssl %ebp, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl blockDepth(%rip), %xmm1
divss %xmm1, %xmm0
call ceilf@PLT
cvttss2sil %xmm0, %eax
movl %eax, gridDepthBlocks(%rip)
imull %r12d, %ebx
imull %ebp, %ebx
movl %ebx, gridArea(%rip)
leaq .LC28(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rdi
leaq .LC29(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC30(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 104(%rsp), %rdx
movq 96(%rsp), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rdi
leaq .LC29(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl timeSteps(%rip), %edx
leaq .LC31(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl gridDepth(%rip), %r8d
movl gridHeight(%rip), %ecx
movl gridWidth(%rip), %edx
leaq .LC32(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl blockDepth(%rip), %r8d
movl blockHeight(%rip), %ecx
movl blockWidth(%rip), %edx
leaq .LC33(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl gridDepthBlocks(%rip), %r8d
movl gridHeightBlocks(%rip), %ecx
movl gridWidthBlocks(%rip), %edx
leaq .LC34(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC35(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq gridWidth(%rip), %rsi
leaq _ZL11gridWidth_d(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq gridHeight(%rip), %rsi
leaq _ZL12gridHeight_d(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq gridDepth(%rip), %rsi
leaq _ZL11gridDepth_d(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq blockWidth(%rip), %rsi
leaq _ZL12blockWidth_d(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq blockHeight(%rip), %rsi
leaq _ZL13blockHeight_d(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq blockDepth(%rip), %rsi
leaq _ZL12blockDepth_d(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq gridWidthBlocks(%rip), %rsi
leaq _ZL17gridWidthBlocks_d(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq gridHeightBlocks(%rip), %rsi
leaq _ZL18gridHeightBlocks_d(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq gridDepthBlocks(%rip), %rsi
leaq _ZL17gridDepthBlocks_d(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl gridWidthBlocks(%rip), %eax
movl %eax, 40(%rsp)
movl gridHeightBlocks(%rip), %eax
movl %eax, 44(%rsp)
movl gridDepthBlocks(%rip), %eax
movl %eax, 48(%rsp)
movl blockWidth(%rip), %eax
movl %eax, 52(%rsp)
movl blockHeight(%rip), %eax
movl %eax, 56(%rsp)
movl blockDepth(%rip), %eax
movl %eax, 60(%rsp)
movl gridWidth(%rip), %ebp
imull gridHeight(%rip), %ebp
imull gridDepth(%rip), %ebp
movslq %ebp, %rbp
movl $1, %esi
movq %rbp, %rdi
call calloc@PLT
movq %rax, %r12
leaq 24(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %r12, %rsi
call _Z12readTextReprRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPb
movl $1, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
cmpl $0, timeSteps(%rip)
jle .L128
movl $0, %ebx
leaq _ZSt4cout(%rip), %r13
jmp .L131
.L168:
testl %eax, %eax
jne .L129
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z27__device_stub__Z6solverPbS_PbS_
.L129:
call cudaDeviceSynchronize@PLT
movq 24(%rsp), %rax
movq 32(%rsp), %rdx
movq %rdx, 24(%rsp)
movq %rax, 32(%rsp)
call cudaGetLastError@PLT
testl %eax, %eax
jne .L167
.L130:
addl $1, %ebx
cmpl %ebx, timeSteps(%rip)
jle .L128
.L131:
movl 60(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movq 40(%rsp), %rdi
movl 48(%rsp), %esi
call __cudaPushCallConfiguration@PLT
jmp .L168
.L167:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L130
.L128:
movl $2, %ecx
movq %rbp, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq 96(%rsp), %rdi
movq %r12, %rsi
call _Z13writeTextReprRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPb
movq %r12, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq 8(%rsp), %rcx
subq %rcx, %rax
movl $1000000, %ecx
cqto
idivq %rcx
movq %rax, %rdx
leaq .LC36(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.LEHE16:
movl $0, %ebx
.L118:
leaq 96(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L169
movl %ebx, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L159:
.cfi_restore_state
movl $1, %ebx
jmp .L118
.L161:
movl $1, %ebx
jmp .L118
.L162:
movl $1, %ebx
jmp .L118
.L163:
movl $1, %ebx
jmp .L118
.L164:
movl $1, %ebx
jmp .L118
.L165:
movl $1, %ebx
jmp .L118
.L145:
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L133:
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
je .L134
call __stack_chk_fail@PLT
.L144:
endbr64
movq %rax, %rbx
jmp .L133
.L134:
movq %rbx, %rdi
.LEHB17:
call _Unwind_Resume@PLT
.LEHE17:
.L169:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3903:
.section .gcc_except_table
.LLSDA3903:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3903-.LLSDACSB3903
.LLSDACSB3903:
.uleb128 .LEHB14-.LFB3903
.uleb128 .LEHE14-.LEHB14
.uleb128 0
.uleb128 0
.uleb128 .LEHB15-.LFB3903
.uleb128 .LEHE15-.LEHB15
.uleb128 .L144-.LFB3903
.uleb128 0
.uleb128 .LEHB16-.LFB3903
.uleb128 .LEHE16-.LEHB16
.uleb128 .L145-.LFB3903
.uleb128 0
.uleb128 .LEHB17-.LFB3903
.uleb128 .LEHE17-.LEHB17
.uleb128 0
.uleb128 0
.LLSDACSE3903:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl timeSteps
.bss
.align 4
.type timeSteps, @object
.size timeSteps, 4
timeSteps:
.zero 4
.local _ZL17gridDepthBlocks_d
.comm _ZL17gridDepthBlocks_d,4,4
.local _ZL18gridHeightBlocks_d
.comm _ZL18gridHeightBlocks_d,4,4
.local _ZL17gridWidthBlocks_d
.comm _ZL17gridWidthBlocks_d,4,4
.local _ZL12blockDepth_d
.comm _ZL12blockDepth_d,4,4
.local _ZL13blockHeight_d
.comm _ZL13blockHeight_d,4,4
.local _ZL12blockWidth_d
.comm _ZL12blockWidth_d,4,4
.local _ZL11gridDepth_d
.comm _ZL11gridDepth_d,4,4
.local _ZL12gridHeight_d
.comm _ZL12gridHeight_d,4,4
.local _ZL11gridWidth_d
.comm _ZL11gridWidth_d,4,4
.globl gridArea
.align 4
.type gridArea, @object
.size gridArea, 4
gridArea:
.zero 4
.globl gridDepthBlocks
.align 4
.type gridDepthBlocks, @object
.size gridDepthBlocks, 4
gridDepthBlocks:
.zero 4
.globl gridHeightBlocks
.align 4
.type gridHeightBlocks, @object
.size gridHeightBlocks, 4
gridHeightBlocks:
.zero 4
.globl gridWidthBlocks
.align 4
.type gridWidthBlocks, @object
.size gridWidthBlocks, 4
gridWidthBlocks:
.zero 4
.globl blockDepth
.align 4
.type blockDepth, @object
.size blockDepth, 4
blockDepth:
.zero 4
.globl blockHeight
.align 4
.type blockHeight, @object
.size blockHeight, 4
blockHeight:
.zero 4
.globl blockWidth
.align 4
.type blockWidth, @object
.size blockWidth, 4
blockWidth:
.zero 4
.globl gridDepth
.align 4
.type gridDepth, @object
.size gridDepth, 4
gridDepth:
.zero 4
.globl gridHeight
.align 4
.type gridHeight, @object
.size gridHeight, 4
gridHeight:
.zero 4
.globl gridWidth
.align 4
.type gridWidth, @object
.size gridWidth, 4
gridWidth:
.zero 4
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include<stdlib.h>
#include<iostream>
#include<cmath>
#include<fstream>
#include<chrono>
//shared host/device constants
int gridWidth,gridHeight,gridDepth,blockWidth,blockHeight,blockDepth,gridWidthBlocks,gridHeightBlocks,gridDepthBlocks,gridArea;
__constant__ int gridWidth_d,gridHeight_d,gridDepth_d,blockWidth_d,blockHeight_d,blockDepth_d,gridWidthBlocks_d,gridHeightBlocks_d,gridDepthBlocks_d;
//host only constants
int timeSteps;
__device__ int arrayPos(const int &x,const int &y,const int &z){
return (z*gridWidth_d*gridHeight_d)+(y*gridWidth_d)+x;
}
__global__ void solver(bool *grid,bool *grid1){
int xpos = (blockIdx.x*blockWidth_d)+threadIdx.x;
int ypos = (blockIdx.y*blockHeight_d)+threadIdx.y;
int zpos = (blockIdx.z*blockDepth_d)+threadIdx.z;
if(xpos>0 && xpos<gridWidth_d-1 && ypos>0 && ypos<gridHeight_d-1 && zpos>0 && zpos<gridDepth_d-1){
int neighbors = grid[arrayPos(xpos+1,ypos,zpos)]+grid[arrayPos(xpos-1,ypos,zpos)]
+grid[arrayPos(xpos,ypos+1,zpos)]+grid[arrayPos(xpos,ypos-1,zpos)]
+grid[arrayPos(xpos,ypos,zpos+1)]+grid[arrayPos(xpos,ypos,zpos-1)];
if(grid[arrayPos(xpos,ypos,zpos)]){
if(neighbors<2 || neighbors>3){
grid1[arrayPos(xpos,ypos,zpos)] = false;
}else{
grid1[arrayPos(xpos,ypos,zpos)] = true;
}
}else{
if(neighbors==3){
grid1[arrayPos(xpos,ypos,zpos)] = true;
}else{
grid1[arrayPos(xpos,ypos,zpos)] = false;
}
}
}
}
//helper function to read grid from a text file
void readTextRepr(const std::string& filename,bool *array){
std::ifstream file(filename);
std::string str;
int index=0;
while(std::getline(file,str)){
if(str!="---"){
for(int i=0;i<str.length();i++){
//stop reading if file is greater than arrayLength
if(index<gridArea){
if(str[i]!='\n'){
if(str[i]=='#'){
array[index]=true;
}else{
array[index]=false;
}
index++;
}
}
}
}
}
//fill in excess space with falses if file is too short
if(index<gridArea){
for(int i=index;i<gridArea;i++){
array[index]=false;
}
}
}
//helper function to write grid to a text file
void writeTextRepr(const std::string& filename,bool *array){
std::ofstream file(filename);
for(int i=0;i<gridArea;i++){
if(array[i]){
file<<'#';
}else{
file<<' ';
}
if((i+1)%gridWidth==0){
file<<'\n';
}
if((i+1)%(gridWidth*gridHeight)==0){
file<<"---\n";
}
}
}
int main(int argc, const char * argv[]){
//start clock
auto startTime = std::chrono::high_resolution_clock::now();
//input and output files
std::string inFile = "in.txt";
std::string outFile = "out.txt";
//time of simulation
timeSteps = 1;
//dimensions of the grid
gridWidth = 16;
gridHeight = 16;
gridDepth = 16;
/*
Speed testing with varying grid and block sizes, using both 3D and 2D kernel implementations
16x16x16 grid, 2mil steps:
3D Kernel
16x16x1 = 18921ms
8x8x16 = 21150ms
8x8x8 = 19432ms
4x4x4 = 21614ms
2x2x2 = 24362ms
2D Kernel
16x16 = 19389ms
8x8 = 19425ms
4x4 = 19992ms
64x64x64 grid, 2mil steps:
3D Kernel
16x16x1 = 44162ms
8x8x8 = 61221ms
8x8x4 = 62442ms
2D Kernel
16x16 = 47543ms
2048x2048x128 grid, 100 steps:
3D Kernel
16x16x1 = 15065ms
8x8x8 = 18386ms
The fastest block size across both small and large grids appears to be 16x16x1, using the 3D kernel
*/
blockWidth = 16;
blockHeight = 16;
blockDepth = 1;
//handle command line arguments
int optionLen = 0;
for(int i=1;i<argc;i+=optionLen){
printf("%d",i);
if(strcmp(argv[i],"-i")==0){
optionLen = 2;
if(i+optionLen<=argc){
inFile = argv[i+1];
}else{
printf("Error: Missing arguments for -i\n");
return 1;
}
}else if(strcmp(argv[i],"-o")==0){
optionLen = 2;
if(i+optionLen<=argc){
outFile = argv[i+1];
}else{
printf("Error: Missing arguments for -o\n");
return 1;
}
}else if(strcmp(argv[i],"-t")==0){
optionLen = 2;
if(i+optionLen<=argc){
timeSteps = strtol(argv[i+1],NULL,10);
}else{
printf("Error: Missing arguments for -t\n");
return 1;
}
}else if(strcmp(argv[i],"-g")==0){
optionLen = 4;
if(i+optionLen<=argc){
gridWidth = strtol(argv[i+1],NULL,10);
gridHeight = strtol(argv[i+2],NULL,10);
gridDepth = strtol(argv[i+3],NULL,10);
}else{
printf("Error: Missing arguments for -g\n");
return 1;
}
}else if(strcmp(argv[i],"-b")==0){
optionLen = 4;
if(i+optionLen<=argc){
blockWidth = strtol(argv[i+1],NULL,10);
blockHeight = strtol(argv[i+2],NULL,10);
blockDepth = strtol(argv[i+3],NULL,10);
}else{
printf("Error: Missing arguments for -b\n");
return 1;
}
}else{
printf("Error: Parameters must be of form:\n");
printf("./game [-i infile] [-o outfile] [-t timesteps] [-g griddimensions] [-b blockdimensions]\n");
return 1;
}
}
//derived values
gridWidthBlocks = std::ceil((float)gridWidth/(float)blockWidth);
gridHeightBlocks = std::ceil((float)gridHeight/(float)blockHeight);
gridDepthBlocks = std::ceil((float)gridDepth/(float)blockDepth);
gridArea = gridWidth*gridHeight*gridDepth;
std::cout << "In file = " << inFile << "\n";
std::cout << "Out file = " << outFile << "\n";
printf("Time steps = %d\n",timeSteps);
printf("Grid dimensions = %dx%dx%d\n",gridWidth,gridHeight,gridDepth);
printf("Block dimensions = %dx%dx%d\n",blockWidth,blockHeight,blockDepth);
printf("Grid in blocks = %dx%dx%d\n",gridWidthBlocks,gridHeightBlocks,gridDepthBlocks);
printf("...");
//set device symbols to dimensions of grid,block,etc.
cudaMemcpyToSymbol(*(&gridWidth_d),&gridWidth,sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(*(&gridHeight_d),&gridHeight,sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(*(&gridDepth_d),&gridDepth,sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(*(&blockWidth_d),&blockWidth,sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(*(&blockHeight_d),&blockHeight,sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(*(&blockDepth_d),&blockDepth,sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(*(&gridWidthBlocks_d),&gridWidthBlocks,sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(*(&gridHeightBlocks_d),&gridHeightBlocks,sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(*(&gridDepthBlocks_d),&gridDepthBlocks,sizeof(int),0,cudaMemcpyHostToDevice);
dim3 numBlocks(gridWidthBlocks,gridHeightBlocks,gridDepthBlocks);
dim3 blockSize(blockWidth,blockHeight,blockDepth);
size_t gridSize = gridWidth*gridHeight*gridDepth;
//device+host grid arrays
bool *grid_h;
bool *grid_d,*grid1_d;
//allocate host memory
grid_h = (bool *)calloc(gridSize,sizeof(bool));
//allocate device memory
cudaMalloc((void **)&grid_d, gridSize);
cudaMalloc((void **)&grid1_d, gridSize);
//load grid
readTextRepr(inFile,grid_h);
//only copy first grid to device, second one is computed by kernel
cudaMemcpy(grid_d,grid_h,gridSize,cudaMemcpyHostToDevice);
for(int i=0;i<timeSteps;i++){
solver<<<numBlocks,blockSize>>>(grid_d,grid1_d);
cudaDeviceSynchronize();
std::swap(grid_d,grid1_d);
cudaError_t error = cudaGetLastError();
if(error != cudaSuccess){
std::cout << cudaGetErrorString(error) << std::endl;
}
}
//only copy first grid to host, since it was computed and then swapped by kernel
cudaMemcpy(grid_h,grid_d,gridSize,cudaMemcpyDeviceToHost);
//output grid
writeTextRepr(outFile,grid_h);
//free host memory
free(grid_h);
//free device memory
cudaFree(grid_d);
cudaFree(grid1_d);
//end clock
auto endTime = std::chrono::high_resolution_clock::now();
auto timePassed = std::chrono::duration_cast<std::chrono::milliseconds>(endTime-startTime).count();
printf("Ran in %ld ms\n",timePassed);
return 0;
}
|
#include <hip/hip_runtime.h>
#include<stdlib.h>
#include<iostream>
#include<cmath>
#include<fstream>
#include<chrono>
//shared host/device constants
int gridWidth,gridHeight,gridDepth,blockWidth,blockHeight,blockDepth,gridWidthBlocks,gridHeightBlocks,gridDepthBlocks,gridArea;
__constant__ int gridWidth_d,gridHeight_d,gridDepth_d,blockWidth_d,blockHeight_d,blockDepth_d,gridWidthBlocks_d,gridHeightBlocks_d,gridDepthBlocks_d;
//host only constants
int timeSteps;
__device__ int arrayPos(const int &x,const int &y,const int &z){
return (z*gridWidth_d*gridHeight_d)+(y*gridWidth_d)+x;
}
__global__ void solver(bool *grid,bool *grid1){
int xpos = (blockIdx.x*blockWidth_d)+threadIdx.x;
int ypos = (blockIdx.y*blockHeight_d)+threadIdx.y;
int zpos = (blockIdx.z*blockDepth_d)+threadIdx.z;
if(xpos>0 && xpos<gridWidth_d-1 && ypos>0 && ypos<gridHeight_d-1 && zpos>0 && zpos<gridDepth_d-1){
int neighbors = grid[arrayPos(xpos+1,ypos,zpos)]+grid[arrayPos(xpos-1,ypos,zpos)]
+grid[arrayPos(xpos,ypos+1,zpos)]+grid[arrayPos(xpos,ypos-1,zpos)]
+grid[arrayPos(xpos,ypos,zpos+1)]+grid[arrayPos(xpos,ypos,zpos-1)];
if(grid[arrayPos(xpos,ypos,zpos)]){
if(neighbors<2 || neighbors>3){
grid1[arrayPos(xpos,ypos,zpos)] = false;
}else{
grid1[arrayPos(xpos,ypos,zpos)] = true;
}
}else{
if(neighbors==3){
grid1[arrayPos(xpos,ypos,zpos)] = true;
}else{
grid1[arrayPos(xpos,ypos,zpos)] = false;
}
}
}
}
//helper function to read grid from a text file
void readTextRepr(const std::string& filename,bool *array){
std::ifstream file(filename);
std::string str;
int index=0;
while(std::getline(file,str)){
if(str!="---"){
for(int i=0;i<str.length();i++){
//stop reading if file is greater than arrayLength
if(index<gridArea){
if(str[i]!='\n'){
if(str[i]=='#'){
array[index]=true;
}else{
array[index]=false;
}
index++;
}
}
}
}
}
//fill in excess space with falses if file is too short
if(index<gridArea){
for(int i=index;i<gridArea;i++){
array[index]=false;
}
}
}
//helper function to write grid to a text file
void writeTextRepr(const std::string& filename,bool *array){
std::ofstream file(filename);
for(int i=0;i<gridArea;i++){
if(array[i]){
file<<'#';
}else{
file<<' ';
}
if((i+1)%gridWidth==0){
file<<'\n';
}
if((i+1)%(gridWidth*gridHeight)==0){
file<<"---\n";
}
}
}
int main(int argc, const char * argv[]){
//start clock
auto startTime = std::chrono::high_resolution_clock::now();
//input and output files
std::string inFile = "in.txt";
std::string outFile = "out.txt";
//time of simulation
timeSteps = 1;
//dimensions of the grid
gridWidth = 16;
gridHeight = 16;
gridDepth = 16;
/*
Speed testing with varying grid and block sizes, using both 3D and 2D kernel implementations
16x16x16 grid, 2mil steps:
3D Kernel
16x16x1 = 18921ms
8x8x16 = 21150ms
8x8x8 = 19432ms
4x4x4 = 21614ms
2x2x2 = 24362ms
2D Kernel
16x16 = 19389ms
8x8 = 19425ms
4x4 = 19992ms
64x64x64 grid, 2mil steps:
3D Kernel
16x16x1 = 44162ms
8x8x8 = 61221ms
8x8x4 = 62442ms
2D Kernel
16x16 = 47543ms
2048x2048x128 grid, 100 steps:
3D Kernel
16x16x1 = 15065ms
8x8x8 = 18386ms
The fastest block size across both small and large grids appears to be 16x16x1, using the 3D kernel
*/
blockWidth = 16;
blockHeight = 16;
blockDepth = 1;
//handle command line arguments
int optionLen = 0;
for(int i=1;i<argc;i+=optionLen){
printf("%d",i);
if(strcmp(argv[i],"-i")==0){
optionLen = 2;
if(i+optionLen<=argc){
inFile = argv[i+1];
}else{
printf("Error: Missing arguments for -i\n");
return 1;
}
}else if(strcmp(argv[i],"-o")==0){
optionLen = 2;
if(i+optionLen<=argc){
outFile = argv[i+1];
}else{
printf("Error: Missing arguments for -o\n");
return 1;
}
}else if(strcmp(argv[i],"-t")==0){
optionLen = 2;
if(i+optionLen<=argc){
timeSteps = strtol(argv[i+1],NULL,10);
}else{
printf("Error: Missing arguments for -t\n");
return 1;
}
}else if(strcmp(argv[i],"-g")==0){
optionLen = 4;
if(i+optionLen<=argc){
gridWidth = strtol(argv[i+1],NULL,10);
gridHeight = strtol(argv[i+2],NULL,10);
gridDepth = strtol(argv[i+3],NULL,10);
}else{
printf("Error: Missing arguments for -g\n");
return 1;
}
}else if(strcmp(argv[i],"-b")==0){
optionLen = 4;
if(i+optionLen<=argc){
blockWidth = strtol(argv[i+1],NULL,10);
blockHeight = strtol(argv[i+2],NULL,10);
blockDepth = strtol(argv[i+3],NULL,10);
}else{
printf("Error: Missing arguments for -b\n");
return 1;
}
}else{
printf("Error: Parameters must be of form:\n");
printf("./game [-i infile] [-o outfile] [-t timesteps] [-g griddimensions] [-b blockdimensions]\n");
return 1;
}
}
//derived values
gridWidthBlocks = std::ceil((float)gridWidth/(float)blockWidth);
gridHeightBlocks = std::ceil((float)gridHeight/(float)blockHeight);
gridDepthBlocks = std::ceil((float)gridDepth/(float)blockDepth);
gridArea = gridWidth*gridHeight*gridDepth;
std::cout << "In file = " << inFile << "\n";
std::cout << "Out file = " << outFile << "\n";
printf("Time steps = %d\n",timeSteps);
printf("Grid dimensions = %dx%dx%d\n",gridWidth,gridHeight,gridDepth);
printf("Block dimensions = %dx%dx%d\n",blockWidth,blockHeight,blockDepth);
printf("Grid in blocks = %dx%dx%d\n",gridWidthBlocks,gridHeightBlocks,gridDepthBlocks);
printf("...");
//set device symbols to dimensions of grid,block,etc.
hipMemcpyToSymbol(HIP_SYMBOL(*(&gridWidth_d)),&gridWidth,sizeof(int),0,hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(*(&gridHeight_d)),&gridHeight,sizeof(int),0,hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(*(&gridDepth_d)),&gridDepth,sizeof(int),0,hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(*(&blockWidth_d)),&blockWidth,sizeof(int),0,hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(*(&blockHeight_d)),&blockHeight,sizeof(int),0,hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(*(&blockDepth_d)),&blockDepth,sizeof(int),0,hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(*(&gridWidthBlocks_d)),&gridWidthBlocks,sizeof(int),0,hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(*(&gridHeightBlocks_d)),&gridHeightBlocks,sizeof(int),0,hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(*(&gridDepthBlocks_d)),&gridDepthBlocks,sizeof(int),0,hipMemcpyHostToDevice);
dim3 numBlocks(gridWidthBlocks,gridHeightBlocks,gridDepthBlocks);
dim3 blockSize(blockWidth,blockHeight,blockDepth);
size_t gridSize = gridWidth*gridHeight*gridDepth;
//device+host grid arrays
bool *grid_h;
bool *grid_d,*grid1_d;
//allocate host memory
grid_h = (bool *)calloc(gridSize,sizeof(bool));
//allocate device memory
hipMalloc((void **)&grid_d, gridSize);
hipMalloc((void **)&grid1_d, gridSize);
//load grid
readTextRepr(inFile,grid_h);
//only copy first grid to device, second one is computed by kernel
hipMemcpy(grid_d,grid_h,gridSize,hipMemcpyHostToDevice);
for(int i=0;i<timeSteps;i++){
solver<<<numBlocks,blockSize>>>(grid_d,grid1_d);
hipDeviceSynchronize();
std::swap(grid_d,grid1_d);
hipError_t error = hipGetLastError();
if(error != hipSuccess){
std::cout << hipGetErrorString(error) << std::endl;
}
}
//only copy first grid to host, since it was computed and then swapped by kernel
hipMemcpy(grid_h,grid_d,gridSize,hipMemcpyDeviceToHost);
//output grid
writeTextRepr(outFile,grid_h);
//free host memory
free(grid_h);
//free device memory
hipFree(grid_d);
hipFree(grid1_d);
//end clock
auto endTime = std::chrono::high_resolution_clock::now();
auto timePassed = std::chrono::duration_cast<std::chrono::milliseconds>(endTime-startTime).count();
printf("Ran in %ld ms\n",timePassed);
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include<stdlib.h>
#include<iostream>
#include<cmath>
#include<fstream>
#include<chrono>
//shared host/device constants
int gridWidth,gridHeight,gridDepth,blockWidth,blockHeight,blockDepth,gridWidthBlocks,gridHeightBlocks,gridDepthBlocks,gridArea;
__constant__ int gridWidth_d,gridHeight_d,gridDepth_d,blockWidth_d,blockHeight_d,blockDepth_d,gridWidthBlocks_d,gridHeightBlocks_d,gridDepthBlocks_d;
//host only constants
int timeSteps;
__device__ int arrayPos(const int &x,const int &y,const int &z){
return (z*gridWidth_d*gridHeight_d)+(y*gridWidth_d)+x;
}
__global__ void solver(bool *grid,bool *grid1){
int xpos = (blockIdx.x*blockWidth_d)+threadIdx.x;
int ypos = (blockIdx.y*blockHeight_d)+threadIdx.y;
int zpos = (blockIdx.z*blockDepth_d)+threadIdx.z;
if(xpos>0 && xpos<gridWidth_d-1 && ypos>0 && ypos<gridHeight_d-1 && zpos>0 && zpos<gridDepth_d-1){
int neighbors = grid[arrayPos(xpos+1,ypos,zpos)]+grid[arrayPos(xpos-1,ypos,zpos)]
+grid[arrayPos(xpos,ypos+1,zpos)]+grid[arrayPos(xpos,ypos-1,zpos)]
+grid[arrayPos(xpos,ypos,zpos+1)]+grid[arrayPos(xpos,ypos,zpos-1)];
if(grid[arrayPos(xpos,ypos,zpos)]){
if(neighbors<2 || neighbors>3){
grid1[arrayPos(xpos,ypos,zpos)] = false;
}else{
grid1[arrayPos(xpos,ypos,zpos)] = true;
}
}else{
if(neighbors==3){
grid1[arrayPos(xpos,ypos,zpos)] = true;
}else{
grid1[arrayPos(xpos,ypos,zpos)] = false;
}
}
}
}
//helper function to read grid from a text file
void readTextRepr(const std::string& filename,bool *array){
std::ifstream file(filename);
std::string str;
int index=0;
while(std::getline(file,str)){
if(str!="---"){
for(int i=0;i<str.length();i++){
//stop reading if file is greater than arrayLength
if(index<gridArea){
if(str[i]!='\n'){
if(str[i]=='#'){
array[index]=true;
}else{
array[index]=false;
}
index++;
}
}
}
}
}
//fill in excess space with falses if file is too short
if(index<gridArea){
for(int i=index;i<gridArea;i++){
array[index]=false;
}
}
}
//helper function to write grid to a text file
void writeTextRepr(const std::string& filename,bool *array){
std::ofstream file(filename);
for(int i=0;i<gridArea;i++){
if(array[i]){
file<<'#';
}else{
file<<' ';
}
if((i+1)%gridWidth==0){
file<<'\n';
}
if((i+1)%(gridWidth*gridHeight)==0){
file<<"---\n";
}
}
}
int main(int argc, const char * argv[]){
//start clock
auto startTime = std::chrono::high_resolution_clock::now();
//input and output files
std::string inFile = "in.txt";
std::string outFile = "out.txt";
//time of simulation
timeSteps = 1;
//dimensions of the grid
gridWidth = 16;
gridHeight = 16;
gridDepth = 16;
/*
Speed testing with varying grid and block sizes, using both 3D and 2D kernel implementations
16x16x16 grid, 2mil steps:
3D Kernel
16x16x1 = 18921ms
8x8x16 = 21150ms
8x8x8 = 19432ms
4x4x4 = 21614ms
2x2x2 = 24362ms
2D Kernel
16x16 = 19389ms
8x8 = 19425ms
4x4 = 19992ms
64x64x64 grid, 2mil steps:
3D Kernel
16x16x1 = 44162ms
8x8x8 = 61221ms
8x8x4 = 62442ms
2D Kernel
16x16 = 47543ms
2048x2048x128 grid, 100 steps:
3D Kernel
16x16x1 = 15065ms
8x8x8 = 18386ms
The fastest block size across both small and large grids appears to be 16x16x1, using the 3D kernel
*/
blockWidth = 16;
blockHeight = 16;
blockDepth = 1;
//handle command line arguments
int optionLen = 0;
for(int i=1;i<argc;i+=optionLen){
printf("%d",i);
if(strcmp(argv[i],"-i")==0){
optionLen = 2;
if(i+optionLen<=argc){
inFile = argv[i+1];
}else{
printf("Error: Missing arguments for -i\n");
return 1;
}
}else if(strcmp(argv[i],"-o")==0){
optionLen = 2;
if(i+optionLen<=argc){
outFile = argv[i+1];
}else{
printf("Error: Missing arguments for -o\n");
return 1;
}
}else if(strcmp(argv[i],"-t")==0){
optionLen = 2;
if(i+optionLen<=argc){
timeSteps = strtol(argv[i+1],NULL,10);
}else{
printf("Error: Missing arguments for -t\n");
return 1;
}
}else if(strcmp(argv[i],"-g")==0){
optionLen = 4;
if(i+optionLen<=argc){
gridWidth = strtol(argv[i+1],NULL,10);
gridHeight = strtol(argv[i+2],NULL,10);
gridDepth = strtol(argv[i+3],NULL,10);
}else{
printf("Error: Missing arguments for -g\n");
return 1;
}
}else if(strcmp(argv[i],"-b")==0){
optionLen = 4;
if(i+optionLen<=argc){
blockWidth = strtol(argv[i+1],NULL,10);
blockHeight = strtol(argv[i+2],NULL,10);
blockDepth = strtol(argv[i+3],NULL,10);
}else{
printf("Error: Missing arguments for -b\n");
return 1;
}
}else{
printf("Error: Parameters must be of form:\n");
printf("./game [-i infile] [-o outfile] [-t timesteps] [-g griddimensions] [-b blockdimensions]\n");
return 1;
}
}
//derived values
gridWidthBlocks = std::ceil((float)gridWidth/(float)blockWidth);
gridHeightBlocks = std::ceil((float)gridHeight/(float)blockHeight);
gridDepthBlocks = std::ceil((float)gridDepth/(float)blockDepth);
gridArea = gridWidth*gridHeight*gridDepth;
std::cout << "In file = " << inFile << "\n";
std::cout << "Out file = " << outFile << "\n";
printf("Time steps = %d\n",timeSteps);
printf("Grid dimensions = %dx%dx%d\n",gridWidth,gridHeight,gridDepth);
printf("Block dimensions = %dx%dx%d\n",blockWidth,blockHeight,blockDepth);
printf("Grid in blocks = %dx%dx%d\n",gridWidthBlocks,gridHeightBlocks,gridDepthBlocks);
printf("...");
//set device symbols to dimensions of grid,block,etc.
hipMemcpyToSymbol(HIP_SYMBOL(*(&gridWidth_d)),&gridWidth,sizeof(int),0,hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(*(&gridHeight_d)),&gridHeight,sizeof(int),0,hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(*(&gridDepth_d)),&gridDepth,sizeof(int),0,hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(*(&blockWidth_d)),&blockWidth,sizeof(int),0,hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(*(&blockHeight_d)),&blockHeight,sizeof(int),0,hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(*(&blockDepth_d)),&blockDepth,sizeof(int),0,hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(*(&gridWidthBlocks_d)),&gridWidthBlocks,sizeof(int),0,hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(*(&gridHeightBlocks_d)),&gridHeightBlocks,sizeof(int),0,hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(*(&gridDepthBlocks_d)),&gridDepthBlocks,sizeof(int),0,hipMemcpyHostToDevice);
dim3 numBlocks(gridWidthBlocks,gridHeightBlocks,gridDepthBlocks);
dim3 blockSize(blockWidth,blockHeight,blockDepth);
size_t gridSize = gridWidth*gridHeight*gridDepth;
//device+host grid arrays
bool *grid_h;
bool *grid_d,*grid1_d;
//allocate host memory
grid_h = (bool *)calloc(gridSize,sizeof(bool));
//allocate device memory
hipMalloc((void **)&grid_d, gridSize);
hipMalloc((void **)&grid1_d, gridSize);
//load grid
readTextRepr(inFile,grid_h);
//only copy first grid to device, second one is computed by kernel
hipMemcpy(grid_d,grid_h,gridSize,hipMemcpyHostToDevice);
for(int i=0;i<timeSteps;i++){
solver<<<numBlocks,blockSize>>>(grid_d,grid1_d);
hipDeviceSynchronize();
std::swap(grid_d,grid1_d);
hipError_t error = hipGetLastError();
if(error != hipSuccess){
std::cout << hipGetErrorString(error) << std::endl;
}
}
//only copy first grid to host, since it was computed and then swapped by kernel
hipMemcpy(grid_h,grid_d,gridSize,hipMemcpyDeviceToHost);
//output grid
writeTextRepr(outFile,grid_h);
//free host memory
free(grid_h);
//free device memory
hipFree(grid_d);
hipFree(grid1_d);
//end clock
auto endTime = std::chrono::high_resolution_clock::now();
auto timePassed = std::chrono::duration_cast<std::chrono::milliseconds>(endTime-startTime).count();
printf("Ran in %ld ms\n",timePassed);
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6solverPbS_
.globl _Z6solverPbS_
.p2align 8
.type _Z6solverPbS_,@function
_Z6solverPbS_:
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, blockWidth_d@rel32@lo+4
s_addc_u32 s3, s3, blockWidth_d@rel32@hi+12
v_and_b32_e32 v3, 0x3ff, v0
s_load_b32 s2, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s13, v[3:4]
s_mov_b32 s2, exec_lo
v_cmpx_lt_i32_e32 0, v1
s_cbranch_execz .LBB0_15
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, blockHeight_d@rel32@lo+4
s_addc_u32 s3, s3, blockHeight_d@rel32@hi+12
v_bfe_u32 v4, v0, 10, 10
s_load_b32 s5, s[2:3], 0x0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, gridWidth_d@rel32@lo+4
s_addc_u32 s3, s3, gridWidth_d@rel32@hi+12
s_load_b32 s4, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, s5, s14, v[4:5]
s_add_i32 s2, s4, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
v_cmp_lt_i32_e64 s2, 0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_15
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, blockDepth_d@rel32@lo+4
s_addc_u32 s3, s3, blockDepth_d@rel32@hi+12
v_bfe_u32 v0, v0, 20, 10
s_load_b32 s6, s[2:3], 0x0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, gridHeight_d@rel32@lo+4
s_addc_u32 s3, s3, gridHeight_d@rel32@hi+12
s_load_b32 s5, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[3:4], null, s6, s15, v[0:1]
s_add_i32 s2, s5, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s2, v2
v_cmp_lt_i32_e64 s2, 0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_15
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, gridDepth_d@rel32@lo+4
s_addc_u32 s3, s3, gridDepth_d@rel32@hi+12
s_load_b32 s2, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v3
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_15
v_mad_u64_u32 v[5:6], null, s5, v3, v[2:3]
s_load_b128 s[0:3], s[0:1], 0x0
v_add_nc_u32_e32 v0, -1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v5, s4, v[1:2]
v_mad_u64_u32 v[6:7], null, s5, v0, v[2:3]
v_add_nc_u32_e32 v0, -1, v5
v_add_nc_u32_e32 v2, s5, v5
v_add_nc_u32_e32 v7, 1, v3
v_add_nc_u32_e32 v9, -1, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[4:5], null, v0, s4, v[1:2]
v_ashrrev_i32_e32 v5, 31, v7
s_delay_alu instid0(VALU_DEP_3)
v_ashrrev_i32_e32 v10, 31, v9
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s0, v7
v_add_nc_u32_e32 v0, s4, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v5, vcc_lo
v_add_co_u32 v9, vcc_lo, s0, v9
v_mad_u64_u32 v[11:12], null, v2, s4, v[1:2]
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v10, vcc_lo
v_ashrrev_i32_e32 v2, 31, v0
s_clause 0x1
global_load_u8 v12, v[7:8], off
global_load_u8 v13, v[9:10], off
v_add_co_u32 v7, vcc_lo, s0, v0
v_ashrrev_i32_e32 v5, 31, v4
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v2, vcc_lo
v_ashrrev_i32_e32 v2, 31, v11
v_add_co_u32 v4, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
v_mad_u64_u32 v[9:10], null, v6, s4, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v11
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
s_clause 0x2
global_load_u8 v2, v[7:8], off
global_load_u8 v7, v[4:5], off
global_load_u8 v8, v[0:1], off
v_ashrrev_i32_e32 v1, 31, v9
v_ashrrev_i32_e32 v4, 31, v3
v_add_co_u32 v0, vcc_lo, s0, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v5, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v4, vcc_lo
s_clause 0x1
global_load_u8 v0, v[0:1], off
global_load_u8 v1, v[5:6], off
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(5)
v_add_nc_u16 v5, v13, v12
s_waitcnt vmcnt(4)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u16 v2, v5, v2
s_waitcnt vmcnt(3)
v_add_nc_u16 v2, v2, v7
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u16 v2, v2, v8
s_waitcnt vmcnt(1)
v_add_nc_u16 v0, v2, v0
s_waitcnt vmcnt(0)
v_cmpx_ne_u16_e32 0, v1
s_xor_b32 s1, exec_lo, s0
s_cbranch_execz .LBB0_10
v_and_b32_e32 v0, 0xfe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_ne_u16_e32 vcc_lo, 2, v0
v_add_co_u32 v0, s0, s2, v3
v_add_co_ci_u32_e64 v1, s0, s3, v4, s0
s_and_saveexec_b32 s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v2, 0
global_store_b8 v[0:1], v2, off
.LBB0_7:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_9
v_mov_b32_e32 v2, 1
global_store_b8 v[0:1], v2, off
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_10:
s_and_not1_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_15
v_and_b32_e32 v0, 0xff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_ne_u16_e32 vcc_lo, 3, v0
v_add_co_u32 v0, s0, s2, v3
v_add_co_ci_u32_e64 v1, s0, s3, v4, s0
s_and_saveexec_b32 s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_13
v_mov_b32_e32 v2, 0
global_store_b8 v[0:1], v2, off
.LBB0_13:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_15
v_mov_b32_e32 v2, 1
global_store_b8 v[0:1], v2, off
.LBB0_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6solverPbS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6solverPbS_, .Lfunc_end0-_Z6solverPbS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected gridWidth_d
.type gridWidth_d,@object
.section .bss,"aw",@nobits
.globl gridWidth_d
.p2align 2, 0x0
gridWidth_d:
.long 0
.size gridWidth_d, 4
.protected gridHeight_d
.type gridHeight_d,@object
.globl gridHeight_d
.p2align 2, 0x0
gridHeight_d:
.long 0
.size gridHeight_d, 4
.protected gridDepth_d
.type gridDepth_d,@object
.globl gridDepth_d
.p2align 2, 0x0
gridDepth_d:
.long 0
.size gridDepth_d, 4
.protected blockWidth_d
.type blockWidth_d,@object
.globl blockWidth_d
.p2align 2, 0x0
blockWidth_d:
.long 0
.size blockWidth_d, 4
.protected blockHeight_d
.type blockHeight_d,@object
.globl blockHeight_d
.p2align 2, 0x0
blockHeight_d:
.long 0
.size blockHeight_d, 4
.protected blockDepth_d
.type blockDepth_d,@object
.globl blockDepth_d
.p2align 2, 0x0
blockDepth_d:
.long 0
.size blockDepth_d, 4
.protected gridWidthBlocks_d
.type gridWidthBlocks_d,@object
.globl gridWidthBlocks_d
.p2align 2, 0x0
gridWidthBlocks_d:
.long 0
.size gridWidthBlocks_d, 4
.protected gridHeightBlocks_d
.type gridHeightBlocks_d,@object
.globl gridHeightBlocks_d
.p2align 2, 0x0
gridHeightBlocks_d:
.long 0
.size gridHeightBlocks_d, 4
.protected gridDepthBlocks_d
.type gridDepthBlocks_d,@object
.globl gridDepthBlocks_d
.p2align 2, 0x0
gridDepthBlocks_d:
.long 0
.size gridDepthBlocks_d, 4
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym gridWidth_d
.addrsig_sym gridHeight_d
.addrsig_sym gridDepth_d
.addrsig_sym blockWidth_d
.addrsig_sym blockHeight_d
.addrsig_sym blockDepth_d
.addrsig_sym gridWidthBlocks_d
.addrsig_sym gridHeightBlocks_d
.addrsig_sym gridDepthBlocks_d
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6solverPbS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6solverPbS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z6solverPbS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002200 */
/*0040*/ S2R R5, SR_CTAID.Z ; /* 0x0000000000057919 */
/* 0x000ea20000002700 */
/*0050*/ IMAD R2, R2, c[0x3][0xc], R3 ; /* 0x00c0030002027a24 */
/* 0x001fc600078e0203 */
/*0060*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002600 */
/*0070*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*0080*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0090*/ ULDC UR4, c[0x3][0x0] ; /* 0x00c0000000047ab9 */
/* 0x006fe20000000800 */
/*00a0*/ IMAD R3, R3, c[0x3][0x10], R0 ; /* 0x00c0040003037a24 */
/* 0x001fe200078e0200 */
/*00b0*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*00c0*/ S2R R0, SR_TID.Z ; /* 0x0000000000007919 */
/* 0x000e2a0000002300 */
/*00d0*/ ISETP.GE.AND P0, PT, R2, UR4, PT ; /* 0x0000000402007c0c */
/* 0x000fc8000bf06270 */
/*00e0*/ ISETP.LT.OR P0, PT, R3, 0x1, P0 ; /* 0x000000010300780c */
/* 0x000fda0000701670 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0100*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x3][0x4] ; /* 0x00c00100ff077624 */
/* 0x000fe400078e00ff */
/*0110*/ IMAD R0, R5, c[0x3][0x14], R0 ; /* 0x00c0050005007a24 */
/* 0x001fc600078e0200 */
/*0120*/ IADD3 R4, R7, -0x1, RZ ; /* 0xffffffff07047810 */
/* 0x000fc80007ffe0ff */
/*0130*/ ISETP.GE.AND P0, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x000fc80003f06270 */
/*0140*/ ISETP.LT.OR P0, PT, R0, 0x1, P0 ; /* 0x000000010000780c */
/* 0x000fda0000701670 */
/*0150*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0160*/ ULDC UR4, c[0x3][0x8] ; /* 0x00c0020000047ab9 */
/* 0x000fe40000000800 */
/*0170*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fcc000fffe03f */
/*0180*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0190*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD R4, R0.reuse, R7, c[0x3][0x4] ; /* 0x00c0010000047624 */
/* 0x040fe200078e0207 */
/*01b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*01c0*/ IMAD.MOV R7, RZ, RZ, -c[0x3][0x4] ; /* 0x80c00100ff077624 */
/* 0x000fe400078e02ff */
/*01d0*/ IMAD R5, R0, c[0x3][0x4], R3 ; /* 0x00c0010000057a24 */
/* 0x000fe400078e0203 */
/*01e0*/ IMAD R6, R7, 0x2, R4 ; /* 0x0000000207067824 */
/* 0x000fe400078e0204 */
/*01f0*/ IMAD R0, R5.reuse, c[0x3][0x0], R2 ; /* 0x00c0000005007a24 */
/* 0x040fe200078e0202 */
/*0200*/ IADD3 R7, R5, 0x1, RZ ; /* 0x0000000105077810 */
/* 0x000fe20007ffe0ff */
/*0210*/ IMAD.IADD R11, R3, 0x1, R6 ; /* 0x00000001030b7824 */
/* 0x000fe200078e0206 */
/*0220*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe20007ffe0ff */
/*0230*/ IMAD.IADD R9, R3, 0x1, R4 ; /* 0x0000000103097824 */
/* 0x000fe200078e0204 */
/*0240*/ SHF.R.S32.HI R16, RZ, 0x1f, R0 ; /* 0x0000001fff107819 */
/* 0x000fe20000011400 */
/*0250*/ IMAD R3, R7, c[0x3][0x0], R2.reuse ; /* 0x00c0000007037a24 */
/* 0x100fe200078e0202 */
/*0260*/ IADD3 R6, P1, R0, c[0x0][0x160], RZ ; /* 0x0000580000067a10 */
/* 0x000fe20007f3e0ff */
/*0270*/ IMAD R12, R9, c[0x3][0x0], R2 ; /* 0x00c00000090c7a24 */
/* 0x000fc400078e0202 */
/*0280*/ IMAD R4, R5, c[0x3][0x0], R2.reuse ; /* 0x00c0000005047a24 */
/* 0x100fe200078e0202 */
/*0290*/ IADD3.X R7, R16, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590010077a10 */
/* 0x000fe20000ffe4ff */
/*02a0*/ IMAD R13, R11, c[0x3][0x0], R2 ; /* 0x00c000000b0d7a24 */
/* 0x000fe200078e0202 */
/*02b0*/ IADD3 R10, P0, R3.reuse, c[0x0][0x160], RZ ; /* 0x00005800030a7a10 */
/* 0x040fe40007f1e0ff */
/*02c0*/ IADD3 R8, P1, R4, c[0x0][0x160], RZ ; /* 0x0000580004087a10 */
/* 0x000fe20007f3e0ff */
/*02d0*/ LDG.E.U8 R15, [R6.64] ; /* 0x00000004060f7981 */
/* 0x000ea2000c1e1100 */
/*02e0*/ IADD3 R2, P2, R12, c[0x0][0x160], RZ ; /* 0x000058000c027a10 */
/* 0x000fe40007f5e0ff */
/*02f0*/ LEA.HI.X.SX32 R11, R3, c[0x0][0x164], 0x1, P0 ; /* 0x00005900030b7a11 */
/* 0x000fe200000f0eff */
/*0300*/ LDG.E.S8 R5, [R6.64+0x1] ; /* 0x0000010406057981 */
/* 0x000ee2000c1e1300 */
/*0310*/ LEA.HI.X.SX32 R9, R4, c[0x0][0x164], 0x1, P1 ; /* 0x0000590004097a11 */
/* 0x000fc400008f0eff */
/*0320*/ LEA.HI.X.SX32 R3, R12, c[0x0][0x164], 0x1, P2 ; /* 0x000059000c037a11 */
/* 0x000fe200010f0eff */
/*0330*/ LDG.E.S8 R14, [R6.64+-0x1] ; /* 0xffffff04060e7981 */
/* 0x000ee2000c1e1300 */
/*0340*/ IADD3 R12, P0, R13, c[0x0][0x160], RZ ; /* 0x000058000d0c7a10 */
/* 0x000fc60007f1e0ff */
/*0350*/ LDG.E.S8 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ee2000c1e1300 */
/*0360*/ LEA.HI.X.SX32 R13, R13, c[0x0][0x164], 0x1, P0 ; /* 0x000059000d0d7a11 */
/* 0x000fc600000f0eff */
/*0370*/ LDG.E.S8 R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000f28000c1e1300 */
/*0380*/ LDG.E.S8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000f28000c1e1300 */
/*0390*/ LDG.E.S8 R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000f62000c1e1300 */
/*03a0*/ IADD3 R4, P1, R0, c[0x0][0x168], RZ ; /* 0x00005a0000047a10 */
/* 0x000fe40007f3e0ff */
/*03b0*/ ISETP.NE.AND P0, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x004fc40003f05270 */
/*03c0*/ IADD3 R14, R10, R14, R5 ; /* 0x0000000e0a0e7210 */
/* 0x008fe40007ffe005 */
/*03d0*/ IADD3.X R5, R16, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0010057a10 */
/* 0x000fe40000ffe4ff */
/*03e0*/ IADD3 R14, R2, R14, R9 ; /* 0x0000000e020e7210 */
/* 0x010fca0007ffe009 */
/*03f0*/ IMAD.IADD R14, R14, 0x1, R13 ; /* 0x000000010e0e7824 */
/* 0x020fe400078e020d */
/*0400*/ @!P0 BRA 0x480 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*0410*/ LOP3.LUT R14, R14, 0xfffffffe, RZ, 0xc0, !PT ; /* 0xfffffffe0e0e7812 */
/* 0x000fc800078ec0ff */
/*0420*/ ISETP.NE.AND P0, PT, R14, 0x2, PT ; /* 0x000000020e00780c */
/* 0x000fda0003f05270 */
/*0430*/ @P0 STG.E.U8 [R4.64], RZ ; /* 0x000000ff04000986 */
/* 0x0001e2000c101104 */
/*0440*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0450*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fca00078e00ff */
/*0460*/ STG.E.U8 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x000fe2000c101104 */
/*0470*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0480*/ ISETP.NE.AND P0, PT, R14, 0x3, PT ; /* 0x000000030e00780c */
/* 0x000fda0003f05270 */
/*0490*/ @P0 STG.E.U8 [R4.64], RZ ; /* 0x000000ff04000986 */
/* 0x0001e2000c101104 */
/*04a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*04b0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fca00078e00ff */
/*04c0*/ STG.E.U8 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x000fe2000c101104 */
/*04d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04e0*/ BRA 0x4e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6solverPbS_
.globl _Z6solverPbS_
.p2align 8
.type _Z6solverPbS_,@function
_Z6solverPbS_:
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, blockWidth_d@rel32@lo+4
s_addc_u32 s3, s3, blockWidth_d@rel32@hi+12
v_and_b32_e32 v3, 0x3ff, v0
s_load_b32 s2, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s13, v[3:4]
s_mov_b32 s2, exec_lo
v_cmpx_lt_i32_e32 0, v1
s_cbranch_execz .LBB0_15
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, blockHeight_d@rel32@lo+4
s_addc_u32 s3, s3, blockHeight_d@rel32@hi+12
v_bfe_u32 v4, v0, 10, 10
s_load_b32 s5, s[2:3], 0x0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, gridWidth_d@rel32@lo+4
s_addc_u32 s3, s3, gridWidth_d@rel32@hi+12
s_load_b32 s4, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, s5, s14, v[4:5]
s_add_i32 s2, s4, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
v_cmp_lt_i32_e64 s2, 0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_15
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, blockDepth_d@rel32@lo+4
s_addc_u32 s3, s3, blockDepth_d@rel32@hi+12
v_bfe_u32 v0, v0, 20, 10
s_load_b32 s6, s[2:3], 0x0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, gridHeight_d@rel32@lo+4
s_addc_u32 s3, s3, gridHeight_d@rel32@hi+12
s_load_b32 s5, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[3:4], null, s6, s15, v[0:1]
s_add_i32 s2, s5, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s2, v2
v_cmp_lt_i32_e64 s2, 0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_15
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, gridDepth_d@rel32@lo+4
s_addc_u32 s3, s3, gridDepth_d@rel32@hi+12
s_load_b32 s2, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v3
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_15
v_mad_u64_u32 v[5:6], null, s5, v3, v[2:3]
s_load_b128 s[0:3], s[0:1], 0x0
v_add_nc_u32_e32 v0, -1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v5, s4, v[1:2]
v_mad_u64_u32 v[6:7], null, s5, v0, v[2:3]
v_add_nc_u32_e32 v0, -1, v5
v_add_nc_u32_e32 v2, s5, v5
v_add_nc_u32_e32 v7, 1, v3
v_add_nc_u32_e32 v9, -1, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[4:5], null, v0, s4, v[1:2]
v_ashrrev_i32_e32 v5, 31, v7
s_delay_alu instid0(VALU_DEP_3)
v_ashrrev_i32_e32 v10, 31, v9
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s0, v7
v_add_nc_u32_e32 v0, s4, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v5, vcc_lo
v_add_co_u32 v9, vcc_lo, s0, v9
v_mad_u64_u32 v[11:12], null, v2, s4, v[1:2]
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v10, vcc_lo
v_ashrrev_i32_e32 v2, 31, v0
s_clause 0x1
global_load_u8 v12, v[7:8], off
global_load_u8 v13, v[9:10], off
v_add_co_u32 v7, vcc_lo, s0, v0
v_ashrrev_i32_e32 v5, 31, v4
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v2, vcc_lo
v_ashrrev_i32_e32 v2, 31, v11
v_add_co_u32 v4, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
v_mad_u64_u32 v[9:10], null, v6, s4, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v11
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
s_clause 0x2
global_load_u8 v2, v[7:8], off
global_load_u8 v7, v[4:5], off
global_load_u8 v8, v[0:1], off
v_ashrrev_i32_e32 v1, 31, v9
v_ashrrev_i32_e32 v4, 31, v3
v_add_co_u32 v0, vcc_lo, s0, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v5, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v4, vcc_lo
s_clause 0x1
global_load_u8 v0, v[0:1], off
global_load_u8 v1, v[5:6], off
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(5)
v_add_nc_u16 v5, v13, v12
s_waitcnt vmcnt(4)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u16 v2, v5, v2
s_waitcnt vmcnt(3)
v_add_nc_u16 v2, v2, v7
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u16 v2, v2, v8
s_waitcnt vmcnt(1)
v_add_nc_u16 v0, v2, v0
s_waitcnt vmcnt(0)
v_cmpx_ne_u16_e32 0, v1
s_xor_b32 s1, exec_lo, s0
s_cbranch_execz .LBB0_10
v_and_b32_e32 v0, 0xfe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_ne_u16_e32 vcc_lo, 2, v0
v_add_co_u32 v0, s0, s2, v3
v_add_co_ci_u32_e64 v1, s0, s3, v4, s0
s_and_saveexec_b32 s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v2, 0
global_store_b8 v[0:1], v2, off
.LBB0_7:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_9
v_mov_b32_e32 v2, 1
global_store_b8 v[0:1], v2, off
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_10:
s_and_not1_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_15
v_and_b32_e32 v0, 0xff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_ne_u16_e32 vcc_lo, 3, v0
v_add_co_u32 v0, s0, s2, v3
v_add_co_ci_u32_e64 v1, s0, s3, v4, s0
s_and_saveexec_b32 s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_13
v_mov_b32_e32 v2, 0
global_store_b8 v[0:1], v2, off
.LBB0_13:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_15
v_mov_b32_e32 v2, 1
global_store_b8 v[0:1], v2, off
.LBB0_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6solverPbS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6solverPbS_, .Lfunc_end0-_Z6solverPbS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected gridWidth_d
.type gridWidth_d,@object
.section .bss,"aw",@nobits
.globl gridWidth_d
.p2align 2, 0x0
gridWidth_d:
.long 0
.size gridWidth_d, 4
.protected gridHeight_d
.type gridHeight_d,@object
.globl gridHeight_d
.p2align 2, 0x0
gridHeight_d:
.long 0
.size gridHeight_d, 4
.protected gridDepth_d
.type gridDepth_d,@object
.globl gridDepth_d
.p2align 2, 0x0
gridDepth_d:
.long 0
.size gridDepth_d, 4
.protected blockWidth_d
.type blockWidth_d,@object
.globl blockWidth_d
.p2align 2, 0x0
blockWidth_d:
.long 0
.size blockWidth_d, 4
.protected blockHeight_d
.type blockHeight_d,@object
.globl blockHeight_d
.p2align 2, 0x0
blockHeight_d:
.long 0
.size blockHeight_d, 4
.protected blockDepth_d
.type blockDepth_d,@object
.globl blockDepth_d
.p2align 2, 0x0
blockDepth_d:
.long 0
.size blockDepth_d, 4
.protected gridWidthBlocks_d
.type gridWidthBlocks_d,@object
.globl gridWidthBlocks_d
.p2align 2, 0x0
gridWidthBlocks_d:
.long 0
.size gridWidthBlocks_d, 4
.protected gridHeightBlocks_d
.type gridHeightBlocks_d,@object
.globl gridHeightBlocks_d
.p2align 2, 0x0
gridHeightBlocks_d:
.long 0
.size gridHeightBlocks_d, 4
.protected gridDepthBlocks_d
.type gridDepthBlocks_d,@object
.globl gridDepthBlocks_d
.p2align 2, 0x0
gridDepthBlocks_d:
.long 0
.size gridDepthBlocks_d, 4
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym gridWidth_d
.addrsig_sym gridHeight_d
.addrsig_sym gridDepth_d
.addrsig_sym blockWidth_d
.addrsig_sym blockHeight_d
.addrsig_sym blockDepth_d
.addrsig_sym gridWidthBlocks_d
.addrsig_sym gridHeightBlocks_d
.addrsig_sym gridDepthBlocks_d
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6solverPbS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6solverPbS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <assert.h>
#ifndef THREADS_PER_BLOCK
#define THREADS_PER_BLOCK 1024
#endif
//#define VERBOSE
//#define PROF
#define CUDA_ERROR_CHECK
#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CudaCheckError() __cudaCheckError( __FILE__, __LINE__ )
inline void __cudaSafeCall( cudaError err, const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
cudaError err = cudaGetLastError();
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment away if needed.
err = cudaDeviceSynchronize();
if( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
#endif
}
__global__ void vc(float *dA, float *dB, int N) {
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < N) {
dA[id] = dB[id];
}
}
extern "C" {
void vcCUDA(float* A, float *B, int start, int end, int GPUN) {
float *dA, *dB;
if (GPUN > 0) {
assert(end - start + 1 == GPUN);
#ifdef VERBOSE
printf("In vcCUDA\n");
printf("\t GPUN: %d\n", GPUN);
printf("\t range: %d..%d\n", start, end);
#endif
#ifdef PROF
cudaEvent_t startCudaKernelEvent, endCudaKernelEvent;
CudaSafeCall(cudaEventCreate(&startCudaKernelEvent));
CudaSafeCall(cudaEventCreate(&endCudaKernelEvent));
#endif
CudaSafeCall(cudaMalloc(&dA, sizeof(float) * GPUN));
CudaSafeCall(cudaMalloc(&dB, sizeof(float) * GPUN));
CudaSafeCall(cudaMemcpy(dB, B + start, sizeof(float) * GPUN, cudaMemcpyHostToDevice));
#ifdef PROF
CudaSafeCall(cudaEventRecord(startCudaKernelEvent));
#endif
vc<<<ceil(((float)GPUN)/THREADS_PER_BLOCK), THREADS_PER_BLOCK>>>(dA, dB, GPUN);
#ifdef PROF
CudaSafeCall(cudaEventRecord(endCudaKernelEvent));
CudaSafeCall(cudaEventSynchronize(endCudaKernelEvent));
#endif
CudaCheckError();
CudaSafeCall(cudaDeviceSynchronize());
CudaSafeCall(cudaMemcpy(A + start, dA, sizeof(float) * GPUN, cudaMemcpyDeviceToHost));
#ifdef PROF
float msecKernel;
CudaSafeCall(cudaEventElapsedTime(&msecKernel, startCudaKernelEvent, endCudaKernelEvent));
printf("CUDA kernel: %lf msec\n", msecKernel);
#endif
CudaSafeCall(cudaFree(dA));
CudaSafeCall(cudaFree(dB));
}
}
}
|
code for sm_80
Function : _Z2vcPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0205 */
/*00b0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <assert.h>
#ifndef THREADS_PER_BLOCK
#define THREADS_PER_BLOCK 1024
#endif
//#define VERBOSE
//#define PROF
#define CUDA_ERROR_CHECK
#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CudaCheckError() __cudaCheckError( __FILE__, __LINE__ )
inline void __cudaSafeCall( cudaError err, const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
cudaError err = cudaGetLastError();
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment away if needed.
err = cudaDeviceSynchronize();
if( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
#endif
}
__global__ void vc(float *dA, float *dB, int N) {
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < N) {
dA[id] = dB[id];
}
}
extern "C" {
void vcCUDA(float* A, float *B, int start, int end, int GPUN) {
float *dA, *dB;
if (GPUN > 0) {
assert(end - start + 1 == GPUN);
#ifdef VERBOSE
printf("In vcCUDA\n");
printf("\t GPUN: %d\n", GPUN);
printf("\t range: %d..%d\n", start, end);
#endif
#ifdef PROF
cudaEvent_t startCudaKernelEvent, endCudaKernelEvent;
CudaSafeCall(cudaEventCreate(&startCudaKernelEvent));
CudaSafeCall(cudaEventCreate(&endCudaKernelEvent));
#endif
CudaSafeCall(cudaMalloc(&dA, sizeof(float) * GPUN));
CudaSafeCall(cudaMalloc(&dB, sizeof(float) * GPUN));
CudaSafeCall(cudaMemcpy(dB, B + start, sizeof(float) * GPUN, cudaMemcpyHostToDevice));
#ifdef PROF
CudaSafeCall(cudaEventRecord(startCudaKernelEvent));
#endif
vc<<<ceil(((float)GPUN)/THREADS_PER_BLOCK), THREADS_PER_BLOCK>>>(dA, dB, GPUN);
#ifdef PROF
CudaSafeCall(cudaEventRecord(endCudaKernelEvent));
CudaSafeCall(cudaEventSynchronize(endCudaKernelEvent));
#endif
CudaCheckError();
CudaSafeCall(cudaDeviceSynchronize());
CudaSafeCall(cudaMemcpy(A + start, dA, sizeof(float) * GPUN, cudaMemcpyDeviceToHost));
#ifdef PROF
float msecKernel;
CudaSafeCall(cudaEventElapsedTime(&msecKernel, startCudaKernelEvent, endCudaKernelEvent));
printf("CUDA kernel: %lf msec\n", msecKernel);
#endif
CudaSafeCall(cudaFree(dA));
CudaSafeCall(cudaFree(dB));
}
}
}
|
.file "tmpxft_00158cee_00000000-6_vc.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z2vcPfS_iPfS_i
.type _Z24__device_stub__Z2vcPfS_iPfS_i, @function
_Z24__device_stub__Z2vcPfS_iPfS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z2vcPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z24__device_stub__Z2vcPfS_iPfS_i, .-_Z24__device_stub__Z2vcPfS_iPfS_i
.globl _Z2vcPfS_i
.type _Z2vcPfS_i, @function
_Z2vcPfS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z2vcPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z2vcPfS_i, .-_Z2vcPfS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/ahayashi/chapel-gpu/master/apps/vector_copy/vc.cu"
.align 8
.LC1:
.string "cudaSafeCall() failed at %s:%i : %s\n"
.align 8
.LC6:
.string "cudaCheckError() failed at %s:%i : %s\n"
.align 8
.LC7:
.string "cudaCheckError() with sync failed at %s:%i : %s\n"
.text
.globl vcCUDA
.type vcCUDA, @function
vcCUDA:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
testl %r8d, %r8d
jg .L25
.L11:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movq %rdi, %r13
movq %rsi, %r12
movl %edx, %ebx
movl %r8d, %ebp
movslq %r8d, %r14
salq $2, %r14
movq %rsp, %rdi
movq %r14, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L27
leaq 8(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L28
movslq %ebx, %rbx
salq $2, %rbx
leaq (%r12,%rbx), %rsi
movl $1, %ecx
movq %r14, %rdx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L29
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %ebp, %xmm0
mulss .LC2(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC8(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC3(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L16
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC5(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L16:
cvttss2siq %xmm3, %rax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl 36(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L17:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L31
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L32
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L33
leaq 0(%r13,%rbx), %rdi
movl $2, %ecx
movq %r14, %rdx
movq (%rsp), %rsi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L34
movq (%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L35
movq 8(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
je .L11
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $99, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L27:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $77, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L28:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $78, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L29:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $79, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L30:
movl %ebp, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z24__device_stub__Z2vcPfS_iPfS_i
jmp .L17
.L31:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $88, %r8d
leaq .LC0(%rip), %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $88, %r8d
leaq .LC0(%rip), %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L33:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $89, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L34:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $90, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L35:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $98, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size vcCUDA, .-vcCUDA
.section .rodata.str1.1,"aMS",@progbits,1
.LC9:
.string "_Z2vcPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z2vcPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 981467136
.align 4
.LC3:
.long 1258291200
.align 4
.LC5:
.long 1065353216
.align 4
.LC8:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <assert.h>
#ifndef THREADS_PER_BLOCK
#define THREADS_PER_BLOCK 1024
#endif
//#define VERBOSE
//#define PROF
#define CUDA_ERROR_CHECK
#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CudaCheckError() __cudaCheckError( __FILE__, __LINE__ )
inline void __cudaSafeCall( cudaError err, const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
cudaError err = cudaGetLastError();
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment away if needed.
err = cudaDeviceSynchronize();
if( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
#endif
}
__global__ void vc(float *dA, float *dB, int N) {
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < N) {
dA[id] = dB[id];
}
}
extern "C" {
void vcCUDA(float* A, float *B, int start, int end, int GPUN) {
float *dA, *dB;
if (GPUN > 0) {
assert(end - start + 1 == GPUN);
#ifdef VERBOSE
printf("In vcCUDA\n");
printf("\t GPUN: %d\n", GPUN);
printf("\t range: %d..%d\n", start, end);
#endif
#ifdef PROF
cudaEvent_t startCudaKernelEvent, endCudaKernelEvent;
CudaSafeCall(cudaEventCreate(&startCudaKernelEvent));
CudaSafeCall(cudaEventCreate(&endCudaKernelEvent));
#endif
CudaSafeCall(cudaMalloc(&dA, sizeof(float) * GPUN));
CudaSafeCall(cudaMalloc(&dB, sizeof(float) * GPUN));
CudaSafeCall(cudaMemcpy(dB, B + start, sizeof(float) * GPUN, cudaMemcpyHostToDevice));
#ifdef PROF
CudaSafeCall(cudaEventRecord(startCudaKernelEvent));
#endif
vc<<<ceil(((float)GPUN)/THREADS_PER_BLOCK), THREADS_PER_BLOCK>>>(dA, dB, GPUN);
#ifdef PROF
CudaSafeCall(cudaEventRecord(endCudaKernelEvent));
CudaSafeCall(cudaEventSynchronize(endCudaKernelEvent));
#endif
CudaCheckError();
CudaSafeCall(cudaDeviceSynchronize());
CudaSafeCall(cudaMemcpy(A + start, dA, sizeof(float) * GPUN, cudaMemcpyDeviceToHost));
#ifdef PROF
float msecKernel;
CudaSafeCall(cudaEventElapsedTime(&msecKernel, startCudaKernelEvent, endCudaKernelEvent));
printf("CUDA kernel: %lf msec\n", msecKernel);
#endif
CudaSafeCall(cudaFree(dA));
CudaSafeCall(cudaFree(dB));
}
}
}
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <assert.h>
#ifndef THREADS_PER_BLOCK
#define THREADS_PER_BLOCK 1024
#endif
//#define VERBOSE
//#define PROF
#define CUDA_ERROR_CHECK
#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CudaCheckError() __cudaCheckError( __FILE__, __LINE__ )
inline void __cudaSafeCall( hipError_t err, const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
if ( hipSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
hipError_t err = hipGetLastError();
if ( hipSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment away if needed.
err = hipDeviceSynchronize();
if( hipSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
#endif
}
__global__ void vc(float *dA, float *dB, int N) {
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < N) {
dA[id] = dB[id];
}
}
extern "C" {
void vcCUDA(float* A, float *B, int start, int end, int GPUN) {
float *dA, *dB;
if (GPUN > 0) {
assert(end - start + 1 == GPUN);
#ifdef VERBOSE
printf("In vcCUDA\n");
printf("\t GPUN: %d\n", GPUN);
printf("\t range: %d..%d\n", start, end);
#endif
#ifdef PROF
hipEvent_t startCudaKernelEvent, endCudaKernelEvent;
CudaSafeCall(hipEventCreate(&startCudaKernelEvent));
CudaSafeCall(hipEventCreate(&endCudaKernelEvent));
#endif
CudaSafeCall(hipMalloc(&dA, sizeof(float) * GPUN));
CudaSafeCall(hipMalloc(&dB, sizeof(float) * GPUN));
CudaSafeCall(hipMemcpy(dB, B + start, sizeof(float) * GPUN, hipMemcpyHostToDevice));
#ifdef PROF
CudaSafeCall(hipEventRecord(startCudaKernelEvent));
#endif
vc<<<ceil(((float)GPUN)/THREADS_PER_BLOCK), THREADS_PER_BLOCK>>>(dA, dB, GPUN);
#ifdef PROF
CudaSafeCall(hipEventRecord(endCudaKernelEvent));
CudaSafeCall(hipEventSynchronize(endCudaKernelEvent));
#endif
CudaCheckError();
CudaSafeCall(hipDeviceSynchronize());
CudaSafeCall(hipMemcpy(A + start, dA, sizeof(float) * GPUN, hipMemcpyDeviceToHost));
#ifdef PROF
float msecKernel;
CudaSafeCall(hipEventElapsedTime(&msecKernel, startCudaKernelEvent, endCudaKernelEvent));
printf("CUDA kernel: %lf msec\n", msecKernel);
#endif
CudaSafeCall(hipFree(dA));
CudaSafeCall(hipFree(dB));
}
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <assert.h>
#ifndef THREADS_PER_BLOCK
#define THREADS_PER_BLOCK 1024
#endif
//#define VERBOSE
//#define PROF
#define CUDA_ERROR_CHECK
#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CudaCheckError() __cudaCheckError( __FILE__, __LINE__ )
inline void __cudaSafeCall( hipError_t err, const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
if ( hipSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
hipError_t err = hipGetLastError();
if ( hipSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment away if needed.
err = hipDeviceSynchronize();
if( hipSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
#endif
}
__global__ void vc(float *dA, float *dB, int N) {
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < N) {
dA[id] = dB[id];
}
}
extern "C" {
void vcCUDA(float* A, float *B, int start, int end, int GPUN) {
float *dA, *dB;
if (GPUN > 0) {
assert(end - start + 1 == GPUN);
#ifdef VERBOSE
printf("In vcCUDA\n");
printf("\t GPUN: %d\n", GPUN);
printf("\t range: %d..%d\n", start, end);
#endif
#ifdef PROF
hipEvent_t startCudaKernelEvent, endCudaKernelEvent;
CudaSafeCall(hipEventCreate(&startCudaKernelEvent));
CudaSafeCall(hipEventCreate(&endCudaKernelEvent));
#endif
CudaSafeCall(hipMalloc(&dA, sizeof(float) * GPUN));
CudaSafeCall(hipMalloc(&dB, sizeof(float) * GPUN));
CudaSafeCall(hipMemcpy(dB, B + start, sizeof(float) * GPUN, hipMemcpyHostToDevice));
#ifdef PROF
CudaSafeCall(hipEventRecord(startCudaKernelEvent));
#endif
vc<<<ceil(((float)GPUN)/THREADS_PER_BLOCK), THREADS_PER_BLOCK>>>(dA, dB, GPUN);
#ifdef PROF
CudaSafeCall(hipEventRecord(endCudaKernelEvent));
CudaSafeCall(hipEventSynchronize(endCudaKernelEvent));
#endif
CudaCheckError();
CudaSafeCall(hipDeviceSynchronize());
CudaSafeCall(hipMemcpy(A + start, dA, sizeof(float) * GPUN, hipMemcpyDeviceToHost));
#ifdef PROF
float msecKernel;
CudaSafeCall(hipEventElapsedTime(&msecKernel, startCudaKernelEvent, endCudaKernelEvent));
printf("CUDA kernel: %lf msec\n", msecKernel);
#endif
CudaSafeCall(hipFree(dA));
CudaSafeCall(hipFree(dB));
}
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z2vcPfS_i
.globl _Z2vcPfS_i
.p2align 8
.type _Z2vcPfS_i,@function
_Z2vcPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z2vcPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z2vcPfS_i, .Lfunc_end0-_Z2vcPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z2vcPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z2vcPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <assert.h>
#ifndef THREADS_PER_BLOCK
#define THREADS_PER_BLOCK 1024
#endif
//#define VERBOSE
//#define PROF
#define CUDA_ERROR_CHECK
#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CudaCheckError() __cudaCheckError( __FILE__, __LINE__ )
inline void __cudaSafeCall( hipError_t err, const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
if ( hipSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
hipError_t err = hipGetLastError();
if ( hipSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment away if needed.
err = hipDeviceSynchronize();
if( hipSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
#endif
}
__global__ void vc(float *dA, float *dB, int N) {
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < N) {
dA[id] = dB[id];
}
}
extern "C" {
void vcCUDA(float* A, float *B, int start, int end, int GPUN) {
float *dA, *dB;
if (GPUN > 0) {
assert(end - start + 1 == GPUN);
#ifdef VERBOSE
printf("In vcCUDA\n");
printf("\t GPUN: %d\n", GPUN);
printf("\t range: %d..%d\n", start, end);
#endif
#ifdef PROF
hipEvent_t startCudaKernelEvent, endCudaKernelEvent;
CudaSafeCall(hipEventCreate(&startCudaKernelEvent));
CudaSafeCall(hipEventCreate(&endCudaKernelEvent));
#endif
CudaSafeCall(hipMalloc(&dA, sizeof(float) * GPUN));
CudaSafeCall(hipMalloc(&dB, sizeof(float) * GPUN));
CudaSafeCall(hipMemcpy(dB, B + start, sizeof(float) * GPUN, hipMemcpyHostToDevice));
#ifdef PROF
CudaSafeCall(hipEventRecord(startCudaKernelEvent));
#endif
vc<<<ceil(((float)GPUN)/THREADS_PER_BLOCK), THREADS_PER_BLOCK>>>(dA, dB, GPUN);
#ifdef PROF
CudaSafeCall(hipEventRecord(endCudaKernelEvent));
CudaSafeCall(hipEventSynchronize(endCudaKernelEvent));
#endif
CudaCheckError();
CudaSafeCall(hipDeviceSynchronize());
CudaSafeCall(hipMemcpy(A + start, dA, sizeof(float) * GPUN, hipMemcpyDeviceToHost));
#ifdef PROF
float msecKernel;
CudaSafeCall(hipEventElapsedTime(&msecKernel, startCudaKernelEvent, endCudaKernelEvent));
printf("CUDA kernel: %lf msec\n", msecKernel);
#endif
CudaSafeCall(hipFree(dA));
CudaSafeCall(hipFree(dB));
}
}
}
|
.text
.file "vc.hip"
.globl _Z17__device_stub__vcPfS_i # -- Begin function _Z17__device_stub__vcPfS_i
.p2align 4, 0x90
.type _Z17__device_stub__vcPfS_i,@function
_Z17__device_stub__vcPfS_i: # @_Z17__device_stub__vcPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z2vcPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z17__device_stub__vcPfS_i, .Lfunc_end0-_Z17__device_stub__vcPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function vcCUDA
.LCPI1_0:
.long 0x3a800000 # float 9.765625E-4
.text
.globl vcCUDA
.p2align 4, 0x90
.type vcCUDA,@function
vcCUDA: # @vcCUDA
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
testl %r8d, %r8d
jle .LBB1_23
# %bb.1:
movl %r8d, %ebp
movl %edx, %r12d
movq %rsi, %r15
movq %rdi, %r14
movl %r8d, %ebx
shlq $2, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_2
# %bb.3: # %_Z14__cudaSafeCall10hipError_tPKci.exit
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_4
# %bb.5: # %_Z14__cudaSafeCall10hipError_tPKci.exit13
movq 8(%rsp), %rdi
movslq %r12d, %r12
leaq (%r15,%r12,4), %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_6
# %bb.7: # %_Z14__cudaSafeCall10hipError_tPKci.exit15
cvtsi2ss %ebp, %xmm0
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_9
# %bb.8:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %ebp, 28(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z2vcPfS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_9:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_10
# %bb.13:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_14
# %bb.15: # %_Z16__cudaCheckErrorPKci.exit
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_16
# %bb.17: # %_Z14__cudaSafeCall10hipError_tPKci.exit18
leaq (%r14,%r12,4), %rdi
movq 16(%rsp), %rsi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_18
# %bb.19: # %_Z14__cudaSafeCall10hipError_tPKci.exit20
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_20
# %bb.21: # %_Z14__cudaSafeCall10hipError_tPKci.exit22
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_22
.LBB1_23: # %_Z14__cudaSafeCall10hipError_tPKci.exit24
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_2:
.cfi_def_cfa_offset 176
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $79, %ecx
jmp .LBB1_12
.LBB1_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $80, %ecx
jmp .LBB1_12
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $81, %ecx
jmp .LBB1_12
.LBB1_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
jmp .LBB1_11
.LBB1_14:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
.LBB1_11:
movl $.L.str, %edx
movq %rbx, %rdi
movl $90, %ecx
jmp .LBB1_12
.LBB1_16:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $91, %ecx
jmp .LBB1_12
.LBB1_18:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $92, %ecx
jmp .LBB1_12
.LBB1_20:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $100, %ecx
jmp .LBB1_12
.LBB1_22:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $101, %ecx
.LBB1_12:
movq %rax, %r8
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end1:
.size vcCUDA, .Lfunc_end1-vcCUDA
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2vcPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z2vcPfS_i,@object # @_Z2vcPfS_i
.section .rodata,"a",@progbits
.globl _Z2vcPfS_i
.p2align 3, 0x0
_Z2vcPfS_i:
.quad _Z17__device_stub__vcPfS_i
.size _Z2vcPfS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/ahayashi/chapel-gpu/master/apps/vector_copy/vc.hip"
.size .L.str, 108
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "cudaSafeCall() failed at %s:%i : %s\n"
.size .L.str.1, 37
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "cudaCheckError() failed at %s:%i : %s\n"
.size .L.str.2, 39
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "cudaCheckError() with sync failed at %s:%i : %s\n"
.size .L.str.3, 49
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z2vcPfS_i"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z17__device_stub__vcPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z2vcPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z2vcPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0205 */
/*00b0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z2vcPfS_i
.globl _Z2vcPfS_i
.p2align 8
.type _Z2vcPfS_i,@function
_Z2vcPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z2vcPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z2vcPfS_i, .Lfunc_end0-_Z2vcPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z2vcPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z2vcPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00158cee_00000000-6_vc.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z2vcPfS_iPfS_i
.type _Z24__device_stub__Z2vcPfS_iPfS_i, @function
_Z24__device_stub__Z2vcPfS_iPfS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z2vcPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z24__device_stub__Z2vcPfS_iPfS_i, .-_Z24__device_stub__Z2vcPfS_iPfS_i
.globl _Z2vcPfS_i
.type _Z2vcPfS_i, @function
_Z2vcPfS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z2vcPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z2vcPfS_i, .-_Z2vcPfS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/ahayashi/chapel-gpu/master/apps/vector_copy/vc.cu"
.align 8
.LC1:
.string "cudaSafeCall() failed at %s:%i : %s\n"
.align 8
.LC6:
.string "cudaCheckError() failed at %s:%i : %s\n"
.align 8
.LC7:
.string "cudaCheckError() with sync failed at %s:%i : %s\n"
.text
.globl vcCUDA
.type vcCUDA, @function
vcCUDA:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
testl %r8d, %r8d
jg .L25
.L11:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movq %rdi, %r13
movq %rsi, %r12
movl %edx, %ebx
movl %r8d, %ebp
movslq %r8d, %r14
salq $2, %r14
movq %rsp, %rdi
movq %r14, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L27
leaq 8(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L28
movslq %ebx, %rbx
salq $2, %rbx
leaq (%r12,%rbx), %rsi
movl $1, %ecx
movq %r14, %rdx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L29
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %ebp, %xmm0
mulss .LC2(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC8(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC3(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L16
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC5(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L16:
cvttss2siq %xmm3, %rax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl 36(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L17:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L31
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L32
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L33
leaq 0(%r13,%rbx), %rdi
movl $2, %ecx
movq %r14, %rdx
movq (%rsp), %rsi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L34
movq (%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L35
movq 8(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
je .L11
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $99, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L27:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $77, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L28:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $78, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L29:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $79, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L30:
movl %ebp, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z24__device_stub__Z2vcPfS_iPfS_i
jmp .L17
.L31:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $88, %r8d
leaq .LC0(%rip), %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $88, %r8d
leaq .LC0(%rip), %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L33:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $89, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L34:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $90, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L35:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $98, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size vcCUDA, .-vcCUDA
.section .rodata.str1.1,"aMS",@progbits,1
.LC9:
.string "_Z2vcPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z2vcPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 981467136
.align 4
.LC3:
.long 1258291200
.align 4
.LC5:
.long 1065353216
.align 4
.LC8:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "vc.hip"
.globl _Z17__device_stub__vcPfS_i # -- Begin function _Z17__device_stub__vcPfS_i
.p2align 4, 0x90
.type _Z17__device_stub__vcPfS_i,@function
_Z17__device_stub__vcPfS_i: # @_Z17__device_stub__vcPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z2vcPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z17__device_stub__vcPfS_i, .Lfunc_end0-_Z17__device_stub__vcPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function vcCUDA
.LCPI1_0:
.long 0x3a800000 # float 9.765625E-4
.text
.globl vcCUDA
.p2align 4, 0x90
.type vcCUDA,@function
vcCUDA: # @vcCUDA
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
testl %r8d, %r8d
jle .LBB1_23
# %bb.1:
movl %r8d, %ebp
movl %edx, %r12d
movq %rsi, %r15
movq %rdi, %r14
movl %r8d, %ebx
shlq $2, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_2
# %bb.3: # %_Z14__cudaSafeCall10hipError_tPKci.exit
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_4
# %bb.5: # %_Z14__cudaSafeCall10hipError_tPKci.exit13
movq 8(%rsp), %rdi
movslq %r12d, %r12
leaq (%r15,%r12,4), %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_6
# %bb.7: # %_Z14__cudaSafeCall10hipError_tPKci.exit15
cvtsi2ss %ebp, %xmm0
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_9
# %bb.8:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %ebp, 28(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z2vcPfS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_9:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_10
# %bb.13:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_14
# %bb.15: # %_Z16__cudaCheckErrorPKci.exit
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_16
# %bb.17: # %_Z14__cudaSafeCall10hipError_tPKci.exit18
leaq (%r14,%r12,4), %rdi
movq 16(%rsp), %rsi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_18
# %bb.19: # %_Z14__cudaSafeCall10hipError_tPKci.exit20
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_20
# %bb.21: # %_Z14__cudaSafeCall10hipError_tPKci.exit22
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_22
.LBB1_23: # %_Z14__cudaSafeCall10hipError_tPKci.exit24
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_2:
.cfi_def_cfa_offset 176
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $79, %ecx
jmp .LBB1_12
.LBB1_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $80, %ecx
jmp .LBB1_12
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $81, %ecx
jmp .LBB1_12
.LBB1_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
jmp .LBB1_11
.LBB1_14:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
.LBB1_11:
movl $.L.str, %edx
movq %rbx, %rdi
movl $90, %ecx
jmp .LBB1_12
.LBB1_16:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $91, %ecx
jmp .LBB1_12
.LBB1_18:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $92, %ecx
jmp .LBB1_12
.LBB1_20:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $100, %ecx
jmp .LBB1_12
.LBB1_22:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $101, %ecx
.LBB1_12:
movq %rax, %r8
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end1:
.size vcCUDA, .Lfunc_end1-vcCUDA
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2vcPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z2vcPfS_i,@object # @_Z2vcPfS_i
.section .rodata,"a",@progbits
.globl _Z2vcPfS_i
.p2align 3, 0x0
_Z2vcPfS_i:
.quad _Z17__device_stub__vcPfS_i
.size _Z2vcPfS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/ahayashi/chapel-gpu/master/apps/vector_copy/vc.hip"
.size .L.str, 108
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "cudaSafeCall() failed at %s:%i : %s\n"
.size .L.str.1, 37
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "cudaCheckError() failed at %s:%i : %s\n"
.size .L.str.2, 39
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "cudaCheckError() with sync failed at %s:%i : %s\n"
.size .L.str.3, 49
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z2vcPfS_i"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z17__device_stub__vcPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z2vcPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
extern "C" __global__ void
mmkernel( float* a, float* b, float* c,
int pitch_a, int pitch_b, int pitch_c,
int n, int m, int p )
{
int tx = threadIdx.x;
int bx = blockDim.x;
int i = blockIdx.x*bx + tx;
int j = blockIdx.y*2;
__shared__ float cb0[512], cb1[512];
float sum0 = 0.0, sum1 = 0.0;
for( int ks = 0; ks < p; ks += bx ){
cb0[tx] = c[ks+tx+pitch_c*j];
cb1[tx] = c[ks+tx+pitch_c*(j+1)];
__syncthreads();
for( int k = ks; k < ks+bx; ++k ){
float rb = b[i+pitch_b*k];
sum0 += rb * cb0[k-ks];
sum1 += rb * cb1[k-ks];
}
__syncthreads();
}
a[i+pitch_a*j] = sum0;
a[i+pitch_a*(j+1)] = sum1;
}
|
code for sm_80
Function : mmkernel
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ MOV R2, c[0x0][0x18c] ; /* 0x0000630000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R19, -RZ, RZ, 0, 0 ; /* 0x00000000ff137435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe40003f06270 */
/*0070*/ MOV R17, RZ ; /* 0x000000ff00117202 */
/* 0x000fe20000000f00 */
/*0080*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e620000002600 */
/*0090*/ IMAD R2, R3, c[0x0][0x0], R0 ; /* 0x0000000003027a24 */
/* 0x001fe200078e0200 */
/*00a0*/ SHF.L.U32 R3, R4, 0x1, RZ ; /* 0x0000000104037819 */
/* 0x002fd000000006ff */
/*00b0*/ @!P0 BRA 0x1070 ; /* 0x00000fb000008947 */
/* 0x000fea0003800000 */
/*00c0*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x000fe2000001ff00 */
/*00d0*/ MOV R17, RZ ; /* 0x000000ff00117202 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R19, RZ ; /* 0x000000ff00137202 */
/* 0x000fc60000000f00 */
/*00f0*/ IADD3 R6, R0, R5, RZ ; /* 0x0000000500067210 */
/* 0x000fca0007ffe0ff */
/*0100*/ IMAD R9, R3, c[0x0][0x180], R6 ; /* 0x0000600003097a24 */
/* 0x000fe200078e0206 */
/*0110*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fc800000001ff */
/*0120*/ IADD3 R11, R9, c[0x0][0x180], RZ ; /* 0x00006000090b7a10 */
/* 0x000fcc0007ffe0ff */
/*0130*/ IMAD.WIDE R8, R9, R6, c[0x0][0x170] ; /* 0x00005c0009087625 */
/* 0x000fc800078e0206 */
/*0140*/ IMAD.WIDE R10, R11, R6, c[0x0][0x170] ; /* 0x00005c000b0a7625 */
/* 0x000fe400078e0206 */
/*0150*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x0000a8000c1e1900 */
/*0160*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ee2000c1e1900 */
/*0170*/ MOV R15, c[0x0][0x0] ; /* 0x00000000000f7a02 */
/* 0x000fe40000000f00 */
/*0180*/ MOV R7, R5 ; /* 0x0000000500077202 */
/* 0x000fe40000000f00 */
/*0190*/ ISETP.GE.AND P0, PT, R15, 0x1, PT ; /* 0x000000010f00780c */
/* 0x000fe20003f06270 */
/*01a0*/ IMAD R12, R4.reuse, R15.reuse, c[0x0][0x0] ; /* 0x00000000040c7624 */
/* 0x0c0fe200078e020f */
/*01b0*/ IADD3 R8, RZ, -c[0x0][0x0], RZ ; /* 0x80000000ff087a10 */
/* 0x001fe20007ffe0ff */
/*01c0*/ IMAD R13, R4, R15, 0x1 ; /* 0x00000001040d7424 */
/* 0x000fe200078e020f */
/*01d0*/ IADD3 R5, R5, c[0x0][0x0], RZ ; /* 0x0000000005057a10 */
/* 0x000fc80007ffe0ff */
/*01e0*/ IMNMX R13, R12, R13, !PT ; /* 0x0000000d0c0d7217 */
/* 0x000fe40007800200 */
/*01f0*/ ISETP.GE.AND P1, PT, R5, c[0x0][0x18c], PT ; /* 0x0000630005007a0c */
/* 0x000fc60003f26270 */
/*0200*/ IMAD R8, R4, R8, R13 ; /* 0x0000000804087224 */
/* 0x000fe200078e020d */
/*0210*/ STS [R0.X4], R9 ; /* 0x0000000900007388 */
/* 0x0041e80000004800 */
/*0220*/ STS [R0.X4+0x800], R11 ; /* 0x0008000b00007388 */
/* 0x0081e80000004800 */
/*0230*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0240*/ @!P0 BRA 0x1030 ; /* 0x00000de000008947 */
/* 0x000fea0003800000 */
/*0250*/ LOP3.LUT P2, R16, R8.reuse, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308107812 */
/* 0x041fe4000784c0ff */
/*0260*/ IADD3 R9, R8, -0x1, RZ ; /* 0xffffffff08097810 */
/* 0x000fc40007ffe0ff */
/*0270*/ MOV R8, R7 ; /* 0x0000000700087202 */
/* 0x000fe40000000f00 */
/*0280*/ ISETP.GE.U32.AND P0, PT, R9, 0x3, PT ; /* 0x000000030900780c */
/* 0x000fce0003f06070 */
/*0290*/ @!P2 BRA 0x410 ; /* 0x000001700000a947 */
/* 0x000fec0003800000 */
/*02a0*/ IMAD R23, R7, c[0x0][0x17c], R2 ; /* 0x00005f0007177a24 */
/* 0x000fe200078e0202 */
/*02b0*/ LDS.128 R8, [RZ] ; /* 0x00000000ff087984 */
/* 0x000e260000000c00 */
/*02c0*/ IMAD.WIDE R20, R23, R6, c[0x0][0x168] ; /* 0x00005a0017147625 */
/* 0x000fe200078e0206 */
/*02d0*/ LDS.128 R12, [0x800] ; /* 0x00080000ff0c7984 */
/* 0x000e6a0000000c00 */
/*02e0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000e22000c1e1900 */
/*02f0*/ ISETP.NE.AND P2, PT, R16, 0x1, PT ; /* 0x000000011000780c */
/* 0x000fe20003f45270 */
/*0300*/ FFMA R19, R8, R20, R19 ; /* 0x0000001408137223 */
/* 0x001fe20000000013 */
/*0310*/ IADD3 R8, R7, 0x1, RZ ; /* 0x0000000107087810 */
/* 0x000fe20007ffe0ff */
/*0320*/ FFMA R17, R20, R12, R17 ; /* 0x0000000c14117223 */
/* 0x002fd40000000011 */
/*0330*/ @!P2 BRA 0x410 ; /* 0x000000d00000a947 */
/* 0x000fea0003800000 */
/*0340*/ ISETP.NE.AND P2, PT, R16, 0x2, PT ; /* 0x000000021000780c */
/* 0x000fe40003f45270 */
/*0350*/ IADD3 R21, R23, c[0x0][0x17c], RZ ; /* 0x00005f0017157a10 */
/* 0x000fd60007ffe0ff */
/*0360*/ @P2 IADD3 R23, R21.reuse, c[0x0][0x17c], RZ ; /* 0x00005f0015172a10 */
/* 0x040fe20007ffe0ff */
/*0370*/ IMAD.WIDE R20, R21, R6, c[0x0][0x168] ; /* 0x00005a0015147625 */
/* 0x000fc800078e0206 */
/*0380*/ @P2 IMAD.WIDE R22, R23, R6, c[0x0][0x168] ; /* 0x00005a0017162625 */
/* 0x000fe400078e0206 */
/*0390*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ea8000c1e1900 */
/*03a0*/ @P2 LDG.E R22, [R22.64] ; /* 0x0000000416162981 */
/* 0x000ee2000c1e1900 */
/*03b0*/ IADD3 R8, R7.reuse, 0x2, RZ ; /* 0x0000000207087810 */
/* 0x040fe40007ffe0ff */
/*03c0*/ @P2 IADD3 R8, R7, 0x3, RZ ; /* 0x0000000307082810 */
/* 0x000fe20007ffe0ff */
/*03d0*/ FFMA R19, R20, R9, R19 ; /* 0x0000000914137223 */
/* 0x004fc40000000013 */
/*03e0*/ FFMA R17, R20, R13, R17 ; /* 0x0000000d14117223 */
/* 0x000fe40000000011 */
/*03f0*/ @P2 FFMA R19, R22.reuse, R10, R19 ; /* 0x0000000a16132223 */
/* 0x048fe40000000013 */
/*0400*/ @P2 FFMA R17, R22, R14, R17 ; /* 0x0000000e16112223 */
/* 0x000fe40000000011 */
/*0410*/ @!P0 BRA 0x1030 ; /* 0x00000c1000008947 */
/* 0x000fea0003800000 */
/*0420*/ IADD3 R9, R5, -R8, RZ ; /* 0x8000000805097210 */
/* 0x000fe20007ffe0ff */
/*0430*/ IMAD R23, R8.reuse, c[0x0][0x17c], R2 ; /* 0x00005f0008177a24 */
/* 0x040fe200078e0202 */
/*0440*/ IADD3 R7, R8, -R7, RZ ; /* 0x8000000708077210 */
/* 0x000fe40007ffe0ff */
/*0450*/ ISETP.GT.AND P2, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */
/* 0x000fe20003f44270 */
/*0460*/ IMAD.WIDE R22, R23, R6, c[0x0][0x168] ; /* 0x00005a0017167625 */
/* 0x000fe200078e0206 */
/*0470*/ SHF.L.U32 R7, R7, 0x2, RZ ; /* 0x0000000207077819 */
/* 0x000fc400000006ff */
/*0480*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0490*/ IADD3 R10, R7.reuse, 0x808, RZ ; /* 0x00000808070a7810 */
/* 0x040fe40007ffe0ff */
/*04a0*/ IADD3 R7, R7, 0x8, RZ ; /* 0x0000000807077810 */
/* 0x000fca0007ffe0ff */
/*04b0*/ @!P2 BRA 0xb30 ; /* 0x000006700000a947 */
/* 0x000fea0003800000 */
/*04c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*04d0*/ IADD3 R9, R5, -0xc, RZ ; /* 0xfffffff405097810 */
/* 0x000fe40007ffe0ff */
/*04e0*/ LDG.E R16, [R22.64] ; /* 0x0000000416107981 */
/* 0x0000a2000c1e1900 */
/*04f0*/ IMAD.WIDE R14, R6, c[0x0][0x17c], R22 ; /* 0x00005f00060e7a25 */
/* 0x000fc600078e0216 */
/*0500*/ LDS R21, [R7+-0x8] ; /* 0xfffff80007157984 */
/* 0x000fe80000000800 */
/*0510*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x0002e2000c1e1900 */
/*0520*/ IMAD.WIDE R28, R6, c[0x0][0x17c], R14 ; /* 0x00005f00061c7a25 */
/* 0x000fc600078e020e */
/*0530*/ LDS R27, [R7+-0x4] ; /* 0xfffffc00071b7984 */
/* 0x000fe80000000800 */
/*0540*/ LDG.E R20, [R28.64] ; /* 0x000000041c147981 */
/* 0x000964000c1e1900 */
/*0550*/ IMAD.WIDE R28, R6, c[0x0][0x17c], R28 ; /* 0x00005f00061c7a25 */
/* 0x010fca00078e021c */
/*0560*/ LDG.E R26, [R28.64] ; /* 0x000000041c1a7981 */
/* 0x000962000c1e1900 */
/*0570*/ IMAD.WIDE R24, R6, c[0x0][0x17c], R28 ; /* 0x00005f0006187a25 */
/* 0x000fca00078e021c */
/*0580*/ LDG.E R11, [R24.64] ; /* 0x00000004180b7981 */
/* 0x000168000c1e1900 */
/*0590*/ LDS R29, [R10+-0x4] ; /* 0xfffffc000a1d7984 */
/* 0x010fe20000000800 */
/*05a0*/ IMAD.WIDE R24, R6, c[0x0][0x17c], R24 ; /* 0x00005f0006187a25 */
/* 0x001fca00078e0218 */
/*05b0*/ LDG.E R12, [R24.64] ; /* 0x00000004180c7981 */
/* 0x000122000c1e1900 */
/*05c0*/ IMAD.WIDE R22, R6, c[0x0][0x17c], R24 ; /* 0x00005f0006167a25 */
/* 0x000fca00078e0218 */
/*05d0*/ LDG.E R13, [R22.64] ; /* 0x00000004160d7981 */
/* 0x000122000c1e1900 */
/*05e0*/ IMAD.WIDE R14, R6, c[0x0][0x17c], R22 ; /* 0x00005f00060e7a25 */
/* 0x002fc600078e0216 */
/*05f0*/ LDS R25, [R7] ; /* 0x0000000007197984 */
/* 0x001fe80000000800 */
/*0600*/ LDS R23, [R10+-0x8] ; /* 0xfffff8000a177984 */
/* 0x000ea80000000800 */
/*0610*/ LDG.E R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x000124000c1e1900 */
/*0620*/ IMAD.WIDE R14, R6, c[0x0][0x17c], R14 ; /* 0x00005f00060e7a25 */
/* 0x001fc800078e020e */
/*0630*/ FFMA R24, R16, R23, R17 ; /* 0x0000001710187223 */
/* 0x004fe40000000011 */
/*0640*/ FFMA R19, R21, R16, R19 ; /* 0x0000001015137223 */
/* 0x000fe20000000013 */
/*0650*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x0000a2000c1e1900 */
/*0660*/ IMAD.WIDE R16, R6, c[0x0][0x17c], R14 ; /* 0x00005f0006107a25 */
/* 0x000fc600078e020e */
/*0670*/ LDS R21, [R10] ; /* 0x000000000a157984 */
/* 0x000e620000000800 */
/*0680*/ FFMA R29, R18, R29, R24 ; /* 0x0000001d121d7223 */
/* 0x008fc60000000018 */
/*0690*/ LDG.E R24, [R16.64] ; /* 0x0000000410187981 */
/* 0x000ae2000c1e1900 */
/*06a0*/ FFMA R28, R27, R18, R19 ; /* 0x000000121b1c7223 */
/* 0x000fc60000000013 */
/*06b0*/ LDS R15, [R7+0x4] ; /* 0x00000400070f7984 */
/* 0x001e280000000800 */
/*06c0*/ LDS R27, [R10+0x4] ; /* 0x000004000a1b7984 */
/* 0x000e220000000800 */
/*06d0*/ IMAD.WIDE R18, R6, c[0x0][0x17c], R16 ; /* 0x00005f0006127a25 */
/* 0x000fc800078e0210 */
/*06e0*/ FFMA R16, R25, R20, R28 ; /* 0x0000001419107223 */
/* 0x020fe4000000001c */
/*06f0*/ LDS R28, [R7+0x8] ; /* 0x00000800071c7984 */
/* 0x000f680000000800 */
/*0700*/ LDG.E R25, [R18.64] ; /* 0x0000000412197981 */
/* 0x0002e4000c1e1900 */
/*0710*/ FFMA R14, R20, R21, R29 ; /* 0x00000015140e7223 */
/* 0x002fe4000000001d */
/*0720*/ LDS R29, [R10+0x8] ; /* 0x000008000a1d7984 */
/* 0x000e620000000800 */
/*0730*/ IMAD.WIDE R20, R6, c[0x0][0x17c], R18 ; /* 0x00005f0006147a25 */
/* 0x000fca00078e0212 */
/*0740*/ LDG.E R19, [R20.64] ; /* 0x0000000414137981 */
/* 0x000ae2000c1e1900 */
/*0750*/ FFMA R18, R15, R26, R16 ; /* 0x0000001a0f127223 */
/* 0x001fe40000000010 */
/*0760*/ FFMA R26, R26, R27, R14 ; /* 0x0000001b1a1a7223 */
/* 0x000fe4000000000e */
/*0770*/ IMAD.WIDE R14, R6.reuse, c[0x0][0x17c], R20 ; /* 0x00005f00060e7a25 */
/* 0x040fe400078e0214 */
/*0780*/ LDS R20, [R7+0xc] ; /* 0x00000c0007147984 */
/* 0x020f280000000800 */
/*0790*/ IMAD.WIDE R16, R6, c[0x0][0x17c], R14 ; /* 0x00005f0006107a25 */
/* 0x000fc400078e020e */
/*07a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000164000c1e1900 */
/*07b0*/ FFMA R15, R28, R11, R18 ; /* 0x0000000b1c0f7223 */
/* 0x001fe40000000012 */
/*07c0*/ FFMA R21, R11, R29, R26 ; /* 0x0000001d0b157223 */
/* 0x002fe4000000001a */
/*07d0*/ IMAD.WIDE R28, R6.reuse, c[0x0][0x17c], R16 ; /* 0x00005f00061c7a25 */
/* 0x040fe400078e0210 */
/*07e0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000168000c1e1900 */
/*07f0*/ IMAD.WIDE R26, R6, c[0x0][0x17c], R28 ; /* 0x00005f00061a7a25 */
/* 0x000fe200078e021c */
/*0800*/ LDG.E R11, [R28.64] ; /* 0x000000041c0b7981 */
/* 0x000768000c1e1900 */
/*0810*/ LDG.E R18, [R26.64] ; /* 0x000000041a127981 */
/* 0x000f62000c1e1900 */
/*0820*/ FFMA R20, R20, R12, R15 ; /* 0x0000000c14147223 */
/* 0x010fc6000000000f */
/*0830*/ LDS R17, [R7+0x14] ; /* 0x0000140007117984 */
/* 0x001fe80000000800 */
/*0840*/ LDS R15, [R10+0xc] ; /* 0x00000c000a0f7984 */
/* 0x000e240000000800 */
/*0850*/ FFMA R12, R12, R15, R21 ; /* 0x0000000f0c0c7223 */
/* 0x001fe40000000015 */
/*0860*/ LDS R15, [R7+0x10] ; /* 0x00001000070f7984 */
/* 0x000e280000000800 */
/*0870*/ LDS R21, [R10+0x10] ; /* 0x000010000a157984 */
/* 0x000e620000000800 */
/*0880*/ FFMA R15, R15, R13, R20 ; /* 0x0000000d0f0f7223 */
/* 0x001fc60000000014 */
/*0890*/ LDS R20, [R10+0x24] ; /* 0x000024000a147984 */
/* 0x000fe20000000800 */
/*08a0*/ FFMA R21, R13, R21, R12 ; /* 0x000000150d157223 */
/* 0x002fc6000000000c */
/*08b0*/ LDS R13, [R10+0x14] ; /* 0x000014000a0d7984 */
/* 0x000e220000000800 */
/*08c0*/ FFMA R12, R17, R22, R15 ; /* 0x00000016110c7223 */
/* 0x000fc6000000000f */
/*08d0*/ LDS R15, [R7+0x18] ; /* 0x00001800070f7984 */
/* 0x000ea80000000800 */
/*08e0*/ LDS R17, [R10+0x18] ; /* 0x000018000a117984 */
/* 0x000e620000000800 */
/*08f0*/ FFMA R22, R22, R13, R21 ; /* 0x0000000d16167223 */
/* 0x001fc60000000015 */
/*0900*/ LDS R13, [R7+0x1c] ; /* 0x00001c00070d7984 */
/* 0x000ee80000000800 */
/*0910*/ LDS R21, [R7+0x20] ; /* 0x0000200007157984 */
/* 0x000e220000000800 */
/*0920*/ FFMA R12, R15, R23, R12 ; /* 0x000000170f0c7223 */
/* 0x004fc6000000000c */
/*0930*/ LDS R15, [R10+0x1c] ; /* 0x00001c000a0f7984 */
/* 0x000ea20000000800 */
/*0940*/ FFMA R17, R23, R17, R22 ; /* 0x0000001117117223 */
/* 0x002fc60000000016 */
/*0950*/ LDS R22, [R10+0x20] ; /* 0x000020000a167984 */
/* 0x000e620000000800 */
/*0960*/ FFMA R28, R13, R24, R12 ; /* 0x000000180d1c7223 */
/* 0x008fc6000000000c */
/*0970*/ LDS R12, [R7+0x24] ; /* 0x00002400070c7984 */
/* 0x000ee80000000800 */
/*0980*/ LDS R13, [R7+0x28] ; /* 0x00002800070d7984 */
/* 0x000f680000000800 */
/*0990*/ LDS R23, [R10+0x34] ; /* 0x000034000a177984 */
/* 0x000fe20000000800 */
/*09a0*/ FFMA R28, R21, R25, R28 ; /* 0x00000019151c7223 */
/* 0x001fc6000000001c */
/*09b0*/ LDS R21, [R10+0x2c] ; /* 0x00002c000a157984 */
/* 0x000fe20000000800 */
/*09c0*/ FFMA R17, R24, R15, R17 ; /* 0x0000000f18117223 */
/* 0x004fc60000000011 */
/*09d0*/ LDS R15, [R10+0x28] ; /* 0x000028000a0f7984 */
/* 0x000e220000000800 */
/*09e0*/ FFMA R22, R25, R22, R17 ; /* 0x0000001619167223 */
/* 0x002fc60000000011 */
/*09f0*/ LDS R17, [R7+0x2c] ; /* 0x00002c0007117984 */
/* 0x000e620000000800 */
/*0a00*/ FFMA R28, R12, R19, R28 ; /* 0x000000130c1c7223 */
/* 0x008fe4000000001c */
/*0a10*/ FFMA R22, R19, R20, R22 ; /* 0x0000001413167223 */
/* 0x000fe20000000016 */
/*0a20*/ LDS R12, [R10+0x30] ; /* 0x000030000a0c7984 */
/* 0x0004e80000000800 */
/*0a30*/ LDS R20, [R7+0x30] ; /* 0x0000300007147984 */
/* 0x000f280000000800 */
/*0a40*/ LDS R19, [R7+0x34] ; /* 0x0000340007137984 */
/* 0x0001220000000800 */
/*0a50*/ IADD3 R8, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.GE.AND P2, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x000fe20003f46270 */
/*0a70*/ FFMA R13, R13, R14, R28 ; /* 0x0000000e0d0d7223 */
/* 0x020fe2000000001c */
/*0a80*/ IADD3 R10, R10, 0x40, RZ ; /* 0x000000400a0a7810 */
/* 0x004fe20007ffe0ff */
/*0a90*/ FFMA R15, R14, R15, R22 ; /* 0x0000000f0e0f7223 */
/* 0x001fc80000000016 */
/*0aa0*/ FFMA R15, R16, R21, R15 ; /* 0x00000015100f7223 */
/* 0x000fe4000000000f */
/*0ab0*/ FFMA R13, R17, R16, R13 ; /* 0x00000010110d7223 */
/* 0x002fe4000000000d */
/*0ac0*/ FFMA R12, R11, R12, R15 ; /* 0x0000000c0b0c7223 */
/* 0x008fe4000000000f */
/*0ad0*/ FFMA R13, R20, R11, R13 ; /* 0x0000000b140d7223 */
/* 0x010fe2000000000d */
/*0ae0*/ IADD3 R7, R7, 0x40, RZ ; /* 0x0000004007077810 */
/* 0x000fe20007ffe0ff */
/*0af0*/ FFMA R17, R18, R23, R12 ; /* 0x0000001712117223 */
/* 0x000fe4000000000c */
/*0b00*/ FFMA R19, R19, R18, R13 ; /* 0x0000001213137223 */
/* 0x000fc4000000000d */
/*0b10*/ IMAD.WIDE R22, R6, c[0x0][0x17c], R26 ; /* 0x00005f0006167a25 */
/* 0x000fe200078e021a */
/*0b20*/ @!P2 BRA 0x4e0 ; /* 0xfffff9b00000a947 */
/* 0x000fea000383ffff */
/*0b30*/ IADD3 R9, R5, -R8, RZ ; /* 0x8000000805097210 */
/* 0x000fc80007ffe0ff */
/*0b40*/ ISETP.GT.AND P2, PT, R9, 0x4, PT ; /* 0x000000040900780c */
/* 0x000fda0003f44270 */
/*0b50*/ @!P2 BRA 0xea0 ; /* 0x000003400000a947 */
/* 0x000fea0003800000 */
/*0b60*/ LDG.E R16, [R22.64] ; /* 0x0000000416107981 */
/* 0x0000a2000c1e1900 */
/*0b70*/ IMAD.WIDE R28, R6, c[0x0][0x17c], R22 ; /* 0x00005f00061c7a25 */
/* 0x000fca00078e0216 */
/*0b80*/ LDG.E R11, [R28.64] ; /* 0x000000041c0b7981 */
/* 0x0002e2000c1e1900 */
/*0b90*/ IMAD.WIDE R24, R6, c[0x0][0x17c], R28 ; /* 0x00005f0006187a25 */
/* 0x000fca00078e021c */
/*0ba0*/ LDG.E R9, [R24.64] ; /* 0x0000000418097981 */
/* 0x000962000c1e1900 */
/*0bb0*/ IMAD.WIDE R26, R6, c[0x0][0x17c], R24 ; /* 0x00005f00061a7a25 */
/* 0x000fc600078e0218 */
/*0bc0*/ LDS R29, [R10+-0x8] ; /* 0xfffff8000a1d7984 */
/* 0x002fe80000000800 */
/*0bd0*/ LDG.E R18, [R26.64] ; /* 0x000000041a127981 */
/* 0x000362000c1e1900 */
/*0be0*/ IMAD.WIDE R20, R6, c[0x0][0x17c], R26 ; /* 0x00005f0006147a25 */
/* 0x000fc600078e021a */
/*0bf0*/ LDS R25, [R7+-0x8] ; /* 0xfffff80007197984 */
/* 0x010ea60000000800 */
/*0c00*/ IMAD.WIDE R12, R6.reuse, c[0x0][0x17c], R20 ; /* 0x00005f00060c7a25 */
/* 0x040fe200078e0214 */
/*0c10*/ LDS R24, [R7+-0x4] ; /* 0xfffffc0007187984 */
/* 0x000ee80000000800 */
/*0c20*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000962000c1e1900 */
/*0c30*/ IMAD.WIDE R14, R6, c[0x0][0x17c], R12 ; /* 0x00005f00060e7a25 */
/* 0x000fc600078e020c */
/*0c40*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000966000c1e1900 */
/*0c50*/ IMAD.WIDE R22, R6.reuse, c[0x0][0x17c], R14 ; /* 0x00005f0006167a25 */
/* 0x041fe200078e020e */
/*0c60*/ LDS R26, [R10+-0x4] ; /* 0xfffffc000a1a7984 */
/* 0x002e280000000800 */
/*0c70*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*0c80*/ LDG.E R28, [R22.64] ; /* 0x00000004161c7981 */
/* 0x000368000c1e1900 */
/*0c90*/ LDS R13, [R10+0x4] ; /* 0x000004000a0d7984 */
/* 0x010fe80000000800 */
/*0ca0*/ LDS R15, [R10+0x8] ; /* 0x000008000a0f7984 */
/* 0x002fe80000000800 */
/*0cb0*/ LDS R21, [R7+0x10] ; /* 0x0000100007157984 */
/* 0x000fe20000000800 */
/*0cc0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0cd0*/ IMAD.WIDE R22, R6, c[0x0][0x17c], R22 ; /* 0x00005f0006167a25 */
/* 0x000fe200078e0216 */
/*0ce0*/ IADD3 R8, R8, 0x8, RZ ; /* 0x0000000808087810 */
/* 0x000fc60007ffe0ff */
/*0cf0*/ FFMA R25, R25, R16, R19 ; /* 0x0000001019197223 */
/* 0x004fe40000000013 */
/*0d00*/ FFMA R29, R16, R29, R17 ; /* 0x0000001d101d7223 */
/* 0x000fe20000000011 */
/*0d10*/ LDS R19, [R10] ; /* 0x000000000a137984 */
/* 0x000f680000000800 */
/*0d20*/ LDS R16, [R7] ; /* 0x0000000007107984 */
/* 0x000e680000000800 */
/*0d30*/ LDS R17, [R7+0x4] ; /* 0x0000040007117984 */
/* 0x000ea20000000800 */
/*0d40*/ FFMA R24, R24, R11, R25 ; /* 0x0000000b18187223 */
/* 0x008fc40000000019 */
/*0d50*/ FFMA R26, R11, R26, R29 ; /* 0x0000001a0b1a7223 */
/* 0x001fe2000000001d */
/*0d60*/ LDS R25, [R7+0x14] ; /* 0x0000140007197984 */
/* 0x000fe80000000800 */
/*0d70*/ LDS R11, [R7+0x8] ; /* 0x00000800070b7984 */
/* 0x000e220000000800 */
/*0d80*/ FFMA R26, R9, R19, R26 ; /* 0x00000013091a7223 */
/* 0x020fc6000000001a */
/*0d90*/ LDS R19, [R7+0xc] ; /* 0x00000c0007137984 */
/* 0x0007220000000800 */
/*0da0*/ FFMA R16, R16, R9, R24 ; /* 0x0000000910107223 */
/* 0x002fc60000000018 */
/*0db0*/ LDS R9, [R10+0xc] ; /* 0x00000c000a097984 */
/* 0x000e620000000800 */
/*0dc0*/ FFMA R16, R17, R18, R16 ; /* 0x0000001211107223 */
/* 0x004fc60000000010 */
/*0dd0*/ LDS R17, [R10+0x10] ; /* 0x000010000a117984 */
/* 0x000ea20000000800 */
/*0de0*/ FFMA R26, R18, R13, R26 ; /* 0x0000000d121a7223 */
/* 0x000fc6000000001a */
/*0df0*/ LDS R13, [R10+0x14] ; /* 0x000014000a0d7984 */
/* 0x000aa20000000800 */
/*0e00*/ FFMA R15, R20, R15, R26 ; /* 0x0000000f140f7223 */
/* 0x000fe4000000001a */
/*0e10*/ FFMA R11, R11, R20, R16 ; /* 0x000000140b0b7223 */
/* 0x001fe20000000010 */
/*0e20*/ IADD3 R7, R7, 0x20, RZ ; /* 0x0000002007077810 */
/* 0x008fe40007ffe0ff */
/*0e30*/ IADD3 R10, R10, 0x20, RZ ; /* 0x000000200a0a7810 */
/* 0x020fe20007ffe0ff */
/*0e40*/ FFMA R11, R19, R12, R11 ; /* 0x0000000c130b7223 */
/* 0x010fe4000000000b */
/*0e50*/ FFMA R9, R12, R9, R15 ; /* 0x000000090c097223 */
/* 0x002fe4000000000f */
/*0e60*/ FFMA R11, R21, R14, R11 ; /* 0x0000000e150b7223 */
/* 0x000fc4000000000b */
/*0e70*/ FFMA R17, R14, R17, R9 ; /* 0x000000110e117223 */
/* 0x004fe40000000009 */
/*0e80*/ FFMA R19, R25, R28, R11 ; /* 0x0000001c19137223 */
/* 0x000fe4000000000b */
/*0e90*/ FFMA R17, R28, R13, R17 ; /* 0x0000000d1c117223 */
/* 0x000fe40000000011 */
/*0ea0*/ ISETP.LT.OR P0, PT, R8, R5, P0 ; /* 0x000000050800720c */
/* 0x000fda0000701670 */
/*0eb0*/ @!P0 BRA 0x1030 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0ec0*/ IMAD.WIDE R12, R6.reuse, c[0x0][0x17c], R22 ; /* 0x00005f00060c7a25 */
/* 0x040fe200078e0216 */
/*0ed0*/ LDS R11, [R10+-0x8] ; /* 0xfffff8000a0b7984 */
/* 0x000fe80000000800 */
/*0ee0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x0000a2000c1e1900 */
/*0ef0*/ IMAD.WIDE R8, R6, c[0x0][0x17c], R12 ; /* 0x00005f0006087a25 */
/* 0x000fc600078e020c */
/*0f00*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x0002e6000c1e1900 */
/*0f10*/ IMAD.WIDE R14, R6, c[0x0][0x17c], R8 ; /* 0x00005f00060e7a25 */
/* 0x000fe200078e0208 */
/*0f20*/ LDS R21, [R7+-0x4] ; /* 0xfffffc0007157984 */
/* 0x000fe80000000800 */
/*0f30*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f28000c1e1900 */
/*0f40*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f68000c1e1900 */
/*0f50*/ LDS R6, [R7+-0x8] ; /* 0xfffff80007067984 */
/* 0x000ea80000000800 */
/*0f60*/ LDS R16, [R10+-0x4] ; /* 0xfffffc000a107984 */
/* 0x000ea80000000800 */
/*0f70*/ LDS R25, [R7] ; /* 0x0000000007197984 */
/* 0x000f280000000800 */
/*0f80*/ LDS R18, [R10] ; /* 0x000000000a127984 */
/* 0x000ea80000000800 */
/*0f90*/ LDS R23, [R7+0x4] ; /* 0x0000040007177984 */
/* 0x001f680000000800 */
/*0fa0*/ LDS R13, [R10+0x4] ; /* 0x000004000a0d7984 */
/* 0x002e220000000800 */
/*0fb0*/ FFMA R6, R6, R22, R19 ; /* 0x0000001606067223 */
/* 0x004fc40000000013 */
/*0fc0*/ FFMA R11, R22, R11, R17 ; /* 0x0000000b160b7223 */
/* 0x000fe40000000011 */
/*0fd0*/ FFMA R6, R21, R12, R6 ; /* 0x0000000c15067223 */
/* 0x008fe40000000006 */
/*0fe0*/ FFMA R11, R12, R16, R11 ; /* 0x000000100c0b7223 */
/* 0x000fe4000000000b */
/*0ff0*/ FFMA R6, R25, R8, R6 ; /* 0x0000000819067223 */
/* 0x010fe40000000006 */
/*1000*/ FFMA R11, R8, R18, R11 ; /* 0x00000012080b7223 */
/* 0x000fe4000000000b */
/*1010*/ FFMA R19, R23, R14, R6 ; /* 0x0000000e17137223 */
/* 0x020fc40000000006 */
/*1020*/ FFMA R17, R14, R13, R11 ; /* 0x0000000d0e117223 */
/* 0x001fe4000000000b */
/*1030*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x001fe20000010000 */
/*1040*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fca0007ffe0ff */
/*1050*/ @P1 CALL.REL.NOINC 0x1070 ; /* 0x0000001000001944 */
/* 0x000fe20003c00000 */
/*1060*/ BRA 0xf0 ; /* 0xfffff08000007947 */
/* 0x000fea000383ffff */
/*1070*/ IMAD R2, R3, c[0x0][0x178], R2 ; /* 0x00005e0003027a24 */
/* 0x000fe200078e0202 */
/*1080*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fc80000000f00 */
/*1090*/ IADD3 R4, R2.reuse, c[0x0][0x178], RZ ; /* 0x00005e0002047a10 */
/* 0x040fe20007ffe0ff */
/*10a0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e0205 */
/*10b0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe200078e0205 */
/*10c0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x000fe8000c101904 */
/*10d0*/ STG.E [R4.64], R17 ; /* 0x0000001104007986 */
/* 0x000fe2000c101904 */
/*10e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*10f0*/ BRA 0x10f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
extern "C" __global__ void
mmkernel( float* a, float* b, float* c,
int pitch_a, int pitch_b, int pitch_c,
int n, int m, int p )
{
int tx = threadIdx.x;
int bx = blockDim.x;
int i = blockIdx.x*bx + tx;
int j = blockIdx.y*2;
__shared__ float cb0[512], cb1[512];
float sum0 = 0.0, sum1 = 0.0;
for( int ks = 0; ks < p; ks += bx ){
cb0[tx] = c[ks+tx+pitch_c*j];
cb1[tx] = c[ks+tx+pitch_c*(j+1)];
__syncthreads();
for( int k = ks; k < ks+bx; ++k ){
float rb = b[i+pitch_b*k];
sum0 += rb * cb0[k-ks];
sum1 += rb * cb1[k-ks];
}
__syncthreads();
}
a[i+pitch_a*j] = sum0;
a[i+pitch_a*(j+1)] = sum1;
}
|
.file "tmpxft_00178726_00000000-6_k4.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z8mmkernelPfS_S_iiiiiiPfS_S_iiiiii
.type _Z37__device_stub__Z8mmkernelPfS_S_iiiiiiPfS_S_iiiiii, @function
_Z37__device_stub__Z8mmkernelPfS_S_iiiiiiPfS_S_iiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq mmkernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z8mmkernelPfS_S_iiiiiiPfS_S_iiiiii, .-_Z37__device_stub__Z8mmkernelPfS_S_iiiiiiPfS_S_iiiiii
.globl mmkernel
.type mmkernel, @function
mmkernel:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z37__device_stub__Z8mmkernelPfS_S_iiiiiiPfS_S_iiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size mmkernel, .-mmkernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "mmkernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq mmkernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
extern "C" __global__ void
mmkernel( float* a, float* b, float* c,
int pitch_a, int pitch_b, int pitch_c,
int n, int m, int p )
{
int tx = threadIdx.x;
int bx = blockDim.x;
int i = blockIdx.x*bx + tx;
int j = blockIdx.y*2;
__shared__ float cb0[512], cb1[512];
float sum0 = 0.0, sum1 = 0.0;
for( int ks = 0; ks < p; ks += bx ){
cb0[tx] = c[ks+tx+pitch_c*j];
cb1[tx] = c[ks+tx+pitch_c*(j+1)];
__syncthreads();
for( int k = ks; k < ks+bx; ++k ){
float rb = b[i+pitch_b*k];
sum0 += rb * cb0[k-ks];
sum1 += rb * cb1[k-ks];
}
__syncthreads();
}
a[i+pitch_a*j] = sum0;
a[i+pitch_a*(j+1)] = sum1;
}
|
#include <hip/hip_runtime.h>
extern "C" __global__ void
mmkernel( float* a, float* b, float* c,
int pitch_a, int pitch_b, int pitch_c,
int n, int m, int p )
{
int tx = threadIdx.x;
int bx = blockDim.x;
int i = blockIdx.x*bx + tx;
int j = blockIdx.y*2;
__shared__ float cb0[512], cb1[512];
float sum0 = 0.0, sum1 = 0.0;
for( int ks = 0; ks < p; ks += bx ){
cb0[tx] = c[ks+tx+pitch_c*j];
cb1[tx] = c[ks+tx+pitch_c*(j+1)];
__syncthreads();
for( int k = ks; k < ks+bx; ++k ){
float rb = b[i+pitch_b*k];
sum0 += rb * cb0[k-ks];
sum1 += rb * cb1[k-ks];
}
__syncthreads();
}
a[i+pitch_a*j] = sum0;
a[i+pitch_a*(j+1)] = sum1;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
extern "C" __global__ void
mmkernel( float* a, float* b, float* c,
int pitch_a, int pitch_b, int pitch_c,
int n, int m, int p )
{
int tx = threadIdx.x;
int bx = blockDim.x;
int i = blockIdx.x*bx + tx;
int j = blockIdx.y*2;
__shared__ float cb0[512], cb1[512];
float sum0 = 0.0, sum1 = 0.0;
for( int ks = 0; ks < p; ks += bx ){
cb0[tx] = c[ks+tx+pitch_c*j];
cb1[tx] = c[ks+tx+pitch_c*(j+1)];
__syncthreads();
for( int k = ks; k < ks+bx; ++k ){
float rb = b[i+pitch_b*k];
sum0 += rb * cb0[k-ks];
sum1 += rb * cb1[k-ks];
}
__syncthreads();
}
a[i+pitch_a*j] = sum0;
a[i+pitch_a*(j+1)] = sum1;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected mmkernel
.globl mmkernel
.p2align 8
.type mmkernel,@function
mmkernel:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s10, s[0:1], 0x2c
s_lshl_b32 s3, s15, 1
s_mov_b32 s12, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s11, s2, 0xffff
s_cmp_lt_i32 s10, 1
v_mad_u64_u32 v[1:2], null, s14, s11, v[0:1]
s_cbranch_scc1 .LBB0_7
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x8
s_or_b32 s14, s3, 1
s_cmp_lg_u32 s11, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_dual_mov_b32 v7, v1 :: v_dual_lshlrev_b32 v6, 2, v0
s_cselect_b32 s2, -1, 0
v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0
v_cndmask_b32_e64 v2, 0, 1, s2
v_add_nc_u32_e32 v8, 0x800, v6
s_delay_alu instid0(VALU_DEP_2)
v_cmp_ne_u32_e64 s2, 1, v2
s_waitcnt lgkmcnt(0)
s_mul_i32 s13, s3, s9
s_mul_i32 s9, s14, s9
s_mul_i32 s14, s8, s11
.LBB0_2:
v_add_nc_u32_e32 v3, s12, v0
s_add_i32 s15, s12, s11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, s13, v3
v_add_nc_u32_e32 v9, s9, v3
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_add_co_u32 v2, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v9, vcc_lo, s6, v9
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
s_and_b32 vcc_lo, exec_lo, s2
s_clause 0x1
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[9:10], off
s_waitcnt vmcnt(1)
ds_store_b32 v6, v2
s_waitcnt vmcnt(0)
ds_store_b32 v8, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB0_5
v_mov_b32_e32 v2, v7
s_mov_b32 s16, 0
.p2align 6
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
s_add_i32 s12, s12, 1
v_lshlrev_b64 v[9:10], 2, v[2:3]
v_add_nc_u32_e32 v2, s8, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v9, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
global_load_b32 v3, v[9:10], off
v_mov_b32_e32 v9, s16
s_add_i32 s16, s16, 4
s_cmp_ge_u32 s12, s15
ds_load_2addr_stride64_b32 v[9:10], v9 offset1:8
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v4, v3, v9
v_fmac_f32_e32 v5, v3, v10
s_cbranch_scc0 .LBB0_4
.LBB0_5:
v_add_nc_u32_e32 v7, s14, v7
s_cmp_ge_i32 s15, s10
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_8
s_mov_b32 s12, s15
s_branch .LBB0_2
.LBB0_7:
v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0
.LBB0_8:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x18
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s3, s2, v[1:2]
s_or_b32 s3, s3, 1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[6:7], null, s3, s2, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_lshlrev_b64 v[2:3], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_clause 0x1
global_store_b32 v[0:1], v4, off
global_store_b32 v[2:3], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel mmkernel
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size mmkernel, .Lfunc_end0-mmkernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: mmkernel
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: mmkernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
extern "C" __global__ void
mmkernel( float* a, float* b, float* c,
int pitch_a, int pitch_b, int pitch_c,
int n, int m, int p )
{
int tx = threadIdx.x;
int bx = blockDim.x;
int i = blockIdx.x*bx + tx;
int j = blockIdx.y*2;
__shared__ float cb0[512], cb1[512];
float sum0 = 0.0, sum1 = 0.0;
for( int ks = 0; ks < p; ks += bx ){
cb0[tx] = c[ks+tx+pitch_c*j];
cb1[tx] = c[ks+tx+pitch_c*(j+1)];
__syncthreads();
for( int k = ks; k < ks+bx; ++k ){
float rb = b[i+pitch_b*k];
sum0 += rb * cb0[k-ks];
sum1 += rb * cb1[k-ks];
}
__syncthreads();
}
a[i+pitch_a*j] = sum0;
a[i+pitch_a*(j+1)] = sum1;
}
|
.text
.file "k4.hip"
.globl __device_stub__mmkernel # -- Begin function __device_stub__mmkernel
.p2align 4, 0x90
.type __device_stub__mmkernel,@function
__device_stub__mmkernel: # @__device_stub__mmkernel
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $mmkernel, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size __device_stub__mmkernel, .Lfunc_end0-__device_stub__mmkernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $mmkernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type mmkernel,@object # @mmkernel
.section .rodata,"a",@progbits
.globl mmkernel
.p2align 3, 0x0
mmkernel:
.quad __device_stub__mmkernel
.size mmkernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "mmkernel"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__mmkernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym mmkernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : mmkernel
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ MOV R2, c[0x0][0x18c] ; /* 0x0000630000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R19, -RZ, RZ, 0, 0 ; /* 0x00000000ff137435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe40003f06270 */
/*0070*/ MOV R17, RZ ; /* 0x000000ff00117202 */
/* 0x000fe20000000f00 */
/*0080*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e620000002600 */
/*0090*/ IMAD R2, R3, c[0x0][0x0], R0 ; /* 0x0000000003027a24 */
/* 0x001fe200078e0200 */
/*00a0*/ SHF.L.U32 R3, R4, 0x1, RZ ; /* 0x0000000104037819 */
/* 0x002fd000000006ff */
/*00b0*/ @!P0 BRA 0x1070 ; /* 0x00000fb000008947 */
/* 0x000fea0003800000 */
/*00c0*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x000fe2000001ff00 */
/*00d0*/ MOV R17, RZ ; /* 0x000000ff00117202 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R19, RZ ; /* 0x000000ff00137202 */
/* 0x000fc60000000f00 */
/*00f0*/ IADD3 R6, R0, R5, RZ ; /* 0x0000000500067210 */
/* 0x000fca0007ffe0ff */
/*0100*/ IMAD R9, R3, c[0x0][0x180], R6 ; /* 0x0000600003097a24 */
/* 0x000fe200078e0206 */
/*0110*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fc800000001ff */
/*0120*/ IADD3 R11, R9, c[0x0][0x180], RZ ; /* 0x00006000090b7a10 */
/* 0x000fcc0007ffe0ff */
/*0130*/ IMAD.WIDE R8, R9, R6, c[0x0][0x170] ; /* 0x00005c0009087625 */
/* 0x000fc800078e0206 */
/*0140*/ IMAD.WIDE R10, R11, R6, c[0x0][0x170] ; /* 0x00005c000b0a7625 */
/* 0x000fe400078e0206 */
/*0150*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x0000a8000c1e1900 */
/*0160*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ee2000c1e1900 */
/*0170*/ MOV R15, c[0x0][0x0] ; /* 0x00000000000f7a02 */
/* 0x000fe40000000f00 */
/*0180*/ MOV R7, R5 ; /* 0x0000000500077202 */
/* 0x000fe40000000f00 */
/*0190*/ ISETP.GE.AND P0, PT, R15, 0x1, PT ; /* 0x000000010f00780c */
/* 0x000fe20003f06270 */
/*01a0*/ IMAD R12, R4.reuse, R15.reuse, c[0x0][0x0] ; /* 0x00000000040c7624 */
/* 0x0c0fe200078e020f */
/*01b0*/ IADD3 R8, RZ, -c[0x0][0x0], RZ ; /* 0x80000000ff087a10 */
/* 0x001fe20007ffe0ff */
/*01c0*/ IMAD R13, R4, R15, 0x1 ; /* 0x00000001040d7424 */
/* 0x000fe200078e020f */
/*01d0*/ IADD3 R5, R5, c[0x0][0x0], RZ ; /* 0x0000000005057a10 */
/* 0x000fc80007ffe0ff */
/*01e0*/ IMNMX R13, R12, R13, !PT ; /* 0x0000000d0c0d7217 */
/* 0x000fe40007800200 */
/*01f0*/ ISETP.GE.AND P1, PT, R5, c[0x0][0x18c], PT ; /* 0x0000630005007a0c */
/* 0x000fc60003f26270 */
/*0200*/ IMAD R8, R4, R8, R13 ; /* 0x0000000804087224 */
/* 0x000fe200078e020d */
/*0210*/ STS [R0.X4], R9 ; /* 0x0000000900007388 */
/* 0x0041e80000004800 */
/*0220*/ STS [R0.X4+0x800], R11 ; /* 0x0008000b00007388 */
/* 0x0081e80000004800 */
/*0230*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0240*/ @!P0 BRA 0x1030 ; /* 0x00000de000008947 */
/* 0x000fea0003800000 */
/*0250*/ LOP3.LUT P2, R16, R8.reuse, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308107812 */
/* 0x041fe4000784c0ff */
/*0260*/ IADD3 R9, R8, -0x1, RZ ; /* 0xffffffff08097810 */
/* 0x000fc40007ffe0ff */
/*0270*/ MOV R8, R7 ; /* 0x0000000700087202 */
/* 0x000fe40000000f00 */
/*0280*/ ISETP.GE.U32.AND P0, PT, R9, 0x3, PT ; /* 0x000000030900780c */
/* 0x000fce0003f06070 */
/*0290*/ @!P2 BRA 0x410 ; /* 0x000001700000a947 */
/* 0x000fec0003800000 */
/*02a0*/ IMAD R23, R7, c[0x0][0x17c], R2 ; /* 0x00005f0007177a24 */
/* 0x000fe200078e0202 */
/*02b0*/ LDS.128 R8, [RZ] ; /* 0x00000000ff087984 */
/* 0x000e260000000c00 */
/*02c0*/ IMAD.WIDE R20, R23, R6, c[0x0][0x168] ; /* 0x00005a0017147625 */
/* 0x000fe200078e0206 */
/*02d0*/ LDS.128 R12, [0x800] ; /* 0x00080000ff0c7984 */
/* 0x000e6a0000000c00 */
/*02e0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000e22000c1e1900 */
/*02f0*/ ISETP.NE.AND P2, PT, R16, 0x1, PT ; /* 0x000000011000780c */
/* 0x000fe20003f45270 */
/*0300*/ FFMA R19, R8, R20, R19 ; /* 0x0000001408137223 */
/* 0x001fe20000000013 */
/*0310*/ IADD3 R8, R7, 0x1, RZ ; /* 0x0000000107087810 */
/* 0x000fe20007ffe0ff */
/*0320*/ FFMA R17, R20, R12, R17 ; /* 0x0000000c14117223 */
/* 0x002fd40000000011 */
/*0330*/ @!P2 BRA 0x410 ; /* 0x000000d00000a947 */
/* 0x000fea0003800000 */
/*0340*/ ISETP.NE.AND P2, PT, R16, 0x2, PT ; /* 0x000000021000780c */
/* 0x000fe40003f45270 */
/*0350*/ IADD3 R21, R23, c[0x0][0x17c], RZ ; /* 0x00005f0017157a10 */
/* 0x000fd60007ffe0ff */
/*0360*/ @P2 IADD3 R23, R21.reuse, c[0x0][0x17c], RZ ; /* 0x00005f0015172a10 */
/* 0x040fe20007ffe0ff */
/*0370*/ IMAD.WIDE R20, R21, R6, c[0x0][0x168] ; /* 0x00005a0015147625 */
/* 0x000fc800078e0206 */
/*0380*/ @P2 IMAD.WIDE R22, R23, R6, c[0x0][0x168] ; /* 0x00005a0017162625 */
/* 0x000fe400078e0206 */
/*0390*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ea8000c1e1900 */
/*03a0*/ @P2 LDG.E R22, [R22.64] ; /* 0x0000000416162981 */
/* 0x000ee2000c1e1900 */
/*03b0*/ IADD3 R8, R7.reuse, 0x2, RZ ; /* 0x0000000207087810 */
/* 0x040fe40007ffe0ff */
/*03c0*/ @P2 IADD3 R8, R7, 0x3, RZ ; /* 0x0000000307082810 */
/* 0x000fe20007ffe0ff */
/*03d0*/ FFMA R19, R20, R9, R19 ; /* 0x0000000914137223 */
/* 0x004fc40000000013 */
/*03e0*/ FFMA R17, R20, R13, R17 ; /* 0x0000000d14117223 */
/* 0x000fe40000000011 */
/*03f0*/ @P2 FFMA R19, R22.reuse, R10, R19 ; /* 0x0000000a16132223 */
/* 0x048fe40000000013 */
/*0400*/ @P2 FFMA R17, R22, R14, R17 ; /* 0x0000000e16112223 */
/* 0x000fe40000000011 */
/*0410*/ @!P0 BRA 0x1030 ; /* 0x00000c1000008947 */
/* 0x000fea0003800000 */
/*0420*/ IADD3 R9, R5, -R8, RZ ; /* 0x8000000805097210 */
/* 0x000fe20007ffe0ff */
/*0430*/ IMAD R23, R8.reuse, c[0x0][0x17c], R2 ; /* 0x00005f0008177a24 */
/* 0x040fe200078e0202 */
/*0440*/ IADD3 R7, R8, -R7, RZ ; /* 0x8000000708077210 */
/* 0x000fe40007ffe0ff */
/*0450*/ ISETP.GT.AND P2, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */
/* 0x000fe20003f44270 */
/*0460*/ IMAD.WIDE R22, R23, R6, c[0x0][0x168] ; /* 0x00005a0017167625 */
/* 0x000fe200078e0206 */
/*0470*/ SHF.L.U32 R7, R7, 0x2, RZ ; /* 0x0000000207077819 */
/* 0x000fc400000006ff */
/*0480*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0490*/ IADD3 R10, R7.reuse, 0x808, RZ ; /* 0x00000808070a7810 */
/* 0x040fe40007ffe0ff */
/*04a0*/ IADD3 R7, R7, 0x8, RZ ; /* 0x0000000807077810 */
/* 0x000fca0007ffe0ff */
/*04b0*/ @!P2 BRA 0xb30 ; /* 0x000006700000a947 */
/* 0x000fea0003800000 */
/*04c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*04d0*/ IADD3 R9, R5, -0xc, RZ ; /* 0xfffffff405097810 */
/* 0x000fe40007ffe0ff */
/*04e0*/ LDG.E R16, [R22.64] ; /* 0x0000000416107981 */
/* 0x0000a2000c1e1900 */
/*04f0*/ IMAD.WIDE R14, R6, c[0x0][0x17c], R22 ; /* 0x00005f00060e7a25 */
/* 0x000fc600078e0216 */
/*0500*/ LDS R21, [R7+-0x8] ; /* 0xfffff80007157984 */
/* 0x000fe80000000800 */
/*0510*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x0002e2000c1e1900 */
/*0520*/ IMAD.WIDE R28, R6, c[0x0][0x17c], R14 ; /* 0x00005f00061c7a25 */
/* 0x000fc600078e020e */
/*0530*/ LDS R27, [R7+-0x4] ; /* 0xfffffc00071b7984 */
/* 0x000fe80000000800 */
/*0540*/ LDG.E R20, [R28.64] ; /* 0x000000041c147981 */
/* 0x000964000c1e1900 */
/*0550*/ IMAD.WIDE R28, R6, c[0x0][0x17c], R28 ; /* 0x00005f00061c7a25 */
/* 0x010fca00078e021c */
/*0560*/ LDG.E R26, [R28.64] ; /* 0x000000041c1a7981 */
/* 0x000962000c1e1900 */
/*0570*/ IMAD.WIDE R24, R6, c[0x0][0x17c], R28 ; /* 0x00005f0006187a25 */
/* 0x000fca00078e021c */
/*0580*/ LDG.E R11, [R24.64] ; /* 0x00000004180b7981 */
/* 0x000168000c1e1900 */
/*0590*/ LDS R29, [R10+-0x4] ; /* 0xfffffc000a1d7984 */
/* 0x010fe20000000800 */
/*05a0*/ IMAD.WIDE R24, R6, c[0x0][0x17c], R24 ; /* 0x00005f0006187a25 */
/* 0x001fca00078e0218 */
/*05b0*/ LDG.E R12, [R24.64] ; /* 0x00000004180c7981 */
/* 0x000122000c1e1900 */
/*05c0*/ IMAD.WIDE R22, R6, c[0x0][0x17c], R24 ; /* 0x00005f0006167a25 */
/* 0x000fca00078e0218 */
/*05d0*/ LDG.E R13, [R22.64] ; /* 0x00000004160d7981 */
/* 0x000122000c1e1900 */
/*05e0*/ IMAD.WIDE R14, R6, c[0x0][0x17c], R22 ; /* 0x00005f00060e7a25 */
/* 0x002fc600078e0216 */
/*05f0*/ LDS R25, [R7] ; /* 0x0000000007197984 */
/* 0x001fe80000000800 */
/*0600*/ LDS R23, [R10+-0x8] ; /* 0xfffff8000a177984 */
/* 0x000ea80000000800 */
/*0610*/ LDG.E R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x000124000c1e1900 */
/*0620*/ IMAD.WIDE R14, R6, c[0x0][0x17c], R14 ; /* 0x00005f00060e7a25 */
/* 0x001fc800078e020e */
/*0630*/ FFMA R24, R16, R23, R17 ; /* 0x0000001710187223 */
/* 0x004fe40000000011 */
/*0640*/ FFMA R19, R21, R16, R19 ; /* 0x0000001015137223 */
/* 0x000fe20000000013 */
/*0650*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x0000a2000c1e1900 */
/*0660*/ IMAD.WIDE R16, R6, c[0x0][0x17c], R14 ; /* 0x00005f0006107a25 */
/* 0x000fc600078e020e */
/*0670*/ LDS R21, [R10] ; /* 0x000000000a157984 */
/* 0x000e620000000800 */
/*0680*/ FFMA R29, R18, R29, R24 ; /* 0x0000001d121d7223 */
/* 0x008fc60000000018 */
/*0690*/ LDG.E R24, [R16.64] ; /* 0x0000000410187981 */
/* 0x000ae2000c1e1900 */
/*06a0*/ FFMA R28, R27, R18, R19 ; /* 0x000000121b1c7223 */
/* 0x000fc60000000013 */
/*06b0*/ LDS R15, [R7+0x4] ; /* 0x00000400070f7984 */
/* 0x001e280000000800 */
/*06c0*/ LDS R27, [R10+0x4] ; /* 0x000004000a1b7984 */
/* 0x000e220000000800 */
/*06d0*/ IMAD.WIDE R18, R6, c[0x0][0x17c], R16 ; /* 0x00005f0006127a25 */
/* 0x000fc800078e0210 */
/*06e0*/ FFMA R16, R25, R20, R28 ; /* 0x0000001419107223 */
/* 0x020fe4000000001c */
/*06f0*/ LDS R28, [R7+0x8] ; /* 0x00000800071c7984 */
/* 0x000f680000000800 */
/*0700*/ LDG.E R25, [R18.64] ; /* 0x0000000412197981 */
/* 0x0002e4000c1e1900 */
/*0710*/ FFMA R14, R20, R21, R29 ; /* 0x00000015140e7223 */
/* 0x002fe4000000001d */
/*0720*/ LDS R29, [R10+0x8] ; /* 0x000008000a1d7984 */
/* 0x000e620000000800 */
/*0730*/ IMAD.WIDE R20, R6, c[0x0][0x17c], R18 ; /* 0x00005f0006147a25 */
/* 0x000fca00078e0212 */
/*0740*/ LDG.E R19, [R20.64] ; /* 0x0000000414137981 */
/* 0x000ae2000c1e1900 */
/*0750*/ FFMA R18, R15, R26, R16 ; /* 0x0000001a0f127223 */
/* 0x001fe40000000010 */
/*0760*/ FFMA R26, R26, R27, R14 ; /* 0x0000001b1a1a7223 */
/* 0x000fe4000000000e */
/*0770*/ IMAD.WIDE R14, R6.reuse, c[0x0][0x17c], R20 ; /* 0x00005f00060e7a25 */
/* 0x040fe400078e0214 */
/*0780*/ LDS R20, [R7+0xc] ; /* 0x00000c0007147984 */
/* 0x020f280000000800 */
/*0790*/ IMAD.WIDE R16, R6, c[0x0][0x17c], R14 ; /* 0x00005f0006107a25 */
/* 0x000fc400078e020e */
/*07a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000164000c1e1900 */
/*07b0*/ FFMA R15, R28, R11, R18 ; /* 0x0000000b1c0f7223 */
/* 0x001fe40000000012 */
/*07c0*/ FFMA R21, R11, R29, R26 ; /* 0x0000001d0b157223 */
/* 0x002fe4000000001a */
/*07d0*/ IMAD.WIDE R28, R6.reuse, c[0x0][0x17c], R16 ; /* 0x00005f00061c7a25 */
/* 0x040fe400078e0210 */
/*07e0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000168000c1e1900 */
/*07f0*/ IMAD.WIDE R26, R6, c[0x0][0x17c], R28 ; /* 0x00005f00061a7a25 */
/* 0x000fe200078e021c */
/*0800*/ LDG.E R11, [R28.64] ; /* 0x000000041c0b7981 */
/* 0x000768000c1e1900 */
/*0810*/ LDG.E R18, [R26.64] ; /* 0x000000041a127981 */
/* 0x000f62000c1e1900 */
/*0820*/ FFMA R20, R20, R12, R15 ; /* 0x0000000c14147223 */
/* 0x010fc6000000000f */
/*0830*/ LDS R17, [R7+0x14] ; /* 0x0000140007117984 */
/* 0x001fe80000000800 */
/*0840*/ LDS R15, [R10+0xc] ; /* 0x00000c000a0f7984 */
/* 0x000e240000000800 */
/*0850*/ FFMA R12, R12, R15, R21 ; /* 0x0000000f0c0c7223 */
/* 0x001fe40000000015 */
/*0860*/ LDS R15, [R7+0x10] ; /* 0x00001000070f7984 */
/* 0x000e280000000800 */
/*0870*/ LDS R21, [R10+0x10] ; /* 0x000010000a157984 */
/* 0x000e620000000800 */
/*0880*/ FFMA R15, R15, R13, R20 ; /* 0x0000000d0f0f7223 */
/* 0x001fc60000000014 */
/*0890*/ LDS R20, [R10+0x24] ; /* 0x000024000a147984 */
/* 0x000fe20000000800 */
/*08a0*/ FFMA R21, R13, R21, R12 ; /* 0x000000150d157223 */
/* 0x002fc6000000000c */
/*08b0*/ LDS R13, [R10+0x14] ; /* 0x000014000a0d7984 */
/* 0x000e220000000800 */
/*08c0*/ FFMA R12, R17, R22, R15 ; /* 0x00000016110c7223 */
/* 0x000fc6000000000f */
/*08d0*/ LDS R15, [R7+0x18] ; /* 0x00001800070f7984 */
/* 0x000ea80000000800 */
/*08e0*/ LDS R17, [R10+0x18] ; /* 0x000018000a117984 */
/* 0x000e620000000800 */
/*08f0*/ FFMA R22, R22, R13, R21 ; /* 0x0000000d16167223 */
/* 0x001fc60000000015 */
/*0900*/ LDS R13, [R7+0x1c] ; /* 0x00001c00070d7984 */
/* 0x000ee80000000800 */
/*0910*/ LDS R21, [R7+0x20] ; /* 0x0000200007157984 */
/* 0x000e220000000800 */
/*0920*/ FFMA R12, R15, R23, R12 ; /* 0x000000170f0c7223 */
/* 0x004fc6000000000c */
/*0930*/ LDS R15, [R10+0x1c] ; /* 0x00001c000a0f7984 */
/* 0x000ea20000000800 */
/*0940*/ FFMA R17, R23, R17, R22 ; /* 0x0000001117117223 */
/* 0x002fc60000000016 */
/*0950*/ LDS R22, [R10+0x20] ; /* 0x000020000a167984 */
/* 0x000e620000000800 */
/*0960*/ FFMA R28, R13, R24, R12 ; /* 0x000000180d1c7223 */
/* 0x008fc6000000000c */
/*0970*/ LDS R12, [R7+0x24] ; /* 0x00002400070c7984 */
/* 0x000ee80000000800 */
/*0980*/ LDS R13, [R7+0x28] ; /* 0x00002800070d7984 */
/* 0x000f680000000800 */
/*0990*/ LDS R23, [R10+0x34] ; /* 0x000034000a177984 */
/* 0x000fe20000000800 */
/*09a0*/ FFMA R28, R21, R25, R28 ; /* 0x00000019151c7223 */
/* 0x001fc6000000001c */
/*09b0*/ LDS R21, [R10+0x2c] ; /* 0x00002c000a157984 */
/* 0x000fe20000000800 */
/*09c0*/ FFMA R17, R24, R15, R17 ; /* 0x0000000f18117223 */
/* 0x004fc60000000011 */
/*09d0*/ LDS R15, [R10+0x28] ; /* 0x000028000a0f7984 */
/* 0x000e220000000800 */
/*09e0*/ FFMA R22, R25, R22, R17 ; /* 0x0000001619167223 */
/* 0x002fc60000000011 */
/*09f0*/ LDS R17, [R7+0x2c] ; /* 0x00002c0007117984 */
/* 0x000e620000000800 */
/*0a00*/ FFMA R28, R12, R19, R28 ; /* 0x000000130c1c7223 */
/* 0x008fe4000000001c */
/*0a10*/ FFMA R22, R19, R20, R22 ; /* 0x0000001413167223 */
/* 0x000fe20000000016 */
/*0a20*/ LDS R12, [R10+0x30] ; /* 0x000030000a0c7984 */
/* 0x0004e80000000800 */
/*0a30*/ LDS R20, [R7+0x30] ; /* 0x0000300007147984 */
/* 0x000f280000000800 */
/*0a40*/ LDS R19, [R7+0x34] ; /* 0x0000340007137984 */
/* 0x0001220000000800 */
/*0a50*/ IADD3 R8, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.GE.AND P2, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x000fe20003f46270 */
/*0a70*/ FFMA R13, R13, R14, R28 ; /* 0x0000000e0d0d7223 */
/* 0x020fe2000000001c */
/*0a80*/ IADD3 R10, R10, 0x40, RZ ; /* 0x000000400a0a7810 */
/* 0x004fe20007ffe0ff */
/*0a90*/ FFMA R15, R14, R15, R22 ; /* 0x0000000f0e0f7223 */
/* 0x001fc80000000016 */
/*0aa0*/ FFMA R15, R16, R21, R15 ; /* 0x00000015100f7223 */
/* 0x000fe4000000000f */
/*0ab0*/ FFMA R13, R17, R16, R13 ; /* 0x00000010110d7223 */
/* 0x002fe4000000000d */
/*0ac0*/ FFMA R12, R11, R12, R15 ; /* 0x0000000c0b0c7223 */
/* 0x008fe4000000000f */
/*0ad0*/ FFMA R13, R20, R11, R13 ; /* 0x0000000b140d7223 */
/* 0x010fe2000000000d */
/*0ae0*/ IADD3 R7, R7, 0x40, RZ ; /* 0x0000004007077810 */
/* 0x000fe20007ffe0ff */
/*0af0*/ FFMA R17, R18, R23, R12 ; /* 0x0000001712117223 */
/* 0x000fe4000000000c */
/*0b00*/ FFMA R19, R19, R18, R13 ; /* 0x0000001213137223 */
/* 0x000fc4000000000d */
/*0b10*/ IMAD.WIDE R22, R6, c[0x0][0x17c], R26 ; /* 0x00005f0006167a25 */
/* 0x000fe200078e021a */
/*0b20*/ @!P2 BRA 0x4e0 ; /* 0xfffff9b00000a947 */
/* 0x000fea000383ffff */
/*0b30*/ IADD3 R9, R5, -R8, RZ ; /* 0x8000000805097210 */
/* 0x000fc80007ffe0ff */
/*0b40*/ ISETP.GT.AND P2, PT, R9, 0x4, PT ; /* 0x000000040900780c */
/* 0x000fda0003f44270 */
/*0b50*/ @!P2 BRA 0xea0 ; /* 0x000003400000a947 */
/* 0x000fea0003800000 */
/*0b60*/ LDG.E R16, [R22.64] ; /* 0x0000000416107981 */
/* 0x0000a2000c1e1900 */
/*0b70*/ IMAD.WIDE R28, R6, c[0x0][0x17c], R22 ; /* 0x00005f00061c7a25 */
/* 0x000fca00078e0216 */
/*0b80*/ LDG.E R11, [R28.64] ; /* 0x000000041c0b7981 */
/* 0x0002e2000c1e1900 */
/*0b90*/ IMAD.WIDE R24, R6, c[0x0][0x17c], R28 ; /* 0x00005f0006187a25 */
/* 0x000fca00078e021c */
/*0ba0*/ LDG.E R9, [R24.64] ; /* 0x0000000418097981 */
/* 0x000962000c1e1900 */
/*0bb0*/ IMAD.WIDE R26, R6, c[0x0][0x17c], R24 ; /* 0x00005f00061a7a25 */
/* 0x000fc600078e0218 */
/*0bc0*/ LDS R29, [R10+-0x8] ; /* 0xfffff8000a1d7984 */
/* 0x002fe80000000800 */
/*0bd0*/ LDG.E R18, [R26.64] ; /* 0x000000041a127981 */
/* 0x000362000c1e1900 */
/*0be0*/ IMAD.WIDE R20, R6, c[0x0][0x17c], R26 ; /* 0x00005f0006147a25 */
/* 0x000fc600078e021a */
/*0bf0*/ LDS R25, [R7+-0x8] ; /* 0xfffff80007197984 */
/* 0x010ea60000000800 */
/*0c00*/ IMAD.WIDE R12, R6.reuse, c[0x0][0x17c], R20 ; /* 0x00005f00060c7a25 */
/* 0x040fe200078e0214 */
/*0c10*/ LDS R24, [R7+-0x4] ; /* 0xfffffc0007187984 */
/* 0x000ee80000000800 */
/*0c20*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000962000c1e1900 */
/*0c30*/ IMAD.WIDE R14, R6, c[0x0][0x17c], R12 ; /* 0x00005f00060e7a25 */
/* 0x000fc600078e020c */
/*0c40*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000966000c1e1900 */
/*0c50*/ IMAD.WIDE R22, R6.reuse, c[0x0][0x17c], R14 ; /* 0x00005f0006167a25 */
/* 0x041fe200078e020e */
/*0c60*/ LDS R26, [R10+-0x4] ; /* 0xfffffc000a1a7984 */
/* 0x002e280000000800 */
/*0c70*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*0c80*/ LDG.E R28, [R22.64] ; /* 0x00000004161c7981 */
/* 0x000368000c1e1900 */
/*0c90*/ LDS R13, [R10+0x4] ; /* 0x000004000a0d7984 */
/* 0x010fe80000000800 */
/*0ca0*/ LDS R15, [R10+0x8] ; /* 0x000008000a0f7984 */
/* 0x002fe80000000800 */
/*0cb0*/ LDS R21, [R7+0x10] ; /* 0x0000100007157984 */
/* 0x000fe20000000800 */
/*0cc0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0cd0*/ IMAD.WIDE R22, R6, c[0x0][0x17c], R22 ; /* 0x00005f0006167a25 */
/* 0x000fe200078e0216 */
/*0ce0*/ IADD3 R8, R8, 0x8, RZ ; /* 0x0000000808087810 */
/* 0x000fc60007ffe0ff */
/*0cf0*/ FFMA R25, R25, R16, R19 ; /* 0x0000001019197223 */
/* 0x004fe40000000013 */
/*0d00*/ FFMA R29, R16, R29, R17 ; /* 0x0000001d101d7223 */
/* 0x000fe20000000011 */
/*0d10*/ LDS R19, [R10] ; /* 0x000000000a137984 */
/* 0x000f680000000800 */
/*0d20*/ LDS R16, [R7] ; /* 0x0000000007107984 */
/* 0x000e680000000800 */
/*0d30*/ LDS R17, [R7+0x4] ; /* 0x0000040007117984 */
/* 0x000ea20000000800 */
/*0d40*/ FFMA R24, R24, R11, R25 ; /* 0x0000000b18187223 */
/* 0x008fc40000000019 */
/*0d50*/ FFMA R26, R11, R26, R29 ; /* 0x0000001a0b1a7223 */
/* 0x001fe2000000001d */
/*0d60*/ LDS R25, [R7+0x14] ; /* 0x0000140007197984 */
/* 0x000fe80000000800 */
/*0d70*/ LDS R11, [R7+0x8] ; /* 0x00000800070b7984 */
/* 0x000e220000000800 */
/*0d80*/ FFMA R26, R9, R19, R26 ; /* 0x00000013091a7223 */
/* 0x020fc6000000001a */
/*0d90*/ LDS R19, [R7+0xc] ; /* 0x00000c0007137984 */
/* 0x0007220000000800 */
/*0da0*/ FFMA R16, R16, R9, R24 ; /* 0x0000000910107223 */
/* 0x002fc60000000018 */
/*0db0*/ LDS R9, [R10+0xc] ; /* 0x00000c000a097984 */
/* 0x000e620000000800 */
/*0dc0*/ FFMA R16, R17, R18, R16 ; /* 0x0000001211107223 */
/* 0x004fc60000000010 */
/*0dd0*/ LDS R17, [R10+0x10] ; /* 0x000010000a117984 */
/* 0x000ea20000000800 */
/*0de0*/ FFMA R26, R18, R13, R26 ; /* 0x0000000d121a7223 */
/* 0x000fc6000000001a */
/*0df0*/ LDS R13, [R10+0x14] ; /* 0x000014000a0d7984 */
/* 0x000aa20000000800 */
/*0e00*/ FFMA R15, R20, R15, R26 ; /* 0x0000000f140f7223 */
/* 0x000fe4000000001a */
/*0e10*/ FFMA R11, R11, R20, R16 ; /* 0x000000140b0b7223 */
/* 0x001fe20000000010 */
/*0e20*/ IADD3 R7, R7, 0x20, RZ ; /* 0x0000002007077810 */
/* 0x008fe40007ffe0ff */
/*0e30*/ IADD3 R10, R10, 0x20, RZ ; /* 0x000000200a0a7810 */
/* 0x020fe20007ffe0ff */
/*0e40*/ FFMA R11, R19, R12, R11 ; /* 0x0000000c130b7223 */
/* 0x010fe4000000000b */
/*0e50*/ FFMA R9, R12, R9, R15 ; /* 0x000000090c097223 */
/* 0x002fe4000000000f */
/*0e60*/ FFMA R11, R21, R14, R11 ; /* 0x0000000e150b7223 */
/* 0x000fc4000000000b */
/*0e70*/ FFMA R17, R14, R17, R9 ; /* 0x000000110e117223 */
/* 0x004fe40000000009 */
/*0e80*/ FFMA R19, R25, R28, R11 ; /* 0x0000001c19137223 */
/* 0x000fe4000000000b */
/*0e90*/ FFMA R17, R28, R13, R17 ; /* 0x0000000d1c117223 */
/* 0x000fe40000000011 */
/*0ea0*/ ISETP.LT.OR P0, PT, R8, R5, P0 ; /* 0x000000050800720c */
/* 0x000fda0000701670 */
/*0eb0*/ @!P0 BRA 0x1030 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0ec0*/ IMAD.WIDE R12, R6.reuse, c[0x0][0x17c], R22 ; /* 0x00005f00060c7a25 */
/* 0x040fe200078e0216 */
/*0ed0*/ LDS R11, [R10+-0x8] ; /* 0xfffff8000a0b7984 */
/* 0x000fe80000000800 */
/*0ee0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x0000a2000c1e1900 */
/*0ef0*/ IMAD.WIDE R8, R6, c[0x0][0x17c], R12 ; /* 0x00005f0006087a25 */
/* 0x000fc600078e020c */
/*0f00*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x0002e6000c1e1900 */
/*0f10*/ IMAD.WIDE R14, R6, c[0x0][0x17c], R8 ; /* 0x00005f00060e7a25 */
/* 0x000fe200078e0208 */
/*0f20*/ LDS R21, [R7+-0x4] ; /* 0xfffffc0007157984 */
/* 0x000fe80000000800 */
/*0f30*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f28000c1e1900 */
/*0f40*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f68000c1e1900 */
/*0f50*/ LDS R6, [R7+-0x8] ; /* 0xfffff80007067984 */
/* 0x000ea80000000800 */
/*0f60*/ LDS R16, [R10+-0x4] ; /* 0xfffffc000a107984 */
/* 0x000ea80000000800 */
/*0f70*/ LDS R25, [R7] ; /* 0x0000000007197984 */
/* 0x000f280000000800 */
/*0f80*/ LDS R18, [R10] ; /* 0x000000000a127984 */
/* 0x000ea80000000800 */
/*0f90*/ LDS R23, [R7+0x4] ; /* 0x0000040007177984 */
/* 0x001f680000000800 */
/*0fa0*/ LDS R13, [R10+0x4] ; /* 0x000004000a0d7984 */
/* 0x002e220000000800 */
/*0fb0*/ FFMA R6, R6, R22, R19 ; /* 0x0000001606067223 */
/* 0x004fc40000000013 */
/*0fc0*/ FFMA R11, R22, R11, R17 ; /* 0x0000000b160b7223 */
/* 0x000fe40000000011 */
/*0fd0*/ FFMA R6, R21, R12, R6 ; /* 0x0000000c15067223 */
/* 0x008fe40000000006 */
/*0fe0*/ FFMA R11, R12, R16, R11 ; /* 0x000000100c0b7223 */
/* 0x000fe4000000000b */
/*0ff0*/ FFMA R6, R25, R8, R6 ; /* 0x0000000819067223 */
/* 0x010fe40000000006 */
/*1000*/ FFMA R11, R8, R18, R11 ; /* 0x00000012080b7223 */
/* 0x000fe4000000000b */
/*1010*/ FFMA R19, R23, R14, R6 ; /* 0x0000000e17137223 */
/* 0x020fc40000000006 */
/*1020*/ FFMA R17, R14, R13, R11 ; /* 0x0000000d0e117223 */
/* 0x001fe4000000000b */
/*1030*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x001fe20000010000 */
/*1040*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fca0007ffe0ff */
/*1050*/ @P1 CALL.REL.NOINC 0x1070 ; /* 0x0000001000001944 */
/* 0x000fe20003c00000 */
/*1060*/ BRA 0xf0 ; /* 0xfffff08000007947 */
/* 0x000fea000383ffff */
/*1070*/ IMAD R2, R3, c[0x0][0x178], R2 ; /* 0x00005e0003027a24 */
/* 0x000fe200078e0202 */
/*1080*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fc80000000f00 */
/*1090*/ IADD3 R4, R2.reuse, c[0x0][0x178], RZ ; /* 0x00005e0002047a10 */
/* 0x040fe20007ffe0ff */
/*10a0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e0205 */
/*10b0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe200078e0205 */
/*10c0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x000fe8000c101904 */
/*10d0*/ STG.E [R4.64], R17 ; /* 0x0000001104007986 */
/* 0x000fe2000c101904 */
/*10e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*10f0*/ BRA 0x10f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected mmkernel
.globl mmkernel
.p2align 8
.type mmkernel,@function
mmkernel:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s10, s[0:1], 0x2c
s_lshl_b32 s3, s15, 1
s_mov_b32 s12, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s11, s2, 0xffff
s_cmp_lt_i32 s10, 1
v_mad_u64_u32 v[1:2], null, s14, s11, v[0:1]
s_cbranch_scc1 .LBB0_7
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x8
s_or_b32 s14, s3, 1
s_cmp_lg_u32 s11, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_dual_mov_b32 v7, v1 :: v_dual_lshlrev_b32 v6, 2, v0
s_cselect_b32 s2, -1, 0
v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0
v_cndmask_b32_e64 v2, 0, 1, s2
v_add_nc_u32_e32 v8, 0x800, v6
s_delay_alu instid0(VALU_DEP_2)
v_cmp_ne_u32_e64 s2, 1, v2
s_waitcnt lgkmcnt(0)
s_mul_i32 s13, s3, s9
s_mul_i32 s9, s14, s9
s_mul_i32 s14, s8, s11
.LBB0_2:
v_add_nc_u32_e32 v3, s12, v0
s_add_i32 s15, s12, s11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, s13, v3
v_add_nc_u32_e32 v9, s9, v3
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_add_co_u32 v2, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v9, vcc_lo, s6, v9
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
s_and_b32 vcc_lo, exec_lo, s2
s_clause 0x1
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[9:10], off
s_waitcnt vmcnt(1)
ds_store_b32 v6, v2
s_waitcnt vmcnt(0)
ds_store_b32 v8, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB0_5
v_mov_b32_e32 v2, v7
s_mov_b32 s16, 0
.p2align 6
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
s_add_i32 s12, s12, 1
v_lshlrev_b64 v[9:10], 2, v[2:3]
v_add_nc_u32_e32 v2, s8, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v9, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
global_load_b32 v3, v[9:10], off
v_mov_b32_e32 v9, s16
s_add_i32 s16, s16, 4
s_cmp_ge_u32 s12, s15
ds_load_2addr_stride64_b32 v[9:10], v9 offset1:8
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v4, v3, v9
v_fmac_f32_e32 v5, v3, v10
s_cbranch_scc0 .LBB0_4
.LBB0_5:
v_add_nc_u32_e32 v7, s14, v7
s_cmp_ge_i32 s15, s10
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_8
s_mov_b32 s12, s15
s_branch .LBB0_2
.LBB0_7:
v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0
.LBB0_8:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x18
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s3, s2, v[1:2]
s_or_b32 s3, s3, 1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[6:7], null, s3, s2, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_lshlrev_b64 v[2:3], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_clause 0x1
global_store_b32 v[0:1], v4, off
global_store_b32 v[2:3], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel mmkernel
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size mmkernel, .Lfunc_end0-mmkernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: mmkernel
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: mmkernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00178726_00000000-6_k4.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z8mmkernelPfS_S_iiiiiiPfS_S_iiiiii
.type _Z37__device_stub__Z8mmkernelPfS_S_iiiiiiPfS_S_iiiiii, @function
_Z37__device_stub__Z8mmkernelPfS_S_iiiiiiPfS_S_iiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq mmkernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z8mmkernelPfS_S_iiiiiiPfS_S_iiiiii, .-_Z37__device_stub__Z8mmkernelPfS_S_iiiiiiPfS_S_iiiiii
.globl mmkernel
.type mmkernel, @function
mmkernel:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z37__device_stub__Z8mmkernelPfS_S_iiiiiiPfS_S_iiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size mmkernel, .-mmkernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "mmkernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq mmkernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "k4.hip"
.globl __device_stub__mmkernel # -- Begin function __device_stub__mmkernel
.p2align 4, 0x90
.type __device_stub__mmkernel,@function
__device_stub__mmkernel: # @__device_stub__mmkernel
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $mmkernel, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size __device_stub__mmkernel, .Lfunc_end0-__device_stub__mmkernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $mmkernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type mmkernel,@object # @mmkernel
.section .rodata,"a",@progbits
.globl mmkernel
.p2align 3, 0x0
mmkernel:
.quad __device_stub__mmkernel
.size mmkernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "mmkernel"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__mmkernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym mmkernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
//#include <helper_cuda.h>
#include "kernel.cuh"
__global__ void my_first_kernel(float *x)
{
int tid = threadIdx.x + blockDim.x*blockIdx.x;
x[tid] = (float) threadIdx.x;
}
void my_first(float *x, int nblocks, int nthreads)
{
my_first_kernel<<<nblocks,nthreads>>>(x);
}
|
code for sm_80
Function : _Z15my_first_kernelPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0050*/ I2F.U32 R5, R0 ; /* 0x0000000000057306 */
/* 0x001e220000201000 */
/*0060*/ IMAD R2, R3, c[0x0][0x0], R0 ; /* 0x0000000003027a24 */
/* 0x002fca00078e0200 */
/*0070*/ IMAD.WIDE R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0207 */
/*0080*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
//#include <helper_cuda.h>
#include "kernel.cuh"
__global__ void my_first_kernel(float *x)
{
int tid = threadIdx.x + blockDim.x*blockIdx.x;
x[tid] = (float) threadIdx.x;
}
void my_first(float *x, int nblocks, int nthreads)
{
my_first_kernel<<<nblocks,nthreads>>>(x);
}
|
.file "tmpxft_0005363b_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z15my_first_kernelPfPf
.type _Z35__device_stub__Z15my_first_kernelPfPf, @function
_Z35__device_stub__Z15my_first_kernelPfPf:
.LFB2052:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15my_first_kernelPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z35__device_stub__Z15my_first_kernelPfPf, .-_Z35__device_stub__Z15my_first_kernelPfPf
.globl _Z15my_first_kernelPf
.type _Z15my_first_kernelPf, @function
_Z15my_first_kernelPf:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z15my_first_kernelPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z15my_first_kernelPf, .-_Z15my_first_kernelPf
.globl _Z8my_firstPfii
.type _Z8my_firstPfii, @function
_Z8my_firstPfii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movl %edx, 20(%rsp)
movl $1, 24(%rsp)
movl %esi, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movq %rbx, %rdi
call _Z35__device_stub__Z15my_first_kernelPfPf
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z8my_firstPfii, .-_Z8my_firstPfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15my_first_kernelPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15my_first_kernelPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
//#include <helper_cuda.h>
#include "kernel.cuh"
__global__ void my_first_kernel(float *x)
{
int tid = threadIdx.x + blockDim.x*blockIdx.x;
x[tid] = (float) threadIdx.x;
}
void my_first(float *x, int nblocks, int nthreads)
{
my_first_kernel<<<nblocks,nthreads>>>(x);
}
|
#ifndef KERNEL_CUH
#define KERNEL_CUH
#include <hip/hip_runtime.h>
void my_first(float *x, int nblocks, int nthreads);
#endif // KERNEL_CUH
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#ifndef KERNEL_CUH
#define KERNEL_CUH
#include <hip/hip_runtime.h>
void my_first(float *x, int nblocks, int nthreads);
#endif // KERNEL_CUH
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#ifndef KERNEL_CUH
#define KERNEL_CUH
#include <hip/hip_runtime.h>
void my_first(float *x, int nblocks, int nthreads);
#endif // KERNEL_CUH
|
.text
.file "kernel.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z15my_first_kernelPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0050*/ I2F.U32 R5, R0 ; /* 0x0000000000057306 */
/* 0x001e220000201000 */
/*0060*/ IMAD R2, R3, c[0x0][0x0], R0 ; /* 0x0000000003027a24 */
/* 0x002fca00078e0200 */
/*0070*/ IMAD.WIDE R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0207 */
/*0080*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0005363b_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z15my_first_kernelPfPf
.type _Z35__device_stub__Z15my_first_kernelPfPf, @function
_Z35__device_stub__Z15my_first_kernelPfPf:
.LFB2052:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15my_first_kernelPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z35__device_stub__Z15my_first_kernelPfPf, .-_Z35__device_stub__Z15my_first_kernelPfPf
.globl _Z15my_first_kernelPf
.type _Z15my_first_kernelPf, @function
_Z15my_first_kernelPf:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z15my_first_kernelPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z15my_first_kernelPf, .-_Z15my_first_kernelPf
.globl _Z8my_firstPfii
.type _Z8my_firstPfii, @function
_Z8my_firstPfii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movl %edx, 20(%rsp)
movl $1, 24(%rsp)
movl %esi, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movq %rbx, %rdi
call _Z35__device_stub__Z15my_first_kernelPfPf
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z8my_firstPfii, .-_Z8my_firstPfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15my_first_kernelPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15my_first_kernelPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "kernel.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
__global__ void matmul(const float *a, const float *b, float *c, int n, int m){
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
//printf("%d %d %d %d %d %d\n",blockDim.x,blockDim.y,blockIdx.x,blockIdx.y,threadIdx.x,threadIdx.y);
int idx = j * n + i;
if(i < n and j < m){
//printf("%d %d %d %d %d %d\n", i, j, idx, a[idx], b[idx], c[idx]);
float sum = 0;
for(int k = 0; k < n; k++){
int idxa = j * n + k;
int idxb = k * n + i;
sum += a[idxa] * b[idxb];
}
c[idx] = sum;
}
}
|
code for sm_80
Function : _Z6matmulPKfS0_Pfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x17c], PT ; /* 0x00005f0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xc00 ; /* 0x00000b0000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0150*/ @!P0 BRA 0xb00 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*01a0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*01b0*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */
/* 0x000fcc00078e0219 */
/*01d0*/ @!P0 BRA 0x970 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6b0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0270*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0280*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0290*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*02a0*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*02b0*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*02c0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*02d0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02e0*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*02f0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*0300*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*0320*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*0330*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0340*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*0350*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0360*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0370*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0380*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0390*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*03a0*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */
/* 0x004fc6000000001c */
/*03b0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03d0*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*03e0*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x008fe4000000001d */
/*03f0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*0400*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0410*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*0420*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*0430*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0440*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */
/* 0x000fc4000000001d */
/*0450*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*0460*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0490*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*04a0*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */
/* 0x020fc6000000001a */
/*04b0*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*04c0*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */
/* 0x000fe40000000009 */
/*04d0*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*04e0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04f0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*0500*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */
/* 0x000fc6000000000b */
/*0510*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*0520*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*0530*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0540*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0550*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0560*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0570*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0580*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */
/* 0x004fc60000000015 */
/*0590*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*05b0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*05c0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05e0*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x000fc80000000009 */
/*05f0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fc80000000007 */
/*0600*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x020fc80000000007 */
/*0610*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */
/* 0x010fe20000000007 */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0650*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x008fc80000000007 */
/*0660*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */
/* 0x004fc80000000007 */
/*0670*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */
/* 0x000fe4000000001c */
/*0680*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0690*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */
/* 0x000fe2000000001c */
/*06a0*/ @P1 BRA 0x220 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x950 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06d0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*06e0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06f0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0710*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe200078e0210 */
/*0720*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0730*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fe200078e0208 */
/*0740*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0750*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0760*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0770*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0780*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0790*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*07a0*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*07b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07c0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07d0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*07e0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07f0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*0800*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*0810*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0830*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0840*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0850*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0860*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0870*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0880*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0890*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*08a0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08b0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08c0*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */
/* 0x004fc8000000001c */
/*08d0*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */
/* 0x008fc80000000007 */
/*08e0*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */
/* 0x020fc80000000007 */
/*08f0*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */
/* 0x000fc80000000007 */
/*0900*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x000fc80000000007 */
/*0910*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x010fc80000000007 */
/*0920*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */
/* 0x000fe40000000007 */
/*0930*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*0940*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */
/* 0x000fe40000000007 */
/*0950*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0960*/ @!P0 BRA 0xb00 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0970*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0980*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0990*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*09a0*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fc800078e0208 */
/*09c0*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*09d0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09f0*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*0a00*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*0a10*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a30*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a40*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a50*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */
/* 0x004fc8000000001c */
/*0ab0*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */
/* 0x008fe40000000007 */
/*0ac0*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0ad0*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x010fc80000000007 */
/*0ae0*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */
/* 0x020fe20000000007 */
/*0af0*/ @P0 BRA 0x970 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc00 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0b20*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b30*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x000fe20007ffe0ff */
/*0b40*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fd000078e0200 */
/*0b50*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b60*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fca00078e0209 */
/*0b70*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b80*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b90*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0ba0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0bb0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0bc0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0bd0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0be0*/ FFMA R28, R11, R4, R28 ; /* 0x000000040b1c7223 */
/* 0x004fcc000000001c */
/*0bf0*/ @P0 BRA 0xb70 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0c00*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c10*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*0c20*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c30*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c50*/ BRA 0xc50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void matmul(const float *a, const float *b, float *c, int n, int m){
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
//printf("%d %d %d %d %d %d\n",blockDim.x,blockDim.y,blockIdx.x,blockIdx.y,threadIdx.x,threadIdx.y);
int idx = j * n + i;
if(i < n and j < m){
//printf("%d %d %d %d %d %d\n", i, j, idx, a[idx], b[idx], c[idx]);
float sum = 0;
for(int k = 0; k < n; k++){
int idxa = j * n + k;
int idxb = k * n + i;
sum += a[idxa] * b[idxb];
}
c[idx] = sum;
}
}
|
.file "tmpxft_000f6a1e_00000000-6_matmul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z6matmulPKfS0_PfiiPKfS0_Pfii
.type _Z33__device_stub__Z6matmulPKfS0_PfiiPKfS0_Pfii, @function
_Z33__device_stub__Z6matmulPKfS0_PfiiPKfS0_Pfii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6matmulPKfS0_Pfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z6matmulPKfS0_PfiiPKfS0_Pfii, .-_Z33__device_stub__Z6matmulPKfS0_PfiiPKfS0_Pfii
.globl _Z6matmulPKfS0_Pfii
.type _Z6matmulPKfS0_Pfii, @function
_Z6matmulPKfS0_Pfii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z6matmulPKfS0_PfiiPKfS0_Pfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6matmulPKfS0_Pfii, .-_Z6matmulPKfS0_Pfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6matmulPKfS0_Pfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6matmulPKfS0_Pfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void matmul(const float *a, const float *b, float *c, int n, int m){
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
//printf("%d %d %d %d %d %d\n",blockDim.x,blockDim.y,blockIdx.x,blockIdx.y,threadIdx.x,threadIdx.y);
int idx = j * n + i;
if(i < n and j < m){
//printf("%d %d %d %d %d %d\n", i, j, idx, a[idx], b[idx], c[idx]);
float sum = 0;
for(int k = 0; k < n; k++){
int idxa = j * n + k;
int idxb = k * n + i;
sum += a[idxa] * b[idxb];
}
c[idx] = sum;
}
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matmul(const float *a, const float *b, float *c, int n, int m){
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
//printf("%d %d %d %d %d %d\n",blockDim.x,blockDim.y,blockIdx.x,blockIdx.y,threadIdx.x,threadIdx.y);
int idx = j * n + i;
if(i < n and j < m){
//printf("%d %d %d %d %d %d\n", i, j, idx, a[idx], b[idx], c[idx]);
float sum = 0;
for(int k = 0; k < n; k++){
int idxa = j * n + k;
int idxb = k * n + i;
sum += a[idxa] * b[idxb];
}
c[idx] = sum;
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matmul(const float *a, const float *b, float *c, int n, int m){
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
//printf("%d %d %d %d %d %d\n",blockDim.x,blockDim.y,blockIdx.x,blockIdx.y,threadIdx.x,threadIdx.y);
int idx = j * n + i;
if(i < n and j < m){
//printf("%d %d %d %d %d %d\n", i, j, idx, a[idx], b[idx], c[idx]);
float sum = 0;
for(int k = 0; k < n; k++){
int idxa = j * n + k;
int idxb = k * n + i;
sum += a[idxa] * b[idxb];
}
c[idx] = sum;
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6matmulPKfS0_Pfii
.globl _Z6matmulPKfS0_Pfii
.p2align 8
.type _Z6matmulPKfS0_Pfii,@function
_Z6matmulPKfS0_Pfii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[8:9], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s9, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_6
v_mul_lo_u32 v1, v1, s8
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_mov_b32 s2, s8
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s8, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v1, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6matmulPKfS0_Pfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6matmulPKfS0_Pfii, .Lfunc_end0-_Z6matmulPKfS0_Pfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6matmulPKfS0_Pfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6matmulPKfS0_Pfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matmul(const float *a, const float *b, float *c, int n, int m){
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
//printf("%d %d %d %d %d %d\n",blockDim.x,blockDim.y,blockIdx.x,blockIdx.y,threadIdx.x,threadIdx.y);
int idx = j * n + i;
if(i < n and j < m){
//printf("%d %d %d %d %d %d\n", i, j, idx, a[idx], b[idx], c[idx]);
float sum = 0;
for(int k = 0; k < n; k++){
int idxa = j * n + k;
int idxb = k * n + i;
sum += a[idxa] * b[idxb];
}
c[idx] = sum;
}
}
|
.text
.file "matmul.hip"
.globl _Z21__device_stub__matmulPKfS0_Pfii # -- Begin function _Z21__device_stub__matmulPKfS0_Pfii
.p2align 4, 0x90
.type _Z21__device_stub__matmulPKfS0_Pfii,@function
_Z21__device_stub__matmulPKfS0_Pfii: # @_Z21__device_stub__matmulPKfS0_Pfii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6matmulPKfS0_Pfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__matmulPKfS0_Pfii, .Lfunc_end0-_Z21__device_stub__matmulPKfS0_Pfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6matmulPKfS0_Pfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6matmulPKfS0_Pfii,@object # @_Z6matmulPKfS0_Pfii
.section .rodata,"a",@progbits
.globl _Z6matmulPKfS0_Pfii
.p2align 3, 0x0
_Z6matmulPKfS0_Pfii:
.quad _Z21__device_stub__matmulPKfS0_Pfii
.size _Z6matmulPKfS0_Pfii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6matmulPKfS0_Pfii"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__matmulPKfS0_Pfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6matmulPKfS0_Pfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z6matmulPKfS0_Pfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x17c], PT ; /* 0x00005f0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xc00 ; /* 0x00000b0000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0150*/ @!P0 BRA 0xb00 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*01a0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*01b0*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */
/* 0x000fcc00078e0219 */
/*01d0*/ @!P0 BRA 0x970 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6b0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0270*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0280*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0290*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*02a0*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*02b0*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*02c0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*02d0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02e0*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*02f0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*0300*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*0320*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*0330*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0340*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*0350*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0360*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0370*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0380*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0390*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*03a0*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */
/* 0x004fc6000000001c */
/*03b0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03d0*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*03e0*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x008fe4000000001d */
/*03f0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*0400*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0410*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*0420*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*0430*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0440*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */
/* 0x000fc4000000001d */
/*0450*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*0460*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0490*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*04a0*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */
/* 0x020fc6000000001a */
/*04b0*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*04c0*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */
/* 0x000fe40000000009 */
/*04d0*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*04e0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04f0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*0500*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */
/* 0x000fc6000000000b */
/*0510*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*0520*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*0530*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0540*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0550*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0560*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0570*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0580*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */
/* 0x004fc60000000015 */
/*0590*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*05b0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*05c0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05e0*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x000fc80000000009 */
/*05f0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fc80000000007 */
/*0600*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x020fc80000000007 */
/*0610*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */
/* 0x010fe20000000007 */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0650*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x008fc80000000007 */
/*0660*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */
/* 0x004fc80000000007 */
/*0670*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */
/* 0x000fe4000000001c */
/*0680*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0690*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */
/* 0x000fe2000000001c */
/*06a0*/ @P1 BRA 0x220 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x950 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06d0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*06e0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06f0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0710*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe200078e0210 */
/*0720*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0730*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fe200078e0208 */
/*0740*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0750*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0760*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0770*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0780*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0790*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*07a0*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*07b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07c0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07d0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*07e0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07f0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*0800*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*0810*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0830*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0840*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0850*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0860*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0870*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0880*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0890*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*08a0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08b0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08c0*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */
/* 0x004fc8000000001c */
/*08d0*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */
/* 0x008fc80000000007 */
/*08e0*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */
/* 0x020fc80000000007 */
/*08f0*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */
/* 0x000fc80000000007 */
/*0900*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x000fc80000000007 */
/*0910*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x010fc80000000007 */
/*0920*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */
/* 0x000fe40000000007 */
/*0930*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*0940*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */
/* 0x000fe40000000007 */
/*0950*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0960*/ @!P0 BRA 0xb00 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0970*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0980*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0990*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*09a0*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fc800078e0208 */
/*09c0*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*09d0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09f0*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*0a00*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*0a10*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a30*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a40*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a50*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */
/* 0x004fc8000000001c */
/*0ab0*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */
/* 0x008fe40000000007 */
/*0ac0*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0ad0*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x010fc80000000007 */
/*0ae0*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */
/* 0x020fe20000000007 */
/*0af0*/ @P0 BRA 0x970 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc00 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0b20*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b30*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x000fe20007ffe0ff */
/*0b40*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fd000078e0200 */
/*0b50*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b60*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fca00078e0209 */
/*0b70*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b80*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b90*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0ba0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0bb0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0bc0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0bd0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0be0*/ FFMA R28, R11, R4, R28 ; /* 0x000000040b1c7223 */
/* 0x004fcc000000001c */
/*0bf0*/ @P0 BRA 0xb70 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0c00*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c10*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*0c20*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c30*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c50*/ BRA 0xc50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6matmulPKfS0_Pfii
.globl _Z6matmulPKfS0_Pfii
.p2align 8
.type _Z6matmulPKfS0_Pfii,@function
_Z6matmulPKfS0_Pfii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[8:9], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s9, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_6
v_mul_lo_u32 v1, v1, s8
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_mov_b32 s2, s8
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s8, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v1, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6matmulPKfS0_Pfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6matmulPKfS0_Pfii, .Lfunc_end0-_Z6matmulPKfS0_Pfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6matmulPKfS0_Pfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6matmulPKfS0_Pfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000f6a1e_00000000-6_matmul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z6matmulPKfS0_PfiiPKfS0_Pfii
.type _Z33__device_stub__Z6matmulPKfS0_PfiiPKfS0_Pfii, @function
_Z33__device_stub__Z6matmulPKfS0_PfiiPKfS0_Pfii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6matmulPKfS0_Pfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z6matmulPKfS0_PfiiPKfS0_Pfii, .-_Z33__device_stub__Z6matmulPKfS0_PfiiPKfS0_Pfii
.globl _Z6matmulPKfS0_Pfii
.type _Z6matmulPKfS0_Pfii, @function
_Z6matmulPKfS0_Pfii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z6matmulPKfS0_PfiiPKfS0_Pfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6matmulPKfS0_Pfii, .-_Z6matmulPKfS0_Pfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6matmulPKfS0_Pfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6matmulPKfS0_Pfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "matmul.hip"
.globl _Z21__device_stub__matmulPKfS0_Pfii # -- Begin function _Z21__device_stub__matmulPKfS0_Pfii
.p2align 4, 0x90
.type _Z21__device_stub__matmulPKfS0_Pfii,@function
_Z21__device_stub__matmulPKfS0_Pfii: # @_Z21__device_stub__matmulPKfS0_Pfii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6matmulPKfS0_Pfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__matmulPKfS0_Pfii, .Lfunc_end0-_Z21__device_stub__matmulPKfS0_Pfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6matmulPKfS0_Pfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6matmulPKfS0_Pfii,@object # @_Z6matmulPKfS0_Pfii
.section .rodata,"a",@progbits
.globl _Z6matmulPKfS0_Pfii
.p2align 3, 0x0
_Z6matmulPKfS0_Pfii:
.quad _Z21__device_stub__matmulPKfS0_Pfii
.size _Z6matmulPKfS0_Pfii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6matmulPKfS0_Pfii"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__matmulPKfS0_Pfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6matmulPKfS0_Pfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
extern "C" __global__ void
mmkernel( float* a, float* b, float* c,
int pitch_a, int pitch_b, int pitch_c,
int n, int m, int p )
{
// This is a shared memory version of k1.
int tx = threadIdx.x;
int i = blockIdx.x*32 + tx;
int j = blockIdx.y;
__shared__ float cb[32];
float sum = 0.0;
for( int ks = 0; ks < p; ks += 32 ){
cb[tx] = c[ks+tx+pitch_c*j];
for( int k = ks; k < ks+32; ++k )
sum += b[i+pitch_b*k] * cb[k-ks];
}
a[i+pitch_a*j] = sum;
}
|
code for sm_80
Function : mmkernel
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0020*/ MOV R2, c[0x0][0x18c] ; /* 0x0000630000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f06270 */
/*0070*/ HFMA2.MMA R15, -RZ, RZ, 0, 0 ; /* 0x00000000ff0f7435 */
/* 0x000fe400000001ff */
/*0080*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002600 */
/*0090*/ LEA R9, R9, R0, 0x5 ; /* 0x0000000009097211 */
/* 0x001fca00078e28ff */
/*00a0*/ IMAD R6, R5, c[0x0][0x178], R9 ; /* 0x00005e0005067a24 */
/* 0x002fc800078e0209 */
/*00b0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe200078e0207 */
/*00c0*/ @!P0 BRA 0x820 ; /* 0x0000075000008947 */
/* 0x000fea0003800000 */
/*00d0*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*00e0*/ IMAD R5, R5, c[0x0][0x180], R0 ; /* 0x0000600005057a24 */
/* 0x000fe200078e0200 */
/*00f0*/ MOV R15, RZ ; /* 0x000000ff000f7202 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD.WIDE R4, R5, R2, c[0x0][0x170] ; /* 0x00005c0005047625 */
/* 0x000fc800078e0202 */
/*0120*/ IMAD.WIDE R8, R9, R2, c[0x0][0x168] ; /* 0x00005a0009087625 */
/* 0x000fca00078e0202 */
/*0130*/ LDG.E R17, [R4.64] ; /* 0x0000000404117981 */
/* 0x000ea2000c1e1900 */
/*0140*/ IMAD.WIDE R10, R2, c[0x0][0x17c], R8 ; /* 0x00005f00020a7a25 */
/* 0x000fc600078e0208 */
/*0150*/ LDG.E R14, [R8.64] ; /* 0x00000004080e7981 */
/* 0x0000e6000c1e1900 */
/*0160*/ IMAD.WIDE R20, R2.reuse, c[0x0][0x17c], R10 ; /* 0x00005f0002147a25 */
/* 0x040fe200078e020a */
/*0170*/ LDG.E R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000128000c1e1900 */
/*0180*/ LDG.E R13, [R20.64] ; /* 0x00000004140d7981 */
/* 0x000362000c1e1900 */
/*0190*/ IMAD.WIDE R24, R2, c[0x0][0x17c], R20 ; /* 0x00005f0002187a25 */
/* 0x000fca00078e0214 */
/*01a0*/ LDG.E R16, [R24.64] ; /* 0x0000000418107981 */
/* 0x0000e2000c1e1900 */
/*01b0*/ IMAD.WIDE R36, R2, c[0x0][0x17c], R24 ; /* 0x00005f0002247a25 */
/* 0x000fca00078e0218 */
/*01c0*/ LDG.E R19, [R36.64] ; /* 0x0000000424137981 */
/* 0x0000e2000c1e1900 */
/*01d0*/ IMAD.WIDE R28, R2, c[0x0][0x17c], R36 ; /* 0x00005f00021c7a25 */
/* 0x000fcc00078e0224 */
/*01e0*/ IMAD.WIDE R30, R2.reuse, c[0x0][0x17c], R28 ; /* 0x00005f00021e7a25 */
/* 0x040fe400078e021c */
/*01f0*/ LDG.E R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x000ee8000c1e1900 */
/*0200*/ LDG.E R27, [R30.64] ; /* 0x000000041e1b7981 */
/* 0x0000e2000c1e1900 */
/*0210*/ IMAD.WIDE R22, R2, c[0x0][0x17c], R30 ; /* 0x00005f0002167a25 */
/* 0x000fca00078e021e */
/*0220*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x0002e2000c1e1900 */
/*0230*/ IMAD.WIDE R34, R2, c[0x0][0x17c], R22 ; /* 0x00005f0002227a25 */
/* 0x000fca00078e0216 */
/*0240*/ LDG.E R25, [R34.64] ; /* 0x0000000422197981 */
/* 0x001162000c1e1900 */
/*0250*/ IMAD.WIDE R32, R2, c[0x0][0x17c], R34 ; /* 0x00005f0002207a25 */
/* 0x000fca00078e0222 */
/*0260*/ LDG.E R24, [R32.64] ; /* 0x0000000420187981 */
/* 0x000162000c1e1900 */
/*0270*/ IMAD.WIDE R20, R2, c[0x0][0x17c], R32 ; /* 0x00005f0002147a25 */
/* 0x002fcc00078e0220 */
/*0280*/ IMAD.WIDE R36, R2.reuse, c[0x0][0x17c], R20 ; /* 0x00005f0002247a25 */
/* 0x040fe400078e0214 */
/*0290*/ LDG.E R21, [R20.64] ; /* 0x0000000414157981 */
/* 0x000368000c1e1900 */
/*02a0*/ IMAD.WIDE R30, R2, c[0x0][0x17c], R36 ; /* 0x00005f00021e7a25 */
/* 0x000fe200078e0224 */
/*02b0*/ LDG.E R22, [R36.64] ; /* 0x0000000424167981 */
/* 0x000168000c1e1900 */
/*02c0*/ LDG.E R23, [R30.64] ; /* 0x000000041e177981 */
/* 0x000168000c1e1900 */
/*02d0*/ STS [R0.X4], R17 ; /* 0x0000001100007388 */
/* 0x004fe80000004800 */
/*02e0*/ LDS.128 R8, [RZ] ; /* 0x00000000ff087984 */
/* 0x000ee40000000c00 */
/*02f0*/ FFMA R8, R8, R14, R15 ; /* 0x0000000e08087223 */
/* 0x008fc8000000000f */
/*0300*/ FFMA R8, R12, R9, R8 ; /* 0x000000090c087223 */
/* 0x010fc80000000008 */
/*0310*/ FFMA R10, R13, R10, R8 ; /* 0x0000000a0d0a7223 */
/* 0x020fe40000000008 */
/*0320*/ LDS.128 R12, [0x10] ; /* 0x00001000ff0c7984 */
/* 0x000ea20000000c00 */
/*0330*/ IMAD.WIDE R8, R2, c[0x0][0x17c], R30 ; /* 0x00005f0002087a25 */
/* 0x000fca00078e021e */
/*0340*/ LDG.E R18, [R8.64] ; /* 0x0000000408127981 */
/* 0x000722000c1e1900 */
/*0350*/ IMAD.WIDE R34, R2, c[0x0][0x17c], R8 ; /* 0x00005f0002227a25 */
/* 0x001fca00078e0208 */
/*0360*/ LDG.E R17, [R34.64] ; /* 0x0000000422117981 */
/* 0x000162000c1e1900 */
/*0370*/ IMAD.WIDE R32, R2, c[0x0][0x17c], R34 ; /* 0x00005f0002207a25 */
/* 0x000fc800078e0222 */
/*0380*/ FFMA R11, R16, R11, R10 ; /* 0x0000000b100b7223 */
/* 0x000fe4000000000a */
/*0390*/ LDG.E R16, [R32.64] ; /* 0x0000000420107981 */
/* 0x000162000c1e1900 */
/*03a0*/ IMAD.WIDE R36, R2, c[0x0][0x17c], R32 ; /* 0x00005f0002247a25 */
/* 0x000fc800078e0220 */
/*03b0*/ FFMA R11, R12, R19, R11 ; /* 0x000000130c0b7223 */
/* 0x004fe4000000000b */
/*03c0*/ LDG.E R19, [R36.64] ; /* 0x0000000424137981 */
/* 0x000562000c1e1900 */
/*03d0*/ IMAD.WIDE R30, R2, c[0x0][0x17c], R36 ; /* 0x00005f00021e7a25 */
/* 0x000fca00078e0224 */
/*03e0*/ LDG.E R20, [R30.64] ; /* 0x000000041e147981 */
/* 0x002362000c1e1900 */
/*03f0*/ FFMA R11, R28, R13, R11 ; /* 0x0000000d1c0b7223 */
/* 0x000fc8000000000b */
/*0400*/ FFMA R14, R27, R14, R11 ; /* 0x0000000e1b0e7223 */
/* 0x000fe4000000000b */
/*0410*/ LDS.128 R8, [0x20] ; /* 0x00002000ff087984 */
/* 0x008ee40000000c00 */
/*0420*/ FFMA R14, R26, R15, R14 ; /* 0x0000000f1a0e7223 */
/* 0x000fe4000000000e */
/*0430*/ IMAD.WIDE R34, R2, c[0x0][0x17c], R30 ; /* 0x00005f0002227a25 */
/* 0x001fca00078e021e */
/*0440*/ LDG.E R29, [R34.64] ; /* 0x00000004221d7981 */
/* 0x000162000c1e1900 */
/*0450*/ IMAD.WIDE R32, R2, c[0x0][0x17c], R34 ; /* 0x00005f0002207a25 */
/* 0x000fca00078e0222 */
/*0460*/ LDG.E R28, [R32.64] ; /* 0x00000004201c7981 */
/* 0x000162000c1e1900 */
/*0470*/ FFMA R8, R8, R25, R14 ; /* 0x0000001908087223 */
/* 0x008fc6000000000e */
/*0480*/ LDS.128 R12, [0x30] ; /* 0x00003000ff0c7984 */
/* 0x000ee20000000c00 */
/*0490*/ FFMA R8, R24, R9, R8 ; /* 0x0000000918087223 */
/* 0x000fe40000000008 */
/*04a0*/ IMAD.WIDE R26, R2, c[0x0][0x17c], R32 ; /* 0x00005f00021a7a25 */
/* 0x000fc800078e0220 */
/*04b0*/ FFMA R8, R21, R10, R8 ; /* 0x0000000a15087223 */
/* 0x000fe40000000008 */
/*04c0*/ IMAD.WIDE R36, R2, c[0x0][0x17c], R26 ; /* 0x00005f0002247a25 */
/* 0x004fe400078e021a */
/*04d0*/ LDG.E R27, [R26.64] ; /* 0x000000041a1b7981 */
/* 0x000564000c1e1900 */
/*04e0*/ FFMA R8, R22, R11, R8 ; /* 0x0000000b16087223 */
/* 0x000fe40000000008 */
/*04f0*/ IMAD.WIDE R32, R2, c[0x0][0x17c], R36 ; /* 0x00005f0002207a25 */
/* 0x001fca00078e0224 */
/*0500*/ LDG.E R25, [R32.64] ; /* 0x0000000420197981 */
/* 0x000168000c1e1900 */
/*0510*/ LDG.E R26, [R36.64] ; /* 0x00000004241a7981 */
/* 0x004562000c1e1900 */
/*0520*/ IMAD.WIDE R34, R2, c[0x0][0x17c], R32 ; /* 0x00005f0002227a25 */
/* 0x000fca00078e0220 */
/*0530*/ LDG.E R24, [R34.64] ; /* 0x0000000422187981 */
/* 0x000162000c1e1900 */
/*0540*/ FFMA R12, R12, R23, R8 ; /* 0x000000170c0c7223 */
/* 0x008fc60000000008 */
/*0550*/ LDS.128 R8, [0x40] ; /* 0x00004000ff087984 */
/* 0x000ee20000000c00 */
/*0560*/ IMAD.WIDE R30, R2, c[0x0][0x17c], R34 ; /* 0x00005f00021e7a25 */
/* 0x002fcc00078e0222 */
/*0570*/ IMAD.WIDE R22, R2, c[0x0][0x17c], R30 ; /* 0x00005f0002167a25 */
/* 0x000fc800078e021e */
/*0580*/ FFMA R13, R18, R13, R12 ; /* 0x0000000d120d7223 */
/* 0x010fc8000000000c */
/*0590*/ FFMA R13, R17, R14, R13 ; /* 0x0000000e110d7223 */
/* 0x020fe4000000000d */
/*05a0*/ LDG.E R17, [R30.64] ; /* 0x000000041e117981 */
/* 0x000324000c1e1900 */
/*05b0*/ FFMA R13, R16, R15, R13 ; /* 0x0000000f100d7223 */
/* 0x000fe4000000000d */
/*05c0*/ IMAD.WIDE R14, R2, c[0x0][0x17c], R22 ; /* 0x00005f00020e7a25 */
/* 0x000fe200078e0216 */
/*05d0*/ LDG.E R16, [R22.64] ; /* 0x0000000416107981 */
/* 0x000b26000c1e1900 */
/*05e0*/ FFMA R8, R8, R19, R13 ; /* 0x0000001308087223 */
/* 0x008fc4000000000d */
/*05f0*/ IMAD.WIDE R12, R2.reuse, c[0x0][0x17c], R14 ; /* 0x00005f00020c7a25 */
/* 0x040fe200078e020e */
/*0600*/ LDG.E R19, [R14.64] ; /* 0x000000040e137981 */
/* 0x000728000c1e1900 */
/*0610*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000722000c1e1900 */
/*0620*/ IMAD.WIDE R36, R2, c[0x0][0x17c], R12 ; /* 0x00005f0002247a25 */
/* 0x004fca00078e020c */
/*0630*/ LDG.E R21, [R36.64] ; /* 0x0000000424157981 */
/* 0x000ea2000c1e1900 */
/*0640*/ IMAD.WIDE R34, R2, c[0x0][0x17c], R36 ; /* 0x00005f0002227a25 */
/* 0x001fc600078e0224 */
/*0650*/ LDS.128 R12, [0x50] ; /* 0x00005000ff0c7984 */
/* 0x008e220000000c00 */
/*0660*/ FFMA R9, R20, R9, R8 ; /* 0x0000000914097223 */
/* 0x000fe40000000008 */
/*0670*/ IMAD.WIDE R32, R2.reuse, c[0x0][0x17c], R34 ; /* 0x00005f0002207a25 */
/* 0x040fe200078e0222 */
/*0680*/ LDG.E R20, [R34.64] ; /* 0x0000000422147981 */
/* 0x000ee8000c1e1900 */
/*0690*/ LDG.E R23, [R32.64] ; /* 0x0000000420177981 */
/* 0x020f62000c1e1900 */
/*06a0*/ IMAD.WIDE R30, R2, c[0x0][0x17c], R32 ; /* 0x00005f00021e7a25 */
/* 0x002fca00078e0220 */
/*06b0*/ LDG.E R22, [R30.64] ; /* 0x000000041e167981 */
/* 0x000f62000c1e1900 */
/*06c0*/ FFMA R9, R29, R10, R9 ; /* 0x0000000a1d097223 */
/* 0x000fc80000000009 */
/*06d0*/ FFMA R9, R28, R11, R9 ; /* 0x0000000b1c097223 */
/* 0x000fc80000000009 */
/*06e0*/ FFMA R9, R12, R27, R9 ; /* 0x0000001b0c097223 */
/* 0x001fc80000000009 */
/*06f0*/ FFMA R13, R26, R13, R9 ; /* 0x0000000d1a0d7223 */
/* 0x000fe40000000009 */
/*0700*/ LDS.128 R8, [0x60] ; /* 0x00006000ff087984 */
/* 0x000f240000000c00 */
/*0710*/ FFMA R13, R25, R14, R13 ; /* 0x0000000e190d7223 */
/* 0x000fc8000000000d */
/*0720*/ FFMA R24, R24, R15, R13 ; /* 0x0000000f18187223 */
/* 0x000fe4000000000d */
/*0730*/ LDS.128 R12, [0x70] ; /* 0x00007000ff0c7984 */
/* 0x000ea20000000c00 */
/*0740*/ IADD3 R3, R3, 0x20, RZ ; /* 0x0000002003037810 */
/* 0x000fc80007ffe0ff */
/*0750*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x18c], PT ; /* 0x0000630003007a0c */
/* 0x000fe40003f06270 */
/*0760*/ IADD3 R4, P1, R4, 0x80, RZ ; /* 0x0000008004047810 */
/* 0x000fc80007f3e0ff */
/*0770*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x000fe20000ffe4ff */
/*0780*/ FFMA R8, R8, R17, R24 ; /* 0x0000001108087223 */
/* 0x010fc80000000018 */
/*0790*/ FFMA R8, R16, R9, R8 ; /* 0x0000000910087223 */
/* 0x000fc80000000008 */
/*07a0*/ FFMA R8, R19, R10, R8 ; /* 0x0000000a13087223 */
/* 0x000fc80000000008 */
/*07b0*/ FFMA R8, R18, R11, R8 ; /* 0x0000000b12087223 */
/* 0x000fc80000000008 */
/*07c0*/ FFMA R8, R12, R21, R8 ; /* 0x000000150c087223 */
/* 0x004fc80000000008 */
/*07d0*/ FFMA R8, R20, R13, R8 ; /* 0x0000000d14087223 */
/* 0x008fc80000000008 */
/*07e0*/ FFMA R8, R23, R14, R8 ; /* 0x0000000e17087223 */
/* 0x020fc80000000008 */
/*07f0*/ FFMA R15, R22, R15, R8 ; /* 0x0000000f160f7223 */
/* 0x000fe40000000008 */
/*0800*/ IMAD.WIDE R8, R2, c[0x0][0x17c], R30 ; /* 0x00005f0002087a25 */
/* 0x000fe200078e021e */
/*0810*/ @!P0 BRA 0x130 ; /* 0xfffff91000008947 */
/* 0x000fea000383ffff */
/*0820*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x000fe2000c101904 */
/*0830*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0840*/ BRA 0x840; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
extern "C" __global__ void
mmkernel( float* a, float* b, float* c,
int pitch_a, int pitch_b, int pitch_c,
int n, int m, int p )
{
// This is a shared memory version of k1.
int tx = threadIdx.x;
int i = blockIdx.x*32 + tx;
int j = blockIdx.y;
__shared__ float cb[32];
float sum = 0.0;
for( int ks = 0; ks < p; ks += 32 ){
cb[tx] = c[ks+tx+pitch_c*j];
for( int k = ks; k < ks+32; ++k )
sum += b[i+pitch_b*k] * cb[k-ks];
}
a[i+pitch_a*j] = sum;
}
|
.file "tmpxft_001ba659_00000000-6_k2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z8mmkernelPfS_S_iiiiiiPfS_S_iiiiii
.type _Z37__device_stub__Z8mmkernelPfS_S_iiiiiiPfS_S_iiiiii, @function
_Z37__device_stub__Z8mmkernelPfS_S_iiiiiiPfS_S_iiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq mmkernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z8mmkernelPfS_S_iiiiiiPfS_S_iiiiii, .-_Z37__device_stub__Z8mmkernelPfS_S_iiiiiiPfS_S_iiiiii
.globl mmkernel
.type mmkernel, @function
mmkernel:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z37__device_stub__Z8mmkernelPfS_S_iiiiiiPfS_S_iiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size mmkernel, .-mmkernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "mmkernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq mmkernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
extern "C" __global__ void
mmkernel( float* a, float* b, float* c,
int pitch_a, int pitch_b, int pitch_c,
int n, int m, int p )
{
// This is a shared memory version of k1.
int tx = threadIdx.x;
int i = blockIdx.x*32 + tx;
int j = blockIdx.y;
__shared__ float cb[32];
float sum = 0.0;
for( int ks = 0; ks < p; ks += 32 ){
cb[tx] = c[ks+tx+pitch_c*j];
for( int k = ks; k < ks+32; ++k )
sum += b[i+pitch_b*k] * cb[k-ks];
}
a[i+pitch_a*j] = sum;
}
|
#include <hip/hip_runtime.h>
extern "C" __global__ void
mmkernel( float* a, float* b, float* c,
int pitch_a, int pitch_b, int pitch_c,
int n, int m, int p )
{
// This is a shared memory version of k1.
int tx = threadIdx.x;
int i = blockIdx.x*32 + tx;
int j = blockIdx.y;
__shared__ float cb[32];
float sum = 0.0;
for( int ks = 0; ks < p; ks += 32 ){
cb[tx] = c[ks+tx+pitch_c*j];
for( int k = ks; k < ks+32; ++k )
sum += b[i+pitch_b*k] * cb[k-ks];
}
a[i+pitch_a*j] = sum;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
extern "C" __global__ void
mmkernel( float* a, float* b, float* c,
int pitch_a, int pitch_b, int pitch_c,
int n, int m, int p )
{
// This is a shared memory version of k1.
int tx = threadIdx.x;
int i = blockIdx.x*32 + tx;
int j = blockIdx.y;
__shared__ float cb[32];
float sum = 0.0;
for( int ks = 0; ks < p; ks += 32 ){
cb[tx] = c[ks+tx+pitch_c*j];
for( int k = ks; k < ks+32; ++k )
sum += b[i+pitch_b*k] * cb[k-ks];
}
a[i+pitch_a*j] = sum;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected mmkernel
.globl mmkernel
.p2align 8
.type mmkernel,@function
mmkernel:
s_load_b32 s8, s[0:1], 0x2c
v_lshl_add_u32 v1, s14, 5, v0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB0_5
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x8
v_dual_mov_b32 v6, v1 :: v_dual_lshlrev_b32 v5, 2, v0
s_mov_b32 s9, 0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, s15, s3, v[0:1]
v_mov_b32_e32 v0, 0
s_lshl_b32 s3, s2, 5
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, s9, v2
s_mov_b32 s10, 0
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v4, v[3:4], off
v_mov_b32_e32 v3, v6
s_waitcnt vmcnt(0)
ds_store_b32 v5, v4
.LBB0_3:
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[3:4]
v_add_nc_u32_e32 v3, s2, v3
v_add_co_u32 v7, vcc_lo, s4, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
global_load_b32 v4, v[7:8], off
v_mov_b32_e32 v7, s10
s_add_i32 s10, s10, 4
s_cmpk_eq_i32 s10, 0x80
ds_load_b32 v7, v7
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v0, v4, v7
s_cbranch_scc0 .LBB0_3
v_add_nc_u32_e32 v6, s3, v6
s_add_i32 s9, s9, 32
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s9, s8
s_cbranch_scc1 .LBB0_2
s_branch .LBB0_6
.LBB0_5:
v_mov_b32_e32 v0, 0
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_clause 0x1
s_load_b32 s2, s[0:1], 0x18
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[1:2], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel mmkernel
.amdhsa_group_segment_fixed_size 128
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size mmkernel, .Lfunc_end0-mmkernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 128
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: mmkernel
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: mmkernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
extern "C" __global__ void
mmkernel( float* a, float* b, float* c,
int pitch_a, int pitch_b, int pitch_c,
int n, int m, int p )
{
// This is a shared memory version of k1.
int tx = threadIdx.x;
int i = blockIdx.x*32 + tx;
int j = blockIdx.y;
__shared__ float cb[32];
float sum = 0.0;
for( int ks = 0; ks < p; ks += 32 ){
cb[tx] = c[ks+tx+pitch_c*j];
for( int k = ks; k < ks+32; ++k )
sum += b[i+pitch_b*k] * cb[k-ks];
}
a[i+pitch_a*j] = sum;
}
|
.text
.file "k2.hip"
.globl __device_stub__mmkernel # -- Begin function __device_stub__mmkernel
.p2align 4, 0x90
.type __device_stub__mmkernel,@function
__device_stub__mmkernel: # @__device_stub__mmkernel
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $mmkernel, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size __device_stub__mmkernel, .Lfunc_end0-__device_stub__mmkernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $mmkernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type mmkernel,@object # @mmkernel
.section .rodata,"a",@progbits
.globl mmkernel
.p2align 3, 0x0
mmkernel:
.quad __device_stub__mmkernel
.size mmkernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "mmkernel"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__mmkernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym mmkernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : mmkernel
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0020*/ MOV R2, c[0x0][0x18c] ; /* 0x0000630000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f06270 */
/*0070*/ HFMA2.MMA R15, -RZ, RZ, 0, 0 ; /* 0x00000000ff0f7435 */
/* 0x000fe400000001ff */
/*0080*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002600 */
/*0090*/ LEA R9, R9, R0, 0x5 ; /* 0x0000000009097211 */
/* 0x001fca00078e28ff */
/*00a0*/ IMAD R6, R5, c[0x0][0x178], R9 ; /* 0x00005e0005067a24 */
/* 0x002fc800078e0209 */
/*00b0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe200078e0207 */
/*00c0*/ @!P0 BRA 0x820 ; /* 0x0000075000008947 */
/* 0x000fea0003800000 */
/*00d0*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*00e0*/ IMAD R5, R5, c[0x0][0x180], R0 ; /* 0x0000600005057a24 */
/* 0x000fe200078e0200 */
/*00f0*/ MOV R15, RZ ; /* 0x000000ff000f7202 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD.WIDE R4, R5, R2, c[0x0][0x170] ; /* 0x00005c0005047625 */
/* 0x000fc800078e0202 */
/*0120*/ IMAD.WIDE R8, R9, R2, c[0x0][0x168] ; /* 0x00005a0009087625 */
/* 0x000fca00078e0202 */
/*0130*/ LDG.E R17, [R4.64] ; /* 0x0000000404117981 */
/* 0x000ea2000c1e1900 */
/*0140*/ IMAD.WIDE R10, R2, c[0x0][0x17c], R8 ; /* 0x00005f00020a7a25 */
/* 0x000fc600078e0208 */
/*0150*/ LDG.E R14, [R8.64] ; /* 0x00000004080e7981 */
/* 0x0000e6000c1e1900 */
/*0160*/ IMAD.WIDE R20, R2.reuse, c[0x0][0x17c], R10 ; /* 0x00005f0002147a25 */
/* 0x040fe200078e020a */
/*0170*/ LDG.E R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000128000c1e1900 */
/*0180*/ LDG.E R13, [R20.64] ; /* 0x00000004140d7981 */
/* 0x000362000c1e1900 */
/*0190*/ IMAD.WIDE R24, R2, c[0x0][0x17c], R20 ; /* 0x00005f0002187a25 */
/* 0x000fca00078e0214 */
/*01a0*/ LDG.E R16, [R24.64] ; /* 0x0000000418107981 */
/* 0x0000e2000c1e1900 */
/*01b0*/ IMAD.WIDE R36, R2, c[0x0][0x17c], R24 ; /* 0x00005f0002247a25 */
/* 0x000fca00078e0218 */
/*01c0*/ LDG.E R19, [R36.64] ; /* 0x0000000424137981 */
/* 0x0000e2000c1e1900 */
/*01d0*/ IMAD.WIDE R28, R2, c[0x0][0x17c], R36 ; /* 0x00005f00021c7a25 */
/* 0x000fcc00078e0224 */
/*01e0*/ IMAD.WIDE R30, R2.reuse, c[0x0][0x17c], R28 ; /* 0x00005f00021e7a25 */
/* 0x040fe400078e021c */
/*01f0*/ LDG.E R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x000ee8000c1e1900 */
/*0200*/ LDG.E R27, [R30.64] ; /* 0x000000041e1b7981 */
/* 0x0000e2000c1e1900 */
/*0210*/ IMAD.WIDE R22, R2, c[0x0][0x17c], R30 ; /* 0x00005f0002167a25 */
/* 0x000fca00078e021e */
/*0220*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x0002e2000c1e1900 */
/*0230*/ IMAD.WIDE R34, R2, c[0x0][0x17c], R22 ; /* 0x00005f0002227a25 */
/* 0x000fca00078e0216 */
/*0240*/ LDG.E R25, [R34.64] ; /* 0x0000000422197981 */
/* 0x001162000c1e1900 */
/*0250*/ IMAD.WIDE R32, R2, c[0x0][0x17c], R34 ; /* 0x00005f0002207a25 */
/* 0x000fca00078e0222 */
/*0260*/ LDG.E R24, [R32.64] ; /* 0x0000000420187981 */
/* 0x000162000c1e1900 */
/*0270*/ IMAD.WIDE R20, R2, c[0x0][0x17c], R32 ; /* 0x00005f0002147a25 */
/* 0x002fcc00078e0220 */
/*0280*/ IMAD.WIDE R36, R2.reuse, c[0x0][0x17c], R20 ; /* 0x00005f0002247a25 */
/* 0x040fe400078e0214 */
/*0290*/ LDG.E R21, [R20.64] ; /* 0x0000000414157981 */
/* 0x000368000c1e1900 */
/*02a0*/ IMAD.WIDE R30, R2, c[0x0][0x17c], R36 ; /* 0x00005f00021e7a25 */
/* 0x000fe200078e0224 */
/*02b0*/ LDG.E R22, [R36.64] ; /* 0x0000000424167981 */
/* 0x000168000c1e1900 */
/*02c0*/ LDG.E R23, [R30.64] ; /* 0x000000041e177981 */
/* 0x000168000c1e1900 */
/*02d0*/ STS [R0.X4], R17 ; /* 0x0000001100007388 */
/* 0x004fe80000004800 */
/*02e0*/ LDS.128 R8, [RZ] ; /* 0x00000000ff087984 */
/* 0x000ee40000000c00 */
/*02f0*/ FFMA R8, R8, R14, R15 ; /* 0x0000000e08087223 */
/* 0x008fc8000000000f */
/*0300*/ FFMA R8, R12, R9, R8 ; /* 0x000000090c087223 */
/* 0x010fc80000000008 */
/*0310*/ FFMA R10, R13, R10, R8 ; /* 0x0000000a0d0a7223 */
/* 0x020fe40000000008 */
/*0320*/ LDS.128 R12, [0x10] ; /* 0x00001000ff0c7984 */
/* 0x000ea20000000c00 */
/*0330*/ IMAD.WIDE R8, R2, c[0x0][0x17c], R30 ; /* 0x00005f0002087a25 */
/* 0x000fca00078e021e */
/*0340*/ LDG.E R18, [R8.64] ; /* 0x0000000408127981 */
/* 0x000722000c1e1900 */
/*0350*/ IMAD.WIDE R34, R2, c[0x0][0x17c], R8 ; /* 0x00005f0002227a25 */
/* 0x001fca00078e0208 */
/*0360*/ LDG.E R17, [R34.64] ; /* 0x0000000422117981 */
/* 0x000162000c1e1900 */
/*0370*/ IMAD.WIDE R32, R2, c[0x0][0x17c], R34 ; /* 0x00005f0002207a25 */
/* 0x000fc800078e0222 */
/*0380*/ FFMA R11, R16, R11, R10 ; /* 0x0000000b100b7223 */
/* 0x000fe4000000000a */
/*0390*/ LDG.E R16, [R32.64] ; /* 0x0000000420107981 */
/* 0x000162000c1e1900 */
/*03a0*/ IMAD.WIDE R36, R2, c[0x0][0x17c], R32 ; /* 0x00005f0002247a25 */
/* 0x000fc800078e0220 */
/*03b0*/ FFMA R11, R12, R19, R11 ; /* 0x000000130c0b7223 */
/* 0x004fe4000000000b */
/*03c0*/ LDG.E R19, [R36.64] ; /* 0x0000000424137981 */
/* 0x000562000c1e1900 */
/*03d0*/ IMAD.WIDE R30, R2, c[0x0][0x17c], R36 ; /* 0x00005f00021e7a25 */
/* 0x000fca00078e0224 */
/*03e0*/ LDG.E R20, [R30.64] ; /* 0x000000041e147981 */
/* 0x002362000c1e1900 */
/*03f0*/ FFMA R11, R28, R13, R11 ; /* 0x0000000d1c0b7223 */
/* 0x000fc8000000000b */
/*0400*/ FFMA R14, R27, R14, R11 ; /* 0x0000000e1b0e7223 */
/* 0x000fe4000000000b */
/*0410*/ LDS.128 R8, [0x20] ; /* 0x00002000ff087984 */
/* 0x008ee40000000c00 */
/*0420*/ FFMA R14, R26, R15, R14 ; /* 0x0000000f1a0e7223 */
/* 0x000fe4000000000e */
/*0430*/ IMAD.WIDE R34, R2, c[0x0][0x17c], R30 ; /* 0x00005f0002227a25 */
/* 0x001fca00078e021e */
/*0440*/ LDG.E R29, [R34.64] ; /* 0x00000004221d7981 */
/* 0x000162000c1e1900 */
/*0450*/ IMAD.WIDE R32, R2, c[0x0][0x17c], R34 ; /* 0x00005f0002207a25 */
/* 0x000fca00078e0222 */
/*0460*/ LDG.E R28, [R32.64] ; /* 0x00000004201c7981 */
/* 0x000162000c1e1900 */
/*0470*/ FFMA R8, R8, R25, R14 ; /* 0x0000001908087223 */
/* 0x008fc6000000000e */
/*0480*/ LDS.128 R12, [0x30] ; /* 0x00003000ff0c7984 */
/* 0x000ee20000000c00 */
/*0490*/ FFMA R8, R24, R9, R8 ; /* 0x0000000918087223 */
/* 0x000fe40000000008 */
/*04a0*/ IMAD.WIDE R26, R2, c[0x0][0x17c], R32 ; /* 0x00005f00021a7a25 */
/* 0x000fc800078e0220 */
/*04b0*/ FFMA R8, R21, R10, R8 ; /* 0x0000000a15087223 */
/* 0x000fe40000000008 */
/*04c0*/ IMAD.WIDE R36, R2, c[0x0][0x17c], R26 ; /* 0x00005f0002247a25 */
/* 0x004fe400078e021a */
/*04d0*/ LDG.E R27, [R26.64] ; /* 0x000000041a1b7981 */
/* 0x000564000c1e1900 */
/*04e0*/ FFMA R8, R22, R11, R8 ; /* 0x0000000b16087223 */
/* 0x000fe40000000008 */
/*04f0*/ IMAD.WIDE R32, R2, c[0x0][0x17c], R36 ; /* 0x00005f0002207a25 */
/* 0x001fca00078e0224 */
/*0500*/ LDG.E R25, [R32.64] ; /* 0x0000000420197981 */
/* 0x000168000c1e1900 */
/*0510*/ LDG.E R26, [R36.64] ; /* 0x00000004241a7981 */
/* 0x004562000c1e1900 */
/*0520*/ IMAD.WIDE R34, R2, c[0x0][0x17c], R32 ; /* 0x00005f0002227a25 */
/* 0x000fca00078e0220 */
/*0530*/ LDG.E R24, [R34.64] ; /* 0x0000000422187981 */
/* 0x000162000c1e1900 */
/*0540*/ FFMA R12, R12, R23, R8 ; /* 0x000000170c0c7223 */
/* 0x008fc60000000008 */
/*0550*/ LDS.128 R8, [0x40] ; /* 0x00004000ff087984 */
/* 0x000ee20000000c00 */
/*0560*/ IMAD.WIDE R30, R2, c[0x0][0x17c], R34 ; /* 0x00005f00021e7a25 */
/* 0x002fcc00078e0222 */
/*0570*/ IMAD.WIDE R22, R2, c[0x0][0x17c], R30 ; /* 0x00005f0002167a25 */
/* 0x000fc800078e021e */
/*0580*/ FFMA R13, R18, R13, R12 ; /* 0x0000000d120d7223 */
/* 0x010fc8000000000c */
/*0590*/ FFMA R13, R17, R14, R13 ; /* 0x0000000e110d7223 */
/* 0x020fe4000000000d */
/*05a0*/ LDG.E R17, [R30.64] ; /* 0x000000041e117981 */
/* 0x000324000c1e1900 */
/*05b0*/ FFMA R13, R16, R15, R13 ; /* 0x0000000f100d7223 */
/* 0x000fe4000000000d */
/*05c0*/ IMAD.WIDE R14, R2, c[0x0][0x17c], R22 ; /* 0x00005f00020e7a25 */
/* 0x000fe200078e0216 */
/*05d0*/ LDG.E R16, [R22.64] ; /* 0x0000000416107981 */
/* 0x000b26000c1e1900 */
/*05e0*/ FFMA R8, R8, R19, R13 ; /* 0x0000001308087223 */
/* 0x008fc4000000000d */
/*05f0*/ IMAD.WIDE R12, R2.reuse, c[0x0][0x17c], R14 ; /* 0x00005f00020c7a25 */
/* 0x040fe200078e020e */
/*0600*/ LDG.E R19, [R14.64] ; /* 0x000000040e137981 */
/* 0x000728000c1e1900 */
/*0610*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000722000c1e1900 */
/*0620*/ IMAD.WIDE R36, R2, c[0x0][0x17c], R12 ; /* 0x00005f0002247a25 */
/* 0x004fca00078e020c */
/*0630*/ LDG.E R21, [R36.64] ; /* 0x0000000424157981 */
/* 0x000ea2000c1e1900 */
/*0640*/ IMAD.WIDE R34, R2, c[0x0][0x17c], R36 ; /* 0x00005f0002227a25 */
/* 0x001fc600078e0224 */
/*0650*/ LDS.128 R12, [0x50] ; /* 0x00005000ff0c7984 */
/* 0x008e220000000c00 */
/*0660*/ FFMA R9, R20, R9, R8 ; /* 0x0000000914097223 */
/* 0x000fe40000000008 */
/*0670*/ IMAD.WIDE R32, R2.reuse, c[0x0][0x17c], R34 ; /* 0x00005f0002207a25 */
/* 0x040fe200078e0222 */
/*0680*/ LDG.E R20, [R34.64] ; /* 0x0000000422147981 */
/* 0x000ee8000c1e1900 */
/*0690*/ LDG.E R23, [R32.64] ; /* 0x0000000420177981 */
/* 0x020f62000c1e1900 */
/*06a0*/ IMAD.WIDE R30, R2, c[0x0][0x17c], R32 ; /* 0x00005f00021e7a25 */
/* 0x002fca00078e0220 */
/*06b0*/ LDG.E R22, [R30.64] ; /* 0x000000041e167981 */
/* 0x000f62000c1e1900 */
/*06c0*/ FFMA R9, R29, R10, R9 ; /* 0x0000000a1d097223 */
/* 0x000fc80000000009 */
/*06d0*/ FFMA R9, R28, R11, R9 ; /* 0x0000000b1c097223 */
/* 0x000fc80000000009 */
/*06e0*/ FFMA R9, R12, R27, R9 ; /* 0x0000001b0c097223 */
/* 0x001fc80000000009 */
/*06f0*/ FFMA R13, R26, R13, R9 ; /* 0x0000000d1a0d7223 */
/* 0x000fe40000000009 */
/*0700*/ LDS.128 R8, [0x60] ; /* 0x00006000ff087984 */
/* 0x000f240000000c00 */
/*0710*/ FFMA R13, R25, R14, R13 ; /* 0x0000000e190d7223 */
/* 0x000fc8000000000d */
/*0720*/ FFMA R24, R24, R15, R13 ; /* 0x0000000f18187223 */
/* 0x000fe4000000000d */
/*0730*/ LDS.128 R12, [0x70] ; /* 0x00007000ff0c7984 */
/* 0x000ea20000000c00 */
/*0740*/ IADD3 R3, R3, 0x20, RZ ; /* 0x0000002003037810 */
/* 0x000fc80007ffe0ff */
/*0750*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x18c], PT ; /* 0x0000630003007a0c */
/* 0x000fe40003f06270 */
/*0760*/ IADD3 R4, P1, R4, 0x80, RZ ; /* 0x0000008004047810 */
/* 0x000fc80007f3e0ff */
/*0770*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x000fe20000ffe4ff */
/*0780*/ FFMA R8, R8, R17, R24 ; /* 0x0000001108087223 */
/* 0x010fc80000000018 */
/*0790*/ FFMA R8, R16, R9, R8 ; /* 0x0000000910087223 */
/* 0x000fc80000000008 */
/*07a0*/ FFMA R8, R19, R10, R8 ; /* 0x0000000a13087223 */
/* 0x000fc80000000008 */
/*07b0*/ FFMA R8, R18, R11, R8 ; /* 0x0000000b12087223 */
/* 0x000fc80000000008 */
/*07c0*/ FFMA R8, R12, R21, R8 ; /* 0x000000150c087223 */
/* 0x004fc80000000008 */
/*07d0*/ FFMA R8, R20, R13, R8 ; /* 0x0000000d14087223 */
/* 0x008fc80000000008 */
/*07e0*/ FFMA R8, R23, R14, R8 ; /* 0x0000000e17087223 */
/* 0x020fc80000000008 */
/*07f0*/ FFMA R15, R22, R15, R8 ; /* 0x0000000f160f7223 */
/* 0x000fe40000000008 */
/*0800*/ IMAD.WIDE R8, R2, c[0x0][0x17c], R30 ; /* 0x00005f0002087a25 */
/* 0x000fe200078e021e */
/*0810*/ @!P0 BRA 0x130 ; /* 0xfffff91000008947 */
/* 0x000fea000383ffff */
/*0820*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x000fe2000c101904 */
/*0830*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0840*/ BRA 0x840; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected mmkernel
.globl mmkernel
.p2align 8
.type mmkernel,@function
mmkernel:
s_load_b32 s8, s[0:1], 0x2c
v_lshl_add_u32 v1, s14, 5, v0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB0_5
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x8
v_dual_mov_b32 v6, v1 :: v_dual_lshlrev_b32 v5, 2, v0
s_mov_b32 s9, 0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, s15, s3, v[0:1]
v_mov_b32_e32 v0, 0
s_lshl_b32 s3, s2, 5
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, s9, v2
s_mov_b32 s10, 0
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v4, v[3:4], off
v_mov_b32_e32 v3, v6
s_waitcnt vmcnt(0)
ds_store_b32 v5, v4
.LBB0_3:
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[3:4]
v_add_nc_u32_e32 v3, s2, v3
v_add_co_u32 v7, vcc_lo, s4, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
global_load_b32 v4, v[7:8], off
v_mov_b32_e32 v7, s10
s_add_i32 s10, s10, 4
s_cmpk_eq_i32 s10, 0x80
ds_load_b32 v7, v7
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v0, v4, v7
s_cbranch_scc0 .LBB0_3
v_add_nc_u32_e32 v6, s3, v6
s_add_i32 s9, s9, 32
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s9, s8
s_cbranch_scc1 .LBB0_2
s_branch .LBB0_6
.LBB0_5:
v_mov_b32_e32 v0, 0
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_clause 0x1
s_load_b32 s2, s[0:1], 0x18
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[1:2], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel mmkernel
.amdhsa_group_segment_fixed_size 128
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size mmkernel, .Lfunc_end0-mmkernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 128
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: mmkernel
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: mmkernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_001ba659_00000000-6_k2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z8mmkernelPfS_S_iiiiiiPfS_S_iiiiii
.type _Z37__device_stub__Z8mmkernelPfS_S_iiiiiiPfS_S_iiiiii, @function
_Z37__device_stub__Z8mmkernelPfS_S_iiiiiiPfS_S_iiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq mmkernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z8mmkernelPfS_S_iiiiiiPfS_S_iiiiii, .-_Z37__device_stub__Z8mmkernelPfS_S_iiiiiiPfS_S_iiiiii
.globl mmkernel
.type mmkernel, @function
mmkernel:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z37__device_stub__Z8mmkernelPfS_S_iiiiiiPfS_S_iiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size mmkernel, .-mmkernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "mmkernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq mmkernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "k2.hip"
.globl __device_stub__mmkernel # -- Begin function __device_stub__mmkernel
.p2align 4, 0x90
.type __device_stub__mmkernel,@function
__device_stub__mmkernel: # @__device_stub__mmkernel
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $mmkernel, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size __device_stub__mmkernel, .Lfunc_end0-__device_stub__mmkernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $mmkernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type mmkernel,@object # @mmkernel
.section .rodata,"a",@progbits
.globl mmkernel
.p2align 3, 0x0
mmkernel:
.quad __device_stub__mmkernel
.size mmkernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "mmkernel"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__mmkernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym mmkernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <stdio.h>
#include <cuda.h>
__global__ void K() {
printf("%d\n", threadIdx.x + threadIdx.y);
}
int main() {
dim3 block(3, 4);
K<<<1, block>>>();
cudaDeviceSynchronize();
return 0;
}
|
code for sm_80
Function : _Z1Kv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002200 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*0070*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fca0007f1e0ff */
/*0080*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe400000e06ff */
/*0090*/ IMAD.IADD R0, R0, 0x1, R3 ; /* 0x0000000100007824 */
/* 0x001fe400078e0203 */
/*00a0*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e260000000a00 */
/*00b0*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0003e40000100800 */
/*00c0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*00d0*/ MOV R11, 0x140 ; /* 0x00000140000b7802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R20, 0xc0 ; /* 0x000000c000147802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fc40000000f00 */
/*0100*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x002fe40000000f00 */
/*0110*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0120*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0130*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x001fea0003c00000 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
#include <cuda.h>
__global__ void K() {
printf("%d\n", threadIdx.x + threadIdx.y);
}
int main() {
dim3 block(3, 4);
K<<<1, block>>>();
cudaDeviceSynchronize();
return 0;
}
|
.file "tmpxft_0008261a_00000000-6_4x3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z19__device_stub__Z1Kvv
.type _Z19__device_stub__Z1Kvv, @function
_Z19__device_stub__Z1Kvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z1Kv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z19__device_stub__Z1Kvv, .-_Z19__device_stub__Z1Kvv
.globl _Z1Kv
.type _Z1Kv, @function
_Z1Kv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z19__device_stub__Z1Kvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z1Kv, .-_Z1Kv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $3, 8(%rsp)
movl $4, 12(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z19__device_stub__Z1Kvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z1Kv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z1Kv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
#include <cuda.h>
__global__ void K() {
printf("%d\n", threadIdx.x + threadIdx.y);
}
int main() {
dim3 block(3, 4);
K<<<1, block>>>();
cudaDeviceSynchronize();
return 0;
}
|
#include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void K() {
printf("%d\n", threadIdx.x + threadIdx.y);
}
int main() {
dim3 block(3, 4);
K<<<1, block>>>();
hipDeviceSynchronize();
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void K() {
printf("%d\n", threadIdx.x + threadIdx.y);
}
int main() {
dim3 block(3, 4);
K<<<1, block>>>();
hipDeviceSynchronize();
return 0;
}
|
.text
.file "4x3.hip"
.globl _Z16__device_stub__Kv # -- Begin function _Z16__device_stub__Kv
.p2align 4, 0x90
.type _Z16__device_stub__Kv,@function
_Z16__device_stub__Kv: # @_Z16__device_stub__Kv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z1Kv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z16__device_stub__Kv, .Lfunc_end0-_Z16__device_stub__Kv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $17179869187, %rdx # imm = 0x400000003
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z1Kv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z1Kv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z1Kv,@object # @_Z1Kv
.section .rodata,"a",@progbits
.globl _Z1Kv
.p2align 3, 0x0
_Z1Kv:
.quad _Z16__device_stub__Kv
.size _Z1Kv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z1Kv"
.size .L__unnamed_1, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z16__device_stub__Kv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z1Kv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0008261a_00000000-6_4x3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z19__device_stub__Z1Kvv
.type _Z19__device_stub__Z1Kvv, @function
_Z19__device_stub__Z1Kvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z1Kv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z19__device_stub__Z1Kvv, .-_Z19__device_stub__Z1Kvv
.globl _Z1Kv
.type _Z1Kv, @function
_Z1Kv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z19__device_stub__Z1Kvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z1Kv, .-_Z1Kv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $3, 8(%rsp)
movl $4, 12(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z19__device_stub__Z1Kvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z1Kv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z1Kv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "4x3.hip"
.globl _Z16__device_stub__Kv # -- Begin function _Z16__device_stub__Kv
.p2align 4, 0x90
.type _Z16__device_stub__Kv,@function
_Z16__device_stub__Kv: # @_Z16__device_stub__Kv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z1Kv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z16__device_stub__Kv, .Lfunc_end0-_Z16__device_stub__Kv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $17179869187, %rdx # imm = 0x400000003
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z1Kv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z1Kv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z1Kv,@object # @_Z1Kv
.section .rodata,"a",@progbits
.globl _Z1Kv
.p2align 3, 0x0
_Z1Kv:
.quad _Z16__device_stub__Kv
.size _Z1Kv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z1Kv"
.size .L__unnamed_1, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z16__device_stub__Kv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z1Kv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <iostream>
#include <math.h>
#include <cstdlib>
#include <ctime>
const int blockSizex = 32;
const int blockSizey = 8;
const int TILE_DIM = blockSizex;
#define imin(a, b) (a<b?a:b)
// Naive matrix transpose
__global__
void gpu_matrix_trans_naive(double *mat_in, double *mat_out) {
int idx = blockIdx.x * TILE_DIM + threadIdx.x;
int idy = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += blockSizey) {
mat_out[idy + j + idx*width] = mat_in[(idy+j)*width + idx];
}
}
// Transpose via shared memory
__global__
void gpu_matrix_trans_sharedmem(double *mat_in, double *mat_out) {
// shared memory (48KB/N per block), N is the number of blocks on the same multiprocessor
__shared__ double tile[TILE_DIM*TILE_DIM];
int idx = blockIdx.x * TILE_DIM + threadIdx.x;
int idy = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += blockSizey) {
tile[threadIdx.x + (threadIdx.y+j)*TILE_DIM] = mat_in[(idy+j)*width + idx];
}
__syncthreads();
for (int j = 0; j < TILE_DIM; j += blockSizey) {
mat_out[(idy+j)*width + idx] = tile[threadIdx.x*TILE_DIM + threadIdx.y + j];
}
}
// Coalesced Transpose via shared memory
__global__
void gpu_matrix_trans_coales_sharedmem(double *mat_in, double *mat_out) {
// shared memory (48KB/N per block), N is the number of blocks on the same multiprocessor
__shared__ double tile[TILE_DIM*TILE_DIM];
int idx = blockIdx.x * TILE_DIM + threadIdx.x;
int idy = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += blockSizey) {
tile[threadIdx.x*TILE_DIM + threadIdx.y + j] = mat_in[(idy+j)*width + idx];
}
__syncthreads();
idx = blockIdx.y * TILE_DIM + threadIdx.x;
idy = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += blockSizey) {
mat_out[(idy+j)*width + idx] = tile[threadIdx.x + (threadIdx.y+j)*TILE_DIM];
}
}
// Coalesced Transpose via shared memory without bank conflict
__global__
void gpu_matrix_trans_coales_sharedmem_NoBankConfl(double *mat_in, double *mat_out) {
// shared memory (48KB/N per block), N is the number of blocks on the same multiprocessor
__shared__ double tile[TILE_DIM][TILE_DIM+1];
int idx = blockIdx.x * TILE_DIM + threadIdx.x;
int idy = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += blockSizey) {
tile[threadIdx.y+j][threadIdx.x] = mat_in[(idy+j)*width + idx];
}
__syncthreads();
idx = blockIdx.y * TILE_DIM + threadIdx.x;
idy = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += blockSizey) {
mat_out[(idy+j)*width + idx] = tile[threadIdx.x][threadIdx.y+j];
}
}
int main(void) {
int cols = 1<<10, rows = 1<<10;
int grid_cols = imin(512, (cols + TILE_DIM - 1)/TILE_DIM);
int grid_rows = imin(512, (rows + TILE_DIM - 1)/TILE_DIM);
dim3 dimBlock(blockSizex, blockSizey, 1);
dim3 dimGrid(grid_cols, grid_rows, 1);
// Allocate memory in host RAM
double *h_mat_in = new double[cols*rows];
double *h_mat_out = new double[cols*rows];
// Initialize h_mat_in
std::srand(1103);
for (int i = 0; i < rows; i++)
for (int j = 0; j < cols; j++)
// h_mat_in[i*cols+j] = double (((generator() % (1000 - 0 + 1)) + 0)/1000);
h_mat_in[i*cols+j] = double(std::rand())/double(RAND_MAX);
// capture the GPU start time
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
// Allocate memory on device
double *d_mat_in, *d_mat_out;
cudaMalloc(&d_mat_in, cols*rows*sizeof(double));
cudaMalloc(&d_mat_out, cols*rows*sizeof(double));
// Copy matrix in from host to device
cudaMemcpy(d_mat_in, h_mat_in, cols*rows*sizeof(double), cudaMemcpyHostToDevice);
// Run kernel
gpu_matrix_trans_naive<<<dimGrid, dimBlock>>>(d_mat_in, d_mat_out);
gpu_matrix_trans_sharedmem<<<dimGrid, dimBlock>>>(d_mat_in, d_mat_out);
gpu_matrix_trans_coales_sharedmem<<<dimGrid, dimBlock>>>(d_mat_in, d_mat_out);
gpu_matrix_trans_coales_sharedmem_NoBankConfl<<<dimGrid, dimBlock>>>(d_mat_in, d_mat_out);
// Copy result from device to host
cudaMemcpy(h_mat_out, d_mat_out, cols*rows*sizeof(double), cudaMemcpyDeviceToHost);
cudaThreadSynchronize();
// get GPU stop time
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
// Check results
int check_flag = 1;
for (int i = 0; i < rows; i++)
for (int j = 0; j < cols; j++)
if (h_mat_out[j*rows + i] != h_mat_in[i*cols + j])
check_flag = 0;
if (!check_flag)
std::cout << "GPU matrix transpose not success!!!" << std::endl;
else {
std::cout << "GPU matrix transpose success!!!" << std::endl;
std::cout << "GPU matrix multiplication time: " << elapsedTime << " ms." << std::endl;
}
// Free memory
cudaFree(d_mat_in);
cudaFree(d_mat_out);
delete [] h_mat_in;
delete [] h_mat_out;
return 0;
}
|
code for sm_80
Function : _Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ MOV R8, c[0x0][0xc] ; /* 0x0000030000087a02 */
/* 0x000fe20000000f00 */
/*0030*/ HFMA2.MMA R4, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff047435 */
/* 0x000fe200000001ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0060*/ SHF.L.U32 R6, R8, 0x5, RZ ; /* 0x0000000508067819 */
/* 0x000fc600000006ff */
/*0070*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002600 */
/*0080*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e620000002200 */
/*0090*/ LEA R9, R3, R0, 0x5 ; /* 0x0000000003097211 */
/* 0x001fe400078e28ff */
/*00a0*/ LEA R2, R5, R7, 0x5 ; /* 0x0000000705027211 */
/* 0x002fca00078e28ff */
/*00b0*/ IMAD R9, R2, R6, R9 ; /* 0x0000000602097224 */
/* 0x000fe200078e0209 */
/*00c0*/ SHF.L.U32 R2, R8, 0x8, RZ ; /* 0x0000000808027819 */
/* 0x000fc600000006ff */
/*00d0*/ IMAD.WIDE R16, R9, R4, c[0x0][0x160] ; /* 0x0000580009107625 */
/* 0x000fcc00078e0204 */
/*00e0*/ IMAD.WIDE R18, R2.reuse, 0x8, R16 ; /* 0x0000000802127825 */
/* 0x040fe400078e0210 */
/*00f0*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ea8000c1e1b00 */
/*0100*/ IMAD.WIDE R8, R2.reuse, 0x8, R18 ; /* 0x0000000802087825 */
/* 0x040fe400078e0212 */
/*0110*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ee8000c1e1b00 */
/*0120*/ IMAD.WIDE R22, R2, 0x8, R8 ; /* 0x0000000802167825 */
/* 0x000fe200078e0208 */
/*0130*/ LDG.E.64 R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000f2a000c1e1b00 */
/*0140*/ LDG.E.64 R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000f62000c1e1b00 */
/*0150*/ IMAD R25, R7, 0x21, R0 ; /* 0x0000002107197824 */
/* 0x000fc400078e0200 */
/*0160*/ IMAD R24, R0, 0x21, R7 ; /* 0x0000002100187824 */
/* 0x000fe200078e0207 */
/*0170*/ LEA R5, R5, R0, 0x5 ; /* 0x0000000005057211 */
/* 0x000fe400078e28ff */
/*0180*/ LEA R3, R3, R7, 0x5 ; /* 0x0000000703037211 */
/* 0x000fca00078e28ff */
/*0190*/ IMAD R5, R6, R3, R5 ; /* 0x0000000306057224 */
/* 0x000fc800078e0205 */
/*01a0*/ IMAD.WIDE R4, R5, R4, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fcc00078e0204 */
/*01b0*/ IMAD.WIDE R6, R2.reuse, 0x8, R4 ; /* 0x0000000802067825 */
/* 0x040fe200078e0204 */
/*01c0*/ STS.64 [R25.X8], R16 ; /* 0x0000001019007388 */
/* 0x0041e80000008a00 */
/*01d0*/ STS.64 [R25.X8+0x840], R18 ; /* 0x0008401219007388 */
/* 0x008fe80000008a00 */
/*01e0*/ STS.64 [R25.X8+0x1080], R20 ; /* 0x0010801419007388 */
/* 0x010fe80000008a00 */
/*01f0*/ STS.64 [R25.X8+0x18c0], R22 ; /* 0x0018c01619007388 */
/* 0x020fe80000008a00 */
/*0200*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0210*/ LDS.64 R14, [R24.X8] ; /* 0x00000000180e7984 */
/* 0x000e680000008a00 */
/*0220*/ LDS.64 R12, [R24.X8+0x40] ; /* 0x00004000180c7984 */
/* 0x000ea80000008a00 */
/*0230*/ LDS.64 R10, [R24.X8+0x80] ; /* 0x00008000180a7984 */
/* 0x000ee80000008a00 */
/*0240*/ LDS.64 R8, [R24.X8+0xc0] ; /* 0x0000c00018087984 */
/* 0x000f220000008a00 */
/*0250*/ IMAD.WIDE R16, R2, 0x8, R6 ; /* 0x0000000802107825 */
/* 0x001fcc00078e0206 */
/*0260*/ IMAD.WIDE R2, R2, 0x8, R16 ; /* 0x0000000802027825 */
/* 0x000fe200078e0210 */
/*0270*/ STG.E.64 [R4.64], R14 ; /* 0x0000000e04007986 */
/* 0x002fe8000c101b04 */
/*0280*/ STG.E.64 [R6.64], R12 ; /* 0x0000000c06007986 */
/* 0x004fe8000c101b04 */
/*0290*/ STG.E.64 [R16.64], R10 ; /* 0x0000000a10007986 */
/* 0x008fe8000c101b04 */
/*02a0*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x010fe2000c101b04 */
/*02b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02c0*/ BRA 0x2c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z33gpu_matrix_trans_coales_sharedmemPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ MOV R8, c[0x0][0xc] ; /* 0x0000030000087a02 */
/* 0x000fe20000000f00 */
/*0030*/ HFMA2.MMA R4, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff047435 */
/* 0x000fe200000001ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0060*/ SHF.L.U32 R6, R8, 0x5, RZ ; /* 0x0000000508067819 */
/* 0x000fc600000006ff */
/*0070*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002600 */
/*0080*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e620000002200 */
/*0090*/ LEA R9, R3, R0, 0x5 ; /* 0x0000000003097211 */
/* 0x001fe400078e28ff */
/*00a0*/ LEA R2, R5, R7, 0x5 ; /* 0x0000000705027211 */
/* 0x002fca00078e28ff */
/*00b0*/ IMAD R9, R2, R6, R9 ; /* 0x0000000602097224 */
/* 0x000fe200078e0209 */
/*00c0*/ SHF.L.U32 R2, R8, 0x8, RZ ; /* 0x0000000808027819 */
/* 0x000fc600000006ff */
/*00d0*/ IMAD.WIDE R16, R9, R4, c[0x0][0x160] ; /* 0x0000580009107625 */
/* 0x000fcc00078e0204 */
/*00e0*/ IMAD.WIDE R18, R2.reuse, 0x8, R16 ; /* 0x0000000802127825 */
/* 0x040fe400078e0210 */
/*00f0*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ea8000c1e1b00 */
/*0100*/ IMAD.WIDE R8, R2.reuse, 0x8, R18 ; /* 0x0000000802087825 */
/* 0x040fe400078e0212 */
/*0110*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ee8000c1e1b00 */
/*0120*/ IMAD.WIDE R22, R2, 0x8, R8 ; /* 0x0000000802167825 */
/* 0x000fe200078e0208 */
/*0130*/ LDG.E.64 R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000f2a000c1e1b00 */
/*0140*/ LDG.E.64 R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000f62000c1e1b00 */
/*0150*/ LEA R25, R0, R7, 0x5 ; /* 0x0000000700197211 */
/* 0x000fc400078e28ff */
/*0160*/ LEA R24, R7, R0.reuse, 0x5 ; /* 0x0000000007187211 */
/* 0x080fe400078e28ff */
/*0170*/ LEA R5, R5, R0, 0x5 ; /* 0x0000000005057211 */
/* 0x000fe400078e28ff */
/*0180*/ LEA R3, R3, R7, 0x5 ; /* 0x0000000703037211 */
/* 0x000fca00078e28ff */
/*0190*/ IMAD R5, R6, R3, R5 ; /* 0x0000000306057224 */
/* 0x000fc800078e0205 */
/*01a0*/ IMAD.WIDE R4, R5, R4, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fcc00078e0204 */
/*01b0*/ IMAD.WIDE R6, R2.reuse, 0x8, R4 ; /* 0x0000000802067825 */
/* 0x040fe200078e0204 */
/*01c0*/ STS.64 [R25.X8], R16 ; /* 0x0000001019007388 */
/* 0x0041e80000008a00 */
/*01d0*/ STS.64 [R25.X8+0x40], R18 ; /* 0x0000401219007388 */
/* 0x008fe80000008a00 */
/*01e0*/ STS.64 [R25.X8+0x80], R20 ; /* 0x0000801419007388 */
/* 0x010fe80000008a00 */
/*01f0*/ STS.64 [R25.X8+0xc0], R22 ; /* 0x0000c01619007388 */
/* 0x020fe80000008a00 */
/*0200*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0210*/ LDS.64 R14, [R24.X8] ; /* 0x00000000180e7984 */
/* 0x000e680000008a00 */
/*0220*/ LDS.64 R12, [R24.X8+0x800] ; /* 0x00080000180c7984 */
/* 0x000ea80000008a00 */
/*0230*/ LDS.64 R10, [R24.X8+0x1000] ; /* 0x00100000180a7984 */
/* 0x000ee80000008a00 */
/*0240*/ LDS.64 R8, [R24.X8+0x1800] ; /* 0x0018000018087984 */
/* 0x000f220000008a00 */
/*0250*/ IMAD.WIDE R16, R2, 0x8, R6 ; /* 0x0000000802107825 */
/* 0x001fcc00078e0206 */
/*0260*/ IMAD.WIDE R2, R2, 0x8, R16 ; /* 0x0000000802027825 */
/* 0x000fe200078e0210 */
/*0270*/ STG.E.64 [R4.64], R14 ; /* 0x0000000e04007986 */
/* 0x002fe8000c101b04 */
/*0280*/ STG.E.64 [R6.64], R12 ; /* 0x0000000c06007986 */
/* 0x004fe8000c101b04 */
/*0290*/ STG.E.64 [R16.64], R10 ; /* 0x0000000a10007986 */
/* 0x008fe8000c101b04 */
/*02a0*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x010fe2000c101b04 */
/*02b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02c0*/ BRA 0x2c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z26gpu_matrix_trans_sharedmemPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ MOV R6, c[0x0][0xc] ; /* 0x0000030000067a02 */
/* 0x000fe20000000f00 */
/*0030*/ HFMA2.MMA R2, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff027435 */
/* 0x000fe200000001ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R22, SR_TID.X ; /* 0x0000000000167919 */
/* 0x000e220000002100 */
/*0060*/ SHF.L.U32 R4, R6, 0x5, RZ ; /* 0x0000000506047819 */
/* 0x000fc600000006ff */
/*0070*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0080*/ S2R R13, SR_TID.Y ; /* 0x00000000000d7919 */
/* 0x000e620000002200 */
/*0090*/ LEA R3, R3, R22, 0x5 ; /* 0x0000001603037211 */
/* 0x001fe400078e28ff */
/*00a0*/ LEA R0, R0, R13, 0x5 ; /* 0x0000000d00007211 */
/* 0x002fca00078e28ff */
/*00b0*/ IMAD R3, R0, R4, R3 ; /* 0x0000000400037224 */
/* 0x000fe200078e0203 */
/*00c0*/ SHF.L.U32 R0, R6, 0x8, RZ ; /* 0x0000000806007819 */
/* 0x000fc600000006ff */
/*00d0*/ IMAD.WIDE R4, R3, R2, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fcc00078e0202 */
/*00e0*/ IMAD.WIDE R6, R0.reuse, 0x8, R4 ; /* 0x0000000800067825 */
/* 0x040fe400078e0204 */
/*00f0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*0100*/ IMAD.WIDE R8, R0.reuse, 0x8, R6 ; /* 0x0000000800087825 */
/* 0x040fe400078e0206 */
/*0110*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee8000c1e1b00 */
/*0120*/ IMAD.WIDE R10, R0, 0x8, R8 ; /* 0x00000008000a7825 */
/* 0x000fc400078e0208 */
/*0130*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f28000c1e1b00 */
/*0140*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f62000c1e1b00 */
/*0150*/ LEA R23, R13, R22, 0x5 ; /* 0x000000160d177211 */
/* 0x000fe400078e28ff */
/*0160*/ LEA R22, R22, R13, 0x5 ; /* 0x0000000d16167211 */
/* 0x000fe200078e28ff */
/*0170*/ IMAD.WIDE R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fcc00078e0202 */
/*0180*/ IMAD.WIDE R16, R0.reuse, 0x8, R2 ; /* 0x0000000800107825 */
/* 0x040fe200078e0202 */
/*0190*/ STS.64 [R23.X8], R4 ; /* 0x0000000417007388 */
/* 0x0041e80000008a00 */
/*01a0*/ STS.64 [R23.X8+0x800], R6 ; /* 0x0008000617007388 */
/* 0x0083e80000008a00 */
/*01b0*/ STS.64 [R23.X8+0x1000], R8 ; /* 0x0010000817007388 */
/* 0x010fe80000008a00 */
/*01c0*/ STS.64 [R23.X8+0x1800], R10 ; /* 0x0018000a17007388 */
/* 0x020fe80000008a00 */
/*01d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01e0*/ LDS.64 R12, [R22.X8] ; /* 0x00000000160c7984 */
/* 0x000ea80000008a00 */
/*01f0*/ LDS.64 R14, [R22.X8+0x40] ; /* 0x00004000160e7984 */
/* 0x000ee80000008a00 */
/*0200*/ LDS.64 R18, [R22.X8+0x80] ; /* 0x0000800016127984 */
/* 0x000f280000008a00 */
/*0210*/ LDS.64 R20, [R22.X8+0xc0] ; /* 0x0000c00016147984 */
/* 0x000f620000008a00 */
/*0220*/ IMAD.WIDE R4, R0, 0x8, R16 ; /* 0x0000000800047825 */
/* 0x001fcc00078e0210 */
/*0230*/ IMAD.WIDE R6, R0, 0x8, R4 ; /* 0x0000000800067825 */
/* 0x002fe200078e0204 */
/*0240*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x004fe8000c101b04 */
/*0250*/ STG.E.64 [R16.64], R14 ; /* 0x0000000e10007986 */
/* 0x008fe8000c101b04 */
/*0260*/ STG.E.64 [R4.64], R18 ; /* 0x0000001204007986 */
/* 0x010fe8000c101b04 */
/*0270*/ STG.E.64 [R6.64], R20 ; /* 0x0000001406007986 */
/* 0x020fe2000c101b04 */
/*0280*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0290*/ BRA 0x290; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z22gpu_matrix_trans_naivePdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R17, c[0x0][0xc] ; /* 0x0000030000117a02 */
/* 0x000fe20000000f00 */
/*0030*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ SHF.L.U32 R6, R17, 0x5, RZ ; /* 0x0000000511067819 */
/* 0x000fc600000006ff */
/*0070*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e680000002600 */
/*0080*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0090*/ LEA R0, R0, R3, 0x5 ; /* 0x0000000300007211 */
/* 0x001fe400078e28ff */
/*00a0*/ LEA R7, R7, R2, 0x5 ; /* 0x0000000207077211 */
/* 0x002fca00078e28ff */
/*00b0*/ IMAD R2, R7, R6, R0 ; /* 0x0000000607027224 */
/* 0x000fc800078e0200 */
/*00c0*/ IMAD.WIDE R2, R2, R9, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0209 */
/*00d0*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1b00 */
/*00e0*/ SHF.L.U32 R17, R17, 0x8, RZ ; /* 0x0000000811117819 */
/* 0x000fe200000006ff */
/*00f0*/ IMAD R6, R0, R6, R7 ; /* 0x0000000600067224 */
/* 0x000fc800078e0207 */
/*0100*/ IMAD.WIDE R6, R6, R9, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0209 */
/*0110*/ IMAD.WIDE R8, R17.reuse, 0x8, R2 ; /* 0x0000000811087825 */
/* 0x040fe200078e0202 */
/*0120*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x004fe8000c101b04 */
/*0130*/ LDG.E.64 R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x000ea2000c1e1b00 */
/*0140*/ IMAD.WIDE R12, R17, 0x8, R8 ; /* 0x00000008110c7825 */
/* 0x000fc600078e0208 */
/*0150*/ STG.E.64 [R6.64+0x40], R10 ; /* 0x0000400a06007986 */
/* 0x004fe8000c101b04 */
/*0160*/ LDG.E.64 R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea2000c1e1b00 */
/*0170*/ IMAD.WIDE R16, R17, 0x8, R12 ; /* 0x0000000811107825 */
/* 0x000fc600078e020c */
/*0180*/ STG.E.64 [R6.64+0x80], R14 ; /* 0x0000800e06007986 */
/* 0x004fe8000c101b04 */
/*0190*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ea8000c1e1b00 */
/*01a0*/ STG.E.64 [R6.64+0xc0], R16 ; /* 0x0000c01006007986 */
/* 0x004fe2000c101b04 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <iostream>
#include <math.h>
#include <cstdlib>
#include <ctime>
const int blockSizex = 32;
const int blockSizey = 8;
const int TILE_DIM = blockSizex;
#define imin(a, b) (a<b?a:b)
// Naive matrix transpose
__global__
void gpu_matrix_trans_naive(double *mat_in, double *mat_out) {
int idx = blockIdx.x * TILE_DIM + threadIdx.x;
int idy = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += blockSizey) {
mat_out[idy + j + idx*width] = mat_in[(idy+j)*width + idx];
}
}
// Transpose via shared memory
__global__
void gpu_matrix_trans_sharedmem(double *mat_in, double *mat_out) {
// shared memory (48KB/N per block), N is the number of blocks on the same multiprocessor
__shared__ double tile[TILE_DIM*TILE_DIM];
int idx = blockIdx.x * TILE_DIM + threadIdx.x;
int idy = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += blockSizey) {
tile[threadIdx.x + (threadIdx.y+j)*TILE_DIM] = mat_in[(idy+j)*width + idx];
}
__syncthreads();
for (int j = 0; j < TILE_DIM; j += blockSizey) {
mat_out[(idy+j)*width + idx] = tile[threadIdx.x*TILE_DIM + threadIdx.y + j];
}
}
// Coalesced Transpose via shared memory
__global__
void gpu_matrix_trans_coales_sharedmem(double *mat_in, double *mat_out) {
// shared memory (48KB/N per block), N is the number of blocks on the same multiprocessor
__shared__ double tile[TILE_DIM*TILE_DIM];
int idx = blockIdx.x * TILE_DIM + threadIdx.x;
int idy = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += blockSizey) {
tile[threadIdx.x*TILE_DIM + threadIdx.y + j] = mat_in[(idy+j)*width + idx];
}
__syncthreads();
idx = blockIdx.y * TILE_DIM + threadIdx.x;
idy = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += blockSizey) {
mat_out[(idy+j)*width + idx] = tile[threadIdx.x + (threadIdx.y+j)*TILE_DIM];
}
}
// Coalesced Transpose via shared memory without bank conflict
__global__
void gpu_matrix_trans_coales_sharedmem_NoBankConfl(double *mat_in, double *mat_out) {
// shared memory (48KB/N per block), N is the number of blocks on the same multiprocessor
__shared__ double tile[TILE_DIM][TILE_DIM+1];
int idx = blockIdx.x * TILE_DIM + threadIdx.x;
int idy = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += blockSizey) {
tile[threadIdx.y+j][threadIdx.x] = mat_in[(idy+j)*width + idx];
}
__syncthreads();
idx = blockIdx.y * TILE_DIM + threadIdx.x;
idy = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += blockSizey) {
mat_out[(idy+j)*width + idx] = tile[threadIdx.x][threadIdx.y+j];
}
}
int main(void) {
int cols = 1<<10, rows = 1<<10;
int grid_cols = imin(512, (cols + TILE_DIM - 1)/TILE_DIM);
int grid_rows = imin(512, (rows + TILE_DIM - 1)/TILE_DIM);
dim3 dimBlock(blockSizex, blockSizey, 1);
dim3 dimGrid(grid_cols, grid_rows, 1);
// Allocate memory in host RAM
double *h_mat_in = new double[cols*rows];
double *h_mat_out = new double[cols*rows];
// Initialize h_mat_in
std::srand(1103);
for (int i = 0; i < rows; i++)
for (int j = 0; j < cols; j++)
// h_mat_in[i*cols+j] = double (((generator() % (1000 - 0 + 1)) + 0)/1000);
h_mat_in[i*cols+j] = double(std::rand())/double(RAND_MAX);
// capture the GPU start time
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
// Allocate memory on device
double *d_mat_in, *d_mat_out;
cudaMalloc(&d_mat_in, cols*rows*sizeof(double));
cudaMalloc(&d_mat_out, cols*rows*sizeof(double));
// Copy matrix in from host to device
cudaMemcpy(d_mat_in, h_mat_in, cols*rows*sizeof(double), cudaMemcpyHostToDevice);
// Run kernel
gpu_matrix_trans_naive<<<dimGrid, dimBlock>>>(d_mat_in, d_mat_out);
gpu_matrix_trans_sharedmem<<<dimGrid, dimBlock>>>(d_mat_in, d_mat_out);
gpu_matrix_trans_coales_sharedmem<<<dimGrid, dimBlock>>>(d_mat_in, d_mat_out);
gpu_matrix_trans_coales_sharedmem_NoBankConfl<<<dimGrid, dimBlock>>>(d_mat_in, d_mat_out);
// Copy result from device to host
cudaMemcpy(h_mat_out, d_mat_out, cols*rows*sizeof(double), cudaMemcpyDeviceToHost);
cudaThreadSynchronize();
// get GPU stop time
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
// Check results
int check_flag = 1;
for (int i = 0; i < rows; i++)
for (int j = 0; j < cols; j++)
if (h_mat_out[j*rows + i] != h_mat_in[i*cols + j])
check_flag = 0;
if (!check_flag)
std::cout << "GPU matrix transpose not success!!!" << std::endl;
else {
std::cout << "GPU matrix transpose success!!!" << std::endl;
std::cout << "GPU matrix multiplication time: " << elapsedTime << " ms." << std::endl;
}
// Free memory
cudaFree(d_mat_in);
cudaFree(d_mat_out);
delete [] h_mat_in;
delete [] h_mat_out;
return 0;
}
|
.file "tmpxft_0019eea9_00000000-6_gpucpptranspose.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z22gpu_matrix_trans_naivePdS_PdS_
.type _Z44__device_stub__Z22gpu_matrix_trans_naivePdS_PdS_, @function
_Z44__device_stub__Z22gpu_matrix_trans_naivePdS_PdS_:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z22gpu_matrix_trans_naivePdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z44__device_stub__Z22gpu_matrix_trans_naivePdS_PdS_, .-_Z44__device_stub__Z22gpu_matrix_trans_naivePdS_PdS_
.globl _Z22gpu_matrix_trans_naivePdS_
.type _Z22gpu_matrix_trans_naivePdS_, @function
_Z22gpu_matrix_trans_naivePdS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z22gpu_matrix_trans_naivePdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z22gpu_matrix_trans_naivePdS_, .-_Z22gpu_matrix_trans_naivePdS_
.globl _Z48__device_stub__Z26gpu_matrix_trans_sharedmemPdS_PdS_
.type _Z48__device_stub__Z26gpu_matrix_trans_sharedmemPdS_PdS_, @function
_Z48__device_stub__Z26gpu_matrix_trans_sharedmemPdS_PdS_:
.LFB3696:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z26gpu_matrix_trans_sharedmemPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z48__device_stub__Z26gpu_matrix_trans_sharedmemPdS_PdS_, .-_Z48__device_stub__Z26gpu_matrix_trans_sharedmemPdS_PdS_
.globl _Z26gpu_matrix_trans_sharedmemPdS_
.type _Z26gpu_matrix_trans_sharedmemPdS_, @function
_Z26gpu_matrix_trans_sharedmemPdS_:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z26gpu_matrix_trans_sharedmemPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z26gpu_matrix_trans_sharedmemPdS_, .-_Z26gpu_matrix_trans_sharedmemPdS_
.globl _Z55__device_stub__Z33gpu_matrix_trans_coales_sharedmemPdS_PdS_
.type _Z55__device_stub__Z33gpu_matrix_trans_coales_sharedmemPdS_PdS_, @function
_Z55__device_stub__Z33gpu_matrix_trans_coales_sharedmemPdS_PdS_:
.LFB3698:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z33gpu_matrix_trans_coales_sharedmemPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z55__device_stub__Z33gpu_matrix_trans_coales_sharedmemPdS_PdS_, .-_Z55__device_stub__Z33gpu_matrix_trans_coales_sharedmemPdS_PdS_
.globl _Z33gpu_matrix_trans_coales_sharedmemPdS_
.type _Z33gpu_matrix_trans_coales_sharedmemPdS_, @function
_Z33gpu_matrix_trans_coales_sharedmemPdS_:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z55__device_stub__Z33gpu_matrix_trans_coales_sharedmemPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z33gpu_matrix_trans_coales_sharedmemPdS_, .-_Z33gpu_matrix_trans_coales_sharedmemPdS_
.globl _Z67__device_stub__Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_PdS_
.type _Z67__device_stub__Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_PdS_, @function
_Z67__device_stub__Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_PdS_:
.LFB3700:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3700:
.size _Z67__device_stub__Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_PdS_, .-_Z67__device_stub__Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_PdS_
.globl _Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
.type _Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_, @function
_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_:
.LFB3701:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z67__device_stub__Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_, .-_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "GPU matrix transpose not success!!!"
.align 8
.LC2:
.string "GPU matrix transpose success!!!"
.align 8
.LC3:
.string "GPU matrix multiplication time: "
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string " ms."
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $32, 48(%rsp)
movl $8, 52(%rsp)
movl $1, 56(%rsp)
movl $32, 60(%rsp)
movl $32, 64(%rsp)
movl $1, 68(%rsp)
movl $8388608, %edi
call _Znam@PLT
movq %rax, %r12
movl $8388608, %edi
call _Znam@PLT
movq %rax, %r13
movl $1103, %edi
call srand@PLT
movq %r12, %rbp
leaq 8192(%r12), %r14
leaq 8396800(%r12), %r15
.L36:
leaq -8192(%r14), %rbx
.L37:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC0(%rip), %xmm0
movsd %xmm0, (%rbx)
addq $8, %rbx
cmpq %r14, %rbx
jne .L37
addq $8192, %r14
cmpq %r15, %r14
jne .L36
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
leaq 32(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8388608, %edx
movq %r12, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L55
.L39:
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L56
.L40:
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L57
.L41:
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L58
.L42:
movl $2, %ecx
movl $8388608, %edx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
call cudaThreadSynchronize@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq 8388608(%r13), %rcx
movl $0, %r8d
movl $1, %esi
movl $0, %edi
jmp .L43
.L55:
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z44__device_stub__Z22gpu_matrix_trans_naivePdS_PdS_
jmp .L39
.L56:
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z48__device_stub__Z26gpu_matrix_trans_sharedmemPdS_PdS_
jmp .L40
.L57:
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z55__device_stub__Z33gpu_matrix_trans_coales_sharedmemPdS_PdS_
jmp .L41
.L58:
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z67__device_stub__Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_PdS_
jmp .L42
.L51:
movl %edi, %esi
.L44:
addq $8192, %rax
addq $8, %rdx
cmpq %rcx, %rax
je .L59
.L46:
movsd (%rax), %xmm0
ucomisd (%rdx), %xmm0
jp .L51
je .L44
jmp .L51
.L59:
addl $1, %r8d
addq $8, %rcx
addq $8192, %rbp
cmpl $1024, %r8d
je .L47
.L43:
leaq -8388608(%rcx), %rax
movq %rbp, %rdx
jmp .L46
.L47:
testl %esi, %esi
jne .L48
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L49:
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq %r13, %rdi
call _ZdaPv@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L60
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L49
.L60:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC5:
.string "_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_"
.align 8
.LC6:
.string "_Z33gpu_matrix_trans_coales_sharedmemPdS_"
.align 8
.LC7:
.string "_Z26gpu_matrix_trans_sharedmemPdS_"
.align 8
.LC8:
.string "_Z22gpu_matrix_trans_naivePdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3703:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z33gpu_matrix_trans_coales_sharedmemPdS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z26gpu_matrix_trans_sharedmemPdS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z22gpu_matrix_trans_naivePdS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3703:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -4194304
.long 1105199103
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <iostream>
#include <math.h>
#include <cstdlib>
#include <ctime>
const int blockSizex = 32;
const int blockSizey = 8;
const int TILE_DIM = blockSizex;
#define imin(a, b) (a<b?a:b)
// Naive matrix transpose
__global__
void gpu_matrix_trans_naive(double *mat_in, double *mat_out) {
int idx = blockIdx.x * TILE_DIM + threadIdx.x;
int idy = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += blockSizey) {
mat_out[idy + j + idx*width] = mat_in[(idy+j)*width + idx];
}
}
// Transpose via shared memory
__global__
void gpu_matrix_trans_sharedmem(double *mat_in, double *mat_out) {
// shared memory (48KB/N per block), N is the number of blocks on the same multiprocessor
__shared__ double tile[TILE_DIM*TILE_DIM];
int idx = blockIdx.x * TILE_DIM + threadIdx.x;
int idy = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += blockSizey) {
tile[threadIdx.x + (threadIdx.y+j)*TILE_DIM] = mat_in[(idy+j)*width + idx];
}
__syncthreads();
for (int j = 0; j < TILE_DIM; j += blockSizey) {
mat_out[(idy+j)*width + idx] = tile[threadIdx.x*TILE_DIM + threadIdx.y + j];
}
}
// Coalesced Transpose via shared memory
__global__
void gpu_matrix_trans_coales_sharedmem(double *mat_in, double *mat_out) {
// shared memory (48KB/N per block), N is the number of blocks on the same multiprocessor
__shared__ double tile[TILE_DIM*TILE_DIM];
int idx = blockIdx.x * TILE_DIM + threadIdx.x;
int idy = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += blockSizey) {
tile[threadIdx.x*TILE_DIM + threadIdx.y + j] = mat_in[(idy+j)*width + idx];
}
__syncthreads();
idx = blockIdx.y * TILE_DIM + threadIdx.x;
idy = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += blockSizey) {
mat_out[(idy+j)*width + idx] = tile[threadIdx.x + (threadIdx.y+j)*TILE_DIM];
}
}
// Coalesced Transpose via shared memory without bank conflict
__global__
void gpu_matrix_trans_coales_sharedmem_NoBankConfl(double *mat_in, double *mat_out) {
// shared memory (48KB/N per block), N is the number of blocks on the same multiprocessor
__shared__ double tile[TILE_DIM][TILE_DIM+1];
int idx = blockIdx.x * TILE_DIM + threadIdx.x;
int idy = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += blockSizey) {
tile[threadIdx.y+j][threadIdx.x] = mat_in[(idy+j)*width + idx];
}
__syncthreads();
idx = blockIdx.y * TILE_DIM + threadIdx.x;
idy = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += blockSizey) {
mat_out[(idy+j)*width + idx] = tile[threadIdx.x][threadIdx.y+j];
}
}
int main(void) {
int cols = 1<<10, rows = 1<<10;
int grid_cols = imin(512, (cols + TILE_DIM - 1)/TILE_DIM);
int grid_rows = imin(512, (rows + TILE_DIM - 1)/TILE_DIM);
dim3 dimBlock(blockSizex, blockSizey, 1);
dim3 dimGrid(grid_cols, grid_rows, 1);
// Allocate memory in host RAM
double *h_mat_in = new double[cols*rows];
double *h_mat_out = new double[cols*rows];
// Initialize h_mat_in
std::srand(1103);
for (int i = 0; i < rows; i++)
for (int j = 0; j < cols; j++)
// h_mat_in[i*cols+j] = double (((generator() % (1000 - 0 + 1)) + 0)/1000);
h_mat_in[i*cols+j] = double(std::rand())/double(RAND_MAX);
// capture the GPU start time
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
// Allocate memory on device
double *d_mat_in, *d_mat_out;
cudaMalloc(&d_mat_in, cols*rows*sizeof(double));
cudaMalloc(&d_mat_out, cols*rows*sizeof(double));
// Copy matrix in from host to device
cudaMemcpy(d_mat_in, h_mat_in, cols*rows*sizeof(double), cudaMemcpyHostToDevice);
// Run kernel
gpu_matrix_trans_naive<<<dimGrid, dimBlock>>>(d_mat_in, d_mat_out);
gpu_matrix_trans_sharedmem<<<dimGrid, dimBlock>>>(d_mat_in, d_mat_out);
gpu_matrix_trans_coales_sharedmem<<<dimGrid, dimBlock>>>(d_mat_in, d_mat_out);
gpu_matrix_trans_coales_sharedmem_NoBankConfl<<<dimGrid, dimBlock>>>(d_mat_in, d_mat_out);
// Copy result from device to host
cudaMemcpy(h_mat_out, d_mat_out, cols*rows*sizeof(double), cudaMemcpyDeviceToHost);
cudaThreadSynchronize();
// get GPU stop time
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
// Check results
int check_flag = 1;
for (int i = 0; i < rows; i++)
for (int j = 0; j < cols; j++)
if (h_mat_out[j*rows + i] != h_mat_in[i*cols + j])
check_flag = 0;
if (!check_flag)
std::cout << "GPU matrix transpose not success!!!" << std::endl;
else {
std::cout << "GPU matrix transpose success!!!" << std::endl;
std::cout << "GPU matrix multiplication time: " << elapsedTime << " ms." << std::endl;
}
// Free memory
cudaFree(d_mat_in);
cudaFree(d_mat_out);
delete [] h_mat_in;
delete [] h_mat_out;
return 0;
}
|
#include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <cstdlib>
#include <ctime>
const int blockSizex = 32;
const int blockSizey = 8;
const int TILE_DIM = blockSizex;
#define imin(a, b) (a<b?a:b)
// Naive matrix transpose
__global__
void gpu_matrix_trans_naive(double *mat_in, double *mat_out) {
int idx = blockIdx.x * TILE_DIM + threadIdx.x;
int idy = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += blockSizey) {
mat_out[idy + j + idx*width] = mat_in[(idy+j)*width + idx];
}
}
// Transpose via shared memory
__global__
void gpu_matrix_trans_sharedmem(double *mat_in, double *mat_out) {
// shared memory (48KB/N per block), N is the number of blocks on the same multiprocessor
__shared__ double tile[TILE_DIM*TILE_DIM];
int idx = blockIdx.x * TILE_DIM + threadIdx.x;
int idy = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += blockSizey) {
tile[threadIdx.x + (threadIdx.y+j)*TILE_DIM] = mat_in[(idy+j)*width + idx];
}
__syncthreads();
for (int j = 0; j < TILE_DIM; j += blockSizey) {
mat_out[(idy+j)*width + idx] = tile[threadIdx.x*TILE_DIM + threadIdx.y + j];
}
}
// Coalesced Transpose via shared memory
__global__
void gpu_matrix_trans_coales_sharedmem(double *mat_in, double *mat_out) {
// shared memory (48KB/N per block), N is the number of blocks on the same multiprocessor
__shared__ double tile[TILE_DIM*TILE_DIM];
int idx = blockIdx.x * TILE_DIM + threadIdx.x;
int idy = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += blockSizey) {
tile[threadIdx.x*TILE_DIM + threadIdx.y + j] = mat_in[(idy+j)*width + idx];
}
__syncthreads();
idx = blockIdx.y * TILE_DIM + threadIdx.x;
idy = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += blockSizey) {
mat_out[(idy+j)*width + idx] = tile[threadIdx.x + (threadIdx.y+j)*TILE_DIM];
}
}
// Coalesced Transpose via shared memory without bank conflict
__global__
void gpu_matrix_trans_coales_sharedmem_NoBankConfl(double *mat_in, double *mat_out) {
// shared memory (48KB/N per block), N is the number of blocks on the same multiprocessor
__shared__ double tile[TILE_DIM][TILE_DIM+1];
int idx = blockIdx.x * TILE_DIM + threadIdx.x;
int idy = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += blockSizey) {
tile[threadIdx.y+j][threadIdx.x] = mat_in[(idy+j)*width + idx];
}
__syncthreads();
idx = blockIdx.y * TILE_DIM + threadIdx.x;
idy = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += blockSizey) {
mat_out[(idy+j)*width + idx] = tile[threadIdx.x][threadIdx.y+j];
}
}
int main(void) {
int cols = 1<<10, rows = 1<<10;
int grid_cols = imin(512, (cols + TILE_DIM - 1)/TILE_DIM);
int grid_rows = imin(512, (rows + TILE_DIM - 1)/TILE_DIM);
dim3 dimBlock(blockSizex, blockSizey, 1);
dim3 dimGrid(grid_cols, grid_rows, 1);
// Allocate memory in host RAM
double *h_mat_in = new double[cols*rows];
double *h_mat_out = new double[cols*rows];
// Initialize h_mat_in
std::srand(1103);
for (int i = 0; i < rows; i++)
for (int j = 0; j < cols; j++)
// h_mat_in[i*cols+j] = double (((generator() % (1000 - 0 + 1)) + 0)/1000);
h_mat_in[i*cols+j] = double(std::rand())/double(RAND_MAX);
// capture the GPU start time
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
// Allocate memory on device
double *d_mat_in, *d_mat_out;
hipMalloc(&d_mat_in, cols*rows*sizeof(double));
hipMalloc(&d_mat_out, cols*rows*sizeof(double));
// Copy matrix in from host to device
hipMemcpy(d_mat_in, h_mat_in, cols*rows*sizeof(double), hipMemcpyHostToDevice);
// Run kernel
gpu_matrix_trans_naive<<<dimGrid, dimBlock>>>(d_mat_in, d_mat_out);
gpu_matrix_trans_sharedmem<<<dimGrid, dimBlock>>>(d_mat_in, d_mat_out);
gpu_matrix_trans_coales_sharedmem<<<dimGrid, dimBlock>>>(d_mat_in, d_mat_out);
gpu_matrix_trans_coales_sharedmem_NoBankConfl<<<dimGrid, dimBlock>>>(d_mat_in, d_mat_out);
// Copy result from device to host
hipMemcpy(h_mat_out, d_mat_out, cols*rows*sizeof(double), hipMemcpyDeviceToHost);
hipDeviceSynchronize();
// get GPU stop time
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
// Check results
int check_flag = 1;
for (int i = 0; i < rows; i++)
for (int j = 0; j < cols; j++)
if (h_mat_out[j*rows + i] != h_mat_in[i*cols + j])
check_flag = 0;
if (!check_flag)
std::cout << "GPU matrix transpose not success!!!" << std::endl;
else {
std::cout << "GPU matrix transpose success!!!" << std::endl;
std::cout << "GPU matrix multiplication time: " << elapsedTime << " ms." << std::endl;
}
// Free memory
hipFree(d_mat_in);
hipFree(d_mat_out);
delete [] h_mat_in;
delete [] h_mat_out;
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <cstdlib>
#include <ctime>
const int blockSizex = 32;
const int blockSizey = 8;
const int TILE_DIM = blockSizex;
#define imin(a, b) (a<b?a:b)
// Naive matrix transpose
__global__
void gpu_matrix_trans_naive(double *mat_in, double *mat_out) {
int idx = blockIdx.x * TILE_DIM + threadIdx.x;
int idy = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += blockSizey) {
mat_out[idy + j + idx*width] = mat_in[(idy+j)*width + idx];
}
}
// Transpose via shared memory
__global__
void gpu_matrix_trans_sharedmem(double *mat_in, double *mat_out) {
// shared memory (48KB/N per block), N is the number of blocks on the same multiprocessor
__shared__ double tile[TILE_DIM*TILE_DIM];
int idx = blockIdx.x * TILE_DIM + threadIdx.x;
int idy = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += blockSizey) {
tile[threadIdx.x + (threadIdx.y+j)*TILE_DIM] = mat_in[(idy+j)*width + idx];
}
__syncthreads();
for (int j = 0; j < TILE_DIM; j += blockSizey) {
mat_out[(idy+j)*width + idx] = tile[threadIdx.x*TILE_DIM + threadIdx.y + j];
}
}
// Coalesced Transpose via shared memory
__global__
void gpu_matrix_trans_coales_sharedmem(double *mat_in, double *mat_out) {
// shared memory (48KB/N per block), N is the number of blocks on the same multiprocessor
__shared__ double tile[TILE_DIM*TILE_DIM];
int idx = blockIdx.x * TILE_DIM + threadIdx.x;
int idy = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += blockSizey) {
tile[threadIdx.x*TILE_DIM + threadIdx.y + j] = mat_in[(idy+j)*width + idx];
}
__syncthreads();
idx = blockIdx.y * TILE_DIM + threadIdx.x;
idy = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += blockSizey) {
mat_out[(idy+j)*width + idx] = tile[threadIdx.x + (threadIdx.y+j)*TILE_DIM];
}
}
// Coalesced Transpose via shared memory without bank conflict
__global__
void gpu_matrix_trans_coales_sharedmem_NoBankConfl(double *mat_in, double *mat_out) {
// shared memory (48KB/N per block), N is the number of blocks on the same multiprocessor
__shared__ double tile[TILE_DIM][TILE_DIM+1];
int idx = blockIdx.x * TILE_DIM + threadIdx.x;
int idy = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += blockSizey) {
tile[threadIdx.y+j][threadIdx.x] = mat_in[(idy+j)*width + idx];
}
__syncthreads();
idx = blockIdx.y * TILE_DIM + threadIdx.x;
idy = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += blockSizey) {
mat_out[(idy+j)*width + idx] = tile[threadIdx.x][threadIdx.y+j];
}
}
int main(void) {
int cols = 1<<10, rows = 1<<10;
int grid_cols = imin(512, (cols + TILE_DIM - 1)/TILE_DIM);
int grid_rows = imin(512, (rows + TILE_DIM - 1)/TILE_DIM);
dim3 dimBlock(blockSizex, blockSizey, 1);
dim3 dimGrid(grid_cols, grid_rows, 1);
// Allocate memory in host RAM
double *h_mat_in = new double[cols*rows];
double *h_mat_out = new double[cols*rows];
// Initialize h_mat_in
std::srand(1103);
for (int i = 0; i < rows; i++)
for (int j = 0; j < cols; j++)
// h_mat_in[i*cols+j] = double (((generator() % (1000 - 0 + 1)) + 0)/1000);
h_mat_in[i*cols+j] = double(std::rand())/double(RAND_MAX);
// capture the GPU start time
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
// Allocate memory on device
double *d_mat_in, *d_mat_out;
hipMalloc(&d_mat_in, cols*rows*sizeof(double));
hipMalloc(&d_mat_out, cols*rows*sizeof(double));
// Copy matrix in from host to device
hipMemcpy(d_mat_in, h_mat_in, cols*rows*sizeof(double), hipMemcpyHostToDevice);
// Run kernel
gpu_matrix_trans_naive<<<dimGrid, dimBlock>>>(d_mat_in, d_mat_out);
gpu_matrix_trans_sharedmem<<<dimGrid, dimBlock>>>(d_mat_in, d_mat_out);
gpu_matrix_trans_coales_sharedmem<<<dimGrid, dimBlock>>>(d_mat_in, d_mat_out);
gpu_matrix_trans_coales_sharedmem_NoBankConfl<<<dimGrid, dimBlock>>>(d_mat_in, d_mat_out);
// Copy result from device to host
hipMemcpy(h_mat_out, d_mat_out, cols*rows*sizeof(double), hipMemcpyDeviceToHost);
hipDeviceSynchronize();
// get GPU stop time
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
// Check results
int check_flag = 1;
for (int i = 0; i < rows; i++)
for (int j = 0; j < cols; j++)
if (h_mat_out[j*rows + i] != h_mat_in[i*cols + j])
check_flag = 0;
if (!check_flag)
std::cout << "GPU matrix transpose not success!!!" << std::endl;
else {
std::cout << "GPU matrix transpose success!!!" << std::endl;
std::cout << "GPU matrix multiplication time: " << elapsedTime << " ms." << std::endl;
}
// Free memory
hipFree(d_mat_in);
hipFree(d_mat_out);
delete [] h_mat_in;
delete [] h_mat_out;
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22gpu_matrix_trans_naivePdS_
.globl _Z22gpu_matrix_trans_naivePdS_
.p2align 8
.type _Z22gpu_matrix_trans_naivePdS_,@function
_Z22gpu_matrix_trans_naivePdS_:
s_load_b32 s4, s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_lshl_b32 s5, s14, 5
s_lshl_b32 s6, s15, 5
s_load_b128 s[0:3], s[0:1], 0x0
v_add_nc_u32_e32 v2, s5, v1
v_add_nc_u32_e32 v3, s6, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, s4, v2
v_mul_lo_u32 v3, s4, v3
s_lshl_b32 s4, s4, 8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v2, 5, v2
v_lshlrev_b32_e32 v3, 5, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v2, v0, v2, s6
v_add3_u32 v0, v1, v3, s5
s_mov_b32 s5, -8
.p2align 6
.LBB0_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s5, s5, 8
v_add_nc_u32_e32 v5, s5, v2
s_cmp_gt_u32 s5, 23
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[3:4], 3, v[0:1]
v_add_nc_u32_e32 v0, s4, v0
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_lshlrev_b64 v[5:6], 3, v[5:6]
global_load_b64 v[3:4], v[3:4], off
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
s_waitcnt vmcnt(0)
global_store_b64 v[5:6], v[3:4], off
s_cbranch_scc0 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22gpu_matrix_trans_naivePdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22gpu_matrix_trans_naivePdS_, .Lfunc_end0-_Z22gpu_matrix_trans_naivePdS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z26gpu_matrix_trans_sharedmemPdS_
.globl _Z26gpu_matrix_trans_sharedmemPdS_
.p2align 8
.type _Z26gpu_matrix_trans_sharedmemPdS_,@function
_Z26gpu_matrix_trans_sharedmemPdS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x0
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_lshl_b32 s5, s14, 5
s_mov_b32 s7, -8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v1, s15, 5, v2
v_lshlrev_b32_e32 v0, 3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshl_add_u32 v5, v2, 8, v0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v4, s4, v1
s_lshl_b32 s6, s4, 8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v1, 5, v4
v_add3_u32 v0, v3, v1, s5
.LBB1_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s7, s7, 8
s_cmp_gt_u32 s7, 23
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 3, v[0:1]
v_add_nc_u32_e32 v0, s6, v0
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_load_b64 v[6:7], v[6:7], off
s_waitcnt vmcnt(0)
ds_store_b64 v5, v[6:7]
v_add_nc_u32_e32 v5, 0x800, v5
s_cbranch_scc0 .LBB1_1
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b32_e32 v0, 5, v4
v_lshlrev_b32_e32 v1, 3, v2
s_lshl_b32 s2, s4, 8
s_mov_b32 s3, -8
s_waitcnt lgkmcnt(0)
v_add3_u32 v0, v3, v0, s5
v_lshl_add_u32 v2, v3, 8, v1
s_barrier
buffer_gl0_inv
.LBB1_3:
ds_load_b64 v[3:4], v2
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v2, 64, v2
s_add_i32 s3, s3, 8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_gt_u32 s3, 23
v_lshlrev_b64 v[5:6], 3, v[0:1]
v_add_nc_u32_e32 v0, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b64 v[5:6], v[3:4], off
s_cbranch_scc0 .LBB1_3
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26gpu_matrix_trans_sharedmemPdS_
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z26gpu_matrix_trans_sharedmemPdS_, .Lfunc_end1-_Z26gpu_matrix_trans_sharedmemPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z33gpu_matrix_trans_coales_sharedmemPdS_
.globl _Z33gpu_matrix_trans_coales_sharedmemPdS_
.p2align 8
.type _Z33gpu_matrix_trans_coales_sharedmemPdS_,@function
_Z33gpu_matrix_trans_coales_sharedmemPdS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x0
v_bfe_u32 v2, v0, 10, 10
s_lshl_b32 s5, s15, 5
v_and_b32_e32 v3, 0x3ff, v0
s_lshl_b32 s6, s14, 5
s_mov_b32 s8, -8
v_add_nc_u32_e32 v1, s5, v2
v_lshlrev_b32_e32 v0, 3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshl_add_u32 v4, v3, 8, v0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v1, s4, v1
s_lshl_b32 s7, s4, 8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v1, 5, v1
v_add3_u32 v0, v3, v1, s6
.LBB2_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s8, s8, 8
s_cmp_gt_u32 s8, 23
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 3, v[0:1]
v_add_nc_u32_e32 v0, s7, v0
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_load_b64 v[5:6], v[5:6], off
s_waitcnt vmcnt(0)
ds_store_b64 v4, v[5:6]
v_add_nc_u32_e32 v4, 64, v4
s_cbranch_scc0 .LBB2_1
v_add_nc_u32_e32 v0, s6, v2
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b32_e32 v1, 3, v3
s_lshl_b32 s2, s4, 8
s_mov_b32 s3, -8
v_mul_lo_u32 v0, s4, v0
s_waitcnt lgkmcnt(0)
v_lshl_add_u32 v2, v2, 8, v1
s_barrier
buffer_gl0_inv
v_lshlrev_b32_e32 v0, 5, v0
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v0, v3, v0, s5
.LBB2_3:
ds_load_b64 v[3:4], v2
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v2, 0x800, v2
s_add_i32 s3, s3, 8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_gt_u32 s3, 23
v_lshlrev_b64 v[5:6], 3, v[0:1]
v_add_nc_u32_e32 v0, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b64 v[5:6], v[3:4], off
s_cbranch_scc0 .LBB2_3
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z33gpu_matrix_trans_coales_sharedmemPdS_
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z33gpu_matrix_trans_coales_sharedmemPdS_, .Lfunc_end2-_Z33gpu_matrix_trans_coales_sharedmemPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
.globl _Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
.p2align 8
.type _Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_,@function
_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x0
v_bfe_u32 v2, v0, 10, 10
s_lshl_b32 s5, s15, 5
v_and_b32_e32 v3, 0x3ff, v0
s_lshl_b32 s6, s14, 5
s_mov_b32 s8, -8
v_add_nc_u32_e32 v1, s5, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v0, 3, v3
v_mad_u32_u24 v4, v2, 0x108, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, s4, v1
s_lshl_b32 s7, s4, 8
v_lshlrev_b32_e32 v1, 5, v1
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v0, v3, v1, s6
.LBB3_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s8, s8, 8
s_cmp_gt_u32 s8, 23
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 3, v[0:1]
v_add_nc_u32_e32 v0, s7, v0
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_load_b64 v[5:6], v[5:6], off
s_waitcnt vmcnt(0)
ds_store_b64 v4, v[5:6]
v_add_nc_u32_e32 v4, 0x840, v4
s_cbranch_scc0 .LBB3_1
v_add_nc_u32_e32 v0, s6, v2
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b32_e32 v1, 3, v2
s_lshl_b32 s2, s4, 8
s_mov_b32 s3, -8
v_mul_lo_u32 v0, s4, v0
s_waitcnt lgkmcnt(0)
v_mad_u32_u24 v2, v3, 0x108, v1
s_barrier
buffer_gl0_inv
v_lshlrev_b32_e32 v0, 5, v0
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v0, v3, v0, s5
.LBB3_3:
ds_load_b64 v[3:4], v2
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v2, 64, v2
s_add_i32 s3, s3, 8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_gt_u32 s3, 23
v_lshlrev_b64 v[5:6], 3, v[0:1]
v_add_nc_u32_e32 v0, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b64 v[5:6], v[3:4], off
s_cbranch_scc0 .LBB3_3
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
.amdhsa_group_segment_fixed_size 8448
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_, .Lfunc_end3-_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22gpu_matrix_trans_naivePdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22gpu_matrix_trans_naivePdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26gpu_matrix_trans_sharedmemPdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26gpu_matrix_trans_sharedmemPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z33gpu_matrix_trans_coales_sharedmemPdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z33gpu_matrix_trans_coales_sharedmemPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8448
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <cstdlib>
#include <ctime>
const int blockSizex = 32;
const int blockSizey = 8;
const int TILE_DIM = blockSizex;
#define imin(a, b) (a<b?a:b)
// Naive matrix transpose
__global__
void gpu_matrix_trans_naive(double *mat_in, double *mat_out) {
int idx = blockIdx.x * TILE_DIM + threadIdx.x;
int idy = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += blockSizey) {
mat_out[idy + j + idx*width] = mat_in[(idy+j)*width + idx];
}
}
// Transpose via shared memory
__global__
void gpu_matrix_trans_sharedmem(double *mat_in, double *mat_out) {
// shared memory (48KB/N per block), N is the number of blocks on the same multiprocessor
__shared__ double tile[TILE_DIM*TILE_DIM];
int idx = blockIdx.x * TILE_DIM + threadIdx.x;
int idy = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += blockSizey) {
tile[threadIdx.x + (threadIdx.y+j)*TILE_DIM] = mat_in[(idy+j)*width + idx];
}
__syncthreads();
for (int j = 0; j < TILE_DIM; j += blockSizey) {
mat_out[(idy+j)*width + idx] = tile[threadIdx.x*TILE_DIM + threadIdx.y + j];
}
}
// Coalesced Transpose via shared memory
__global__
void gpu_matrix_trans_coales_sharedmem(double *mat_in, double *mat_out) {
// shared memory (48KB/N per block), N is the number of blocks on the same multiprocessor
__shared__ double tile[TILE_DIM*TILE_DIM];
int idx = blockIdx.x * TILE_DIM + threadIdx.x;
int idy = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += blockSizey) {
tile[threadIdx.x*TILE_DIM + threadIdx.y + j] = mat_in[(idy+j)*width + idx];
}
__syncthreads();
idx = blockIdx.y * TILE_DIM + threadIdx.x;
idy = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += blockSizey) {
mat_out[(idy+j)*width + idx] = tile[threadIdx.x + (threadIdx.y+j)*TILE_DIM];
}
}
// Coalesced Transpose via shared memory without bank conflict
__global__
void gpu_matrix_trans_coales_sharedmem_NoBankConfl(double *mat_in, double *mat_out) {
// shared memory (48KB/N per block), N is the number of blocks on the same multiprocessor
__shared__ double tile[TILE_DIM][TILE_DIM+1];
int idx = blockIdx.x * TILE_DIM + threadIdx.x;
int idy = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += blockSizey) {
tile[threadIdx.y+j][threadIdx.x] = mat_in[(idy+j)*width + idx];
}
__syncthreads();
idx = blockIdx.y * TILE_DIM + threadIdx.x;
idy = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += blockSizey) {
mat_out[(idy+j)*width + idx] = tile[threadIdx.x][threadIdx.y+j];
}
}
int main(void) {
int cols = 1<<10, rows = 1<<10;
int grid_cols = imin(512, (cols + TILE_DIM - 1)/TILE_DIM);
int grid_rows = imin(512, (rows + TILE_DIM - 1)/TILE_DIM);
dim3 dimBlock(blockSizex, blockSizey, 1);
dim3 dimGrid(grid_cols, grid_rows, 1);
// Allocate memory in host RAM
double *h_mat_in = new double[cols*rows];
double *h_mat_out = new double[cols*rows];
// Initialize h_mat_in
std::srand(1103);
for (int i = 0; i < rows; i++)
for (int j = 0; j < cols; j++)
// h_mat_in[i*cols+j] = double (((generator() % (1000 - 0 + 1)) + 0)/1000);
h_mat_in[i*cols+j] = double(std::rand())/double(RAND_MAX);
// capture the GPU start time
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
// Allocate memory on device
double *d_mat_in, *d_mat_out;
hipMalloc(&d_mat_in, cols*rows*sizeof(double));
hipMalloc(&d_mat_out, cols*rows*sizeof(double));
// Copy matrix in from host to device
hipMemcpy(d_mat_in, h_mat_in, cols*rows*sizeof(double), hipMemcpyHostToDevice);
// Run kernel
gpu_matrix_trans_naive<<<dimGrid, dimBlock>>>(d_mat_in, d_mat_out);
gpu_matrix_trans_sharedmem<<<dimGrid, dimBlock>>>(d_mat_in, d_mat_out);
gpu_matrix_trans_coales_sharedmem<<<dimGrid, dimBlock>>>(d_mat_in, d_mat_out);
gpu_matrix_trans_coales_sharedmem_NoBankConfl<<<dimGrid, dimBlock>>>(d_mat_in, d_mat_out);
// Copy result from device to host
hipMemcpy(h_mat_out, d_mat_out, cols*rows*sizeof(double), hipMemcpyDeviceToHost);
hipDeviceSynchronize();
// get GPU stop time
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
// Check results
int check_flag = 1;
for (int i = 0; i < rows; i++)
for (int j = 0; j < cols; j++)
if (h_mat_out[j*rows + i] != h_mat_in[i*cols + j])
check_flag = 0;
if (!check_flag)
std::cout << "GPU matrix transpose not success!!!" << std::endl;
else {
std::cout << "GPU matrix transpose success!!!" << std::endl;
std::cout << "GPU matrix multiplication time: " << elapsedTime << " ms." << std::endl;
}
// Free memory
hipFree(d_mat_in);
hipFree(d_mat_out);
delete [] h_mat_in;
delete [] h_mat_out;
return 0;
}
|
.text
.file "gpucpptranspose.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z37__device_stub__gpu_matrix_trans_naivePdS_ # -- Begin function _Z37__device_stub__gpu_matrix_trans_naivePdS_
.p2align 4, 0x90
.type _Z37__device_stub__gpu_matrix_trans_naivePdS_,@function
_Z37__device_stub__gpu_matrix_trans_naivePdS_: # @_Z37__device_stub__gpu_matrix_trans_naivePdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z22gpu_matrix_trans_naivePdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z37__device_stub__gpu_matrix_trans_naivePdS_, .Lfunc_end0-_Z37__device_stub__gpu_matrix_trans_naivePdS_
.cfi_endproc
# -- End function
.globl _Z41__device_stub__gpu_matrix_trans_sharedmemPdS_ # -- Begin function _Z41__device_stub__gpu_matrix_trans_sharedmemPdS_
.p2align 4, 0x90
.type _Z41__device_stub__gpu_matrix_trans_sharedmemPdS_,@function
_Z41__device_stub__gpu_matrix_trans_sharedmemPdS_: # @_Z41__device_stub__gpu_matrix_trans_sharedmemPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z26gpu_matrix_trans_sharedmemPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z41__device_stub__gpu_matrix_trans_sharedmemPdS_, .Lfunc_end1-_Z41__device_stub__gpu_matrix_trans_sharedmemPdS_
.cfi_endproc
# -- End function
.globl _Z48__device_stub__gpu_matrix_trans_coales_sharedmemPdS_ # -- Begin function _Z48__device_stub__gpu_matrix_trans_coales_sharedmemPdS_
.p2align 4, 0x90
.type _Z48__device_stub__gpu_matrix_trans_coales_sharedmemPdS_,@function
_Z48__device_stub__gpu_matrix_trans_coales_sharedmemPdS_: # @_Z48__device_stub__gpu_matrix_trans_coales_sharedmemPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z33gpu_matrix_trans_coales_sharedmemPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z48__device_stub__gpu_matrix_trans_coales_sharedmemPdS_, .Lfunc_end2-_Z48__device_stub__gpu_matrix_trans_coales_sharedmemPdS_
.cfi_endproc
# -- End function
.globl _Z60__device_stub__gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_ # -- Begin function _Z60__device_stub__gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
.p2align 4, 0x90
.type _Z60__device_stub__gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_,@function
_Z60__device_stub__gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_: # @_Z60__device_stub__gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z60__device_stub__gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_, .Lfunc_end3-_Z60__device_stub__gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x41dfffffffc00000 # double 2147483647
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $8388608, %edi # imm = 0x800000
callq _Znam
movq %rax, %rbx
movl $8388608, %edi # imm = 0x800000
callq _Znam
movq %rax, %r14
movl $1103, %edi # imm = 0x44F
callq srand
xorl %r15d, %r15d
movq %rbx, %r12
.p2align 4, 0x90
.LBB4_1: # %.preheader127
# =>This Loop Header: Depth=1
# Child Loop BB4_2 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_2: # Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movsd .LCPI4_0(%rip), %xmm1 # xmm1 = mem[0],zero
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd %xmm1, %xmm0
movsd %xmm0, (%r12,%r13,8)
incq %r13
cmpq $1024, %r13 # imm = 0x400
jne .LBB4_2
# %bb.3: # in Loop: Header=BB4_1 Depth=1
incq %r15
addq $8192, %r12 # imm = 0x2000
cmpq $1024, %r15 # imm = 0x400
jne .LBB4_1
# %bb.4:
movabsq $137438953504, %r12 # imm = 0x2000000020
movabsq $34359738400, %r15 # imm = 0x800000020
leaq 112(%rsp), %rdi
callq hipEventCreate
leaq 104(%rsp), %rdi
callq hipEventCreate
movq 112(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 96(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
leaq 88(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
movq 96(%rsp), %rdi
movl $8388608, %edx # imm = 0x800000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_6
# %bb.5:
movq 96(%rsp), %rax
movq 88(%rsp), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z22gpu_matrix_trans_naivePdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_6:
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_8
# %bb.7:
movq 96(%rsp), %rax
movq 88(%rsp), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z26gpu_matrix_trans_sharedmemPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_8:
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_10
# %bb.9:
movq 96(%rsp), %rax
movq 88(%rsp), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z33gpu_matrix_trans_coales_sharedmemPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_10:
xorl %r13d, %r13d
movl $1, %ebp
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_12
# %bb.11:
movq 96(%rsp), %rax
movq 88(%rsp), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_12:
movq 88(%rsp), %rsi
movl $8388608, %edx # imm = 0x800000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
movq 104(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 104(%rsp), %rdi
callq hipEventSynchronize
movq 112(%rsp), %rsi
movq 104(%rsp), %rdx
leaq 64(%rsp), %rdi
callq hipEventElapsedTime
movq %r14, %rax
movq %rbx, %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_13: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_14 Depth 2
movq %rax, %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB4_14: # Parent Loop BB4_13 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rsi), %xmm0 # xmm0 = mem[0],zero
ucomisd (%rcx,%rdi,8), %xmm0
cmovnel %r13d, %ebp
cmovpl %r13d, %ebp
incq %rdi
addq $8192, %rsi # imm = 0x2000
cmpq $1024, %rdi # imm = 0x400
jne .LBB4_14
# %bb.15: # in Loop: Header=BB4_13 Depth=1
incq %rdx
addq $8192, %rcx # imm = 0x2000
addq $8, %rax
cmpq $1024, %rdx # imm = 0x400
jne .LBB4_13
# %bb.16:
movl $_ZSt4cout, %edi
testl %ebp, %ebp
je .LBB4_17
# %bb.22:
movl $.L.str.1, %esi
movl $31, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB4_32
# %bb.23: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i104
cmpb $0, 56(%r15)
je .LBB4_25
# %bb.24:
movzbl 67(%r15), %eax
jmp .LBB4_26
.LBB4_17:
movl $.L.str, %esi
movl $35, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB4_32
# %bb.18: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB4_20
# %bb.19:
movzbl 67(%r15), %eax
jmp .LBB4_21
.LBB4_25:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_26: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit107
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $32, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str.3, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB4_32
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i109
cmpb $0, 56(%r12)
je .LBB4_29
# %bb.28:
movzbl 67(%r12), %eax
jmp .LBB4_30
.LBB4_29:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_30: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit112
movsbl %al, %esi
movq %r15, %rdi
jmp .LBB4_31
.LBB4_20:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_21: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
.LBB4_31:
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 96(%rsp), %rdi
callq hipFree
movq 88(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_32:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22gpu_matrix_trans_naivePdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26gpu_matrix_trans_sharedmemPdS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z33gpu_matrix_trans_coales_sharedmemPdS_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22gpu_matrix_trans_naivePdS_,@object # @_Z22gpu_matrix_trans_naivePdS_
.section .rodata,"a",@progbits
.globl _Z22gpu_matrix_trans_naivePdS_
.p2align 3, 0x0
_Z22gpu_matrix_trans_naivePdS_:
.quad _Z37__device_stub__gpu_matrix_trans_naivePdS_
.size _Z22gpu_matrix_trans_naivePdS_, 8
.type _Z26gpu_matrix_trans_sharedmemPdS_,@object # @_Z26gpu_matrix_trans_sharedmemPdS_
.globl _Z26gpu_matrix_trans_sharedmemPdS_
.p2align 3, 0x0
_Z26gpu_matrix_trans_sharedmemPdS_:
.quad _Z41__device_stub__gpu_matrix_trans_sharedmemPdS_
.size _Z26gpu_matrix_trans_sharedmemPdS_, 8
.type _Z33gpu_matrix_trans_coales_sharedmemPdS_,@object # @_Z33gpu_matrix_trans_coales_sharedmemPdS_
.globl _Z33gpu_matrix_trans_coales_sharedmemPdS_
.p2align 3, 0x0
_Z33gpu_matrix_trans_coales_sharedmemPdS_:
.quad _Z48__device_stub__gpu_matrix_trans_coales_sharedmemPdS_
.size _Z33gpu_matrix_trans_coales_sharedmemPdS_, 8
.type _Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_,@object # @_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
.globl _Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
.p2align 3, 0x0
_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_:
.quad _Z60__device_stub__gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
.size _Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "GPU matrix transpose not success!!!"
.size .L.str, 36
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU matrix transpose success!!!"
.size .L.str.1, 32
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "GPU matrix multiplication time: "
.size .L.str.2, 33
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " ms."
.size .L.str.3, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z22gpu_matrix_trans_naivePdS_"
.size .L__unnamed_1, 31
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z26gpu_matrix_trans_sharedmemPdS_"
.size .L__unnamed_2, 35
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z33gpu_matrix_trans_coales_sharedmemPdS_"
.size .L__unnamed_3, 42
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_"
.size .L__unnamed_4, 54
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__gpu_matrix_trans_naivePdS_
.addrsig_sym _Z41__device_stub__gpu_matrix_trans_sharedmemPdS_
.addrsig_sym _Z48__device_stub__gpu_matrix_trans_coales_sharedmemPdS_
.addrsig_sym _Z60__device_stub__gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22gpu_matrix_trans_naivePdS_
.addrsig_sym _Z26gpu_matrix_trans_sharedmemPdS_
.addrsig_sym _Z33gpu_matrix_trans_coales_sharedmemPdS_
.addrsig_sym _Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0019eea9_00000000-6_gpucpptranspose.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z22gpu_matrix_trans_naivePdS_PdS_
.type _Z44__device_stub__Z22gpu_matrix_trans_naivePdS_PdS_, @function
_Z44__device_stub__Z22gpu_matrix_trans_naivePdS_PdS_:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z22gpu_matrix_trans_naivePdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z44__device_stub__Z22gpu_matrix_trans_naivePdS_PdS_, .-_Z44__device_stub__Z22gpu_matrix_trans_naivePdS_PdS_
.globl _Z22gpu_matrix_trans_naivePdS_
.type _Z22gpu_matrix_trans_naivePdS_, @function
_Z22gpu_matrix_trans_naivePdS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z22gpu_matrix_trans_naivePdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z22gpu_matrix_trans_naivePdS_, .-_Z22gpu_matrix_trans_naivePdS_
.globl _Z48__device_stub__Z26gpu_matrix_trans_sharedmemPdS_PdS_
.type _Z48__device_stub__Z26gpu_matrix_trans_sharedmemPdS_PdS_, @function
_Z48__device_stub__Z26gpu_matrix_trans_sharedmemPdS_PdS_:
.LFB3696:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z26gpu_matrix_trans_sharedmemPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z48__device_stub__Z26gpu_matrix_trans_sharedmemPdS_PdS_, .-_Z48__device_stub__Z26gpu_matrix_trans_sharedmemPdS_PdS_
.globl _Z26gpu_matrix_trans_sharedmemPdS_
.type _Z26gpu_matrix_trans_sharedmemPdS_, @function
_Z26gpu_matrix_trans_sharedmemPdS_:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z26gpu_matrix_trans_sharedmemPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z26gpu_matrix_trans_sharedmemPdS_, .-_Z26gpu_matrix_trans_sharedmemPdS_
.globl _Z55__device_stub__Z33gpu_matrix_trans_coales_sharedmemPdS_PdS_
.type _Z55__device_stub__Z33gpu_matrix_trans_coales_sharedmemPdS_PdS_, @function
_Z55__device_stub__Z33gpu_matrix_trans_coales_sharedmemPdS_PdS_:
.LFB3698:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z33gpu_matrix_trans_coales_sharedmemPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z55__device_stub__Z33gpu_matrix_trans_coales_sharedmemPdS_PdS_, .-_Z55__device_stub__Z33gpu_matrix_trans_coales_sharedmemPdS_PdS_
.globl _Z33gpu_matrix_trans_coales_sharedmemPdS_
.type _Z33gpu_matrix_trans_coales_sharedmemPdS_, @function
_Z33gpu_matrix_trans_coales_sharedmemPdS_:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z55__device_stub__Z33gpu_matrix_trans_coales_sharedmemPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z33gpu_matrix_trans_coales_sharedmemPdS_, .-_Z33gpu_matrix_trans_coales_sharedmemPdS_
.globl _Z67__device_stub__Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_PdS_
.type _Z67__device_stub__Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_PdS_, @function
_Z67__device_stub__Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_PdS_:
.LFB3700:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3700:
.size _Z67__device_stub__Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_PdS_, .-_Z67__device_stub__Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_PdS_
.globl _Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
.type _Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_, @function
_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_:
.LFB3701:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z67__device_stub__Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_, .-_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "GPU matrix transpose not success!!!"
.align 8
.LC2:
.string "GPU matrix transpose success!!!"
.align 8
.LC3:
.string "GPU matrix multiplication time: "
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string " ms."
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $32, 48(%rsp)
movl $8, 52(%rsp)
movl $1, 56(%rsp)
movl $32, 60(%rsp)
movl $32, 64(%rsp)
movl $1, 68(%rsp)
movl $8388608, %edi
call _Znam@PLT
movq %rax, %r12
movl $8388608, %edi
call _Znam@PLT
movq %rax, %r13
movl $1103, %edi
call srand@PLT
movq %r12, %rbp
leaq 8192(%r12), %r14
leaq 8396800(%r12), %r15
.L36:
leaq -8192(%r14), %rbx
.L37:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC0(%rip), %xmm0
movsd %xmm0, (%rbx)
addq $8, %rbx
cmpq %r14, %rbx
jne .L37
addq $8192, %r14
cmpq %r15, %r14
jne .L36
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
leaq 32(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8388608, %edx
movq %r12, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L55
.L39:
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L56
.L40:
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L57
.L41:
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L58
.L42:
movl $2, %ecx
movl $8388608, %edx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
call cudaThreadSynchronize@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq 8388608(%r13), %rcx
movl $0, %r8d
movl $1, %esi
movl $0, %edi
jmp .L43
.L55:
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z44__device_stub__Z22gpu_matrix_trans_naivePdS_PdS_
jmp .L39
.L56:
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z48__device_stub__Z26gpu_matrix_trans_sharedmemPdS_PdS_
jmp .L40
.L57:
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z55__device_stub__Z33gpu_matrix_trans_coales_sharedmemPdS_PdS_
jmp .L41
.L58:
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z67__device_stub__Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_PdS_
jmp .L42
.L51:
movl %edi, %esi
.L44:
addq $8192, %rax
addq $8, %rdx
cmpq %rcx, %rax
je .L59
.L46:
movsd (%rax), %xmm0
ucomisd (%rdx), %xmm0
jp .L51
je .L44
jmp .L51
.L59:
addl $1, %r8d
addq $8, %rcx
addq $8192, %rbp
cmpl $1024, %r8d
je .L47
.L43:
leaq -8388608(%rcx), %rax
movq %rbp, %rdx
jmp .L46
.L47:
testl %esi, %esi
jne .L48
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L49:
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq %r13, %rdi
call _ZdaPv@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L60
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L49
.L60:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC5:
.string "_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_"
.align 8
.LC6:
.string "_Z33gpu_matrix_trans_coales_sharedmemPdS_"
.align 8
.LC7:
.string "_Z26gpu_matrix_trans_sharedmemPdS_"
.align 8
.LC8:
.string "_Z22gpu_matrix_trans_naivePdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3703:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z33gpu_matrix_trans_coales_sharedmemPdS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z26gpu_matrix_trans_sharedmemPdS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z22gpu_matrix_trans_naivePdS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3703:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -4194304
.long 1105199103
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "gpucpptranspose.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z37__device_stub__gpu_matrix_trans_naivePdS_ # -- Begin function _Z37__device_stub__gpu_matrix_trans_naivePdS_
.p2align 4, 0x90
.type _Z37__device_stub__gpu_matrix_trans_naivePdS_,@function
_Z37__device_stub__gpu_matrix_trans_naivePdS_: # @_Z37__device_stub__gpu_matrix_trans_naivePdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z22gpu_matrix_trans_naivePdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z37__device_stub__gpu_matrix_trans_naivePdS_, .Lfunc_end0-_Z37__device_stub__gpu_matrix_trans_naivePdS_
.cfi_endproc
# -- End function
.globl _Z41__device_stub__gpu_matrix_trans_sharedmemPdS_ # -- Begin function _Z41__device_stub__gpu_matrix_trans_sharedmemPdS_
.p2align 4, 0x90
.type _Z41__device_stub__gpu_matrix_trans_sharedmemPdS_,@function
_Z41__device_stub__gpu_matrix_trans_sharedmemPdS_: # @_Z41__device_stub__gpu_matrix_trans_sharedmemPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z26gpu_matrix_trans_sharedmemPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z41__device_stub__gpu_matrix_trans_sharedmemPdS_, .Lfunc_end1-_Z41__device_stub__gpu_matrix_trans_sharedmemPdS_
.cfi_endproc
# -- End function
.globl _Z48__device_stub__gpu_matrix_trans_coales_sharedmemPdS_ # -- Begin function _Z48__device_stub__gpu_matrix_trans_coales_sharedmemPdS_
.p2align 4, 0x90
.type _Z48__device_stub__gpu_matrix_trans_coales_sharedmemPdS_,@function
_Z48__device_stub__gpu_matrix_trans_coales_sharedmemPdS_: # @_Z48__device_stub__gpu_matrix_trans_coales_sharedmemPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z33gpu_matrix_trans_coales_sharedmemPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z48__device_stub__gpu_matrix_trans_coales_sharedmemPdS_, .Lfunc_end2-_Z48__device_stub__gpu_matrix_trans_coales_sharedmemPdS_
.cfi_endproc
# -- End function
.globl _Z60__device_stub__gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_ # -- Begin function _Z60__device_stub__gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
.p2align 4, 0x90
.type _Z60__device_stub__gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_,@function
_Z60__device_stub__gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_: # @_Z60__device_stub__gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z60__device_stub__gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_, .Lfunc_end3-_Z60__device_stub__gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x41dfffffffc00000 # double 2147483647
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $8388608, %edi # imm = 0x800000
callq _Znam
movq %rax, %rbx
movl $8388608, %edi # imm = 0x800000
callq _Znam
movq %rax, %r14
movl $1103, %edi # imm = 0x44F
callq srand
xorl %r15d, %r15d
movq %rbx, %r12
.p2align 4, 0x90
.LBB4_1: # %.preheader127
# =>This Loop Header: Depth=1
# Child Loop BB4_2 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_2: # Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movsd .LCPI4_0(%rip), %xmm1 # xmm1 = mem[0],zero
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd %xmm1, %xmm0
movsd %xmm0, (%r12,%r13,8)
incq %r13
cmpq $1024, %r13 # imm = 0x400
jne .LBB4_2
# %bb.3: # in Loop: Header=BB4_1 Depth=1
incq %r15
addq $8192, %r12 # imm = 0x2000
cmpq $1024, %r15 # imm = 0x400
jne .LBB4_1
# %bb.4:
movabsq $137438953504, %r12 # imm = 0x2000000020
movabsq $34359738400, %r15 # imm = 0x800000020
leaq 112(%rsp), %rdi
callq hipEventCreate
leaq 104(%rsp), %rdi
callq hipEventCreate
movq 112(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 96(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
leaq 88(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
movq 96(%rsp), %rdi
movl $8388608, %edx # imm = 0x800000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_6
# %bb.5:
movq 96(%rsp), %rax
movq 88(%rsp), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z22gpu_matrix_trans_naivePdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_6:
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_8
# %bb.7:
movq 96(%rsp), %rax
movq 88(%rsp), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z26gpu_matrix_trans_sharedmemPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_8:
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_10
# %bb.9:
movq 96(%rsp), %rax
movq 88(%rsp), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z33gpu_matrix_trans_coales_sharedmemPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_10:
xorl %r13d, %r13d
movl $1, %ebp
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_12
# %bb.11:
movq 96(%rsp), %rax
movq 88(%rsp), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_12:
movq 88(%rsp), %rsi
movl $8388608, %edx # imm = 0x800000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
movq 104(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 104(%rsp), %rdi
callq hipEventSynchronize
movq 112(%rsp), %rsi
movq 104(%rsp), %rdx
leaq 64(%rsp), %rdi
callq hipEventElapsedTime
movq %r14, %rax
movq %rbx, %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_13: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_14 Depth 2
movq %rax, %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB4_14: # Parent Loop BB4_13 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rsi), %xmm0 # xmm0 = mem[0],zero
ucomisd (%rcx,%rdi,8), %xmm0
cmovnel %r13d, %ebp
cmovpl %r13d, %ebp
incq %rdi
addq $8192, %rsi # imm = 0x2000
cmpq $1024, %rdi # imm = 0x400
jne .LBB4_14
# %bb.15: # in Loop: Header=BB4_13 Depth=1
incq %rdx
addq $8192, %rcx # imm = 0x2000
addq $8, %rax
cmpq $1024, %rdx # imm = 0x400
jne .LBB4_13
# %bb.16:
movl $_ZSt4cout, %edi
testl %ebp, %ebp
je .LBB4_17
# %bb.22:
movl $.L.str.1, %esi
movl $31, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB4_32
# %bb.23: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i104
cmpb $0, 56(%r15)
je .LBB4_25
# %bb.24:
movzbl 67(%r15), %eax
jmp .LBB4_26
.LBB4_17:
movl $.L.str, %esi
movl $35, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB4_32
# %bb.18: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB4_20
# %bb.19:
movzbl 67(%r15), %eax
jmp .LBB4_21
.LBB4_25:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_26: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit107
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $32, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str.3, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB4_32
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i109
cmpb $0, 56(%r12)
je .LBB4_29
# %bb.28:
movzbl 67(%r12), %eax
jmp .LBB4_30
.LBB4_29:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_30: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit112
movsbl %al, %esi
movq %r15, %rdi
jmp .LBB4_31
.LBB4_20:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_21: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
.LBB4_31:
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 96(%rsp), %rdi
callq hipFree
movq 88(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_32:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22gpu_matrix_trans_naivePdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26gpu_matrix_trans_sharedmemPdS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z33gpu_matrix_trans_coales_sharedmemPdS_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22gpu_matrix_trans_naivePdS_,@object # @_Z22gpu_matrix_trans_naivePdS_
.section .rodata,"a",@progbits
.globl _Z22gpu_matrix_trans_naivePdS_
.p2align 3, 0x0
_Z22gpu_matrix_trans_naivePdS_:
.quad _Z37__device_stub__gpu_matrix_trans_naivePdS_
.size _Z22gpu_matrix_trans_naivePdS_, 8
.type _Z26gpu_matrix_trans_sharedmemPdS_,@object # @_Z26gpu_matrix_trans_sharedmemPdS_
.globl _Z26gpu_matrix_trans_sharedmemPdS_
.p2align 3, 0x0
_Z26gpu_matrix_trans_sharedmemPdS_:
.quad _Z41__device_stub__gpu_matrix_trans_sharedmemPdS_
.size _Z26gpu_matrix_trans_sharedmemPdS_, 8
.type _Z33gpu_matrix_trans_coales_sharedmemPdS_,@object # @_Z33gpu_matrix_trans_coales_sharedmemPdS_
.globl _Z33gpu_matrix_trans_coales_sharedmemPdS_
.p2align 3, 0x0
_Z33gpu_matrix_trans_coales_sharedmemPdS_:
.quad _Z48__device_stub__gpu_matrix_trans_coales_sharedmemPdS_
.size _Z33gpu_matrix_trans_coales_sharedmemPdS_, 8
.type _Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_,@object # @_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
.globl _Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
.p2align 3, 0x0
_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_:
.quad _Z60__device_stub__gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
.size _Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "GPU matrix transpose not success!!!"
.size .L.str, 36
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU matrix transpose success!!!"
.size .L.str.1, 32
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "GPU matrix multiplication time: "
.size .L.str.2, 33
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " ms."
.size .L.str.3, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z22gpu_matrix_trans_naivePdS_"
.size .L__unnamed_1, 31
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z26gpu_matrix_trans_sharedmemPdS_"
.size .L__unnamed_2, 35
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z33gpu_matrix_trans_coales_sharedmemPdS_"
.size .L__unnamed_3, 42
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_"
.size .L__unnamed_4, 54
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__gpu_matrix_trans_naivePdS_
.addrsig_sym _Z41__device_stub__gpu_matrix_trans_sharedmemPdS_
.addrsig_sym _Z48__device_stub__gpu_matrix_trans_coales_sharedmemPdS_
.addrsig_sym _Z60__device_stub__gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22gpu_matrix_trans_naivePdS_
.addrsig_sym _Z26gpu_matrix_trans_sharedmemPdS_
.addrsig_sym _Z33gpu_matrix_trans_coales_sharedmemPdS_
.addrsig_sym _Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include<stdio.h>
__global__ void unique_grid_id_calculation_2d_2d(int* data)
{
int thread_id = blockDim.x * threadIdx.y + threadIdx.x;
int num_threads_in_a_block = blockDim.x * blockDim.y;
int block_offset = blockIdx.x * num_threads_in_a_block;
int num_threads_in_a_row = num_threads_in_a_block * gridDim.x;
int row_offset = num_threads_in_a_row * blockIdx.y;
int grid_id = thread_id + row_offset + block_offset;
printf("blockIdx.x: %d, blockIdx.y: %d, threadIdx.x: %d, grid ID: %d, - data : %d \n",
blockIdx.x, blockIdx.y, thread_id, grid_id, data[grid_id]);
}
/*
int main()
{
int array_size = 16;
int array_byte_size = sizeof(int) * array_size;
int h_data[] = { 23, 9, 4, 53, 65, 12, 1, 33, 87, 45, 23, 12, 342, 56, 44, 99 };
int* d_data;
cudaMalloc((void**)&d_data, array_byte_size);
cudaMemcpy(d_data, h_data, array_byte_size, cudaMemcpyHostToDevice);
dim3 block(2, 2);
dim3 grid(2, 2);
unique_grid_id_calculation_2d_2d<<<grid, block>>>(d_data);
cudaDeviceSynchronize();
cudaDeviceReset();
return 0;
}
*/
|
code for sm_80
Function : _Z32unique_grid_id_calculation_2d_2dPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002200 */
/*0020*/ ULDC.64 UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fe200078e00ff */
/*0040*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe2000f8e023f */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ IADD3 R1, R1, -0x18, RZ ; /* 0xffffffe801017810 */
/* 0x000fc60007ffe0ff */
/*0070*/ S2R R12, SR_CTAID.X ; /* 0x00000000000c7919 */
/* 0x000e680000002500 */
/*0080*/ S2R R13, SR_CTAID.Y ; /* 0x00000000000d7919 */
/* 0x000e620000002600 */
/*0090*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fe400078e0203 */
/*00a0*/ IMAD R3, R13, c[0x0][0xc], R12 ; /* 0x000003000d037a24 */
/* 0x002fc800078e020c */
/*00b0*/ IMAD R3, R3, UR4, R2 ; /* 0x0000000403037c24 */
/* 0x000fe2000f8e0202 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00d0*/ IMAD.WIDE R8, R3, R8, c[0x0][0x160] ; /* 0x0000580003087625 */
/* 0x000fcc00078e0208 */
/*00e0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0110*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0120*/ STL.64 [R1], R12 ; /* 0x0000000c01007387 */
/* 0x0001e20000100a00 */
/*0130*/ LDC.64 R10, c[0x4][R0] ; /* 0x01000000000a7b82 */
/* 0x0000620000000a00 */
/*0140*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*0150*/ STL.64 [R1+0x8], R2 ; /* 0x0000080201007387 */
/* 0x0001e20000100a00 */
/*0160*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fc600000e06ff */
/*0170*/ STL [R1+0x10], R8 ; /* 0x0000100801007387 */
/* 0x0041e80000100800 */
/*0180*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x003fe40000000000 */
/*0190*/ MOV R9, 0x200 ; /* 0x0000020000097802 */
/* 0x000fe40000000f00 */
/*01a0*/ MOV R20, 0x180 ; /* 0x0000018000147802 */
/* 0x000fe40000000f00 */
/*01b0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*01c0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*01d0*/ IADD3 R20, P0, P1, -R20, R9, R2 ; /* 0x0000000914147210 */
/* 0x000fc8000791e102 */
/*01e0*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*01f0*/ CALL.ABS.NOINC R10 ; /* 0x000000000a007343 */
/* 0x000fea0003c00000 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include<stdio.h>
__global__ void unique_grid_id_calculation_2d_2d(int* data)
{
int thread_id = blockDim.x * threadIdx.y + threadIdx.x;
int num_threads_in_a_block = blockDim.x * blockDim.y;
int block_offset = blockIdx.x * num_threads_in_a_block;
int num_threads_in_a_row = num_threads_in_a_block * gridDim.x;
int row_offset = num_threads_in_a_row * blockIdx.y;
int grid_id = thread_id + row_offset + block_offset;
printf("blockIdx.x: %d, blockIdx.y: %d, threadIdx.x: %d, grid ID: %d, - data : %d \n",
blockIdx.x, blockIdx.y, thread_id, grid_id, data[grid_id]);
}
/*
int main()
{
int array_size = 16;
int array_byte_size = sizeof(int) * array_size;
int h_data[] = { 23, 9, 4, 53, 65, 12, 1, 33, 87, 45, 23, 12, 342, 56, 44, 99 };
int* d_data;
cudaMalloc((void**)&d_data, array_byte_size);
cudaMemcpy(d_data, h_data, array_byte_size, cudaMemcpyHostToDevice);
dim3 block(2, 2);
dim3 grid(2, 2);
unique_grid_id_calculation_2d_2d<<<grid, block>>>(d_data);
cudaDeviceSynchronize();
cudaDeviceReset();
return 0;
}
*/
|
.file "tmpxft_001a8622_00000000-6_7.unique_grid_id_calculation_2d_thread_block.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z52__device_stub__Z32unique_grid_id_calculation_2d_2dPiPi
.type _Z52__device_stub__Z32unique_grid_id_calculation_2d_2dPiPi, @function
_Z52__device_stub__Z32unique_grid_id_calculation_2d_2dPiPi:
.LFB2081:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z32unique_grid_id_calculation_2d_2dPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z52__device_stub__Z32unique_grid_id_calculation_2d_2dPiPi, .-_Z52__device_stub__Z32unique_grid_id_calculation_2d_2dPiPi
.globl _Z32unique_grid_id_calculation_2d_2dPi
.type _Z32unique_grid_id_calculation_2d_2dPi, @function
_Z32unique_grid_id_calculation_2d_2dPi:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z32unique_grid_id_calculation_2d_2dPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z32unique_grid_id_calculation_2d_2dPi, .-_Z32unique_grid_id_calculation_2d_2dPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z32unique_grid_id_calculation_2d_2dPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z32unique_grid_id_calculation_2d_2dPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include<stdio.h>
__global__ void unique_grid_id_calculation_2d_2d(int* data)
{
int thread_id = blockDim.x * threadIdx.y + threadIdx.x;
int num_threads_in_a_block = blockDim.x * blockDim.y;
int block_offset = blockIdx.x * num_threads_in_a_block;
int num_threads_in_a_row = num_threads_in_a_block * gridDim.x;
int row_offset = num_threads_in_a_row * blockIdx.y;
int grid_id = thread_id + row_offset + block_offset;
printf("blockIdx.x: %d, blockIdx.y: %d, threadIdx.x: %d, grid ID: %d, - data : %d \n",
blockIdx.x, blockIdx.y, thread_id, grid_id, data[grid_id]);
}
/*
int main()
{
int array_size = 16;
int array_byte_size = sizeof(int) * array_size;
int h_data[] = { 23, 9, 4, 53, 65, 12, 1, 33, 87, 45, 23, 12, 342, 56, 44, 99 };
int* d_data;
cudaMalloc((void**)&d_data, array_byte_size);
cudaMemcpy(d_data, h_data, array_byte_size, cudaMemcpyHostToDevice);
dim3 block(2, 2);
dim3 grid(2, 2);
unique_grid_id_calculation_2d_2d<<<grid, block>>>(d_data);
cudaDeviceSynchronize();
cudaDeviceReset();
return 0;
}
*/
|
#include "hip/hip_runtime.h"
#include<stdio.h>
__global__ void unique_grid_id_calculation_2d_2d(int* data)
{
int thread_id = blockDim.x * threadIdx.y + threadIdx.x;
int num_threads_in_a_block = blockDim.x * blockDim.y;
int block_offset = blockIdx.x * num_threads_in_a_block;
int num_threads_in_a_row = num_threads_in_a_block * gridDim.x;
int row_offset = num_threads_in_a_row * blockIdx.y;
int grid_id = thread_id + row_offset + block_offset;
printf("blockIdx.x: %d, blockIdx.y: %d, threadIdx.x: %d, grid ID: %d, - data : %d \n",
blockIdx.x, blockIdx.y, thread_id, grid_id, data[grid_id]);
}
/*
int main()
{
int array_size = 16;
int array_byte_size = sizeof(int) * array_size;
int h_data[] = { 23, 9, 4, 53, 65, 12, 1, 33, 87, 45, 23, 12, 342, 56, 44, 99 };
int* d_data;
cudaMalloc((void**)&d_data, array_byte_size);
cudaMemcpy(d_data, h_data, array_byte_size, cudaMemcpyHostToDevice);
dim3 block(2, 2);
dim3 grid(2, 2);
unique_grid_id_calculation_2d_2d<<<grid, block>>>(d_data);
cudaDeviceSynchronize();
cudaDeviceReset();
return 0;
}
*/
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include "hip/hip_runtime.h"
#include<stdio.h>
__global__ void unique_grid_id_calculation_2d_2d(int* data)
{
int thread_id = blockDim.x * threadIdx.y + threadIdx.x;
int num_threads_in_a_block = blockDim.x * blockDim.y;
int block_offset = blockIdx.x * num_threads_in_a_block;
int num_threads_in_a_row = num_threads_in_a_block * gridDim.x;
int row_offset = num_threads_in_a_row * blockIdx.y;
int grid_id = thread_id + row_offset + block_offset;
printf("blockIdx.x: %d, blockIdx.y: %d, threadIdx.x: %d, grid ID: %d, - data : %d \n",
blockIdx.x, blockIdx.y, thread_id, grid_id, data[grid_id]);
}
/*
int main()
{
int array_size = 16;
int array_byte_size = sizeof(int) * array_size;
int h_data[] = { 23, 9, 4, 53, 65, 12, 1, 33, 87, 45, 23, 12, 342, 56, 44, 99 };
int* d_data;
cudaMalloc((void**)&d_data, array_byte_size);
cudaMemcpy(d_data, h_data, array_byte_size, cudaMemcpyHostToDevice);
dim3 block(2, 2);
dim3 grid(2, 2);
unique_grid_id_calculation_2d_2d<<<grid, block>>>(d_data);
cudaDeviceSynchronize();
cudaDeviceReset();
return 0;
}
*/
|
.text
.file "7.unique_grid_id_calculation_2d_thread_block.hip"
.globl _Z47__device_stub__unique_grid_id_calculation_2d_2dPi # -- Begin function _Z47__device_stub__unique_grid_id_calculation_2d_2dPi
.p2align 4, 0x90
.type _Z47__device_stub__unique_grid_id_calculation_2d_2dPi,@function
_Z47__device_stub__unique_grid_id_calculation_2d_2dPi: # @_Z47__device_stub__unique_grid_id_calculation_2d_2dPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z32unique_grid_id_calculation_2d_2dPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z47__device_stub__unique_grid_id_calculation_2d_2dPi, .Lfunc_end0-_Z47__device_stub__unique_grid_id_calculation_2d_2dPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z32unique_grid_id_calculation_2d_2dPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z32unique_grid_id_calculation_2d_2dPi,@object # @_Z32unique_grid_id_calculation_2d_2dPi
.section .rodata,"a",@progbits
.globl _Z32unique_grid_id_calculation_2d_2dPi
.p2align 3, 0x0
_Z32unique_grid_id_calculation_2d_2dPi:
.quad _Z47__device_stub__unique_grid_id_calculation_2d_2dPi
.size _Z32unique_grid_id_calculation_2d_2dPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z32unique_grid_id_calculation_2d_2dPi"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z47__device_stub__unique_grid_id_calculation_2d_2dPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z32unique_grid_id_calculation_2d_2dPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_001a8622_00000000-6_7.unique_grid_id_calculation_2d_thread_block.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z52__device_stub__Z32unique_grid_id_calculation_2d_2dPiPi
.type _Z52__device_stub__Z32unique_grid_id_calculation_2d_2dPiPi, @function
_Z52__device_stub__Z32unique_grid_id_calculation_2d_2dPiPi:
.LFB2081:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z32unique_grid_id_calculation_2d_2dPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z52__device_stub__Z32unique_grid_id_calculation_2d_2dPiPi, .-_Z52__device_stub__Z32unique_grid_id_calculation_2d_2dPiPi
.globl _Z32unique_grid_id_calculation_2d_2dPi
.type _Z32unique_grid_id_calculation_2d_2dPi, @function
_Z32unique_grid_id_calculation_2d_2dPi:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z32unique_grid_id_calculation_2d_2dPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z32unique_grid_id_calculation_2d_2dPi, .-_Z32unique_grid_id_calculation_2d_2dPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z32unique_grid_id_calculation_2d_2dPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z32unique_grid_id_calculation_2d_2dPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "7.unique_grid_id_calculation_2d_thread_block.hip"
.globl _Z47__device_stub__unique_grid_id_calculation_2d_2dPi # -- Begin function _Z47__device_stub__unique_grid_id_calculation_2d_2dPi
.p2align 4, 0x90
.type _Z47__device_stub__unique_grid_id_calculation_2d_2dPi,@function
_Z47__device_stub__unique_grid_id_calculation_2d_2dPi: # @_Z47__device_stub__unique_grid_id_calculation_2d_2dPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z32unique_grid_id_calculation_2d_2dPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z47__device_stub__unique_grid_id_calculation_2d_2dPi, .Lfunc_end0-_Z47__device_stub__unique_grid_id_calculation_2d_2dPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z32unique_grid_id_calculation_2d_2dPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z32unique_grid_id_calculation_2d_2dPi,@object # @_Z32unique_grid_id_calculation_2d_2dPi
.section .rodata,"a",@progbits
.globl _Z32unique_grid_id_calculation_2d_2dPi
.p2align 3, 0x0
_Z32unique_grid_id_calculation_2d_2dPi:
.quad _Z47__device_stub__unique_grid_id_calculation_2d_2dPi
.size _Z32unique_grid_id_calculation_2d_2dPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z32unique_grid_id_calculation_2d_2dPi"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z47__device_stub__unique_grid_id_calculation_2d_2dPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z32unique_grid_id_calculation_2d_2dPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <chrono>
#include <cmath>
#include <string>
#include <iostream>
using namespace std::chrono;
using namespace std;
__global__ void addMatOnDevice2D(float *in1, float *in2, float *out, int nx, int ny)
{
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int iy = threadIdx.y + blockIdx.y * blockDim.y;
if (ix < nx && iy < ny)
{
int i = iy * nx + ix;
out[i] = in1[i] + in2[i];
}
}
__global__ void addMatOnDevice1D(float *in1, float *in2, float *out, int nx, int ny)
{
int ix = threadIdx.x + blockIdx.x * blockDim.x;
if (ix < nx)
{
for (int iy = 0; iy < ny; iy++)
{
int idx = iy * nx + ix;
out[idx] = in1[idx] + in2[idx];
}
}
}
__global__ void addMatOnDeviceMix(float *in1, float *in2, float *out, int nx, int ny)
{
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int iy = blockIdx.y;
if (ix < nx)
{
int idx = iy * nx + ix;
out[idx] = in1[idx] + in2[idx];
}
}
void addMatOnHost(float *in1, float *in2, float *out,
int nx, int ny)
{
for (int i = 0; i < ny; i++)
for (int j = 0; j < nx; j++){
int idx = i * nx + j;
out[idx] = in1[idx] + in2[idx];
}
}
void printMatrix(float *matrix, int nx, int ny)
{
printf("\n");
for (int i = 0; i < ny; i++){
for (int j = 0; j < nx; j++){
int idx = i * ny + j;
printf("%f ", matrix[idx]);
}
printf("\n");
}
}
void calcTimeOnDevice(float *in1, float *in2, float *out, int nx, int ny, dim3 blockSize, dim3 gridSize, int typeDevice)
{
int size = nx * ny * sizeof(float);
// Allocate vector to device memory
float *d_in1, *d_in2, *d_out;
cudaMalloc(&d_in1, size);
cudaMalloc(&d_in2, size);
cudaMalloc(&d_out, size);
// Copy inputs to device
cudaMemcpy(d_in1, in1, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_in2, in2, size, cudaMemcpyHostToDevice);
auto start_device = high_resolution_clock::now();
string deviceName = "";
if (typeDevice == 1){
deviceName = "addMatOnDevice2D";
addMatOnDevice2D<<<gridSize, blockSize>>>(d_in1, d_in2, d_out, nx, ny);
}else if (typeDevice == 2){
deviceName = "addMatOnDevice1D";
addMatOnDevice1D<<<gridSize, blockSize>>>(d_in1, d_in2, d_out, nx, ny);
}else if (typeDevice == 3){
deviceName = "addMatOnDevice2DNotMix";
addMatOnDevice2D<<<gridSize, blockSize>>>(d_in1, d_in2, d_out, nx, ny);
}else {
deviceName = "addMatOnDeviceMix";
addMatOnDeviceMix<<<gridSize, blockSize>>>(d_in1, d_in2, d_out, nx, ny);
}
cudaDeviceSynchronize();
cudaGetLastError();
cudaMemcpy(out, d_out, size, cudaMemcpyDeviceToHost);
auto stop_device = high_resolution_clock::now();
auto duration_device = duration_cast<microseconds>(stop_device - start_device);
auto duration = duration_device.count();
printf("%s|%d x %d\t|%d x %d\t|%d ms\t\n", deviceName.c_str(), blockSize.x, blockSize.y, gridSize.x, gridSize.y, duration);
// Cleanup
cudaFree(d_in1);
cudaFree(d_in2);
cudaFree(d_out);
}
int main()
{
int nx, ny; // Số cột và số dòng
float *in1, *in2; // input matrix
float *out; // output vector
nx = pow(2, 13) + 1;
ny = pow(2, 13) + 1;
int size = nx * ny * sizeof(float);
in1 = (float *)malloc(size);
in2 = (float *)malloc(size);
out = (float *)malloc(size);
// Setup input values
srand(time(0));
for (int i = 0; i < ny; i++){
for (int j = 0; j < nx; j++){
int idx = i * ny + j;
in1[idx] = static_cast<float>(rand()) / static_cast<float>(RAND_MAX);
in2[idx] = static_cast<float>(rand()) / static_cast<float>(RAND_MAX);
}
}
auto start_host = high_resolution_clock::now();
addMatOnHost(in1, in2, out, nx, ny);
auto stop_host = high_resolution_clock::now();
auto duration_host = duration_cast<microseconds>(stop_host - start_host);
printf("Function\t|Block size\t|Grid size\t|Time (ms)\n");
printf("addMatOnHost\t|\t\t|\t\t|%d\n", duration_host.count());
/********************************
addMatOnDevice2D
*********************************/
int typeDevice = 1;
dim3 blockSize(32, 32);
dim3 gridSize(257, 257);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(16, 32);
gridSize = dim3(513, 257);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(32, 16);
gridSize = dim3(257, 513);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(16, 16);
gridSize = dim3(513, 513);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
/********************************
addMatOnDevice1D
*********************************/
typeDevice = 2;
blockSize = dim3(32, 1);
gridSize = dim3(257, 1);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(64, 1);
gridSize = dim3(129, 1);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(128, 1);
gridSize = dim3(65, 1);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
/********************************
addMatOnDevice2DNotMix
*********************************/
typeDevice = 3;
blockSize = dim3(32, 1);
gridSize = dim3(257, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(64, 1);
gridSize = dim3(129, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(128, 1);
gridSize = dim3(65, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(256, 1);
gridSize = dim3(33, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(512, 1);
gridSize = dim3(17, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(1024, 1);
gridSize = dim3(9, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(2048, 1);
gridSize = dim3(5, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
/********************************
addMatOnDeviceMix
*********************************/
typeDevice = 4;
blockSize = dim3(32, 1);
gridSize = dim3(257, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(64, 1);
gridSize = dim3(129, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(128, 1);
gridSize = dim3(65, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(256, 1);
gridSize = dim3(33, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(512, 1);
gridSize = dim3(17, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(1024, 1);
gridSize = dim3(9, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(2048, 1);
gridSize = dim3(5, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
free(in1);
free(in2);
free(out);
return 0;
}
|
.file "tmpxft_0007f802_00000000-6_calcTimeOnDevice.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3778:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3778:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12addMatOnHostPfS_S_ii
.type _Z12addMatOnHostPfS_S_ii, @function
_Z12addMatOnHostPfS_S_ii:
.LFB3768:
.cfi_startproc
endbr64
testl %r8d, %r8d
jle .L11
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdx, %r9
movl $0, %r11d
movl $0, %r10d
movslq %ecx, %rbx
jmp .L5
.L7:
movslq %r11d, %rdx
leaq 0(,%rdx,4), %rax
addq %rbx, %rdx
salq $2, %rdx
.L6:
movss (%rdi,%rax), %xmm0
addss (%rsi,%rax), %xmm0
movss %xmm0, (%r9,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L6
.L8:
addl $1, %r10d
addl %ecx, %r11d
cmpl %r10d, %r8d
je .L3
.L5:
testl %ecx, %ecx
jg .L7
jmp .L8
.L3:
popq %rbx
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore 3
ret
.cfi_endproc
.LFE3768:
.size _Z12addMatOnHostPfS_S_ii, .-_Z12addMatOnHostPfS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n"
.LC1:
.string "%f "
.text
.globl _Z11printMatrixPfii
.type _Z11printMatrixPfii, @function
_Z11printMatrixPfii:
.LFB3769:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, %ebx
movl %esi, 12(%rsp)
movl %edx, %r15d
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %r15d, %r15d
jle .L14
movl $0, %r14d
movl $0, %r13d
movslq %ebx, %rax
movq %rax, 24(%rsp)
leaq .LC1(%rip), %r12
jmp .L16
.L18:
movslq %r14d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rdx
addq %rdx, %rax
leaq (%rcx,%rax,4), %rbp
.L17:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L17
.L19:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addl %r15d, %r14d
cmpl %r13d, %r15d
je .L14
.L16:
cmpl $0, 12(%rsp)
jg .L18
jmp .L19
.L14:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3769:
.size _Z11printMatrixPfii, .-_Z11printMatrixPfii
.globl _Z42__device_stub__Z16addMatOnDevice2DPfS_S_iiPfS_S_ii
.type _Z42__device_stub__Z16addMatOnDevice2DPfS_S_iiPfS_S_ii, @function
_Z42__device_stub__Z16addMatOnDevice2DPfS_S_iiPfS_S_ii:
.LFB3800:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L26
.L22:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16addMatOnDevice2DPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L22
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3800:
.size _Z42__device_stub__Z16addMatOnDevice2DPfS_S_iiPfS_S_ii, .-_Z42__device_stub__Z16addMatOnDevice2DPfS_S_iiPfS_S_ii
.globl _Z16addMatOnDevice2DPfS_S_ii
.type _Z16addMatOnDevice2DPfS_S_ii, @function
_Z16addMatOnDevice2DPfS_S_ii:
.LFB3801:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z16addMatOnDevice2DPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3801:
.size _Z16addMatOnDevice2DPfS_S_ii, .-_Z16addMatOnDevice2DPfS_S_ii
.globl _Z42__device_stub__Z16addMatOnDevice1DPfS_S_iiPfS_S_ii
.type _Z42__device_stub__Z16addMatOnDevice1DPfS_S_iiPfS_S_ii, @function
_Z42__device_stub__Z16addMatOnDevice1DPfS_S_iiPfS_S_ii:
.LFB3802:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L34
.L30:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16addMatOnDevice1DPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L30
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3802:
.size _Z42__device_stub__Z16addMatOnDevice1DPfS_S_iiPfS_S_ii, .-_Z42__device_stub__Z16addMatOnDevice1DPfS_S_iiPfS_S_ii
.globl _Z16addMatOnDevice1DPfS_S_ii
.type _Z16addMatOnDevice1DPfS_S_ii, @function
_Z16addMatOnDevice1DPfS_S_ii:
.LFB3803:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z16addMatOnDevice1DPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3803:
.size _Z16addMatOnDevice1DPfS_S_ii, .-_Z16addMatOnDevice1DPfS_S_ii
.globl _Z43__device_stub__Z17addMatOnDeviceMixPfS_S_iiPfS_S_ii
.type _Z43__device_stub__Z17addMatOnDeviceMixPfS_S_iiPfS_S_ii, @function
_Z43__device_stub__Z17addMatOnDeviceMixPfS_S_iiPfS_S_ii:
.LFB3804:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L42
.L38:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L43
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17addMatOnDeviceMixPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L38
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3804:
.size _Z43__device_stub__Z17addMatOnDeviceMixPfS_S_iiPfS_S_ii, .-_Z43__device_stub__Z17addMatOnDeviceMixPfS_S_iiPfS_S_ii
.globl _Z17addMatOnDeviceMixPfS_S_ii
.type _Z17addMatOnDeviceMixPfS_S_ii, @function
_Z17addMatOnDeviceMixPfS_S_ii:
.LFB3805:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z17addMatOnDeviceMixPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3805:
.size _Z17addMatOnDeviceMixPfS_S_ii, .-_Z17addMatOnDeviceMixPfS_S_ii
.section .rodata.str1.1
.LC2:
.string "addMatOnDevice2D"
.LC3:
.string "addMatOnDevice1D"
.LC4:
.string "addMatOnDevice2DNotMix"
.LC5:
.string "addMatOnDeviceMix"
.LC6:
.string "%s|%d x %d\t|%d x %d\t|%d ms\t\n"
.text
.globl _Z16calcTimeOnDevicePfS_S_ii4dim3S0_i
.type _Z16calcTimeOnDevicePfS_S_ii4dim3S0_i, @function
_Z16calcTimeOnDevicePfS_S_ii4dim3S0_i:
.LFB3770:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3770
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $104, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %rdi, %r15
movq %rsi, %r14
movq %rdx, -144(%rbp)
movl %ecx, %r12d
movl %r8d, %r13d
movl %r9d, -132(%rbp)
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
movl %ecx, %ebx
imull %r8d, %ebx
sall $2, %ebx
movslq %ebx, %rbx
leaq -120(%rbp), %rdi
movq %rbx, %rsi
.LEHB0:
call cudaMalloc@PLT
leaq -112(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq -104(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq -120(%rbp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq -112(%rbp), %rdi
call cudaMemcpy@PLT
.LEHE0:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r14
leaq -80(%rbp), %rax
movq %rax, -96(%rbp)
movq $0, -88(%rbp)
movb $0, -80(%rbp)
cmpl $1, -132(%rbp)
je .L57
cmpl $2, -132(%rbp)
je .L58
cmpl $3, -132(%rbp)
je .L59
leaq -96(%rbp), %rdi
movl $17, %r8d
leaq .LC5(%rip), %rcx
movl $0, %edx
movl $0, %esi
.LEHB1:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm@PLT
jmp .L60
.L57:
leaq -96(%rbp), %rdi
movl $16, %r8d
leaq .LC2(%rip), %rcx
movl $0, %edx
movl $0, %esi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm@PLT
movl 24(%rbp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rbp), %rdx
movq 32(%rbp), %rdi
movl 40(%rbp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L48
movl %r13d, %r8d
movl %r12d, %ecx
movq -104(%rbp), %rdx
movq -112(%rbp), %rsi
movq -120(%rbp), %rdi
call _Z42__device_stub__Z16addMatOnDevice2DPfS_S_iiPfS_S_ii
jmp .L48
.L58:
leaq -96(%rbp), %rdi
movl $16, %r8d
leaq .LC3(%rip), %rcx
movl $0, %edx
movl $0, %esi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm@PLT
movl 24(%rbp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rbp), %rdx
movq 32(%rbp), %rdi
movl 40(%rbp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L48
movl %r13d, %r8d
movl %r12d, %ecx
movq -104(%rbp), %rdx
movq -112(%rbp), %rsi
movq -120(%rbp), %rdi
call _Z42__device_stub__Z16addMatOnDevice1DPfS_S_iiPfS_S_ii
jmp .L48
.L59:
leaq -96(%rbp), %rdi
movl $22, %r8d
leaq .LC4(%rip), %rcx
movl $0, %edx
movl $0, %esi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm@PLT
movl 24(%rbp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rbp), %rdx
movq 32(%rbp), %rdi
movl 40(%rbp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L48
movl %r13d, %r8d
movl %r12d, %ecx
movq -104(%rbp), %rdx
movq -112(%rbp), %rsi
movq -120(%rbp), %rdi
call _Z42__device_stub__Z16addMatOnDevice2DPfS_S_iiPfS_S_ii
jmp .L48
.L60:
movl 24(%rbp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rbp), %rdx
movq 32(%rbp), %rdi
movl 40(%rbp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L61
.L48:
call cudaDeviceSynchronize@PLT
jmp .L62
.L61:
movl %r13d, %r8d
movl %r12d, %ecx
movq -104(%rbp), %rdx
movq -112(%rbp), %rsi
movq -120(%rbp), %rdi
call _Z43__device_stub__Z17addMatOnDeviceMixPfS_S_iiPfS_S_ii
jmp .L48
.L62:
call cudaGetLastError@PLT
movl $2, %ecx
movq %rbx, %rdx
movq -104(%rbp), %rsi
movq -144(%rbp), %rdi
call cudaMemcpy@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %r14, %rax
movq %rax, %rcx
movabsq $2361183241434822607, %rdx
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
pushq %rdx
movl 36(%rbp), %eax
pushq %rax
movl 32(%rbp), %r9d
movl 20(%rbp), %r8d
movl 16(%rbp), %ecx
movq -96(%rbp), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
.cfi_escape 0x2e,0x10
call __printf_chk@PLT
addq $16, %rsp
movq -120(%rbp), %rdi
.cfi_escape 0x2e,0
call cudaFree@PLT
movq -112(%rbp), %rdi
call cudaFree@PLT
movq -104(%rbp), %rdi
call cudaFree@PLT
.LEHE1:
movq -96(%rbp), %rdi
leaq -80(%rbp), %rax
cmpq %rax, %rdi
je .L46
movq -80(%rbp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L46:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L63
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L55:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq -96(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L53
call __stack_chk_fail@PLT
.L53:
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L63:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3770:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3770:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3770-.LLSDACSB3770
.LLSDACSB3770:
.uleb128 .LEHB0-.LFB3770
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3770
.uleb128 .LEHE1-.LEHB1
.uleb128 .L55-.LFB3770
.uleb128 0
.uleb128 .LEHB2-.LFB3770
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE3770:
.text
.size _Z16calcTimeOnDevicePfS_S_ii4dim3S0_i, .-_Z16calcTimeOnDevicePfS_S_ii4dim3S0_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "Function\t|Block size\t|Grid size\t|Time (ms)\n"
.section .rodata.str1.1
.LC9:
.string "addMatOnHost\t|\t\t|\t\t|%d\n"
.text
.globl main
.type main, @function
main:
.LFB3774:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl $268500996, %edi
call malloc@PLT
movq %rax, %r13
movl $268500996, %edi
call malloc@PLT
movq %rax, %r14
movl $268500996, %edi
call malloc@PLT
movq %rax, %r15
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movq %r13, %rbp
movq %r14, %r12
leaq 268500996(%r13), %rax
movq %rax, 8(%rsp)
.L65:
movl $0, %ebx
.L66:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC7(%rip), %xmm0
movss %xmm0, 0(%rbp,%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC7(%rip), %xmm0
movss %xmm0, (%r12,%rbx)
addq $4, %rbx
cmpq $32772, %rbx
jne .L66
addq $32772, %rbp
addq $32772, %r12
movq 8(%rsp), %rax
cmpq %rax, %rbp
jne .L65
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
movl $8193, %r8d
movl $8193, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq %r13, %rdi
call _Z12addMatOnHostPfS_S_ii
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %rbx, %rax
movq %rax, %rcx
movabsq $2361183241434822607, %rdx
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
movq %rdx, %rbx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $32, 24(%rsp)
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $257, 36(%rsp)
movl $257, 40(%rsp)
movl $1, 44(%rsp)
subq $32, %rsp
.cfi_def_cfa_offset 144
movq 68(%rsp), %rax
movq %rax, 16(%rsp)
movl $1, 24(%rsp)
movq 56(%rsp), %rax
movq %rax, (%rsp)
movl $1, 8(%rsp)
movl $1, %r9d
movl $8193, %r8d
movl $8193, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq %r13, %rdi
call _Z16calcTimeOnDevicePfS_S_ii4dim3S0_i
movl $16, 56(%rsp)
movl $513, 68(%rsp)
movq 68(%rsp), %rax
movq %rax, 16(%rsp)
movl 76(%rsp), %eax
movl %eax, 24(%rsp)
movq 56(%rsp), %rax
movq %rax, (%rsp)
movl 64(%rsp), %eax
movl %eax, 8(%rsp)
movl $1, %r9d
movl $8193, %r8d
movl $8193, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq %r13, %rdi
call _Z16calcTimeOnDevicePfS_S_ii4dim3S0_i
movl $32, 56(%rsp)
movl $16, 60(%rsp)
movl $257, 68(%rsp)
movl $513, 72(%rsp)
movq 68(%rsp), %rax
movq %rax, 16(%rsp)
movl 76(%rsp), %eax
movl %eax, 24(%rsp)
movq 56(%rsp), %rax
movq %rax, (%rsp)
movl 64(%rsp), %eax
movl %eax, 8(%rsp)
movl $1, %r9d
movl $8193, %r8d
movl $8193, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq %r13, %rdi
call _Z16calcTimeOnDevicePfS_S_ii4dim3S0_i
movl $16, 56(%rsp)
movl $513, 68(%rsp)
movq 68(%rsp), %rax
movq %rax, 16(%rsp)
movl 76(%rsp), %eax
movl %eax, 24(%rsp)
movq 56(%rsp), %rax
movq %rax, (%rsp)
movl 64(%rsp), %eax
movl %eax, 8(%rsp)
movl $1, %r9d
movl $8193, %r8d
movl $8193, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq %r13, %rdi
call _Z16calcTimeOnDevicePfS_S_ii4dim3S0_i
movl $32, 56(%rsp)
movl $1, 60(%rsp)
movl $257, 68(%rsp)
movl $1, 72(%rsp)
movq 68(%rsp), %rax
movq %rax, 16(%rsp)
movl 76(%rsp), %eax
movl %eax, 24(%rsp)
movq 56(%rsp), %rax
movq %rax, (%rsp)
movl 64(%rsp), %eax
movl %eax, 8(%rsp)
movl $2, %r9d
movl $8193, %r8d
movl $8193, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq %r13, %rdi
call _Z16calcTimeOnDevicePfS_S_ii4dim3S0_i
movl $64, 56(%rsp)
movl $129, 68(%rsp)
movq 68(%rsp), %rax
movq %rax, 16(%rsp)
movl 76(%rsp), %eax
movl %eax, 24(%rsp)
movq 56(%rsp), %rax
movq %rax, (%rsp)
movl 64(%rsp), %eax
movl %eax, 8(%rsp)
movl $2, %r9d
movl $8193, %r8d
movl $8193, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq %r13, %rdi
call _Z16calcTimeOnDevicePfS_S_ii4dim3S0_i
movl $128, 56(%rsp)
movl $65, 68(%rsp)
movq 68(%rsp), %rax
movq %rax, 16(%rsp)
movl 76(%rsp), %eax
movl %eax, 24(%rsp)
movq 56(%rsp), %rax
movq %rax, (%rsp)
movl 64(%rsp), %eax
movl %eax, 8(%rsp)
movl $2, %r9d
movl $8193, %r8d
movl $8193, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq %r13, %rdi
call _Z16calcTimeOnDevicePfS_S_ii4dim3S0_i
movl $32, 56(%rsp)
movl $257, 68(%rsp)
movl $8193, 72(%rsp)
movq 68(%rsp), %rax
movq %rax, 16(%rsp)
movl 76(%rsp), %eax
movl %eax, 24(%rsp)
movq 56(%rsp), %rax
movq %rax, (%rsp)
movl 64(%rsp), %eax
movl %eax, 8(%rsp)
movl $3, %r9d
movl $8193, %r8d
movl $8193, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq %r13, %rdi
call _Z16calcTimeOnDevicePfS_S_ii4dim3S0_i
movl $64, 56(%rsp)
movl $129, 68(%rsp)
movq 68(%rsp), %rax
movq %rax, 16(%rsp)
movl 76(%rsp), %eax
movl %eax, 24(%rsp)
movq 56(%rsp), %rax
movq %rax, (%rsp)
movl 64(%rsp), %eax
movl %eax, 8(%rsp)
movl $3, %r9d
movl $8193, %r8d
movl $8193, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq %r13, %rdi
call _Z16calcTimeOnDevicePfS_S_ii4dim3S0_i
movl $128, 56(%rsp)
movl $65, 68(%rsp)
movq 68(%rsp), %rax
movq %rax, 16(%rsp)
movl 76(%rsp), %eax
movl %eax, 24(%rsp)
movq 56(%rsp), %rax
movq %rax, (%rsp)
movl 64(%rsp), %eax
movl %eax, 8(%rsp)
movl $3, %r9d
movl $8193, %r8d
movl $8193, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq %r13, %rdi
call _Z16calcTimeOnDevicePfS_S_ii4dim3S0_i
movl $256, 56(%rsp)
movl $33, 68(%rsp)
movq 68(%rsp), %rax
movq %rax, 16(%rsp)
movl 76(%rsp), %eax
movl %eax, 24(%rsp)
movq 56(%rsp), %rax
movq %rax, (%rsp)
movl 64(%rsp), %eax
movl %eax, 8(%rsp)
movl $3, %r9d
movl $8193, %r8d
movl $8193, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq %r13, %rdi
call _Z16calcTimeOnDevicePfS_S_ii4dim3S0_i
movl $512, 56(%rsp)
movl $17, 68(%rsp)
movq 68(%rsp), %rax
movq %rax, 16(%rsp)
movl 76(%rsp), %eax
movl %eax, 24(%rsp)
movq 56(%rsp), %rax
movq %rax, (%rsp)
movl 64(%rsp), %eax
movl %eax, 8(%rsp)
movl $3, %r9d
movl $8193, %r8d
movl $8193, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq %r13, %rdi
call _Z16calcTimeOnDevicePfS_S_ii4dim3S0_i
movl $1024, 56(%rsp)
movl $9, 68(%rsp)
movq 68(%rsp), %rax
movq %rax, 16(%rsp)
movl 76(%rsp), %eax
movl %eax, 24(%rsp)
movq 56(%rsp), %rax
movq %rax, (%rsp)
movl 64(%rsp), %eax
movl %eax, 8(%rsp)
movl $3, %r9d
movl $8193, %r8d
movl $8193, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq %r13, %rdi
call _Z16calcTimeOnDevicePfS_S_ii4dim3S0_i
movl $2048, 56(%rsp)
movl $5, 68(%rsp)
movq 68(%rsp), %rax
movq %rax, 16(%rsp)
movl 76(%rsp), %eax
movl %eax, 24(%rsp)
movq 56(%rsp), %rax
movq %rax, (%rsp)
movl 64(%rsp), %eax
movl %eax, 8(%rsp)
movl $3, %r9d
movl $8193, %r8d
movl $8193, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq %r13, %rdi
call _Z16calcTimeOnDevicePfS_S_ii4dim3S0_i
movl $32, 56(%rsp)
movl $257, 68(%rsp)
movq 68(%rsp), %rax
movq %rax, 16(%rsp)
movl 76(%rsp), %eax
movl %eax, 24(%rsp)
movq 56(%rsp), %rax
movq %rax, (%rsp)
movl 64(%rsp), %eax
movl %eax, 8(%rsp)
movl $4, %r9d
movl $8193, %r8d
movl $8193, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq %r13, %rdi
call _Z16calcTimeOnDevicePfS_S_ii4dim3S0_i
movl $64, 56(%rsp)
movl $129, 68(%rsp)
movq 68(%rsp), %rax
movq %rax, 16(%rsp)
movl 76(%rsp), %eax
movl %eax, 24(%rsp)
movq 56(%rsp), %rax
movq %rax, (%rsp)
movl 64(%rsp), %eax
movl %eax, 8(%rsp)
movl $4, %r9d
movl $8193, %r8d
movl $8193, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq %r13, %rdi
call _Z16calcTimeOnDevicePfS_S_ii4dim3S0_i
movl $128, 56(%rsp)
movl $65, 68(%rsp)
movq 68(%rsp), %rax
movq %rax, 16(%rsp)
movl 76(%rsp), %eax
movl %eax, 24(%rsp)
movq 56(%rsp), %rax
movq %rax, (%rsp)
movl 64(%rsp), %eax
movl %eax, 8(%rsp)
movl $4, %r9d
movl $8193, %r8d
movl $8193, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq %r13, %rdi
call _Z16calcTimeOnDevicePfS_S_ii4dim3S0_i
movl $256, 56(%rsp)
movl $33, 68(%rsp)
movq 68(%rsp), %rax
movq %rax, 16(%rsp)
movl 76(%rsp), %eax
movl %eax, 24(%rsp)
movq 56(%rsp), %rax
movq %rax, (%rsp)
movl 64(%rsp), %eax
movl %eax, 8(%rsp)
movl $4, %r9d
movl $8193, %r8d
movl $8193, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq %r13, %rdi
call _Z16calcTimeOnDevicePfS_S_ii4dim3S0_i
movl $512, 56(%rsp)
movl $17, 68(%rsp)
movq 68(%rsp), %rax
movq %rax, 16(%rsp)
movl 76(%rsp), %eax
movl %eax, 24(%rsp)
movq 56(%rsp), %rax
movq %rax, (%rsp)
movl 64(%rsp), %eax
movl %eax, 8(%rsp)
movl $4, %r9d
movl $8193, %r8d
movl $8193, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq %r13, %rdi
call _Z16calcTimeOnDevicePfS_S_ii4dim3S0_i
movl $1024, 56(%rsp)
movl $9, 68(%rsp)
movq 68(%rsp), %rax
movq %rax, 16(%rsp)
movl 76(%rsp), %eax
movl %eax, 24(%rsp)
movq 56(%rsp), %rax
movq %rax, (%rsp)
movl 64(%rsp), %eax
movl %eax, 8(%rsp)
movl $4, %r9d
movl $8193, %r8d
movl $8193, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq %r13, %rdi
call _Z16calcTimeOnDevicePfS_S_ii4dim3S0_i
movl $2048, 56(%rsp)
movl $5, 68(%rsp)
movq 68(%rsp), %rax
movq %rax, 16(%rsp)
movl 76(%rsp), %eax
movl %eax, 24(%rsp)
movq 56(%rsp), %rax
movq %rax, (%rsp)
movl 64(%rsp), %eax
movl %eax, 8(%rsp)
movl $4, %r9d
movl $8193, %r8d
movl $8193, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq %r13, %rdi
call _Z16calcTimeOnDevicePfS_S_ii4dim3S0_i
addq $32, %rsp
.cfi_def_cfa_offset 112
movq %r13, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movl $0, %eax
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3774:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z17addMatOnDeviceMixPfS_S_ii"
.LC11:
.string "_Z16addMatOnDevice1DPfS_S_ii"
.LC12:
.string "_Z16addMatOnDevice2DPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3807:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z17addMatOnDeviceMixPfS_S_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z16addMatOnDevice1DPfS_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z16addMatOnDevice2DPfS_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3807:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC7:
.long 805306368
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
#include <stdlib.h>
#include <chrono>
#include <cmath>
#include <string>
#include <iostream>
using namespace std::chrono;
using namespace std;
__global__ void addMatOnDevice2D(float *in1, float *in2, float *out, int nx, int ny)
{
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int iy = threadIdx.y + blockIdx.y * blockDim.y;
if (ix < nx && iy < ny)
{
int i = iy * nx + ix;
out[i] = in1[i] + in2[i];
}
}
__global__ void addMatOnDevice1D(float *in1, float *in2, float *out, int nx, int ny)
{
int ix = threadIdx.x + blockIdx.x * blockDim.x;
if (ix < nx)
{
for (int iy = 0; iy < ny; iy++)
{
int idx = iy * nx + ix;
out[idx] = in1[idx] + in2[idx];
}
}
}
__global__ void addMatOnDeviceMix(float *in1, float *in2, float *out, int nx, int ny)
{
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int iy = blockIdx.y;
if (ix < nx)
{
int idx = iy * nx + ix;
out[idx] = in1[idx] + in2[idx];
}
}
void addMatOnHost(float *in1, float *in2, float *out,
int nx, int ny)
{
for (int i = 0; i < ny; i++)
for (int j = 0; j < nx; j++){
int idx = i * nx + j;
out[idx] = in1[idx] + in2[idx];
}
}
void printMatrix(float *matrix, int nx, int ny)
{
printf("\n");
for (int i = 0; i < ny; i++){
for (int j = 0; j < nx; j++){
int idx = i * ny + j;
printf("%f ", matrix[idx]);
}
printf("\n");
}
}
void calcTimeOnDevice(float *in1, float *in2, float *out, int nx, int ny, dim3 blockSize, dim3 gridSize, int typeDevice)
{
int size = nx * ny * sizeof(float);
// Allocate vector to device memory
float *d_in1, *d_in2, *d_out;
cudaMalloc(&d_in1, size);
cudaMalloc(&d_in2, size);
cudaMalloc(&d_out, size);
// Copy inputs to device
cudaMemcpy(d_in1, in1, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_in2, in2, size, cudaMemcpyHostToDevice);
auto start_device = high_resolution_clock::now();
string deviceName = "";
if (typeDevice == 1){
deviceName = "addMatOnDevice2D";
addMatOnDevice2D<<<gridSize, blockSize>>>(d_in1, d_in2, d_out, nx, ny);
}else if (typeDevice == 2){
deviceName = "addMatOnDevice1D";
addMatOnDevice1D<<<gridSize, blockSize>>>(d_in1, d_in2, d_out, nx, ny);
}else if (typeDevice == 3){
deviceName = "addMatOnDevice2DNotMix";
addMatOnDevice2D<<<gridSize, blockSize>>>(d_in1, d_in2, d_out, nx, ny);
}else {
deviceName = "addMatOnDeviceMix";
addMatOnDeviceMix<<<gridSize, blockSize>>>(d_in1, d_in2, d_out, nx, ny);
}
cudaDeviceSynchronize();
cudaGetLastError();
cudaMemcpy(out, d_out, size, cudaMemcpyDeviceToHost);
auto stop_device = high_resolution_clock::now();
auto duration_device = duration_cast<microseconds>(stop_device - start_device);
auto duration = duration_device.count();
printf("%s|%d x %d\t|%d x %d\t|%d ms\t\n", deviceName.c_str(), blockSize.x, blockSize.y, gridSize.x, gridSize.y, duration);
// Cleanup
cudaFree(d_in1);
cudaFree(d_in2);
cudaFree(d_out);
}
int main()
{
int nx, ny; // Số cột và số dòng
float *in1, *in2; // input matrix
float *out; // output vector
nx = pow(2, 13) + 1;
ny = pow(2, 13) + 1;
int size = nx * ny * sizeof(float);
in1 = (float *)malloc(size);
in2 = (float *)malloc(size);
out = (float *)malloc(size);
// Setup input values
srand(time(0));
for (int i = 0; i < ny; i++){
for (int j = 0; j < nx; j++){
int idx = i * ny + j;
in1[idx] = static_cast<float>(rand()) / static_cast<float>(RAND_MAX);
in2[idx] = static_cast<float>(rand()) / static_cast<float>(RAND_MAX);
}
}
auto start_host = high_resolution_clock::now();
addMatOnHost(in1, in2, out, nx, ny);
auto stop_host = high_resolution_clock::now();
auto duration_host = duration_cast<microseconds>(stop_host - start_host);
printf("Function\t|Block size\t|Grid size\t|Time (ms)\n");
printf("addMatOnHost\t|\t\t|\t\t|%d\n", duration_host.count());
/********************************
addMatOnDevice2D
*********************************/
int typeDevice = 1;
dim3 blockSize(32, 32);
dim3 gridSize(257, 257);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(16, 32);
gridSize = dim3(513, 257);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(32, 16);
gridSize = dim3(257, 513);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(16, 16);
gridSize = dim3(513, 513);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
/********************************
addMatOnDevice1D
*********************************/
typeDevice = 2;
blockSize = dim3(32, 1);
gridSize = dim3(257, 1);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(64, 1);
gridSize = dim3(129, 1);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(128, 1);
gridSize = dim3(65, 1);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
/********************************
addMatOnDevice2DNotMix
*********************************/
typeDevice = 3;
blockSize = dim3(32, 1);
gridSize = dim3(257, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(64, 1);
gridSize = dim3(129, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(128, 1);
gridSize = dim3(65, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(256, 1);
gridSize = dim3(33, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(512, 1);
gridSize = dim3(17, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(1024, 1);
gridSize = dim3(9, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(2048, 1);
gridSize = dim3(5, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
/********************************
addMatOnDeviceMix
*********************************/
typeDevice = 4;
blockSize = dim3(32, 1);
gridSize = dim3(257, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(64, 1);
gridSize = dim3(129, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(128, 1);
gridSize = dim3(65, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(256, 1);
gridSize = dim3(33, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(512, 1);
gridSize = dim3(17, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(1024, 1);
gridSize = dim3(9, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(2048, 1);
gridSize = dim3(5, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
free(in1);
free(in2);
free(out);
return 0;
}
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <chrono>
#include <cmath>
#include <string>
#include <iostream>
using namespace std::chrono;
using namespace std;
__global__ void addMatOnDevice2D(float *in1, float *in2, float *out, int nx, int ny)
{
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int iy = threadIdx.y + blockIdx.y * blockDim.y;
if (ix < nx && iy < ny)
{
int i = iy * nx + ix;
out[i] = in1[i] + in2[i];
}
}
__global__ void addMatOnDevice1D(float *in1, float *in2, float *out, int nx, int ny)
{
int ix = threadIdx.x + blockIdx.x * blockDim.x;
if (ix < nx)
{
for (int iy = 0; iy < ny; iy++)
{
int idx = iy * nx + ix;
out[idx] = in1[idx] + in2[idx];
}
}
}
__global__ void addMatOnDeviceMix(float *in1, float *in2, float *out, int nx, int ny)
{
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int iy = blockIdx.y;
if (ix < nx)
{
int idx = iy * nx + ix;
out[idx] = in1[idx] + in2[idx];
}
}
void addMatOnHost(float *in1, float *in2, float *out,
int nx, int ny)
{
for (int i = 0; i < ny; i++)
for (int j = 0; j < nx; j++){
int idx = i * nx + j;
out[idx] = in1[idx] + in2[idx];
}
}
void printMatrix(float *matrix, int nx, int ny)
{
printf("\n");
for (int i = 0; i < ny; i++){
for (int j = 0; j < nx; j++){
int idx = i * ny + j;
printf("%f ", matrix[idx]);
}
printf("\n");
}
}
void calcTimeOnDevice(float *in1, float *in2, float *out, int nx, int ny, dim3 blockSize, dim3 gridSize, int typeDevice)
{
int size = nx * ny * sizeof(float);
// Allocate vector to device memory
float *d_in1, *d_in2, *d_out;
hipMalloc(&d_in1, size);
hipMalloc(&d_in2, size);
hipMalloc(&d_out, size);
// Copy inputs to device
hipMemcpy(d_in1, in1, size, hipMemcpyHostToDevice);
hipMemcpy(d_in2, in2, size, hipMemcpyHostToDevice);
auto start_device = high_resolution_clock::now();
string deviceName = "";
if (typeDevice == 1){
deviceName = "addMatOnDevice2D";
addMatOnDevice2D<<<gridSize, blockSize>>>(d_in1, d_in2, d_out, nx, ny);
}else if (typeDevice == 2){
deviceName = "addMatOnDevice1D";
addMatOnDevice1D<<<gridSize, blockSize>>>(d_in1, d_in2, d_out, nx, ny);
}else if (typeDevice == 3){
deviceName = "addMatOnDevice2DNotMix";
addMatOnDevice2D<<<gridSize, blockSize>>>(d_in1, d_in2, d_out, nx, ny);
}else {
deviceName = "addMatOnDeviceMix";
addMatOnDeviceMix<<<gridSize, blockSize>>>(d_in1, d_in2, d_out, nx, ny);
}
hipDeviceSynchronize();
hipGetLastError();
hipMemcpy(out, d_out, size, hipMemcpyDeviceToHost);
auto stop_device = high_resolution_clock::now();
auto duration_device = duration_cast<microseconds>(stop_device - start_device);
auto duration = duration_device.count();
printf("%s|%d x %d\t|%d x %d\t|%d ms\t\n", deviceName.c_str(), blockSize.x, blockSize.y, gridSize.x, gridSize.y, duration);
// Cleanup
hipFree(d_in1);
hipFree(d_in2);
hipFree(d_out);
}
int main()
{
int nx, ny; // Số cột và số dòng
float *in1, *in2; // input matrix
float *out; // output vector
nx = pow(2, 13) + 1;
ny = pow(2, 13) + 1;
int size = nx * ny * sizeof(float);
in1 = (float *)malloc(size);
in2 = (float *)malloc(size);
out = (float *)malloc(size);
// Setup input values
srand(time(0));
for (int i = 0; i < ny; i++){
for (int j = 0; j < nx; j++){
int idx = i * ny + j;
in1[idx] = static_cast<float>(rand()) / static_cast<float>(RAND_MAX);
in2[idx] = static_cast<float>(rand()) / static_cast<float>(RAND_MAX);
}
}
auto start_host = high_resolution_clock::now();
addMatOnHost(in1, in2, out, nx, ny);
auto stop_host = high_resolution_clock::now();
auto duration_host = duration_cast<microseconds>(stop_host - start_host);
printf("Function\t|Block size\t|Grid size\t|Time (ms)\n");
printf("addMatOnHost\t|\t\t|\t\t|%d\n", duration_host.count());
/********************************
addMatOnDevice2D
*********************************/
int typeDevice = 1;
dim3 blockSize(32, 32);
dim3 gridSize(257, 257);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(16, 32);
gridSize = dim3(513, 257);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(32, 16);
gridSize = dim3(257, 513);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(16, 16);
gridSize = dim3(513, 513);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
/********************************
addMatOnDevice1D
*********************************/
typeDevice = 2;
blockSize = dim3(32, 1);
gridSize = dim3(257, 1);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(64, 1);
gridSize = dim3(129, 1);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(128, 1);
gridSize = dim3(65, 1);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
/********************************
addMatOnDevice2DNotMix
*********************************/
typeDevice = 3;
blockSize = dim3(32, 1);
gridSize = dim3(257, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(64, 1);
gridSize = dim3(129, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(128, 1);
gridSize = dim3(65, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(256, 1);
gridSize = dim3(33, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(512, 1);
gridSize = dim3(17, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(1024, 1);
gridSize = dim3(9, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(2048, 1);
gridSize = dim3(5, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
/********************************
addMatOnDeviceMix
*********************************/
typeDevice = 4;
blockSize = dim3(32, 1);
gridSize = dim3(257, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(64, 1);
gridSize = dim3(129, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(128, 1);
gridSize = dim3(65, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(256, 1);
gridSize = dim3(33, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(512, 1);
gridSize = dim3(17, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(1024, 1);
gridSize = dim3(9, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(2048, 1);
gridSize = dim3(5, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
free(in1);
free(in2);
free(out);
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <chrono>
#include <cmath>
#include <string>
#include <iostream>
using namespace std::chrono;
using namespace std;
__global__ void addMatOnDevice2D(float *in1, float *in2, float *out, int nx, int ny)
{
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int iy = threadIdx.y + blockIdx.y * blockDim.y;
if (ix < nx && iy < ny)
{
int i = iy * nx + ix;
out[i] = in1[i] + in2[i];
}
}
__global__ void addMatOnDevice1D(float *in1, float *in2, float *out, int nx, int ny)
{
int ix = threadIdx.x + blockIdx.x * blockDim.x;
if (ix < nx)
{
for (int iy = 0; iy < ny; iy++)
{
int idx = iy * nx + ix;
out[idx] = in1[idx] + in2[idx];
}
}
}
__global__ void addMatOnDeviceMix(float *in1, float *in2, float *out, int nx, int ny)
{
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int iy = blockIdx.y;
if (ix < nx)
{
int idx = iy * nx + ix;
out[idx] = in1[idx] + in2[idx];
}
}
void addMatOnHost(float *in1, float *in2, float *out,
int nx, int ny)
{
for (int i = 0; i < ny; i++)
for (int j = 0; j < nx; j++){
int idx = i * nx + j;
out[idx] = in1[idx] + in2[idx];
}
}
void printMatrix(float *matrix, int nx, int ny)
{
printf("\n");
for (int i = 0; i < ny; i++){
for (int j = 0; j < nx; j++){
int idx = i * ny + j;
printf("%f ", matrix[idx]);
}
printf("\n");
}
}
void calcTimeOnDevice(float *in1, float *in2, float *out, int nx, int ny, dim3 blockSize, dim3 gridSize, int typeDevice)
{
int size = nx * ny * sizeof(float);
// Allocate vector to device memory
float *d_in1, *d_in2, *d_out;
hipMalloc(&d_in1, size);
hipMalloc(&d_in2, size);
hipMalloc(&d_out, size);
// Copy inputs to device
hipMemcpy(d_in1, in1, size, hipMemcpyHostToDevice);
hipMemcpy(d_in2, in2, size, hipMemcpyHostToDevice);
auto start_device = high_resolution_clock::now();
string deviceName = "";
if (typeDevice == 1){
deviceName = "addMatOnDevice2D";
addMatOnDevice2D<<<gridSize, blockSize>>>(d_in1, d_in2, d_out, nx, ny);
}else if (typeDevice == 2){
deviceName = "addMatOnDevice1D";
addMatOnDevice1D<<<gridSize, blockSize>>>(d_in1, d_in2, d_out, nx, ny);
}else if (typeDevice == 3){
deviceName = "addMatOnDevice2DNotMix";
addMatOnDevice2D<<<gridSize, blockSize>>>(d_in1, d_in2, d_out, nx, ny);
}else {
deviceName = "addMatOnDeviceMix";
addMatOnDeviceMix<<<gridSize, blockSize>>>(d_in1, d_in2, d_out, nx, ny);
}
hipDeviceSynchronize();
hipGetLastError();
hipMemcpy(out, d_out, size, hipMemcpyDeviceToHost);
auto stop_device = high_resolution_clock::now();
auto duration_device = duration_cast<microseconds>(stop_device - start_device);
auto duration = duration_device.count();
printf("%s|%d x %d\t|%d x %d\t|%d ms\t\n", deviceName.c_str(), blockSize.x, blockSize.y, gridSize.x, gridSize.y, duration);
// Cleanup
hipFree(d_in1);
hipFree(d_in2);
hipFree(d_out);
}
int main()
{
int nx, ny; // Số cột và số dòng
float *in1, *in2; // input matrix
float *out; // output vector
nx = pow(2, 13) + 1;
ny = pow(2, 13) + 1;
int size = nx * ny * sizeof(float);
in1 = (float *)malloc(size);
in2 = (float *)malloc(size);
out = (float *)malloc(size);
// Setup input values
srand(time(0));
for (int i = 0; i < ny; i++){
for (int j = 0; j < nx; j++){
int idx = i * ny + j;
in1[idx] = static_cast<float>(rand()) / static_cast<float>(RAND_MAX);
in2[idx] = static_cast<float>(rand()) / static_cast<float>(RAND_MAX);
}
}
auto start_host = high_resolution_clock::now();
addMatOnHost(in1, in2, out, nx, ny);
auto stop_host = high_resolution_clock::now();
auto duration_host = duration_cast<microseconds>(stop_host - start_host);
printf("Function\t|Block size\t|Grid size\t|Time (ms)\n");
printf("addMatOnHost\t|\t\t|\t\t|%d\n", duration_host.count());
/********************************
addMatOnDevice2D
*********************************/
int typeDevice = 1;
dim3 blockSize(32, 32);
dim3 gridSize(257, 257);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(16, 32);
gridSize = dim3(513, 257);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(32, 16);
gridSize = dim3(257, 513);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(16, 16);
gridSize = dim3(513, 513);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
/********************************
addMatOnDevice1D
*********************************/
typeDevice = 2;
blockSize = dim3(32, 1);
gridSize = dim3(257, 1);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(64, 1);
gridSize = dim3(129, 1);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(128, 1);
gridSize = dim3(65, 1);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
/********************************
addMatOnDevice2DNotMix
*********************************/
typeDevice = 3;
blockSize = dim3(32, 1);
gridSize = dim3(257, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(64, 1);
gridSize = dim3(129, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(128, 1);
gridSize = dim3(65, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(256, 1);
gridSize = dim3(33, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(512, 1);
gridSize = dim3(17, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(1024, 1);
gridSize = dim3(9, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(2048, 1);
gridSize = dim3(5, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
/********************************
addMatOnDeviceMix
*********************************/
typeDevice = 4;
blockSize = dim3(32, 1);
gridSize = dim3(257, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(64, 1);
gridSize = dim3(129, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(128, 1);
gridSize = dim3(65, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(256, 1);
gridSize = dim3(33, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(512, 1);
gridSize = dim3(17, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(1024, 1);
gridSize = dim3(9, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
blockSize = dim3(2048, 1);
gridSize = dim3(5, 8193);
calcTimeOnDevice(in1, in2, out, nx, ny, blockSize, gridSize, typeDevice);
free(in1);
free(in2);
free(out);
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16addMatOnDevice2DPfS_S_ii
.globl _Z16addMatOnDevice2DPfS_S_ii
.p2align 8
.type _Z16addMatOnDevice2DPfS_S_ii,@function
_Z16addMatOnDevice2DPfS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[8:11], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16addMatOnDevice2DPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16addMatOnDevice2DPfS_S_ii, .Lfunc_end0-_Z16addMatOnDevice2DPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16addMatOnDevice1DPfS_S_ii
.globl _Z16addMatOnDevice1DPfS_S_ii
.p2align 8
.type _Z16addMatOnDevice1DPfS_S_ii,@function
_Z16addMatOnDevice1DPfS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_cmp_gt_i32 s3, 0
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_cselect_b32 s4, -1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_b32 s4, vcc_lo, s4
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB1_3
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
.p2align 6
.LBB1_2:
v_ashrrev_i32_e32 v2, 31, v1
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s3, 0
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, s2, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v4
global_store_b32 v[2:3], v0, off
s_cbranch_scc1 .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16addMatOnDevice1DPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z16addMatOnDevice1DPfS_S_ii, .Lfunc_end1-_Z16addMatOnDevice1DPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z17addMatOnDeviceMixPfS_S_ii
.globl _Z17addMatOnDeviceMixPfS_S_ii
.p2align 8
.type _Z17addMatOnDeviceMixPfS_S_ii,@function
_Z17addMatOnDeviceMixPfS_S_ii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB2_2
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17addMatOnDeviceMixPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z17addMatOnDeviceMixPfS_S_ii, .Lfunc_end2-_Z17addMatOnDeviceMixPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16addMatOnDevice2DPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16addMatOnDevice2DPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16addMatOnDevice1DPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16addMatOnDevice1DPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17addMatOnDeviceMixPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17addMatOnDeviceMixPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
//Global Variable Declaration
float* p;
//Memory Allocation Function
void memAlloc(float **data_ptr, int dim_x, int dim_y)
{
float *data;
data = (float *) malloc(sizeof(float *) * dim_x * dim_y);
*data_ptr = data;
}
//void cleanp()
//{
//if(p)
// free(p);
//}
/* ----------------------------------------------------
main method for Cholesky decomposition.
input n size of matrix
input/output a Symmetric positive def. matrix
output p vector of resulting diag of a
----------------------------------------------------- */
int choldc1(int n, float* a)
{
int i,j,k;
float sum;
for (i = 0; i < n; i++)
{
for (j = i; j < n; j++)
{
sum = a[i * n + j];
for (k = i - 1; k >= 0; k--)
{
sum -= a[i * n + k] * a[j * n + k];
}
if (i == j)
{
if (sum <= 0)
{
printf(" S is not positive definite!\n");
return 0;
}
p[i] = sqrt(sum);
}
else
{
a[j * n + i] = sum / p[i];
}
}
}
return 1;
}
/* -----------------------------------------------------
Inverse of Cholesky decomposition.
input n size of matrix
input A Symmetric positive def. matrix
output a inverse of lower deomposed matrix
uses choldc1(int,MAT,VEC)
----------------------------------------------------- */
int choldcsl(int n, float* A, float* a)
{
int i,j,k; float sum;
int success;
for (i = 0; i < n; i++)
for (j = 0; j < n; j++)
a[i * n + j] = A[i * n + j];
success = choldc1(n, a);
if (success == 0)
return 0;
for (i = 0; i < n; i++)
{
a[i * n + i] = 1 / p[i];
for (j = i + 1; j < n; j++)
{
sum = 0;
for (k = i; k < j; k++)
{
sum -= a[j * n + k] * a[k * n + i];
}
a[j * n + i] = sum / p[j];
}
}
return 1;
}
/* ---------------------------------------------------
Matrix inverse using Cholesky decomposition
input n size of matrix
input A Symmetric positive def. matrix
output a inverse of A
uses choldc1(MAT, VEC)
--------------------------------------------------- */
int inverse(int n, float* A, float* a)
{
int i,j,k,success;
//temp memory allocation for p
memAlloc(&p,n,n);
//printf("\n memory allocation done \n");
success = choldcsl(n,A,a);
if( success == 0)
{
//cleanp();
return 0;
}
for (i = 0; i < n; i++)
{
for (j = i + 1; j < n; j++)
{
a[i * n + j] = 0.0;
}
}
for (i = 0; i < n; i++)
{
a[i * n + i] *= a[i * n + i];
for (k = i + 1; k < n; k++)
{
a[i * n + i] += a[k * n + i] * a[k * n + i];
}
for (j = i + 1; j < n; j++)
{
for (k = j; k < n; k++)
{
a[i * n + j] += a[k * n + i] * a[k * n + j];
}
}
}
for (i = 0; i < n; i++)
{
for (j = 0; j < i; j++)
{
a[i * n + j] = a[j * n + i];
}
}
//cleanp();
return 1;
}
//Inversion Complete
//Other Matrix operations
//Addition
void add(float* C, float* A, float* B, int h, int w)
{
int i,j;
for (i = 0; i < h; i++)
{
for(j = 0; j < w ;j++)
{
C[i * w +j] = A[i * w + j] + B[i * w + j];
}
}
}
//subtraction
void sub(float* C, float* A, float* B, int h, int w)
{
int i,j;
for (i = 0; i < h; i++)
{
for(j = 0; j < w ;j++)
{
C[i * w + j] = A[i * w + j] - B[i * w + j];
}
}
}
//Multiplication
void mult(float* C, float* A, float* B, int ha, int wa, int hb, int wb)
{
int i,j,k;
float sum,a = 0,b = 0;
for (i = 0; i < ha; i++)
{
for(j = 0; j < wb ;j++)
{
sum = 0;
for(k = 0; k < wa; k++)
{
a = A[i * wa + k];
b = B[k * wb + j];
sum += a * b;
}
C[i * wb + j] = sum;
}
}
}
//Transpose
void transpose(float* B, float* A,int h, int w)
{
int i,j;
for (i = 0; i < h; i++)
{
for(j = 0; j < w ;j++)
{
B[j * h + i] = A[i * w + j];
}
}
}
//print the matrix
void matPrint(float *A, int h, int w)
{
int i,j;
for(i = 0;i < h;i++)
{
for(j = 0;j < w;j++)
{
printf("%f ", A[i * w + j]);
}
printf("\n");}
}
//Matrix Copy
void matcopy(float *B, float *A, int h, int w)
{
int i;
for(i = 0;i < (h*w);i++)
B[i] = A[i];
}
// generating L
void generateL(float *L, int n)
{
int i,j;
srand(1);
for (i = 0; i < n; i++)
{
for(j = 0; j < n ;j++)
{
if(j <= i)
L[i*n + j]= (rand() % 10) + 1;
else
L[i*n + j] = 0;
}
}
}
//Random Initialize
void RandomInit(float* data, int n1, int n2)
{
srand(1);
for (int i = 0; i < (n1*n2); ++i)
data[i] = (rand() % 10) + 1;
}
//Ideintity Matrix Generation
void Identity(float *data, int n)
{
for (int i = 0; i < (n*n); i=i+1)
{
if((i%(n+1))==0)
data[i] = 1;
else
data[i] = 0;
}
}
void Initialize(float *X,float *P,float *F,float *Z,float *H,float *E,float *I,float *Ht,float *Ft,float *s, int ns, int no)
{
RandomInit(X, ns, 1);
RandomInit(Z, no, 1);
RandomInit(H, no, ns);
transpose(Ht,H,no,ns);
//printf("\n Transpose of H successful\n");
float *P1;
float *P2;
memAlloc(&P1,ns,ns);
memAlloc(&P2,ns,ns);
generateL(P1,ns);
transpose(P2,P1,ns,ns);
mult(P,P1,P2,ns,ns,ns,ns);
if(P1)
free(P1);
if(P2)
free(P2);
float *F1;
float *F2;
memAlloc(&F1,ns,ns);
memAlloc(&F2,ns,ns);
generateL(F1,ns);
transpose(F2,F1,ns,ns);
mult(F,F1,F2,ns,ns,ns,ns);
if(F1)
free(F1);
if(F2)
free(F2);
transpose(Ft,F,ns,ns);
//printf("\n Transpose of F successful\n");
float *E1;
float *E2;
memAlloc(&E1,no,no);
memAlloc(&E2,no,no);
generateL(E1,no);
transpose(E2,E1,no,no);
mult(E,E1,E2,no,no,no,no);
if(E1)
free(E1);
if(E2)
free(E2);
float *s1;
float *s2;
memAlloc(&s1,no,no);
memAlloc(&s2,no,no);
generateL(s1,no);
transpose(s2,s1,no,no);
mult(s,s1,s2,no,no,no,no);
if(s1)
free(s1);
if(s2)
free(s2);
Identity(I, ns);
}
|
code for sm_80
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
//Global Variable Declaration
float* p;
//Memory Allocation Function
void memAlloc(float **data_ptr, int dim_x, int dim_y)
{
float *data;
data = (float *) malloc(sizeof(float *) * dim_x * dim_y);
*data_ptr = data;
}
//void cleanp()
//{
//if(p)
// free(p);
//}
/* ----------------------------------------------------
main method for Cholesky decomposition.
input n size of matrix
input/output a Symmetric positive def. matrix
output p vector of resulting diag of a
----------------------------------------------------- */
int choldc1(int n, float* a)
{
int i,j,k;
float sum;
for (i = 0; i < n; i++)
{
for (j = i; j < n; j++)
{
sum = a[i * n + j];
for (k = i - 1; k >= 0; k--)
{
sum -= a[i * n + k] * a[j * n + k];
}
if (i == j)
{
if (sum <= 0)
{
printf(" S is not positive definite!\n");
return 0;
}
p[i] = sqrt(sum);
}
else
{
a[j * n + i] = sum / p[i];
}
}
}
return 1;
}
/* -----------------------------------------------------
Inverse of Cholesky decomposition.
input n size of matrix
input A Symmetric positive def. matrix
output a inverse of lower deomposed matrix
uses choldc1(int,MAT,VEC)
----------------------------------------------------- */
int choldcsl(int n, float* A, float* a)
{
int i,j,k; float sum;
int success;
for (i = 0; i < n; i++)
for (j = 0; j < n; j++)
a[i * n + j] = A[i * n + j];
success = choldc1(n, a);
if (success == 0)
return 0;
for (i = 0; i < n; i++)
{
a[i * n + i] = 1 / p[i];
for (j = i + 1; j < n; j++)
{
sum = 0;
for (k = i; k < j; k++)
{
sum -= a[j * n + k] * a[k * n + i];
}
a[j * n + i] = sum / p[j];
}
}
return 1;
}
/* ---------------------------------------------------
Matrix inverse using Cholesky decomposition
input n size of matrix
input A Symmetric positive def. matrix
output a inverse of A
uses choldc1(MAT, VEC)
--------------------------------------------------- */
int inverse(int n, float* A, float* a)
{
int i,j,k,success;
//temp memory allocation for p
memAlloc(&p,n,n);
//printf("\n memory allocation done \n");
success = choldcsl(n,A,a);
if( success == 0)
{
//cleanp();
return 0;
}
for (i = 0; i < n; i++)
{
for (j = i + 1; j < n; j++)
{
a[i * n + j] = 0.0;
}
}
for (i = 0; i < n; i++)
{
a[i * n + i] *= a[i * n + i];
for (k = i + 1; k < n; k++)
{
a[i * n + i] += a[k * n + i] * a[k * n + i];
}
for (j = i + 1; j < n; j++)
{
for (k = j; k < n; k++)
{
a[i * n + j] += a[k * n + i] * a[k * n + j];
}
}
}
for (i = 0; i < n; i++)
{
for (j = 0; j < i; j++)
{
a[i * n + j] = a[j * n + i];
}
}
//cleanp();
return 1;
}
//Inversion Complete
//Other Matrix operations
//Addition
void add(float* C, float* A, float* B, int h, int w)
{
int i,j;
for (i = 0; i < h; i++)
{
for(j = 0; j < w ;j++)
{
C[i * w +j] = A[i * w + j] + B[i * w + j];
}
}
}
//subtraction
void sub(float* C, float* A, float* B, int h, int w)
{
int i,j;
for (i = 0; i < h; i++)
{
for(j = 0; j < w ;j++)
{
C[i * w + j] = A[i * w + j] - B[i * w + j];
}
}
}
//Multiplication
void mult(float* C, float* A, float* B, int ha, int wa, int hb, int wb)
{
int i,j,k;
float sum,a = 0,b = 0;
for (i = 0; i < ha; i++)
{
for(j = 0; j < wb ;j++)
{
sum = 0;
for(k = 0; k < wa; k++)
{
a = A[i * wa + k];
b = B[k * wb + j];
sum += a * b;
}
C[i * wb + j] = sum;
}
}
}
//Transpose
void transpose(float* B, float* A,int h, int w)
{
int i,j;
for (i = 0; i < h; i++)
{
for(j = 0; j < w ;j++)
{
B[j * h + i] = A[i * w + j];
}
}
}
//print the matrix
void matPrint(float *A, int h, int w)
{
int i,j;
for(i = 0;i < h;i++)
{
for(j = 0;j < w;j++)
{
printf("%f ", A[i * w + j]);
}
printf("\n");}
}
//Matrix Copy
void matcopy(float *B, float *A, int h, int w)
{
int i;
for(i = 0;i < (h*w);i++)
B[i] = A[i];
}
// generating L
void generateL(float *L, int n)
{
int i,j;
srand(1);
for (i = 0; i < n; i++)
{
for(j = 0; j < n ;j++)
{
if(j <= i)
L[i*n + j]= (rand() % 10) + 1;
else
L[i*n + j] = 0;
}
}
}
//Random Initialize
void RandomInit(float* data, int n1, int n2)
{
srand(1);
for (int i = 0; i < (n1*n2); ++i)
data[i] = (rand() % 10) + 1;
}
//Ideintity Matrix Generation
void Identity(float *data, int n)
{
for (int i = 0; i < (n*n); i=i+1)
{
if((i%(n+1))==0)
data[i] = 1;
else
data[i] = 0;
}
}
void Initialize(float *X,float *P,float *F,float *Z,float *H,float *E,float *I,float *Ht,float *Ft,float *s, int ns, int no)
{
RandomInit(X, ns, 1);
RandomInit(Z, no, 1);
RandomInit(H, no, ns);
transpose(Ht,H,no,ns);
//printf("\n Transpose of H successful\n");
float *P1;
float *P2;
memAlloc(&P1,ns,ns);
memAlloc(&P2,ns,ns);
generateL(P1,ns);
transpose(P2,P1,ns,ns);
mult(P,P1,P2,ns,ns,ns,ns);
if(P1)
free(P1);
if(P2)
free(P2);
float *F1;
float *F2;
memAlloc(&F1,ns,ns);
memAlloc(&F2,ns,ns);
generateL(F1,ns);
transpose(F2,F1,ns,ns);
mult(F,F1,F2,ns,ns,ns,ns);
if(F1)
free(F1);
if(F2)
free(F2);
transpose(Ft,F,ns,ns);
//printf("\n Transpose of F successful\n");
float *E1;
float *E2;
memAlloc(&E1,no,no);
memAlloc(&E2,no,no);
generateL(E1,no);
transpose(E2,E1,no,no);
mult(E,E1,E2,no,no,no,no);
if(E1)
free(E1);
if(E2)
free(E2);
float *s1;
float *s2;
memAlloc(&s1,no,no);
memAlloc(&s2,no,no);
generateL(s1,no);
transpose(s2,s1,no,no);
mult(s,s1,s2,no,no,no,no);
if(s1)
free(s1);
if(s2)
free(s2);
Identity(I, ns);
}
|
.file "tmpxft_00142551_00000000-6_matrix.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2073:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8memAllocPPfii
.type _Z8memAllocPPfii, @function
_Z8memAllocPPfii:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movslq %esi, %rsi
movslq %edx, %rdx
imulq %rdx, %rsi
leaq 0(,%rsi,8), %rdi
call malloc@PLT
movq %rax, (%rbx)
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z8memAllocPPfii, .-_Z8memAllocPPfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string " S is not positive definite!\n"
.text
.globl _Z7choldc1iPf
.type _Z7choldc1iPf, @function
_Z7choldc1iPf:
.LFB2058:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L17
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %edi, %r8d
movq %rsi, %r10
leal 1(%rdi), %r14d
movslq %edi, %r15
movl $0, %ebp
movq $-1, %r9
movl $0, %r13d
movl $0, %r12d
movl $0, %r11d
movl $0, %ecx
pxor %xmm2, %xmm2
movl %r14d, %esi
jmp .L7
.L29:
comiss %xmm1, %xmm2
jnb .L27
movq %r11, %rax
addq p(%rip), %rax
sqrtss %xmm1, %xmm1
movss %xmm1, (%rax)
.L13:
addq $1, %rdi
addl %r8d, %ebx
cmpl %edi, %r8d
jle .L28
.L14:
movss (%rdx,%rdi,4), %xmm1
testl %r9d, %r9d
js .L8
leal (%rbx,%rbp), %eax
cltq
leaq (%r10,%rax,4), %rcx
movq %r9, %rax
.L9:
movss (%rdx,%rax,4), %xmm0
mulss (%rcx,%rax,4), %xmm0
subss %xmm0, %xmm1
subq $1, %rax
testl %eax, %eax
jns .L9
.L8:
cmpl %edi, %r14d
je .L29
movslq %ebx, %rax
movq p(%rip), %rcx
divss (%rcx,%r11), %xmm1
movss %xmm1, (%r10,%rax,4)
jmp .L13
.L27:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
.L5:
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movq 8(%rsp), %rcx
.L16:
addq $1, %rcx
addq $4, %r11
addl %esi, %r12d
addl %r8d, %r13d
addq $1, %r9
subl $1, %ebp
cmpq %r15, %rcx
je .L18
.L7:
movl %ecx, %r14d
cmpl %ecx, %r8d
jle .L16
movslq %r13d, %rax
leaq (%r10,%rax,4), %rdx
movl %r12d, %ebx
movq %rcx, %rdi
movq %rcx, 8(%rsp)
jmp .L14
.L17:
.cfi_def_cfa_offset 8
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
movl $1, %eax
ret
.L18:
.cfi_def_cfa_offset 80
.cfi_offset 3, -56
.cfi_offset 6, -48
.cfi_offset 12, -40
.cfi_offset 13, -32
.cfi_offset 14, -24
.cfi_offset 15, -16
movl $1, %eax
jmp .L5
.cfi_endproc
.LFE2058:
.size _Z7choldc1iPf, .-_Z7choldc1iPf
.globl _Z8choldcsliPfS_
.type _Z8choldcsliPfS_, @function
_Z8choldcsliPfS_:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl %edi, %ebp
movq %rdx, %rbx
testl %edi, %edi
jle .L31
movslq %edi, %rdi
leaq 0(,%rdi,4), %r8
negq %rdi
salq $2, %rdi
movq %r8, %rdx
movl $0, %ecx
.L32:
leaq (%rdx,%rdi), %rax
.L33:
movss (%rsi,%rax), %xmm0
movss %xmm0, (%rbx,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L33
addl $1, %ecx
addq %r8, %rdx
cmpl %ecx, %ebp
jne .L32
movq %rbx, %rsi
movl %ebp, %edi
call _Z7choldc1iPf
testl %eax, %eax
je .L30
.L42:
movslq %ebp, %rax
movq %rax, 32(%rsp)
leaq 4(,%rax,4), %rsi
movq %rsi, 40(%rsp)
leaq 0(,%rax,4), %rcx
leaq (%rbx,%rcx), %rsi
leal -1(%rbp), %edi
movq %rdi, 16(%rsp)
negq %rax
salq $2, %rax
movq %rax, 24(%rsp)
movl %ebp, %r12d
movl $0, %edx
movl $1, %r15d
movl $0, %r8d
movss .LC2(%rip), %xmm2
movq %r15, %rax
jmp .L41
.L31:
movq %rdx, %rsi
call _Z7choldc1iPf
testl %eax, %eax
je .L30
testl %ebp, %ebp
jg .L42
movl $1, %eax
jmp .L30
.L49:
movslq %r13d, %rdi
leaq (%rdi,%r8), %rax
leaq (%rbx,%rax,4), %rax
movl %r9d, %edx
addq %rdi, %rdx
addq %r8, %rdx
leaq (%rbx,%rdx,4), %rdi
movq %r15, %rdx
pxor %xmm1, %xmm1
.L37:
movss (%rax), %xmm0
mulss (%rdx), %xmm0
subss %xmm0, %xmm1
addq $4, %rax
addq %rcx, %rdx
cmpq %rdi, %rax
jne .L37
.L40:
movq p(%rip), %rax
divss (%rax,%r11), %xmm1
movss %xmm1, (%r10)
addq $4, %r11
addq %rcx, %r10
addl %ebp, %r13d
addl $1, %r9d
cmpl %r12d, %r9d
je .L38
.L36:
leal (%r9,%r14), %eax
pxor %xmm1, %xmm1
cmpl %r8d, %eax
jg .L49
jmp .L40
.L38:
movl 4(%rsp), %edi
movq 8(%rsp), %rax
addq $1, %r8
addq $1, %rax
subl $1, %r12d
movq 40(%rsp), %rdx
addq %rdx, %rsi
movq 32(%rsp), %rdx
cmpq %rdx, %r8
je .L50
movl %edi, %edx
.L41:
movl %r8d, %r14d
movq p(%rip), %rdi
movaps %xmm2, %xmm0
divss (%rdi,%r8,4), %xmm0
movq 24(%rsp), %rdi
movss %xmm0, (%rsi,%rdi)
movq 16(%rsp), %rdi
cmpq %rdi, %r8
je .L44
leaq 0(,%rax,4), %r11
leal 0(%rbp,%rdx), %edi
movslq %edx, %rdx
addq %r8, %rdx
leaq (%rbx,%rdx,4), %r15
movl %edi, %r13d
movq %rsi, %r10
movl $1, %r9d
movl %edi, 4(%rsp)
movq %rax, 8(%rsp)
jmp .L36
.L50:
movl $1, %eax
jmp .L30
.L44:
movl $1, %eax
.L30:
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z8choldcsliPfS_, .-_Z8choldcsliPfS_
.globl _Z7inverseiPfS_
.type _Z7inverseiPfS_, @function
_Z7inverseiPfS_:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %r12d
movq %rsi, %rbp
movq %rdx, %rbx
movl %edi, %edx
movl %edi, %esi
leaq p(%rip), %rdi
call _Z8memAllocPPfii
movq %rbx, %rdx
movq %rbp, %rsi
movl %r12d, %edi
call _Z8choldcsliPfS_
testl %eax, %eax
je .L51
testl %r12d, %r12d
jle .L68
movslq %r12d, %r9
addq $1, %r9
leaq 0(,%r9,4), %rsi
leaq 4(%rbx), %r8
movl $0, %ecx
movl $0, %edi
leal -1(%r12), %r11d
leaq 8(%rbx), %r10
.L55:
leal 1(%rdi), %ebp
cmpl %ebp, %r12d
je .L53
movl %r11d, %eax
subl %ebp, %eax
addq %rcx, %rax
leaq (%r10,%rax,4), %rdx
movq %r8, %rax
.L54:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L54
addq %rsi, %r8
addq %r9, %rcx
movl %ebp, %edi
jmp .L55
.L53:
movslq %ebp, %r14
movl %edi, %r15d
leaq -4(%rsi), %r8
movq %rbx, %rax
movl $0, %r13d
movl $0, %r12d
movq %r14, %r9
jmp .L63
.L61:
leal (%r11,%r13), %eax
cltq
leaq (%rbx,%rax,4), %rcx
movslq %r14d, %rax
addq %r12, %rax
leaq (%rbx,%rax,4), %rax
movl %r11d, %edx
.L59:
movss (%rax), %xmm0
mulss (%rax,%r10,4), %xmm0
addss (%rcx), %xmm0
movss %xmm0, (%rcx)
movl %edx, %r9d
addl $1, %edx
addq %r8, %rax
cmpl %r9d, %edi
jne .L59
.L62:
leal 1(%r11), %eax
addq $1, %r10
addl %ebp, %r14d
cmpl %r11d, %edi
je .L60
movl %eax, %r11d
.L58:
cmpl %r11d, %ebp
jg .L61
jmp .L62
.L60:
movl 12(%rsp), %edx
movq 16(%rsp), %rax
movq 24(%rsp), %r9
addq $1, %r12
addq %rsi, %rax
cmpq %r9, %r12
je .L56
movl %edx, %r13d
.L63:
movq %rax, %r10
movss (%rax), %xmm0
mulss %xmm0, %xmm0
movss %xmm0, (%rax)
leal 1(%r12), %r11d
cmpq %r15, %r12
je .L56
leaq (%r8,%rax), %rcx
movl %r11d, %edx
.L57:
movss (%rcx), %xmm0
mulss %xmm0, %xmm0
addss (%r10), %xmm0
movss %xmm0, (%r10)
movl %edx, %r14d
addl $1, %edx
addq %r8, %rcx
cmpl %r14d, %edi
jne .L57
leal 0(%r13,%rbp), %edx
movl %edx, %r14d
movl $1, %r10d
movl %edx, 12(%rsp)
movq %rax, 16(%rsp)
movq %r9, 24(%rsp)
jmp .L58
.L56:
movq %r9, %r14
movq %rbx, %r9
movl $0, %edi
movl $0, %esi
jmp .L64
.L66:
movslq %edi, %rdx
leaq (%rbx,%rdx,4), %rax
addq %rsi, %rdx
leaq (%rbx,%rdx,4), %rcx
movq %r9, %rdx
.L65:
movss (%rdx), %xmm0
movss %xmm0, (%rax)
addq %r8, %rdx
addq $4, %rax
cmpq %rcx, %rax
jne .L65
.L67:
addq $1, %rsi
addq $4, %r9
addl %ebp, %edi
cmpq %r14, %rsi
je .L70
.L64:
testl %esi, %esi
jg .L66
jmp .L67
.L68:
movl $1, %eax
jmp .L51
.L70:
movl $1, %eax
.L51:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z7inverseiPfS_, .-_Z7inverseiPfS_
.globl _Z3addPfS_S_ii
.type _Z3addPfS_S_ii, @function
_Z3addPfS_S_ii:
.LFB2061:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L84
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdx, %r9
movl $0, %r11d
movl $0, %r10d
movslq %r8d, %rbx
jmp .L78
.L80:
movslq %r11d, %rdx
leaq 0(,%rdx,4), %rax
addq %rbx, %rdx
salq $2, %rdx
.L79:
movss (%rsi,%rax), %xmm0
addss (%r9,%rax), %xmm0
movss %xmm0, (%rdi,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L79
.L81:
addl $1, %r10d
addl %r8d, %r11d
cmpl %r10d, %ecx
je .L76
.L78:
testl %r8d, %r8d
jg .L80
jmp .L81
.L76:
popq %rbx
.cfi_def_cfa_offset 8
ret
.L84:
.cfi_restore 3
ret
.cfi_endproc
.LFE2061:
.size _Z3addPfS_S_ii, .-_Z3addPfS_S_ii
.globl _Z3subPfS_S_ii
.type _Z3subPfS_S_ii, @function
_Z3subPfS_S_ii:
.LFB2062:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L95
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdx, %r9
movl $0, %r11d
movl $0, %r10d
movslq %r8d, %rbx
jmp .L89
.L91:
movslq %r11d, %rdx
leaq 0(,%rdx,4), %rax
addq %rbx, %rdx
salq $2, %rdx
.L90:
movss (%rsi,%rax), %xmm0
subss (%r9,%rax), %xmm0
movss %xmm0, (%rdi,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L90
.L92:
addl $1, %r10d
addl %r8d, %r11d
cmpl %r10d, %ecx
je .L87
.L89:
testl %r8d, %r8d
jg .L91
jmp .L92
.L87:
popq %rbx
.cfi_def_cfa_offset 8
ret
.L95:
.cfi_restore 3
ret
.cfi_endproc
.LFE2062:
.size _Z3subPfS_S_ii, .-_Z3subPfS_S_ii
.globl _Z4multPfS_S_iiii
.type _Z4multPfS_S_iiii, @function
_Z4multPfS_S_iiii:
.LFB2063:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rdi, -16(%rsp)
movq %rdx, -8(%rsp)
movl %ecx, -20(%rsp)
movl 56(%rsp), %r14d
testl %ecx, %ecx
jle .L98
movq %rsi, %rbp
movl %r8d, %r9d
movslq %r14d, %rbx
leaq 0(,%rbx,4), %rsi
movl $0, %r13d
movl $0, %r12d
movl $0, %edx
movslq %r8d, %r15
movq %r15, %rcx
jmp .L100
.L101:
movss (%rax), %xmm0
mulss (%rdx), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
addq %rsi, %rdx
cmpq %rdi, %rax
jne .L101
.L103:
movss %xmm1, (%r11,%r8,4)
addq $1, %r8
addq $4, %r10
cmpq %r8, %rbx
je .L108
.L104:
movq %r10, %rdx
movq %r15, %rax
pxor %xmm1, %xmm1
testl %r9d, %r9d
jg .L101
jmp .L103
.L108:
movl -24(%rsp), %edx
.L102:
addl $1, %edx
addl %r14d, %r12d
addl %r9d, %r13d
cmpl %edx, -20(%rsp)
je .L98
.L100:
testl %r14d, %r14d
jle .L102
movq -8(%rsp), %r10
movslq %r13d, %rax
leaq 0(%rbp,%rax,4), %r15
addq %rcx, %rax
leaq 0(%rbp,%rax,4), %rdi
movslq %r12d, %rax
movq -16(%rsp), %r11
leaq (%r11,%rax,4), %r11
movl $0, %r8d
movl %edx, -24(%rsp)
jmp .L104
.L98:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _Z4multPfS_S_iiii, .-_Z4multPfS_S_iiii
.globl _Z9transposePfS_ii
.type _Z9transposePfS_ii, @function
_Z9transposePfS_ii:
.LFB2064:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L119
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movq %rsi, %r11
movl %edx, %ebx
movslq %edx, %r8
salq $2, %r8
movl $0, %r10d
movl $0, %r9d
movslq %ecx, %rbp
jmp .L113
.L115:
movslq %r10d, %rdx
leaq (%r11,%rdx,4), %rax
addq %rbp, %rdx
leaq (%r11,%rdx,4), %rsi
movq %rdi, %rdx
.L114:
movss (%rax), %xmm0
movss %xmm0, (%rdx)
addq $4, %rax
addq %r8, %rdx
cmpq %rsi, %rax
jne .L114
.L116:
addl $1, %r9d
addq $4, %rdi
addl %ecx, %r10d
cmpl %r9d, %ebx
je .L111
.L113:
testl %ecx, %ecx
jg .L115
jmp .L116
.L111:
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L119:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2064:
.size _Z9transposePfS_ii, .-_Z9transposePfS_ii
.section .rodata.str1.1
.LC3:
.string "%f "
.LC4:
.string "\n"
.text
.globl _Z8matPrintPfii
.type _Z8matPrintPfii, @function
_Z8matPrintPfii:
.LFB2065:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L122
movl %edx, %r15d
movl $0, %r14d
movl $0, %r13d
movslq %edx, %rax
movq %rax, 24(%rsp)
leaq .LC3(%rip), %r12
jmp .L124
.L126:
movslq %r14d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rdx
addq %rdx, %rax
leaq (%rcx,%rax,4), %rbp
.L125:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L125
.L127:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addl %r15d, %r14d
cmpl %r13d, 12(%rsp)
je .L122
.L124:
testl %r15d, %r15d
jg .L126
jmp .L127
.L122:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _Z8matPrintPfii, .-_Z8matPrintPfii
.globl _Z7matcopyPfS_ii
.type _Z7matcopyPfS_ii, @function
_Z7matcopyPfS_ii:
.LFB2066:
.cfi_startproc
endbr64
imull %ecx, %edx
testl %edx, %edx
jle .L130
movslq %edx, %rdx
salq $2, %rdx
movl $0, %eax
.L132:
movss (%rsi,%rax), %xmm0
movss %xmm0, (%rdi,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L132
.L130:
ret
.cfi_endproc
.LFE2066:
.size _Z7matcopyPfS_ii, .-_Z7matcopyPfS_ii
.globl _Z9generateLPfi
.type _Z9generateLPfi, @function
_Z9generateLPfi:
.LFB2067:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r14
movl %esi, %r13d
movl $1, %edi
call srand@PLT
testl %r13d, %r13d
jle .L134
movl $0, %r12d
movl $0, %ebp
movl $0, %r15d
jmp .L136
.L137:
leal (%rbx,%r12), %eax
cltq
movl $0x00000000, (%r14,%rax,4)
.L138:
leal 1(%rbx), %eax
cmpl %eax, %r13d
je .L142
movl %eax, %ebx
.L139:
cmpl %ebx, %ebp
jl .L137
call rand@PLT
leal (%rbx,%r12), %ecx
movslq %ecx, %rcx
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %esi
sarl $31, %esi
subl %esi, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
addl $1, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r14,%rcx,4)
jmp .L138
.L142:
leal 1(%rbp), %eax
addl %r13d, %r12d
cmpl %ebx, %ebp
je .L134
movl %eax, %ebp
.L136:
movl %r15d, %ebx
jmp .L139
.L134:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2067:
.size _Z9generateLPfi, .-_Z9generateLPfi
.globl _Z10RandomInitPfii
.type _Z10RandomInitPfii, @function
_Z10RandomInitPfii:
.LFB2068:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbp
movl %esi, %ebx
movl %edx, %r12d
movl $1, %edi
call srand@PLT
movl %ebx, %esi
imull %r12d, %esi
testl %esi, %esi
jle .L143
movq %rbp, %rbx
movslq %esi, %rsi
leaq 0(%rbp,%rsi,4), %rbp
.L145:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
addl $1, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L145
.L143:
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2068:
.size _Z10RandomInitPfii, .-_Z10RandomInitPfii
.globl _Z8IdentityPfi
.type _Z8IdentityPfi, @function
_Z8IdentityPfi:
.LFB2069:
.cfi_startproc
endbr64
movl %esi, %r8d
imull %esi, %r8d
testl %r8d, %r8d
jle .L148
movslq %r8d, %r8
movl $0, %ecx
addl $1, %esi
pxor %xmm1, %xmm1
jmp .L151
.L150:
movss %xmm0, (%rdi,%rcx,4)
addq $1, %rcx
cmpq %r8, %rcx
je .L148
.L151:
movl %ecx, %eax
cltd
idivl %esi
movaps %xmm1, %xmm0
testl %edx, %edx
jne .L150
movss .LC2(%rip), %xmm0
jmp .L150
.L148:
ret
.cfi_endproc
.LFE2069:
.size _Z8IdentityPfi, .-_Z8IdentityPfi
.globl _Z10InitializePfS_S_S_S_S_S_S_S_S_ii
.type _Z10InitializePfS_S_S_S_S_S_S_S_S_ii, @function
_Z10InitializePfS_S_S_S_S_S_S_S_S_ii:
.LFB2070:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, 24(%rsp)
movq %r8, %r15
movq %r9, 32(%rsp)
movq 192(%rsp), %rax
movq %rax, 40(%rsp)
movq 200(%rsp), %r12
movq 208(%rsp), %r14
movq 216(%rsp), %r13
movl 224(%rsp), %ebx
movl 232(%rsp), %ebp
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $1, %edx
movl %ebx, %esi
call _Z10RandomInitPfii
movl $1, %edx
movl %ebp, %esi
movq 24(%rsp), %rdi
call _Z10RandomInitPfii
movl %ebx, %edx
movl %ebp, %esi
movq %r15, %rdi
call _Z10RandomInitPfii
movl %ebx, %ecx
movl %ebp, %edx
movq %r15, %rsi
movq %r12, %rdi
call _Z9transposePfS_ii
leaq 56(%rsp), %rdi
movl %ebx, %edx
movl %ebx, %esi
call _Z8memAllocPPfii
leaq 64(%rsp), %rdi
movl %ebx, %edx
movl %ebx, %esi
call _Z8memAllocPPfii
movq 56(%rsp), %r12
movl %ebx, %esi
movq %r12, %rdi
call _Z9generateLPfi
movq 64(%rsp), %r15
movl %ebx, %ecx
movl %ebx, %edx
movq %r12, %rsi
movq %r15, %rdi
call _Z9transposePfS_ii
subq $8, %rsp
.cfi_def_cfa_offset 200
pushq %rbx
.cfi_def_cfa_offset 208
movl %ebx, %r9d
movl %ebx, %r8d
movl %ebx, %ecx
movq %r15, %rdx
movq %r12, %rsi
movq 32(%rsp), %rdi
call _Z4multPfS_S_iiii
addq $16, %rsp
.cfi_def_cfa_offset 192
testq %r12, %r12
je .L155
movq %r12, %rdi
call free@PLT
.L155:
testq %r15, %r15
je .L156
movq %r15, %rdi
call free@PLT
.L156:
leaq 72(%rsp), %rdi
movl %ebx, %edx
movl %ebx, %esi
call _Z8memAllocPPfii
leaq 80(%rsp), %rdi
movl %ebx, %edx
movl %ebx, %esi
call _Z8memAllocPPfii
movq 72(%rsp), %r12
movl %ebx, %esi
movq %r12, %rdi
call _Z9generateLPfi
movq 80(%rsp), %r15
movl %ebx, %ecx
movl %ebx, %edx
movq %r12, %rsi
movq %r15, %rdi
call _Z9transposePfS_ii
subq $8, %rsp
.cfi_def_cfa_offset 200
pushq %rbx
.cfi_def_cfa_offset 208
movl %ebx, %r9d
movl %ebx, %r8d
movl %ebx, %ecx
movq %r15, %rdx
movq %r12, %rsi
movq 24(%rsp), %rdi
call _Z4multPfS_S_iiii
addq $16, %rsp
.cfi_def_cfa_offset 192
testq %r12, %r12
je .L157
movq %r12, %rdi
call free@PLT
.L157:
testq %r15, %r15
je .L158
movq %r15, %rdi
call free@PLT
.L158:
movl %ebx, %ecx
movl %ebx, %edx
movq 8(%rsp), %rsi
movq %r14, %rdi
call _Z9transposePfS_ii
leaq 88(%rsp), %rdi
movl %ebp, %edx
movl %ebp, %esi
call _Z8memAllocPPfii
leaq 96(%rsp), %rdi
movl %ebp, %edx
movl %ebp, %esi
call _Z8memAllocPPfii
movq 88(%rsp), %r12
movl %ebp, %esi
movq %r12, %rdi
call _Z9generateLPfi
movq 96(%rsp), %r14
movl %ebp, %ecx
movl %ebp, %edx
movq %r12, %rsi
movq %r14, %rdi
call _Z9transposePfS_ii
subq $8, %rsp
.cfi_def_cfa_offset 200
pushq %rbp
.cfi_def_cfa_offset 208
movl %ebp, %r9d
movl %ebp, %r8d
movl %ebp, %ecx
movq %r14, %rdx
movq %r12, %rsi
movq 48(%rsp), %rdi
call _Z4multPfS_S_iiii
addq $16, %rsp
.cfi_def_cfa_offset 192
testq %r12, %r12
je .L159
movq %r12, %rdi
call free@PLT
.L159:
testq %r14, %r14
je .L160
movq %r14, %rdi
call free@PLT
.L160:
leaq 104(%rsp), %rdi
movl %ebp, %edx
movl %ebp, %esi
call _Z8memAllocPPfii
leaq 112(%rsp), %rdi
movl %ebp, %edx
movl %ebp, %esi
call _Z8memAllocPPfii
movq 104(%rsp), %r12
movl %ebp, %esi
movq %r12, %rdi
call _Z9generateLPfi
movq 112(%rsp), %r14
movl %ebp, %ecx
movl %ebp, %edx
movq %r12, %rsi
movq %r14, %rdi
call _Z9transposePfS_ii
subq $8, %rsp
.cfi_def_cfa_offset 200
pushq %rbp
.cfi_def_cfa_offset 208
movl %ebp, %r9d
movl %ebp, %r8d
movl %ebp, %ecx
movq %r14, %rdx
movq %r12, %rsi
movq %r13, %rdi
call _Z4multPfS_S_iiii
addq $16, %rsp
.cfi_def_cfa_offset 192
testq %r12, %r12
je .L161
movq %r12, %rdi
call free@PLT
.L161:
testq %r14, %r14
je .L162
movq %r14, %rdi
call free@PLT
.L162:
movl %ebx, %esi
movq 40(%rsp), %rdi
call _Z8IdentityPfi
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L165
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L165:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size _Z10InitializePfS_S_S_S_S_S_S_S_S_ii, .-_Z10InitializePfS_S_S_S_S_S_S_S_S_ii
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2096:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl p
.bss
.align 8
.type p, @object
.size p, 8
p:
.zero 8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
//Global Variable Declaration
float* p;
//Memory Allocation Function
void memAlloc(float **data_ptr, int dim_x, int dim_y)
{
float *data;
data = (float *) malloc(sizeof(float *) * dim_x * dim_y);
*data_ptr = data;
}
//void cleanp()
//{
//if(p)
// free(p);
//}
/* ----------------------------------------------------
main method for Cholesky decomposition.
input n size of matrix
input/output a Symmetric positive def. matrix
output p vector of resulting diag of a
----------------------------------------------------- */
int choldc1(int n, float* a)
{
int i,j,k;
float sum;
for (i = 0; i < n; i++)
{
for (j = i; j < n; j++)
{
sum = a[i * n + j];
for (k = i - 1; k >= 0; k--)
{
sum -= a[i * n + k] * a[j * n + k];
}
if (i == j)
{
if (sum <= 0)
{
printf(" S is not positive definite!\n");
return 0;
}
p[i] = sqrt(sum);
}
else
{
a[j * n + i] = sum / p[i];
}
}
}
return 1;
}
/* -----------------------------------------------------
Inverse of Cholesky decomposition.
input n size of matrix
input A Symmetric positive def. matrix
output a inverse of lower deomposed matrix
uses choldc1(int,MAT,VEC)
----------------------------------------------------- */
int choldcsl(int n, float* A, float* a)
{
int i,j,k; float sum;
int success;
for (i = 0; i < n; i++)
for (j = 0; j < n; j++)
a[i * n + j] = A[i * n + j];
success = choldc1(n, a);
if (success == 0)
return 0;
for (i = 0; i < n; i++)
{
a[i * n + i] = 1 / p[i];
for (j = i + 1; j < n; j++)
{
sum = 0;
for (k = i; k < j; k++)
{
sum -= a[j * n + k] * a[k * n + i];
}
a[j * n + i] = sum / p[j];
}
}
return 1;
}
/* ---------------------------------------------------
Matrix inverse using Cholesky decomposition
input n size of matrix
input A Symmetric positive def. matrix
output a inverse of A
uses choldc1(MAT, VEC)
--------------------------------------------------- */
int inverse(int n, float* A, float* a)
{
int i,j,k,success;
//temp memory allocation for p
memAlloc(&p,n,n);
//printf("\n memory allocation done \n");
success = choldcsl(n,A,a);
if( success == 0)
{
//cleanp();
return 0;
}
for (i = 0; i < n; i++)
{
for (j = i + 1; j < n; j++)
{
a[i * n + j] = 0.0;
}
}
for (i = 0; i < n; i++)
{
a[i * n + i] *= a[i * n + i];
for (k = i + 1; k < n; k++)
{
a[i * n + i] += a[k * n + i] * a[k * n + i];
}
for (j = i + 1; j < n; j++)
{
for (k = j; k < n; k++)
{
a[i * n + j] += a[k * n + i] * a[k * n + j];
}
}
}
for (i = 0; i < n; i++)
{
for (j = 0; j < i; j++)
{
a[i * n + j] = a[j * n + i];
}
}
//cleanp();
return 1;
}
//Inversion Complete
//Other Matrix operations
//Addition
void add(float* C, float* A, float* B, int h, int w)
{
int i,j;
for (i = 0; i < h; i++)
{
for(j = 0; j < w ;j++)
{
C[i * w +j] = A[i * w + j] + B[i * w + j];
}
}
}
//subtraction
void sub(float* C, float* A, float* B, int h, int w)
{
int i,j;
for (i = 0; i < h; i++)
{
for(j = 0; j < w ;j++)
{
C[i * w + j] = A[i * w + j] - B[i * w + j];
}
}
}
//Multiplication
void mult(float* C, float* A, float* B, int ha, int wa, int hb, int wb)
{
int i,j,k;
float sum,a = 0,b = 0;
for (i = 0; i < ha; i++)
{
for(j = 0; j < wb ;j++)
{
sum = 0;
for(k = 0; k < wa; k++)
{
a = A[i * wa + k];
b = B[k * wb + j];
sum += a * b;
}
C[i * wb + j] = sum;
}
}
}
//Transpose
void transpose(float* B, float* A,int h, int w)
{
int i,j;
for (i = 0; i < h; i++)
{
for(j = 0; j < w ;j++)
{
B[j * h + i] = A[i * w + j];
}
}
}
//print the matrix
void matPrint(float *A, int h, int w)
{
int i,j;
for(i = 0;i < h;i++)
{
for(j = 0;j < w;j++)
{
printf("%f ", A[i * w + j]);
}
printf("\n");}
}
//Matrix Copy
void matcopy(float *B, float *A, int h, int w)
{
int i;
for(i = 0;i < (h*w);i++)
B[i] = A[i];
}
// generating L
void generateL(float *L, int n)
{
int i,j;
srand(1);
for (i = 0; i < n; i++)
{
for(j = 0; j < n ;j++)
{
if(j <= i)
L[i*n + j]= (rand() % 10) + 1;
else
L[i*n + j] = 0;
}
}
}
//Random Initialize
void RandomInit(float* data, int n1, int n2)
{
srand(1);
for (int i = 0; i < (n1*n2); ++i)
data[i] = (rand() % 10) + 1;
}
//Ideintity Matrix Generation
void Identity(float *data, int n)
{
for (int i = 0; i < (n*n); i=i+1)
{
if((i%(n+1))==0)
data[i] = 1;
else
data[i] = 0;
}
}
void Initialize(float *X,float *P,float *F,float *Z,float *H,float *E,float *I,float *Ht,float *Ft,float *s, int ns, int no)
{
RandomInit(X, ns, 1);
RandomInit(Z, no, 1);
RandomInit(H, no, ns);
transpose(Ht,H,no,ns);
//printf("\n Transpose of H successful\n");
float *P1;
float *P2;
memAlloc(&P1,ns,ns);
memAlloc(&P2,ns,ns);
generateL(P1,ns);
transpose(P2,P1,ns,ns);
mult(P,P1,P2,ns,ns,ns,ns);
if(P1)
free(P1);
if(P2)
free(P2);
float *F1;
float *F2;
memAlloc(&F1,ns,ns);
memAlloc(&F2,ns,ns);
generateL(F1,ns);
transpose(F2,F1,ns,ns);
mult(F,F1,F2,ns,ns,ns,ns);
if(F1)
free(F1);
if(F2)
free(F2);
transpose(Ft,F,ns,ns);
//printf("\n Transpose of F successful\n");
float *E1;
float *E2;
memAlloc(&E1,no,no);
memAlloc(&E2,no,no);
generateL(E1,no);
transpose(E2,E1,no,no);
mult(E,E1,E2,no,no,no,no);
if(E1)
free(E1);
if(E2)
free(E2);
float *s1;
float *s2;
memAlloc(&s1,no,no);
memAlloc(&s2,no,no);
generateL(s1,no);
transpose(s2,s1,no,no);
mult(s,s1,s2,no,no,no,no);
if(s1)
free(s1);
if(s2)
free(s2);
Identity(I, ns);
}
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
//Global Variable Declaration
float* p;
//Memory Allocation Function
void memAlloc(float **data_ptr, int dim_x, int dim_y)
{
float *data;
data = (float *) malloc(sizeof(float *) * dim_x * dim_y);
*data_ptr = data;
}
//void cleanp()
//{
//if(p)
// free(p);
//}
/* ----------------------------------------------------
main method for Cholesky decomposition.
input n size of matrix
input/output a Symmetric positive def. matrix
output p vector of resulting diag of a
----------------------------------------------------- */
int choldc1(int n, float* a)
{
int i,j,k;
float sum;
for (i = 0; i < n; i++)
{
for (j = i; j < n; j++)
{
sum = a[i * n + j];
for (k = i - 1; k >= 0; k--)
{
sum -= a[i * n + k] * a[j * n + k];
}
if (i == j)
{
if (sum <= 0)
{
printf(" S is not positive definite!\n");
return 0;
}
p[i] = sqrt(sum);
}
else
{
a[j * n + i] = sum / p[i];
}
}
}
return 1;
}
/* -----------------------------------------------------
Inverse of Cholesky decomposition.
input n size of matrix
input A Symmetric positive def. matrix
output a inverse of lower deomposed matrix
uses choldc1(int,MAT,VEC)
----------------------------------------------------- */
int choldcsl(int n, float* A, float* a)
{
int i,j,k; float sum;
int success;
for (i = 0; i < n; i++)
for (j = 0; j < n; j++)
a[i * n + j] = A[i * n + j];
success = choldc1(n, a);
if (success == 0)
return 0;
for (i = 0; i < n; i++)
{
a[i * n + i] = 1 / p[i];
for (j = i + 1; j < n; j++)
{
sum = 0;
for (k = i; k < j; k++)
{
sum -= a[j * n + k] * a[k * n + i];
}
a[j * n + i] = sum / p[j];
}
}
return 1;
}
/* ---------------------------------------------------
Matrix inverse using Cholesky decomposition
input n size of matrix
input A Symmetric positive def. matrix
output a inverse of A
uses choldc1(MAT, VEC)
--------------------------------------------------- */
int inverse(int n, float* A, float* a)
{
int i,j,k,success;
//temp memory allocation for p
memAlloc(&p,n,n);
//printf("\n memory allocation done \n");
success = choldcsl(n,A,a);
if( success == 0)
{
//cleanp();
return 0;
}
for (i = 0; i < n; i++)
{
for (j = i + 1; j < n; j++)
{
a[i * n + j] = 0.0;
}
}
for (i = 0; i < n; i++)
{
a[i * n + i] *= a[i * n + i];
for (k = i + 1; k < n; k++)
{
a[i * n + i] += a[k * n + i] * a[k * n + i];
}
for (j = i + 1; j < n; j++)
{
for (k = j; k < n; k++)
{
a[i * n + j] += a[k * n + i] * a[k * n + j];
}
}
}
for (i = 0; i < n; i++)
{
for (j = 0; j < i; j++)
{
a[i * n + j] = a[j * n + i];
}
}
//cleanp();
return 1;
}
//Inversion Complete
//Other Matrix operations
//Addition
void add(float* C, float* A, float* B, int h, int w)
{
int i,j;
for (i = 0; i < h; i++)
{
for(j = 0; j < w ;j++)
{
C[i * w +j] = A[i * w + j] + B[i * w + j];
}
}
}
//subtraction
void sub(float* C, float* A, float* B, int h, int w)
{
int i,j;
for (i = 0; i < h; i++)
{
for(j = 0; j < w ;j++)
{
C[i * w + j] = A[i * w + j] - B[i * w + j];
}
}
}
//Multiplication
void mult(float* C, float* A, float* B, int ha, int wa, int hb, int wb)
{
int i,j,k;
float sum,a = 0,b = 0;
for (i = 0; i < ha; i++)
{
for(j = 0; j < wb ;j++)
{
sum = 0;
for(k = 0; k < wa; k++)
{
a = A[i * wa + k];
b = B[k * wb + j];
sum += a * b;
}
C[i * wb + j] = sum;
}
}
}
//Transpose
void transpose(float* B, float* A,int h, int w)
{
int i,j;
for (i = 0; i < h; i++)
{
for(j = 0; j < w ;j++)
{
B[j * h + i] = A[i * w + j];
}
}
}
//print the matrix
void matPrint(float *A, int h, int w)
{
int i,j;
for(i = 0;i < h;i++)
{
for(j = 0;j < w;j++)
{
printf("%f ", A[i * w + j]);
}
printf("\n");}
}
//Matrix Copy
void matcopy(float *B, float *A, int h, int w)
{
int i;
for(i = 0;i < (h*w);i++)
B[i] = A[i];
}
// generating L
void generateL(float *L, int n)
{
int i,j;
srand(1);
for (i = 0; i < n; i++)
{
for(j = 0; j < n ;j++)
{
if(j <= i)
L[i*n + j]= (rand() % 10) + 1;
else
L[i*n + j] = 0;
}
}
}
//Random Initialize
void RandomInit(float* data, int n1, int n2)
{
srand(1);
for (int i = 0; i < (n1*n2); ++i)
data[i] = (rand() % 10) + 1;
}
//Ideintity Matrix Generation
void Identity(float *data, int n)
{
for (int i = 0; i < (n*n); i=i+1)
{
if((i%(n+1))==0)
data[i] = 1;
else
data[i] = 0;
}
}
void Initialize(float *X,float *P,float *F,float *Z,float *H,float *E,float *I,float *Ht,float *Ft,float *s, int ns, int no)
{
RandomInit(X, ns, 1);
RandomInit(Z, no, 1);
RandomInit(H, no, ns);
transpose(Ht,H,no,ns);
//printf("\n Transpose of H successful\n");
float *P1;
float *P2;
memAlloc(&P1,ns,ns);
memAlloc(&P2,ns,ns);
generateL(P1,ns);
transpose(P2,P1,ns,ns);
mult(P,P1,P2,ns,ns,ns,ns);
if(P1)
free(P1);
if(P2)
free(P2);
float *F1;
float *F2;
memAlloc(&F1,ns,ns);
memAlloc(&F2,ns,ns);
generateL(F1,ns);
transpose(F2,F1,ns,ns);
mult(F,F1,F2,ns,ns,ns,ns);
if(F1)
free(F1);
if(F2)
free(F2);
transpose(Ft,F,ns,ns);
//printf("\n Transpose of F successful\n");
float *E1;
float *E2;
memAlloc(&E1,no,no);
memAlloc(&E2,no,no);
generateL(E1,no);
transpose(E2,E1,no,no);
mult(E,E1,E2,no,no,no,no);
if(E1)
free(E1);
if(E2)
free(E2);
float *s1;
float *s2;
memAlloc(&s1,no,no);
memAlloc(&s2,no,no);
generateL(s1,no);
transpose(s2,s1,no,no);
mult(s,s1,s2,no,no,no,no);
if(s1)
free(s1);
if(s2)
free(s2);
Identity(I, ns);
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
//Global Variable Declaration
float* p;
//Memory Allocation Function
void memAlloc(float **data_ptr, int dim_x, int dim_y)
{
float *data;
data = (float *) malloc(sizeof(float *) * dim_x * dim_y);
*data_ptr = data;
}
//void cleanp()
//{
//if(p)
// free(p);
//}
/* ----------------------------------------------------
main method for Cholesky decomposition.
input n size of matrix
input/output a Symmetric positive def. matrix
output p vector of resulting diag of a
----------------------------------------------------- */
int choldc1(int n, float* a)
{
int i,j,k;
float sum;
for (i = 0; i < n; i++)
{
for (j = i; j < n; j++)
{
sum = a[i * n + j];
for (k = i - 1; k >= 0; k--)
{
sum -= a[i * n + k] * a[j * n + k];
}
if (i == j)
{
if (sum <= 0)
{
printf(" S is not positive definite!\n");
return 0;
}
p[i] = sqrt(sum);
}
else
{
a[j * n + i] = sum / p[i];
}
}
}
return 1;
}
/* -----------------------------------------------------
Inverse of Cholesky decomposition.
input n size of matrix
input A Symmetric positive def. matrix
output a inverse of lower deomposed matrix
uses choldc1(int,MAT,VEC)
----------------------------------------------------- */
int choldcsl(int n, float* A, float* a)
{
int i,j,k; float sum;
int success;
for (i = 0; i < n; i++)
for (j = 0; j < n; j++)
a[i * n + j] = A[i * n + j];
success = choldc1(n, a);
if (success == 0)
return 0;
for (i = 0; i < n; i++)
{
a[i * n + i] = 1 / p[i];
for (j = i + 1; j < n; j++)
{
sum = 0;
for (k = i; k < j; k++)
{
sum -= a[j * n + k] * a[k * n + i];
}
a[j * n + i] = sum / p[j];
}
}
return 1;
}
/* ---------------------------------------------------
Matrix inverse using Cholesky decomposition
input n size of matrix
input A Symmetric positive def. matrix
output a inverse of A
uses choldc1(MAT, VEC)
--------------------------------------------------- */
int inverse(int n, float* A, float* a)
{
int i,j,k,success;
//temp memory allocation for p
memAlloc(&p,n,n);
//printf("\n memory allocation done \n");
success = choldcsl(n,A,a);
if( success == 0)
{
//cleanp();
return 0;
}
for (i = 0; i < n; i++)
{
for (j = i + 1; j < n; j++)
{
a[i * n + j] = 0.0;
}
}
for (i = 0; i < n; i++)
{
a[i * n + i] *= a[i * n + i];
for (k = i + 1; k < n; k++)
{
a[i * n + i] += a[k * n + i] * a[k * n + i];
}
for (j = i + 1; j < n; j++)
{
for (k = j; k < n; k++)
{
a[i * n + j] += a[k * n + i] * a[k * n + j];
}
}
}
for (i = 0; i < n; i++)
{
for (j = 0; j < i; j++)
{
a[i * n + j] = a[j * n + i];
}
}
//cleanp();
return 1;
}
//Inversion Complete
//Other Matrix operations
//Addition
void add(float* C, float* A, float* B, int h, int w)
{
int i,j;
for (i = 0; i < h; i++)
{
for(j = 0; j < w ;j++)
{
C[i * w +j] = A[i * w + j] + B[i * w + j];
}
}
}
//subtraction
void sub(float* C, float* A, float* B, int h, int w)
{
int i,j;
for (i = 0; i < h; i++)
{
for(j = 0; j < w ;j++)
{
C[i * w + j] = A[i * w + j] - B[i * w + j];
}
}
}
//Multiplication
void mult(float* C, float* A, float* B, int ha, int wa, int hb, int wb)
{
int i,j,k;
float sum,a = 0,b = 0;
for (i = 0; i < ha; i++)
{
for(j = 0; j < wb ;j++)
{
sum = 0;
for(k = 0; k < wa; k++)
{
a = A[i * wa + k];
b = B[k * wb + j];
sum += a * b;
}
C[i * wb + j] = sum;
}
}
}
//Transpose
void transpose(float* B, float* A,int h, int w)
{
int i,j;
for (i = 0; i < h; i++)
{
for(j = 0; j < w ;j++)
{
B[j * h + i] = A[i * w + j];
}
}
}
//print the matrix
void matPrint(float *A, int h, int w)
{
int i,j;
for(i = 0;i < h;i++)
{
for(j = 0;j < w;j++)
{
printf("%f ", A[i * w + j]);
}
printf("\n");}
}
//Matrix Copy
void matcopy(float *B, float *A, int h, int w)
{
int i;
for(i = 0;i < (h*w);i++)
B[i] = A[i];
}
// generating L
void generateL(float *L, int n)
{
int i,j;
srand(1);
for (i = 0; i < n; i++)
{
for(j = 0; j < n ;j++)
{
if(j <= i)
L[i*n + j]= (rand() % 10) + 1;
else
L[i*n + j] = 0;
}
}
}
//Random Initialize
void RandomInit(float* data, int n1, int n2)
{
srand(1);
for (int i = 0; i < (n1*n2); ++i)
data[i] = (rand() % 10) + 1;
}
//Ideintity Matrix Generation
void Identity(float *data, int n)
{
for (int i = 0; i < (n*n); i=i+1)
{
if((i%(n+1))==0)
data[i] = 1;
else
data[i] = 0;
}
}
void Initialize(float *X,float *P,float *F,float *Z,float *H,float *E,float *I,float *Ht,float *Ft,float *s, int ns, int no)
{
RandomInit(X, ns, 1);
RandomInit(Z, no, 1);
RandomInit(H, no, ns);
transpose(Ht,H,no,ns);
//printf("\n Transpose of H successful\n");
float *P1;
float *P2;
memAlloc(&P1,ns,ns);
memAlloc(&P2,ns,ns);
generateL(P1,ns);
transpose(P2,P1,ns,ns);
mult(P,P1,P2,ns,ns,ns,ns);
if(P1)
free(P1);
if(P2)
free(P2);
float *F1;
float *F2;
memAlloc(&F1,ns,ns);
memAlloc(&F2,ns,ns);
generateL(F1,ns);
transpose(F2,F1,ns,ns);
mult(F,F1,F2,ns,ns,ns,ns);
if(F1)
free(F1);
if(F2)
free(F2);
transpose(Ft,F,ns,ns);
//printf("\n Transpose of F successful\n");
float *E1;
float *E2;
memAlloc(&E1,no,no);
memAlloc(&E2,no,no);
generateL(E1,no);
transpose(E2,E1,no,no);
mult(E,E1,E2,no,no,no,no);
if(E1)
free(E1);
if(E2)
free(E2);
float *s1;
float *s2;
memAlloc(&s1,no,no);
memAlloc(&s2,no,no);
generateL(s1,no);
transpose(s2,s1,no,no);
mult(s,s1,s2,no,no,no,no);
if(s1)
free(s1);
if(s2)
free(s2);
Identity(I, ns);
}
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <stdio.h>
#define N 16
#define BLOCK_SIZE 4
__global__ void transpose(int *input,int *output){
__shared__ int sharedMemory[BLOCK_SIZE][BLOCK_SIZE + 1];
//global index
int indexX = threadIdx.x + blockIdx.x*blockDim.x;
int indexY = threadIdx.y + blockIdx.y*blockDim.y;
//transposed index
int tindexX = threadIdx.x + blockIdx.y*blockDim.x;
int tindexY = threadIdx.y + blockIdx.x*blockDim.y;
//local index
int localIndexX = threadIdx.x;
int localIndexY = threadIdx.y;
int index = indexX*N + indexY;
int transposedIndex = tindexY*N + tindexX;
sharedMemory[localIndexX][localIndexY] = input[index];
__syncthreads();
output[transposedIndex] = sharedMemory[localIndexY][localIndexX];
}
void fill_data(int *data){
for(int idx=0;idx < N*N;idx++)
data[idx] = idx;
}
void print_matrix(int *data,int n){
for(int i = 0;i < n;i++){
for(int j = 0;j < n;j++){
printf("%4d ",data[i*n + j]);
}
printf("\n");
}
}
int main(void){
int *a,*b;
int *d_a,*d_b;
int size = N*N*sizeof(int);
a = (int*)malloc(size);
b = (int*)malloc(size);
fill_data(a);
cudaMalloc((void**)&d_a,size);
cudaMalloc((void**)&d_b,size);
cudaMemcpy(d_a,a,size,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b,size,cudaMemcpyHostToDevice);
dim3 blockSize(BLOCK_SIZE,BLOCK_SIZE,1);
dim3 gridSize(N/BLOCK_SIZE,N/BLOCK_SIZE,1);
transpose<<<blockSize,gridSize>>>(d_a,d_b);
cudaMemcpy(b,d_b,size,cudaMemcpyDeviceToHost);
printf("Original:\n");
print_matrix(a,N);
printf("Transposed:\n");
print_matrix(b,N);
free(a);
free(b);
cudaFree(d_a);
cudaFree(d_b);
}
|
code for sm_80
Function : _Z9transposePiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0050*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000e680000002200 */
/*0060*/ S2R R6, SR_CTAID.Y ; /* 0x0000000000067919 */
/* 0x000e620000002600 */
/*0070*/ IMAD R0, R5, c[0x0][0x0], R4 ; /* 0x0000000005007a24 */
/* 0x001fc400078e0204 */
/*0080*/ IMAD R3, R6, c[0x0][0x4], R9 ; /* 0x0000010006037a24 */
/* 0x002fca00078e0209 */
/*0090*/ LEA R3, R0, R3, 0x4 ; /* 0x0000000300037211 */
/* 0x000fca00078e20ff */
/*00a0*/ IMAD.WIDE R2, R3, R8, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fcc00078e0208 */
/*00b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD R11, R4, 0x5, R9.reuse ; /* 0x00000005040b7824 */
/* 0x100fe400078e0209 */
/*00d0*/ IMAD R7, R9, 0x5, R4.reuse ; /* 0x0000000509077824 */
/* 0x100fe400078e0204 */
/*00e0*/ IMAD R5, R5, c[0x0][0x4], R9 ; /* 0x0000010005057a24 */
/* 0x000fe400078e0209 */
/*00f0*/ IMAD R0, R6, c[0x0][0x0], R4 ; /* 0x0000000006007a24 */
/* 0x000fca00078e0204 */
/*0100*/ LEA R5, R5, R0, 0x4 ; /* 0x0000000005057211 */
/* 0x000fca00078e20ff */
/*0110*/ IMAD.WIDE R4, R5, R8, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fe200078e0208 */
/*0120*/ STS [R11.X4], R2 ; /* 0x000000020b007388 */
/* 0x004fe80000004800 */
/*0130*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0140*/ LDS R7, [R7.X4] ; /* 0x0000000007077984 */
/* 0x000e280000004800 */
/*0150*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x001fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
#define N 16
#define BLOCK_SIZE 4
__global__ void transpose(int *input,int *output){
__shared__ int sharedMemory[BLOCK_SIZE][BLOCK_SIZE + 1];
//global index
int indexX = threadIdx.x + blockIdx.x*blockDim.x;
int indexY = threadIdx.y + blockIdx.y*blockDim.y;
//transposed index
int tindexX = threadIdx.x + blockIdx.y*blockDim.x;
int tindexY = threadIdx.y + blockIdx.x*blockDim.y;
//local index
int localIndexX = threadIdx.x;
int localIndexY = threadIdx.y;
int index = indexX*N + indexY;
int transposedIndex = tindexY*N + tindexX;
sharedMemory[localIndexX][localIndexY] = input[index];
__syncthreads();
output[transposedIndex] = sharedMemory[localIndexY][localIndexX];
}
void fill_data(int *data){
for(int idx=0;idx < N*N;idx++)
data[idx] = idx;
}
void print_matrix(int *data,int n){
for(int i = 0;i < n;i++){
for(int j = 0;j < n;j++){
printf("%4d ",data[i*n + j]);
}
printf("\n");
}
}
int main(void){
int *a,*b;
int *d_a,*d_b;
int size = N*N*sizeof(int);
a = (int*)malloc(size);
b = (int*)malloc(size);
fill_data(a);
cudaMalloc((void**)&d_a,size);
cudaMalloc((void**)&d_b,size);
cudaMemcpy(d_a,a,size,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b,size,cudaMemcpyHostToDevice);
dim3 blockSize(BLOCK_SIZE,BLOCK_SIZE,1);
dim3 gridSize(N/BLOCK_SIZE,N/BLOCK_SIZE,1);
transpose<<<blockSize,gridSize>>>(d_a,d_b);
cudaMemcpy(b,d_b,size,cudaMemcpyDeviceToHost);
printf("Original:\n");
print_matrix(a,N);
printf("Transposed:\n");
print_matrix(b,N);
free(a);
free(b);
cudaFree(d_a);
cudaFree(d_b);
}
|
.file "tmpxft_0001b29b_00000000-6_transpose.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9fill_dataPi
.type _Z9fill_dataPi, @function
_Z9fill_dataPi:
.LFB2057:
.cfi_startproc
endbr64
movl $0, %eax
.L4:
movl %eax, (%rdi,%rax,4)
addq $1, %rax
cmpq $256, %rax
jne .L4
ret
.cfi_endproc
.LFE2057:
.size _Z9fill_dataPi, .-_Z9fill_dataPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%4d "
.LC1:
.string "\n"
.text
.globl _Z12print_matrixPii
.type _Z12print_matrixPii, @function
_Z12print_matrixPii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L6
movslq %esi, %r14
leaq 0(,%r14,4), %r15
leaq (%rdi,%r15), %rbp
negq %r14
salq $2, %r14
movl $0, %r13d
leaq .LC0(%rip), %r12
.L8:
leaq 0(%rbp,%r14), %rbx
.L9:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L9
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addq %r15, %rbp
cmpl %r13d, 12(%rsp)
jne .L8
.L6:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z12print_matrixPii, .-_Z12print_matrixPii
.globl _Z30__device_stub__Z9transposePiS_PiS_
.type _Z30__device_stub__Z9transposePiS_PiS_, @function
_Z30__device_stub__Z9transposePiS_PiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9transposePiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z30__device_stub__Z9transposePiS_PiS_, .-_Z30__device_stub__Z9transposePiS_PiS_
.globl _Z9transposePiS_
.type _Z9transposePiS_, @function
_Z9transposePiS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9transposePiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z9transposePiS_, .-_Z9transposePiS_
.section .rodata.str1.1
.LC2:
.string "Original:\n"
.LC3:
.string "Transposed:\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $1024, %edi
call malloc@PLT
movq %rax, %rbp
movl $1024, %edi
call malloc@PLT
movq %rax, %rbx
movq %rbp, %rdi
call _Z9fill_dataPi
movq %rsp, %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $1024, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1024, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 16(%rsp)
movl $4, 20(%rsp)
movl $4, 28(%rsp)
movl $4, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L21:
movl $2, %ecx
movl $1024, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16, %esi
movq %rbp, %rdi
call _Z12print_matrixPii
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16, %esi
movq %rbx, %rdi
call _Z12print_matrixPii
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z30__device_stub__Z9transposePiS_PiS_
jmp .L21
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z9transposePiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z9transposePiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
#define N 16
#define BLOCK_SIZE 4
__global__ void transpose(int *input,int *output){
__shared__ int sharedMemory[BLOCK_SIZE][BLOCK_SIZE + 1];
//global index
int indexX = threadIdx.x + blockIdx.x*blockDim.x;
int indexY = threadIdx.y + blockIdx.y*blockDim.y;
//transposed index
int tindexX = threadIdx.x + blockIdx.y*blockDim.x;
int tindexY = threadIdx.y + blockIdx.x*blockDim.y;
//local index
int localIndexX = threadIdx.x;
int localIndexY = threadIdx.y;
int index = indexX*N + indexY;
int transposedIndex = tindexY*N + tindexX;
sharedMemory[localIndexX][localIndexY] = input[index];
__syncthreads();
output[transposedIndex] = sharedMemory[localIndexY][localIndexX];
}
void fill_data(int *data){
for(int idx=0;idx < N*N;idx++)
data[idx] = idx;
}
void print_matrix(int *data,int n){
for(int i = 0;i < n;i++){
for(int j = 0;j < n;j++){
printf("%4d ",data[i*n + j]);
}
printf("\n");
}
}
int main(void){
int *a,*b;
int *d_a,*d_b;
int size = N*N*sizeof(int);
a = (int*)malloc(size);
b = (int*)malloc(size);
fill_data(a);
cudaMalloc((void**)&d_a,size);
cudaMalloc((void**)&d_b,size);
cudaMemcpy(d_a,a,size,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b,size,cudaMemcpyHostToDevice);
dim3 blockSize(BLOCK_SIZE,BLOCK_SIZE,1);
dim3 gridSize(N/BLOCK_SIZE,N/BLOCK_SIZE,1);
transpose<<<blockSize,gridSize>>>(d_a,d_b);
cudaMemcpy(b,d_b,size,cudaMemcpyDeviceToHost);
printf("Original:\n");
print_matrix(a,N);
printf("Transposed:\n");
print_matrix(b,N);
free(a);
free(b);
cudaFree(d_a);
cudaFree(d_b);
}
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#define N 16
#define BLOCK_SIZE 4
__global__ void transpose(int *input,int *output){
__shared__ int sharedMemory[BLOCK_SIZE][BLOCK_SIZE + 1];
//global index
int indexX = threadIdx.x + blockIdx.x*blockDim.x;
int indexY = threadIdx.y + blockIdx.y*blockDim.y;
//transposed index
int tindexX = threadIdx.x + blockIdx.y*blockDim.x;
int tindexY = threadIdx.y + blockIdx.x*blockDim.y;
//local index
int localIndexX = threadIdx.x;
int localIndexY = threadIdx.y;
int index = indexX*N + indexY;
int transposedIndex = tindexY*N + tindexX;
sharedMemory[localIndexX][localIndexY] = input[index];
__syncthreads();
output[transposedIndex] = sharedMemory[localIndexY][localIndexX];
}
void fill_data(int *data){
for(int idx=0;idx < N*N;idx++)
data[idx] = idx;
}
void print_matrix(int *data,int n){
for(int i = 0;i < n;i++){
for(int j = 0;j < n;j++){
printf("%4d ",data[i*n + j]);
}
printf("\n");
}
}
int main(void){
int *a,*b;
int *d_a,*d_b;
int size = N*N*sizeof(int);
a = (int*)malloc(size);
b = (int*)malloc(size);
fill_data(a);
hipMalloc((void**)&d_a,size);
hipMalloc((void**)&d_b,size);
hipMemcpy(d_a,a,size,hipMemcpyHostToDevice);
hipMemcpy(d_b,b,size,hipMemcpyHostToDevice);
dim3 blockSize(BLOCK_SIZE,BLOCK_SIZE,1);
dim3 gridSize(N/BLOCK_SIZE,N/BLOCK_SIZE,1);
transpose<<<blockSize,gridSize>>>(d_a,d_b);
hipMemcpy(b,d_b,size,hipMemcpyDeviceToHost);
printf("Original:\n");
print_matrix(a,N);
printf("Transposed:\n");
print_matrix(b,N);
free(a);
free(b);
hipFree(d_a);
hipFree(d_b);
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#define N 16
#define BLOCK_SIZE 4
__global__ void transpose(int *input,int *output){
__shared__ int sharedMemory[BLOCK_SIZE][BLOCK_SIZE + 1];
//global index
int indexX = threadIdx.x + blockIdx.x*blockDim.x;
int indexY = threadIdx.y + blockIdx.y*blockDim.y;
//transposed index
int tindexX = threadIdx.x + blockIdx.y*blockDim.x;
int tindexY = threadIdx.y + blockIdx.x*blockDim.y;
//local index
int localIndexX = threadIdx.x;
int localIndexY = threadIdx.y;
int index = indexX*N + indexY;
int transposedIndex = tindexY*N + tindexX;
sharedMemory[localIndexX][localIndexY] = input[index];
__syncthreads();
output[transposedIndex] = sharedMemory[localIndexY][localIndexX];
}
void fill_data(int *data){
for(int idx=0;idx < N*N;idx++)
data[idx] = idx;
}
void print_matrix(int *data,int n){
for(int i = 0;i < n;i++){
for(int j = 0;j < n;j++){
printf("%4d ",data[i*n + j]);
}
printf("\n");
}
}
int main(void){
int *a,*b;
int *d_a,*d_b;
int size = N*N*sizeof(int);
a = (int*)malloc(size);
b = (int*)malloc(size);
fill_data(a);
hipMalloc((void**)&d_a,size);
hipMalloc((void**)&d_b,size);
hipMemcpy(d_a,a,size,hipMemcpyHostToDevice);
hipMemcpy(d_b,b,size,hipMemcpyHostToDevice);
dim3 blockSize(BLOCK_SIZE,BLOCK_SIZE,1);
dim3 gridSize(N/BLOCK_SIZE,N/BLOCK_SIZE,1);
transpose<<<blockSize,gridSize>>>(d_a,d_b);
hipMemcpy(b,d_b,size,hipMemcpyDeviceToHost);
printf("Original:\n");
print_matrix(a,N);
printf("Transposed:\n");
print_matrix(b,N);
free(a);
free(b);
hipFree(d_a);
hipFree(d_b);
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9transposePiS_
.globl _Z9transposePiS_
.p2align 8
.type _Z9transposePiS_,@function
_Z9transposePiS_:
s_load_b32 s4, s[0:1], 0x1c
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b32_e32 v4, 2, v2
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_mul_i32 s6, s14, s5
s_mul_i32 s14, s14, s4
v_add_lshl_u32 v0, s6, v2, 4
s_mul_i32 s6, s15, s4
v_add_lshl_u32 v5, s14, v3, 4
s_mul_i32 s15, s15, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, s6, v3, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v1, v[0:1], off
v_lshlrev_b32_e32 v0, 2, v3
v_mad_u32_u24 v3, v3, 20, v4
v_mad_u32_u24 v6, v2, 20, v0
v_add3_u32 v0, s15, v2, v5
s_waitcnt vmcnt(0)
ds_store_b32 v6, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v2, v3
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9transposePiS_
.amdhsa_group_segment_fixed_size 80
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9transposePiS_, .Lfunc_end0-_Z9transposePiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 80
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9transposePiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9transposePiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#define N 16
#define BLOCK_SIZE 4
__global__ void transpose(int *input,int *output){
__shared__ int sharedMemory[BLOCK_SIZE][BLOCK_SIZE + 1];
//global index
int indexX = threadIdx.x + blockIdx.x*blockDim.x;
int indexY = threadIdx.y + blockIdx.y*blockDim.y;
//transposed index
int tindexX = threadIdx.x + blockIdx.y*blockDim.x;
int tindexY = threadIdx.y + blockIdx.x*blockDim.y;
//local index
int localIndexX = threadIdx.x;
int localIndexY = threadIdx.y;
int index = indexX*N + indexY;
int transposedIndex = tindexY*N + tindexX;
sharedMemory[localIndexX][localIndexY] = input[index];
__syncthreads();
output[transposedIndex] = sharedMemory[localIndexY][localIndexX];
}
void fill_data(int *data){
for(int idx=0;idx < N*N;idx++)
data[idx] = idx;
}
void print_matrix(int *data,int n){
for(int i = 0;i < n;i++){
for(int j = 0;j < n;j++){
printf("%4d ",data[i*n + j]);
}
printf("\n");
}
}
int main(void){
int *a,*b;
int *d_a,*d_b;
int size = N*N*sizeof(int);
a = (int*)malloc(size);
b = (int*)malloc(size);
fill_data(a);
hipMalloc((void**)&d_a,size);
hipMalloc((void**)&d_b,size);
hipMemcpy(d_a,a,size,hipMemcpyHostToDevice);
hipMemcpy(d_b,b,size,hipMemcpyHostToDevice);
dim3 blockSize(BLOCK_SIZE,BLOCK_SIZE,1);
dim3 gridSize(N/BLOCK_SIZE,N/BLOCK_SIZE,1);
transpose<<<blockSize,gridSize>>>(d_a,d_b);
hipMemcpy(b,d_b,size,hipMemcpyDeviceToHost);
printf("Original:\n");
print_matrix(a,N);
printf("Transposed:\n");
print_matrix(b,N);
free(a);
free(b);
hipFree(d_a);
hipFree(d_b);
}
|
.text
.file "transpose.hip"
.globl _Z24__device_stub__transposePiS_ # -- Begin function _Z24__device_stub__transposePiS_
.p2align 4, 0x90
.type _Z24__device_stub__transposePiS_,@function
_Z24__device_stub__transposePiS_: # @_Z24__device_stub__transposePiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9transposePiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__transposePiS_, .Lfunc_end0-_Z24__device_stub__transposePiS_
.cfi_endproc
# -- End function
.globl _Z9fill_dataPi # -- Begin function _Z9fill_dataPi
.p2align 4, 0x90
.type _Z9fill_dataPi,@function
_Z9fill_dataPi: # @_Z9fill_dataPi
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%rdi,%rax,4)
incq %rax
cmpq $256, %rax # imm = 0x100
jne .LBB1_1
# %bb.2:
retq
.Lfunc_end1:
.size _Z9fill_dataPi, .Lfunc_end1-_Z9fill_dataPi
.cfi_endproc
# -- End function
.globl _Z12print_matrixPii # -- Begin function _Z12print_matrixPii
.p2align 4, 0x90
.type _Z12print_matrixPii,@function
_Z12print_matrixPii: # @_Z12print_matrixPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, (%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB2_5
# %bb.1: # %.preheader.lr.ph
movl %esi, %ebx
movl %esi, %r15d
xorl %ebp, %ebp
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
movl %ebp, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r13
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r13,%r14,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq %r14, %r15
jne .LBB2_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
addl %ebx, %ebp
cmpq %r15, %r12
jne .LBB2_2
.LBB2_5: # %._crit_edge13
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z12print_matrixPii, .Lfunc_end2-_Z12print_matrixPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $96, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %rbx
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%rbx,%rax,4)
incq %rax
cmpq $256, %rax # imm = 0x100
jne .LBB3_1
# %bb.2: # %_Z9fill_dataPi.exit
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq %rsp, %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq 8(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $1024, %edx # imm = 0x400
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $17179869188, %rdi # imm = 0x400000004
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9transposePiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
movq (%rsp), %rsi
movl $1024, %edx # imm = 0x400
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
movq %rbx, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_5: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_6: # Parent Loop BB3_5 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r15,%r13,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r13
cmpq $16, %r13
jne .LBB3_6
# %bb.7: # %._crit_edge.i
# in Loop: Header=BB3_5 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
addq $64, %r15
cmpq $16, %r12
jne .LBB3_5
# %bb.8: # %_Z12print_matrixPii.exit
movl $.Lstr.1, %edi
callq puts@PLT
movq %r14, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_9: # %.preheader.i25
# =>This Loop Header: Depth=1
# Child Loop BB3_10 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_10: # Parent Loop BB3_9 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r15,%r13,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r13
cmpq $16, %r13
jne .LBB3_10
# %bb.11: # %._crit_edge.i30
# in Loop: Header=BB3_9 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
addq $64, %r15
cmpq $16, %r12
jne .LBB3_9
# %bb.12: # %_Z12print_matrixPii.exit34
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9transposePiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9transposePiS_,@object # @_Z9transposePiS_
.section .rodata,"a",@progbits
.globl _Z9transposePiS_
.p2align 3, 0x0
_Z9transposePiS_:
.quad _Z24__device_stub__transposePiS_
.size _Z9transposePiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%4d "
.size .L.str, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9transposePiS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Original:"
.size .Lstr, 10
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Transposed:"
.size .Lstr.1, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__transposePiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9transposePiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z9transposePiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0050*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000e680000002200 */
/*0060*/ S2R R6, SR_CTAID.Y ; /* 0x0000000000067919 */
/* 0x000e620000002600 */
/*0070*/ IMAD R0, R5, c[0x0][0x0], R4 ; /* 0x0000000005007a24 */
/* 0x001fc400078e0204 */
/*0080*/ IMAD R3, R6, c[0x0][0x4], R9 ; /* 0x0000010006037a24 */
/* 0x002fca00078e0209 */
/*0090*/ LEA R3, R0, R3, 0x4 ; /* 0x0000000300037211 */
/* 0x000fca00078e20ff */
/*00a0*/ IMAD.WIDE R2, R3, R8, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fcc00078e0208 */
/*00b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD R11, R4, 0x5, R9.reuse ; /* 0x00000005040b7824 */
/* 0x100fe400078e0209 */
/*00d0*/ IMAD R7, R9, 0x5, R4.reuse ; /* 0x0000000509077824 */
/* 0x100fe400078e0204 */
/*00e0*/ IMAD R5, R5, c[0x0][0x4], R9 ; /* 0x0000010005057a24 */
/* 0x000fe400078e0209 */
/*00f0*/ IMAD R0, R6, c[0x0][0x0], R4 ; /* 0x0000000006007a24 */
/* 0x000fca00078e0204 */
/*0100*/ LEA R5, R5, R0, 0x4 ; /* 0x0000000005057211 */
/* 0x000fca00078e20ff */
/*0110*/ IMAD.WIDE R4, R5, R8, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fe200078e0208 */
/*0120*/ STS [R11.X4], R2 ; /* 0x000000020b007388 */
/* 0x004fe80000004800 */
/*0130*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0140*/ LDS R7, [R7.X4] ; /* 0x0000000007077984 */
/* 0x000e280000004800 */
/*0150*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x001fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9transposePiS_
.globl _Z9transposePiS_
.p2align 8
.type _Z9transposePiS_,@function
_Z9transposePiS_:
s_load_b32 s4, s[0:1], 0x1c
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b32_e32 v4, 2, v2
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_mul_i32 s6, s14, s5
s_mul_i32 s14, s14, s4
v_add_lshl_u32 v0, s6, v2, 4
s_mul_i32 s6, s15, s4
v_add_lshl_u32 v5, s14, v3, 4
s_mul_i32 s15, s15, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, s6, v3, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v1, v[0:1], off
v_lshlrev_b32_e32 v0, 2, v3
v_mad_u32_u24 v3, v3, 20, v4
v_mad_u32_u24 v6, v2, 20, v0
v_add3_u32 v0, s15, v2, v5
s_waitcnt vmcnt(0)
ds_store_b32 v6, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v2, v3
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9transposePiS_
.amdhsa_group_segment_fixed_size 80
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9transposePiS_, .Lfunc_end0-_Z9transposePiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 80
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9transposePiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9transposePiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0001b29b_00000000-6_transpose.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9fill_dataPi
.type _Z9fill_dataPi, @function
_Z9fill_dataPi:
.LFB2057:
.cfi_startproc
endbr64
movl $0, %eax
.L4:
movl %eax, (%rdi,%rax,4)
addq $1, %rax
cmpq $256, %rax
jne .L4
ret
.cfi_endproc
.LFE2057:
.size _Z9fill_dataPi, .-_Z9fill_dataPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%4d "
.LC1:
.string "\n"
.text
.globl _Z12print_matrixPii
.type _Z12print_matrixPii, @function
_Z12print_matrixPii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L6
movslq %esi, %r14
leaq 0(,%r14,4), %r15
leaq (%rdi,%r15), %rbp
negq %r14
salq $2, %r14
movl $0, %r13d
leaq .LC0(%rip), %r12
.L8:
leaq 0(%rbp,%r14), %rbx
.L9:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L9
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addq %r15, %rbp
cmpl %r13d, 12(%rsp)
jne .L8
.L6:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z12print_matrixPii, .-_Z12print_matrixPii
.globl _Z30__device_stub__Z9transposePiS_PiS_
.type _Z30__device_stub__Z9transposePiS_PiS_, @function
_Z30__device_stub__Z9transposePiS_PiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9transposePiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z30__device_stub__Z9transposePiS_PiS_, .-_Z30__device_stub__Z9transposePiS_PiS_
.globl _Z9transposePiS_
.type _Z9transposePiS_, @function
_Z9transposePiS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9transposePiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z9transposePiS_, .-_Z9transposePiS_
.section .rodata.str1.1
.LC2:
.string "Original:\n"
.LC3:
.string "Transposed:\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $1024, %edi
call malloc@PLT
movq %rax, %rbp
movl $1024, %edi
call malloc@PLT
movq %rax, %rbx
movq %rbp, %rdi
call _Z9fill_dataPi
movq %rsp, %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $1024, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1024, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 16(%rsp)
movl $4, 20(%rsp)
movl $4, 28(%rsp)
movl $4, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L21:
movl $2, %ecx
movl $1024, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16, %esi
movq %rbp, %rdi
call _Z12print_matrixPii
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16, %esi
movq %rbx, %rdi
call _Z12print_matrixPii
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z30__device_stub__Z9transposePiS_PiS_
jmp .L21
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z9transposePiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z9transposePiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "transpose.hip"
.globl _Z24__device_stub__transposePiS_ # -- Begin function _Z24__device_stub__transposePiS_
.p2align 4, 0x90
.type _Z24__device_stub__transposePiS_,@function
_Z24__device_stub__transposePiS_: # @_Z24__device_stub__transposePiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9transposePiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__transposePiS_, .Lfunc_end0-_Z24__device_stub__transposePiS_
.cfi_endproc
# -- End function
.globl _Z9fill_dataPi # -- Begin function _Z9fill_dataPi
.p2align 4, 0x90
.type _Z9fill_dataPi,@function
_Z9fill_dataPi: # @_Z9fill_dataPi
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%rdi,%rax,4)
incq %rax
cmpq $256, %rax # imm = 0x100
jne .LBB1_1
# %bb.2:
retq
.Lfunc_end1:
.size _Z9fill_dataPi, .Lfunc_end1-_Z9fill_dataPi
.cfi_endproc
# -- End function
.globl _Z12print_matrixPii # -- Begin function _Z12print_matrixPii
.p2align 4, 0x90
.type _Z12print_matrixPii,@function
_Z12print_matrixPii: # @_Z12print_matrixPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, (%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB2_5
# %bb.1: # %.preheader.lr.ph
movl %esi, %ebx
movl %esi, %r15d
xorl %ebp, %ebp
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
movl %ebp, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r13
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r13,%r14,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq %r14, %r15
jne .LBB2_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
addl %ebx, %ebp
cmpq %r15, %r12
jne .LBB2_2
.LBB2_5: # %._crit_edge13
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z12print_matrixPii, .Lfunc_end2-_Z12print_matrixPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $96, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %rbx
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%rbx,%rax,4)
incq %rax
cmpq $256, %rax # imm = 0x100
jne .LBB3_1
# %bb.2: # %_Z9fill_dataPi.exit
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq %rsp, %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq 8(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $1024, %edx # imm = 0x400
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $17179869188, %rdi # imm = 0x400000004
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9transposePiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
movq (%rsp), %rsi
movl $1024, %edx # imm = 0x400
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
movq %rbx, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_5: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_6: # Parent Loop BB3_5 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r15,%r13,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r13
cmpq $16, %r13
jne .LBB3_6
# %bb.7: # %._crit_edge.i
# in Loop: Header=BB3_5 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
addq $64, %r15
cmpq $16, %r12
jne .LBB3_5
# %bb.8: # %_Z12print_matrixPii.exit
movl $.Lstr.1, %edi
callq puts@PLT
movq %r14, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_9: # %.preheader.i25
# =>This Loop Header: Depth=1
# Child Loop BB3_10 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_10: # Parent Loop BB3_9 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r15,%r13,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r13
cmpq $16, %r13
jne .LBB3_10
# %bb.11: # %._crit_edge.i30
# in Loop: Header=BB3_9 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
addq $64, %r15
cmpq $16, %r12
jne .LBB3_9
# %bb.12: # %_Z12print_matrixPii.exit34
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9transposePiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9transposePiS_,@object # @_Z9transposePiS_
.section .rodata,"a",@progbits
.globl _Z9transposePiS_
.p2align 3, 0x0
_Z9transposePiS_:
.quad _Z24__device_stub__transposePiS_
.size _Z9transposePiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%4d "
.size .L.str, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9transposePiS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Original:"
.size .Lstr, 10
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Transposed:"
.size .Lstr.1, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__transposePiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9transposePiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <stdio.h>
// Device code
__global__ void VecAdd(float* A, float* B, float* C, int N)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < N)
C[i] = A[i] + B[i];
}
// Initialise the input vectors
void initialise_input_vect(float* A, float* B, int N)
{
for(int i=0; i<N; i++){
A[i]=i;
B[i]=2*i;
}
}
// Host code
int main()
{
int N = 1000; // Number of elements to process
bool print_results = 0; // Boolean variable for printing the results
size_t size = N * sizeof(float);
//==========================================================================
// Get the GPUs properties:
// Device name, Compute Capability, Global Memory (GB) etc
int nDevices;
cudaGetDeviceCount(&nDevices);
for (int i = 0; i < nDevices; i++) {
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, i);
printf("Device Number: %d\n", i);
printf(" Device name: %s\n", prop.name);
printf(" Compute Capability: %d.%d\n", prop.major, prop.minor);
printf(" Total Global Mem: %.1fGB\n\n", ((double)prop.totalGlobalMem/1073741824.0));
printf(" Memory Clock Rate (KHz): %d\n",
prop.memoryClockRate);
printf(" Memory Bus Width (bits): %d\n",
prop.memoryBusWidth);
printf(" Peak Memory Bandwidth (GB/s): %f\n\n",
2.0*prop.memoryClockRate*(prop.memoryBusWidth/8)/1.0e6);
printf(" Max Number of Threads per Block: %d\n", prop.maxThreadsPerBlock);
printf(" Max Number of Blocks allowed in x-dir: %d\n", prop.maxGridSize[0]);
printf(" Max Number of Blocks allowed in y-dir: %d\n", prop.maxGridSize[1]);
printf(" Max Number of Blocks allowed in z-dir: %d\n", prop.maxGridSize[2]);
printf(" Warp Size: %d\n", prop.warpSize);
printf("===============================================\n\n");
}
//==========================================================================
// Allocate input vectors h_A and h_B in host memory
float* h_A = new float[N];
float* h_B = new float[N];
float* h_C = new float[N];
// Initialize input vectors
initialise_input_vect(h_A, h_B, N);
// Allocate vectors in device memory
float* d_A;
cudaMalloc(&d_A, size);
float* d_B;
cudaMalloc(&d_B, size);
float* d_C;
cudaMalloc(&d_C, size);
// Copy vectors from host memory to device memory
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
// Invoke kernel
int nThreadsPerBlock = 256;
int nblocks = (N / nThreadsPerBlock) + ((N % nThreadsPerBlock > 0) ? 1 : 0);
VecAdd<<<nblocks, nThreadsPerBlock>>>(d_A, d_B, d_C, N);
// Copy result from device memory to host memory
// h_C contains the result in host memory
cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
// Print the results
if(print_results) for (int i=0; i<N; i++) printf("h_C[%d] = %2.2f \n", i, h_C[i] );
// Free device memory
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
// Free host memory
delete[] h_A, h_B, h_C;
}
|
code for sm_80
Function : _Z6VecAddPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
// Device code
__global__ void VecAdd(float* A, float* B, float* C, int N)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < N)
C[i] = A[i] + B[i];
}
// Initialise the input vectors
void initialise_input_vect(float* A, float* B, int N)
{
for(int i=0; i<N; i++){
A[i]=i;
B[i]=2*i;
}
}
// Host code
int main()
{
int N = 1000; // Number of elements to process
bool print_results = 0; // Boolean variable for printing the results
size_t size = N * sizeof(float);
//==========================================================================
// Get the GPUs properties:
// Device name, Compute Capability, Global Memory (GB) etc
int nDevices;
cudaGetDeviceCount(&nDevices);
for (int i = 0; i < nDevices; i++) {
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, i);
printf("Device Number: %d\n", i);
printf(" Device name: %s\n", prop.name);
printf(" Compute Capability: %d.%d\n", prop.major, prop.minor);
printf(" Total Global Mem: %.1fGB\n\n", ((double)prop.totalGlobalMem/1073741824.0));
printf(" Memory Clock Rate (KHz): %d\n",
prop.memoryClockRate);
printf(" Memory Bus Width (bits): %d\n",
prop.memoryBusWidth);
printf(" Peak Memory Bandwidth (GB/s): %f\n\n",
2.0*prop.memoryClockRate*(prop.memoryBusWidth/8)/1.0e6);
printf(" Max Number of Threads per Block: %d\n", prop.maxThreadsPerBlock);
printf(" Max Number of Blocks allowed in x-dir: %d\n", prop.maxGridSize[0]);
printf(" Max Number of Blocks allowed in y-dir: %d\n", prop.maxGridSize[1]);
printf(" Max Number of Blocks allowed in z-dir: %d\n", prop.maxGridSize[2]);
printf(" Warp Size: %d\n", prop.warpSize);
printf("===============================================\n\n");
}
//==========================================================================
// Allocate input vectors h_A and h_B in host memory
float* h_A = new float[N];
float* h_B = new float[N];
float* h_C = new float[N];
// Initialize input vectors
initialise_input_vect(h_A, h_B, N);
// Allocate vectors in device memory
float* d_A;
cudaMalloc(&d_A, size);
float* d_B;
cudaMalloc(&d_B, size);
float* d_C;
cudaMalloc(&d_C, size);
// Copy vectors from host memory to device memory
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
// Invoke kernel
int nThreadsPerBlock = 256;
int nblocks = (N / nThreadsPerBlock) + ((N % nThreadsPerBlock > 0) ? 1 : 0);
VecAdd<<<nblocks, nThreadsPerBlock>>>(d_A, d_B, d_C, N);
// Copy result from device memory to host memory
// h_C contains the result in host memory
cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
// Print the results
if(print_results) for (int i=0; i<N; i++) printf("h_C[%d] = %2.2f \n", i, h_C[i] );
// Free device memory
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
// Free host memory
delete[] h_A, h_B, h_C;
}
|
.file "tmpxft_000b4184_00000000-6_GPU_memory_challenge.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z21initialise_input_vectPfS_i
.type _Z21initialise_input_vectPfS_i, @function
_Z21initialise_input_vectPfS_i:
.LFB2057:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L3
movslq %edx, %rdx
movl $0, %eax
.L5:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rdi,%rax,4)
leal (%rax,%rax), %ecx
pxor %xmm0, %xmm0
cvtsi2ssl %ecx, %xmm0
movss %xmm0, (%rsi,%rax,4)
addq $1, %rax
cmpq %rdx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z21initialise_input_vectPfS_i, .-_Z21initialise_input_vectPfS_i
.globl _Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i
.type _Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i, @function
_Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6VecAddPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i, .-_Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i
.globl _Z6VecAddPfS_S_i
.type _Z6VecAddPfS_S_i, @function
_Z6VecAddPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z6VecAddPfS_S_i, .-_Z6VecAddPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Device Number: %d\n"
.LC1:
.string " Device name: %s\n"
.LC2:
.string " Compute Capability: %d.%d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string " Total Global Mem: %.1fGB\n\n"
.align 8
.LC5:
.string " Memory Clock Rate (KHz): %d\n"
.align 8
.LC6:
.string " Memory Bus Width (bits): %d\n"
.align 8
.LC8:
.string " Peak Memory Bandwidth (GB/s): %f\n\n"
.align 8
.LC9:
.string " Max Number of Threads per Block: %d\n"
.align 8
.LC10:
.string " Max Number of Blocks allowed in x-dir: %d\n"
.align 8
.LC11:
.string " Max Number of Blocks allowed in y-dir: %d\n"
.align 8
.LC12:
.string " Max Number of Blocks allowed in z-dir: %d\n"
.section .rodata.str1.1
.LC13:
.string " Warp Size: %d\n"
.section .rodata.str1.8
.align 8
.LC14:
.string "===============================================\n\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $1112, %rsp
.cfi_def_cfa_offset 1152
movq %fs:40, %rax
movq %rax, 1096(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
jle .L16
movl $0, %ebx
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %rbp
jmp .L19
.L17:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
.L18:
mulsd .LC3(%rip), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 672(%rsp), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 676(%rsp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2sdl 672(%rsp), %xmm0
addsd %xmm0, %xmm0
movl 676(%rsp), %edx
leal 7(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $3, %eax
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
mulsd %xmm1, %xmm0
divsd .LC7(%rip), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 384(%rsp), %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 400(%rsp), %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 404(%rsp), %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 408(%rsp), %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 372(%rsp), %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jle .L16
.L19:
leaq 64(%rsp), %r13
movl %ebx, %esi
movq %r13, %rdi
call cudaGetDeviceProperties_v2@PLT
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 428(%rsp), %ecx
movl 424(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 352(%rsp), %rax
testq %rax, %rax
js .L17
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
jmp .L18
.L16:
movl $4000, %edi
call _Znam@PLT
movq %rax, %rbx
movl $4000, %edi
call _Znam@PLT
movq %rax, %rbp
movl $4000, %edi
call _Znam@PLT
movq %rax, %r12
movl $1000, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z21initialise_input_vectPfS_i
leaq 16(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4000, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4000, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 52(%rsp)
movl $1, 56(%rsp)
movl $4, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movl $2, %ecx
movl $4000, %edx
movq 32(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq 1096(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $1112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movl $1000, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC15:
.string "_Z6VecAddPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z6VecAddPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1041235968
.align 8
.LC7:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
// Device code
__global__ void VecAdd(float* A, float* B, float* C, int N)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < N)
C[i] = A[i] + B[i];
}
// Initialise the input vectors
void initialise_input_vect(float* A, float* B, int N)
{
for(int i=0; i<N; i++){
A[i]=i;
B[i]=2*i;
}
}
// Host code
int main()
{
int N = 1000; // Number of elements to process
bool print_results = 0; // Boolean variable for printing the results
size_t size = N * sizeof(float);
//==========================================================================
// Get the GPUs properties:
// Device name, Compute Capability, Global Memory (GB) etc
int nDevices;
cudaGetDeviceCount(&nDevices);
for (int i = 0; i < nDevices; i++) {
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, i);
printf("Device Number: %d\n", i);
printf(" Device name: %s\n", prop.name);
printf(" Compute Capability: %d.%d\n", prop.major, prop.minor);
printf(" Total Global Mem: %.1fGB\n\n", ((double)prop.totalGlobalMem/1073741824.0));
printf(" Memory Clock Rate (KHz): %d\n",
prop.memoryClockRate);
printf(" Memory Bus Width (bits): %d\n",
prop.memoryBusWidth);
printf(" Peak Memory Bandwidth (GB/s): %f\n\n",
2.0*prop.memoryClockRate*(prop.memoryBusWidth/8)/1.0e6);
printf(" Max Number of Threads per Block: %d\n", prop.maxThreadsPerBlock);
printf(" Max Number of Blocks allowed in x-dir: %d\n", prop.maxGridSize[0]);
printf(" Max Number of Blocks allowed in y-dir: %d\n", prop.maxGridSize[1]);
printf(" Max Number of Blocks allowed in z-dir: %d\n", prop.maxGridSize[2]);
printf(" Warp Size: %d\n", prop.warpSize);
printf("===============================================\n\n");
}
//==========================================================================
// Allocate input vectors h_A and h_B in host memory
float* h_A = new float[N];
float* h_B = new float[N];
float* h_C = new float[N];
// Initialize input vectors
initialise_input_vect(h_A, h_B, N);
// Allocate vectors in device memory
float* d_A;
cudaMalloc(&d_A, size);
float* d_B;
cudaMalloc(&d_B, size);
float* d_C;
cudaMalloc(&d_C, size);
// Copy vectors from host memory to device memory
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
// Invoke kernel
int nThreadsPerBlock = 256;
int nblocks = (N / nThreadsPerBlock) + ((N % nThreadsPerBlock > 0) ? 1 : 0);
VecAdd<<<nblocks, nThreadsPerBlock>>>(d_A, d_B, d_C, N);
// Copy result from device memory to host memory
// h_C contains the result in host memory
cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
// Print the results
if(print_results) for (int i=0; i<N; i++) printf("h_C[%d] = %2.2f \n", i, h_C[i] );
// Free device memory
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
// Free host memory
delete[] h_A, h_B, h_C;
}
|
#include <hip/hip_runtime.h>
#include <stdio.h>
// Device code
__global__ void VecAdd(float* A, float* B, float* C, int N)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < N)
C[i] = A[i] + B[i];
}
// Initialise the input vectors
void initialise_input_vect(float* A, float* B, int N)
{
for(int i=0; i<N; i++){
A[i]=i;
B[i]=2*i;
}
}
// Host code
int main()
{
int N = 1000; // Number of elements to process
bool print_results = 0; // Boolean variable for printing the results
size_t size = N * sizeof(float);
//==========================================================================
// Get the GPUs properties:
// Device name, Compute Capability, Global Memory (GB) etc
int nDevices;
hipGetDeviceCount(&nDevices);
for (int i = 0; i < nDevices; i++) {
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, i);
printf("Device Number: %d\n", i);
printf(" Device name: %s\n", prop.name);
printf(" Compute Capability: %d.%d\n", prop.major, prop.minor);
printf(" Total Global Mem: %.1fGB\n\n", ((double)prop.totalGlobalMem/1073741824.0));
printf(" Memory Clock Rate (KHz): %d\n",
prop.memoryClockRate);
printf(" Memory Bus Width (bits): %d\n",
prop.memoryBusWidth);
printf(" Peak Memory Bandwidth (GB/s): %f\n\n",
2.0*prop.memoryClockRate*(prop.memoryBusWidth/8)/1.0e6);
printf(" Max Number of Threads per Block: %d\n", prop.maxThreadsPerBlock);
printf(" Max Number of Blocks allowed in x-dir: %d\n", prop.maxGridSize[0]);
printf(" Max Number of Blocks allowed in y-dir: %d\n", prop.maxGridSize[1]);
printf(" Max Number of Blocks allowed in z-dir: %d\n", prop.maxGridSize[2]);
printf(" Warp Size: %d\n", prop.warpSize);
printf("===============================================\n\n");
}
//==========================================================================
// Allocate input vectors h_A and h_B in host memory
float* h_A = new float[N];
float* h_B = new float[N];
float* h_C = new float[N];
// Initialize input vectors
initialise_input_vect(h_A, h_B, N);
// Allocate vectors in device memory
float* d_A;
hipMalloc(&d_A, size);
float* d_B;
hipMalloc(&d_B, size);
float* d_C;
hipMalloc(&d_C, size);
// Copy vectors from host memory to device memory
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
// Invoke kernel
int nThreadsPerBlock = 256;
int nblocks = (N / nThreadsPerBlock) + ((N % nThreadsPerBlock > 0) ? 1 : 0);
VecAdd<<<nblocks, nThreadsPerBlock>>>(d_A, d_B, d_C, N);
// Copy result from device memory to host memory
// h_C contains the result in host memory
hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
// Print the results
if(print_results) for (int i=0; i<N; i++) printf("h_C[%d] = %2.2f \n", i, h_C[i] );
// Free device memory
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
// Free host memory
delete[] h_A, h_B, h_C;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
// Device code
__global__ void VecAdd(float* A, float* B, float* C, int N)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < N)
C[i] = A[i] + B[i];
}
// Initialise the input vectors
void initialise_input_vect(float* A, float* B, int N)
{
for(int i=0; i<N; i++){
A[i]=i;
B[i]=2*i;
}
}
// Host code
int main()
{
int N = 1000; // Number of elements to process
bool print_results = 0; // Boolean variable for printing the results
size_t size = N * sizeof(float);
//==========================================================================
// Get the GPUs properties:
// Device name, Compute Capability, Global Memory (GB) etc
int nDevices;
hipGetDeviceCount(&nDevices);
for (int i = 0; i < nDevices; i++) {
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, i);
printf("Device Number: %d\n", i);
printf(" Device name: %s\n", prop.name);
printf(" Compute Capability: %d.%d\n", prop.major, prop.minor);
printf(" Total Global Mem: %.1fGB\n\n", ((double)prop.totalGlobalMem/1073741824.0));
printf(" Memory Clock Rate (KHz): %d\n",
prop.memoryClockRate);
printf(" Memory Bus Width (bits): %d\n",
prop.memoryBusWidth);
printf(" Peak Memory Bandwidth (GB/s): %f\n\n",
2.0*prop.memoryClockRate*(prop.memoryBusWidth/8)/1.0e6);
printf(" Max Number of Threads per Block: %d\n", prop.maxThreadsPerBlock);
printf(" Max Number of Blocks allowed in x-dir: %d\n", prop.maxGridSize[0]);
printf(" Max Number of Blocks allowed in y-dir: %d\n", prop.maxGridSize[1]);
printf(" Max Number of Blocks allowed in z-dir: %d\n", prop.maxGridSize[2]);
printf(" Warp Size: %d\n", prop.warpSize);
printf("===============================================\n\n");
}
//==========================================================================
// Allocate input vectors h_A and h_B in host memory
float* h_A = new float[N];
float* h_B = new float[N];
float* h_C = new float[N];
// Initialize input vectors
initialise_input_vect(h_A, h_B, N);
// Allocate vectors in device memory
float* d_A;
hipMalloc(&d_A, size);
float* d_B;
hipMalloc(&d_B, size);
float* d_C;
hipMalloc(&d_C, size);
// Copy vectors from host memory to device memory
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
// Invoke kernel
int nThreadsPerBlock = 256;
int nblocks = (N / nThreadsPerBlock) + ((N % nThreadsPerBlock > 0) ? 1 : 0);
VecAdd<<<nblocks, nThreadsPerBlock>>>(d_A, d_B, d_C, N);
// Copy result from device memory to host memory
// h_C contains the result in host memory
hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
// Print the results
if(print_results) for (int i=0; i<N; i++) printf("h_C[%d] = %2.2f \n", i, h_C[i] );
// Free device memory
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
// Free host memory
delete[] h_A, h_B, h_C;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6VecAddPfS_S_i
.globl _Z6VecAddPfS_S_i
.p2align 8
.type _Z6VecAddPfS_S_i,@function
_Z6VecAddPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6VecAddPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6VecAddPfS_S_i, .Lfunc_end0-_Z6VecAddPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6VecAddPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6VecAddPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
// Device code
__global__ void VecAdd(float* A, float* B, float* C, int N)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < N)
C[i] = A[i] + B[i];
}
// Initialise the input vectors
void initialise_input_vect(float* A, float* B, int N)
{
for(int i=0; i<N; i++){
A[i]=i;
B[i]=2*i;
}
}
// Host code
int main()
{
int N = 1000; // Number of elements to process
bool print_results = 0; // Boolean variable for printing the results
size_t size = N * sizeof(float);
//==========================================================================
// Get the GPUs properties:
// Device name, Compute Capability, Global Memory (GB) etc
int nDevices;
hipGetDeviceCount(&nDevices);
for (int i = 0; i < nDevices; i++) {
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, i);
printf("Device Number: %d\n", i);
printf(" Device name: %s\n", prop.name);
printf(" Compute Capability: %d.%d\n", prop.major, prop.minor);
printf(" Total Global Mem: %.1fGB\n\n", ((double)prop.totalGlobalMem/1073741824.0));
printf(" Memory Clock Rate (KHz): %d\n",
prop.memoryClockRate);
printf(" Memory Bus Width (bits): %d\n",
prop.memoryBusWidth);
printf(" Peak Memory Bandwidth (GB/s): %f\n\n",
2.0*prop.memoryClockRate*(prop.memoryBusWidth/8)/1.0e6);
printf(" Max Number of Threads per Block: %d\n", prop.maxThreadsPerBlock);
printf(" Max Number of Blocks allowed in x-dir: %d\n", prop.maxGridSize[0]);
printf(" Max Number of Blocks allowed in y-dir: %d\n", prop.maxGridSize[1]);
printf(" Max Number of Blocks allowed in z-dir: %d\n", prop.maxGridSize[2]);
printf(" Warp Size: %d\n", prop.warpSize);
printf("===============================================\n\n");
}
//==========================================================================
// Allocate input vectors h_A and h_B in host memory
float* h_A = new float[N];
float* h_B = new float[N];
float* h_C = new float[N];
// Initialize input vectors
initialise_input_vect(h_A, h_B, N);
// Allocate vectors in device memory
float* d_A;
hipMalloc(&d_A, size);
float* d_B;
hipMalloc(&d_B, size);
float* d_C;
hipMalloc(&d_C, size);
// Copy vectors from host memory to device memory
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
// Invoke kernel
int nThreadsPerBlock = 256;
int nblocks = (N / nThreadsPerBlock) + ((N % nThreadsPerBlock > 0) ? 1 : 0);
VecAdd<<<nblocks, nThreadsPerBlock>>>(d_A, d_B, d_C, N);
// Copy result from device memory to host memory
// h_C contains the result in host memory
hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
// Print the results
if(print_results) for (int i=0; i<N; i++) printf("h_C[%d] = %2.2f \n", i, h_C[i] );
// Free device memory
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
// Free host memory
delete[] h_A, h_B, h_C;
}
|
.text
.file "GPU_memory_challenge.hip"
.globl _Z21__device_stub__VecAddPfS_S_i # -- Begin function _Z21__device_stub__VecAddPfS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__VecAddPfS_S_i,@function
_Z21__device_stub__VecAddPfS_S_i: # @_Z21__device_stub__VecAddPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6VecAddPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__VecAddPfS_S_i, .Lfunc_end0-_Z21__device_stub__VecAddPfS_S_i
.cfi_endproc
# -- End function
.globl _Z21initialise_input_vectPfS_i # -- Begin function _Z21initialise_input_vectPfS_i
.p2align 4, 0x90
.type _Z21initialise_input_vectPfS_i,@function
_Z21initialise_input_vectPfS_i: # @_Z21initialise_input_vectPfS_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %edx, %eax
xorl %ecx, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
movss %xmm0, (%rdi,%rdx,4)
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rsi,%rdx,4)
incq %rdx
addl $2, %ecx
cmpq %rdx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z21initialise_input_vectPfS_i, .Lfunc_end1-_Z21initialise_input_vectPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI2_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI2_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_2:
.quad 0x3e10000000000000 # double 9.3132257461547852E-10
.LCPI2_3:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1592, %rsp # imm = 0x638
.cfi_def_cfa_offset 1632
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 4(%rsp)
jle .LBB2_3
# %bb.1: # %.lr.ph
leaq 112(%rsp), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_2: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 472(%rsp), %esi
movl 476(%rsp), %edx
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movsd 400(%rsp), %xmm1 # xmm1 = mem[0],zero
unpcklps .LCPI2_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI2_1(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
mulsd .LCPI2_2(%rip), %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movl 720(%rsp), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl 724(%rsp), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
xorps %xmm1, %xmm1
cvtsi2sdl 720(%rsp), %xmm1
addsd %xmm1, %xmm1
movl 724(%rsp), %eax
leal 7(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $3, %ecx
xorps %xmm0, %xmm0
cvtsi2sd %ecx, %xmm0
mulsd %xmm1, %xmm0
divsd .LCPI2_3(%rip), %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movl 432(%rsp), %esi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl 448(%rsp), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movl 452(%rsp), %esi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl 456(%rsp), %esi
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movl 420(%rsp), %esi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl $.Lstr, %edi
callq puts@PLT
incl %ebp
cmpl 4(%rsp), %ebp
jl .LBB2_2
.LBB2_3: # %._crit_edge
movl $4000, %edi # imm = 0xFA0
callq _Znam
movq %rax, %rbx
movl $4000, %edi # imm = 0xFA0
callq _Znam
movq %rax, %r15
movl $4000, %edi # imm = 0xFA0
callq _Znam
movq %rax, %r14
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_4: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rbx,%rcx,4)
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r15,%rcx,4)
incq %rcx
addl $2, %eax
cmpq $1000, %rcx # imm = 0x3E8
jne .LBB2_4
# %bb.5: # %_Z21initialise_input_vectPfS_i.exit
leaq 24(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
movq 24(%rsp), %rdi
movl $4000, %edx # imm = 0xFA0
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $4000, %edx # imm = 0xFA0
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967300, %rdi # imm = 0x100000004
leaq 252(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_7
# %bb.6:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $1000, 36(%rsp) # imm = 0x3E8
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6VecAddPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_7:
movq 8(%rsp), %rsi
movl $4000, %edx # imm = 0xFA0
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $1592, %rsp # imm = 0x638
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6VecAddPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6VecAddPfS_S_i,@object # @_Z6VecAddPfS_S_i
.section .rodata,"a",@progbits
.globl _Z6VecAddPfS_S_i
.p2align 3, 0x0
_Z6VecAddPfS_S_i:
.quad _Z21__device_stub__VecAddPfS_S_i
.size _Z6VecAddPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Device Number: %d\n"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " Device name: %s\n"
.size .L.str.1, 26
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " Compute Capability: %d.%d\n"
.size .L.str.2, 29
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " Total Global Mem: %.1fGB\n\n"
.size .L.str.3, 31
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " Memory Clock Rate (KHz): %d\n"
.size .L.str.4, 31
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " Memory Bus Width (bits): %d\n"
.size .L.str.5, 31
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " Peak Memory Bandwidth (GB/s): %f\n\n"
.size .L.str.6, 37
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " Max Number of Threads per Block: %d\n"
.size .L.str.7, 40
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz " Max Number of Blocks allowed in x-dir: %d\n"
.size .L.str.8, 46
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " Max Number of Blocks allowed in y-dir: %d\n"
.size .L.str.9, 46
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz " Max Number of Blocks allowed in z-dir: %d\n"
.size .L.str.10, 46
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz " Warp Size: %d\n"
.size .L.str.11, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6VecAddPfS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "===============================================\n"
.size .Lstr, 49
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__VecAddPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6VecAddPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z6VecAddPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6VecAddPfS_S_i
.globl _Z6VecAddPfS_S_i
.p2align 8
.type _Z6VecAddPfS_S_i,@function
_Z6VecAddPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6VecAddPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6VecAddPfS_S_i, .Lfunc_end0-_Z6VecAddPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6VecAddPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6VecAddPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000b4184_00000000-6_GPU_memory_challenge.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z21initialise_input_vectPfS_i
.type _Z21initialise_input_vectPfS_i, @function
_Z21initialise_input_vectPfS_i:
.LFB2057:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L3
movslq %edx, %rdx
movl $0, %eax
.L5:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rdi,%rax,4)
leal (%rax,%rax), %ecx
pxor %xmm0, %xmm0
cvtsi2ssl %ecx, %xmm0
movss %xmm0, (%rsi,%rax,4)
addq $1, %rax
cmpq %rdx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z21initialise_input_vectPfS_i, .-_Z21initialise_input_vectPfS_i
.globl _Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i
.type _Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i, @function
_Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6VecAddPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i, .-_Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i
.globl _Z6VecAddPfS_S_i
.type _Z6VecAddPfS_S_i, @function
_Z6VecAddPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z6VecAddPfS_S_i, .-_Z6VecAddPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Device Number: %d\n"
.LC1:
.string " Device name: %s\n"
.LC2:
.string " Compute Capability: %d.%d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string " Total Global Mem: %.1fGB\n\n"
.align 8
.LC5:
.string " Memory Clock Rate (KHz): %d\n"
.align 8
.LC6:
.string " Memory Bus Width (bits): %d\n"
.align 8
.LC8:
.string " Peak Memory Bandwidth (GB/s): %f\n\n"
.align 8
.LC9:
.string " Max Number of Threads per Block: %d\n"
.align 8
.LC10:
.string " Max Number of Blocks allowed in x-dir: %d\n"
.align 8
.LC11:
.string " Max Number of Blocks allowed in y-dir: %d\n"
.align 8
.LC12:
.string " Max Number of Blocks allowed in z-dir: %d\n"
.section .rodata.str1.1
.LC13:
.string " Warp Size: %d\n"
.section .rodata.str1.8
.align 8
.LC14:
.string "===============================================\n\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $1112, %rsp
.cfi_def_cfa_offset 1152
movq %fs:40, %rax
movq %rax, 1096(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
jle .L16
movl $0, %ebx
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %rbp
jmp .L19
.L17:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
.L18:
mulsd .LC3(%rip), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 672(%rsp), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 676(%rsp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2sdl 672(%rsp), %xmm0
addsd %xmm0, %xmm0
movl 676(%rsp), %edx
leal 7(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $3, %eax
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
mulsd %xmm1, %xmm0
divsd .LC7(%rip), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 384(%rsp), %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 400(%rsp), %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 404(%rsp), %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 408(%rsp), %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 372(%rsp), %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jle .L16
.L19:
leaq 64(%rsp), %r13
movl %ebx, %esi
movq %r13, %rdi
call cudaGetDeviceProperties_v2@PLT
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 428(%rsp), %ecx
movl 424(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 352(%rsp), %rax
testq %rax, %rax
js .L17
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
jmp .L18
.L16:
movl $4000, %edi
call _Znam@PLT
movq %rax, %rbx
movl $4000, %edi
call _Znam@PLT
movq %rax, %rbp
movl $4000, %edi
call _Znam@PLT
movq %rax, %r12
movl $1000, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z21initialise_input_vectPfS_i
leaq 16(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4000, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4000, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 52(%rsp)
movl $1, 56(%rsp)
movl $4, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movl $2, %ecx
movl $4000, %edx
movq 32(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq 1096(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $1112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movl $1000, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC15:
.string "_Z6VecAddPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z6VecAddPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1041235968
.align 8
.LC7:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "GPU_memory_challenge.hip"
.globl _Z21__device_stub__VecAddPfS_S_i # -- Begin function _Z21__device_stub__VecAddPfS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__VecAddPfS_S_i,@function
_Z21__device_stub__VecAddPfS_S_i: # @_Z21__device_stub__VecAddPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6VecAddPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__VecAddPfS_S_i, .Lfunc_end0-_Z21__device_stub__VecAddPfS_S_i
.cfi_endproc
# -- End function
.globl _Z21initialise_input_vectPfS_i # -- Begin function _Z21initialise_input_vectPfS_i
.p2align 4, 0x90
.type _Z21initialise_input_vectPfS_i,@function
_Z21initialise_input_vectPfS_i: # @_Z21initialise_input_vectPfS_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %edx, %eax
xorl %ecx, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
movss %xmm0, (%rdi,%rdx,4)
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rsi,%rdx,4)
incq %rdx
addl $2, %ecx
cmpq %rdx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z21initialise_input_vectPfS_i, .Lfunc_end1-_Z21initialise_input_vectPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI2_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI2_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_2:
.quad 0x3e10000000000000 # double 9.3132257461547852E-10
.LCPI2_3:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1592, %rsp # imm = 0x638
.cfi_def_cfa_offset 1632
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 4(%rsp)
jle .LBB2_3
# %bb.1: # %.lr.ph
leaq 112(%rsp), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_2: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 472(%rsp), %esi
movl 476(%rsp), %edx
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movsd 400(%rsp), %xmm1 # xmm1 = mem[0],zero
unpcklps .LCPI2_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI2_1(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
mulsd .LCPI2_2(%rip), %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movl 720(%rsp), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl 724(%rsp), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
xorps %xmm1, %xmm1
cvtsi2sdl 720(%rsp), %xmm1
addsd %xmm1, %xmm1
movl 724(%rsp), %eax
leal 7(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $3, %ecx
xorps %xmm0, %xmm0
cvtsi2sd %ecx, %xmm0
mulsd %xmm1, %xmm0
divsd .LCPI2_3(%rip), %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movl 432(%rsp), %esi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl 448(%rsp), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movl 452(%rsp), %esi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl 456(%rsp), %esi
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movl 420(%rsp), %esi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl $.Lstr, %edi
callq puts@PLT
incl %ebp
cmpl 4(%rsp), %ebp
jl .LBB2_2
.LBB2_3: # %._crit_edge
movl $4000, %edi # imm = 0xFA0
callq _Znam
movq %rax, %rbx
movl $4000, %edi # imm = 0xFA0
callq _Znam
movq %rax, %r15
movl $4000, %edi # imm = 0xFA0
callq _Znam
movq %rax, %r14
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_4: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rbx,%rcx,4)
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r15,%rcx,4)
incq %rcx
addl $2, %eax
cmpq $1000, %rcx # imm = 0x3E8
jne .LBB2_4
# %bb.5: # %_Z21initialise_input_vectPfS_i.exit
leaq 24(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
movq 24(%rsp), %rdi
movl $4000, %edx # imm = 0xFA0
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $4000, %edx # imm = 0xFA0
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967300, %rdi # imm = 0x100000004
leaq 252(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_7
# %bb.6:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $1000, 36(%rsp) # imm = 0x3E8
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6VecAddPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_7:
movq 8(%rsp), %rsi
movl $4000, %edx # imm = 0xFA0
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $1592, %rsp # imm = 0x638
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6VecAddPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6VecAddPfS_S_i,@object # @_Z6VecAddPfS_S_i
.section .rodata,"a",@progbits
.globl _Z6VecAddPfS_S_i
.p2align 3, 0x0
_Z6VecAddPfS_S_i:
.quad _Z21__device_stub__VecAddPfS_S_i
.size _Z6VecAddPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Device Number: %d\n"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " Device name: %s\n"
.size .L.str.1, 26
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " Compute Capability: %d.%d\n"
.size .L.str.2, 29
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " Total Global Mem: %.1fGB\n\n"
.size .L.str.3, 31
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " Memory Clock Rate (KHz): %d\n"
.size .L.str.4, 31
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " Memory Bus Width (bits): %d\n"
.size .L.str.5, 31
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " Peak Memory Bandwidth (GB/s): %f\n\n"
.size .L.str.6, 37
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " Max Number of Threads per Block: %d\n"
.size .L.str.7, 40
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz " Max Number of Blocks allowed in x-dir: %d\n"
.size .L.str.8, 46
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " Max Number of Blocks allowed in y-dir: %d\n"
.size .L.str.9, 46
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz " Max Number of Blocks allowed in z-dir: %d\n"
.size .L.str.10, 46
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz " Warp Size: %d\n"
.size .L.str.11, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6VecAddPfS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "===============================================\n"
.size .Lstr, 49
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__VecAddPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6VecAddPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
__global__ void add(int n, float *x, float *y)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < n)
y[i] = x[i] + y[i];
}
|
code for sm_80
Function : _Z3addiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe400078e0205 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FADD R7, R0, R3 ; /* 0x0000000300077221 */
/* 0x004fca0000000000 */
/*00d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void add(int n, float *x, float *y)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < n)
y[i] = x[i] + y[i];
}
|
.file "tmpxft_00197cf7_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z3addiPfS_iPfS_
.type _Z25__device_stub__Z3addiPfS_iPfS_, @function
_Z25__device_stub__Z3addiPfS_iPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z25__device_stub__Z3addiPfS_iPfS_, .-_Z25__device_stub__Z3addiPfS_iPfS_
.globl _Z3addiPfS_
.type _Z3addiPfS_, @function
_Z3addiPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3addiPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3addiPfS_, .-_Z3addiPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void add(int n, float *x, float *y)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < n)
y[i] = x[i] + y[i];
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add(int n, float *x, float *y)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < n)
y[i] = x[i] + y[i];
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add(int n, float *x, float *y)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < n)
y[i] = x[i] + y[i];
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiPfS_
.globl _Z3addiPfS_
.p2align 8
.type _Z3addiPfS_,@function
_Z3addiPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiPfS_, .Lfunc_end0-_Z3addiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add(int n, float *x, float *y)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < n)
y[i] = x[i] + y[i];
}
|
.text
.file "add.hip"
.globl _Z18__device_stub__addiPfS_ # -- Begin function _Z18__device_stub__addiPfS_
.p2align 4, 0x90
.type _Z18__device_stub__addiPfS_,@function
_Z18__device_stub__addiPfS_: # @_Z18__device_stub__addiPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addiPfS_, .Lfunc_end0-_Z18__device_stub__addiPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiPfS_,@object # @_Z3addiPfS_
.section .rodata,"a",@progbits
.globl _Z3addiPfS_
.p2align 3, 0x0
_Z3addiPfS_:
.quad _Z18__device_stub__addiPfS_
.size _Z3addiPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addiPfS_"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z3addiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe400078e0205 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FADD R7, R0, R3 ; /* 0x0000000300077221 */
/* 0x004fca0000000000 */
/*00d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiPfS_
.globl _Z3addiPfS_
.p2align 8
.type _Z3addiPfS_,@function
_Z3addiPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiPfS_, .Lfunc_end0-_Z3addiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00197cf7_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z3addiPfS_iPfS_
.type _Z25__device_stub__Z3addiPfS_iPfS_, @function
_Z25__device_stub__Z3addiPfS_iPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z25__device_stub__Z3addiPfS_iPfS_, .-_Z25__device_stub__Z3addiPfS_iPfS_
.globl _Z3addiPfS_
.type _Z3addiPfS_, @function
_Z3addiPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3addiPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3addiPfS_, .-_Z3addiPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "add.hip"
.globl _Z18__device_stub__addiPfS_ # -- Begin function _Z18__device_stub__addiPfS_
.p2align 4, 0x90
.type _Z18__device_stub__addiPfS_,@function
_Z18__device_stub__addiPfS_: # @_Z18__device_stub__addiPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addiPfS_, .Lfunc_end0-_Z18__device_stub__addiPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiPfS_,@object # @_Z3addiPfS_
.section .rodata,"a",@progbits
.globl _Z3addiPfS_
.p2align 3, 0x0
_Z3addiPfS_:
.quad _Z18__device_stub__addiPfS_
.size _Z3addiPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addiPfS_"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
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