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1 Introduction RISC-V (pronounced “risk-five”) is a new instruction-set architecture (ISA) that was originallydesigned to support computer architecture research and education, but which we now hope willalso become a standard free and open architecture for industry implementations. Our goals indefining RISC-V include:•A c... | RV32ISPEC.pdf#segment0 | 2023-07-18T10:37:52.211712 | segment0 | 1 Introduction | [] |
1.1 RISC-V Hardware Platform Terminology A RISC-V hardware platform can contain one or more RISC-V-compatible processing cores to-gether with other non-RISC-V-compatible cores, fixed-function accelerators, various physical mem-ory structures, I/O devices, and an interconnect structure to allow the components to communic... | RV32ISPEC.pdf#segment1 | 2023-07-18T10:37:52.211915 | segment1 | 1.1 RISC-V Hardware Platform Terminology | [] |
1.2 RISC-V Software Execution Environments and HartsThe behavior of a RISC-V program depends on the execution environment in which it runs. ARISC-V execution environment interface (EEI) defines the initial state of the program, the numberand type of harts in the environment including the privilege modes supported by the... | RV32ISPEC.pdf#segment2 | 2023-07-18T10:37:52.212045 | segment2 | 1.2 RISC-V Software Execution Environments and Harts | [] |
1.3 RISC-V ISA Overview A RISC-V ISA is defined as a base integer ISA, which must be present in any implementation, plusoptional extensions to the base ISA. The base integer ISAs are very similar to that of the earlyRISC processors except with no branch delay slots and with support for optional variable-lengthinstructio... | RV32ISPEC.pdf#segment3 | 2023-07-18T10:37:52.212242 | segment3 | 1.3 RISC-V ISA Overview | [] |
1.4 Memory A RISC-V hart has a single byte-addressable address space of 2XLENbytes for all memory accesses.Awordof memory is defined as 32 bits (4 bytes). Correspondingly, ahalfwordis 16 bits (2 bytes), adoublewordis 64 bits (8 bytes), and aquadwordis 128 bits (16 bytes). The memory address space iscircular, so that the... | RV32ISPEC.pdf#segment4 | 2023-07-18T10:37:52.212436 | segment4 | 1.4 Memory | [] |
1.5 Base Instruction-Length Encoding The base RISC-V ISA has fixed-length 32-bit instructions that must be naturally aligned on 32-bitboundaries. However, the standard RISC-V encoding scheme is designed to support ISA extensionswith variable-length instructions, where each instruction can be any number of 16-bit instruc... | RV32ISPEC.pdf#segment5 | 2023-07-18T10:37:52.212565 | segment5 | 1.5 Base Instruction-Length Encoding | [] |
1.6 Exceptions, Traps, and Interrupts We use the termexceptionto refer to an unusual condition occurring at run time associated withan instruction in the current RISC-V hart. We use the terminterruptto refer to an externalasynchronous event that may cause a RISC-V hart to experience an unexpected transfer of control.We... | RV32ISPEC.pdf#segment6 | 2023-07-18T10:37:52.212748 | segment6 | 1.6 Exceptions, Traps, and Interrupts | [] |
1.7 UNSPECIFIED Behaviors and Values The architecture fully describes what implementations must do and any constraints on what theymay do. In cases where the architecture intentionally does not constrain implementations, the termunspecifiedis explicitly used.The termunspecifiedrefers to a behavior or value that is inte... | RV32ISPEC.pdf#segment7 | 2023-07-18T10:37:52.212935 | segment7 | 1.7 UNSPECIFIED Behaviors and Values | [] |
2 RV32I Base Integer Instruction Set,Version 2.1 This chapter describes version 2.0 of the RV32I base integer instruction set.RV32I was designed to be su cient to form a compiler target and to support modern operatingsystem environments. The ISA was also designed to reduce the hardware required in a minimalimplementati... | RV32ISPEC.pdf#segment8 | 2023-07-18T10:37:52.213045 | segment8 | 2 RV32I Base Integer Instruction Set,Version 2.1 | [] |
2.1 Programmers’ Model for Base Integer ISA Figure2.1shows the unprivileged state for the base integer ISA. For RV32I, the 32xregistersare each 32 bits wide, i.e., XLEN=32. Registerx0is hardwired with all bits equal to 0. Generalpurpose registersx1–x31hold values that various instructions interpret as a collection of B... | RV32ISPEC.pdf#segment9 | 2023-07-18T10:37:52.213229 | segment9 | 2.1 Programmers' Model for Base Integer ISA | [] |
2.2 Base Instruction Formats In the base RV32I ISA, there are four core instruction formats (R/I/S/U), as shown in Figure2.2.All are a fixed 32 bits in length and must be aligned on a four-byte boundary in memory. Aninstruction-address-misaligned exception is generated on a taken branch or unconditional jumpif the targe... | RV32ISPEC.pdf#segment10 | 2023-07-18T10:37:52.213418 | segment10 | 2.2 Base Instruction Formats | [] |
2.3 Immediate Encoding Variants There are a further two variants of the instruction formats (B/J) based on the handling of imme-diates, as shown in Figure2.3.31 30 25 24 21 20 19 15 14 12 11 8 7 6 0funct7rs2rs1funct3rdopcodeR-typeimm[11:0]rs1funct3rdopcodeI-typeimm[11:5]rs2rs1funct3imm[4:0]opcodeS-typeimm[12]imm[10:5]r... | RV32ISPEC.pdf#segment11 | 2023-07-18T10:37:52.213598 | segment11 | 2.3 Immediate Encoding Variants | [] |
2.4 Integer Computational Instructions Most integer computational instructions operate on XLEN bits of values held in the integer registerfile. Integer computational instructions are either encoded as register-immediate operations usingthe I-type format or as register-register operations using the R-type format. The des... | RV32ISPEC.pdf#segment12 | 2023-07-18T10:37:52.213692 | segment12 | 2.4 Integer Computational Instructions | [] |
2.5 Control Transfer Instructions RV32I provides two types of control transfer instructions: unconditional jumps and conditionalbranches. Control transfer instructions in RV32I donothave architecturally visible delay slots.Unconditional JumpsThe jump and link (JAL) instruction uses the J-type format, where the J-immedi... | RV32ISPEC.pdf#segment13 | 2023-07-18T10:37:52.213884 | segment13 | 2.5 Control Transfer Instructions | [] |
2.6 Load and Store Instructions RV32I is a load-store architecture, where only load and store instructions access memory andarithmetic instructions only operate on CPU registers. RV32I provides a 32-bit address space thatis byte-addressed. The EEI will define what portions of the address space are legal to access withwh... | RV32ISPEC.pdf#segment14 | 2023-07-18T10:37:52.214067 | segment14 | 2.6 Load and Store Instructions | [] |
2.7 Memory Ordering Instructions 31 28 27 26 25 24 23 22 21 20 19 15 14 12 11 7 6 0fmPIPOPRPWSISOSRSWrs1funct3rdopcode41 1 1 1 1111 5 3 5 7FM predecessor successor 0 FENCE 0 MISC-MEMThe FENCE instruction is used to order device I/O and memory accesses as viewed by other RISC-V harts and external devices or coprocessors... | RV32ISPEC.pdf#segment15 | 2023-07-18T10:37:52.214247 | segment15 | 2.7 Memory Ordering Instructions | [] |
2.8 Environment Call and Breakpoints SYSTEM instructions are used to access system functionality that might require privileged ac-cess and are encoded using the I-type instruction format. These can be divided into two mainclasses: those that atomically read-modify-write control and status registers (CSRs), and all othe... | RV32ISPEC.pdf#segment16 | 2023-07-18T10:37:52.214398 | segment16 | 2.8 Environment Call and Breakpoints | [] |
2.9 HINT Instructions RV32I reserves a large encoding space for HINT instructions, which are usually used to commu-nicate performance hints to the microarchitecture. HINTs are encoded as integer computationalinstructions withrd=x0. Hence, like the NOP instruction, HINTs do not change any architecturallyvisible state, e... | RV32ISPEC.pdf#segment17 | 2023-07-18T10:37:52.214677 | segment17 | 2.9 HINT Instructions | [] |
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