| {"paper_meta":{"paper_id":"arxiv:0710.4680","title":"0710.4680","authors":[],"year":null,"published":null,"updated":null,"venue_or_source":"arxiv-papers-shard","primary_category":"cs","secondary_categories":[],"doi":null,"license":"unknown","source_type":"pdf+shard","source_url":null,"pdf_url":null},"abstract":{"raw":"","cleaned":"","offsets":[]},"full_paper_text":{"raw_ordered_text":"Abstract - The problem of determining lower bounds for the\nenergy cost of a given nanoscale design is addressed via a\ncomplexity theory-based approach. This paper provides a\ntheoretical framework that is able to assess the trade-offs\nexisting in nanoscale designs between the amount of\nredundancy needed for a given level of resilience to errors and\nthe associated energy cost. Circuit size, logic depth and error\nresilience are analyzed and brought together in a theoretical\nframework that can be seamlessly integrated with automated\nsynthesis tools and can guide the design process of nanoscale\nsystems comprised of failure prone devices. The impact of\nredundancy addition on the switching energy and its\nrelationship with leakage energy is modeled in detail. Results\nshow that 99% error resilience is possible for fault-tolerant\ndesigns, but at the expense of at least 40% more energy if\nindividual gates fail independently with probability of 1%. \n1. Introduction \nNanoscale computing for either CMOS or non-CMOS\ntechnology is widely agreed to be characterized by non-\ndeterministic and unreliable behavior. In the case of nanometer\nCMOS designs, uncertainties stem from process and system\nparameter variability and their impact on performance and\nbehavior of switching devices, as well as from increased\nsusceptibility to soft errors which may thus create incorrect or\nfaulty functionality. For non-CMOS nanoscale electronics (such\nas molecular or self-assembly), uncertainties in operation\noriginate in the inherent non-deterministic switching behavior\nof such devices. While fault-tolerant computing is a mature area\nof research, automatically designing reliable systems out of\nunreliable components may prove to be a challenging task. As a\nnatural solution to the fault-tolerance problem, the use of\nredundancy has been proposed and analyzed theoretically as\nearly as five decades ago in the seminal work of von Neumann\n[1] and more recently by others [2,3,4,5,6,7]. While a practical\nsolution to synthesizing in an automated manner nanoscale\ndesigns that are inherently fault-tolerant has yet to be found,\nnonetheless such theoretical results offer a good insight into the\nachievable limits of error-resilience and required minimum\nredundancy (or extra logic) needed. Furthermore, in the case of\nCMOS nanoscale technology, power density and energy cost\nhave become the main design bottlenecks [8]. Adding\nredundancy in the hope of increasing error-resilience has the\nnegative effect of eventually decreasing the energy efficiency of\na given design. Thus, given the clear trade-off between\nachieving resilience via redundancy addition and energy\nefficiency, tools that can aid and guide the design process in a\nnanoscale design methodology become mandatory. \nThis paper is a step in this direction, by proposing theoretic\nlower bounds and trade-offs between energy efficiency and\nredundancy needed for achieving a certain error-resilience level.\nSuch bounds and theoretical trade-offs provide valuable insights\nearly in the design process and may aid and guide the automatic\nsynthesis process of nanoscale systems.\nWhile the fault-\ntolerance aspects described in this paper are relevant for any\ntype of nanoscale designs based on emerging technologies that\ninherently include non-determinism in normal operation, we\nwill restrict ourselves to considering as a driver application\ncomputing systems that use electrons and energy barriers to\nrepresent or manipulate their states [9]. CMOS nanoscale\ndesigns are one such example. Based on first principle physics\nlaws, it has been shown recently [9] that power density of such\ndesigns will reach in the next decade values close to 100 Watts/\ncm2. \nThese \npower \ndensities, \ncoupled \nwith \nincreased\ncomplexities and integration densities, put a lot more pressure\non achieving more efficient designs in the nanoscale era. To\naddress this problem, we consider the case of fault-tolerant\nnanoscale systems which need to rely on added redundancy to\nbe able to cope with increased error rates. To characterize the\navailable trade-offs between the required redundancy and the\nassociated energy cost, we propose the use of a complexity\ntheory-based framework. \n2. Related Work and Paper Contribution\nThis paper addresses the impact of error-resilience and\nredundancy in a theoretical framework that can guide the design\nprocess for nanoscale systems. Our framework is able to\nprovide bounds on the energy cost associated with achieving a\ngiven error-resilience level for a design based on error-prone\ngates (characterized by non-deterministic behavior), while also\ndetailing when these bounds are likely to be tight. As opposed\nto the theoretical bounds developed by von Neumann and his\nsuccessors [1,2,3,4,5,6], our approach does not assume any\nparticular use of redundancy, such as majority voting or parallel\nrestitution [1]. Instead, it is based on a framework relying on\ninformation theory concepts [7] to quantify the energy\nefficiency of nanoscale designs in the presence of errors. \nWhile the problem of analyzing the fault-tolerance of\nnanoscale designs under given gate or wire error models has\nbeen recently started to gain interest [10], no such study has\nlinked the error-resilience of a circuit to its energy efficiency.\nRecent work [11] has shown, using information theoretic\narguments, that it is possible to trade-off energy efficiency and\nfault-tolerance through the use of voltage scaling. Indeed, by\nEnergy Bounds for Fault-Tolerant Nanoscale Designs\nDiana Marculescu\nDept. of Electrical and Computer Engineering\nCarnegie Mellon University\nPittsburgh, PA 15213\nProceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’05) \n1530-1591/05 $ 20.00 IEEE\n\nallowing the voltage to be reduced, power cost is reduced\nsignificantly, while noise level is increased, thereby allowing\nfor trading-off energy and error-resilience. However, our goal is\ndifferent. We propose to quantify how added redundancy\nnecessary for achieving reliable operation out of unreliable\ncomponents impacts overall energy efficiency of a nanoscale\ndesign. In addition, our approach is not bound to any particular\ntype of redundancy (based on techniques such as majority\nvoting or parallel restitution) and assumes that “noisy” gates\nand can be modeled as error-free devices cascaded with a\nsymmetric communication channel modeling the error. In\naddition, while previous work [11] has linked energy efficiency\nand fault-tolerance in an information theoretic environment, it\ntargets voltage scaling-reliability trade-offs and does not\naddress entities that are more complex than a single gate or\ndevice. Our theoretical framework is able to completely\ncharacterize complex designs in terms of the energy-error-\nresilience trade-offs, while also providing insights into the\nrelative contributions of static and switching energy. \n3. Preliminaries\nWithout loss of generality, we restrict ourselves to nanoscale\nsystems with the following characteristics:\n•\nCircuits are assumed comprised of devices or gates that can\nbe either error-free, or failure prone.1\n•\nWe consider the case of error-free and failure-prone circuits\nin which internal gates can fail independently with a\nprobability \n.2 We assume that any interconnect\nerror \nprobabilities \nare \nlumped \ninto \ndevice \nerror\nprobabilities.\n•\nWe also consider device (gate) output error probabilities\nmodeled as symmetric communication channels with an ε\nerror probability. As shown in Figure 1, each failure-prone\ndevice is assumed modeled as an error-free device\ncascaded with a symmetric communication channel.\n•\nFor the case of failure-prone circuits, we consider the case\nof \n-reliable computation, that is, with probability of\n1-δ, the output of the circuit is correct. \n•\nWhile not restricting ourselves to any particular technology\ncharacterized by failure-prone operation, we consider the\ncase of systems that use electrons and energy barriers to\nrepresent or manipulate their states. Examples include\nnanoscale CMOS applications or systems comprised of\nirreversible logic switch devices. \n•\nGiven this constraint, we are mostly concerned with\nswitching energy or the energy lost due to information\nprocessing or transfer. \nTo this end, we consider the impact that any additional\nredundancy added to increase error resilience has on the overall\nenergy efficiency of a nanoscale design. Assuming that most of\nthe switching energy is consumed during output charging and\ndischarging (\n, where E is the total energy\nconsumed during a certain time interval, Vdd is the supply\nvoltage, C is the load capacitance and sw is the total switching\nactivity during the considered interval), fault-tolerant circuits\nrelying on added redundancy for increased error resilience can\nhave both their load capacitance and switching activity affected.\nIn addition, added redundancy may also impact logic depth, and\nthus overall latency. To this end, trade-offs between energy,\ndelay or composite metrics (such as energy-delay product) on\none hand, and required output error resilience δ, on the other\nhand, can be uncovered and analyzed in an analytical manner.\n4. Bounds on Switching Energy Metrics\nIntuitively, added logic redundancy, not necessarily committed\nto any particular implementation (e.g., majority based voting\nused in triple or n-tuple modular redundancy vs. parallel\nrestitution [1]) is expected to increase the error resilience of a\nfailure-prone nanoscale design by providing multiple logical\npaths from the inputs to the outputs, thus decreasing the impact\nof the “noise” on the overall input-output communication\nchannel. One may expect that the added redundant logic (when\nerror-free) will perform in a similar manner as far as switching\nactivity is concerned. However, we note that a non-zero error\nprobability on the output of each device (be it part of the\noriginal circuit, or part of the redundant logic) can affect the\nswitching behavior of that gate output, as shown next.\n4.1. Impact on Switching Activity\nIn what follows, we denote by p(x) the probability of a binary\nrandom variable x being one and by sw(x) the probability that x\nchanges state. We also denote by x an array of binary variables,\nand by f a multiple output Boolean function.\nThe following result quantifies the change in the switching\nactivity that a given “noise” level produces on the output of a\nswitching device:\nTheorem 1. If y, z are the error-free and error-prone outputs of a\ndevice which fails with a probability of as in Figure 1, then:\n.\nHint for proof:3 Uses switching activity definition for temporal\n1. Devices and gates are assumed to denote the same entity in this paper.\n2. As it will be seen in the sequel, if error probabilities are close to 1/2, reliable\ncomputation is not possible unless an unbounded overhead is considered. \n0\nε\n1 2\n⁄\n≤\n≤\nError-free\n device\nError\nmodel\nx\ny\nz\n0 0\n1 1\nε\n1\nε\n–\n1\nε\n–\ny\nz\nε\nFigure 1. Modeling error-prone devices using error-free devices and a symmetric communication channel error model ε. The error-\nfree device is a gate with a single or multiple bit input x and a single bit output y.\n1\nδ\n–\n(\n)\n3. Due to space limits, if not provided, all proofs can be found in [12].\nE\n1\n2--CVdd\n2 sw\n=\nε\nsw z( )\n1\n2ε\n–\n(\n)2sw y\n( )\n2ε 1\nε\n–\n(\n)\n+\n=\nProceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’05) \n1530-1591/05 $ 20.00 IEEE\n\nindependent signals: \n. \n \nIt is interesting to note that failure-prone designs do not\nnecessarily experience a monotonic trend as far as switching\nactivity is concerned. As seen in Figure 2, while for smaller\nvalues of the error probability ε, the switching activity is less\naffected, for larger values (closer to 0.5) the switching activity\nbecomes closer to 0.5, thus making gates with smaller switching\nactivity more active and vice versa. In other words, increased\nerror rates make the output of a failure-prone device look more\nrandom and less likely to carry any useful information. \n4.2. Impact on Circuit Size\nAs shown in Theorem 1, any non-zero probability of error for a\nfailure-prone device affects its average switching activity. In\naddition, added redundancy does not come for free: it affects\nboth logic depth, as well as circuit size, which in turn affect\nperformance and energy cost of the entire system. \nIn this section, we quantify the impact of added logic\nredundancy on circuit size, for a given error probability per gate\nε, and a required maximum error probability on the output δ.\nThe following result provides the tightest bounds known for the\nminimum circuit size required for computing a Boolean\nfunction with a given output fault-tolerance:\nTheorem 2. [13] For \n and \n, if a Boolean\nfunction is \n-reliably computed by a circuit with ε-noisy,\nk-input gates, then the additional redundancy in the circuit is at\nleast:1\nwhere s is the sensitivity of Boolean function f (or the maximum\nnumber of inputs that, if changed individually, produce a change\non the output), \n, and \n.\nThe theorem confirms previous results [14,15] that show an\n proportionality relation for the error-prone circuit size,\nbut points to a superlinear increase in complexity with increased\nvalues of ε. Indeed, for ε values close to 0.5, circuit size\napproaches infinity, thus making \n-reliable computation\nimpossible for all practical purposes. On the other hand, it has\nbeen shown [2,3,5] that an upper bound on the size of a fault-\ntolerant circuit is \n (S0 is the size of the error-free\nimplementation). For both the upper and lower bounds, equality\nis achieved for parity functions, implemented using decision\ntrees or Shannon-like circuits. While the result above holds for\nsingle output circuits (Boolean functions), we extend it to\ngeneral circuits below:\nCorollary 1. For \n and \n, if an m-output\nfunction of n inputs \n is \n-reliably\ncomputed by a circuit with ε-noisy, k-input gates, then the\nadditional redundancy in the circuit is at least:\nwhere s is the sensitivity of the multiple output function f , and\n are as in Theorem 2.\nHint for proof: The characteristic function for f is a single\noutput function with the same sensitivity. \nTo understand the impact of increased gate count due to\nadded redundancy, we show in Figure 3 the lower bound from\nTheorem 2 and Corollary 1 as a function of device error ε to\n-reliably compute a 10-input parity function with\nsensitivity s = 10, error-free size S0 = 21, and δ = 0.01. We note\nthat more than an order of magnitude redundancy factor is\nneeded for error levels close to 0.5. It is thus expected that the\nincreased size will also impact the total load capacitance and\nenergy cost of the implementation.\n4.3. Impact on Switching Energy\nThe impact of using redundancy on the energy of fault-tolerant\nnanoscale designs can be quantified through: 1) the change in\nthe average switching activity for a generic internal gate; and 2)\nthe change in the required number of devices needed to achieve\na certain output reliability. Since we assume that, if considered\nerror-free, redundant logic behaves almost the same as the\noriginal circuit in terms of switching activity, one can infer that\nTheorem 1 holds for the average switching activity of the error-\nfree and error-prone circuits implementing the same function.\nIn addition, Corollary 1 can be used to quantify the increase\nin \nthe \ntotal \nload \ncapacitance \nof \nthe \nfault-tolerant\n1. In this paper, log is assumed base two, unless noted otherwise.\nsw z( )\n2p z( ) 1\np z( )\n–\n(\n)\n=\nFigure 2. Switching activity of error-prone devices as a function\nof the switching activity of error-free devices.\nε increases\n0\nε\n<\n1 2\n⁄\n≤\n0\nδ\n≤\n1 2\n⁄\n<\n1\nδ\n–\n(\n)\ns\ns\n2s\n2 1\n2δ\n–\n(\n)\n(\n)\nlog\n⋅\n+\nlog\n⋅\nk\nt\nlog\n⋅\n----------------------------------------------------------------------\nt\nω3\n1\nω\n–\n(\n)3\n+\nω 1\nω\n–\n(\n)\n--------------------------------\n=\nω\n1\n1\n2ε\n–\nk\n–\n2\n---------------------------\n=\ns\ns\nlog\n⋅\n1\nδ\n–\n(\n)\nO S0\nS0\nlog\n⋅\n(\n)\n0\nε\n<\n1 2\n⁄\n≤\n0\nδ\n≤\n1 2\n⁄\n<\nf : 0 1\n,\n{\n}n\n0 1\n,\n{\n}m\n→\n1\nδ\n–\n(\n)\ns\ns\n2s\n2 1\n2δ\n–\n(\n)\n(\n)\nlog\n⋅\n+\nlog\n⋅\nk\nt\nlog\n⋅\n----------------------------------------------------------------------\nt ω\n,\n1\nδ\n–\n(\n)\nFigure 3. Minimum redundancy needed as a function of the device\nerror ε, for s = 10, S0 = 21, and δ = 0.01 assuming 2-, 3-, and 4-\ninput gate implementations.\nProceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’05) \n1530-1591/05 $ 20.00 IEEE\n\nimplementation: most high-level energy estimation frameworks\nhave shown that total load capacitance is, with sufficient\naccuracy, proportional to the total device count [16,17]. Thus,\none can conclude that the increase factor in energy for a fault-\ntolerant implementation satisfies the following:\nCorollary 2. Consider \n. The energy Eε,δ\nof a circuit composed of ε-noisy, k-input gates, that \n-\nreliably computes f satisfies:\nwhere E0 is the energy cost of the error-free implementation, s is\nthe sensitivity of f , sw0 (\n) is the average switching\nactivity per gate of the error-free implementation, S0 is the size\nof the error-free circuit implementing f , and \n are as in\nTheorem 2.\nHint for proof: Uses Theorems 1-2 for energy estimation,\nassuming load capacitance is proportional to the total device\ncount [16][17].\n5. Case Study: Nanoscale CMOS Designs\nThe results presented in Section 4 hold true for the switching\nenergy of any nanoscale computing system that relies on\nirreversible switching devices that use electrons and energy\nbarriers to represent or manipulate their states. However, it is\nworth noting that, in the particular case of nanoscale CMOS\ndesigns (i.e., 0.09um and beyond) leakage power becomes the\ndominant component of the overall power, and thus increased\nredundancy implies increased number of idle devices or more\nleakage power. In addition, added logic redundancy comes at\nthe expense of increased logic depth, which affects negatively\ncircuit latency and overall performance. We address in the\nsequel some of these issues and the available trade-offs between\nswitching energy bounds and leakage cost or performance.\n5.1. Impact on Leakage Power\nWhile the direct impact of logic redundancy on static power is\nclear through the increased number of potentially idle devices,\nthere is a more subtle effect on leakage energy, due to changes\nin average switching activity per gate. More precisely, with\nprobability \n a generic gate in the error-prone circuit\nis idle and subject to leakage energy, not switching energy.\nThus, any change in the average switching activity triggers a\nchange in the overall contribution of leakage energy to overall\ncircuit energy. The next result details this change:\nTheorem 3. If \n is the ratio of leakage energy to switching\nenergy in a circuit composed of ε-noisy gates, then:\nwhere \n is the ratio of leakage energy to switching energy\nin the error-free case and sw0 (\n) is the average\nswitching activity per gate of the error-free implementation.\nHint for proof: Since switching energy \n and\nstatic energy \n (S0 is the size of the\ncircuit, Vdd the supply voltage, and K is a factor that depends on\ntechnology and threshold voltage), we can use Theorems 1-2 to\ndetermine switching/static energy in the error-prone case.\nTo understand how the relative contribution to the overall\nenergy cost changes, we show in Figure 4 the variation of the\nnormalized ratio for the error-prone circuit, with respect to the\nerror-free implementation for various switching activity values\nand error probabilities. As it can be noticed, the relative\ncontribution of leakage energy decreases with increased error\nrates if the switching activity sw0 is less than 0.5. Indeed, in this\ncase, switching activity in the error-prone implementation\nincreases and thus devices are less likely to be idle. The\nopposite is true if the switching activity of the error-free circuit\nexceeds 0.5. The relative contribution stays the same if sw0 is\nexactly 0.5. \n5.2. Impact on Performance, Average Power and \nEnergy-Delay Product\nAdded redundancy is expected to have a significant effect on\nthe circuit depth as well, and thus on overall latency. Indeed, the\nfollowing result has been shown for circuit depth of fault-\ntolerant circuits:\nTheorem 4. [7] Consider \n. The logic\ndepth dε,δ of a circuit composed of ε-noisy, k-input gates, that\n-reliably computes f satisfies:\n•\nIf \n, then \n.\n•\nIf \n, then \n.\nwhere \n with \n1 and ∆ is defined as\nf : 0 1\n,\n{\n}n\n0 1\n,\n{\n}m\n→\n1\nδ\n–\n(\n)\nEε δ\n,\nE0\n---------\n1\ns\n2\n2 1\n2δ\n–\n(\n)\n(\n)\nlog\n⋅\n+\nlog\n(\n)\nk\nt\nlog\n⋅\n-----------------------------------------------------------------\ns\nS0\n----\n⋅\n+\n1\n2ε\n–\n(\n)2\n2ε 1\nε\n–\n(\n)\nsw0\n----------------------\n+\n⋅\n≥\n0\nsw0\n1\n≤\n<\nt ω\n,\n1\nswε δ\n,\n–\n(\n)\nWL ε δ\n, ,\nWL ε δ\n, ,\nWL 0\n,\n----------------\n1\n2ε\n–\n(\n)2\n2ε 1\nε\n–\n(\n)\n1\nsw0\n–\n(\n)\n⁄\n+\n1\n2ε\n–\n(\n)2\n2ε 1\nε\n–\n(\n) sw0\n⁄\n+\n------------------------------------------------------------------------------\n=\nWL 0\n,\n0\nsw0\n1\n<\n<\n1. As shown in Section 4, only error levels that are less than 0.5 are of practical\ninterest, thus the error probability is modeled as \n.\nE0\nS0Vdd\n2 sw0\n∝\nEL 0\n,\n1\nsw0\n–\n(\n) S0 V\n⋅\ndd K\n⋅\n⋅\n∝\nFigure 4. Normalized ratio between leakage energy and switching\nenergy (\n) as a function of device error probability ε. The\nbaseline is the ratio for the error-free implementation (\n).\nNote the logarithmic scale on the Y-axis.\nWL ε δ\n, ,\nWL 0\n,\nf : 0 1\n,\n{\n}n\n0 1\n,\n{\n}m\n→\n1\nδ\n–\n(\n)\nξ2\n1 k\n⁄\n>\ndε δ\n,\nn∆\n(\n)\nlog\nkξ2\n(\n)\nlog\n⁄\n≥\nξ2\n1 k\n⁄\n≤\nn\n1 ∆\n⁄\n≤\nε\n1\nξ\n–\n(\n) 2\n⁄\n=\n0\nξ\n<\n1\n≤\n1\nξ\n–\n(\n) 2\n⁄\nProceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’05) \n1530-1591/05 $ 20.00 IEEE\n\n.\nIn other words, to achieve a given error resilience\n(characterized by δ), for sufficiently low error probabilities per\ngate, the minimum logic depth is inversely proportional to\n; otherwise, no circuit \n-reliably computes f ,\nunless the number of inputs is less than 1/∆. In the latter case, no\nknown bounds are available for the size of the fault-tolerant\nimplementation. \nAnalyzing these results, we note that, trade-offs between the\nfault-tolerance and performance, on one hand, and the average\npower consumption, or energyxdelay product, on the other\nhand, can be deduced. Assuming that the latency of the failure-\nprone circuit varies as \n [18] (where VT\nis the threshold voltage and α is a technology dependent factor),\nif the same energy budget as the error-free circuit is targeted, the\nfault-tolerant implementation will need to rely on a lower Vdd to\ncompensate for the change in switched capacitance, which in\nturn further increases overall latency. Similar conclusions can\nbe drawn if performance constraints need to be maintained\ninstead: in this case, Vdd must be increased to compensate for\nthe logic depth increase, thus triggering an energy increase. As\nshown in Figure 5, the lower bound for normalized\nenergyxdelay product is higher than the one for normalized\nlatency, for the same error level. This comes at no surprise,\ngiven the fact that both energy and delay increase for the fault-\ntolerant circuit implementation. However, the same cannot be\nsaid about the average power (or energy spent per unit time). \nFigure 6 shows the dependency of the normalized average\npower on the device error probability and internal gates fanin.\nAs it can be seen, for low error rates, the average power of the\nfault-tolerant implementation is larger than the one of the error-\nfree circuit: in this case, delay increases at a lower rate than\ncircuit size, and thus energy. Furthermore, a larger fanin reduces\nthe overhead in average power. For larger error rates, however,\nthe logic depth (and thus delay) increases at much higher rates\nthan circuit size, thus making error-resilient implementations\nmore power efficient, at the expense of significantly larger\ndelays. In this case, larger fanins introduce a smaller power\nreduction as the difference in the increase rate for circuit depth\nand circuit size tapers off. \n6. Results\nAlthough the theoretical results presented in previous sections\nare applicable on average to generic circuits, it is worthwhile to\ninvestigate how do these lower bounds apply for specific\nbenchmarks. Even though all lower bounds presented are tight\nfor a certain family of Boolean functions (mainly, parity\nfunctions implemented using decision-trees or based on a\nShannon-like organization), when applied to specific circuits,\nthese bounds still offer an idea about the possible trends that\nswitching (and static) energy may have for fault-tolerant\nnanoscale designs. \nTo this end, we consider a subset of ISCAS’85 benchmarks\nand some computer arithmetic circuits (ripple-carry adders and\narray multipliers) with various bitwidths. The ISCAS’85\nbenchmarks have been optimized in the SIS [19] environment\nusing script.rugged. All benchmarks have been mapped using a\ngeneric library comprised of gates with a maximum fanin of\nthree. The average switching activity of a generic gate part of\neach benchmark has been obtained considering randomly\ngenerated inputs. For the error-free implementation we have\nassumed that 50% of the total energy is leakage (which is inline\nwith predictions for technologies smaller than 0.09um [8]).\nWe show in Figure 7 the lower bounds for the energy and\ndelay of the fault-tolerant implementation, normalized with\nrespect to the error-free implementation. In each case, we\nconsider three scenarios corresponding to gates independently\nfailing with probability ε = {0.001, 0.01, 0.1}, and required\nmaximum probability on the output δ = 0.01. As it can be seen,\nthe lower bounds increase significantly with higher error rates,\nnecessitating in some cases at least 40% more energy if error\n∆\n1\nδ\nδ\nlog\n1\nδ\n–\n(\n)\n1\nδ\n–\n(\n)\nlog\n+\n+\n=\nkξ2\n(\n)\nlog\n1\nδ\n–\n(\n)\nDε δ\n,\ndε δ\n,\nVdd\nVdd\nVT\n–\n(\n)α\n----------------------------\n⋅\n∝\nFigure 5. Normalized delay (energyxdelay) as a function of ε. The\nbaseline is the delay (energyxdelay) for the error-free\nimplementation. The contributions of the switching and leakage\nenergy are assumed equal and switching activity is considered 0.5\nin the baseline. All other parameters are as in Figure 3. Note the\nlogarithmic scale on the Y-axis.\nFigure 6. Normalized average power as a function of device error\nprobability ε. The baseline is the average power for the error-free\nimplementation. The contributions of the switching and leakage\nenergy are assumed equal and the switching activity is considered\n0.5 in the baseline. All other parameters are as in Figure 3. \nProceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’05) \n1530-1591/05 $ 20.00 IEEE\n\nrates are 1% per gate. We note that, while energy bounds are\nmore circuit dependent (due to Boolean sensitivity s and\nswitching activity sw0), delay is less so, as the only circuit\nspecific information it relies on is the average fanin k. Figure 8\nshows the trend for the average power and energyxdelay lower\nbounds, \nnormalized \nwith \nrespect \nto \nthe \nerror-free\nimplementation. While energyxdelay lower bound experiences\nup to a 2.8X increase, average power is reduced due to the\nsignificant increase in logic depth (and latency). \n7. Conclusion\nThis paper has introduced the use of complexity theory concepts\nfor determining lower bounds on energy and related metrics for\nnanoscale, fault-tolerant designs. The theoretical results\npresented herein can be used to guide the automatic synthesis of\nerror-prone nanoscale designs, while also uncovering the\ninterplay between switching and static energy for these systems.\nFuture work includes the treatment of sequential circuits and the\nrefinement of the lower bounds depending on the circuit\nfunctionality.\n8. References\nFigure 7. Lower bounds for energy and delay for ε = {0.001, 0.01,\n0.1} and δ = 0.01, normalized with respect to the error-free\nimplementation. The contributions of switching and leakage\nenergy are assumed equal in the error-free baseline. \nFigure 8. Lower bounds for average power and energyxdelay for ε\n= {0.001, 0.01, 0.1} and δ = 0.01, normalized with respect to the\nerror-free implementation. The contributions of switching and\nleakage energy are assumed equal in the error-free baseline. \n[1]\nJ. von Neumann, J., “Probabilistic Logics and the Synthesis of\nReliable Organisms from Unreliable Components,” pp. 43-98 in\nAutomata Studies, C. E. Shannon, J. McCarthy, eds., Princeton Univ.\nPress, Princeton, N.J. (1956); Also in Collected Works, vol. 5:329-\n378.\n[2]\nN. Pippenger, “Reliable computation by formulas in the presence of\nnoise,” in IEEE Transactions on Information Theory, vol. 34, no. 2,\npp. 194-197, February 1988.\n[3]\nN. Pippenger, G.D. Stamoulis, and J.N. Tsitsiklis, “On a lower bound\nfor the redundancy of reliable networks with noisy gates,” in IEEE\nTransactions on Information Theory, vol. 37, no. 3, pp. 639-643,\nMarch 1991.\n[4]\nD. Kleitman, T. Leighton, and Y. Ma, “On the design of reliable\nBoolean circuits that contain partially unreliable gates,” in 35th\nIEEE Annual Symposium on Foundations of Computer Science, pp.\n332-346, Santa Fe, New Mexico, November 1994.\n[5]\nP. G'acs and A. G'al, “Lower bounds for the complexity of reliable\nBoolean circuits with noisy gates,” in IEEE Transactions on\nInformation Theory, vol. 40, no. 2, pp. 579-583, March 1994.\n[6]\nW. Evans and N. Pippenger, “On the maximum tolerable noise for\nreliable computation by formulas,” in IEEE Transactions on\nInformation Theory, vol. 44, no. 3, pp. 1299-1305, May 1998. \n[7]\nW. Evans and L. J. Schulman, “Signal propagation and noisy\ncircuits,” in IEEE Transactions on Information Theory, vol. 45, no.\n7, pp. 2367-2373, November 1999. \n[8]\nInternational Technology Roadmap for Semiconductors (http://\npublic.itrs.net), 2003.\n[9]\nV. V. Zhirnov, R. K. Cavin, J. A. Hutchby, G. I. Bourianoff, “Limits to\nBinary Logic Switch Scaling - A Gedanken Model,” in Proc. of the\nIEEE, Special Issue on Nanoelectronics and Nanoscale Processing,\nvol. 91, no. 11, pp. 1934-1939, November 2003.\n[10]\nR. I. Bahar, J. Mundy, and J. Chen, “A Probabilistic-Based Design\nMethodology for Nanoscale Computation,” in Proc. IEEE/ACM Intl.\nConf. on Computer-Aided Design, San Jose, CA, Nov. 2003.\n[11]\nR. Hegde and N. R. Shanbhag, “Towards achieving energy-\nefficiency in presence of deep submicron noise,” in IEEE\nTransactions on VLSI Systems, vol. 8, no. 4, pp. 379-391, Aug. 2000. \n[12]\nD. Marculescu, “Fault-Tolerant Nanoscale Design: An Energy\nPerspective,” Technical Report CSSI 04-33, Sept. 2004 (http://\nwww.ece.cmu.edu/~dianam/conferences). \n[13]\nW. Evans, “Information Theory and Noisy Computation,” PhD\nthesis, University of California at Berkeley, 1994 (UC Berkeley\nTechnical Report 94-057). \n[14]\nA. G’al, “Combinatorial Methods in Boolean Function Complexity,”\nPh.D.-thesis, University of Chicago, 1995.\n[15]\nR. Reischuk, B. Schmeltz, “Reliable Computation with Noisy\nCircuits and Decision Trees, A General nlogn Lower Bound,” in\nProc. IEEE Conference on Foundations of Computer Science, pp.\n602-611, San Juan, Puerto Rico, 1991.\n[16]\nM. Nemani and F. N. Najm, “Towards a high-level power estimation\ncapability,” in IEEE Transactions on Computer-Aided Design, vol.\n15, no. 6, pp. 588-598, June 1996.\n[17]\nD. Marculescu, R. Marculescu, and M. Pedram, “Information-\nTheoretic Measures for Power Analysis,” in IEEE Transactions on\nComputer-Aided Design of Circuits and Systems, vol. 15, no. 6, pp.\n599-610, June 1996.\n[18]\nK. Chen and C. Hu, “Performance and Vdd Scaling in Deep\nSubmicrometer CMOS,” in IEEE Journal of Solid State Circuits,\nOct. 1998.\n[19]\nE. M. Sentovich et al., “SIS: A System for Sequential Circuit\nSynthesis,” Technical Report UCB/ERL M92/41, Electronics\nResearch Lab, Univ. of California, Berkeley, May 1992.\nProceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’05) \n1530-1591/05 $ 20.00 IEEE","paragraphs":[{"paragraph_id":"p1","order":1,"text":"Abstract - The problem of determining lower bounds for the\nenergy cost of a given nanoscale design is addressed via a\ncomplexity theory-based approach. This paper provides a\ntheoretical framework that is able to assess the trade-offs\nexisting in nanoscale designs between the amount of\nredundancy needed for a given level of resilience to errors and\nthe associated energy cost. Circuit size, logic depth and error\nresilience are analyzed and brought together in a theoretical\nframework that can be seamlessly integrated with automated\nsynthesis tools and can guide the design process of nanoscale\nsystems comprised of failure prone devices. The impact of\nredundancy addition on the switching energy and its\nrelationship with leakage energy is modeled in detail. Results\nshow that 99% error resilience is possible for fault-tolerant\ndesigns, but at the expense of at least 40% more energy if\nindividual gates fail independently with probability of 1%. \n1. Introduction \nNanoscale computing for either CMOS or non-CMOS\ntechnology is widely agreed to be characterized by non-\ndeterministic and unreliable behavior. In the case of nanometer\nCMOS designs, uncertainties stem from process and system\nparameter variability and their impact on performance and\nbehavior of switching devices, as well as from increased\nsusceptibility to soft errors which may thus create incorrect or\nfaulty functionality. For non-CMOS nanoscale electronics (such\nas molecular or self-assembly), uncertainties in operation\noriginate in the inherent non-deterministic switching behavior\nof such devices. While fault-tolerant computing is a mature area\nof research, automatically designing reliable systems out of\nunreliable components may prove to be a challenging task. As a\nnatural solution to the fault-tolerance problem, the use of\nredundancy has been proposed and analyzed theoretically as\nearly as five decades ago in the seminal work of von Neumann\n[1] and more recently by others [2,3,4,5,6,7]. While a practical\nsolution to synthesizing in an automated manner nanoscale\ndesigns that are inherently fault-tolerant has yet to be found,\nnonetheless such theoretical results offer a good insight into the\nachievable limits of error-resilience and required minimum\nredundancy (or extra logic) needed. Furthermore, in the case of\nCMOS nanoscale technology, power density and energy cost\nhave become the main design bottlenecks [8]. Adding\nredundancy in the hope of increasing error-resilience has the\nnegative effect of eventually decreasing the energy efficiency of\na given design. Thus, given the clear trade-off between\nachieving resilience via redundancy addition and energy\nefficiency, tools that can aid and guide the design process in a\nnanoscale design methodology become mandatory. \nThis paper is a step in this direction, by proposing theoretic\nlower bounds and trade-offs between energy efficiency and\nredundancy needed for achieving a certain error-resilience level.\nSuch bounds and theoretical trade-offs provide valuable insights\nearly in the design process and may aid and guide the automatic\nsynthesis process of nanoscale systems.\nWhile the fault-\ntolerance aspects described in this paper are relevant for any\ntype of nanoscale designs based on emerging technologies that\ninherently include non-determinism in normal operation, we\nwill restrict ourselves to considering as a driver application\ncomputing systems that use electrons and energy barriers to\nrepresent or manipulate their states [9]. CMOS nanoscale\ndesigns are one such example. Based on first principle physics\nlaws, it has been shown recently [9] that power density of such\ndesigns will reach in the next decade values close to 100 Watts/\ncm2. \nThese \npower \ndensities, \ncoupled \nwith \nincreased\ncomplexities and integration densities, put a lot more pressure\non achieving more efficient designs in the nanoscale era. To\naddress this problem, we consider the case of fault-tolerant\nnanoscale systems which need to rely on added redundancy to\nbe able to cope with increased error rates. To characterize the\navailable trade-offs between the required redundancy and the\nassociated energy cost, we propose the use of a complexity\ntheory-based framework. \n2. Related Work and Paper Contribution\nThis paper addresses the impact of error-resilience and\nredundancy in a theoretical framework that can guide the design\nprocess for nanoscale systems. Our framework is able to\nprovide bounds on the energy cost associated with achieving a\ngiven error-resilience level for a design based on error-prone\ngates (characterized by non-deterministic behavior), while also\ndetailing when these bounds are likely to be tight. As opposed\nto the theoretical bounds developed by von Neumann and his\nsuccessors [1,2,3,4,5,6], our approach does not assume any\nparticular use of redundancy, such as majority voting or parallel\nrestitution [1]. Instead, it is based on a framework relying on\ninformation theory concepts [7] to quantify the energy\nefficiency of nanoscale designs in the presence of errors. \nWhile the problem of analyzing the fault-tolerance of\nnanoscale designs under given gate or wire error models has\nbeen recently started to gain interest [10], no such study has\nlinked the error-resilience of a circuit to its energy efficiency.\nRecent work [11] has shown, using information theoretic\narguments, that it is possible to trade-off energy efficiency and\nfault-tolerance through the use of voltage scaling. Indeed, by\nEnergy Bounds for Fault-Tolerant Nanoscale Designs\nDiana Marculescu\nDept. of Electrical and Computer Engineering\nCarnegie Mellon University\nPittsburgh, PA 15213\nProceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’05) \n1530-1591/05 $ 20.00 IEEE"},{"paragraph_id":"p2","order":2,"text":"allowing the voltage to be reduced, power cost is reduced\nsignificantly, while noise level is increased, thereby allowing\nfor trading-off energy and error-resilience. However, our goal is\ndifferent. We propose to quantify how added redundancy\nnecessary for achieving reliable operation out of unreliable\ncomponents impacts overall energy efficiency of a nanoscale\ndesign. In addition, our approach is not bound to any particular\ntype of redundancy (based on techniques such as majority\nvoting or parallel restitution) and assumes that “noisy” gates\nand can be modeled as error-free devices cascaded with a\nsymmetric communication channel modeling the error. In\naddition, while previous work [11] has linked energy efficiency\nand fault-tolerance in an information theoretic environment, it\ntargets voltage scaling-reliability trade-offs and does not\naddress entities that are more complex than a single gate or\ndevice. Our theoretical framework is able to completely\ncharacterize complex designs in terms of the energy-error-\nresilience trade-offs, while also providing insights into the\nrelative contributions of static and switching energy. \n3. Preliminaries\nWithout loss of generality, we restrict ourselves to nanoscale\nsystems with the following characteristics:\n•\nCircuits are assumed comprised of devices or gates that can\nbe either error-free, or failure prone.1\n•\nWe consider the case of error-free and failure-prone circuits\nin which internal gates can fail independently with a\nprobability \n.2 We assume that any interconnect\nerror \nprobabilities \nare \nlumped \ninto \ndevice \nerror\nprobabilities.\n•\nWe also consider device (gate) output error probabilities\nmodeled as symmetric communication channels with an ε\nerror probability. As shown in Figure 1, each failure-prone\ndevice is assumed modeled as an error-free device\ncascaded with a symmetric communication channel.\n•\nFor the case of failure-prone circuits, we consider the case\nof \n-reliable computation, that is, with probability of\n1-δ, the output of the circuit is correct. \n•\nWhile not restricting ourselves to any particular technology\ncharacterized by failure-prone operation, we consider the\ncase of systems that use electrons and energy barriers to\nrepresent or manipulate their states. Examples include\nnanoscale CMOS applications or systems comprised of\nirreversible logic switch devices. \n•\nGiven this constraint, we are mostly concerned with\nswitching energy or the energy lost due to information\nprocessing or transfer. \nTo this end, we consider the impact that any additional\nredundancy added to increase error resilience has on the overall\nenergy efficiency of a nanoscale design. Assuming that most of\nthe switching energy is consumed during output charging and\ndischarging (\n, where E is the total energy\nconsumed during a certain time interval, Vdd is the supply\nvoltage, C is the load capacitance and sw is the total switching\nactivity during the considered interval), fault-tolerant circuits\nrelying on added redundancy for increased error resilience can\nhave both their load capacitance and switching activity affected.\nIn addition, added redundancy may also impact logic depth, and\nthus overall latency. To this end, trade-offs between energy,\ndelay or composite metrics (such as energy-delay product) on\none hand, and required output error resilience δ, on the other\nhand, can be uncovered and analyzed in an analytical manner.\n4. Bounds on Switching Energy Metrics\nIntuitively, added logic redundancy, not necessarily committed\nto any particular implementation (e.g., majority based voting\nused in triple or n-tuple modular redundancy vs. parallel\nrestitution [1]) is expected to increase the error resilience of a\nfailure-prone nanoscale design by providing multiple logical\npaths from the inputs to the outputs, thus decreasing the impact\nof the “noise” on the overall input-output communication\nchannel. One may expect that the added redundant logic (when\nerror-free) will perform in a similar manner as far as switching\nactivity is concerned. However, we note that a non-zero error\nprobability on the output of each device (be it part of the\noriginal circuit, or part of the redundant logic) can affect the\nswitching behavior of that gate output, as shown next.\n4.1. Impact on Switching Activity\nIn what follows, we denote by p(x) the probability of a binary\nrandom variable x being one and by sw(x) the probability that x\nchanges state. We also denote by x an array of binary variables,\nand by f a multiple output Boolean function.\nThe following result quantifies the change in the switching\nactivity that a given “noise” level produces on the output of a\nswitching device:\nTheorem 1. If y, z are the error-free and error-prone outputs of a\ndevice which fails with a probability of as in Figure 1, then:\n.\nHint for proof:3 Uses switching activity definition for temporal\n1. Devices and gates are assumed to denote the same entity in this paper.\n2. As it will be seen in the sequel, if error probabilities are close to 1/2, reliable\ncomputation is not possible unless an unbounded overhead is considered. \n0\nε\n1 2\n⁄\n≤\n≤\nError-free\n device\nError\nmodel\nx\ny\nz\n0 0\n1 1\nε\n1\nε\n–\n1\nε\n–\ny\nz\nε\nFigure 1. Modeling error-prone devices using error-free devices and a symmetric communication channel error model ε. The error-\nfree device is a gate with a single or multiple bit input x and a single bit output y.\n1\nδ\n–\n(\n)\n3. Due to space limits, if not provided, all proofs can be found in [12].\nE\n1\n2--CVdd\n2 sw\n=\nε\nsw z( )\n1\n2ε\n–\n(\n)2sw y\n( )\n2ε 1\nε\n–\n(\n)\n+\n=\nProceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’05) \n1530-1591/05 $ 20.00 IEEE"},{"paragraph_id":"p3","order":3,"text":"independent signals: \n."},{"paragraph_id":"p4","order":4,"text":"It is interesting to note that failure-prone designs do not\nnecessarily experience a monotonic trend as far as switching\nactivity is concerned. As seen in Figure 2, while for smaller\nvalues of the error probability ε, the switching activity is less\naffected, for larger values (closer to 0.5) the switching activity\nbecomes closer to 0.5, thus making gates with smaller switching\nactivity more active and vice versa. In other words, increased\nerror rates make the output of a failure-prone device look more\nrandom and less likely to carry any useful information. \n4.2. Impact on Circuit Size\nAs shown in Theorem 1, any non-zero probability of error for a\nfailure-prone device affects its average switching activity. In\naddition, added redundancy does not come for free: it affects\nboth logic depth, as well as circuit size, which in turn affect\nperformance and energy cost of the entire system. \nIn this section, we quantify the impact of added logic\nredundancy on circuit size, for a given error probability per gate\nε, and a required maximum error probability on the output δ.\nThe following result provides the tightest bounds known for the\nminimum circuit size required for computing a Boolean\nfunction with a given output fault-tolerance:\nTheorem 2. [13] For \n and \n, if a Boolean\nfunction is \n-reliably computed by a circuit with ε-noisy,\nk-input gates, then the additional redundancy in the circuit is at\nleast:1\nwhere s is the sensitivity of Boolean function f (or the maximum\nnumber of inputs that, if changed individually, produce a change\non the output), \n, and \n.\nThe theorem confirms previous results [14,15] that show an\n proportionality relation for the error-prone circuit size,\nbut points to a superlinear increase in complexity with increased\nvalues of ε. Indeed, for ε values close to 0.5, circuit size\napproaches infinity, thus making \n-reliable computation\nimpossible for all practical purposes. On the other hand, it has\nbeen shown [2,3,5] that an upper bound on the size of a fault-\ntolerant circuit is \n (S0 is the size of the error-free\nimplementation). For both the upper and lower bounds, equality\nis achieved for parity functions, implemented using decision\ntrees or Shannon-like circuits. While the result above holds for\nsingle output circuits (Boolean functions), we extend it to\ngeneral circuits below:\nCorollary 1. For \n and \n, if an m-output\nfunction of n inputs \n is \n-reliably\ncomputed by a circuit with ε-noisy, k-input gates, then the\nadditional redundancy in the circuit is at least:\nwhere s is the sensitivity of the multiple output function f , and\n are as in Theorem 2.\nHint for proof: The characteristic function for f is a single\noutput function with the same sensitivity. \nTo understand the impact of increased gate count due to\nadded redundancy, we show in Figure 3 the lower bound from\nTheorem 2 and Corollary 1 as a function of device error ε to\n-reliably compute a 10-input parity function with\nsensitivity s = 10, error-free size S0 = 21, and δ = 0.01. We note\nthat more than an order of magnitude redundancy factor is\nneeded for error levels close to 0.5. It is thus expected that the\nincreased size will also impact the total load capacitance and\nenergy cost of the implementation.\n4.3. Impact on Switching Energy\nThe impact of using redundancy on the energy of fault-tolerant\nnanoscale designs can be quantified through: 1) the change in\nthe average switching activity for a generic internal gate; and 2)\nthe change in the required number of devices needed to achieve\na certain output reliability. Since we assume that, if considered\nerror-free, redundant logic behaves almost the same as the\noriginal circuit in terms of switching activity, one can infer that\nTheorem 1 holds for the average switching activity of the error-\nfree and error-prone circuits implementing the same function.\nIn addition, Corollary 1 can be used to quantify the increase\nin \nthe \ntotal \nload \ncapacitance \nof \nthe \nfault-tolerant\n1. In this paper, log is assumed base two, unless noted otherwise.\nsw z( )\n2p z( ) 1\np z( )\n–\n(\n)\n=\nFigure 2. Switching activity of error-prone devices as a function\nof the switching activity of error-free devices.\nε increases\n0\nε\n<\n1 2\n⁄\n≤\n0\nδ\n≤\n1 2\n⁄\n<\n1\nδ\n–\n(\n)\ns\ns\n2s\n2 1\n2δ\n–\n(\n)\n(\n)\nlog\n⋅\n+\nlog\n⋅\nk\nt\nlog\n⋅\n----------------------------------------------------------------------\nt\nω3\n1\nω\n–\n(\n)3\n+\nω 1\nω\n–\n(\n)\n--------------------------------\n=\nω\n1\n1\n2ε\n–\nk\n–\n2\n---------------------------\n=\ns\ns\nlog\n⋅\n1\nδ\n–\n(\n)\nO S0\nS0\nlog\n⋅\n(\n)\n0\nε\n<\n1 2\n⁄\n≤\n0\nδ\n≤\n1 2\n⁄\n<\nf : 0 1\n,\n{\n}n\n0 1\n,\n{\n}m\n→\n1\nδ\n–\n(\n)\ns\ns\n2s\n2 1\n2δ\n–\n(\n)\n(\n)\nlog\n⋅\n+\nlog\n⋅\nk\nt\nlog\n⋅\n----------------------------------------------------------------------\nt ω\n,\n1\nδ\n–\n(\n)\nFigure 3. Minimum redundancy needed as a function of the device\nerror ε, for s = 10, S0 = 21, and δ = 0.01 assuming 2-, 3-, and 4-\ninput gate implementations.\nProceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’05) \n1530-1591/05 $ 20.00 IEEE"},{"paragraph_id":"p5","order":5,"text":"implementation: most high-level energy estimation frameworks\nhave shown that total load capacitance is, with sufficient\naccuracy, proportional to the total device count [16,17]. Thus,\none can conclude that the increase factor in energy for a fault-\ntolerant implementation satisfies the following:\nCorollary 2. Consider \n. The energy Eε,δ\nof a circuit composed of ε-noisy, k-input gates, that \n-\nreliably computes f satisfies:\nwhere E0 is the energy cost of the error-free implementation, s is\nthe sensitivity of f , sw0 (\n) is the average switching\nactivity per gate of the error-free implementation, S0 is the size\nof the error-free circuit implementing f , and \n are as in\nTheorem 2.\nHint for proof: Uses Theorems 1-2 for energy estimation,\nassuming load capacitance is proportional to the total device\ncount [16][17].\n5. Case Study: Nanoscale CMOS Designs\nThe results presented in Section 4 hold true for the switching\nenergy of any nanoscale computing system that relies on\nirreversible switching devices that use electrons and energy\nbarriers to represent or manipulate their states. However, it is\nworth noting that, in the particular case of nanoscale CMOS\ndesigns (i.e., 0.09um and beyond) leakage power becomes the\ndominant component of the overall power, and thus increased\nredundancy implies increased number of idle devices or more\nleakage power. In addition, added logic redundancy comes at\nthe expense of increased logic depth, which affects negatively\ncircuit latency and overall performance. We address in the\nsequel some of these issues and the available trade-offs between\nswitching energy bounds and leakage cost or performance.\n5.1. Impact on Leakage Power\nWhile the direct impact of logic redundancy on static power is\nclear through the increased number of potentially idle devices,\nthere is a more subtle effect on leakage energy, due to changes\nin average switching activity per gate. More precisely, with\nprobability \n a generic gate in the error-prone circuit\nis idle and subject to leakage energy, not switching energy.\nThus, any change in the average switching activity triggers a\nchange in the overall contribution of leakage energy to overall\ncircuit energy. The next result details this change:\nTheorem 3. If \n is the ratio of leakage energy to switching\nenergy in a circuit composed of ε-noisy gates, then:\nwhere \n is the ratio of leakage energy to switching energy\nin the error-free case and sw0 (\n) is the average\nswitching activity per gate of the error-free implementation.\nHint for proof: Since switching energy \n and\nstatic energy \n (S0 is the size of the\ncircuit, Vdd the supply voltage, and K is a factor that depends on\ntechnology and threshold voltage), we can use Theorems 1-2 to\ndetermine switching/static energy in the error-prone case.\nTo understand how the relative contribution to the overall\nenergy cost changes, we show in Figure 4 the variation of the\nnormalized ratio for the error-prone circuit, with respect to the\nerror-free implementation for various switching activity values\nand error probabilities. As it can be noticed, the relative\ncontribution of leakage energy decreases with increased error\nrates if the switching activity sw0 is less than 0.5. Indeed, in this\ncase, switching activity in the error-prone implementation\nincreases and thus devices are less likely to be idle. The\nopposite is true if the switching activity of the error-free circuit\nexceeds 0.5. The relative contribution stays the same if sw0 is\nexactly 0.5. \n5.2. Impact on Performance, Average Power and \nEnergy-Delay Product\nAdded redundancy is expected to have a significant effect on\nthe circuit depth as well, and thus on overall latency. Indeed, the\nfollowing result has been shown for circuit depth of fault-\ntolerant circuits:\nTheorem 4. [7] Consider \n. The logic\ndepth dε,δ of a circuit composed of ε-noisy, k-input gates, that\n-reliably computes f satisfies:\n•\nIf \n, then \n.\n•\nIf \n, then \n.\nwhere \n with \n1 and ∆ is defined as\nf : 0 1\n,\n{\n}n\n0 1\n,\n{\n}m\n→\n1\nδ\n–\n(\n)\nEε δ\n,\nE0\n---------\n1\ns\n2\n2 1\n2δ\n–\n(\n)\n(\n)\nlog\n⋅\n+\nlog\n(\n)\nk\nt\nlog\n⋅\n-----------------------------------------------------------------\ns\nS0\n----\n⋅\n+\n1\n2ε\n–\n(\n)2\n2ε 1\nε\n–\n(\n)\nsw0\n----------------------\n+\n⋅\n≥\n0\nsw0\n1\n≤\n<\nt ω\n,\n1\nswε δ\n,\n–\n(\n)\nWL ε δ\n, ,\nWL ε δ\n, ,\nWL 0\n,\n----------------\n1\n2ε\n–\n(\n)2\n2ε 1\nε\n–\n(\n)\n1\nsw0\n–\n(\n)\n⁄\n+\n1\n2ε\n–\n(\n)2\n2ε 1\nε\n–\n(\n) sw0\n⁄\n+\n------------------------------------------------------------------------------\n=\nWL 0\n,\n0\nsw0\n1\n<\n<\n1. As shown in Section 4, only error levels that are less than 0.5 are of practical\ninterest, thus the error probability is modeled as \n.\nE0\nS0Vdd\n2 sw0\n∝\nEL 0\n,\n1\nsw0\n–\n(\n) S0 V\n⋅\ndd K\n⋅\n⋅\n∝\nFigure 4. Normalized ratio between leakage energy and switching\nenergy (\n) as a function of device error probability ε. The\nbaseline is the ratio for the error-free implementation (\n).\nNote the logarithmic scale on the Y-axis.\nWL ε δ\n, ,\nWL 0\n,\nf : 0 1\n,\n{\n}n\n0 1\n,\n{\n}m\n→\n1\nδ\n–\n(\n)\nξ2\n1 k\n⁄\n>\ndε δ\n,\nn∆\n(\n)\nlog\nkξ2\n(\n)\nlog\n⁄\n≥\nξ2\n1 k\n⁄\n≤\nn\n1 ∆\n⁄\n≤\nε\n1\nξ\n–\n(\n) 2\n⁄\n=\n0\nξ\n<\n1\n≤\n1\nξ\n–\n(\n) 2\n⁄\nProceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’05) \n1530-1591/05 $ 20.00 IEEE"},{"paragraph_id":"p6","order":6,"text":".\nIn other words, to achieve a given error resilience\n(characterized by δ), for sufficiently low error probabilities per\ngate, the minimum logic depth is inversely proportional to\n; otherwise, no circuit \n-reliably computes f ,\nunless the number of inputs is less than 1/∆. In the latter case, no\nknown bounds are available for the size of the fault-tolerant\nimplementation. \nAnalyzing these results, we note that, trade-offs between the\nfault-tolerance and performance, on one hand, and the average\npower consumption, or energyxdelay product, on the other\nhand, can be deduced. Assuming that the latency of the failure-\nprone circuit varies as \n [18] (where VT\nis the threshold voltage and α is a technology dependent factor),\nif the same energy budget as the error-free circuit is targeted, the\nfault-tolerant implementation will need to rely on a lower Vdd to\ncompensate for the change in switched capacitance, which in\nturn further increases overall latency. Similar conclusions can\nbe drawn if performance constraints need to be maintained\ninstead: in this case, Vdd must be increased to compensate for\nthe logic depth increase, thus triggering an energy increase. As\nshown in Figure 5, the lower bound for normalized\nenergyxdelay product is higher than the one for normalized\nlatency, for the same error level. This comes at no surprise,\ngiven the fact that both energy and delay increase for the fault-\ntolerant circuit implementation. However, the same cannot be\nsaid about the average power (or energy spent per unit time). \nFigure 6 shows the dependency of the normalized average\npower on the device error probability and internal gates fanin.\nAs it can be seen, for low error rates, the average power of the\nfault-tolerant implementation is larger than the one of the error-\nfree circuit: in this case, delay increases at a lower rate than\ncircuit size, and thus energy. Furthermore, a larger fanin reduces\nthe overhead in average power. For larger error rates, however,\nthe logic depth (and thus delay) increases at much higher rates\nthan circuit size, thus making error-resilient implementations\nmore power efficient, at the expense of significantly larger\ndelays. In this case, larger fanins introduce a smaller power\nreduction as the difference in the increase rate for circuit depth\nand circuit size tapers off. \n6. Results\nAlthough the theoretical results presented in previous sections\nare applicable on average to generic circuits, it is worthwhile to\ninvestigate how do these lower bounds apply for specific\nbenchmarks. Even though all lower bounds presented are tight\nfor a certain family of Boolean functions (mainly, parity\nfunctions implemented using decision-trees or based on a\nShannon-like organization), when applied to specific circuits,\nthese bounds still offer an idea about the possible trends that\nswitching (and static) energy may have for fault-tolerant\nnanoscale designs. \nTo this end, we consider a subset of ISCAS’85 benchmarks\nand some computer arithmetic circuits (ripple-carry adders and\narray multipliers) with various bitwidths. The ISCAS’85\nbenchmarks have been optimized in the SIS [19] environment\nusing script.rugged. All benchmarks have been mapped using a\ngeneric library comprised of gates with a maximum fanin of\nthree. The average switching activity of a generic gate part of\neach benchmark has been obtained considering randomly\ngenerated inputs. For the error-free implementation we have\nassumed that 50% of the total energy is leakage (which is inline\nwith predictions for technologies smaller than 0.09um [8]).\nWe show in Figure 7 the lower bounds for the energy and\ndelay of the fault-tolerant implementation, normalized with\nrespect to the error-free implementation. In each case, we\nconsider three scenarios corresponding to gates independently\nfailing with probability ε = {0.001, 0.01, 0.1}, and required\nmaximum probability on the output δ = 0.01. As it can be seen,\nthe lower bounds increase significantly with higher error rates,\nnecessitating in some cases at least 40% more energy if error\n∆\n1\nδ\nδ\nlog\n1\nδ\n–\n(\n)\n1\nδ\n–\n(\n)\nlog\n+\n+\n=\nkξ2\n(\n)\nlog\n1\nδ\n–\n(\n)\nDε δ\n,\ndε δ\n,\nVdd\nVdd\nVT\n–\n(\n)α\n----------------------------\n⋅\n∝\nFigure 5. Normalized delay (energyxdelay) as a function of ε. The\nbaseline is the delay (energyxdelay) for the error-free\nimplementation. The contributions of the switching and leakage\nenergy are assumed equal and switching activity is considered 0.5\nin the baseline. All other parameters are as in Figure 3. Note the\nlogarithmic scale on the Y-axis.\nFigure 6. Normalized average power as a function of device error\nprobability ε. The baseline is the average power for the error-free\nimplementation. The contributions of the switching and leakage\nenergy are assumed equal and the switching activity is considered\n0.5 in the baseline. All other parameters are as in Figure 3. \nProceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’05) \n1530-1591/05 $ 20.00 IEEE"},{"paragraph_id":"p7","order":7,"text":"rates are 1% per gate. We note that, while energy bounds are\nmore circuit dependent (due to Boolean sensitivity s and\nswitching activity sw0), delay is less so, as the only circuit\nspecific information it relies on is the average fanin k. Figure 8\nshows the trend for the average power and energyxdelay lower\nbounds, \nnormalized \nwith \nrespect \nto \nthe \nerror-free\nimplementation. While energyxdelay lower bound experiences\nup to a 2.8X increase, average power is reduced due to the\nsignificant increase in logic depth (and latency). \n7. Conclusion\nThis paper has introduced the use of complexity theory concepts\nfor determining lower bounds on energy and related metrics for\nnanoscale, fault-tolerant designs. The theoretical results\npresented herein can be used to guide the automatic synthesis of\nerror-prone nanoscale designs, while also uncovering the\ninterplay between switching and static energy for these systems.\nFuture work includes the treatment of sequential circuits and the\nrefinement of the lower bounds depending on the circuit\nfunctionality.\n8. References\nFigure 7. Lower bounds for energy and delay for ε = {0.001, 0.01,\n0.1} and δ = 0.01, normalized with respect to the error-free\nimplementation. The contributions of switching and leakage\nenergy are assumed equal in the error-free baseline. \nFigure 8. Lower bounds for average power and energyxdelay for ε\n= {0.001, 0.01, 0.1} and δ = 0.01, normalized with respect to the\nerror-free implementation. The contributions of switching and\nleakage energy are assumed equal in the error-free baseline. \n[1]\nJ. von Neumann, J., “Probabilistic Logics and the Synthesis of\nReliable Organisms from Unreliable Components,” pp. 43-98 in\nAutomata Studies, C. E. Shannon, J. McCarthy, eds., Princeton Univ.\nPress, Princeton, N.J. (1956); Also in Collected Works, vol. 5:329-\n378.\n[2]\nN. Pippenger, “Reliable computation by formulas in the presence of\nnoise,” in IEEE Transactions on Information Theory, vol. 34, no. 2,\npp. 194-197, February 1988.\n[3]\nN. Pippenger, G.D. Stamoulis, and J.N. Tsitsiklis, “On a lower bound\nfor the redundancy of reliable networks with noisy gates,” in IEEE\nTransactions on Information Theory, vol. 37, no. 3, pp. 639-643,\nMarch 1991.\n[4]\nD. Kleitman, T. Leighton, and Y. Ma, “On the design of reliable\nBoolean circuits that contain partially unreliable gates,” in 35th\nIEEE Annual Symposium on Foundations of Computer Science, pp.\n332-346, Santa Fe, New Mexico, November 1994.\n[5]\nP. G'acs and A. G'al, “Lower bounds for the complexity of reliable\nBoolean circuits with noisy gates,” in IEEE Transactions on\nInformation Theory, vol. 40, no. 2, pp. 579-583, March 1994.\n[6]\nW. Evans and N. Pippenger, “On the maximum tolerable noise for\nreliable computation by formulas,” in IEEE Transactions on\nInformation Theory, vol. 44, no. 3, pp. 1299-1305, May 1998. \n[7]\nW. Evans and L. J. Schulman, “Signal propagation and noisy\ncircuits,” in IEEE Transactions on Information Theory, vol. 45, no.\n7, pp. 2367-2373, November 1999. \n[8]\nInternational Technology Roadmap for Semiconductors (http://\npublic.itrs.net), 2003.\n[9]\nV. V. Zhirnov, R. K. Cavin, J. A. Hutchby, G. I. Bourianoff, “Limits to\nBinary Logic Switch Scaling - A Gedanken Model,” in Proc. of the\nIEEE, Special Issue on Nanoelectronics and Nanoscale Processing,\nvol. 91, no. 11, pp. 1934-1939, November 2003.\n[10]\nR. I. Bahar, J. Mundy, and J. Chen, “A Probabilistic-Based Design\nMethodology for Nanoscale Computation,” in Proc. IEEE/ACM Intl.\nConf. on Computer-Aided Design, San Jose, CA, Nov. 2003.\n[11]\nR. Hegde and N. R. Shanbhag, “Towards achieving energy-\nefficiency in presence of deep submicron noise,” in IEEE\nTransactions on VLSI Systems, vol. 8, no. 4, pp. 379-391, Aug. 2000. \n[12]\nD. Marculescu, “Fault-Tolerant Nanoscale Design: An Energy\nPerspective,” Technical Report CSSI 04-33, Sept. 2004 (http://\nwww.ece.cmu.edu/~dianam/conferences). \n[13]\nW. Evans, “Information Theory and Noisy Computation,” PhD\nthesis, University of California at Berkeley, 1994 (UC Berkeley\nTechnical Report 94-057). \n[14]\nA. G’al, “Combinatorial Methods in Boolean Function Complexity,”\nPh.D.-thesis, University of Chicago, 1995.\n[15]\nR. Reischuk, B. Schmeltz, “Reliable Computation with Noisy\nCircuits and Decision Trees, A General nlogn Lower Bound,” in\nProc. IEEE Conference on Foundations of Computer Science, pp.\n602-611, San Juan, Puerto Rico, 1991.\n[16]\nM. Nemani and F. N. Najm, “Towards a high-level power estimation\ncapability,” in IEEE Transactions on Computer-Aided Design, vol.\n15, no. 6, pp. 588-598, June 1996.\n[17]\nD. Marculescu, R. Marculescu, and M. Pedram, “Information-\nTheoretic Measures for Power Analysis,” in IEEE Transactions on\nComputer-Aided Design of Circuits and Systems, vol. 15, no. 6, pp.\n599-610, June 1996.\n[18]\nK. Chen and C. Hu, “Performance and Vdd Scaling in Deep\nSubmicrometer CMOS,” in IEEE Journal of Solid State Circuits,\nOct. 1998.\n[19]\nE. M. Sentovich et al., “SIS: A System for Sequential Circuit\nSynthesis,” Technical Report UCB/ERL M92/41, Electronics\nResearch Lab, Univ. of California, Berkeley, May 1992.\nProceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’05) \n1530-1591/05 $ 20.00 IEEE"}],"pages":[{"page":1,"text":"Abstract - The problem of determining lower bounds for the\nenergy cost of a given nanoscale design is addressed via a\ncomplexity theory-based approach. This paper provides a\ntheoretical framework that is able to assess the trade-offs\nexisting in nanoscale designs between the amount of\nredundancy needed for a given level of resilience to errors and\nthe associated energy cost. Circuit size, logic depth and error\nresilience are analyzed and brought together in a theoretical\nframework that can be seamlessly integrated with automated\nsynthesis tools and can guide the design process of nanoscale\nsystems comprised of failure prone devices. The impact of\nredundancy addition on the switching energy and its\nrelationship with leakage energy is modeled in detail. Results\nshow that 99% error resilience is possible for fault-tolerant\ndesigns, but at the expense of at least 40% more energy if\nindividual gates fail independently with probability of 1%. \n1. Introduction \nNanoscale computing for either CMOS or non-CMOS\ntechnology is widely agreed to be characterized by non-\ndeterministic and unreliable behavior. In the case of nanometer\nCMOS designs, uncertainties stem from process and system\nparameter variability and their impact on performance and\nbehavior of switching devices, as well as from increased\nsusceptibility to soft errors which may thus create incorrect or\nfaulty functionality. For non-CMOS nanoscale electronics (such\nas molecular or self-assembly), uncertainties in operation\noriginate in the inherent non-deterministic switching behavior\nof such devices. While fault-tolerant computing is a mature area\nof research, automatically designing reliable systems out of\nunreliable components may prove to be a challenging task. As a\nnatural solution to the fault-tolerance problem, the use of\nredundancy has been proposed and analyzed theoretically as\nearly as five decades ago in the seminal work of von Neumann\n[1] and more recently by others [2,3,4,5,6,7]. While a practical\nsolution to synthesizing in an automated manner nanoscale\ndesigns that are inherently fault-tolerant has yet to be found,\nnonetheless such theoretical results offer a good insight into the\nachievable limits of error-resilience and required minimum\nredundancy (or extra logic) needed. Furthermore, in the case of\nCMOS nanoscale technology, power density and energy cost\nhave become the main design bottlenecks [8]. Adding\nredundancy in the hope of increasing error-resilience has the\nnegative effect of eventually decreasing the energy efficiency of\na given design. Thus, given the clear trade-off between\nachieving resilience via redundancy addition and energy\nefficiency, tools that can aid and guide the design process in a\nnanoscale design methodology become mandatory. \nThis paper is a step in this direction, by proposing theoretic\nlower bounds and trade-offs between energy efficiency and\nredundancy needed for achieving a certain error-resilience level.\nSuch bounds and theoretical trade-offs provide valuable insights\nearly in the design process and may aid and guide the automatic\nsynthesis process of nanoscale systems.\nWhile the fault-\ntolerance aspects described in this paper are relevant for any\ntype of nanoscale designs based on emerging technologies that\ninherently include non-determinism in normal operation, we\nwill restrict ourselves to considering as a driver application\ncomputing systems that use electrons and energy barriers to\nrepresent or manipulate their states [9]. CMOS nanoscale\ndesigns are one such example. Based on first principle physics\nlaws, it has been shown recently [9] that power density of such\ndesigns will reach in the next decade values close to 100 Watts/\ncm2. \nThese \npower \ndensities, \ncoupled \nwith \nincreased\ncomplexities and integration densities, put a lot more pressure\non achieving more efficient designs in the nanoscale era. To\naddress this problem, we consider the case of fault-tolerant\nnanoscale systems which need to rely on added redundancy to\nbe able to cope with increased error rates. To characterize the\navailable trade-offs between the required redundancy and the\nassociated energy cost, we propose the use of a complexity\ntheory-based framework. \n2. Related Work and Paper Contribution\nThis paper addresses the impact of error-resilience and\nredundancy in a theoretical framework that can guide the design\nprocess for nanoscale systems. Our framework is able to\nprovide bounds on the energy cost associated with achieving a\ngiven error-resilience level for a design based on error-prone\ngates (characterized by non-deterministic behavior), while also\ndetailing when these bounds are likely to be tight. As opposed\nto the theoretical bounds developed by von Neumann and his\nsuccessors [1,2,3,4,5,6], our approach does not assume any\nparticular use of redundancy, such as majority voting or parallel\nrestitution [1]. Instead, it is based on a framework relying on\ninformation theory concepts [7] to quantify the energy\nefficiency of nanoscale designs in the presence of errors. \nWhile the problem of analyzing the fault-tolerance of\nnanoscale designs under given gate or wire error models has\nbeen recently started to gain interest [10], no such study has\nlinked the error-resilience of a circuit to its energy efficiency.\nRecent work [11] has shown, using information theoretic\narguments, that it is possible to trade-off energy efficiency and\nfault-tolerance through the use of voltage scaling. Indeed, by\nEnergy Bounds for Fault-Tolerant Nanoscale Designs\nDiana Marculescu\nDept. of Electrical and Computer Engineering\nCarnegie Mellon University\nPittsburgh, PA 15213\nProceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’05) \n1530-1591/05 $ 20.00 IEEE"},{"page":2,"text":"allowing the voltage to be reduced, power cost is reduced\nsignificantly, while noise level is increased, thereby allowing\nfor trading-off energy and error-resilience. However, our goal is\ndifferent. We propose to quantify how added redundancy\nnecessary for achieving reliable operation out of unreliable\ncomponents impacts overall energy efficiency of a nanoscale\ndesign. In addition, our approach is not bound to any particular\ntype of redundancy (based on techniques such as majority\nvoting or parallel restitution) and assumes that “noisy” gates\nand can be modeled as error-free devices cascaded with a\nsymmetric communication channel modeling the error. In\naddition, while previous work [11] has linked energy efficiency\nand fault-tolerance in an information theoretic environment, it\ntargets voltage scaling-reliability trade-offs and does not\naddress entities that are more complex than a single gate or\ndevice. Our theoretical framework is able to completely\ncharacterize complex designs in terms of the energy-error-\nresilience trade-offs, while also providing insights into the\nrelative contributions of static and switching energy. \n3. Preliminaries\nWithout loss of generality, we restrict ourselves to nanoscale\nsystems with the following characteristics:\n•\nCircuits are assumed comprised of devices or gates that can\nbe either error-free, or failure prone.1\n•\nWe consider the case of error-free and failure-prone circuits\nin which internal gates can fail independently with a\nprobability \n.2 We assume that any interconnect\nerror \nprobabilities \nare \nlumped \ninto \ndevice \nerror\nprobabilities.\n•\nWe also consider device (gate) output error probabilities\nmodeled as symmetric communication channels with an ε\nerror probability. As shown in Figure 1, each failure-prone\ndevice is assumed modeled as an error-free device\ncascaded with a symmetric communication channel.\n•\nFor the case of failure-prone circuits, we consider the case\nof \n-reliable computation, that is, with probability of\n1-δ, the output of the circuit is correct. \n•\nWhile not restricting ourselves to any particular technology\ncharacterized by failure-prone operation, we consider the\ncase of systems that use electrons and energy barriers to\nrepresent or manipulate their states. Examples include\nnanoscale CMOS applications or systems comprised of\nirreversible logic switch devices. \n•\nGiven this constraint, we are mostly concerned with\nswitching energy or the energy lost due to information\nprocessing or transfer. \nTo this end, we consider the impact that any additional\nredundancy added to increase error resilience has on the overall\nenergy efficiency of a nanoscale design. Assuming that most of\nthe switching energy is consumed during output charging and\ndischarging (\n, where E is the total energy\nconsumed during a certain time interval, Vdd is the supply\nvoltage, C is the load capacitance and sw is the total switching\nactivity during the considered interval), fault-tolerant circuits\nrelying on added redundancy for increased error resilience can\nhave both their load capacitance and switching activity affected.\nIn addition, added redundancy may also impact logic depth, and\nthus overall latency. To this end, trade-offs between energy,\ndelay or composite metrics (such as energy-delay product) on\none hand, and required output error resilience δ, on the other\nhand, can be uncovered and analyzed in an analytical manner.\n4. Bounds on Switching Energy Metrics\nIntuitively, added logic redundancy, not necessarily committed\nto any particular implementation (e.g., majority based voting\nused in triple or n-tuple modular redundancy vs. parallel\nrestitution [1]) is expected to increase the error resilience of a\nfailure-prone nanoscale design by providing multiple logical\npaths from the inputs to the outputs, thus decreasing the impact\nof the “noise” on the overall input-output communication\nchannel. One may expect that the added redundant logic (when\nerror-free) will perform in a similar manner as far as switching\nactivity is concerned. However, we note that a non-zero error\nprobability on the output of each device (be it part of the\noriginal circuit, or part of the redundant logic) can affect the\nswitching behavior of that gate output, as shown next.\n4.1. Impact on Switching Activity\nIn what follows, we denote by p(x) the probability of a binary\nrandom variable x being one and by sw(x) the probability that x\nchanges state. We also denote by x an array of binary variables,\nand by f a multiple output Boolean function.\nThe following result quantifies the change in the switching\nactivity that a given “noise” level produces on the output of a\nswitching device:\nTheorem 1. If y, z are the error-free and error-prone outputs of a\ndevice which fails with a probability of as in Figure 1, then:\n.\nHint for proof:3 Uses switching activity definition for temporal\n1. Devices and gates are assumed to denote the same entity in this paper.\n2. As it will be seen in the sequel, if error probabilities are close to 1/2, reliable\ncomputation is not possible unless an unbounded overhead is considered. \n0\nε\n1 2\n⁄\n≤\n≤\nError-free\n device\nError\nmodel\nx\ny\nz\n0 0\n1 1\nε\n1\nε\n–\n1\nε\n–\ny\nz\nε\nFigure 1. Modeling error-prone devices using error-free devices and a symmetric communication channel error model ε. The error-\nfree device is a gate with a single or multiple bit input x and a single bit output y.\n1\nδ\n–\n(\n)\n3. Due to space limits, if not provided, all proofs can be found in [12].\nE\n1\n2--CVdd\n2 sw\n=\nε\nsw z( )\n1\n2ε\n–\n(\n)2sw y\n( )\n2ε 1\nε\n–\n(\n)\n+\n=\nProceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’05) \n1530-1591/05 $ 20.00 IEEE"},{"page":3,"text":"independent signals: \n. \n \nIt is interesting to note that failure-prone designs do not\nnecessarily experience a monotonic trend as far as switching\nactivity is concerned. As seen in Figure 2, while for smaller\nvalues of the error probability ε, the switching activity is less\naffected, for larger values (closer to 0.5) the switching activity\nbecomes closer to 0.5, thus making gates with smaller switching\nactivity more active and vice versa. In other words, increased\nerror rates make the output of a failure-prone device look more\nrandom and less likely to carry any useful information. \n4.2. Impact on Circuit Size\nAs shown in Theorem 1, any non-zero probability of error for a\nfailure-prone device affects its average switching activity. In\naddition, added redundancy does not come for free: it affects\nboth logic depth, as well as circuit size, which in turn affect\nperformance and energy cost of the entire system. \nIn this section, we quantify the impact of added logic\nredundancy on circuit size, for a given error probability per gate\nε, and a required maximum error probability on the output δ.\nThe following result provides the tightest bounds known for the\nminimum circuit size required for computing a Boolean\nfunction with a given output fault-tolerance:\nTheorem 2. [13] For \n and \n, if a Boolean\nfunction is \n-reliably computed by a circuit with ε-noisy,\nk-input gates, then the additional redundancy in the circuit is at\nleast:1\nwhere s is the sensitivity of Boolean function f (or the maximum\nnumber of inputs that, if changed individually, produce a change\non the output), \n, and \n.\nThe theorem confirms previous results [14,15] that show an\n proportionality relation for the error-prone circuit size,\nbut points to a superlinear increase in complexity with increased\nvalues of ε. Indeed, for ε values close to 0.5, circuit size\napproaches infinity, thus making \n-reliable computation\nimpossible for all practical purposes. On the other hand, it has\nbeen shown [2,3,5] that an upper bound on the size of a fault-\ntolerant circuit is \n (S0 is the size of the error-free\nimplementation). For both the upper and lower bounds, equality\nis achieved for parity functions, implemented using decision\ntrees or Shannon-like circuits. While the result above holds for\nsingle output circuits (Boolean functions), we extend it to\ngeneral circuits below:\nCorollary 1. For \n and \n, if an m-output\nfunction of n inputs \n is \n-reliably\ncomputed by a circuit with ε-noisy, k-input gates, then the\nadditional redundancy in the circuit is at least:\nwhere s is the sensitivity of the multiple output function f , and\n are as in Theorem 2.\nHint for proof: The characteristic function for f is a single\noutput function with the same sensitivity. \nTo understand the impact of increased gate count due to\nadded redundancy, we show in Figure 3 the lower bound from\nTheorem 2 and Corollary 1 as a function of device error ε to\n-reliably compute a 10-input parity function with\nsensitivity s = 10, error-free size S0 = 21, and δ = 0.01. We note\nthat more than an order of magnitude redundancy factor is\nneeded for error levels close to 0.5. It is thus expected that the\nincreased size will also impact the total load capacitance and\nenergy cost of the implementation.\n4.3. Impact on Switching Energy\nThe impact of using redundancy on the energy of fault-tolerant\nnanoscale designs can be quantified through: 1) the change in\nthe average switching activity for a generic internal gate; and 2)\nthe change in the required number of devices needed to achieve\na certain output reliability. Since we assume that, if considered\nerror-free, redundant logic behaves almost the same as the\noriginal circuit in terms of switching activity, one can infer that\nTheorem 1 holds for the average switching activity of the error-\nfree and error-prone circuits implementing the same function.\nIn addition, Corollary 1 can be used to quantify the increase\nin \nthe \ntotal \nload \ncapacitance \nof \nthe \nfault-tolerant\n1. In this paper, log is assumed base two, unless noted otherwise.\nsw z( )\n2p z( ) 1\np z( )\n–\n(\n)\n=\nFigure 2. Switching activity of error-prone devices as a function\nof the switching activity of error-free devices.\nε increases\n0\nε\n<\n1 2\n⁄\n≤\n0\nδ\n≤\n1 2\n⁄\n<\n1\nδ\n–\n(\n)\ns\ns\n2s\n2 1\n2δ\n–\n(\n)\n(\n)\nlog\n⋅\n+\nlog\n⋅\nk\nt\nlog\n⋅\n----------------------------------------------------------------------\nt\nω3\n1\nω\n–\n(\n)3\n+\nω 1\nω\n–\n(\n)\n--------------------------------\n=\nω\n1\n1\n2ε\n–\nk\n–\n2\n---------------------------\n=\ns\ns\nlog\n⋅\n1\nδ\n–\n(\n)\nO S0\nS0\nlog\n⋅\n(\n)\n0\nε\n<\n1 2\n⁄\n≤\n0\nδ\n≤\n1 2\n⁄\n<\nf : 0 1\n,\n{\n}n\n0 1\n,\n{\n}m\n→\n1\nδ\n–\n(\n)\ns\ns\n2s\n2 1\n2δ\n–\n(\n)\n(\n)\nlog\n⋅\n+\nlog\n⋅\nk\nt\nlog\n⋅\n----------------------------------------------------------------------\nt ω\n,\n1\nδ\n–\n(\n)\nFigure 3. Minimum redundancy needed as a function of the device\nerror ε, for s = 10, S0 = 21, and δ = 0.01 assuming 2-, 3-, and 4-\ninput gate implementations.\nProceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’05) \n1530-1591/05 $ 20.00 IEEE"},{"page":4,"text":"implementation: most high-level energy estimation frameworks\nhave shown that total load capacitance is, with sufficient\naccuracy, proportional to the total device count [16,17]. Thus,\none can conclude that the increase factor in energy for a fault-\ntolerant implementation satisfies the following:\nCorollary 2. Consider \n. The energy Eε,δ\nof a circuit composed of ε-noisy, k-input gates, that \n-\nreliably computes f satisfies:\nwhere E0 is the energy cost of the error-free implementation, s is\nthe sensitivity of f , sw0 (\n) is the average switching\nactivity per gate of the error-free implementation, S0 is the size\nof the error-free circuit implementing f , and \n are as in\nTheorem 2.\nHint for proof: Uses Theorems 1-2 for energy estimation,\nassuming load capacitance is proportional to the total device\ncount [16][17].\n5. Case Study: Nanoscale CMOS Designs\nThe results presented in Section 4 hold true for the switching\nenergy of any nanoscale computing system that relies on\nirreversible switching devices that use electrons and energy\nbarriers to represent or manipulate their states. However, it is\nworth noting that, in the particular case of nanoscale CMOS\ndesigns (i.e., 0.09um and beyond) leakage power becomes the\ndominant component of the overall power, and thus increased\nredundancy implies increased number of idle devices or more\nleakage power. In addition, added logic redundancy comes at\nthe expense of increased logic depth, which affects negatively\ncircuit latency and overall performance. We address in the\nsequel some of these issues and the available trade-offs between\nswitching energy bounds and leakage cost or performance.\n5.1. Impact on Leakage Power\nWhile the direct impact of logic redundancy on static power is\nclear through the increased number of potentially idle devices,\nthere is a more subtle effect on leakage energy, due to changes\nin average switching activity per gate. More precisely, with\nprobability \n a generic gate in the error-prone circuit\nis idle and subject to leakage energy, not switching energy.\nThus, any change in the average switching activity triggers a\nchange in the overall contribution of leakage energy to overall\ncircuit energy. The next result details this change:\nTheorem 3. If \n is the ratio of leakage energy to switching\nenergy in a circuit composed of ε-noisy gates, then:\nwhere \n is the ratio of leakage energy to switching energy\nin the error-free case and sw0 (\n) is the average\nswitching activity per gate of the error-free implementation.\nHint for proof: Since switching energy \n and\nstatic energy \n (S0 is the size of the\ncircuit, Vdd the supply voltage, and K is a factor that depends on\ntechnology and threshold voltage), we can use Theorems 1-2 to\ndetermine switching/static energy in the error-prone case.\nTo understand how the relative contribution to the overall\nenergy cost changes, we show in Figure 4 the variation of the\nnormalized ratio for the error-prone circuit, with respect to the\nerror-free implementation for various switching activity values\nand error probabilities. As it can be noticed, the relative\ncontribution of leakage energy decreases with increased error\nrates if the switching activity sw0 is less than 0.5. Indeed, in this\ncase, switching activity in the error-prone implementation\nincreases and thus devices are less likely to be idle. The\nopposite is true if the switching activity of the error-free circuit\nexceeds 0.5. The relative contribution stays the same if sw0 is\nexactly 0.5. \n5.2. Impact on Performance, Average Power and \nEnergy-Delay Product\nAdded redundancy is expected to have a significant effect on\nthe circuit depth as well, and thus on overall latency. Indeed, the\nfollowing result has been shown for circuit depth of fault-\ntolerant circuits:\nTheorem 4. [7] Consider \n. The logic\ndepth dε,δ of a circuit composed of ε-noisy, k-input gates, that\n-reliably computes f satisfies:\n•\nIf \n, then \n.\n•\nIf \n, then \n.\nwhere \n with \n1 and ∆ is defined as\nf : 0 1\n,\n{\n}n\n0 1\n,\n{\n}m\n→\n1\nδ\n–\n(\n)\nEε δ\n,\nE0\n---------\n1\ns\n2\n2 1\n2δ\n–\n(\n)\n(\n)\nlog\n⋅\n+\nlog\n(\n)\nk\nt\nlog\n⋅\n-----------------------------------------------------------------\ns\nS0\n----\n⋅\n+\n1\n2ε\n–\n(\n)2\n2ε 1\nε\n–\n(\n)\nsw0\n----------------------\n+\n⋅\n≥\n0\nsw0\n1\n≤\n<\nt ω\n,\n1\nswε δ\n,\n–\n(\n)\nWL ε δ\n, ,\nWL ε δ\n, ,\nWL 0\n,\n----------------\n1\n2ε\n–\n(\n)2\n2ε 1\nε\n–\n(\n)\n1\nsw0\n–\n(\n)\n⁄\n+\n1\n2ε\n–\n(\n)2\n2ε 1\nε\n–\n(\n) sw0\n⁄\n+\n------------------------------------------------------------------------------\n=\nWL 0\n,\n0\nsw0\n1\n<\n<\n1. As shown in Section 4, only error levels that are less than 0.5 are of practical\ninterest, thus the error probability is modeled as \n.\nE0\nS0Vdd\n2 sw0\n∝\nEL 0\n,\n1\nsw0\n–\n(\n) S0 V\n⋅\ndd K\n⋅\n⋅\n∝\nFigure 4. Normalized ratio between leakage energy and switching\nenergy (\n) as a function of device error probability ε. The\nbaseline is the ratio for the error-free implementation (\n).\nNote the logarithmic scale on the Y-axis.\nWL ε δ\n, ,\nWL 0\n,\nf : 0 1\n,\n{\n}n\n0 1\n,\n{\n}m\n→\n1\nδ\n–\n(\n)\nξ2\n1 k\n⁄\n>\ndε δ\n,\nn∆\n(\n)\nlog\nkξ2\n(\n)\nlog\n⁄\n≥\nξ2\n1 k\n⁄\n≤\nn\n1 ∆\n⁄\n≤\nε\n1\nξ\n–\n(\n) 2\n⁄\n=\n0\nξ\n<\n1\n≤\n1\nξ\n–\n(\n) 2\n⁄\nProceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’05) \n1530-1591/05 $ 20.00 IEEE"},{"page":5,"text":".\nIn other words, to achieve a given error resilience\n(characterized by δ), for sufficiently low error probabilities per\ngate, the minimum logic depth is inversely proportional to\n; otherwise, no circuit \n-reliably computes f ,\nunless the number of inputs is less than 1/∆. In the latter case, no\nknown bounds are available for the size of the fault-tolerant\nimplementation. \nAnalyzing these results, we note that, trade-offs between the\nfault-tolerance and performance, on one hand, and the average\npower consumption, or energyxdelay product, on the other\nhand, can be deduced. Assuming that the latency of the failure-\nprone circuit varies as \n [18] (where VT\nis the threshold voltage and α is a technology dependent factor),\nif the same energy budget as the error-free circuit is targeted, the\nfault-tolerant implementation will need to rely on a lower Vdd to\ncompensate for the change in switched capacitance, which in\nturn further increases overall latency. Similar conclusions can\nbe drawn if performance constraints need to be maintained\ninstead: in this case, Vdd must be increased to compensate for\nthe logic depth increase, thus triggering an energy increase. As\nshown in Figure 5, the lower bound for normalized\nenergyxdelay product is higher than the one for normalized\nlatency, for the same error level. This comes at no surprise,\ngiven the fact that both energy and delay increase for the fault-\ntolerant circuit implementation. However, the same cannot be\nsaid about the average power (or energy spent per unit time). \nFigure 6 shows the dependency of the normalized average\npower on the device error probability and internal gates fanin.\nAs it can be seen, for low error rates, the average power of the\nfault-tolerant implementation is larger than the one of the error-\nfree circuit: in this case, delay increases at a lower rate than\ncircuit size, and thus energy. Furthermore, a larger fanin reduces\nthe overhead in average power. For larger error rates, however,\nthe logic depth (and thus delay) increases at much higher rates\nthan circuit size, thus making error-resilient implementations\nmore power efficient, at the expense of significantly larger\ndelays. In this case, larger fanins introduce a smaller power\nreduction as the difference in the increase rate for circuit depth\nand circuit size tapers off. \n6. Results\nAlthough the theoretical results presented in previous sections\nare applicable on average to generic circuits, it is worthwhile to\ninvestigate how do these lower bounds apply for specific\nbenchmarks. Even though all lower bounds presented are tight\nfor a certain family of Boolean functions (mainly, parity\nfunctions implemented using decision-trees or based on a\nShannon-like organization), when applied to specific circuits,\nthese bounds still offer an idea about the possible trends that\nswitching (and static) energy may have for fault-tolerant\nnanoscale designs. \nTo this end, we consider a subset of ISCAS’85 benchmarks\nand some computer arithmetic circuits (ripple-carry adders and\narray multipliers) with various bitwidths. The ISCAS’85\nbenchmarks have been optimized in the SIS [19] environment\nusing script.rugged. All benchmarks have been mapped using a\ngeneric library comprised of gates with a maximum fanin of\nthree. The average switching activity of a generic gate part of\neach benchmark has been obtained considering randomly\ngenerated inputs. For the error-free implementation we have\nassumed that 50% of the total energy is leakage (which is inline\nwith predictions for technologies smaller than 0.09um [8]).\nWe show in Figure 7 the lower bounds for the energy and\ndelay of the fault-tolerant implementation, normalized with\nrespect to the error-free implementation. In each case, we\nconsider three scenarios corresponding to gates independently\nfailing with probability ε = {0.001, 0.01, 0.1}, and required\nmaximum probability on the output δ = 0.01. As it can be seen,\nthe lower bounds increase significantly with higher error rates,\nnecessitating in some cases at least 40% more energy if error\n∆\n1\nδ\nδ\nlog\n1\nδ\n–\n(\n)\n1\nδ\n–\n(\n)\nlog\n+\n+\n=\nkξ2\n(\n)\nlog\n1\nδ\n–\n(\n)\nDε δ\n,\ndε δ\n,\nVdd\nVdd\nVT\n–\n(\n)α\n----------------------------\n⋅\n∝\nFigure 5. Normalized delay (energyxdelay) as a function of ε. The\nbaseline is the delay (energyxdelay) for the error-free\nimplementation. The contributions of the switching and leakage\nenergy are assumed equal and switching activity is considered 0.5\nin the baseline. All other parameters are as in Figure 3. Note the\nlogarithmic scale on the Y-axis.\nFigure 6. Normalized average power as a function of device error\nprobability ε. The baseline is the average power for the error-free\nimplementation. The contributions of the switching and leakage\nenergy are assumed equal and the switching activity is considered\n0.5 in the baseline. All other parameters are as in Figure 3. \nProceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’05) \n1530-1591/05 $ 20.00 IEEE"},{"page":6,"text":"rates are 1% per gate. We note that, while energy bounds are\nmore circuit dependent (due to Boolean sensitivity s and\nswitching activity sw0), delay is less so, as the only circuit\nspecific information it relies on is the average fanin k. Figure 8\nshows the trend for the average power and energyxdelay lower\nbounds, \nnormalized \nwith \nrespect \nto \nthe \nerror-free\nimplementation. While energyxdelay lower bound experiences\nup to a 2.8X increase, average power is reduced due to the\nsignificant increase in logic depth (and latency). \n7. Conclusion\nThis paper has introduced the use of complexity theory concepts\nfor determining lower bounds on energy and related metrics for\nnanoscale, fault-tolerant designs. The theoretical results\npresented herein can be used to guide the automatic synthesis of\nerror-prone nanoscale designs, while also uncovering the\ninterplay between switching and static energy for these systems.\nFuture work includes the treatment of sequential circuits and the\nrefinement of the lower bounds depending on the circuit\nfunctionality.\n8. References\nFigure 7. Lower bounds for energy and delay for ε = {0.001, 0.01,\n0.1} and δ = 0.01, normalized with respect to the error-free\nimplementation. The contributions of switching and leakage\nenergy are assumed equal in the error-free baseline. \nFigure 8. Lower bounds for average power and energyxdelay for ε\n= {0.001, 0.01, 0.1} and δ = 0.01, normalized with respect to the\nerror-free implementation. The contributions of switching and\nleakage energy are assumed equal in the error-free baseline. \n[1]\nJ. von Neumann, J., “Probabilistic Logics and the Synthesis of\nReliable Organisms from Unreliable Components,” pp. 43-98 in\nAutomata Studies, C. E. Shannon, J. McCarthy, eds., Princeton Univ.\nPress, Princeton, N.J. (1956); Also in Collected Works, vol. 5:329-\n378.\n[2]\nN. Pippenger, “Reliable computation by formulas in the presence of\nnoise,” in IEEE Transactions on Information Theory, vol. 34, no. 2,\npp. 194-197, February 1988.\n[3]\nN. Pippenger, G.D. Stamoulis, and J.N. Tsitsiklis, “On a lower bound\nfor the redundancy of reliable networks with noisy gates,” in IEEE\nTransactions on Information Theory, vol. 37, no. 3, pp. 639-643,\nMarch 1991.\n[4]\nD. Kleitman, T. Leighton, and Y. Ma, “On the design of reliable\nBoolean circuits that contain partially unreliable gates,” in 35th\nIEEE Annual Symposium on Foundations of Computer Science, pp.\n332-346, Santa Fe, New Mexico, November 1994.\n[5]\nP. G'acs and A. G'al, “Lower bounds for the complexity of reliable\nBoolean circuits with noisy gates,” in IEEE Transactions on\nInformation Theory, vol. 40, no. 2, pp. 579-583, March 1994.\n[6]\nW. Evans and N. Pippenger, “On the maximum tolerable noise for\nreliable computation by formulas,” in IEEE Transactions on\nInformation Theory, vol. 44, no. 3, pp. 1299-1305, May 1998. \n[7]\nW. Evans and L. J. Schulman, “Signal propagation and noisy\ncircuits,” in IEEE Transactions on Information Theory, vol. 45, no.\n7, pp. 2367-2373, November 1999. \n[8]\nInternational Technology Roadmap for Semiconductors (http://\npublic.itrs.net), 2003.\n[9]\nV. V. Zhirnov, R. K. Cavin, J. A. Hutchby, G. I. Bourianoff, “Limits to\nBinary Logic Switch Scaling - A Gedanken Model,” in Proc. of the\nIEEE, Special Issue on Nanoelectronics and Nanoscale Processing,\nvol. 91, no. 11, pp. 1934-1939, November 2003.\n[10]\nR. I. Bahar, J. Mundy, and J. Chen, “A Probabilistic-Based Design\nMethodology for Nanoscale Computation,” in Proc. IEEE/ACM Intl.\nConf. on Computer-Aided Design, San Jose, CA, Nov. 2003.\n[11]\nR. Hegde and N. R. Shanbhag, “Towards achieving energy-\nefficiency in presence of deep submicron noise,” in IEEE\nTransactions on VLSI Systems, vol. 8, no. 4, pp. 379-391, Aug. 2000. \n[12]\nD. Marculescu, “Fault-Tolerant Nanoscale Design: An Energy\nPerspective,” Technical Report CSSI 04-33, Sept. 2004 (http://\nwww.ece.cmu.edu/~dianam/conferences). \n[13]\nW. Evans, “Information Theory and Noisy Computation,” PhD\nthesis, University of California at Berkeley, 1994 (UC Berkeley\nTechnical Report 94-057). \n[14]\nA. G’al, “Combinatorial Methods in Boolean Function Complexity,”\nPh.D.-thesis, University of Chicago, 1995.\n[15]\nR. Reischuk, B. Schmeltz, “Reliable Computation with Noisy\nCircuits and Decision Trees, A General nlogn Lower Bound,” in\nProc. IEEE Conference on Foundations of Computer Science, pp.\n602-611, San Juan, Puerto Rico, 1991.\n[16]\nM. Nemani and F. N. Najm, “Towards a high-level power estimation\ncapability,” in IEEE Transactions on Computer-Aided Design, vol.\n15, no. 6, pp. 588-598, June 1996.\n[17]\nD. Marculescu, R. Marculescu, and M. Pedram, “Information-\nTheoretic Measures for Power Analysis,” in IEEE Transactions on\nComputer-Aided Design of Circuits and Systems, vol. 15, no. 6, pp.\n599-610, June 1996.\n[18]\nK. Chen and C. Hu, “Performance and Vdd Scaling in Deep\nSubmicrometer CMOS,” in IEEE Journal of Solid State Circuits,\nOct. 1998.\n[19]\nE. M. Sentovich et al., “SIS: A System for Sequential Circuit\nSynthesis,” Technical Report UCB/ERL M92/41, Electronics\nResearch Lab, Univ. of California, Berkeley, May 1992.\nProceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’05) \n1530-1591/05 $ 20.00 IEEE"}]},"section_tree":[],"assets":{"figures":[],"tables":[],"images":[]},"math_expressions":{"inline":[],"block":[{"equation_id":"eq1","equation_number":null,"raw_text":"sensitivity s = 10, error-free size S0 = 21, and δ = 0.01. We note","raw_latex":null,"normalized_latex":null,"display_type":"block_candidate"},{"equation_id":"eq2","equation_number":null,"raw_text":"error ε, for s = 10, S0 = 21, and δ = 0.01 assuming 2-, 3-, and 4-","raw_latex":null,"normalized_latex":null,"display_type":"block_candidate"},{"equation_id":"eq3","equation_number":null,"raw_text":"failing with probability ε = {0.001, 0.01, 0.1}, and required","raw_latex":null,"normalized_latex":null,"display_type":"block_candidate"},{"equation_id":"eq4","equation_number":null,"raw_text":"maximum probability on the output δ = 0.01. As it can be seen,","raw_latex":null,"normalized_latex":null,"display_type":"block_candidate"},{"equation_id":"eq5","equation_number":null,"raw_text":"Figure 7. Lower bounds for energy and delay for ε = {0.001, 0.01,","raw_latex":null,"normalized_latex":null,"display_type":"block_candidate"},{"equation_id":"eq6","equation_number":null,"raw_text":"0.1} and δ = 0.01, normalized with respect to the error-free","raw_latex":null,"normalized_latex":null,"display_type":"block_candidate"},{"equation_id":"eq7","equation_number":null,"raw_text":"= {0.001, 0.01, 0.1} and δ = 0.01, normalized with respect to the","raw_latex":null,"normalized_latex":null,"display_type":"block_candidate"}],"equation_refs":[]},"symbol_table":[],"references":{"in_text_markers":[],"bibliography":[]},"claims":[],"flow_graph":{"nodes":[],"edges":[]},"quality":{"text_char_count":31774,"parse_confidence":0.5,"equation_parse_rate_proxy":0.35,"citation_resolution_rate_proxy":0.0,"structure_coverage_proxy":0.0,"asset_coverage_proxy":0.0,"accepted_for_training":true}} |