code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module td_fused_top_fifo_w6_d2_S_x (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
in... | 6.827284 |
module td_fused_top_fifo_w6_d2_S_x_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr... | 6.827284 |
module td_fused_top_fifo_w6_d2_S_x0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
i... | 6.827284 |
module td_fused_top_fifo_w6_d2_S_x0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] s... | 6.827284 |
module td_fused_top_fifo_w6_d2_S_x0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] s... | 6.827284 |
module td_fused_top_fifo_w6_d2_S_x_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr... | 6.827284 |
module td_fused_top_fifo_w6_d6_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd6;
input clk;
input r... | 6.827284 |
module td_fused_top_fifo_w6_d6_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd6;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
//reg[DATA_WIDTH-1:0] SRL... | 6.827284 |
module td_fused_top_fifo_w6_d6_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd6;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
//reg[DATA_WIDTH-1:0] SRL... | 6.827284 |
module td_fused_top_fifo_w6_d7_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
inpu... | 6.827284 |
module td_fused_top_fifo_w6_d7_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_fifo_w6_d7_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_fifo_w6_d7_S_x (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
in... | 6.827284 |
module td_fused_top_fifo_w6_d7_S_x_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr... | 6.827284 |
module td_fused_top_fifo_w6_d7_S_x_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr... | 6.827284 |
module td_fused_top_fifo_w6_d8_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
inpu... | 6.827284 |
module td_fused_top_fifo_w6_d8_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_fifo_w6_d8_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_fifo_w6_d8_S_x (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
in... | 6.827284 |
module td_fused_top_fifo_w6_d8_S_x_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr... | 6.827284 |
module td_fused_top_fifo_w6_d8_S_x_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr... | 6.827284 |
module td_fused_top_fifo_w6_d9_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 5'd9;
input clk;
inpu... | 6.827284 |
module td_fused_top_fifo_w6_d9_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 5'd9;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_fifo_w6_d9_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 5'd9;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_fifo_w7_d10_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd7;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 5'd10;
input clk;
in... | 6.827284 |
module td_fused_top_fifo_w7_d10_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd7;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 5'd10;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr... | 6.827284 |
module td_fused_top_fifo_w7_d10_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd7;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 5'd10;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr... | 6.827284 |
module td_fused_top_fifo_w7_d2_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd7;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
inpu... | 6.827284 |
module td_fused_top_fifo_w7_d2_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd7;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_fifo_w7_d2_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd7;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_fifo_w7_d2_S_x (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd7;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
in... | 6.827284 |
module td_fused_top_fifo_w7_d2_S_x_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd7;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr... | 6.827284 |
module td_fused_top_fifo_w7_d2_S_x0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd7;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
i... | 6.827284 |
module td_fused_top_fifo_w7_d2_S_x0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd7;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] s... | 6.827284 |
module td_fused_top_fifo_w7_d2_S_x0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd7;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] s... | 6.827284 |
module td_fused_top_fifo_w7_d2_S_x_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd7;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr... | 6.827284 |
module td_fused_top_fifo_w7_d7_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd7;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
inpu... | 6.827284 |
module td_fused_top_fifo_w7_d7_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd7;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_fifo_w7_d7_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd7;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_fifo_w7_d8_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd7;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
inpu... | 6.827284 |
module td_fused_top_fifo_w7_d8_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd7;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_fifo_w7_d8_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd7;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_fifo_w7_d8_S_x (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd7;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
in... | 6.827284 |
module td_fused_top_fifo_w7_d8_S_x_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd7;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr... | 6.827284 |
module td_fused_top_fifo_w7_d8_S_x0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd7;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
i... | 6.827284 |
module td_fused_top_fifo_w7_d8_S_x0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd7;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] s... | 6.827284 |
module td_fused_top_fifo_w7_d8_S_x0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd7;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] s... | 6.827284 |
module td_fused_top_fifo_w7_d8_S_x_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd7;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr... | 6.827284 |
module td_fused_top_fifo_w7_d9_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd7;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 5'd9;
input clk;
inpu... | 6.827284 |
module td_fused_top_fifo_w7_d9_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd7;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 5'd9;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_fifo_w7_d9_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd7;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 5'd9;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_fifo_w8_d10_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 5'd10;
input clk;
in... | 6.827284 |
module td_fused_top_fifo_w8_d10_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 5'd10;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr... | 6.827284 |
module td_fused_top_fifo_w8_d10_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 5'd10;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr... | 6.827284 |
module td_fused_top_fifo_w8_d10_S_x (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 5'd10;
input clk;
... | 6.827284 |
module td_fused_top_fifo_w8_d10_S_x_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 5'd10;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] ... | 6.827284 |
module td_fused_top_fifo_w8_d10_S_x_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 5'd10;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] ... | 6.827284 |
module td_fused_top_fifo_w8_d2_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
inpu... | 6.827284 |
module td_fused_top_fifo_w8_d2_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_fifo_w8_d2_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_fifo_w8_d2_S_x (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
in... | 6.827284 |
module td_fused_top_fifo_w8_d2_S_x_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr... | 6.827284 |
module td_fused_top_fifo_w8_d2_S_x_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr... | 6.827284 |
module td_fused_top_fifo_w8_d7_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
inpu... | 6.827284 |
module td_fused_top_fifo_w8_d7_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_fifo_w8_d7_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_fifo_w8_d7_S_x (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
in... | 6.827284 |
module td_fused_top_fifo_w8_d7_S_x_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr... | 6.827284 |
module td_fused_top_fifo_w8_d7_S_x0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
i... | 6.827284 |
module td_fused_top_fifo_w8_d7_S_x0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] s... | 6.827284 |
module td_fused_top_fifo_w8_d7_S_x0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] s... | 6.827284 |
module td_fused_top_fifo_w8_d7_S_x_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr... | 6.827284 |
module td_fused_top_fifo_w8_d8_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
inpu... | 6.827284 |
module td_fused_top_fifo_w8_d8_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_fifo_w8_d8_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_fifo_w8_d8_S_x (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
in... | 6.827284 |
module td_fused_top_fifo_w8_d8_S_x_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr... | 6.827284 |
module td_fused_top_fifo_w8_d8_S_x0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
i... | 6.827284 |
module td_fused_top_fifo_w8_d8_S_x0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] s... | 6.827284 |
module td_fused_top_fifo_w8_d8_S_x0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] s... | 6.827284 |
module td_fused_top_fifo_w8_d8_S_x_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr... | 6.827284 |
module td_fused_top_fifo_w9_d2_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd9;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
inpu... | 6.827284 |
module td_fused_top_fifo_w9_d2_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd9;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_fifo_w9_d2_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd9;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_fifo_w9_d2_S_x (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd9;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
in... | 6.827284 |
module td_fused_top_fifo_w9_d2_S_x_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd9;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr... | 6.827284 |
module td_fused_top_fifo_w9_d2_S_x_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd9;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr... | 6.827284 |
module td_fused_top_fifo_w9_d7_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd9;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
inpu... | 6.827284 |
module td_fused_top_fifo_w9_d7_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd9;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_fifo_w9_d7_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd9;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_fifo_w9_d8_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd9;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
inpu... | 6.827284 |
module td_fused_top_fifo_w9_d8_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd9;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_fifo_w9_d8_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd9;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_hadd_16ns_16ns_16_2_full_dsp_1 #(
parameter ID = 45,
NUM_STAGE = 2,
din0_WIDTH = 16,
din1_WIDTH = 16,
dout_WIDTH = 16
) (
input wire clk,
input wire reset,
input wire ... | 6.827284 |
module td_fused_top_ap_hadd_0_full_dsp_16 (
input wire s_axis_a_tvalid,
input wire [15:0] s_axis_a_tdata,
input wire s_axis_b_tvalid,
input wire [15:0] s_axis_b_tdata,
output wire m_axis_result_tvalid,
output wire [15:0] m_axis_result_tdata
);
`ifdef complex_dsp
adde... | 6.827284 |
module FPAddSub_ExceptionModule (
Z,
NegE,
R,
S,
InputExc,
EOF,
P,
Flags
);
// Input ports
input [`DWIDTH-1:0] Z; // Final product
input NegE; // Negative exponent?
input R; // Round bit
input S; // Sticky bit
input [4:0] InputExc; // Exceptions in inputs A and B
inpu... | 7.326377 |
module FPAddSub_RoundModule (
ZeroSum,
NormE,
NormM,
R,
S,
G,
Sa,
Sb,
Ctrl,
MaxAB,
Z,
EOF
);
// Input ports
input ZeroSum; // Sum is zero
input [`EXPONENT:0] NormE; // Normalized exponent
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input R; // Round... | 7.753919 |
module FPAddSub_NormalizeShift2 (
PSSum,
CExp,
Shift,
NormM,
NormE,
ZeroSum,
NegE,
R,
S,
FG
);
// Input ports
input [`DWIDTH:0] PSSum; // The Pre-Shift-Sum
input [`EXPONENT-1:0] CExp;
input [4:0] Shift; // Amount to be shifted
// Output ports
output [`MANTISSA-1:0... | 6.905513 |
module FPAddSub_NormalizeShift1 (
MminP,
Shift,
Mmin
);
// Input ports
input [`DWIDTH:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [3:0] Shift; // Shift amount
// Output ports
output [`DWIDTH:0] Mmin; // The smaller mantissa
reg [ `DWIDTH:0] Lvl2;
wire [2*`DWIDTH+1... | 6.905513 |
module FPAddSub_NormalizeModule (
Sum,
Mmin,
Shift
);
// Input ports
input [`DWIDTH:0] Sum; // Mantissa sum including hidden 1 and GRS
// Output ports
output [`DWIDTH:0] Mmin; // Mantissa after 16|0 shift
output [4:0] Shift; // Shift amount
// Determine normalization shift amount by findin... | 6.905513 |
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