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# Running a simple combinatorial design
Tool: OpenDB
Subcategory: Module name mismatch
## Conversation
### Dandy201
Hi all, I'm new to using ORFS and tried some tutorials from https://github.com/The-OpenROAD-Project/micro2022tutorial.
Completing exercise 5 got this simple output:
.
From this, I'm trying to make a simple combinational circuit. Running make DESIGN_CONFIG=../../half_Adder/config.mk, it always ends at this error:
7. Executing Verilog-2005 frontend: /home/dan/Desktop/Work/vlsi/tools/OpenROAD-flow-scripts/flow/platforms/asap7/yoSys/cells_clkgate_R.v
Using ABC speed script.
[FLOW] Extracting clock period from SDC file: ./results/asap7/halfAdder/base/clock_period.txt
[FLOW] Setting clock period to 5
8. Executing SYNTH pass.
8.1. Executing HIERARCHY pass (managing design hierarchy).
**ERROR: TCL interpreter returned an error: Yosys command produced an error
Command exited with non-zero status 1
Elapsed time: 0:00.59[h:]min:sec. CPU time: user 0.56 sys 0.02 (99%). Peak memory: 72508KB.
make[1]: *** [Makefile:496: do-yosys] Error 1
make: *** [Makefile:499: results/asap7/halfAdder/base/1_1_yosys.v] Error 2.**
Config file
Constraint file
Verilog file
### maliberty
Please package this as a standalone test case and attach it. Reproducing it from screen shots is inefficient.
### Dandy201
[try.zip](https://github.com/user-attachments/files/15751707/try.zip)
Here's the zip file along with the command : make DESIGN_CONFIG=../../try/config.mk
### mi-and-core
(1) change module name from 'half_adder' to 'halfAdder'
### maliberty
In the config.mk
```
export DESIGN_NAME = halfAdder
```
while in halfAdder.v:
```
module half_adder(
```
These names need to match.
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