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# Can I calculate the delay for a macro based on the .lib file?
Tool: OpenSTA
Subcategory: Understanding delay calculation
## Conversation
### oharboe
I would like to understand the .lib file format a bit better. It is my understanding that I should be able to calculate the delay of the macro output based on what is in the .lib file.
For the mock-array, we have 183.19 ps delay for driving the io_outs_left[0] output. Looking at the .lib file, I can't figure out where 183.19ps comes from.
```
183.19 486.43 ^ ces_7_0/io_outs_left[0] (Element)
```
From mock-array:
```
>>> report_checks -path_delay max -to io_outs_left_7[0] -format full -format full_clock_expanded
Startpoint: ces_7_0 (rising edge-triggered flip-flop clocked by clock)
Endpoint: io_outs_left_7[0] (output port clocked by clock)
Path Group: clock
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clock (rise edge)
0.00 0.00 clock source latency
0.00 0.00 ^ clock (in)
38.29 38.29 ^ wire65/Y (BUFx16f_ASAP7_75t_R)
43.22 81.50 ^ clkbuf_0_clock/Y (BUFx4_ASAP7_75t_R)
39.84 121.35 ^ clkbuf_1_1_0_clock/Y (BUFx4_ASAP7_75t_R)
29.43 150.78 ^ clkbuf_2_2_0_clock/Y (BUFx4_ASAP7_75t_R)
32.00 182.78 ^ clkbuf_3_5_0_clock/Y (BUFx4_ASAP7_75t_R)
39.23 222.00 ^ clkbuf_4_10_0_clock/Y (BUFx4_ASAP7_75t_R)
16.70 238.70 ^ max_length67/Y (BUFx12f_ASAP7_75t_R)
30.80 269.51 ^ max_length66/Y (BUFx12f_ASAP7_75t_R)
33.73 303.24 ^ ces_7_0/clock (Element)
183.19 486.43 ^ ces_7_0/io_outs_left[0] (Element)
18.46 504.89 ^ output3073/Y (BUFx2_ASAP7_75t_R)
0.88 505.77 ^ io_outs_left_7[0] (out)
505.77 data arrival time
1000.00 1000.00 clock clock (rise edge)
0.00 1000.00 clock network delay (propagated)
0.00 1000.00 clock reconvergence pessimism
-200.00 800.00 output external delay
800.00 data required time
---------------------------------------------------------
800.00 data required time
-505.77 data arrival time
---------------------------------------------------------
294.23 slack (MET)
```
If I look in the Element, I can get a full report of what is driving that pin. However, my understanding is that some detail(I don't know what) is lost in the Element.lib representation:
```
>>> report_checks -path_delay max -to io_outs_left[0]
Startpoint: _749_ (falling edge-triggered flip-flop clocked by clock')
Endpoint: io_outs_left[0] (output port clocked by clock)
Path Group: clock
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clock' (fall edge)
108.94 108.94 clock network delay (propagated)
0.00 108.94 v _749_/CLK (DFFLQNx2_ASAP7_75t_R)
47.39 156.33 v _749_/QN (DFFLQNx2_ASAP7_75t_R)
12.65 168.98 ^ _496_/Y (INVx3_ASAP7_75t_R)
18.89 187.86 ^ _777_/Y (BUFx2_ASAP7_75t_R)
18.21 206.07 ^ output336/Y (BUFx2_ASAP7_75t_R)
0.75 206.82 ^ io_outs_left[0] (out)
206.82 data arrival time
1000.00 1000.00 clock clock (rise edge)
0.00 1000.00 clock network delay (propagated)
-20.00 980.00 clock uncertainty
0.00 980.00 clock reconvergence pessimism
-50.00 930.00 output external delay
930.00 data required time
---------------------------------------------------------
930.00 data required time
-206.82 data arrival time
---------------------------------------------------------
723.18 slack (MET)
```
Here the latency is 206.82, so that's not the same as 183.19 above...
Here is the pin from the .lib file... Since the above is a rising transition, I think something in the "rise" part should add up to 183.19?
```
library (Element) {
comment : "";
delay_model : table_lookup;
simulation : false;
capacitive_load_unit (1,fF);
leakage_power_unit : 1pW;
current_unit : "1A";
pulling_resistance_unit : "1kohm";
time_unit : "1ps";
voltage_unit : "1v";
library_features(report_delay_calculation);
input_threshold_pct_rise : 50;
input_threshold_pct_fall : 50;
output_threshold_pct_rise : 50;
output_threshold_pct_fall : 50;
slew_lower_threshold_pct_rise : 10;
slew_lower_threshold_pct_fall : 10;
slew_upper_threshold_pct_rise : 90;
slew_upper_threshold_pct_fall : 90;
slew_derate_from_library : 1.0;
nom_process : 1.0;
nom_temperature : 0.0;
nom_voltage : 0.77;
lu_table_template(template_1) {
variable_1 : total_output_net_capacitance;
index_1 ("1.44000, 2.88000, 5.76000, 11.52000, 23.04000, 46.08000, 92.16000");
}
[deleted]
type ("io_outs_left") {
base_type : array;
data_type : bit;
bit_width : 64;
bit_from : 63;
bit_to : 0;
}
[deleted]
pin("io_outs_left[0]") {
direction : output;
capacitance : 0.0000;
timing() {
related_pin : "clock";
timing_type : rising_edge;
cell_rise(template_1) {
values("179.22894,181.54152,185.64272,193.40265,208.65739,239.04976,299.74982");
}
rise_transition(template_1) {
values("7.61338,11.68247,19.95989,36.84301,71.06670,139.93100,277.88907");
}
cell_fall(template_1) {
values("176.95767,179.16806,182.98384,189.92587,203.38441,230.16859,283.65878");
}
fall_transition(template_1) {
values("6.99804,10.42909,17.26771,31.14958,59.35967,116.35495,230.77396");
}
}
}
```
When I look at mock-array, I see that the wire is highlighted in yellow when I clock on the Element delay.
But when I click on the next line, that wire segment is also highlighted.
So I guess the wire segments are associated with some of the lines in the timing list, but I can't see what the delay is due to the wire and I don't know which item that delay is associated with. I have seen separate "wire" lines in the timing report for `make gui_final`, but not in this case...
### maliberty
You might try report_dcalc. Also ```report_checks -path_delay min -fields {slew cap input nets fanout} ``` helps to break out the gate and net delay.
In general it isn't a simple calculation when there are wire parasitics. With a simple capacitive load you just look at the table and interpolate.
In this case I would suspect input slews might be different between block and top level.
### rovinski
Maybe take a read of this article to help understand the non-linear delay model (NLDM) for .lib:
https://www.physicaldesign4u.com/2020/05/non-linear-delay-model-nldm-in-vlsi.html
The "exact number" will never appear in the .lib file. The .lib file creates a series of lookup tables. The inputs to those lookup tables are the capacitance of the wiring on the output and the input slew. If the inputs are not exactly one of the keys in the lookup table (which they usually aren't because of floating point numbers) then the output is interpolated. You will almost never see the "exact" delay value appear in the .lib file itself.
### maliberty
```report_dcalc -from output3073/A -to output3073/Y```
works but the report is not simple to interpret
### maliberty
What is your goal in this process? Likely there is more calculation in the interconnect side of the delay.
You can only use it on a single arc and not along a path.
### oharboe
I am looking at some numbers that are concerning and I wanted to understand this well enough that I can find out if OpenROAD/STA are probably working correctly or if the numbers are off and it is worth digging in to.
I think I do now.
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