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# MegaBoom with clock tree
Tool: Clock Tree Synthesis
Subcategory: Clock tree issue
## Conversation
### oharboe
Looks much more reasonable now. There are H-clock trees after CTS.
`make cts_issue`; CTS takes ca. 25000 seconds on my machine: https://drive.google.com/file/d/13eenpP2JgzXJD0uP3KIpX4QLArBVjzT2/view?usp=sharing
This is apples and oranges comparision, but ... Minimum clock period is 5000ps, whereas I've seen claims on the order of 1000ps with commercial tools for the most similar design I know of to MegaBoom: https://carrv.github.io/2020/papers/CARRV2020_paper_15_Zhao.pdf
```
>>> report_clock_min_period
clock period_min = 5403.70 fmax = 185.06
clock_vir period_min = 0.00 fmax = inf
fake_pll_clk period_min = 5403.70 fmax = 185.06
serial_tl_0_clock period_min = 953.62 fmax = 1048.63
```
Yellow are hold cells, very reasonable... Clock tree looks odd. Those leaf nodes on the right side are flip flops. It would be nice if there was some clear visual indication of macros vs. flip flop endpoints in the CTS view....
```
report_checks -path_delay max -fields {fanout skew}
Startpoint: reset (input port clocked by clock_vir)
Endpoint: system/prci_ctrl_domain/_3041_
(recovery check against rising-edge clock fake_pll_clk)
Path Group: asynchronous
Path Type: max
Fanout Delay Time Description
---------------------------------------------------------------
0.00 0.00 clock clock_vir (rise edge)
1000.00 1000.00 clock network delay (ideal)
1700.00 2700.00 v input external delay
1 0.00 2700.00 v reset (in)
1 10.58 2710.58 v hold4662/Y (BUFx2_ASAP7_75t_R)
1 12.61 2723.18 v hold4387/Y (BUFx2_ASAP7_75t_R)
1 12.49 2735.67 v hold4663/Y (BUFx2_ASAP7_75t_R)
1 12.65 2748.32 v hold4335/Y (BUFx2_ASAP7_75t_R)
1 12.65 2760.97 v hold4664/Y (BUFx2_ASAP7_75t_R)
1 12.72 2773.69 v hold4388/Y (BUFx2_ASAP7_75t_R)
1 12.81 2786.50 v hold4665/Y (BUFx2_ASAP7_75t_R)
1 12.50 2799.00 v hold64/Y (BUFx2_ASAP7_75t_R)
1 12.66 2811.66 v hold4666/Y (BUFx2_ASAP7_75t_R)
1 12.66 2824.31 v hold4389/Y (BUFx2_ASAP7_75t_R)
1 12.59 2836.91 v hold4667/Y (BUFx2_ASAP7_75t_R)
1 12.71 2849.61 v hold4336/Y (BUFx2_ASAP7_75t_R)
1 12.48 2862.09 v hold4668/Y (BUFx2_ASAP7_75t_R)
1 12.39 2874.48 v hold4390/Y (BUFx2_ASAP7_75t_R)
1 12.40 2886.88 v hold4669/Y (BUFx2_ASAP7_75t_R)
1 12.34 2899.21 v hold56/Y (BUFx2_ASAP7_75t_R)
1 12.32 2911.54 v hold4670/Y (BUFx2_ASAP7_75t_R)
1 12.23 2923.77 v hold4391/Y (BUFx2_ASAP7_75t_R)
1 12.45 2936.22 v hold4671/Y (BUFx2_ASAP7_75t_R)
1 12.49 2948.71 v hold4337/Y (BUFx2_ASAP7_75t_R)
1 12.35 2961.06 v hold4672/Y (BUFx2_ASAP7_75t_R)
1 12.16 2973.22 v hold4392/Y (BUFx2_ASAP7_75t_R)
1 12.26 2985.48 v hold4673/Y (BUFx2_ASAP7_75t_R)
1 12.38 2997.87 v hold65/Y (BUFx2_ASAP7_75t_R)
1 12.25 3010.12 v hold4674/Y (BUFx2_ASAP7_75t_R)
1 12.19 3022.31 v hold4393/Y (BUFx2_ASAP7_75t_R)
1 12.21 3034.52 v hold4675/Y (BUFx2_ASAP7_75t_R)
1 12.21 3046.72 v hold4338/Y (BUFx2_ASAP7_75t_R)
1 12.47 3059.19 v hold4676/Y (BUFx2_ASAP7_75t_R)
1 12.59 3071.78 v hold4394/Y (BUFx2_ASAP7_75t_R)
1 15.63 3087.41 v hold4677/Y (BUFx2_ASAP7_75t_R)
1 18.70 3106.12 v input5/Y (BUFx24_ASAP7_75t_R)
1 13.56 3119.68 v hold4678/Y (BUFx2_ASAP7_75t_R)
1 14.47 3134.15 v hold4395/Y (BUFx2_ASAP7_75t_R)
1 15.29 3149.44 v hold4339/Y (BUFx2_ASAP7_75t_R)
1 15.29 3164.73 v hold4396/Y (BUFx2_ASAP7_75t_R)
1 15.27 3180.00 v hold66/Y (BUFx2_ASAP7_75t_R)
1 15.29 3195.29 v hold4397/Y (BUFx2_ASAP7_75t_R)
1 15.25 3210.53 v hold4340/Y (BUFx2_ASAP7_75t_R)
1 15.21 3225.74 v hold4398/Y (BUFx2_ASAP7_75t_R)
1 15.29 3241.03 v hold57/Y (BUFx2_ASAP7_75t_R)
1 15.30 3256.34 v hold4399/Y (BUFx2_ASAP7_75t_R)
1 15.23 3271.56 v hold4341/Y (BUFx2_ASAP7_75t_R)
1 15.26 3286.82 v hold4400/Y (BUFx2_ASAP7_75t_R)
1 15.29 3302.12 v hold67/Y (BUFx2_ASAP7_75t_R)
1 15.24 3317.35 v hold4401/Y (BUFx2_ASAP7_75t_R)
1 15.20 3332.56 v hold4342/Y (BUFx2_ASAP7_75t_R)
1 17.90 3350.46 v hold4402/Y (BUFx2_ASAP7_75t_R)
1 16.93 3367.38 v wire96200/Y (BUFx16f_ASAP7_75t_R)
1 14.22 3381.60 v hold4403/Y (BUFx2_ASAP7_75t_R)
1 15.14 3396.75 v hold4343/Y (BUFx2_ASAP7_75t_R)
1 15.26 3412.01 v hold4404/Y (BUFx2_ASAP7_75t_R)
1 15.29 3427.30 v hold68/Y (BUFx2_ASAP7_75t_R)
1 15.19 3442.49 v hold4405/Y (BUFx2_ASAP7_75t_R)
1 15.21 3457.70 v hold4344/Y (BUFx2_ASAP7_75t_R)
1 15.28 3472.98 v hold4406/Y (BUFx2_ASAP7_75t_R)
1 15.24 3488.22 v hold58/Y (BUFx2_ASAP7_75t_R)
1 15.18 3503.40 v hold4407/Y (BUFx2_ASAP7_75t_R)
1 15.24 3518.64 v hold4345/Y (BUFx2_ASAP7_75t_R)
1 15.23 3533.87 v hold4408/Y (BUFx2_ASAP7_75t_R)
1 15.18 3549.06 v hold69/Y (BUFx2_ASAP7_75t_R)
1 15.15 3564.21 v hold4409/Y (BUFx2_ASAP7_75t_R)
1 15.13 3579.33 v hold4346/Y (BUFx2_ASAP7_75t_R)
1 17.89 3597.22 v hold4410/Y (BUFx2_ASAP7_75t_R)
1 16.94 3614.16 v wire96199/Y (BUFx16f_ASAP7_75t_R)
1 14.34 3628.51 v hold4411/Y (BUFx2_ASAP7_75t_R)
1 15.29 3643.80 v hold4347/Y (BUFx2_ASAP7_75t_R)
1 15.28 3659.08 v hold4412/Y (BUFx2_ASAP7_75t_R)
1 15.28 3674.36 v hold70/Y (BUFx2_ASAP7_75t_R)
1 15.29 3689.65 v hold4413/Y (BUFx2_ASAP7_75t_R)
1 15.29 3704.94 v hold4348/Y (BUFx2_ASAP7_75t_R)
1 15.24 3720.18 v hold4414/Y (BUFx2_ASAP7_75t_R)
1 15.31 3735.49 v hold59/Y (BUFx2_ASAP7_75t_R)
1 15.33 3750.82 v hold4415/Y (BUFx2_ASAP7_75t_R)
1 15.27 3766.08 v hold4349/Y (BUFx2_ASAP7_75t_R)
1 15.24 3781.32 v hold4416/Y (BUFx2_ASAP7_75t_R)
1 15.21 3796.53 v hold71/Y (BUFx2_ASAP7_75t_R)
1 15.32 3811.85 v hold4417/Y (BUFx2_ASAP7_75t_R)
1 15.36 3827.21 v hold4350/Y (BUFx2_ASAP7_75t_R)
1 17.90 3845.10 v hold4418/Y (BUFx2_ASAP7_75t_R)
1 16.84 3861.95 v wire96198/Y (BUFx16f_ASAP7_75t_R)
1 14.33 3876.27 v hold4419/Y (BUFx2_ASAP7_75t_R)
1 15.34 3891.61 v hold4351/Y (BUFx2_ASAP7_75t_R)
1 15.31 3906.92 v hold4420/Y (BUFx2_ASAP7_75t_R)
1 15.21 3922.13 v hold72/Y (BUFx2_ASAP7_75t_R)
1 15.30 3937.43 v hold4421/Y (BUFx2_ASAP7_75t_R)
1 15.29 3952.73 v hold4352/Y (BUFx2_ASAP7_75t_R)
1 15.20 3967.93 v hold4422/Y (BUFx2_ASAP7_75t_R)
1 15.33 3983.26 v hold60/Y (BUFx2_ASAP7_75t_R)
1 15.31 3998.57 v hold4423/Y (BUFx2_ASAP7_75t_R)
1 15.31 4013.88 v hold4353/Y (BUFx2_ASAP7_75t_R)
1 15.28 4029.16 v hold4424/Y (BUFx2_ASAP7_75t_R)
1 15.17 4044.33 v hold73/Y (BUFx2_ASAP7_75t_R)
1 15.24 4059.57 v hold4425/Y (BUFx2_ASAP7_75t_R)
1 15.37 4074.94 v hold4354/Y (BUFx2_ASAP7_75t_R)
1 17.95 4092.90 v hold4426/Y (BUFx2_ASAP7_75t_R)
1 16.85 4109.75 v wire96197/Y (BUFx16f_ASAP7_75t_R)
1 14.32 4124.07 v hold4427/Y (BUFx2_ASAP7_75t_R)
1 15.33 4139.40 v hold4355/Y (BUFx2_ASAP7_75t_R)
1 15.37 4154.77 v hold4428/Y (BUFx2_ASAP7_75t_R)
1 15.24 4170.01 v hold74/Y (BUFx2_ASAP7_75t_R)
1 15.19 4185.20 v hold4429/Y (BUFx2_ASAP7_75t_R)
1 15.26 4200.45 v hold4356/Y (BUFx2_ASAP7_75t_R)
1 15.22 4215.67 v hold4430/Y (BUFx2_ASAP7_75t_R)
1 15.31 4230.98 v hold61/Y (BUFx2_ASAP7_75t_R)
1 15.27 4246.25 v hold4431/Y (BUFx2_ASAP7_75t_R)
1 15.28 4261.53 v hold4357/Y (BUFx2_ASAP7_75t_R)
1 15.33 4276.86 v hold4432/Y (BUFx2_ASAP7_75t_R)
1 15.29 4292.15 v hold75/Y (BUFx2_ASAP7_75t_R)
1 15.21 4307.35 v hold4433/Y (BUFx2_ASAP7_75t_R)
1 15.23 4322.59 v hold4358/Y (BUFx2_ASAP7_75t_R)
1 17.96 4340.55 v hold4434/Y (BUFx2_ASAP7_75t_R)
1 20.57 4361.13 v wire96196/Y (BUFx24_ASAP7_75t_R)
1 14.76 4375.89 v hold4435/Y (BUFx2_ASAP7_75t_R)
1 15.31 4391.20 v hold4359/Y (BUFx2_ASAP7_75t_R)
1 15.29 4406.49 v hold4436/Y (BUFx2_ASAP7_75t_R)
1 15.27 4421.75 v hold76/Y (BUFx2_ASAP7_75t_R)
1 15.27 4437.02 v hold4437/Y (BUFx2_ASAP7_75t_R)
1 15.24 4452.26 v hold4360/Y (BUFx2_ASAP7_75t_R)
1 15.26 4467.52 v hold4438/Y (BUFx2_ASAP7_75t_R)
1 15.27 4482.79 v hold62/Y (BUFx2_ASAP7_75t_R)
1 15.20 4497.99 v hold4439/Y (BUFx2_ASAP7_75t_R)
1 15.18 4513.17 v hold4361/Y (BUFx2_ASAP7_75t_R)
1 15.25 4528.42 v hold4440/Y (BUFx2_ASAP7_75t_R)
1 15.24 4543.66 v hold77/Y (BUFx2_ASAP7_75t_R)
1 15.22 4558.88 v hold4441/Y (BUFx2_ASAP7_75t_R)
1 15.35 4574.23 v hold4362/Y (BUFx2_ASAP7_75t_R)
1 22.85 4597.08 v hold4442/Y (BUFx2_ASAP7_75t_R)
15 15.42 4612.50 ^ system/prci_ctrl_domain/_1567_/Y (INVx11_ASAP7_75t_R)
2.22 4614.72 ^ system/prci_ctrl_domain/_3041_/SETN (DFFASRHQNx1_ASAP7_75t_R)
4614.72 data arrival time
8500.00 8500.00 clock fake_pll_clk (rise edge)
474.60 8974.60 clock network delay (propagated)
-10.00 8964.60 clock uncertainty
0.00 8964.60 clock reconvergence pessimism
8964.60 ^ system/prci_ctrl_domain/_3041_/CLK (DFFASRHQNx1_ASAP7_75t_R)
4.83 8969.43 library recovery time
8969.43 data required time
---------------------------------------------------------------
8969.43 data required time
-4614.72 data arrival time
---------------------------------------------------------------
4354.71 slack (MET)
Startpoint: system/prci_ctrl_domain/_2967_
(rising edge-triggered flip-flop clocked by clock)
Endpoint: system/prci_ctrl_domain/_1576_
(rising clock gating-check end-point clocked by fake_pll_clk)
Path Group: gated clock
Path Type: max
Fanout Delay Time Description
---------------------------------------------------------------
0.00 0.00 clock clock (rise edge)
983.66 983.66 clock network delay (propagated)
0.00 983.66 ^ system/prci_ctrl_domain/_2967_/CLK (DFFASRHQNx1_ASAP7_75t_R)
29 134.66 1118.32 v system/prci_ctrl_domain/_2967_/QN (DFFASRHQNx1_ASAP7_75t_R)
1 41.06 1159.38 v hold6293/Y (BUFx2_ASAP7_75t_R)
1 14.10 1173.47 v hold6165/Y (BUFx2_ASAP7_75t_R)
1 12.29 1185.77 v hold6294/Y (BUFx2_ASAP7_75t_R)
1 12.31 1198.07 v hold6101/Y (BUFx2_ASAP7_75t_R)
1 12.29 1210.37 v hold6295/Y (BUFx2_ASAP7_75t_R)
1 12.26 1222.63 v hold6166/Y (BUFx2_ASAP7_75t_R)
1 12.25 1234.88 v hold6296/Y (BUFx2_ASAP7_75t_R)
1 12.29 1247.17 v hold5379/Y (BUFx2_ASAP7_75t_R)
1 12.23 1259.39 v hold6297/Y (BUFx2_ASAP7_75t_R)
1 12.35 1271.74 v hold6167/Y (BUFx2_ASAP7_75t_R)
1 12.36 1284.10 v hold6298/Y (BUFx2_ASAP7_75t_R)
1 12.28 1296.38 v hold6102/Y (BUFx2_ASAP7_75t_R)
1 12.26 1308.63 v hold6299/Y (BUFx2_ASAP7_75t_R)
1 12.46 1321.09 v hold6168/Y (BUFx2_ASAP7_75t_R)
1 12.73 1333.82 v hold6300/Y (BUFx2_ASAP7_75t_R)
1 12.52 1346.34 v hold4926/Y (BUFx2_ASAP7_75t_R)
1 12.20 1358.54 v hold6301/Y (BUFx2_ASAP7_75t_R)
1 12.31 1370.85 v hold6169/Y (BUFx2_ASAP7_75t_R)
1 12.27 1383.12 v hold6302/Y (BUFx2_ASAP7_75t_R)
1 12.41 1395.53 v hold6103/Y (BUFx2_ASAP7_75t_R)
1 12.73 1408.26 v hold6303/Y (BUFx2_ASAP7_75t_R)
1 12.77 1421.03 v hold6170/Y (BUFx2_ASAP7_75t_R)
1 12.69 1433.72 v hold6304/Y (BUFx2_ASAP7_75t_R)
1 12.68 1446.40 v hold5380/Y (BUFx2_ASAP7_75t_R)
1 12.80 1459.19 v hold6305/Y (BUFx2_ASAP7_75t_R)
1 12.82 1472.02 v hold6171/Y (BUFx2_ASAP7_75t_R)
1 12.57 1484.59 v hold6306/Y (BUFx2_ASAP7_75t_R)
1 12.37 1496.96 v hold6104/Y (BUFx2_ASAP7_75t_R)
1 12.26 1509.22 v hold6307/Y (BUFx2_ASAP7_75t_R)
1 12.70 1521.92 v hold6172/Y (BUFx2_ASAP7_75t_R)
1 12.82 1534.74 v hold6308/Y (BUFx2_ASAP7_75t_R)
1 12.61 1547.36 v hold4681/Y (BUFx2_ASAP7_75t_R)
1 12.39 1559.74 v hold6309/Y (BUFx2_ASAP7_75t_R)
1 12.25 1572.00 v hold6173/Y (BUFx2_ASAP7_75t_R)
1 12.30 1584.30 v hold6310/Y (BUFx2_ASAP7_75t_R)
1 12.77 1597.06 v hold6105/Y (BUFx2_ASAP7_75t_R)
1 12.51 1609.57 v hold6311/Y (BUFx2_ASAP7_75t_R)
1 12.16 1621.73 v hold6174/Y (BUFx2_ASAP7_75t_R)
1 12.80 1634.53 v hold6312/Y (BUFx2_ASAP7_75t_R)
1 13.18 1647.71 v hold5381/Y (BUFx2_ASAP7_75t_R)
1 13.15 1660.86 v hold6313/Y (BUFx2_ASAP7_75t_R)
1 13.14 1674.00 v hold6175/Y (BUFx2_ASAP7_75t_R)
1 13.11 1687.12 v hold6314/Y (BUFx2_ASAP7_75t_R)
1 12.64 1699.76 v hold6106/Y (BUFx2_ASAP7_75t_R)
1 12.21 1711.97 v hold6315/Y (BUFx2_ASAP7_75t_R)
1 12.33 1724.29 v hold6176/Y (BUFx2_ASAP7_75t_R)
1 13.02 1737.31 v hold6316/Y (BUFx2_ASAP7_75t_R)
1 12.61 1749.93 v hold4927/Y (BUFx2_ASAP7_75t_R)
1 12.77 1762.70 v hold6317/Y (BUFx2_ASAP7_75t_R)
1 12.54 1775.24 v hold6177/Y (BUFx2_ASAP7_75t_R)
1 12.73 1787.97 v hold6318/Y (BUFx2_ASAP7_75t_R)
1 13.09 1801.06 v hold6107/Y (BUFx2_ASAP7_75t_R)
1 13.16 1814.23 v hold6319/Y (BUFx2_ASAP7_75t_R)
1 12.82 1827.04 v hold6178/Y (BUFx2_ASAP7_75t_R)
1 12.89 1839.94 v hold6320/Y (BUFx2_ASAP7_75t_R)
1 12.49 1852.42 v hold5382/Y (BUFx2_ASAP7_75t_R)
1 12.64 1865.07 v hold6321/Y (BUFx2_ASAP7_75t_R)
1 12.48 1877.55 v hold6179/Y (BUFx2_ASAP7_75t_R)
1 12.30 1889.85 v hold6322/Y (BUFx2_ASAP7_75t_R)
1 13.04 1902.89 v hold6108/Y (BUFx2_ASAP7_75t_R)
1 13.16 1916.05 v hold6323/Y (BUFx2_ASAP7_75t_R)
1 12.63 1928.68 v hold6180/Y (BUFx2_ASAP7_75t_R)
1 12.66 1941.34 v hold6324/Y (BUFx2_ASAP7_75t_R)
1 12.54 1953.88 v hold4532/Y (BUFx2_ASAP7_75t_R)
1 12.28 1966.16 v hold6325/Y (BUFx2_ASAP7_75t_R)
1 12.24 1978.40 v hold6181/Y (BUFx2_ASAP7_75t_R)
1 12.20 1990.60 v hold6326/Y (BUFx2_ASAP7_75t_R)
1 12.16 2002.76 v hold6109/Y (BUFx2_ASAP7_75t_R)
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1 13.29 5484.95 v hold5408/Y (BUFx2_ASAP7_75t_R)
1 13.66 5498.61 v hold6283/Y (BUFx2_ASAP7_75t_R)
1 12.76 5511.37 v hold6160/Y (BUFx2_ASAP7_75t_R)
1 12.90 5524.28 v hold6284/Y (BUFx2_ASAP7_75t_R)
1 12.92 5537.19 v hold4688/Y (BUFx2_ASAP7_75t_R)
1 12.60 5549.79 v hold6285/Y (BUFx2_ASAP7_75t_R)
1 12.30 5562.09 v hold6161/Y (BUFx2_ASAP7_75t_R)
1 12.50 5574.59 v hold6286/Y (BUFx2_ASAP7_75t_R)
1 12.39 5586.98 v hold5409/Y (BUFx2_ASAP7_75t_R)
1 12.57 5599.54 v hold6287/Y (BUFx2_ASAP7_75t_R)
1 12.79 5612.33 v hold6162/Y (BUFx2_ASAP7_75t_R)
1 12.72 5625.05 v hold6288/Y (BUFx2_ASAP7_75t_R)
1 12.32 5637.37 v hold4941/Y (BUFx2_ASAP7_75t_R)
1 12.26 5649.62 v hold6289/Y (BUFx2_ASAP7_75t_R)
1 12.30 5661.93 v hold6163/Y (BUFx2_ASAP7_75t_R)
1 12.76 5674.69 v hold6290/Y (BUFx2_ASAP7_75t_R)
1 12.90 5687.59 v hold5410/Y (BUFx2_ASAP7_75t_R)
1 12.56 5700.14 v hold6291/Y (BUFx2_ASAP7_75t_R)
1 12.33 5712.48 v hold6164/Y (BUFx2_ASAP7_75t_R)
1 12.32 5724.80 v hold6292/Y (BUFx2_ASAP7_75t_R)
0.02 5724.82 v system/prci_ctrl_domain/_1576_/A (AND2x2_ASAP7_75t_R)
5724.82 data arrival time
8500.00 8500.00 clock fake_pll_clk (rise edge)
898.15 9398.15 clock network delay (propagated)
-10.00 9388.15 clock uncertainty
0.00 9388.15 clock reconvergence pessimism
9388.15 ^ system/prci_ctrl_domain/_1576_/B (AND2x2_ASAP7_75t_R)
0.00 9388.15 clock gating setup time
9388.15 data required time
---------------------------------------------------------------
9388.15 data required time
-5724.82 data arrival time
---------------------------------------------------------------
3663.32 slack (MET)
Startpoint: system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_100801_
(rising edge-triggered flip-flop clocked by clock)
Endpoint: system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_3405_
(rising edge-triggered flip-flop clocked by clock)
Path Group: clock
Path Type: max
Fanout Delay Time Description
---------------------------------------------------------------
0.00 0.00 clock clock (rise edge)
1459.67 1459.67 clock network delay (propagated)
0.00 1459.67 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_100801_/CLK (DFFHQNx2_ASAP7_75t_R)
16 87.80 1547.47 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_100801_/QN (DFFHQNx2_ASAP7_75t_R)
8 25.27 1572.74 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_055753_/Y (INVx13_ASAP7_75t_R)
3 21.71 1594.45 v max_length80840/Y (BUFx12f_ASAP7_75t_R)
10 106.10 1700.55 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_100755_/CON (HAxp5_ASAP7_75t_R)
5 38.99 1739.54 ^ load_slew77788/Y (BUFx12f_ASAP7_75t_R)
6 18.39 1757.93 ^ load_slew77787/Y (BUFx12f_ASAP7_75t_R)
24 74.82 1832.75 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_055925_/Y (OR4x2_ASAP7_75t_R)
1 52.70 1885.46 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_055926_/Y (OA22x2_ASAP7_75t_R)
1 32.11 1917.56 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_055940_/Y (AND5x1_ASAP7_75t_R)
4 40.36 1957.93 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_055972_/Y (AND4x2_ASAP7_75t_R)
21 41.38 1999.31 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_055973_/Y (NAND2x2_ASAP7_75t_R)
3 92.34 2091.65 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_056022_/Y (OR3x4_ASAP7_75t_R)
4 34.23 2125.88 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_056088_/Y (NOR3x2_ASAP7_75t_R)
1 82.97 2208.86 ^ wire54325/Y (BUFx16f_ASAP7_75t_R)
3 79.05 2287.91 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09171_/Y (NAND2x2_ASAP7_75t_R)
2 72.45 2360.36 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09366_/Y (OA21x2_ASAP7_75t_R)
1 30.95 2391.30 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09368_/Y (OR4x1_ASAP7_75t_R)
2 43.84 2435.15 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09369_/Y (OR4x2_ASAP7_75t_R)
5 41.86 2477.01 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_10984_/Y (NOR3x2_ASAP7_75t_R)
20 54.43 2531.44 ^ wire46500/Y (BUFx16f_ASAP7_75t_R)
3 113.22 2644.66 ^ wire46499/Y (BUFx16f_ASAP7_75t_R)
2 74.22 2718.88 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383170_/Y (AND2x2_ASAP7_75t_R)
14 24.78 2743.66 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383188_/Y (NAND2x2_ASAP7_75t_R)
12 63.17 2806.83 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383224_/Y (AO21x2_ASAP7_75t_R)
5 24.83 2831.66 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_479882_/Y (CKINVDCx20_ASAP7_75t_R)
11 84.15 2915.81 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_732259_/CON (HAxp5_ASAP7_75t_R)
3 31.45 2947.26 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383227_/Y (INVx2_ASAP7_75t_R)
2 25.01 2972.27 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383231_/Y (AND2x2_ASAP7_75t_R)
2 22.19 2994.46 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_732246_/CON (HAxp5_ASAP7_75t_R)
2 31.03 3025.49 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_732246_/SN (HAxp5_ASAP7_75t_R)
1 31.95 3057.44 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_393218_/Y (XNOR2x1_ASAP7_75t_R)
1 40.29 3097.73 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_393222_/Y (AND5x2_ASAP7_75t_R)
1 38.93 3136.66 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09361_/Y (AO22x2_ASAP7_75t_R)
1 60.29 3196.95 ^ wire32998/Y (BUFx16f_ASAP7_75t_R)
1 63.16 3260.11 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09362_/Y (OR4x2_ASAP7_75t_R)
1 16.20 3276.31 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09363_/Y (OR4x1_ASAP7_75t_R)
1 19.72 3296.03 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09371_/Y (AO22x1_ASAP7_75t_R)
3 10.78 3306.81 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09372_/Y (INVx2_ASAP7_75t_R)
5 32.27 3339.08 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_10980_/Y (AND3x4_ASAP7_75t_R)
2 32.46 3371.54 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_10981_/Y (AND2x6_ASAP7_75t_R)
6 26.61 3398.15 v wire30552/Y (BUFx16f_ASAP7_75t_R)
3 117.06 3515.20 v wire30547/Y (BUFx16f_ASAP7_75t_R)
2 79.46 3594.66 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383202_/Y (AND2x2_ASAP7_75t_R)
13 30.10 3624.76 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383232_/Y (NAND2x2_ASAP7_75t_R)
37 104.44 3729.20 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383277_/Y (AO21x2_ASAP7_75t_R)
8 123.99 3853.19 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383285_/Y (NOR2x2_ASAP7_75t_R)
2 69.54 3922.74 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383289_/Y (AND2x2_ASAP7_75t_R)
2 70.43 3993.16 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_732263_/SN (HAxp5_ASAP7_75t_R)
1 35.94 4029.10 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_393224_/Y (XNOR2x1_ASAP7_75t_R)
1 33.88 4062.98 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_393228_/Y (AND5x2_ASAP7_75t_R)
1 22.63 4085.61 v wire18339/Y (BUFx12f_ASAP7_75t_R)
1 90.65 4176.26 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09348_/Y (AO221x2_ASAP7_75t_R)
1 78.25 4254.51 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09352_/Y (OR4x1_ASAP7_75t_R)
2 12.50 4267.01 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09353_/Y (INVx1_ASAP7_75t_R)
2 29.33 4296.34 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_13707_/Y (AND3x4_ASAP7_75t_R)
2 16.51 4312.85 ^ max_length17970/Y (BUFx12f_ASAP7_75t_R)
2 58.75 4371.60 ^ wire17968/Y (BUFx16f_ASAP7_75t_R)
4 69.67 4441.27 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383260_/Y (AND2x4_ASAP7_75t_R)
8 22.60 4463.87 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383290_/Y (NAND2x2_ASAP7_75t_R)
25 39.78 4503.65 v load_slew17553/Y (BUFx16f_ASAP7_75t_R)
8 52.97 4556.62 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_389614_/Y (OA21x2_ASAP7_75t_R)
15 27.29 4583.91 v max_length15743/Y (BUFx16f_ASAP7_75t_R)
6 44.22 4628.14 v wire15739/Y (BUFx16f_ASAP7_75t_R)
2 96.47 4724.61 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_732319_/CON (HAxp5_ASAP7_75t_R)
10 26.31 4750.92 ^ wire10637/Y (BUFx12f_ASAP7_75t_R)
9 28.31 4779.22 ^ wire10635/Y (BUFx12f_ASAP7_75t_R)
5 23.85 4803.08 ^ wire10634/Y (BUFx16f_ASAP7_75t_R)
3 49.02 4852.10 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_393150_/Y (INVx3_ASAP7_75t_R)
1 19.43 4871.53 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_732322_/CON (HAxp5_ASAP7_75t_R)
2 13.70 4885.23 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_732225_/Y (INVx1_ASAP7_75t_R)
2 54.56 4939.79 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_732324_/CON (HAxp5_ASAP7_75t_R)
2 57.06 4996.85 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_732324_/SN (HAxp5_ASAP7_75t_R)
1 39.36 5036.22 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_393230_/Y (XNOR2x1_ASAP7_75t_R)
1 29.47 5065.69 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_393234_/Y (AND5x2_ASAP7_75t_R)
1 38.32 5104.01 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09177_/Y (AO22x2_ASAP7_75t_R)
1 65.68 5169.69 v wire10120/Y (BUFx16f_ASAP7_75t_R)
1 85.75 5255.45 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09180_/Y (OR4x2_ASAP7_75t_R)
1 47.72 5303.17 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09181_/Y (OR4x2_ASAP7_75t_R)
1 14.50 5317.66 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09182_/Y (INVx1_ASAP7_75t_R)
3 20.96 5338.62 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09346_/Y (AO31x2_ASAP7_75t_R)
1 22.09 5360.71 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09357_/Y (AND2x2_ASAP7_75t_R)
3 22.17 5382.88 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09375_/Y (NAND3x2_ASAP7_75t_R)
2 44.87 5427.75 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_13855_/Y (NOR2x2_ASAP7_75t_R)
4 31.84 5459.59 ^ max_length10066/Y (BUFx16f_ASAP7_75t_R)
3 46.40 5505.98 ^ wire10064/Y (BUFx16f_ASAP7_75t_R)
1 74.29 5580.27 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_14394_/Y (AND2x2_ASAP7_75t_R)
1 5.61 5585.88 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/_065683_/Y (INVx1_ASAP7_75t_R)
2 61.87 5647.75 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/_065702_/Y (OR5x2_ASAP7_75t_R)
2 53.28 5701.03 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/_065722_/Y (NAND2x2_ASAP7_75t_R)
24 24.22 5725.25 ^ max_length8441/Y (BUFx16f_ASAP7_75t_R)
22 43.01 5768.26 ^ wire8439/Y (BUFx16f_ASAP7_75t_R)
19 49.84 5818.10 ^ load_slew8429/Y (BUFx16f_ASAP7_75t_R)
14 47.09 5865.20 ^ wire8426/Y (BUFx16f_ASAP7_75t_R)
11 48.21 5913.41 ^ max_length8425/Y (BUFx16f_ASAP7_75t_R)
10 58.85 5972.26 ^ wire8424/Y (BUFx16f_ASAP7_75t_R)
10 61.11 6033.37 ^ max_length8423/Y (BUFx12f_ASAP7_75t_R)
11 38.21 6071.58 ^ wire8422/Y (BUFx16f_ASAP7_75t_R)
25 51.58 6123.15 ^ wire8421/Y (BUFx16f_ASAP7_75t_R)
6 60.76 6183.91 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_1678_/Y (INVx11_ASAP7_75t_R)
24 21.32 6205.24 v max_length4569/Y (BUFx16f_ASAP7_75t_R)
11 62.98 6268.22 v wire4568/Y (BUFx16f_ASAP7_75t_R)
10 53.54 6321.76 v wire4567/Y (BUFx16f_ASAP7_75t_R)
12 73.47 6395.22 v wire4566/Y (BUFx16f_ASAP7_75t_R)
35 109.03 6504.25 v max_length4564/Y (BUFx16f_ASAP7_75t_R)
57 67.38 6571.63 v load_slew4563/Y (BUFx16f_ASAP7_75t_R)
1 95.45 6667.09 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_1885_/Y (NAND2x1_ASAP7_75t_R)
13 52.03 6719.12 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_1886_/Y (OA21x2_ASAP7_75t_R)
1 30.21 6749.33 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_3041_/Y (XNOR2x1_ASAP7_75t_R)
1 30.06 6779.38 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_3043_/Y (AND4x1_ASAP7_75t_R)
1 32.88 6812.26 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_3047_/Y (AND5x1_ASAP7_75t_R)
1 19.43 6831.69 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_3048_/Y (OR4x1_ASAP7_75t_R)
1 29.64 6861.33 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_3133_/Y (OA31x2_ASAP7_75t_R)
2.24 6863.57 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_3405_/D (DFFHQNx2_ASAP7_75t_R)
6863.57 data arrival time
8500.00 8500.00 clock clock (rise edge)
1476.29 9976.29 clock network delay (propagated)
-10.00 9966.29 clock uncertainty
4.53 9970.81 clock reconvergence pessimism
9970.81 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_3405_/CLK (DFFHQNx2_ASAP7_75t_R)
-10.95 9959.87 library setup time
9959.87 data required time
---------------------------------------------------------------
9959.87 data required time
-6863.57 data arrival time
---------------------------------------------------------------
3096.30 slack (MET)
Startpoint: system/serial_tl_domain/_1142_
(rising edge-triggered flip-flop clocked by clock)
Endpoint: serial_tl_0_bits_in_ready (output port clocked by clock_vir)
Path Group: clock_vir
Path Type: max
Fanout Delay Time Description
---------------------------------------------------------------
0.00 0.00 clock clock (rise edge)
1486.19 1486.19 clock network delay (propagated)
0.00 1486.19 ^ system/serial_tl_domain/_1142_/CLK (DFFHQNx2_ASAP7_75t_R)
3 50.71 1536.90 ^ system/serial_tl_domain/_1142_/QN (DFFHQNx2_ASAP7_75t_R)
3 35.82 1572.72 v system/serial_tl_domain/_0641_/Y (NOR3x2_ASAP7_75t_R)
1 61.16 1633.88 v output14/Y (BUFx2_ASAP7_75t_R)
0.02 1633.90 v serial_tl_0_bits_in_ready (out)
1633.90 data arrival time
8500.00 8500.00 clock clock_vir (rise edge)
1000.00 9500.00 clock network delay (ideal)
-10.00 9490.00 clock uncertainty
0.00 9490.00 clock reconvergence pessimism
-1700.00 7790.00 output external delay
7790.00 data required time
---------------------------------------------------------------
7790.00 data required time
-1633.90 data arrival time
---------------------------------------------------------------
6156.10 slack (MET)
Startpoint: system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_100801_
(rising edge-triggered flip-flop clocked by clock)
Endpoint: system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_3405_
(rising edge-triggered flip-flop clocked by fake_pll_clk)
Path Group: fake_pll_clk
Path Type: max
Fanout Delay Time Description
---------------------------------------------------------------
0.00 0.00 clock clock (rise edge)
1459.67 1459.67 clock network delay (propagated)
0.00 1459.67 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_100801_/CLK (DFFHQNx2_ASAP7_75t_R)
16 87.80 1547.47 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_100801_/QN (DFFHQNx2_ASAP7_75t_R)
8 25.27 1572.74 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_055753_/Y (INVx13_ASAP7_75t_R)
3 21.71 1594.45 v max_length80840/Y (BUFx12f_ASAP7_75t_R)
10 106.10 1700.55 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_100755_/CON (HAxp5_ASAP7_75t_R)
5 38.99 1739.54 ^ load_slew77788/Y (BUFx12f_ASAP7_75t_R)
6 18.39 1757.93 ^ load_slew77787/Y (BUFx12f_ASAP7_75t_R)
24 74.82 1832.75 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_055925_/Y (OR4x2_ASAP7_75t_R)
1 52.70 1885.46 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_055926_/Y (OA22x2_ASAP7_75t_R)
1 32.11 1917.56 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_055940_/Y (AND5x1_ASAP7_75t_R)
4 40.36 1957.93 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_055972_/Y (AND4x2_ASAP7_75t_R)
21 41.38 1999.31 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_055973_/Y (NAND2x2_ASAP7_75t_R)
3 92.34 2091.65 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_056022_/Y (OR3x4_ASAP7_75t_R)
4 34.23 2125.88 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_056088_/Y (NOR3x2_ASAP7_75t_R)
1 82.97 2208.86 ^ wire54325/Y (BUFx16f_ASAP7_75t_R)
3 79.05 2287.91 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09171_/Y (NAND2x2_ASAP7_75t_R)
2 72.45 2360.36 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09366_/Y (OA21x2_ASAP7_75t_R)
1 30.95 2391.30 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09368_/Y (OR4x1_ASAP7_75t_R)
2 43.84 2435.15 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09369_/Y (OR4x2_ASAP7_75t_R)
5 41.86 2477.01 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_10984_/Y (NOR3x2_ASAP7_75t_R)
20 54.43 2531.44 ^ wire46500/Y (BUFx16f_ASAP7_75t_R)
3 113.22 2644.66 ^ wire46499/Y (BUFx16f_ASAP7_75t_R)
2 74.22 2718.88 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383170_/Y (AND2x2_ASAP7_75t_R)
14 24.78 2743.66 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383188_/Y (NAND2x2_ASAP7_75t_R)
12 63.17 2806.83 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383224_/Y (AO21x2_ASAP7_75t_R)
5 24.83 2831.66 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_479882_/Y (CKINVDCx20_ASAP7_75t_R)
11 84.15 2915.81 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_732259_/CON (HAxp5_ASAP7_75t_R)
3 31.45 2947.26 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383227_/Y (INVx2_ASAP7_75t_R)
2 25.01 2972.27 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383231_/Y (AND2x2_ASAP7_75t_R)
2 22.19 2994.46 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_732246_/CON (HAxp5_ASAP7_75t_R)
2 31.03 3025.49 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_732246_/SN (HAxp5_ASAP7_75t_R)
1 31.95 3057.44 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_393218_/Y (XNOR2x1_ASAP7_75t_R)
1 40.29 3097.73 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_393222_/Y (AND5x2_ASAP7_75t_R)
1 38.93 3136.66 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09361_/Y (AO22x2_ASAP7_75t_R)
1 60.29 3196.95 ^ wire32998/Y (BUFx16f_ASAP7_75t_R)
1 63.16 3260.11 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09362_/Y (OR4x2_ASAP7_75t_R)
1 16.20 3276.31 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09363_/Y (OR4x1_ASAP7_75t_R)
1 19.72 3296.03 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09371_/Y (AO22x1_ASAP7_75t_R)
3 10.78 3306.81 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09372_/Y (INVx2_ASAP7_75t_R)
5 32.27 3339.08 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_10980_/Y (AND3x4_ASAP7_75t_R)
2 32.46 3371.54 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_10981_/Y (AND2x6_ASAP7_75t_R)
6 26.61 3398.15 v wire30552/Y (BUFx16f_ASAP7_75t_R)
3 117.06 3515.20 v wire30547/Y (BUFx16f_ASAP7_75t_R)
2 79.46 3594.66 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383202_/Y (AND2x2_ASAP7_75t_R)
13 30.10 3624.76 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383232_/Y (NAND2x2_ASAP7_75t_R)
37 104.44 3729.20 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383277_/Y (AO21x2_ASAP7_75t_R)
8 123.99 3853.19 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383285_/Y (NOR2x2_ASAP7_75t_R)
2 69.54 3922.74 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383289_/Y (AND2x2_ASAP7_75t_R)
2 70.43 3993.16 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_732263_/SN (HAxp5_ASAP7_75t_R)
1 35.94 4029.10 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_393224_/Y (XNOR2x1_ASAP7_75t_R)
1 33.88 4062.98 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_393228_/Y (AND5x2_ASAP7_75t_R)
1 22.63 4085.61 v wire18339/Y (BUFx12f_ASAP7_75t_R)
1 90.65 4176.26 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09348_/Y (AO221x2_ASAP7_75t_R)
1 78.25 4254.51 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09352_/Y (OR4x1_ASAP7_75t_R)
2 12.50 4267.01 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09353_/Y (INVx1_ASAP7_75t_R)
2 29.33 4296.34 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_13707_/Y (AND3x4_ASAP7_75t_R)
2 16.51 4312.85 ^ max_length17970/Y (BUFx12f_ASAP7_75t_R)
2 58.75 4371.60 ^ wire17968/Y (BUFx16f_ASAP7_75t_R)
4 69.67 4441.27 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383260_/Y (AND2x4_ASAP7_75t_R)
8 22.60 4463.87 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383290_/Y (NAND2x2_ASAP7_75t_R)
25 39.78 4503.65 v load_slew17553/Y (BUFx16f_ASAP7_75t_R)
8 52.97 4556.62 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_389614_/Y (OA21x2_ASAP7_75t_R)
15 27.29 4583.91 v max_length15743/Y (BUFx16f_ASAP7_75t_R)
6 44.22 4628.14 v wire15739/Y (BUFx16f_ASAP7_75t_R)
2 96.47 4724.61 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_732319_/CON (HAxp5_ASAP7_75t_R)
10 26.31 4750.92 ^ wire10637/Y (BUFx12f_ASAP7_75t_R)
9 28.31 4779.22 ^ wire10635/Y (BUFx12f_ASAP7_75t_R)
5 23.85 4803.08 ^ wire10634/Y (BUFx16f_ASAP7_75t_R)
3 49.02 4852.10 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_393150_/Y (INVx3_ASAP7_75t_R)
1 19.43 4871.53 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_732322_/CON (HAxp5_ASAP7_75t_R)
2 13.70 4885.23 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_732225_/Y (INVx1_ASAP7_75t_R)
2 54.56 4939.79 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_732324_/CON (HAxp5_ASAP7_75t_R)
2 57.06 4996.85 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_732324_/SN (HAxp5_ASAP7_75t_R)
1 39.36 5036.22 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_393230_/Y (XNOR2x1_ASAP7_75t_R)
1 29.47 5065.69 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_393234_/Y (AND5x2_ASAP7_75t_R)
1 38.32 5104.01 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09177_/Y (AO22x2_ASAP7_75t_R)
1 65.68 5169.69 v wire10120/Y (BUFx16f_ASAP7_75t_R)
1 85.75 5255.45 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09180_/Y (OR4x2_ASAP7_75t_R)
1 47.72 5303.17 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09181_/Y (OR4x2_ASAP7_75t_R)
1 14.50 5317.66 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09182_/Y (INVx1_ASAP7_75t_R)
3 20.96 5338.62 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09346_/Y (AO31x2_ASAP7_75t_R)
1 22.09 5360.71 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09357_/Y (AND2x2_ASAP7_75t_R)
3 22.17 5382.88 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09375_/Y (NAND3x2_ASAP7_75t_R)
2 44.87 5427.75 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_13855_/Y (NOR2x2_ASAP7_75t_R)
4 31.84 5459.59 ^ max_length10066/Y (BUFx16f_ASAP7_75t_R)
3 46.40 5505.98 ^ wire10064/Y (BUFx16f_ASAP7_75t_R)
1 74.29 5580.27 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_14394_/Y (AND2x2_ASAP7_75t_R)
1 5.61 5585.88 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/_065683_/Y (INVx1_ASAP7_75t_R)
2 61.87 5647.75 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/_065702_/Y (OR5x2_ASAP7_75t_R)
2 53.28 5701.03 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/_065722_/Y (NAND2x2_ASAP7_75t_R)
24 24.22 5725.25 ^ max_length8441/Y (BUFx16f_ASAP7_75t_R)
22 43.01 5768.26 ^ wire8439/Y (BUFx16f_ASAP7_75t_R)
19 49.84 5818.10 ^ load_slew8429/Y (BUFx16f_ASAP7_75t_R)
14 47.09 5865.20 ^ wire8426/Y (BUFx16f_ASAP7_75t_R)
11 48.21 5913.41 ^ max_length8425/Y (BUFx16f_ASAP7_75t_R)
10 58.85 5972.26 ^ wire8424/Y (BUFx16f_ASAP7_75t_R)
10 61.11 6033.37 ^ max_length8423/Y (BUFx12f_ASAP7_75t_R)
11 38.21 6071.58 ^ wire8422/Y (BUFx16f_ASAP7_75t_R)
25 51.58 6123.15 ^ wire8421/Y (BUFx16f_ASAP7_75t_R)
6 60.76 6183.91 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_1678_/Y (INVx11_ASAP7_75t_R)
24 21.32 6205.24 v max_length4569/Y (BUFx16f_ASAP7_75t_R)
11 62.98 6268.22 v wire4568/Y (BUFx16f_ASAP7_75t_R)
10 53.54 6321.76 v wire4567/Y (BUFx16f_ASAP7_75t_R)
12 73.47 6395.22 v wire4566/Y (BUFx16f_ASAP7_75t_R)
35 109.03 6504.25 v max_length4564/Y (BUFx16f_ASAP7_75t_R)
57 67.38 6571.63 v load_slew4563/Y (BUFx16f_ASAP7_75t_R)
1 95.45 6667.09 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_1885_/Y (NAND2x1_ASAP7_75t_R)
13 52.03 6719.12 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_1886_/Y (OA21x2_ASAP7_75t_R)
1 30.21 6749.33 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_3041_/Y (XNOR2x1_ASAP7_75t_R)
1 30.06 6779.38 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_3043_/Y (AND4x1_ASAP7_75t_R)
1 32.88 6812.26 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_3047_/Y (AND5x1_ASAP7_75t_R)
1 19.43 6831.69 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_3048_/Y (OR4x1_ASAP7_75t_R)
1 29.64 6861.33 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_3133_/Y (OA31x2_ASAP7_75t_R)
2.24 6863.57 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_3405_/D (DFFHQNx2_ASAP7_75t_R)
6863.57 data arrival time
8500.00 8500.00 clock fake_pll_clk (rise edge)
1445.94 9945.94 clock network delay (propagated)
-10.00 9935.94 clock uncertainty
0.00 9935.94 clock reconvergence pessimism
9935.94 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_3405_/CLK (DFFHQNx2_ASAP7_75t_R)
-10.95 9924.99 library setup time
9924.99 data required time
---------------------------------------------------------------
9924.99 data required time
-6863.57 data arrival time
---------------------------------------------------------------
3061.42 slack (MET)
Startpoint: serial_tl_0_bits_out_ready (input port clocked by clock_vir)
Endpoint: system/serial_tl_domain/_1190_
(rising edge-triggered flip-flop clocked by serial_tl_0_clock)
Path Group: serial_tl_0_clock
Path Type: max
Fanout Delay Time Description
---------------------------------------------------------------
0.00 0.00 clock clock_vir (rise edge)
1000.00 1000.00 clock network delay (ideal)
1700.00 2700.00 v input external delay
1 0.00 2700.00 v serial_tl_0_bits_out_ready (in)
1 12.09 2712.09 v input11/Y (BUFx2_ASAP7_75t_R)
1 21.58 2733.66 v system/serial_tl_domain/_0823_/Y (AND2x6_ASAP7_75t_R)
1 25.37 2759.03 v wire96183/Y (BUFx12f_ASAP7_75t_R)
13 259.71 3018.74 v system/serial_tl_domain/_1128_/SN (HAxp5_ASAP7_75t_R)
3 104.06 3122.80 v system/serial_tl_domain/_0882_/Y (OR3x4_ASAP7_75t_R)
1 13.63 3136.44 ^ system/serial_tl_domain/_0897_/Y (AOI211x1_ASAP7_75t_R)
1 22.32 3158.76 ^ system/serial_tl_domain/_0898_/Y (AO221x1_ASAP7_75t_R)
1 23.94 3182.70 ^ system/serial_tl_domain/_0899_/Y (OR4x2_ASAP7_75t_R)
1 20.19 3202.89 ^ system/serial_tl_domain/_0900_/Y (OA22x2_ASAP7_75t_R)
0.01 3202.90 ^ system/serial_tl_domain/_1190_/D (DFFHQNx2_ASAP7_75t_R)
3202.90 data arrival time
8500.00 8500.00 clock serial_tl_0_clock (rise edge)
99.58 8599.58 clock network delay (propagated)
-10.00 8589.58 clock uncertainty
0.00 8589.58 clock reconvergence pessimism
8589.58 ^ system/serial_tl_domain/_1190_/CLK (DFFHQNx2_ASAP7_75t_R)
-5.33 8584.25 library setup time
8584.25 data required time
---------------------------------------------------------------
8584.25 data required time
-3202.90 data arrival time
---------------------------------------------------------------
5381.35 slack (MET)
```
### oharboe
To get this to build in Yosys, I had to mock fake_pll_clk:
https://github.com/The-OpenROAD-Project/megaboom/blob/931c2a882510bf5735dbf5efab1a8c474f838c49/mock/ChipTop.sv#L31
Whereas Chipyard has this clock coming out of a PLL:
https://github.com/The-OpenROAD-Project/megaboom/blob/931c2a882510bf5735dbf5efab1a8c474f838c49/rtl/ChipTop.sv#L150
I don't know what the relationships are between these clocks, this is my first cut .sdc file that I used:
https://github.com/The-OpenROAD-Project/megaboom/blob/main/constraints-chiptop.sdc
### oharboe
I've reached out to Chipyard to get some help with the .sdc file for the clocks: https://groups.google.com/g/chipyard/c/PzVcnnqRwf8/m/t1pIDPnuAwAJ
### oharboe
Failed in global routing, ca. 7000 seconds.
`make macro_place_issue` reproducible case for mpl2: https://drive.google.com/file/d/1w_vIUNtWp7dBntP9i7WGEkgtGhTRD6M_/view?usp=sharing
I suppose I could try to flatten the design for the two macros with contention, but if macro placement can't place these two bigger macros, what are the chances it can place many smaller macros(there are SRAMs inside the branch predictor and the data cache that have all the congestion on top)?
Intentionally, BranchPredictor has all the pins on the left side. This is to break the rotational and mirroring symmetry such that mpl2 can try different directions to find one that is better.
This is odd... Why is the macro rotated R180? That puts the pins on the right hand side... I would have thought, looking at the floorplan, that having the pins on the left side was better, given the placement...
### maliberty
You can zoom in with the mouse wheel in the CTS view. If you do so on the odd branch on the right you can select the end points and see what they are. That would be helpful.
The setup paths with tons of hold buffers are quite odd. I suspect an SDC issue.
You might lower the placement density slightly to see if that helps with congestion.
A test case for the flipping is needed to say much about it. Perhaps the connections go to pins on the right?
### oharboe
Broke out #4513 and #4512 for further investigation
### oharboe
So, I think I understand more or less what is going on.
The Verilog is not the way I want it yet. It contains a fake PLL that is controlled via the TileLink interface at the top level that multiplies the top level clock to the core frequency. This PLL is set up out of bounds of a single core.
https://github.com/ucb-bar/chipyard/blob/c9fa23edf049f35f9b8e6291b0e2b82b1056540b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala#L12
|