diff --git a/gh_discussions/Bug/3217.md b/gh_discussions/Bug/3217.md deleted file mode 100644 index 32f5ded31b131f34b006b9cce40029dd2a31167b..0000000000000000000000000000000000000000 --- a/gh_discussions/Bug/3217.md +++ /dev/null @@ -1,25 +0,0 @@ -# DRC error in detailed routing - Short - -Tool: Detailed Routing - -Subcategory: Routing violation - -## Conversation - -### oharboe -What is detailed routing trying to do here? The grey area is a macro. - -Is the detailed route simply spilling onto the macro because it can't find a valid place to put the wire? - -![image](https://user-images.githubusercontent.com/2798822/233313803-be73a31c-255b-4857-acb3-d304cb37db11.png) - - -![image](https://user-images.githubusercontent.com/2798822/233314427-9f2f4378-db70-4f2f-bc54-c23118c5e2b9.png) - - -### oharboe -Since no-one answers, I'm thinking I guessed right :-) - -### maliberty -Most likely (assuming the layers are blocked and this isn't just available resource). - diff --git a/gh_discussions/Bug/3314.md b/gh_discussions/Bug/3314.md deleted file mode 100644 index 661ab6942998ed988045ceee03d8310c41ccdbfc..0000000000000000000000000000000000000000 --- a/gh_discussions/Bug/3314.md +++ /dev/null @@ -1,138 +0,0 @@ -# [WARNING STA-0139] ... 63.3687 is not a float. - -Tool: OpenSTA - -Subcategory: Locale issue - -## Conversation - -### oharboe -I get a lot of these warnings when I run `make gui_final` - -This is with the latest ORFS. - -What are they? - -``` -$ make DESIGN_CONFIG=designs/asap7/mock-array-big/Element/config.mk place -``` - - -``` -[WARNING STA-0139] /home/oyvind/OpenROAD-flow-scripts/flow/platforms/asap7/lib/asap7sc7p5t_AO_RVT_TT_nldm_211120.lib.gz line 397, 63.3687 is not a float. -[WARNING STA-0139] /home/oyvind/OpenROAD-flow-scripts/flow/platforms/asap7/lib/asap7sc7p5t_AO_RVT_TT_nldm_211120.lib.gz line 397, 79.0805 is not a float. -[WARNING STA-0139] /home/oyvind/OpenROAD-flow-scripts/flow/platforms/asap7/lib/asap7sc7p5t_AO_RVT_TT_nldm_211120.lib.gz line 397, 106.935 is not a float. -[WARNING STA-0139] /home/oyvind/OpenROAD-flow-scripts/flow/platforms/asap7/lib/asap7sc7p5t_AO_RVT_TT_nldm_211120.lib.gz line 397, 156.622 is not a float. -[WARNING STA-0139] /home/oyvind/OpenROAD-flow-scripts/flow/platforms/asap7/lib/asap7sc7p5t_AO_RVT_TT_nldm_211120.lib.gz line 397, 248.596 is not a float. -[WARNING STA-0139] /home/oyvind/OpenROAD-flow-scripts/flow/platforms/asap7/lib/asap7sc7p5t_AO_RVT_TT_nldm_211120.lib.gz line 397, 432.982 is not a float. -[WARNING STA-0139] /home/oyvind/OpenROAD-flow-scripts/flow/platforms/asap7/lib/asap7sc7p5t_AO_RVT_TT_nldm_211120.lib.gz line 406, 0.36 is not a float. -[WARNING STA-0139] /home/oyvind/OpenROAD-flow-scripts/flow/platforms/asap7/lib/asap7sc7p5t_AO_RVT_TT_nldm_211120.lib.gz line 406, 0.72 is not a float. -[WARNING STA-0139] /home/oyvind/OpenROAD-flow-scripts/flow/platforms/asap7/lib/asap7sc7p5t_AO_RVT_TT_nldm_211120.lib.gz line 406, 1.44 is not a float. -[WARNING STA-0139] /home/oyvind/OpenROAD-flow-scripts/flow/platforms/asap7/lib/asap7sc7p5t_AO_RVT_TT_nldm_211120.lib.gz line 406, 2.88 is not a float. -[WARNING STA-0139] /home/oyvind/OpenROAD-flow-scripts/flow/platforms/asap7/lib/asap7sc7p5t_AO_RVT_TT_nldm_211120.lib.gz line 406, 5.76 is not a float. -[WARNING STA-0139] /home/oyvind/OpenROAD-flow-scripts/flow/platforms/asap7/lib/asap7sc7p5t_AO_RVT_TT_nldm_211120.lib.gz line 406, 11.52 is not a float. -[WARNING STA-0139] /home/oyvind/OpenROAD-flow-scripts/flow/platforms/asap7/lib/asap7sc7p5t_AO_RVT_TT_nldm_211120.lib.gz line 406, 23.04 is not a float. -[WARNING STA-0139] /home/oyvind/OpenROAD-flow-scripts/flow/platforms/asap7/lib/asap7sc7p5t_AO_RVT_TT_nldm_211120.lib.gz line 415, 12.8576 is not a float. -[WARNING STA-0139] /home/oyvind/OpenROAD-flow-scripts/flow/platforms/asap7/lib/asap7sc7p5t_AO_RVT_TT_nldm_211120.lib.gz line 415, 15.7364 is not a float. -[WARNING STA-0139] /home/oyvind/OpenROAD-flow-scripts/flow/platforms/asap7/lib/asap7sc7p5t_AO_RVT_TT_nldm_211120.lib.gz line 415, 21.3969 is not a float. -[WARNING STA-0139] /home/oyvind/OpenROAD-flow-scripts/flow/platforms/asap7/lib/asap7sc7p5t_AO_RVT_TT_nldm_211120.lib.gz line 415, 32.5931 is not a float. -``` - -### vijayank88 -@oharboe -I ran with latest commit and not able to get similar logs. - -### maliberty -The report says 'make place' and 'make gui_final' which are not a compatible pair. I can't reproduce this either even running all the way through. - -### oharboe -``` -rm -rf results/ -make DESIGN_CONFIG=designs/asap7/mock-array-big/Element/config.mk place -make DESIGN_CONFIG=designs/asap7/mock-array-big/Element/config.mk gui_place -``` - -``` -$ make DESIGN_CONFIG=designs/asap7/mock-array-big/Element/config.mk gui_place -[INFO][FLOW] Using platform directory ./platforms/asap7 -[INFO-FLOW] ASU ASAP7 - version 2 -Default PVT selection: BC -ODB_FILE=./results/asap7/mock-array-big_Element/base/3_place.odb /home/oyvind/OpenROAD-flow-scripts/tools/install/OpenROAD/bin/openroad -gui ./scripts/gui.tcl -Warning: Ignoring XDG_SESSION_TYPE=wayland on Gnome. Use QT_QPA_PLATFORM=wayland to run on Wayland anyway. -This plugin does not support propagateSizeHints() -OpenROAD v2.0-8114-gaa1f8060d -This program is licensed under the BSD-3 license. See the LICENSE file for details. -Components of this program may be licensed under more restrictive licenses which must be honored. -[WARNING STA-0139] ./platforms/asap7/lib/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz line 82, 0.72 is not a float. -[WARNING STA-0139] ./platforms/asap7/lib/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz line 82, 1.44 is not a float. -[WARNING STA-0139] ./platforms/asap7/lib/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz line 82, 2.88 is not a float. -[WARNING STA-0139] ./platforms/asap7/lib/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz line 82, 5.76 is not a float. -[WARNING STA-0139] ./platforms/asap7/lib/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz line 82, 11.52 is not a float. -[WARNING STA-0139] ./platforms/asap7/lib/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz line 82, 23.04 is not a float. -[WARNING STA-0139] ./platforms/asap7/lib/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz line 82, 46.08 is not a float. -[WARNING STA-0139] ./platforms/asap7/lib/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz line 96, 0.72 is not a float. -[WARNING STA-0139] ./platforms/asap7/lib/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz line 96, 1.44 is not a float. -[WARNING STA-0139] ./platforms/asap7/lib/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz line 96, 2.88 is not a float. -[WARNING STA-0139] ./platforms/asap7/lib/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz line 96, 5.76 is not a float. -``` - - -### oharboe -@maliberty Aha! This is a locale issue. In their wisdom a hundred years ago, Norwegians decided to use "," to separate integers from fractions in floating point... So "12.34" is not a valid float in Norwegian locale, rather "12,34" is. - -The evidence that this is the problem is that setting `LC_NUMERIC="en_GB.UTF-8"` fixes the problem. - -In this case, the locale is decided by the format that is being parsed, it is not a human readable/writeable number. - -Let's see if this works: https://github.com/Pinata-Consulting/OpenSTA/tree/lock-down-strtof-locale - -Yep :-) - -This also explains why we don't see this when we run from docker, only local install. - -### maliberty -Brazil has the same issue. https://github.com/The-OpenROAD-Project/OpenROAD/blob/6920ac530b6959f742e75b7f55062b1642730b14/src/Main.cc#L217 attempts to solve this. Do none of the locales exist on your systems? - -### maliberty -Would you try your strtof check along with getlocale after these various points to try to see what's going on. I think this works in Brazil so I'm trying to understand what's different here. @luis201420 any insights? - - -### maliberty -Perhaps it relates to LC_NUMERIC or another. Can you try unsetting all LC_* but LC_ALL in your environment to see if that matters? - -### oharboe -@maliberty @luis201420 With this change, I no longer get the warnings. - -This is just a quick hack, I think it would be better if someone who knows what is going on and are aware of other edgecases articulates the pull request :-) - -``` -diff --git a/src/gui/src/gui.cpp b/src/gui/src/gui.cpp -index 355aa6842..7d79d99a3 100644 ---- a/src/gui/src/gui.cpp -+++ b/src/gui/src/gui.cpp -@@ -1141,6 +1141,16 @@ int startGui(int& argc, - } - main_window->show(); - -+ // This avoids problems with locale setting dependent -+ // C functions like strtod (e.g. 0.5 vs 0,5). -+ std::array locales = {"en_US.UTF-8", "C.UTF-8", "C"}; -+ for (auto locale : locales) { -+ if (std::setlocale(LC_ALL, locale) != nullptr) { -+ break; -+ } -+ } -+ -+ - gui->setLogger(open_road->getLogger()); - - main_window->setDatabase(open_road->getDb()); -``` - - -### maliberty -@luis201420 will you look at this since you can reproduce it - -### oharboe -I guess this has been identified as a bug in OpenROAD, given that there are frameworks that set the locale after OpenROAD has set the locale. - diff --git a/gh_discussions/Bug/3362.md b/gh_discussions/Bug/3362.md deleted file mode 100644 index 999c80b5696d575a6e7bf0950f18b10e32faff26..0000000000000000000000000000000000000000 --- a/gh_discussions/Bug/3362.md +++ /dev/null @@ -1,60 +0,0 @@ -# Where does "Error: tdms_place.tcl, 35 cannot create std::vector larger than max_size()" - -Tool: Global Placement - -Subcategory: Memory allocation error - -## Conversation - -### oharboe -I want to debug it, but I searched the code and couldn't find this error message in the source. - -``` -[INFO GPL-0003] SiteSize: 54 270 -[INFO GPL-0004] CoreAreaLxLy: 2160 2160 -[INFO GPL-0005] CoreAreaUxUy: 25922160 25922160 -Error: tdms_place.tcl, 35 cannot create std::vector larger than max_size() -Command exited with non-zero status 1 -``` - - -### maliberty -My guess is this is an STL exception and not in the OR code. In gdb try 'catch throw' to see when it is being thrown. - -### oharboe -This is odd... 48000*96000 = 4608000000. Ah. overflow. - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/ca384a53-04da-42fd-9039-014b3bdd89f9) - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/a0156546-48aa-4c6c-84a1-ee9b89647226) - - -``` -D$ git diff -diff --git a/src/gpl/src/placerBase.cpp b/src/gpl/src/placerBase.cpp -index 30ff82771..4f2c10b4e 100644 ---- a/src/gpl/src/placerBase.cpp -+++ b/src/gpl/src/placerBase.cpp -@@ -1002,8 +1002,8 @@ void PlacerBase::initInstsForUnusableSites() - { - dbSet rows = db_->getChip()->getBlock()->getRows(); - -- int siteCountX = (die_.coreUx() - die_.coreLx()) / siteSizeX_; -- int siteCountY = (die_.coreUy() - die_.coreLy()) / siteSizeY_; -+ long siteCountX = (die_.coreUx() - die_.coreLx()) / siteSizeX_; -+ long siteCountY = (die_.coreUy() - die_.coreLy()) / siteSizeY_; - - enum PlaceInfo - { -``` - -gives me: - -``` -[INFO GPL-0002] DBU: 1000 -[INFO GPL-0003] SiteSize: 54 270 -[INFO GPL-0004] CoreAreaLxLy: 2160 2160 -[INFO GPL-0005] CoreAreaUxUy: 25922160 25922160 -Error: out of memory. -``` - diff --git a/gh_discussions/Bug/3589.md b/gh_discussions/Bug/3589.md deleted file mode 100644 index 10bee36814137e7deb7aa8ad68acd3ca0f4043aa..0000000000000000000000000000000000000000 --- a/gh_discussions/Bug/3589.md +++ /dev/null @@ -1,26 +0,0 @@ -# how to fix metal spacing DRCs - -Tool: Detailed Routing - -Subcategory: DRC violation - -## Conversation - -### gkamendje -After 64 iterations DRT stopped on my design a generated a DRC report. It turns out that most of the DRC are related to METAL1 spacing (with net VSS) and Metal SpacingTableTw. The design is not very congested so I wonder why the tool could not fix these rules. Could it be that I am missing something here (maybe something in my platform definition)? Is there a way to fix these violations? -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/56942214/af73acfe-92fb-4590-baaf-31be8548e95e) - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/56942214/4ed7f795-fef7-4d49-9f78-76b85c9cae37) - - - -### maliberty -Can you provide a test case? - -### maliberty -You have very wide METAL1 power stripes: - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/761514/ec146977-bcb3-4725-8140-4bef3c0137ef) - -The pin is less than the min space (0.19 < 0.23) from the stripe so there is always going to be a DRC error here. You need to adjust your PDN definition to be resolve this. - diff --git a/gh_discussions/Bug/3597.md b/gh_discussions/Bug/3597.md deleted file mode 100644 index c1ccf33853bf2a0bdc58661101c741e07f4a0591..0000000000000000000000000000000000000000 --- a/gh_discussions/Bug/3597.md +++ /dev/null @@ -1,53 +0,0 @@ -# Detailed routing loops instead of straight wire... - -Tool: Detailed Routing - -Subcategory: Routing pattern anomaly - -## Conversation - -### oharboe -I've been fixing some problems in mock-array in positioning of macros and pins not being aligned and now things are working well. - -However, I found this curious thing when inspecting, a detailed routing loop :-) - -I don't see any reason why a horizontal wire wouldn't work here... - -Any ideas or insights? - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/381a3158-6635-452c-a270-247df28a6dae) - - -The above can be found if creating a `flow/settings.mk` file: - -``` -export DESIGN_CONFIG?=designs/asap7/mock-array/config.mk -export MOCK_ARRAY_DATAWIDTH?=8 -export MOCK_ARRAY_TABLE?=8 8 4 4 5 5 -export MOCK_ARRAY_SCALE?=80 -``` - -and running `make verilog` and `make` - - -Various interesting things can be seen in detailed routing: - -- almost all the wires are vertical/horizontal between "Element" macros. The loop above is untypical, usually it's just a slight horizontal/vertical deviation. -- there are hold cells in the middle to the right - - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/e9bca2da-5e41-4ee6-b279-e7ca375bb26a) - - - -Hold cells have to be placed *outside* to the right of the array, hence many non-vertical vertical wires between those two elements. - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/3a17be46-8604-498c-901f-ce375cbed5cc) - - -### maliberty -@osamahammad21 any thoughts on the loop? - -### oharboe -A feature request filed: https://github.com/The-OpenROAD-Project/OpenROAD/issues/3634 - diff --git a/gh_discussions/Bug/4163.md b/gh_discussions/Bug/4163.md deleted file mode 100644 index 7004b40c0477650eabb7abb6c54042c3660f86a1..0000000000000000000000000000000000000000 --- a/gh_discussions/Bug/4163.md +++ /dev/null @@ -1,29 +0,0 @@ -# [WARNING GRT-0350] Missing route to pin iregister_read/io_bypass_1_bits_data[0]. - -Tool: Global Routing - -Subcategory: Parasitics estimation issue - -## Conversation - -### oharboe -This is for the top level of MegaBoom that I'm playing around with. - -Is this warning telling me that it can't find a route for the buffer tree for the pin in the warning? - -It looks like this buffer tree is going from the iregister_read macro to the ALUExeUnit, which traverses Rob(reorder buffer), rename stage and the memory issue unit. The mpl2 macro placement is unfortunate here... - - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/e3c6b965-bf83-403c-9dd5-70413735a8ca) - - - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/c2a76f06-f286-4b5a-8bc7-2fc0219bc9f8) - - -### maliberty -@eder-matheus please respond - -### eder-matheus -@oharboe @maliberty This warning is related to the estimate_parasitics using global route parasitics. It usually happens when a routing topology is not correctly translated to the parasitics estimation structures. I will look into the test case and fix the cause of this bug. - diff --git a/gh_discussions/Bug/4845.md b/gh_discussions/Bug/4845.md deleted file mode 100644 index ba6bca413b84e27bb9a914674a9c35c84c94ed1e..0000000000000000000000000000000000000000 --- a/gh_discussions/Bug/4845.md +++ /dev/null @@ -1,34 +0,0 @@ -# Is [read_def -floorplan_initialize ] expected to unset [set_max_transition] and [set_max_capacitance] from sdc file? - -Tool: Initialize Floorplan - -Subcategory: Unexpected behavior - -## Conversation - -### b62833 -Before I file a bug, I want to make sure this is unexpected behavior. - -In my sdc file I do a -``` - -set_max_transition [exp $clk_period * 0.20] [current_design] -set_max_capacitance 30 [current_design] -``` - -and then read a floorplan by setting FLOORPLAN_DEF. - -When I run through floorplanning, 2_floorplan.sdc doesn't have those commands. I've narrowed it down to floorplan.tcl's `read_def -floorplan_initialize` that's removing these. Max transition and max capacitance can't be set in DEF if I remember correctly, so this is unexpected. Is this the desired tool behavior? - - - -### maliberty -I would consider it unexpected so go ahead and open an issue with a test case - -### b62833 -Over the weekend I upgraded to OpenROAD version 2.0-13286-gebcc5196e and it works now. - -It was broken in the version v2.0-11493-gaddecc2bd that I'd been using before. - -We're good now. - diff --git a/gh_discussions/Bug/5333.md b/gh_discussions/Bug/5333.md deleted file mode 100644 index 8df3fefa2336011e0f57447ed83205fc8161ba75..0000000000000000000000000000000000000000 --- a/gh_discussions/Bug/5333.md +++ /dev/null @@ -1,48 +0,0 @@ -# pdgen remove stripes with [WARNING PDN-0200] Removing floating shape: - -Tool: Power Distribution Network Generator - -Subcategory: Power distribution network issue - -## Conversation - -### titan73 -Based on the example at the bottom of https://openroad.readthedocs.io/en/latest/main/src/pdn/README.html. - -I did the following floorplan with the .def containing the power pins: - - read_def -floorplan_initialize floor.def - set fp_area [ord::get_die_area] - initialize_floorplan -die_area $fp_area -core_area $fp_area -site CORECUBRICK - - add_global_connection -net VDDD -pin_pattern {^VDDD$} -power - add_global_connection -net GNDD -pin_pattern {^GNDD$} -ground - - set_voltage_domain -power VDDD -ground GNDD - - define_pdn_grid -name "Core" - add_pdn_ring -grid "Core" -layers {metal4B alucap} -widths 5.0 -spacings 2.0 -core_offsets 4.5 -connect_to_pads - - add_pdn_stripe -followpins -layer metal1 -extend_to_core_ring - - add_pdn_stripe -layer metal4B -width 0.48 -pitch 56.0 -offset 2.0 -extend_to_core_ring - add_pdn_stripe -layer alucap -width 1.40 -pitch 40.0 -offset 2.0 -extend_to_core_ring - - add_pdn_connect -layers {metal4B alucap} - add_pdn_connect -layers {alucap metal4B} - - pdngen - -The sroutes and the ring are created but not the stripes and I get the the warnings: - - [WARNING PDN-0200] Removing floating shape: GNDD (1.7600, -9.5000) - (2.2400, 821.3000) on metal4B - [WARNING PDN-0200] Removing floating shape: VDDD (29.7600, -16.5000) - (30.2400, 828.3000) on metal4B - -Is there something more to do to connect these shapes? - -### titan73 -Also note that the related power pins imported the from .def are removed. - -### maliberty -Can you provide a test case? Its hard to say much from just the output - diff --git a/gh_discussions/Build/1951.md b/gh_discussions/Build/1951.md deleted file mode 100644 index 9b75f1978968c794a2312d447d1e4e2b28094859..0000000000000000000000000000000000000000 --- a/gh_discussions/Build/1951.md +++ /dev/null @@ -1,25 +0,0 @@ -# Is it possible to generate a static binary of OpenROAD? - -Subcategory: Static binary generation - -## Conversation - -### TiagoAFontana -Hi all, I am trying to execute the OpenROAD in a cluster machine. However, in this machine, I am not able to install the dependencies to compile the OpenROAD or even use the docker image to run the OpenROAD. - -I was wondering if it is possible to set a cmake flag to generate a static binary (without any dependencies) for the OpenROAD project. With this, I will be able to run this binary on every machine that I need. - -Does someone know how to do this? - -### vijayank88 -@vvbandeira Any suggestion? - -### QuantamHD -Bazel rules hdl supports fully static builds of openroad. - -Just download bazel, git clone https://github.com/hdl/bazel_rules_hdl - -And run bazel build @org_theopenroadproject//:openroad in the git repo. - -It also statically builds the entire dependency chain of openroad from source. - diff --git a/gh_discussions/Build/2330.md b/gh_discussions/Build/2330.md deleted file mode 100644 index a9ae083555cb9fc41bb20de92c8a1d5ac8321ed7..0000000000000000000000000000000000000000 --- a/gh_discussions/Build/2330.md +++ /dev/null @@ -1,50 +0,0 @@ -# Compilation Error - -Subcategory: Compilation error - -## Conversation - -### gudeh -Hey guys! I am getting the following compilation error: - -> [100%] Linking CXX executable openroad -> cd /home/gudeh/Documents/OpenROAD-flow-scripts/tools/OpenROAD/build/src && /usr/local/bin/cmake -E cmake_link_script CMakeFiles/openroad.dir/link.txt --verbose=1 -> /usr/bin/c++ -O3 -DNDEBUG -Wl,--export-dynamic -rdynamic CMakeFiles/openroad.dir/Design.cc.o CMakeFiles/openroad.dir/Tech.cc.o CMakeFiles/openroad.dir/OpenRoad.cc.o CMakeFiles/openroad.dir/Main.cc.o -o openroad ifp/src/ifp.a openroad_swig.a gpl/gpl.a dpl/dpl.a dpo/dpo.a fin/fin.a rsz/src/rsz.a ppl/ppl.a stt/stt.a dbSta/src/dbSta.a ../../src/sta/app/libOpenSTA.a odb/src/db/libodb.a odb/src/swig/tcl/odbtcl.a rcx/src/rcx.a rmp/src/rmp.a cts/src/cts.a grt/grt.a tap/src/tap.a gui/gui.a drt/drt.a dst/dst.a mpl/mpl.a mpl2/mpl2.a psm/src/psm.a ant/src/ant.a par/par.a utl/utl.a pdn/src/pdn.a ../third-party/abc/libabc.a /usr/lib/x86_64-linux-gnu/libtcl.so -lpthread /usr/lib/x86_64-linux-gnu/libtclreadline.so /usr/lib/x86_64-linux-gnu/libz.so _openroad_swig_py.a odb/src/swig/python/_odbpy.a ifp/src/_ifp_py.a /usr/lib/x86_64-linux-gnu/librt.so ppl/src/munkres/libMunkres.a -lm -ldl -lrt rsz/src/rsz.a grt/grt.a ant/src/ant.a grt/grt.a ant/src/ant.a dpl/dpl.a grt/src/fastroute/libFastRoute4.1.a stt/stt.a sta/sta_swig.a /usr/local/lib/libboost_serialization.a /usr/local/lib/libboost_system.a /usr/local/lib/libboost_thread.a /usr/lib/gcc/x86_64-linux-gnu/9/libgomp.so /usr/lib/x86_64-linux-gnu/libpthread.so /usr/local/lib/libboost_serialization.a mpl/src/ParquetFP/libParquetFP.a par/src/MLPart/libMLPart.a dbSta/src/dbSta.a gui/gui.a /usr/lib/x86_64-linux-gnu/libQt5Widgets.so.5.12.8 /usr/lib/x86_64-linux-gnu/libQt5Gui.so.5.12.8 /usr/lib/x86_64-linux-gnu/libQt5Core.so.5.12.8 ../../src/sta/app/libOpenSTA.a odb/src/db/libodb.a odb/src/defout/libdefout.a odb/src/lefout/liblefout.a odb/src/tm/libtm.a /usr/lib/x86_64-linux-gnu/libtcl.so odb/src/cdl/libcdl.a odb/src/swig/common/libodb_swig_common.a odb/src/defin/libdefin.a odb/src/def/libdef.a odb/src/def/libdefzlib.a odb/src/lefin/liblefin.a odb/src/zutil/libzutil.a utl/utl.a /usr/local/lib/libspdlog.a -lpthread odb/src/lef/liblef.a odb/src/lef/liblefzlib.a /usr/lib/x86_64-linux-gnu/libz.so /usr/lib/x86_64-linux-gnu/libpython3.8.so -> /usr/bin/ld: drt/drt.a(TritonRoute.cpp.o): in function \`boost::archive::basic_binary_iarchive::init()': -> TritonRoute.cpp:(.text._ZN5boost7archive21basic_binary_iarchiveIN2fr10frIArchiveEE4initEv[_ZN5boost7archive21basic_binary_iarchiveIN2fr10frIArchiveEE4initEv]+0xc4): undefined reference to `boost::archive::detail::basic_iarchive::set_library_version(boost::archive::library_version_type)' -> collect2: error: ld returned 1 exit status -> make[2]: *** [src/CMakeFiles/openroad.dir/build.make:210: src/openroad] Error 1 -> make[2]: Leaving directory '/home/gudeh/Documents/OpenROAD-flow-scripts/tools/OpenROAD/build' -> make[1]: *** [CMakeFiles/Makefile2:449: src/CMakeFiles/openroad.dir/all] Error 2 -> make[1]: *** Waiting for unfinished jobs.... -> [100%] Linking CXX executable trTest -> cd /home/gudeh/Documents/OpenROAD-flow-scripts/tools/OpenROAD/build/src/drt && /usr/local/bin/cmake -E cmake_link_script CMakeFiles/trTest.dir/link.txt --verbose=1 -> /usr/bin/c++ -O3 -DNDEBUG CMakeFiles/trTest.dir/test/gcTest.cpp.o CMakeFiles/trTest.dir/test/fixture.cpp.o CMakeFiles/trTest.dir/test/stubs.cpp.o CMakeFiles/trTest.dir/__/gui/src/stub.cpp.o -o trTest drt.a ../odb/src/db/libodb.a ../stt/stt.a ../dst/dst.a ../sta/sta_swig.a /usr/local/lib/libboost_serialization.a /usr/local/lib/libboost_system.a /usr/local/lib/libboost_thread.a ../dbSta/src/dbSta.a ../gui/gui.a ../odb/src/db/libodb.a ../odb/src/cdl/libcdl.a ../odb/src/defin/libdefin.a ../odb/src/def/libdef.a ../odb/src/def/libdefzlib.a ../odb/src/defout/libdefout.a ../odb/src/lefin/liblefin.a ../odb/src/lef/liblef.a ../odb/src/lef/liblefzlib.a ../odb/src/lefout/liblefout.a ../odb/src/tm/libtm.a ../odb/src/zutil/libzutil.a /usr/lib/x86_64-linux-gnu/libtcl.so /usr/lib/x86_64-linux-gnu/libQt5Widgets.so.5.12.8 /usr/lib/x86_64-linux-gnu/libQt5Gui.so.5.12.8 /usr/lib/x86_64-linux-gnu/libQt5Core.so.5.12.8 ../../../src/sta/app/libOpenSTA.a ../utl/utl.a /usr/local/lib/libspdlog.a -lpthread /usr/lib/gcc/x86_64-linux-gnu/9/libgomp.so /usr/lib/x86_64-linux-gnu/libpthread.so /usr/local/lib/libboost_serialization.a /usr/lib/x86_64-linux-gnu/libz.so -> make[2]: Leaving directory '/home/gudeh/Documents/OpenROAD-flow-scripts/tools/OpenROAD/build' -> [100%] Built target trTest -> make[1]: Leaving directory '/home/gudeh/Documents/OpenROAD-flow-scripts/tools/OpenROAD/build' -> make: *** [Makefile:133: all] Error 2 - -The error I pasted here is from a clean clone from the flow repository. I did the following commands to get to this error: - -> git clone --recursive https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts -> cd OpenROAD-flow-scripts -> sudo ./tools/OpenROAD/etc/DependencyInstaller.sh -dev -> ./build_openroad.sh --local - -I noticed that if I run DepdencyInstaller multiple times it actually updates and compile Boost everytime. Not sure how to proceed, any help is welcome. - -### maliberty -What OS and what compiler? - -### maliberty -The log unfortunately doesn't have the boost version so I just added print that in the OR master branch. What version of boost do you have installed? - -### gudeh -Hi everyone, I was able to solve the issue by manually updating Boost. I used the links from [this stackoverflow page](https://stackoverflow.com/questions/2829523/upgrading-boost-version) and set the "-prefix=" with the same location my Boost was already installed. Also, I had to clean my previous build from OR. - -It seems that for some reason the DependencyInstaller didn't fetch the correct Boost version to upgrade to. - -### maliberty -@vvbandeira any idea about " for some reason the DependencyInstaller didn't fetch the correct Boost version to upgrade to."? - diff --git a/gh_discussions/Build/2342.md b/gh_discussions/Build/2342.md deleted file mode 100644 index 077bfac0420680bbcd99a6ce41b5f531e6d41a64..0000000000000000000000000000000000000000 --- a/gh_discussions/Build/2342.md +++ /dev/null @@ -1,51 +0,0 @@ -# Apple clang 14.0.0 (Xcode 14.0.1) M1 coredumps compiling abc .c files - -Tool: ABC - -Subcategory: Compiler crash - -## Conversation - -### stefanottili -Hi Folks, - -just a heads up for anybody using an Apple M1 with the most recent Xcode 14.0.1 - -Apple clang 14.0.0 randomly coredumps compiling abc .c files. But not deterministically, restarting ./build_openroad.sh will eventually compile some of them til it finally always coredumps compiling extraUtilMisc.c. - -I was able to compile OpenROAD on this machine before, but not with the latest and greatest Xcode. - -I'm curious whether there are other M1/Xcode users out there with similar experience. - -Stefan - -gmake[2]: Entering directory '/Users/user/OpenROAD-flow-scripts/tools/OpenROAD/build' -[ 0%] Building CXX object third-party/abc/CMakeFiles/libabc.dir/src/misc/extra/extraUtilMisc.c.o -cd /Users/user/OpenROAD-flow-scripts/tools/OpenROAD/build/third-party/abc && /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/bin/c++ -I/Users/user/OpenROAD-flow-scripts/tools/OpenROAD/third-party/abc/src -O3 -DNDEBUG -arch arm64 -isysroot /Applications/Xcode.app/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/MacOSX12.3.sdk -Wall -Wno-array-bounds -Wno-nonnull -Wno-unused-variable -Wno-unused-function -Wno-write-strings -Wno-sign-compare -Wno-deprecated -Wno-c++11-narrowing -Wno-register -Wno-format -Wno-reserved-user-defined-literal -DABC_USE_STDINT_H=1 -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -DABC_USE_CUDD=1 -DABC_USE_PTHREADS -Wno-unused-but-set-variable -std=c++17 -MD -MT third-party/abc/CMakeFiles/libabc.dir/src/misc/extra/extraUtilMisc.c.o -MF CMakeFiles/libabc.dir/src/misc/extra/extraUtilMisc.c.o.d -o CMakeFiles/libabc.dir/src/misc/extra/extraUtilMisc.c.o -c /Users/user/OpenROAD-flow-scripts/tools/OpenROAD/third-party/abc/src/misc/extra/extraUtilMisc.c -clang: error: unable to execute command: Segmentation fault: 11 -clang: error: clang frontend command failed due to signal (use -v to see invocation) -Apple clang version 14.0.0 (clang-1400.0.29.102) -Target: arm64-apple-darwin21.6.0 -Thread model: posix -InstalledDir: /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/bin - - -### stefanottili -downgrading the command line tools to 13.4 allows to build the project - -### stefanottili -Here's some feedback from https://developer.apple.com/forums/thread/717259 - -> It only happens with optimized code. An alternative workaround for building openroad is to patch the abc cmake file to include -g - -third-party/CMakeLists.txt @@ -46,6 +46,10 @@ if (NOT USE_SYSTEM_ABC) -readline is not needed since we call abc from c++ -set(READLINE_FOUND FALSE) -+# apple clang 14.0.0 seg faults on abc without -g +add_compile_options( -$<$:-g> -+) add_subdirectory(abc) -endif() - -### stefanottili -clang-1400.0.29.202 as part of Xcode 14.1.0 compiles OpenRoad without issues - diff --git a/gh_discussions/Build/2952.md b/gh_discussions/Build/2952.md deleted file mode 100644 index 03f176d96f06e3e026e7d093473ff19728ee9339..0000000000000000000000000000000000000000 --- a/gh_discussions/Build/2952.md +++ /dev/null @@ -1,104 +0,0 @@ -# Cannot build with CUDA - -Tool: Verilog to DB - -Subcategory: Compiler version mismatch - -## Conversation - -### yathAg -I am trying to build Openroad with cmake .. -DGPU=true and I get the following output - -``` --- GPU is enabled --- CUDA is found --- The CUDA compiler identification is NVIDIA 10.1.243 --- Detecting CUDA compiler ABI info --- Detecting CUDA compiler ABI info - done --- Check for working CUDA compiler: /usr/bin/nvcc - skipped --- Detecting CUDA compile features --- Detecting CUDA compile features - done --- Found re2: /opt/or-tools/lib/cmake/re2/re2Config.cmake (found version "9.0.0") --- Found Clp: /opt/or-tools/lib/cmake/Clp/ClpConfig.cmake (found version "1.17.7") --- Found Cbc: /opt/or-tools/lib/cmake/Cbc/CbcConfig.cmake (found version "2.10.7") --- Found Eigen3: /usr/local/share/eigen3/cmake/Eigen3Config.cmake (found version "3.4.0") --- Found SCIP: /opt/or-tools/lib/cmake/scip/scip-config.cmake (found version "8.0.1") --- GUI is enabled --- Found Boost: /usr/local/lib/cmake/Boost-1.80.0/BoostConfig.cmake (found version "1.80.0") found components: serialization --- Found OpenMP_CXX: -fopenmp (found version "4.5") --- Found OpenMP: TRUE (found version "4.5") --- Could NOT find VTune (missing: VTune_LIBRARIES VTune_INCLUDE_DIRS) --- Found Boost: /usr/local/lib/cmake/Boost-1.80.0/BoostConfig.cmake (found suitable version "1.80.0", minimum required is "1.78") --- Found Boost: /usr/local/lib/cmake/Boost-1.80.0/BoostConfig.cmake (found version "1.80.0") found components: serialization system thread --- TCL readline enabled --- Tcl Extended disabled --- Python3 enabled --- Configuring done -CMake Warning (dev) in src/gpl/CMakeLists.txt: - Policy CMP0104 is not set: CMAKE_CUDA_ARCHITECTURES now detected for NVCC, - empty CUDA_ARCHITECTURES not allowed. Run "cmake --help-policy CMP0104" - for policy details. Use the cmake_policy command to set the policy and - suppress this warning. - - CUDA_ARCHITECTURES is empty for target "gpl". -This warning is for project developers. Use -Wno-dev to suppress it. - -CMake Error in src/gpl/CMakeLists.txt: - Target "gpl" requires the language dialect "CUDA17" . But the current - compiler "NVIDIA" does not support this, or CMake does not know the flags - to enable it. - - --- Generating done -CMake Generate step failed. Build files cannot be regenerated correctly. -``` - -I have Cuda installed and on `nvidia-smi` I get - -``` -+-----------------------------------------------------------------------------+ -| NVIDIA-SMI 525.85.12 Driver Version: 525.85.12 CUDA Version: 12.0 | -|-------------------------------+----------------------+----------------------+ -| GPU Name Persistence-M| Bus-Id Disp.A | Volatile Uncorr. ECC | -| Fan Temp Perf Pwr:Usage/Cap| Memory-Usage | GPU-Util Compute M. | -| | | MIG M. | -|===============================+======================+======================| -| 0 NVIDIA GeForce ... On | 00000000:01:00.0 On | N/A | -| N/A 51C P5 18W / 115W | 187MiB / 6144MiB | 19% Default | -| | | N/A | -+-------------------------------+----------------------+----------------------+ - -+-----------------------------------------------------------------------------+ -| Processes: | -| GPU GI CI PID Type Process name GPU Memory | -| ID ID Usage | -|=============================================================================| -| 0 N/A N/A 1211 G /usr/lib/xorg/Xorg 52MiB | -| 0 N/A N/A 1875 G /usr/lib/xorg/Xorg 133MiB | -+-----------------------------------------------------------------------------+ -``` - -and on `nvcc -V` - -``` -nvcc: NVIDIA (R) Cuda compiler driver -Copyright (c) 2005-2019 NVIDIA Corporation -Built on Sun_Jul_28_19:07:16_PDT_2019 -Cuda compilation tools, release 10.1, V10.1.243 -``` -Any help on how to get the setup working is really appreciated and thanks in advanced. - - - - - - - -### vvbandeira -Please install a newer version of `nvcc` and try again. As per NVIDIA docs, you will require at least v11; see more [here](https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#c-17-language-features). - -### maliberty -If we bump to cmake 3.10 then https://cmake.org/cmake/help/latest/module/FindCUDA.html suggests we can use the usual VERSION keyword. - -FYI - the use of CUDA is quite minimal and probably not worth the bother at this point. - diff --git a/gh_discussions/Build/3094.md b/gh_discussions/Build/3094.md deleted file mode 100644 index 10d5a630ac65e8175ead61ff2b9d87bdca73bb6c..0000000000000000000000000000000000000000 --- a/gh_discussions/Build/3094.md +++ /dev/null @@ -1,50 +0,0 @@ -# Problems with etc/DependencyInstaller.sh and md5 on boost - -Subcategory: Dependency installation - -## Conversation - -### oharboe -What's going on here? - -```bash -$ etc/DependencyInstaller.sh -prefix=~/openroad-tools/ -common -[deleted] -Length: 136670223 (130M) [application/x-gzip] -Saving to: ‘boost_1_80_0.tar.gz.1’ - -boost_1_80_0.tar.gz 100%[===================>] 130,34M 2,37MB/s in 65s - -2023-03-27 16:56:06 (2,02 MB/s) - ‘boost_1_80_0.tar.gz.1’ saved [136670223/136670223] - -+ md5sum -c /dev/fd/63 -++ echo '077f074743ea7b0cb49c6ed43953ae95 boost_1_80_0.tar.gz' -boost_1_80_0.tar.gz: FAILED -md5sum: WARNING: 1 computed checksum did NOT match -+ exit 1 -``` - -### oharboe -Hmm.... I suspect a manifestation of https://github.com/The-OpenROAD-Project/OpenROAD/issues/3096 - -### vvbandeira -The problem is that the first download failed, and the file was not correctly deleted. - -New download: -``` -boost_1_80_0.tar.gz 100%[===================>] 130,34M 2,37MB/s in 65s -``` - -Saving with the `.1` suffix: -``` -2023-03-27 16:56:06 (2,02 MB/s) - ‘boost_1_80_0.tar.gz.1’ saved [136670223/136670223] -``` - -Checking against the file without the suffix: -``` -+ md5sum -c /dev/fd/63 -++ echo '077f074743ea7b0cb49c6ed43953ae95 boost_1_80_0.tar.gz' -``` - -I will propose a PR that uses `mktemp` that should avoid this and the #3096 issues. You can manually delete the folder/offending file for now -- apologies for the inconvenience. - diff --git a/gh_discussions/Build/3124.md b/gh_discussions/Build/3124.md deleted file mode 100644 index c209e09d16f78ebf8a8b3b6b4cd7d2f3fff2dd57..0000000000000000000000000000000000000000 --- a/gh_discussions/Build/3124.md +++ /dev/null @@ -1,43 +0,0 @@ -# Problems building - undefined reference to `ord::getLogger()' - -Subcategory: Compilation error - -## Conversation - -### oharboe -Any idea what is going on here? - -``` -./build_openroad.sh --local --openroad-args "-D CMAKE_BUILD_TYPE=RELEASE" -[deleted] -TIMEOUT=5 -D TEST_XML_OUTPUT_DIR= -P /home/oyvind/ascenium/OpenROAD-flow-scripts/dependencies/share/cmake-3.24/Modules/GoogleTestAddTests.cmake -/usr/bin/ld: src/utl/utl.a(LoggerCommon.cpp.o): in function `utl::report(char const*)': -LoggerCommon.cpp:(.text+0x18f): undefined reference to `ord::getLogger()' -/usr/bin/ld: src/utl/utl.a(LoggerCommon.cpp.o): in function `utl::open_metrics(char const*)': -LoggerCommon.cpp:(.text+0x2e9): undefined reference to `ord::getLogger()' -/usr/bin/ld: src/utl/utl.a(LoggerCommon.cpp.o): in function `utl::close_metrics(char const*)': -LoggerCommon.cpp:(.text+0x309): undefined reference to `ord::getLogger()' -/usr/bin/ld: src/utl/utl.a(LoggerCommon.cpp.o): in function `utl::set_metrics_stage(char const*)': -LoggerCommon.cpp:(.text+0x32e): undefined reference to `ord::getLogger()' -/usr/bin/ld: src/utl/utl.a(LoggerCommon.cpp.o): in function `utl::clear_metrics_stage()': -LoggerCommon.cpp:(.text+0x369): undefined reference to `ord::getLogger()' -/usr/bin/ld: src/utl/utl.a(LoggerCommon.cpp.o):LoggerCommon.cpp:(.text+0x38e): more undefined references to `ord::getLogger()' follow -collect2: error: ld returned 1 exit status -``` - -### vijayank88 -@oharboe -Have you removed `OpenROAD-flow-scripts/tools` directory before building again. -Sometimes it may cause the issue. -@vvbandeira Can please check this? - -### maliberty -which binary is it building when the error happens? - -### oharboe -Rejoice! I finally got it to compile. I deleted the *entire* ORFS folder, recloned, reran sudo ./setup.sh and then the build worked. - -So, somewhere inside the ORFS folder there was an out of date file that wasn't being built... - -It would be nice to know what exactly is going wrong, but I guess that will have to wait until next time it breaks and I do some more investigations? - diff --git a/gh_discussions/Build/3148.md b/gh_discussions/Build/3148.md deleted file mode 100644 index dfc8e23b793a586e9f5b04dbb2a71ff972eaa7ac..0000000000000000000000000000000000000000 --- a/gh_discussions/Build/3148.md +++ /dev/null @@ -1,51 +0,0 @@ -# LoggerCommon.cpp:(.text+0x18f): undefined reference to `ord::getLogger()' - -Subcategory: Linking error - -## Conversation - -### oharboe -I'm getting this problem again while building OpenROAD locally. I've tried recloning and deleting the entire ORFS folder, still no luck. - -Any ideas? - -``` -$ lsb_release -a -No LSB modules are available. -Distributor ID: Ubuntu -Description: Ubuntu 22.10 -Release: 22.10 -Codename: kinetic - -``` -``` -./build_openroad.sh --local --openroad-args "-D CMAKE_BUILD_TYPE=RELEASE" -``` - -``` -[deleted] -FAILED: src/dpl/test/dpl_test src/dpl/test/dpl_test[1]_tests.cmake /home/oyvind/ascenium/blah/tools/OpenROAD/build/src/dpl/test/dpl_test[1]_tests.cmake -: && /usr/bin/c++ -O3 -DNDEBUG src/dpl/test/CMakeFiles/dpl_test.dir/dpl_test.cc.o -o src/dpl/test/dpl_test -lgtest -lgtest_main src/dpl/libdpl_lib.a src/odb/src/cdl/libcdl.a src/odb/src/defin/libdefin.a src/odb/src/def/libdef.a src/odb/src/def/libdefzlib.a src/odb/src/lefin/liblefin.a src/odb/src/lef/liblef.a src/odb/src/lef/liblefzlib.a /usr/lib/x86_64-linux-gnu/libz.so src/odb/src/db/libdb.a src/odb/src/defout/libdefout.a src/odb/src/lefout/liblefout.a src/odb/src/zutil/libzutil.a src/odb/src/db/libdb.a src/odb/src/defout/libdefout.a src/odb/src/lefout/liblefout.a src/odb/src/zutil/libzutil.a src/odb/src/tm/libtm.a /home/oyvind/ascenium/blah/tools/OpenROAD/src/sta/app/libOpenSTA.a /usr/lib/x86_64-linux-gnu/libtcl.so /usr/lib/x86_64-linux-gnu/libtclreadline.so /usr/lib/x86_64-linux-gnu/libz.so -ltcl src/utl/utl.a src/utl/libutl_lib.a /home/oyvind/ascenium/blah/dependencies/lib/libspdlog.a && cd /home/oyvind/ascenium/blah/tools/OpenROAD/build/src/dpl/test && /home/oyvind/ascenium/blah/dependencies/bin/cmake -D TEST_TARGET=dpl_test -D TEST_EXECUTABLE=/home/oyvind/ascenium/blah/tools/OpenROAD/build/src/dpl/test/dpl_test -D TEST_EXECUTOR= -D TEST_WORKING_DIR=/home/oyvind/ascenium/blah/tools/OpenROAD/src/dpl/test -D TEST_EXTRA_ARGS= -D TEST_PROPERTIES= -D TEST_PREFIX= -D TEST_SUFFIX= -D TEST_FILTER= -D NO_PRETTY_TYPES=FALSE -D NO_PRETTY_VALUES=FALSE -D TEST_LIST=dpl_test_TESTS -D CTEST_FILE=/home/oyvind/ascenium/blah/tools/OpenROAD/build/src/dpl/test/dpl_test[1]_tests.cmake -D TEST_DISCOVERY_TIMEOUT=5 -D TEST_XML_OUTPUT_DIR= -P /home/oyvind/ascenium/blah/dependencies/share/cmake-3.24/Modules/GoogleTestAddTests.cmake -/usr/bin/ld: src/utl/utl.a(LoggerCommon.cpp.o): in function `utl::report(char const*)': -LoggerCommon.cpp:(.text+0x18f): undefined reference to `ord::getLogger()' -/usr/bin/ld: src/utl/utl.a(LoggerCommon.cpp.o): in function `utl::open_metrics(char const*)': -LoggerCommon.cpp:(.text+0x2e9): undefined reference to `ord::getLogger()' -/usr/bin/ld: src/utl/utl.a(LoggerCommon.cpp.o): in function `utl::close_metrics(char const*)': -LoggerCommon.cpp:(.text+0x309): undefined reference to `ord::getLogger()' -/usr/bin/ld: src/utl/utl.a(LoggerCommon.cpp.o): in function `utl::set_metrics_stage(char const*)': -LoggerCommon.cpp:(.text+0x32e): undefined reference to `ord::getLogger()' -/usr/bin/ld: src/utl/utl.a(LoggerCommon.cpp.o): in function `utl::clear_metrics_stage()': -LoggerCommon.cpp:(.text+0x369): undefined reference to `ord::getLogger()' -/usr/bin/ld: src/utl/utl.a(LoggerCommon.cpp.o):LoggerCommon.cpp:(.text+0x38e): more undefined references to `ord::getLogger()' follow -collect2: error: ld returned 1 exit status -[3/39] Automatic MOC and UIC for target gui -ninja: build stopped: subcommand failed. -``` - - -### maliberty -I can't reproduce it but can you try changing https://github.com/The-OpenROAD-Project/OpenROAD/blob/8a49dff86645352d30780951b1146b31ef41b0f4/src/dpl/CMakeLists.txt#L58 to utl_lib and see if that helps. - -### maliberty -PR coming. I'm not sure why it varies - perhaps different compilers? - diff --git a/gh_discussions/Build/3489.md b/gh_discussions/Build/3489.md deleted file mode 100644 index ff33a61e095e182bfe215715fc3f82c514554460..0000000000000000000000000000000000000000 --- a/gh_discussions/Build/3489.md +++ /dev/null @@ -1,26 +0,0 @@ -# ABC contains local modifications! - -Tool: Verilog to DB - -Subcategory: Compilation error - -## Conversation - -### Simonliudan -[ 12%] Building abc/abc-bafd2a7 -Debug: ABCREV=bafd2a7 -[ 22%] Building passes/techmap/filterlib.o -[ 22%] Building yosys-smtbmc -ERROR: ABC contains local modifications! Set ABCREV=default in Yosys Makefile! -make: *** [Makefile:749: abc/abc-bafd2a7] Error 1 - -in Centos, I have set ABCREV = default, but the debug info is bafd2a7 - - -### vijayank88 -Is this installation issue? -Can you provide steps to reproduce the same? - -### vvbandeira -@Simonliudan, this looks more like an issue than a discussion. Please file an Issue and follow the Issue template, the template give us important information to help you. - diff --git a/gh_discussions/Build/3513.md b/gh_discussions/Build/3513.md deleted file mode 100644 index d78f7877579d3384ae592aaf6384de22b2fbf4de..0000000000000000000000000000000000000000 --- a/gh_discussions/Build/3513.md +++ /dev/null @@ -1,33 +0,0 @@ -# Build problems. Missing gmock.h - -Subcategory: Missing dependency - -## Conversation - -### oharboe -There has been a lot of activity concerning build errors, but I tried with latest master merged with #3512 - -Is it enough to update to latest master or do I need to purge something or other locally? - -``` -./build_openroad.sh --local --openroad-args "-DCMAKE_BUILD_TYPE=RELEASE -DCMAKE_CXX_FLAGS=-g" -``` - -``` -[ 25%] Building CXX object src/odb/test/cpp/CMakeFiles/TestGuide.dir/TestGuide.cpp.o -/home/oyvind/OpenROAD-flow-scripts/tools/OpenROAD/src/odb/test/cpp/TestAbstractLef.cc:13:10: fatal error: gmock/gmock.h: No such file or directory - 13 | #include "gmock/gmock.h" - | ^~~~~~~~~~~~~~~ -compilation terminated. -gmake[2]: *** [src/odb/test/cpp/CMakeFiles/OdbGTests.dir/build.make:90: src/odb/test/cpp/CMakeFiles/OdbGTests.dir/TestAbstractLef.cc.o] Error 1 -gmake[1]: *** [CMakeFiles/Makefile2:2331: src/odb/test/cpp/CMakeFiles/OdbGTests.dir/all] Error 2 -gmake[1]: *** Waiting for unfinished jobs... -``` - - -### QuantamHD -This ones my bad. It seems that some installations of libgtest-dev don't include google mock. If you uninstall your system gtest it will fix this error, but I'll see if there's something else we could do to fix this. - -### vvbandeira -Fixed on #3514 - diff --git a/gh_discussions/Build/3779.md b/gh_discussions/Build/3779.md deleted file mode 100644 index 9deb6a49470fdfa8b3421d003ddeb983054cb302..0000000000000000000000000000000000000000 --- a/gh_discussions/Build/3779.md +++ /dev/null @@ -1,19 +0,0 @@ -# arm64 release for Ubuntu - -Subcategory: Cross-platform compilation - -## Conversation - -### ilyaext -I'm looking for an arm64 OpenROAD architecture release to install on Linux AWS EC2 arm64. -Can anyone give me a link or suggest how to compile? - -### maliberty -We don't test or release on arm64 but you can probably build from source. - -### maliberty -https://openroad.readthedocs.io/en/latest/user/Build.html - -### maliberty -https://openroad-flow-scripts.readthedocs.io/en/latest/user/BuildLocally.html for ORFS - diff --git a/gh_discussions/Build/4137.md b/gh_discussions/Build/4137.md deleted file mode 100644 index 34fcb78326d871c3eda57279cf900c579ffed281..0000000000000000000000000000000000000000 --- a/gh_discussions/Build/4137.md +++ /dev/null @@ -1,1565 +0,0 @@ -# OpenROAD build issue - -Subcategory: Compilation error - -## Conversation - -### idokoike - -I've been trying to fully install OpenROAD using the` ./build_openroad.sh --local --threads 1` command but I keep getting the error -``` -[INFO FLW-0027] Saving logs to build_openroad.log -[INFO FLW-0028] ./build_openroad.sh --local --threads 1 -[INFO FLW-0002] Updating git submodules. -[INFO FLW-0001] Using local build method. This will create binaries at 'tools/install' unless overwritten. -[INFO FLW-0017] Compiling Yosys. -make: Entering directory '/home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/tools/yosys' -mkdir -p /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/tools/install/yosys/bin -cp yosys yosys-config yosys-abc yosys-filterlib yosys-smtbmc /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/tools/install/yosys/bin -strip -S /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/tools/install/yosys/bin/yosys -strip /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/tools/install/yosys/bin/yosys-abc -strip /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/tools/install/yosys/bin/yosys-filterlib -mkdir -p /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/tools/install/yosys/share/yosys -cp -r share/. /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/tools/install/yosys/share/yosys/. -make: Leaving directory '/home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/tools/yosys' -[INFO FLW-0018] Compiling OpenROAD. --- OpenROAD version: v2.0-10669-g436c7801a --- System name: Linux --- Compiler: GNU 11.4.0 --- Build type: RELEASE --- Install prefix: /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/tools/install/OpenROAD --- C++ Standard: 17 --- C++ Standard Required: ON --- C++ Extensions: OFF --- TCL library: /usr/lib/x86_64-linux-gnu/libtcl.so --- TCL header: /usr/include/tcl/tcl.h --- TCL readline library: /usr/lib/x86_64-linux-gnu/libtclreadline.so --- TCL readline header: /usr/include/x86_64-linux-gnu --- boost: 1.74.0 --- spdlog: 1.9.2 -CMake Warning at src/CMakeLists.txt:242 (message): - spdlog: SPDLOG_FMT_EXTERNAL=ON - - --- Could NOT find Doxygen (missing: DOXYGEN_EXECUTABLE) --- STA version: 2.4.0 --- STA git sha: 44f06c521560e803859218732255b3259de048e1 --- System name: Linux --- Compiler: GNU 11.4.0 --- Build type: RELEASE --- Build CXX_FLAGS: -O3 -DNDEBUG --- Install prefix: /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/tools/install/OpenROAD --- TCL library: /usr/lib/x86_64-linux-gnu/libtcl.so --- TCL header: /usr/include/tcl/tcl.h --- SSTA: 0 --- STA executable: /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/tools/OpenROAD/src/sta/app/sta -CMake Error at src/gpl/CMakeLists.txt:44 (find_package): - By not providing "Findortools.cmake" in CMAKE_MODULE_PATH this project has - asked CMake to find a package configuration file provided by "ortools", but - CMake did not find one. - - Could not find a package configuration file provided by "ortools" with any - of the following names: - - ortoolsConfig.cmake - ortools-config.cmake - - Add the installation prefix of "ortools" to CMAKE_PREFIX_PATH or set - "ortools_DIR" to a directory containing one of the above files. If - "ortools" provides a separate development package or SDK, be sure it has - been installed. - - --- Configuring incomplete, errors occurred! - -``` -I've installed or-tools using `git clone https://github.com/google/or-tools.git` and I'm still getting the error - -### rovinski -This is better to submit as an issue in order to get a better handle on your environment. - -That being said, where are you installing ortools? The default location that CMake looks for is the default paths searched by CMake's `find_package` and also `/opt/or-tools/lib64/` and `/opt/or-tools/lib/`. If it's not in one of those locations, you should either install it there, or add `--openroad-args "ortools_DIR=path/to/your/ortools/cmake/file"` to your script invocation. - -### idokoike -Thanks. I've added `--openroad-args "ortools_DIR=path/to/your/ortools/cmake/file"` to my script, and it works kind of but I'm getting another error - -``` -[INFO FLW-0027] Saving logs to build_openroad.log -[INFO FLW-0028] ./build_openroad.sh --local threads 2 --openroad-args /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/build -[INFO FLW-0002] Updating git submodules. -[INFO FLW-0001] Using local build method. This will create binaries at 'tools/install' unless overwritten. -[INFO FLW-0017] Compiling Yosys. -make: Entering directory '/home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/tools/yosys' -mkdir -p /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/tools/install/yosys/bin -cp yosys yosys-config yosys-abc yosys-filterlib yosys-smtbmc /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/tools/install/yosys/bin -strip -S /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/tools/install/yosys/bin/yosys -strip /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/tools/install/yosys/bin/yosys-abc -strip /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/tools/install/yosys/bin/yosys-filterlib -mkdir -p /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/tools/install/yosys/share/yosys -cp -r share/. /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/tools/install/yosys/share/yosys/. -make: Leaving directory '/home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/tools/yosys' -[INFO FLW-0018] Compiling OpenROAD. --- ortools version: 9.7.3002 --- Build type: Release --- Build C++ library: ON --- Build Python: OFF --- Build Java: OFF --- Build .Net: OFF --- Build Flatzinc: ON --- Build LP Parser: ON --- Build standalone Glop: OFF --- Build samples: ON --- Build C++ samples: ON --- Build Python samples: OFF --- Build Java samples: OFF --- Build .Net samples: OFF --- Build examples: ON --- Build C++ examples: ON --- Build Python examples: OFF --- Build Java examples: OFF --- Build .Net examples: OFF --- Build documentation: OFF --- Install doc: OFF --- Build all dependencies: ON --- Build ZLIB: ON --- Build abseil-cpp: ON --- Build protobuf: ON --- Build re2: ON --- Build googletest: ON --- COIN-OR support: OFF --- GLPK support: OFF --- HiGHS support: OFF --- PDLP support: ON --- Build PDLP: ON --- Build eigen3: ON --- SCIP support: OFF --- CPLEX support: OFF --- XPRESS support: OFF --- C++: Build doc: OFF --- Fetching ZLIB --- Populating zlib --- Configuring done --- Generating done --- Build files have been written to: /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/build/_deps/zlib-subbuild -[100%] Built target zlib-populate --- Fetching ZLIB - fetched --- Fetching Abseil-cpp --- Populating absl --- Configuring done --- Generating done --- Build files have been written to: /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/build/_deps/absl-subbuild -[100%] Built target absl-populate -CMake Warning at build/_deps/absl-src/CMake/AbseilDll.cmake:605 (message): - ABSL_CXX_STANDARD: -Call Stack (most recent call first): - build/_deps/absl-src/CMakeLists.txt:86 (include) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilDll.cmake:606 (message): - CMAKE_CXX_STANDARD: 17 -Call Stack (most recent call first): - build/_deps/absl-src/CMakeLists.txt:86 (include) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilDll.cmake:607 (message): - CMAKE_CXX_STANDARD_REQUIRED: ON -Call Stack (most recent call first): - build/_deps/absl-src/CMakeLists.txt:86 (include) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilDll.cmake:608 (message): - CMAKE_CXX_FLAGS: -Call Stack (most recent call first): - build/_deps/absl-src/CMakeLists.txt:86 (include) - - -CMake Warning at build/_deps/absl-src/absl/copts/AbseilConfigureCopts.cmake:97 (message): - ABSL_CXX_STANDARD: 17. -Call Stack (most recent call first): - build/_deps/absl-src/CMake/AbseilHelpers.cmake:18 (include) - build/_deps/absl-src/CMakeLists.txt:87 (include) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilDll.cmake:605 (message): - ABSL_CXX_STANDARD: 17 -Call Stack (most recent call first): - build/_deps/absl-src/CMake/AbseilHelpers.cmake:19 (include) - build/_deps/absl-src/CMakeLists.txt:87 (include) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilDll.cmake:606 (message): - CMAKE_CXX_STANDARD: 17 -Call Stack (most recent call first): - build/_deps/absl-src/CMake/AbseilHelpers.cmake:19 (include) - build/_deps/absl-src/CMakeLists.txt:87 (include) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilDll.cmake:607 (message): - CMAKE_CXX_STANDARD_REQUIRED: ON -Call Stack (most recent call first): - build/_deps/absl-src/CMake/AbseilHelpers.cmake:19 (include) - build/_deps/absl-src/CMakeLists.txt:87 (include) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilDll.cmake:608 (message): - CMAKE_CXX_FLAGS: -Call Stack (most recent call first): - build/_deps/absl-src/CMake/AbseilHelpers.cmake:19 (include) - build/_deps/absl-src/CMakeLists.txt:87 (include) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/base/CMakeLists.txt:20 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/base/CMakeLists.txt:33 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/base/CMakeLists.txt:44 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/base/CMakeLists.txt:58 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/base/CMakeLists.txt:76 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/base/CMakeLists.txt:95 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/base/CMakeLists.txt:107 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/base/CMakeLists.txt:121 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/base/CMakeLists.txt:140 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/base/CMakeLists.txt:161 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/base/CMakeLists.txt:177 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/base/CMakeLists.txt:220 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/base/CMakeLists.txt:249 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/base/CMakeLists.txt:428 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/base/CMakeLists.txt:539 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/base/CMakeLists.txt:591 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/base/CMakeLists.txt:623 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/base/CMakeLists.txt:649 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/algorithm/CMakeLists.txt:17 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/algorithm/CMakeLists.txt:42 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/cleanup/CMakeLists.txt:16 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/cleanup/CMakeLists.txt:30 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/container/CMakeLists.txt:17 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/container/CMakeLists.txt:91 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/container/CMakeLists.txt:120 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/container/CMakeLists.txt:170 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/container/CMakeLists.txt:186 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/container/CMakeLists.txt:204 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/container/CMakeLists.txt:277 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/container/CMakeLists.txt:313 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/container/CMakeLists.txt:351 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/container/CMakeLists.txt:387 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/container/CMakeLists.txt:423 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/container/CMakeLists.txt:453 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/container/CMakeLists.txt:530 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/container/CMakeLists.txt:556 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/container/CMakeLists.txt:581 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/container/CMakeLists.txt:613 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/container/CMakeLists.txt:625 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/container/CMakeLists.txt:638 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/container/CMakeLists.txt:664 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/container/CMakeLists.txt:679 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/container/CMakeLists.txt:691 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/container/CMakeLists.txt:760 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/crc/CMakeLists.txt:16 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/crc/CMakeLists.txt:31 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/crc/CMakeLists.txt:56 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/crc/CMakeLists.txt:97 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/crc/CMakeLists.txt:109 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/crc/CMakeLists.txt:150 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/debugging/CMakeLists.txt:19 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/debugging/CMakeLists.txt:61 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/debugging/CMakeLists.txt:115 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/debugging/CMakeLists.txt:132 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/debugging/CMakeLists.txt:169 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/debugging/CMakeLists.txt:191 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/debugging/CMakeLists.txt:223 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/debugging/CMakeLists.txt:285 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/flags/CMakeLists.txt:18 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/flags/CMakeLists.txt:34 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/flags/CMakeLists.txt:54 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/flags/CMakeLists.txt:75 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/flags/CMakeLists.txt:96 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/flags/CMakeLists.txt:113 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/flags/CMakeLists.txt:133 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/flags/CMakeLists.txt:151 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/flags/CMakeLists.txt:174 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/flags/CMakeLists.txt:199 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/flags/CMakeLists.txt:224 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/flags/CMakeLists.txt:250 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/flags/CMakeLists.txt:269 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/functional/CMakeLists.txt:17 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/functional/CMakeLists.txt:53 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/functional/CMakeLists.txt:81 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/hash/CMakeLists.txt:17 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/hash/CMakeLists.txt:106 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/hash/CMakeLists.txt:134 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/log/CMakeLists.txt:18 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/log/CMakeLists.txt:36 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/log/CMakeLists.txt:56 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/log/CMakeLists.txt:74 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/log/CMakeLists.txt:89 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/log/CMakeLists.txt:103 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/log/CMakeLists.txt:127 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/log/CMakeLists.txt:147 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/log/CMakeLists.txt:163 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/log/CMakeLists.txt:182 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/log/CMakeLists.txt:219 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/log/CMakeLists.txt:248 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/log/CMakeLists.txt:264 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/log/CMakeLists.txt:281 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/log/CMakeLists.txt:363 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/log/CMakeLists.txt:377 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/log/CMakeLists.txt:394 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/log/CMakeLists.txt:409 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/log/CMakeLists.txt:424 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/log/CMakeLists.txt:444 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/log/CMakeLists.txt:463 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/log/CMakeLists.txt:487 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/log/CMakeLists.txt:507 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/log/CMakeLists.txt:526 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/log/CMakeLists.txt:541 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/log/CMakeLists.txt:563 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/log/CMakeLists.txt:580 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/log/CMakeLists.txt:597 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/log/CMakeLists.txt:643 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/log/CMakeLists.txt:658 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/memory/CMakeLists.txt:17 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/meta/CMakeLists.txt:17 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/meta/CMakeLists.txt:45 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/numeric/CMakeLists.txt:17 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/numeric/CMakeLists.txt:44 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/numeric/CMakeLists.txt:79 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/numeric/CMakeLists.txt:89 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/profiling/CMakeLists.txt:15 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/profiling/CMakeLists.txt:40 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/profiling/CMakeLists.txt:67 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/random/CMakeLists.txt:17 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/random/CMakeLists.txt:35 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/random/CMakeLists.txt:70 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/random/CMakeLists.txt:161 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/random/CMakeLists.txt:199 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/random/CMakeLists.txt:214 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/random/CMakeLists.txt:517 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/random/CMakeLists.txt:531 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/random/CMakeLists.txt:547 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/random/CMakeLists.txt:561 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/random/CMakeLists.txt:583 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/random/CMakeLists.txt:639 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/random/CMakeLists.txt:657 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/random/CMakeLists.txt:672 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/random/CMakeLists.txt:689 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/random/CMakeLists.txt:705 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/random/CMakeLists.txt:719 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/random/CMakeLists.txt:739 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/random/CMakeLists.txt:757 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/random/CMakeLists.txt:775 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/random/CMakeLists.txt:792 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/random/CMakeLists.txt:810 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/random/CMakeLists.txt:827 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/random/CMakeLists.txt:847 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/random/CMakeLists.txt:864 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/random/CMakeLists.txt:1155 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/status/CMakeLists.txt:16 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/status/CMakeLists.txt:58 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/strings/CMakeLists.txt:17 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/strings/CMakeLists.txt:77 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/strings/CMakeLists.txt:396 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/strings/CMakeLists.txt:409 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/strings/CMakeLists.txt:579 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/strings/CMakeLists.txt:620 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/strings/CMakeLists.txt:647 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/strings/CMakeLists.txt:676 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/strings/CMakeLists.txt:691 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/strings/CMakeLists.txt:725 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/strings/CMakeLists.txt:794 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/strings/CMakeLists.txt:833 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/strings/CMakeLists.txt:866 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/synchronization/CMakeLists.txt:18 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/synchronization/CMakeLists.txt:37 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/synchronization/CMakeLists.txt:50 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/time/CMakeLists.txt:17 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/time/CMakeLists.txt:45 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/time/CMakeLists.txt:61 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/types/CMakeLists.txt:16 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/types/CMakeLists.txt:33 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/types/CMakeLists.txt:47 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/types/CMakeLists.txt:106 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/types/CMakeLists.txt:163 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/types/CMakeLists.txt:183 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:293 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/types/CMakeLists.txt:198 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/types/CMakeLists.txt:296 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/types/CMakeLists.txt:332 (absl_cc_library) - - -CMake Warning at build/_deps/absl-src/CMake/AbseilHelpers.cmake:342 (message): - Force CXX_FLAGS flags to cxx_std_17 -Call Stack (most recent call first): - build/_deps/absl-src/absl/utility/CMakeLists.txt:17 (absl_cc_library) - - --- Fetching Abseil-cpp - fetched --- Fetching Protobuf --- Populating protobuf --- Configuring done --- Generating done --- Build files have been written to: /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/build/_deps/protobuf-subbuild -[100%] Built target protobuf-populate --- --- 23.3.0 --- Fetching Protobuf - fetched --- Fetching re2 --- Populating re2 --- Configuring done --- Generating done --- Build files have been written to: /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/build/_deps/re2-subbuild -[100%] Built target re2-populate --- Fetching re2 - fetched --- Fetching Eigen3 --- Populating eigen3 --- Configuring done --- Generating done --- Build files have been written to: /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/build/_deps/eigen3-subbuild -[100%] Built target eigen3-populate --- Performing Test COMPILER_SUPPORT_std=cpp03 --- Performing Test COMPILER_SUPPORT_std=cpp03 - Success --- Standard libraries to link to explicitly: none --- Found unsuitable Qt version "5.15.3" from /usr/bin/qmake --- Qt4 not found, so disabling the mandelbrot and opengl demos --- Could NOT find CHOLMOD (missing: CHOLMOD_INCLUDES CHOLMOD_LIBRARIES) --- Could NOT find UMFPACK (missing: UMFPACK_INCLUDES UMFPACK_LIBRARIES) --- Could NOT find KLU (missing: KLU_INCLUDES KLU_LIBRARIES) --- Could NOT find SuperLU (missing: SUPERLU_INCLUDES SUPERLU_LIBRARIES SUPERLU_VERSION_OK) (Required is at least version "4.0") --- A version of Pastix has been found but pastix_nompi.h does not exist in the include directory. Because Eigen tests require a version without MPI, we disable the Pastix backend. --- --- Configured Eigen 3.4.0 --- --- Available targets (use: make TARGET): --- ---------+-------------------------------------------------------------- --- Target | Description --- ---------+-------------------------------------------------------------- --- install | Install Eigen. Headers will be installed to: --- | / --- | Using the following values: --- | CMAKE_INSTALL_PREFIX: /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/tools/install/OpenROAD --- | INCLUDE_INSTALL_DIR: include/eigen3 --- | Change the install location of Eigen headers using: --- | cmake . -DCMAKE_INSTALL_PREFIX=yourprefix --- | Or: --- | cmake . -DINCLUDE_INSTALL_DIR=yourdir --- doc | Generate the API documentation, requires Doxygen & LaTeX --- blas | Build BLAS library (not the same thing as Eigen) --- uninstall| Remove files installed by the install target --- ---------+-------------------------------------------------------------- --- --- Fetching Eigen3 - fetched --- Fetching googletest --- Populating googletest --- Configuring done --- Generating done --- Build files have been written to: /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/build/_deps/googletest-subbuild -[100%] Built target googletest-populate --- Fetching googletest - fetched --- Found long size: 8 --- Found long long size: 8 --- Found int64_t size: 8 --- Found unsigned long size: 8 --- Found unsigned long long size: 8 --- Found uint64_t size: 8 --- Found int * size: 8 --- Adding proto path: $ --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/algorithms/samples/knapsack.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/algorithms/samples/knapsack.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/algorithms/samples/simple_knapsack_program.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/algorithms/samples/simple_knapsack_program.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/graph/samples/assignment_linear_sum_assignment.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/graph/samples/assignment_linear_sum_assignment.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/graph/samples/assignment_min_flow.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/graph/samples/assignment_min_flow.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/graph/samples/balance_min_flow.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/graph/samples/balance_min_flow.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/graph/samples/simple_max_flow_program.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/graph/samples/simple_max_flow_program.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/graph/samples/simple_min_cost_flow_program.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/graph/samples/simple_min_cost_flow_program.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/glop/samples/simple_glop_program.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/glop/samples/simple_glop_program.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/cp_is_fun_cp.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/cp_is_fun_cp.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/minimal_jobshop_cp.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/minimal_jobshop_cp.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/nqueens_cp.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/nqueens_cp.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/nurses_cp.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/nurses_cp.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/rabbits_and_pheasants_cp.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/rabbits_and_pheasants_cp.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/simple_cp_program.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/simple_cp_program.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/simple_ls_program.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/simple_ls_program.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/simple_routing_program.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/simple_routing_program.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/tsp.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/tsp.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/tsp_circuit_board.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/tsp_circuit_board.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/tsp_cities.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/tsp_cities.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/tsp_cities_routes.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/tsp_cities_routes.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/tsp_distance_matrix.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/tsp_distance_matrix.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/vrp.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/vrp.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/vrp_breaks.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/vrp_breaks.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/vrp_capacity.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/vrp_capacity.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/vrp_drop_nodes.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/vrp_drop_nodes.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/vrp_global_span.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/vrp_global_span.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/vrp_initial_routes.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/vrp_initial_routes.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/vrp_pickup_delivery.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/vrp_pickup_delivery.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/vrp_pickup_delivery_fifo.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/vrp_pickup_delivery_fifo.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/vrp_pickup_delivery_lifo.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/vrp_pickup_delivery_lifo.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/vrp_resources.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/vrp_resources.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/vrp_routes.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/vrp_routes.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/vrp_solution_callback.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/vrp_solution_callback.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/vrp_starts_ends.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/vrp_starts_ends.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/vrp_time_windows.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/vrp_time_windows.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/vrp_with_time_limit.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/vrp_with_time_limit.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/vrptw_store_solution_data.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/constraint_solver/samples/vrptw_store_solution_data.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/linear_solver/samples/assignment_groups_mip.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/linear_solver/samples/assignment_groups_mip.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/linear_solver/samples/assignment_mip.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/linear_solver/samples/assignment_mip.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/linear_solver/samples/assignment_task_sizes_mip.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/linear_solver/samples/assignment_task_sizes_mip.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/linear_solver/samples/assignment_teams_mip.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/linear_solver/samples/assignment_teams_mip.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/linear_solver/samples/basic_example.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/linear_solver/samples/basic_example.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/linear_solver/samples/bin_packing_mip.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/linear_solver/samples/bin_packing_mip.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/linear_solver/samples/integer_programming_example.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/linear_solver/samples/integer_programming_example.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/linear_solver/samples/linear_programming_example.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/linear_solver/samples/linear_programming_example.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/linear_solver/samples/mip_var_array.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/linear_solver/samples/mip_var_array.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/linear_solver/samples/multiple_knapsack_mip.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/linear_solver/samples/multiple_knapsack_mip.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/linear_solver/samples/simple_lp_program.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/linear_solver/samples/simple_lp_program.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/linear_solver/samples/simple_mip_program.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/linear_solver/samples/simple_mip_program.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/linear_solver/samples/stigler_diet.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/linear_solver/samples/stigler_diet.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/pdlp/samples/simple_pdlp_program.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/pdlp/samples/simple_pdlp_program.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/assignment_groups_sat.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/assignment_groups_sat.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/assignment_sat.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/assignment_sat.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/assignment_task_sizes_sat.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/assignment_task_sizes_sat.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/assignment_teams_sat.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/assignment_teams_sat.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/assumptions_sample_sat.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/assumptions_sample_sat.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/binpacking_problem_sat.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/binpacking_problem_sat.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/bool_or_sample_sat.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/bool_or_sample_sat.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/channeling_sample_sat.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/channeling_sample_sat.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/copy_model_sample_sat.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/copy_model_sample_sat.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/cp_is_fun_sat.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/cp_is_fun_sat.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/cp_sat_example.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/cp_sat_example.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/earliness_tardiness_cost_sample_sat.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/earliness_tardiness_cost_sample_sat.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/interval_sample_sat.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/interval_sample_sat.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/literal_sample_sat.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/literal_sample_sat.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/minimal_jobshop_sat.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/minimal_jobshop_sat.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/multiple_knapsack_sat.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/multiple_knapsack_sat.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/no_overlap_sample_sat.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/no_overlap_sample_sat.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/non_linear_sat.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/non_linear_sat.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/nqueens_sat.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/nqueens_sat.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/nurses_sat.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/nurses_sat.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/optional_interval_sample_sat.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/optional_interval_sample_sat.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/rabbits_and_pheasants_sat.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/rabbits_and_pheasants_sat.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/ranking_sample_sat.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/ranking_sample_sat.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/reified_sample_sat.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/reified_sample_sat.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/schedule_requests_sat.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/schedule_requests_sat.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/search_for_all_solutions_sample_sat.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/search_for_all_solutions_sample_sat.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/simple_sat_program.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/simple_sat_program.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/solution_hinting_sample_sat.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/solution_hinting_sample_sat.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/solve_and_print_intermediate_solutions_sample_sat.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/solve_and_print_intermediate_solutions_sample_sat.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/solve_with_time_limit_sample_sat.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/solve_with_time_limit_sample_sat.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/step_function_sample_sat.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/step_function_sample_sat.cc: ...DONE --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/stop_after_n_solutions_sample_sat.cc: ... --- Configuring sample /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/ortools/sat/samples/stop_after_n_solutions_sample_sat.cc: ...DONE --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/constraint_programming_cp.cc: ... --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/constraint_programming_cp.cc: ...DONE --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/costas_array_sat.cc: ... --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/costas_array_sat.cc: ...DONE --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/cryptarithm_sat.cc: ... --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/cryptarithm_sat.cc: ...DONE --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/cvrp_disjoint_tw.cc: ... --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/cvrp_disjoint_tw.cc: ...DONE --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/cvrptw.cc: ... --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/cvrptw.cc: ...DONE --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/cvrptw_with_resources.cc: ... --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/cvrptw_with_resources.cc: ...DONE --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/cvrptw_with_stop_times_and_resources.cc: ... --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/cvrptw_with_stop_times_and_resources.cc: ...DONE --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/flow_api.cc: ... --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/flow_api.cc: ...DONE --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/golomb_sat.cc: ... --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/golomb_sat.cc: ...DONE --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/integer_programming.cc: ... --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/integer_programming.cc: ...DONE --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/linear_assignment_api.cc: ... --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/linear_assignment_api.cc: ...DONE --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/linear_programming.cc: ... --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/linear_programming.cc: ...DONE --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/linear_solver_protocol_buffers.cc: ... --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/linear_solver_protocol_buffers.cc: ...DONE --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/magic_sequence_sat.cc: ... --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/magic_sequence_sat.cc: ...DONE --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/magic_square_sat.cc: ... --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/magic_square_sat.cc: ...DONE --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/max_flow.cc: ... --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/max_flow.cc: ...DONE --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/min_cost_flow.cc: ... --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/min_cost_flow.cc: ...DONE --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/nqueens.cc: ... --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/nqueens.cc: ...DONE --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/qap_sat.cc: ... --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/qap_sat.cc: ...DONE --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/random_tsp.cc: ... --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/random_tsp.cc: ...DONE --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/slitherlink_sat.cc: ... --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/slitherlink_sat.cc: ...DONE --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/uncapacitated_facility_location.cc: ... --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/uncapacitated_facility_location.cc: ...DONE --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/variable_intervals_sat.cc: ... --- Configuring example /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/cpp/variable_intervals_sat.cc: ...DONE --- Configuring test /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/tests/bug_fz1.cc: ... --- Configuring test /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/tests/bug_fz1.cc: ...DONE --- Configuring test /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/tests/cpp11_test.cc: ... --- Configuring test /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/tests/cpp11_test.cc: ...DONE --- Configuring test /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/tests/forbidden_intervals_test.cc: ... --- Configuring test /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/tests/forbidden_intervals_test.cc: ...DONE --- Configuring test /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/tests/init_test.cc: ... --- Configuring test /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/tests/init_test.cc: ...DONE --- Configuring test /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/tests/issue1303.cc: ... --- Configuring test /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/tests/issue1303.cc: ...DONE --- Configuring test /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/tests/issue173.cc: ... --- Configuring test /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/tests/issue173.cc: ...DONE --- Configuring test /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/tests/issue57.cc: ... --- Configuring test /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/tests/issue57.cc: ...DONE --- Configuring test /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/tests/lp_test.cc: ... --- Configuring test /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/tests/lp_test.cc: ...DONE --- Configuring test /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/tests/min_max_test.cc: ... --- Configuring test /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/examples/tests/min_max_test.cc: ...DONE --- Configuring done --- Generating done --- Build files have been written to: /home/ikenna/Work/vlsi/tools/OpenROAD-flow-scripts/or-tools/build -gmake: Makefile: No such file or directory -gmake: *** No rule to make target 'Makefile'. Stop. - -``` - -### vvbandeira -@idokoike, please file a GitHub Issue and fill out our form which includes you environment and OS, also include which steps did you take, e.g., did you run the DependencyInstaller.sh? If not, any reason why? - diff --git a/gh_discussions/Build/4269.md b/gh_discussions/Build/4269.md deleted file mode 100644 index a7323fc5e3818c940cdb117215db31aed41be4a1..0000000000000000000000000000000000000000 --- a/gh_discussions/Build/4269.md +++ /dev/null @@ -1,52 +0,0 @@ -# How to add new classes/structures to OpenROAD's schema? - -Tool: OpenDB - -Subcategory: Code generation issue - -## Conversation - -### fgaray -Hello OpenRoad devs, - -I am following https://github.com/The-OpenROAD-Project/OpenROAD/discussions/3619 to implement a structure to share scan chain data between OpenROAD's components but I am blocked at an compile issue. - -See: https://github.com/fgaray/OpenROAD/tree/ctl_db, path src/odb/src/codeGenerator/schema/scan - -I am adding 3 new *.json files: dbScanInst.json dbScanPartition.json dbScanPin.json - -In dbScanPin.json I am defining an "union" of dbBTerm and dbITerm - -In dbScanPartition.json I am trying to use dbScanPin for my "start" and "stop" fields. - - -I am running the ./generate script in src/odb/src/codeGenerator to generate the C++ code but I am getting the following error: - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/1619948/fc8774d8-b742-4407-86ef-e877d347f5d3) - -Looks like it is trying to use dbScanPin in the private dbScanPartition.h class, but if I change it to _dbScanPin in my dbScanPartition.json, then it fails in the public class definition in db.h. - -Is there an step that I am missing or maybe some config? - -Thanks! - - -### maliberty -Use dbId to store references to other db objects -``` - "name": "start", -- "type": "dbScanPin" -+ "type": "dbId" - }, - { - "name": "stop", -- "type": "dbScanPin" -+ "type": "dbId" - }, -``` - -### fgaray -I forgot to close this issue, but the answer was given by @maliberty . - -Writing the custom setter was the way to go when implementing this. - diff --git a/gh_discussions/Build/4956.md b/gh_discussions/Build/4956.md deleted file mode 100644 index 85e27e320a830de9a0acefec9460d86264919416..0000000000000000000000000000000000000000 --- a/gh_discussions/Build/4956.md +++ /dev/null @@ -1,67 +0,0 @@ -# OpenROAD Build From Sources - -Subcategory: Compilation error - -## Conversation - -### sebinho -Hello Guys, - -I am using ArchLinux and I have been using OpenROAD from an install package from the AUR. -This install does not seem to work anymore (it was working on my setup a couple of weeks ago). - -So I am trying to build from sources but I get the same errors as I get with the AUR package: -``` -[ 74%] Building CXX object src/gui/CMakeFiles/gui.dir/src/scriptWidget.cpp.o -In file included from /home/zed/repos/OpenROAD/src/gui/src/tclCmdInputWidget.h:50, - from /home/zed/repos/OpenROAD/src/gui/src/scriptWidget.cpp:49: -/home/zed/repos/OpenROAD/build/src/gui/tclSwig.h: In function ‘int SWIG_Tcl_GetArgs(Tcl_Interp*, int, Tcl_Obj* const*, const char*, ...)’: -/home/zed/repos/OpenROAD/build/src/gui/tclSwig.h:1623:11: error: ‘Tcl_Size’ was not declared in this scope; did you mean ‘Tcl_Time’? - 1623 | Tcl_Size *vlptr = (Tcl_Size *) va_arg(ap, void *); - | ^~~~~~~~ - | Tcl_Time -/home/zed/repos/OpenROAD/build/src/gui/tclSwig.h:1623:21: error: ‘vlptr’ was not declared in this scope; did you mean ‘vptr’? - 1623 | Tcl_Size *vlptr = (Tcl_Size *) va_arg(ap, void *); - | ^~~~~ - | vptr -/home/zed/repos/OpenROAD/build/src/gui/tclSwig.h:1623:40: error: expected primary-expression before ‘)’ token - 1623 | Tcl_Size *vlptr = (Tcl_Size *) va_arg(ap, void *); - | ^ -make[2]: *** [src/gui/CMakeFiles/gui.dir/build.make:226: src/gui/CMakeFiles/gui.dir/src/scriptWidget.cpp.o] Error 1 -make[2]: *** Waiting for unfinished jobs.... -[ 74%] Building CXX object src/rcx/src/CMakeFiles/rcxUnitTest.dir/__/test/ext2dBoxTest.cpp.o -In file included from /home/zed/repos/OpenROAD/build/src/gui/gui_autogen/UVLADIE3JM/../../../../../src/gui/src/tclCmdInputWidget.h:50, - from /home/zed/repos/OpenROAD/build/src/gui/gui_autogen/UVLADIE3JM/moc_tclCmdInputWidget.cpp:10, - from /home/zed/repos/OpenROAD/build/src/gui/gui_autogen/mocs_compilation.cpp:23: -/home/zed/repos/OpenROAD/build/src/gui/tclSwig.h: In function ‘int SWIG_Tcl_GetArgs(Tcl_Interp*, int, Tcl_Obj* const*, const char*, ...)’: -/home/zed/repos/OpenROAD/build/src/gui/tclSwig.h:1623:11: error: ‘Tcl_Size’ was not declared in this scope; did you mean ‘Tcl_Time’? - 1623 | Tcl_Size *vlptr = (Tcl_Size *) va_arg(ap, void *); - | ^~~~~~~~ - | Tcl_Time -/home/zed/repos/OpenROAD/build/src/gui/tclSwig.h:1623:21: error: ‘vlptr’ was not declared in this scope; did you mean ‘vptr’? - 1623 | Tcl_Size *vlptr = (Tcl_Size *) va_arg(ap, void *); - | ^~~~~ - | vptr -/home/zed/repos/OpenROAD/build/src/gui/tclSwig.h:1623:40: error: expected primary-expression before ‘)’ token - 1623 | Tcl_Size *vlptr = (Tcl_Size *) va_arg(ap, void *); - | ^ -[ 74%] Linking CXX executable dpl_test -``` - -Seems to be something related to Swig with TCL. Does anybody know what the problem is? - -Thanks for your help - - - -### maliberty -What version of TCL and swig do you have installed? - -### maliberty -Perhaps something is different in 4.2.1 as with 4.1.0 I don't see any used of Tcl_Size in tclSwig.h. Is it possible for you to downgrade? - -### stefanottili -Does anybody know how to downgrade swig on MacOS M1 homebrew ? -The current SWIG Version 4.2.1 causes the same error here. -Can be worked around by commenting out the two offending lines, they seem to be in an error path ... - diff --git a/gh_discussions/Build/5101.md b/gh_discussions/Build/5101.md deleted file mode 100644 index f7184f40e81aa0192af3044184e953a32f48f985..0000000000000000000000000000000000000000 --- a/gh_discussions/Build/5101.md +++ /dev/null @@ -1,31 +0,0 @@ -# OpenROAD build with recent versions of FMT and SPDLOG - -Subcategory: Dependency compatibility issues - -## Conversation - -### sebinho -I am not sure where to put this, but I had lots of issues lately building OpenROAD on ArchLinux and I thought this might help other people. -The issues I had seem to be related to more recent versions of spdlog and fmt packages. -Dowgrading fmt to 8.1.1-2 and spdlog to 1.13.0 solves the issues (latest versions are 10.2.0-1 and 1.14.1-1). - -The issues were as follows during the build (one example, others are similar): - -``` -/usr/include/fmt/core.h:1600:63: error: ‘fmt::v10::detail::type_is_unformattable_for, char> _’ has incomplete type - 1600 | type_is_unformattable_for _; - | ^ -/usr/include/fmt/core.h:1604:7: error: static assertion failed: Cannot format an argument. To make type T formattable provide a formatter specialization: https://fmt.dev/latest/api.html#udt - 1604 | formattable, - | ^~~~~~~~~~~ -/usr/include/fmt/core.h:1604:7: note: ‘formattable’ evaluates to false -``` - -The better way for me to solve my issue (instead of downgrading packages) was to build OpenROAD with the following flag during `cmake`: `-DSPDLOG_FMT_EXTERNAL=OFF` - -### rovinski -You might want to take a look at the dependency installer because this issue is known. It may not have support for Arch but you can look at comments for other distros for notes like this. - -### maliberty -Please see my comment about FMT_DEPRECATED_OSTREAM in https://github.com/The-OpenROAD-Project/OpenROAD/pull/2696 - diff --git a/gh_discussions/Configuration/2442.md b/gh_discussions/Configuration/2442.md deleted file mode 100644 index b45e9f510f0dbfad25880d8c9f31a7f2498eab7e..0000000000000000000000000000000000000000 --- a/gh_discussions/Configuration/2442.md +++ /dev/null @@ -1,20 +0,0 @@ -# Unable to find image 'openroad/flow-scripts:latest' locally - -Subcategory: Docker setup issue - -## Conversation - -### heaton56 -After install, trying to run the docker I get the following. ny ideas? - -Unable to find image 'openroad/flow-scripts:latest' locally -docker: Error response from daemon: pull access denied for openroad/flow-scripts, repository does not exist or may require 'docker login': denied: requested access to the resource is denied. - -### maliberty -How did you 'install' it? What command did you run that gave this message? - -### heaton56 -Thanks for you response, but I decided to do a local install of OpenROAD-flow-scripts instead, since I would have a learning curve with docker. - - - diff --git a/gh_discussions/Configuration/3350.md b/gh_discussions/Configuration/3350.md deleted file mode 100644 index e8d73e9786513a625ecbdf7d800fb2f6fd5bea4d..0000000000000000000000000000000000000000 --- a/gh_discussions/Configuration/3350.md +++ /dev/null @@ -1,41 +0,0 @@ -# Which distros to support - -Subcategory: Environment setup - -## Conversation - -### maliberty -Currently OR CI is built with -* Local centos7 gcc8 -* Local centos7 gcc8 without GUI -* Docker centos7 gcc8 -* Docker ubuntu20.04 gcc9 - -PRs additionally have GH actions that test: -* macOS (x86) -* c++20 (using clang-16) - -Centos7 is getting quite dated and I think it is time to replace it with a more modern distro. #3344 shows an example problem where qt5charts is not available in this older distro. I think Ubuntu 22 or Debian 11 are good contenders. - -I'd like community input as to what distro others are using with OR to help guide our choice. @antonblanchard @gadfort @QuantamHD @rovinski @msaligane @oharboe @donn @nayiri-k - -The default compiler version would be updated to match the distro default. - -FYI @vvbandeira @tspyrou - -### QuantamHD -Google is on Debian test called [Glinux](https://en.wikipedia.org/wiki/GLinux). Ubuntu 22 or Debian 11 seem like reasonable choices to me. - -But we use bazel to build everything from source so the biggest issue for me is if we start requiring very new versions of widely used libraries like Boost, because then I have to upgrade all of Google to use that version of software which can be a big pain. - -Google has a one version policy for any piece of software in the universe, and it's all stored in a monorepo. - -### donn -I use Nix as a build system, so as long as the CMakeFiles are generic enough to compile on both macOS, Ubuntu and CentOS I have no issues with the specific versions of the operating system. - -### rovinski -CentOS 7 is EOL on 2024-06-30. I know of machines that are still running it, so maybe it would be a good idea to hold off removing support until then. - -### olofk -As a data point, I wanted to mention that I just got it running on Gentoo, depending only on system packages except for or-tools - diff --git a/gh_discussions/Configuration/3943.md b/gh_discussions/Configuration/3943.md deleted file mode 100644 index 6b0a0cc3df392c73753e03e198e1e52bdf62cdc5..0000000000000000000000000000000000000000 --- a/gh_discussions/Configuration/3943.md +++ /dev/null @@ -1,35 +0,0 @@ -# How to develop the " setRC.tcl " file from a captable for a foreign PDK ? - -Tool: Parasitics Extraction - -Subcategory: Setting up foreign PDK - -## Conversation - -### faisaladilquadery -I have a foreign PDK which I want to invoke in openroad. But for that I need to develop the setRC.tcl file. How do I accurately input the resistance and capacitance for the setRC.tcl file . - -N.B : I have a captable for the pdk -I can also generate a spef file from Innovus for the PDK - -### maliberty -@vvbandeira @luarss do we have any documentation for correlateRC ? - -Note that if you LEF res & cap has values you can use those without a setRC to get started. - -### vvbandeira -@faisaladilquadery -We have a section on the `setRC.tcl` file configuration in our platform bring-up documentation. -https://openroad-flow-scripts.readthedocs.io/en/latest/contrib/PlatformBringUp.html#setrc-configuration - -### faisaladilquadery -Thankyou! @maliberty @vvbandeira . I have used the lef file in replacement of the setRC.tcl file . But I am getting **net delay** mismatch between the same path with the same cells for Innovus and OpenRoad. Any Idea why ? - -### faisaladilquadery -Thankyou @maliberty I have used the the RCX flow you mentioned to generate a rc tech file for my pdk and used the tech file to generate a spef in ORFS to obtain a more accurate RC. - -### b224hisl -> set_wire_rc is used to set a default layer to use when doing placement based parasitic estimation. There is no meaning to multiple layers here as there would be no way to divide up the estimate meaningfully. - -So I'm confused why it needs to set jsut one layer, do you mean only placement based parasitic estimation is related to `set_wire_rc` ? If there' s no way to divide up the estimate meaningfully, the layer can be set randomly? - diff --git a/gh_discussions/Configuration/4289.md b/gh_discussions/Configuration/4289.md deleted file mode 100644 index eea0ec4412f1066ea79e58e9bd901cd5d16fb678..0000000000000000000000000000000000000000 --- a/gh_discussions/Configuration/4289.md +++ /dev/null @@ -1,31 +0,0 @@ -# Disable LEF Warning Messages - -Tool: OpenDB - -Subcategory: Warnings and messages - -## Conversation - -### abaababa -Hi all, - -I am trying to load custom lef/lib files for pnr, and my lef files contain some properties unsupported by openroad. I got too much warning messages from this and the unsupported properties didn't have effect on my pnr results. Is there any way to disable the LEF warning messages temporarily? I checked the documents but failed to find an option that can turn off the warnings. Sorry if I missed it from the documents. - -Thanks in advance! - - - -### maliberty -There is no method to do that currently. No single message will print more than 1k times. - -### luarss -@maliberty Correct me if I am wrong, but doesn't Tcl function `suppress_message` do this? - -Edit: i guess there's no function that achieves full suppression for all warnings, what OP requested - -https://github.com/The-OpenROAD-Project/OpenROAD/blob/28892de3bef1af52f3371d547f752acf0af20021/test/helpers.tcl#L203 - -Corresponding source: -https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/utl/src/Logger.cpp - - diff --git a/gh_discussions/Configuration/4515.md b/gh_discussions/Configuration/4515.md deleted file mode 100644 index e34fa529376b740e8b575460e4a41c721f8b8ad4..0000000000000000000000000000000000000000 --- a/gh_discussions/Configuration/4515.md +++ /dev/null @@ -1,23 +0,0 @@ -# How do I avoid cells rotation in placement? - -Tool: Detailed Placement - -Subcategory: Cell placement rules - -## Conversation - -### OuDret -I need a cell that does not rotate in both global and detailed placement. Is there any way to achieve it? I did not find any parameter. - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/74424277/9d1b472c-dac6-4458-a3f6-f045e42abcfc) - -Thanks - - - -### maliberty -If it is a standard cell the LEF for the cell gives its symmetry. - -### maliberty -As this isn't a usual use case it has been lower priority. The simplest thing might be to just delete the rows that represent Y symmetry if you want to avoid such for your experiments. - diff --git a/gh_discussions/Configuration/5065.md b/gh_discussions/Configuration/5065.md deleted file mode 100644 index a0e5bf29f0a1720e77d46b410d0137e158ea1829..0000000000000000000000000000000000000000 --- a/gh_discussions/Configuration/5065.md +++ /dev/null @@ -1,155 +0,0 @@ -# howo to run openroad by reading an existing DEF file - -Tool: OpenDB - -Subcategory: Initialization from existing DEF - -## Conversation - -### bittnada -Hello -I have a DEF file in which row, track, components, and pins are written. -The position of the cells are on the step of global placement, obtained by using another method. -Now, I want to finish the rest of the procedures by modifying "test/flow.tcl" file. -I just skipped the steps of pin placement and global placement and added "read_def [my_def_fiel}'", but it did not work. -I will appreciate if anyone let me know how to solve this problem. -Thanks, - - - -### maliberty -What happened when it "did not work"? Its not much to go on. - -### bittnada - -Sorry for my delayed response. - -I've just conducted a test using gcd_nangate45.tcl, and I've created my own DEF file containing rows, tracks, pins, nets, and components. I performed a simple test by modifying a flow.tcl script to skip buffer insertion, IO placement, Macro Placement, tap cell insertion, power distribution, and global placement, and then adding "read_def". - -After running gcd_nangate45.tcl, I received the following output: - -==================================================================================== -OpenROAD v2.0-13652-g6fc686431 -Features included (+) or not (-): +Charts +GPU +GUI +Python -This program is licensed under the BSD-3 license. See the LICENSE file for details. -Components of this program may be licensed under more restrictive licenses which must be honored. -[INFO ODB-0227] LEF file: Nangate45/Nangate45_tech.lef, created 22 layers, 27 vias -[INFO ODB-0227] LEF file: Nangate45/Nangate45_stdcell.lef, created 135 library cells -[WARNING STA-0441] set_input_delay relative to a clock defined on the same port/pin not allowed. -[INFO IFP-0001] Added 57 rows of 422 site FreePDK45_38x28_10R_NP_162NW_34O. -[INFO ORD-0048] Loading an additional DEF. -Error: Chip already exists -[INFO RSZ-0058] Using max wire length 693um. -[INFO RSZ-0039] Resized 41 instances. -Placement Analysis ---------------------------------- -total displacement 17739.5 u -average displacement 49.0 u -max displacement 62.9 u -original HPWL 280.4 u -legalized HPWL 9839.7 u -delta HPWL 3410 % - -worst slack 0.105 -worst slack -0.011 -tns -0.011 -[INFO CTS-0050] Root buffer is BUF_X4. -[INFO CTS-0051] Sink buffer is BUF_X4. -[INFO CTS-0052] The following clock buffers will be used for CTS: - BUF_X4 -[INFO CTS-0049] Characterization buffer is BUF_X4. -[INFO CTS-0007] Net "clk" found for clock "core_clock". -[WARNING CTS-0041] Net "clk" has 0 sinks. Skipping... -[WARNING CTS-0083] No clock nets have been found. -[INFO CTS-0008] TritonCTS found 0 clock nets. -[WARNING CTS-0082] No valid clock nets in the design. -[INFO RSZ-0058] Using max wire length 693um. -Placement Analysis ---------------------------------- -total displacement 0.0 u -average displacement 0.0 u -max displacement 0.0 u -original HPWL 9839.7 u -legalized HPWL 9839.7 u -delta HPWL 0 % - -[INFO RSZ-0094] Found 1 endpoints with setup violations. -[WARNING RSZ-0075] makeBufferedNet failed for driver _393_/ZN -[WARNING RSZ-0075] makeBufferedNet failed for driver _393_/ZN -[WARNING RSZ-0075] makeBufferedNet failed for driver _393_/ZN -[WARNING RSZ-0075] makeBufferedNet failed for driver _393_/ZN -[INFO RSZ-0041] Resized 5 instances. -[INFO RSZ-0043] Swapped pins on 2 instances. -[INFO RSZ-0033] No hold violations found. -worst slack 0.106 -worst slack 0.000 -tns 0.000 -Placement Analysis ---------------------------------- -total displacement 91.3 u -average displacement 0.3 u -max displacement 6.4 u -original HPWL 9840.8 u -legalized HPWL 9925.0 u -delta HPWL 1 % - -[INFO DRT-0149] Reading tech and libs. - -Units: 2000 -Number of layers: 21 -Number of macros: 135 -Number of vias: 27 -Number of viarulegen: 19 - -Signal 11 received -Stack trace: - 0# 0x0000564758181A44 in /mnt/work/OpenROAD/bin/bin/openroad - 1# 0x00007F4028F54F10 in /lib/x86_64-linux-gnu/libc.so.6 - 2# odb::dbTechVia::getTopLayer() in /mnt/work/OpenROAD/bin/bin/openroad - 3# odb::dbWireEncoder::addTechVia(odb::dbTechVia*) in /mnt/work/OpenROAD/bin/bin/openroad - 4# drt::TritonRoute::stackVias(odb::dbBTerm*, int, int, bool) in /mnt/work/OpenROAD/bin/bin/openroad - 5# drt::TritonRoute::processBTermsAboveTopLayer(bool) in /mnt/work/OpenROAD/bin/bin/openroad - 6# drt::TritonRoute::initDesign() in /mnt/work/OpenROAD/bin/bin/openroad - 7# drt::TritonRoute::pinAccess(std::vector > const&) in /mnt/work/OpenROAD/bin/bin/openroad - 8# pin_access_cmd(char const*, char const*, char const*, int, int) in /mnt/work/OpenROAD/bin/bin/openroad - 9# 0x00005647589E491B in /mnt/work/OpenROAD/bin/bin/openroad -10# TclNRRunCallbacks in /usr/lib/x86_64-linux-gnu/libtcl8.6.so -11# 0x00007F402E79BFBA in /usr/lib/x86_64-linux-gnu/libtcl8.6.so -12# Tcl_EvalEx in /usr/lib/x86_64-linux-gnu/libtcl8.6.so -13# Tcl_Eval in /usr/lib/x86_64-linux-gnu/libtcl8.6.so -14# gui::TclCmdInputWidget::executeCommand(QString const&, bool, bool) in /mnt/work/OpenROAD/bin/bin/openroad -15# gui::CmdInputWidget::handleEnterKeyPress(QKeyEvent*) in /mnt/work/OpenROAD/bin/bin/openroad -16# gui::TclCmdInputWidget::keyPressEvent(QKeyEvent*) in /mnt/work/OpenROAD/bin/bin/openroad -17# QWidget::event(QEvent*) in /usr/lib/x86_64-linux-gnu/libQt5Widgets.so.5 -18# QFrame::event(QEvent*) in /usr/lib/x86_64-linux-gnu/libQt5Widgets.so.5 -19# QAbstractScrollArea::event(QEvent*) in /usr/lib/x86_64-linux-gnu/libQt5Widgets.so.5 -20# QPlainTextEdit::event(QEvent*) in /usr/lib/x86_64-linux-gnu/libQt5Widgets.so.5 -21# QApplicationPrivate::notify_helper(QObject*, QEvent*) in /usr/lib/x86_64-linux-gnu/libQt5Widgets.so.5 -22# QApplication::notify(QObject*, QEvent*) in /usr/lib/x86_64-linux-gnu/libQt5Widgets.so.5 -23# QCoreApplication::notifyInternal2(QObject*, QEvent*) in /usr/lib/x86_64-linux-gnu/libQt5Core.so.5 -24# 0x00007F402B1357B5 in /usr/lib/x86_64-linux-gnu/libQt5Widgets.so.5 -25# QApplicationPrivate::notify_helper(QObject*, QEvent*) in /usr/lib/x86_64-linux-gnu/libQt5Widgets.so.5 -26# QApplication::notify(QObject*, QEvent*) in /usr/lib/x86_64-linux-gnu/libQt5Widgets.so.5 -27# QCoreApplication::notifyInternal2(QObject*, QEvent*) in /usr/lib/x86_64-linux-gnu/libQt5Core.so.5 -28# QGuiApplicationPrivate::processKeyEvent(QWindowSystemInterfacePrivate::KeyEvent*) in /usr/lib/x86_64-linux-gnu/libQt5Gui.so.5 -29# QGuiApplicationPrivate::processWindowSystemEvent(QWindowSystemInterfacePrivate::WindowSystemEvent*) in /usr/lib/x86_64-linux-gnu/libQt5Gui.so.5 -30# QWindowSystemInterface::sendWindowSystemEvents(QFlags) in /usr/lib/x86_64-linux-gnu/libQt5Gui.so.5 -31# 0x00007F4022595260 in /usr/lib/x86_64-linux-gnu/libQt5XcbQpa.so.5 -32# g_main_context_dispatch in /usr/lib/x86_64-linux-gnu/libglib-2.0.so.0 -33# 0x00007F402783C770 in /usr/lib/x86_64-linux-gnu/libglib-2.0.so.0 -34# g_main_context_iteration in /usr/lib/x86_64-linux-gnu/libglib-2.0.so.0 -35# QEventDispatcherGlib::processEvents(QFlags) in /usr/lib/x86_64-linux-gnu/libQt5Core.so.5 -36# QEventLoop::exec(QFlags) in /usr/lib/x86_64-linux-gnu/libQt5Core.so.5 -37# QCoreApplication::exec() in /usr/lib/x86_64-linux-gnu/libQt5Core.so.5 -38# gui::startGui(int&, char**, Tcl_Interp*, std::__cxx11::basic_string, std::allocator > const&, bool) in /mnt/work/OpenROAD/bin/bin/openroad -39# ord::tclAppInit(Tcl_Interp*) in /mnt/work/OpenROAD/bin/bin/openroad -40# Tcl_MainEx in /usr/lib/x86_64-linux-gnu/libtcl8.6.so -41# main in /mnt/work/OpenROAD/bin/bin/openroad -42# __libc_start_main in /lib/x86_64-linux-gnu/libc.so.6 -43# _start in /mnt/work/OpenROAD/bin/bin/openroad -================================================================================================ - -I also examined the source codes and realized that the testing approach I employed did not yield the desired results. However, I am unsure about how to proceed from the step after global placement by reading the DEF file. - -Thanks. - diff --git a/gh_discussions/Configuration/5199.md b/gh_discussions/Configuration/5199.md deleted file mode 100644 index e073d28f793aaf769c51eadd92ef6e1af46bc27f..0000000000000000000000000000000000000000 --- a/gh_discussions/Configuration/5199.md +++ /dev/null @@ -1,24 +0,0 @@ -# Non-rectilinear core area - -Tool: Initialize Floorplan - -Subcategory: Floorplan customization - -## Conversation - -### Blebowski -Hello, - -is it possible to somehow specify core-area that is non-rectilinear (e.g. as a group of polygons surrounding concave shape) ? - -I understand that if doing "digital on top" FP where all the analog is a digital macro, this does not make sense. However, it may be usefull in case where "analog-on-top" is done, and digital may have some weird shape and is eventually placed as hard GDSII macro into analog-on-top design. - - - -### maliberty -The simplest would be to make a rectangular block and add placement and routing blockages for the disallowed area - -### Blebowski -Thanks. Can I then do the `add_pdn_ring` around just the cut area (e.g. L-shape pdn-ring) ? Or is there some other trick how -to achieve this ? - diff --git a/gh_discussions/Configuration/5213.md b/gh_discussions/Configuration/5213.md deleted file mode 100644 index cf8df559d659405dc4e57bc0dff985455754af64..0000000000000000000000000000000000000000 --- a/gh_discussions/Configuration/5213.md +++ /dev/null @@ -1,66 +0,0 @@ -# Running a simple combinatorial design - -Tool: OpenDB - -Subcategory: Module name mismatch - -## Conversation - -### Dandy201 -Hi all, I'm new to using ORFS and tried some tutorials from https://github.com/The-OpenROAD-Project/micro2022tutorial. -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/172090682/8a6e4ccd-503a-4751-8ead-8c1c5d209890) - -Completing exercise 5 got this simple output: -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/172090682/63ead36e-c51b-456b-9526-819d76f8a209). - -From this, I'm trying to make a simple combinational circuit. Running make DESIGN_CONFIG=../../half_Adder/config.mk, it always ends at this error: - -7. Executing Verilog-2005 frontend: /home/dan/Desktop/Work/vlsi/tools/OpenROAD-flow-scripts/flow/platforms/asap7/yoSys/cells_clkgate_R.v -Using ABC speed script. -[FLOW] Extracting clock period from SDC file: ./results/asap7/halfAdder/base/clock_period.txt -[FLOW] Setting clock period to 5 -8. Executing SYNTH pass. -8.1. Executing HIERARCHY pass (managing design hierarchy). -**ERROR: TCL interpreter returned an error: Yosys command produced an error -Command exited with non-zero status 1 -Elapsed time: 0:00.59[h:]min:sec. CPU time: user 0.56 sys 0.02 (99%). Peak memory: 72508KB. -make[1]: *** [Makefile:496: do-yosys] Error 1 -make: *** [Makefile:499: results/asap7/halfAdder/base/1_1_yosys.v] Error 2.** - -Config file -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/172090682/324abeb8-c78c-42a6-906f-811f9c4134b6) - -Constraint file -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/172090682/c305c964-35a7-4fae-b038-7cbb9539f98d) - -Verilog file -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/172090682/fe9cc773-67be-4235-a4b5-b66b06dee795) - - - - - -### maliberty -Please package this as a standalone test case and attach it. Reproducing it from screen shots is inefficient. - -### Dandy201 -[try.zip](https://github.com/user-attachments/files/15751707/try.zip) - -Here's the zip file along with the command : make DESIGN_CONFIG=../../try/config.mk - - -### mi-and-core -(1) change module name from 'half_adder' to 'halfAdder' - - -### maliberty -In the config.mk -``` -export DESIGN_NAME = halfAdder -``` -while in halfAdder.v: -``` -module half_adder( -``` -These names need to match. - diff --git a/gh_discussions/Documentation/4495.md b/gh_discussions/Documentation/4495.md deleted file mode 100644 index b5e4859ba61615e5169d2af89febb0c12272bc54..0000000000000000000000000000000000000000 --- a/gh_discussions/Documentation/4495.md +++ /dev/null @@ -1,27 +0,0 @@ -# pad_left/right units for GPL and repair_clock_inverters description - -Tool: Global Placement - -Subcategory: Missing information - -## Conversation - -### lustefan97 - - -I looked in OpenROAD documentation for Global Placement and Gate Resizer to get more detail about the units of the pad_left/right parameters of the `global_placement` command [(GPL)](https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/gpl) and the use/behavior of `repair_clock_inverters` [(RSZ).](https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/rsz/README.md) - -Both the variables units description is missing (while present for DPL (site count units), but since the two tools are different I don't want to assume it is the same for both) in GPL, and there is no description concerning `repair_clock_inverters` use case or behavior description (like there would be for `repair_timing` or `repair_design`. - -What are the units of pad_left/right, and what does `repair_clock_inverters` do/how to use it ? - -### maliberty -The units are sites from the LEF. - -repair_clock_inverters is useful when you have an inverter in the clock tree that would split the tree. It clones the inverter so you have one per flop instead. - -### maliberty -before CTS see https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/181e9133776117ea1b9f74dbacbfdaadff8c331b/flow/scripts/cts.tcl#L7 - -You might benefit from investigating how ORFS works - diff --git a/gh_discussions/Documentation/5312.md b/gh_discussions/Documentation/5312.md deleted file mode 100644 index bdeda7abf30c2fbe12bd7ab04fafd3dc12ff4bb0..0000000000000000000000000000000000000000 --- a/gh_discussions/Documentation/5312.md +++ /dev/null @@ -1,34 +0,0 @@ -# How to query odb database - -Tool: OpenDB - -Subcategory: Incomplete documentation - -## Conversation - -### titan73 -I want to directly query odb database. How can I do that? There is no command for that. -I found some ord::xxx commands by searching the net but there is no proper documentation with all commands. - -### titan73 -also found odb::xxx. No documentation either. -Most functions required a self argument. -Tested "::odb::dbBlock_getPowerDomains [::odb::dbBlock]" to get power domains but it crashes. - -### titan73 -I got to something using orf and odb to get the created power domains: - -foreach pd [::odb::dbBlock_getPowerDomains [::ord::get_db_block]] { - puts "[::odb::dbPowerDomain_getName $pd]" -} - -I think I get the idea. A pity it's not documented. - - -### maliberty -We use swig on https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/odb/include/odb/db.h so the APIs and comments there should be a guide. If you have specific questions please ask. - -### titan73 -Ok thanks. It helps. Although not all methods have comments. dbPowerDomain for instance. -How does int& is supposed to be mapped in tcl? Ex: bool getArea(int& x1, int& y1, int& x2, int& y2); - diff --git a/gh_discussions/Installation/2679.md b/gh_discussions/Installation/2679.md deleted file mode 100644 index 49de5d4cced74de9e7472c7042bbaf086f27ffbb..0000000000000000000000000000000000000000 --- a/gh_discussions/Installation/2679.md +++ /dev/null @@ -1,37 +0,0 @@ -# How can I run the OpenROAD GUI on Ubuntu locally and not in Docker? - -Tool: Graphical User Interface - -Subcategory: Local installation - -## Conversation - -### oharboe -How can I install and run the OpenROAD GUI locally? - -I want the advantages of Docker, not having to install everything, easy to deploy upgrades, but when I run the OpenROAD GUI from docker, the experience is pretty good, but not quite as good as running locally on Ubuntu. - -Another problem is that the OpenROAD-flow-scripts sets up a TON of environment variables, even if I had OpenROAD GUI installed locally, how could I get the envioronment set up correctly as I build various designs? - -Example of how I run the OpenROAD GUI in Docker. To run my own designs, I map results, log, objects, designs to my local drive by modifying the script in the github issue below. - -https://github.com/The-OpenROAD-Project/OpenROAD/issues/2675#issue-1513733033 - - -Ideally I'd like a debian package for the OpenROAD GUI. It seems like it should be possible to host a debian package on github, but it is a bit of work, especially considering that it probably needs to be built nightly to be truely useful in the open soruce development process: https://assafmo.github.io/2019/05/02/ppa-repo-hosted-on-github.html - - - -### QuantamHD -Creating a snap package in the CI might be a good option https://ubuntu.com/tutorials/create-your-first-snap#1-overview - -### maliberty -You would run the [dependency installer](https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/etc/DependencyInstaller.sh) and then compiler OR locally (build_openroad.sh --local). - -I'm surprised using docker makes much of a difference for the GUI. What do you see? - -You can always mount your directory in docker so envars shouldn't be a big issue. - -### mithro -Have you tried the conda packages? - diff --git a/gh_discussions/Installation/2971.md b/gh_discussions/Installation/2971.md deleted file mode 100644 index caeba2e44846b9f5d74c9c3ad710522eebfa154c..0000000000000000000000000000000000000000 --- a/gh_discussions/Installation/2971.md +++ /dev/null @@ -1,43 +0,0 @@ -# Arm64 Support - -Subcategory: Architecture compatibility - -## Conversation - -### DylanTom -Hi, I am looking to use OpenROAD and have tried to install it on my computer. - -It is an M2 Pro Macbook Pro, 32 GB RAM, 1TB SSD. I am running an Ubuntu VM through UTM which has 8GB RAM and 64 GB SSD. - -I am having trouble with building OpenROAD because one of the dependencies is `or-tools`, which does not appear to have Ubuntu support for the ARM architecture. I was wondering if anyone had similar issues or would know how to resolve this. - -Specifically, does OpenROAD support the ARM architecture, and if not, is that a priority in the future? - -Thanks! - -### vijayank88 -Can you try OpenROAD-flow-scripts with docker based: https://openroad-flow-scripts.readthedocs.io/en/latest/user/BuildWithDocker.html#clone-and-build - -### maliberty -We do not officially support it as we don't have the hardware resources to test on that platform. We do try to make sure we can compile on mac M1 based systems. That said or-tools is available for arm64 as Vijayan pointed out. - -### vvbandeira -> Note: OR-Tools only provides archives for the x86_64 (also known as amd64) architecture. -Source: https://developers.google.com/optimization/install/cpp/binary_linux - -@DylanTom If you are already using a VM, you can create a x86_64 VM and avoid this issue. - -### stefanottili -If you're on M2, why not give "native" OR a try ? - -I've been compiling it on and off using HomeBrew for dependencies (including or-tools) for a while now. -or-tools and mpl2 keep on breaking the build and mpl2 is still be disabled. ->> -- Removing MPL2 and PAR to avoid run time fatal error. - -So occasionally it doesn't work, but most of the times I got it to compile in < 15min on a M1. - -etc/DependencyInstaller.sh (unforunately now installs x86 klayout, I prefer building it natively) -./build_openroad.sh --local --latest --clean-force (breaks today in a mpl2 test) -./build_openroad.sh --local (when run again it finishes, go figure) - - diff --git a/gh_discussions/Installation/2972.md b/gh_discussions/Installation/2972.md deleted file mode 100644 index 679ec966ab821f06135e880b76dc0bbafd46804a..0000000000000000000000000000000000000000 --- a/gh_discussions/Installation/2972.md +++ /dev/null @@ -1,102 +0,0 @@ -# CMAKE errors while installing Openroad - -Subcategory: Build issues - -## Conversation - -### mdzaki-git -HI All, - -After installing the dependencies we re stuck with cmake errors and would appreciate your help in fixing them. Attaching the error snippet for reference. -Cmake Error - - -### vijayank88 -attach log `build_openroad.log` - -### mdzaki-git -[openroad_build.log](https://github.com/The-OpenROAD-Project/OpenROAD/files/10897535/openroad_build.log) - - -### mdzaki-git -Following the install instruction mentioned on git hub. -https://github.com/The-OpenROAD-Project/OpenROAD - -### mdzaki-git -Hi Vitor, - -Recloned the repository and tried again, getting below errors now. - - - -On Mon, Mar 6, 2023 at 7:32 PM Vitor Bandeira ***@***.***> -wrote: - -> @vijayank88 , this warning is not a -> problem with CMake; this indicates that the folder is not a git repo. -> @mdzaki-git , can you make sure that the -> clone ended fine? Maybe check the output of git status --long, the output -> of this command should look something like this: -> -> > git status --long -> On branch master -> Your branch is up to date with 'origin/master'. -> nothing to commit, working tree clean -> -> Also, try to do a clean build and in case of any errors upload the new log -> file. -> -> ./etc/Build.sh -clean -> -> — -> Reply to this email directly, view it on GitHub -> , -> or unsubscribe -> -> . -> You are receiving this because you were mentioned.Message ID: -> github.com> -> - - -### mdzaki-git -[openroad_build.log](https://github.com/The-OpenROAD-Project/OpenROAD/files/10899446/openroad_build.log) - - -### vvbandeira -Looks like you missed the `--recursive` when cloning. Please run - -``` -git submodule update --init -``` - -In the future you should use `git clone --recursive` to also clone the submodules `abc` and `sta`. - -### mdzaki-git -Hi All, - -Thanks it works now. - -On Mon, Mar 6, 2023 at 9:37 PM Vitor Bandeira ***@***.***> -wrote: - -> Looks like you missed the --recursive when cloning. Please run -> -> git submodule update --init -> -> In the future you should use git clone --recursive to also clone the -> submodules abc and sta. -> -> — -> Reply to this email directly, view it on GitHub -> , -> or unsubscribe -> -> . -> You are receiving this because you were mentioned.Message ID: -> github.com> -> - - diff --git a/gh_discussions/Installation/3004.md b/gh_discussions/Installation/3004.md deleted file mode 100644 index 9de2a999c5db1ddaed535b875b9d02400f8918b9..0000000000000000000000000000000000000000 --- a/gh_discussions/Installation/3004.md +++ /dev/null @@ -1,107 +0,0 @@ -# openRoad installation - -Subcategory: Dependency issues - -## Conversation - -### msingh9 -I was successfully able to run cmake and then make. However, output of cmake has following two messages which seems problematic to me. How do I resolve these? - --- GUI is not enabled --- Could NOT find VTune (missing: VTune_LIBRARIES VTune_INCLUDE_DIRS) - -I ran following command -cmake .. -DCMAKE_INSTALL_PREFIX=/home/msingh/openRoad -DPYTHON_INCLUDE_DIR=$(python3 -c "import sysconfig; print(sysconfig.get_path('include'))") -DPYTHON_LIBRARY=$(python3 -c\ - "import sysconfig; print(sysconfig.get_config_var('LIBDIR'))") - -I also ran make afterwards, which seems to finish. There are bunch of warnings but no error message. Where do I find the executable. I don't find it in CMAKE_INSTALL_PREFIX/bin directory. - -Does it mean that installation didn't complete? - -I am looking for some help because I am stuck in the installation. - -I just cleared the buffer that has log, but I can redo those steps if you need the complete log output. - -### maliberty -Vtune is unimportant unless you are a developer of OR. - -The GUI suggests that you don't have Qt installed. Did you run the dependency installer? - -### msingh9 -Thanks Maliberty for response. - -I followed the steps "https://openroad-flow-scripts.readthedocs.io/en/latest/user/BuildLocally.html" and was able to build with hiccups. -How do I make sure Qt is installed? BTW - I am trying to install it on Linux RH8. Is it supported platform? - -When I try to invoke it, I get this missing library error. -openroad -help -openroad: error while loading shared libraries: libortools.so.9: cannot open shared object file: No such file or directory - - -### maliberty -I don't know what OS you are on and you haven't included any logs. If you look at https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/etc/DependencyInstaller.sh it you'll see it references Qt libraries. - -### msingh9 -I am trying to build it on RH8. I am really stuck at this point now. I ran "sudo ./DependencyInstaller.sh" successfully. - -I can check that qt5 is installed. - -[msingh@lnx-msingh cv6 /tmp]$ sudo yum -y install qt5-srpm-macros.noarch -Last metadata expiration check: 0:07:51 ago on Sun 12 Mar 2023 12:19:34 AM PST. -Package qt5-srpm-macros-5.12.5-3.el8.noarch is already installed. -Dependencies resolved. -Nothing to do. - -When I run cmake to create build files, I get that "GUI is not enabled". Is there a switch I need to pass to cmake. Here is my command and it's output. - -[msingh@lnx-msingh cv6 build]$ cmake .. -DPYTHON_INCLUDE_DIR=/cv6/tools2/tv2/release/Python3/3.9.0/include/python3.9 -DPYTHON_LIBRARY=/cv6/tools2/tv2/release/Python3/3.9.0/lib -Dortools_DIR=/opt/or-tools --- OpenROAD version: v2.0-7131-g1d8d24209 --- System name: Linux --- Compiler: GNU 8.3.1 --- Build type: RELEASE --- Install prefix: /usr/local --- C++ Standard: 17 --- C++ Standard Required: ON --- C++ Extensions: OFF --- TCL library: /usr/lib64/libtcl.so --- TCL header: /usr/include/tcl.h --- TCL readline library: /usr/lib64/libtclreadline.so --- TCL readline header: /usr/include --- Found Boost: /usr/local/lib/cmake/Boost-1.80.0/BoostConfig.cmake (found version "1.80.0") --- boost: 1.80.0 --- spdlog: 1.8.1 --- STA version: 2.4.0 --- STA git sha: f84e617fc435d2d280a3f76045aa461afa386e2b --- System name: Linux --- Compiler: GNU 8.3.1 --- Build type: RELEASE --- Build CXX_FLAGS: -O3 -DNDEBUG --- Install prefix: /usr/local --- TCL library: /usr/lib64/libtcl.so --- TCL header: /usr/include/tcl.h --- SSTA: 0 --- STA executable: /dump/vlsidump302/msingh/OpenROAD/src/sta/app/sta --- GPU is not enabled --- GUI is not enabled --- Found Boost: /usr/local/lib/cmake/Boost-1.80.0/BoostConfig.cmake (found version "1.80.0") found components: serialization --- Could NOT find VTune (missing: VTune_LIBRARIES VTune_INCLUDE_DIRS) --- Found Boost: /usr/local/lib/cmake/Boost-1.80.0/BoostConfig.cmake (found suitable version "1.80.0", minimum required is "1.78") --- Found Boost: /usr/local/lib/cmake/Boost-1.80.0/BoostConfig.cmake (found version "1.80.0") found components: serialization system thread --- TCL readline enabled --- Tcl Extended disabled --- Python3 disabled --- Configuring done --- Generating done --- Build files have been written to: /dump/vlsidump302/msingh/OpenROAD/build - - -### maliberty -What OS are you using? Is qt in the default location? - -### vijayank88 -@msingh9 -Can you try docker based installation [steps](https://openroad-flow-scripts.readthedocs.io/en/latest/user/BuildWithDocker.html) ? - -### msingh9 -Thank you everyone for support. I finally managed to make it work on RH8. It is exciting to see this tool in action. I really like to appreciate everyone effort to make this open-source magic. I will post my results once I can make it work. - diff --git a/gh_discussions/Installation/4162.md b/gh_discussions/Installation/4162.md deleted file mode 100644 index 8e2a6548db2e6a3a6345dda988e7abf4818f4ed1..0000000000000000000000000000000000000000 --- a/gh_discussions/Installation/4162.md +++ /dev/null @@ -1,23 +0,0 @@ -# Libfmt v8 required for conda installation - -Subcategory: Dependency issue - -## Conversation - -### chetanyagoyal -Trying to use -openroad==2.0_10145_g0de6f5131 installed with conda gives the following error - -`openroad: error while loading shared libraries: libfmt.so.8: cannot open shared object file: No such file or directory` - -This error occurs only on Ubuntu20.04 because libfmt version 8 does not exist for it. -Are there any workarounds to this? - -### rovinski -I don't think we host a conda installation. The installer would be from a third party and you should ask them for support. - -### maliberty -@proppy is the conda installer something you support? - -### proppy -yes, it seems they already filed an issue over at https://github.com/hdl/conda-eda/issues/360 (so feel free to close the issue here). - diff --git a/gh_discussions/Installation/4653.md b/gh_discussions/Installation/4653.md deleted file mode 100644 index e611e455748dd20efeb898f558c28fcc02d85e9e..0000000000000000000000000000000000000000 --- a/gh_discussions/Installation/4653.md +++ /dev/null @@ -1,20 +0,0 @@ -# Openroad and QtCharts - -Tool: Graphical User Interface - -Subcategory: Library dependency issue - -## Conversation - -### pguerr91 -I installed openroad on RHEL8 using the documentation from GitHub. After launching openroad -gui, I noticed that it mentions QtCharts is not installed. So I built and compiled it (from source qtcharts-everywhere-src-5.15.0.zip), and and it appears to have installed in /usr/include/qt5/QtCharts ..but when I launch openroad -gui again , it STILL says "QtCharts not installed" ..(see attachment) Any ideas on what to do ?? This doesn't appear to be very straightforward - -![openroad_QtCharts_missing](https://github.com/The-OpenROAD-Project/OpenROAD/assets/47336735/70f5288c-1aa8-447b-ac35-0c0cfb27bee0) - - -### maliberty -Cmake does some caching so I suggest removing your build directory and re-running cmake to see if it then finds it. - -### maliberty -Is the rest of Qt installed in the same area? - diff --git a/gh_discussions/Query/1539.md b/gh_discussions/Query/1539.md deleted file mode 100644 index 52aa80a4dd98af9b84c9f6a02aaa15f9b5c4dbb6..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/1539.md +++ /dev/null @@ -1,21 +0,0 @@ -# CTS Characterization - -Tool: Clock Tree Synthesis - -Subcategory: Customization request - -## Conversation - -### EffeErreG4 -I was trying to customize the CTS parameters using the command "configure_cts_characterization", but I don't see any changes is the maximum slew constrain reported in the .log file. Trying to understand if I was doing something wrong I noticed that there's a file called "CtsOptions.h" that should set the desired constrains with no "CtsOptions.cpp" file to describe the actual function. How can I manage to customize the maximum transition time? Thanks for your attention. - -### maliberty -All the functions are inlined so there is no need for a cpp. - -Would you give the command you are using and the message you are getting in the log. - -### EffeErreG4 -Sorry if I made a silly observation. -I was trying to define the maximum limits of slew and maybe I misunderstood the command. -Is it possible to change the values of maximum slew and maximum skew constrain for the CTS synthesis? - diff --git a/gh_discussions/Query/1610.md b/gh_discussions/Query/1610.md deleted file mode 100644 index a2985e8d94bcd04966fc049cd6353a6dcb0af757..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/1610.md +++ /dev/null @@ -1,144 +0,0 @@ -# How to get heatmap data? - -Tool: Graphical User Interface - -Subcategory: Data extraction - -## Conversation - -### gudeh -Hi guys, congratulations on all the great job done with the OpenROAD project!! I want to use it to develop my ideas during my Ph.D. - -I am trying to build a dataset for graph neural network training. My idea is to perform physical design predictions with a mapped circuit before P&R. I am trying to extract features from Verilog with Yosys, send them to the DGL python library and perform training with DGL. These steps are already operational, but I am missing an essential aspect of the prediction: the label! - -To solve the mentioned issue **I would like to have the data shown by the heatmaps in the GUI, such as placement density and routing congestion**. I would like them not as images but the actual numeric values. The positions of the cells and wires would also be essential. - -- Can anyone point me to which path I should go to get this data? I understand all of it is already processed by the code to show the images in the GUI. I just need to find it. -- Would there be any TCL command which could help me with that? -- Or my best shot is to try and use the odb database and edit some code? - -I noticed there are some heatmap codes in [./src/gui/src](https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/gui/src), but there are so many attributes and methods. Also, I am not used to the odb database yet. Any help is welcome. - -### gudeh -By the way I couldn't find the path `./build/src/swig/tcl/opendbtcl` and `./build/src/swig/tcl/opendb_wrapper.cpp` as mentioned in [the documentation](https://openroad.readthedocs.io/en/latest/main/src/odb/README.html). - -### maliberty -The bit of documentation is out of date as we now include the tcl functionality in openroad itself and no longer build standalone executables for odb. (@vvbandeira) - -@arlpetergadfort My first thought was to look at each engine but maybe it would be easier to provide a dump_heatmap command in the GUI since it has already abstracted the interface to each engine. Does that seem reasonable to you? - -### maliberty -#1612 is merged so you should be good to go. - -### maliberty -You are repeating the previous rule and probably want something like: - -my_gui: my_gui_6_final.def -$(foreach file,$(RESULTS_DEF),my_gui_$(file)): my_gui_%: - -You are getting the bbox of each instance. You'll have to map that back to the grid you are working with (an instance may be across a boundary as well). - -### gudeh -Hey guys, I have some issues with the heatmap features. I noticed that running the GCD project from a fresh OpenROAD-flow with this exact sequence of commands: -``` -git clone --recursive https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts.git -cd OpenROAD-flow-scripts/ -sudo ./build_openroad.sh --local -cd flow -make -make gui_final -``` -Renders no output on the circuit's image when clicking on the checkbox for `Placement Density`. The `Power Density` checkbox works fine. Furthermore, clicking on `Routing Congestion` and `IR Drop` gives the error message bellow and shows no heatmap in the image. -``` -[WARNING GUI-0066] Heat map "Routing Congestion" has not been populated with data. -[WARNING GUI-0066] Heat map "IR Drop" has not been populated with data. -``` - -If I run the AES project I can see the Placement and Power heatmaps. Although I have the same errors with Routing and IR Drop. - -The Routing and IR Drop also gives errors when trying to call gui::dump_heatmap: `[ERROR GUI-0072] "Routing Congestion" is not populated with data.` -I also noticed that the CSVs provided by the gui::dump_heatmap command gives bouding boxes with different sizes for Placement and Power, is this expected? - - -### maliberty -I don't see any issue with placement density. This is gcd/ng45: -![image](https://user-images.githubusercontent.com/761514/153918958-d33becda-6a06-417a-a685-463e6076575a.png) - - -### maliberty -@arlpetergadfort I'm seeing: -``` ->>> read_guides results/nangate45/gcd/base/route.guide -[WARNING GUI-0066] Heat map "Routing Congestion" has not been populated with data. -``` -This used to work - do you know what has changed? - -### gudeh -Hi again! I am progressing with my dataset generation. Looking real promising. I am only having issues trying to close the gui. Even if I use gui::hide it goes to the `openroad>` command option in terminal. How can I exit it the gui AND the openroad afterwards via a TCL file? [This is what I have tried](https://github.com/gudeh/OpenROAD-flow-scripts/blob/master/flow/scripts/getLabels.tcl). As seen in the last lines. - -By the way if you uncoment the part where I try to use the Routing and IRdrop heatmaps the gui::hide doesn't work. - -### gudeh - - -### gudeh -Hi everyone! I am coming back to this project. I was focusing on other tasks the last months. - -I wanted to share with you an example of what my code is able to generate by editing Yosys and OpenROAD: https://drive.google.com/drive/folders/1xTz4iTuGx0bDD-ZWAOV-MDQWKI0a8XA8?usp=sharing . - -This pair of CSV files can be used as input for DGL Python library and create a GNN. - -There is an issue though, I created a [Python script to check for collisions among the heatmaps and logic gate locations,](https://github.com/gudeh/OpenROAD-flow-scripts/blob/master/flow/myStuff/gateToHeat.py) and it is really slow. I made it by comparing the location of all the gates against each of the 4 heat types. I would like to ask any suggestions on how to improve this. Is this able to be solved on the OpenROAD db? - -### maliberty -The link to your script is broken. The heatmaps are a grid so it should be easy to compute the index into the map. - -Matt - -### gudeh -Hello again! I found a bug on my code to retrieve learning data using OpenROAD. The logic gate names don't match! - -My machine learning model features come from the verilog generated during the flow. Optionally I can use the 1_1_yosys.v ( post tech map ) or the 6_final.v ( post route ). Afterwards I get the labels using some TCL commands discussed previously in this post. For example: - - -> set dut gatesPosition_ -> set fileName ${designPath}/${dut}${::env(DESIGN_NAME)}.csv -> set outFile [open $fileName w] -> puts $outFile "Name,xMin,yMin,xMax,yMax" -> set block [ord::get_db_block] -> foreach inst [$block getInsts] { -> set box [$inst getBBox] -> puts $outFile "[$inst getName], [ord::dbu_to_microns [$box xMin]], [ord::dbu_to_microns [$box yMin]], [ord::dbu_to_microns [$box xMax]], [ord::dbu_to_microns [$box yMax]]" -> } -> close $outFile - -At last, I have to build up my dataset by matching the logic gates names from the verilog, the logic gate names(from the TCL snippet pasted here and the heatmap dumps (positions). **But there is a problem:** - -I noticed that sometimes the flow changes the names of the gates between the verilog and the names retrieved from the TCL command ( `[$inst getName]`) causing unexpected behavior when I build the dataset. For example, the design bp_be_top with nangate45, there is a gate called `\be_calculator/_09864_` in the 6_final.v, and the name I get with the TCL command is `be_calculator/_09864_` without the `\`. - -**My question is:** Is there anyway to be sure that OR flow won't change the names of the gates? If not when and how does the tool changes the names of the gates, does it simply remove the starting `\` or are there any other possible modifications? - -### gudeh -Hi guys, I have another doubt regarding the heatmaps provided by OR. I would like to make sure the behavior is as intended. This is the routing congestion heatmap when executing the Rocket Tile design with standard values (config.mk) given by the repository: -![image](https://user-images.githubusercontent.com/37420320/230185344-17959d7b-05b3-4ee8-ab04-6865fb097f41.png) - -After executing the flow, OR inserts a lot of Filler Cells. It seems that the standard core size for Rocket Tile is extremely large, is there a reason for that? - -I ran the flow with the same design, although dividing the max X and max Y core area values in half and leaving the die area as is: - -> export DIE_AREA = 0 0 924.92 799.4 -> #export CORE_AREA = 10.07 9.8 914.85 789.6 -> export CORE_AREA = 10.07 9.8 457.425 394.8 - -And this is the routing congestion heatmap after execution. There is still a considerably high congestion between core and die: -![image](https://user-images.githubusercontent.com/37420320/230186482-44fd0f4f-85d4-4fcc-afa1-ed0b05a1635d.png) - -To confirm, this is the placement density after the same run: -![image](https://user-images.githubusercontent.com/37420320/230188189-c3be97c8-c7a9-4f42-b78d-03918a202baf.png) - - -This seems strange to me. I wouldn't expect so much routing congestion between die and core area. Furthermore, I couldn't even see metal wires on the green congested area. Is this as supposed to? - -### gudeh -Hello again. I wonder if there is a way to get the heatmaps considering only certain metal layers, is that possible? - diff --git a/gh_discussions/Query/1732.md b/gh_discussions/Query/1732.md deleted file mode 100644 index 7ad3185c59f7055995e9e4623e114d11a8702857..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/1732.md +++ /dev/null @@ -1,52 +0,0 @@ -# Can the grid/clips in the TritonRoute be exported? - -Tool: TritonRoute - -Subcategory: Information request - -## Conversation - -### Mohamed-Mejri -Hello, -I would like to know if the grid can be exported after the processing of the global router output and/or the TA step. - -I'm planning on trying some other AI based approaches instead of Heuristics. And if I can export the grid or the clips it would be more helpful. - -Any idea/help will be much appreciated! - -### maliberty -Do you mean the gcell grid? There are messages - -"GCELLGRID X {} DO {} STEP {} ;", -"GCELLGRID Y {} DO {} STEP {} ;", - -that will give you those values. They don't change during drt. - -### maliberty -The post-processed guides are generated as output_guide.mod in ORFS (controlled by -output_guide). Other internal state of the router is not exported today. - -### maliberty -Its the same guide format as the input guide file - -### Mohamed-Mejri -Hello again, -I would like to get the access points to each pin in a net and I saw [this on another discussion](https://github.com/The-OpenROAD-Project/OpenROAD/discussions/625?sort=new#discussioncomment-636424), however, when I tried it the coordinates didn't make sense. -For example when I try it on the nangate45 gcd, for the _000_ net we have: `_000_ ( _672_ D ) ( _504_ ZN ) + USE SIGNAL` -and the components in the net are `_672_ DFF_X2 + PLACED ( 107540 145600 ) N ;` and `_504_ OAI21_X1 + PLACED ( 107540 148400 ) FS ;` -and this is the output of the code -net _000_ -( 46930 141260 ) layerNum 2 metal1 -( 46930 141120 ) layerNum 2 metal1 -( 46740 141260 ) layerNum 2 metal1 -( 51490 146580 ) layerNum 2 metal1 -( 51490 146860 ) layerNum 2 metal1 -( 51490 147140 ) layerNum 2 metal1 -( 51490 147420 ) layerNum 2 metal1 -( 50730 147420 ) layerNum 2 metal1 -( 51870 147420 ) layerNum 2 metal1 -( 51870 147700 ) layerNum 2 metal1 -( 51870 147980 ) layerNum 2 metal1 -( 51110 147420 ) layerNum 2 metal1 - -So from what I see these coordinates can't be correct, any idea why is this happening? - diff --git a/gh_discussions/Query/1870.md b/gh_discussions/Query/1870.md deleted file mode 100644 index 381576697856e6f4c95756b6a2b9ed5d1a822967..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/1870.md +++ /dev/null @@ -1,20 +0,0 @@ -# Does detail router support spacing between different cut layers? - -Tool: Detailed Routing - -Subcategory: Tool capability - -## Conversation - -### davidcarails -I have seen an example of a via/cut spacing rule between different layers. -For example : v4 space v5 >= 38 -Can/does the detailed router support this? - -### maliberty -Its helpful to ask about a specific LEF rule but yes it does support cut spacing between layers. - -### maliberty -![image](https://user-images.githubusercontent.com/761514/169117659-453ea3a8-10cb-4794-bb41-16558182e3f8.png) - - diff --git a/gh_discussions/Query/2083.md b/gh_discussions/Query/2083.md deleted file mode 100644 index 955dfce034ea54cee0c13bf835908614a0b18fcd..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/2083.md +++ /dev/null @@ -1,93 +0,0 @@ -# How to contribute? - -Subcategory: Contribution inquiry - -## Conversation - -### niv280 -Hi, There is any way to contribute to the openRoad project? - -### QuantamHD -They accepted code changes through PRs. - -Is there something you are interested in working on? - -### maliberty -We are glad to have contributors. Do you want some suggestions or do you have something in mind? - -### maliberty -To help narrow it a bit are you more interested in development, testing, documentation, outreach? If you are willing to share a bit about yourself it would help to find a task of appropriate complexity. - -On the development side one idea that comes to mind is to improve write_abstract_lef written by @QuantamHD to give more precise obstructions. I can describe that further if it is of interest. - -### maliberty -The LEF abstract is a physical model of a block that is intended to be used at a higher level in the hierarchy to model the interface and obstructions in the block. The current code starts from https://github.com/The-OpenROAD-Project/OpenROAD/blob/c4a8479c341c31fd0db26a17f4a909f59285cf58/src/odb/src/lefout/lefout.cpp#L1213 - -The current code is rather simplistic in its modeling of obstructions. If you look at lefout::getTechLayerObstructions it just gathers a set of layers that have any shapes on them and then blocks the entire layer. - -I think it would be better to use Boost polygon to OR together the shapes on each layer; do a bloat then shrink cycle to merge them into simpler shapes and then write out the result as the layer obstruction. The amount of bloating could be a user control with a reasonable default (say 2*pitch). - -The goal is to balance model size with precision. Does this make sense? I can go into more detail where needed. - -### stefanottili -Please keep in mind that there are two types of abstracts used by $$$ tools. The “cutout” where obstructions are cut out around pins and the “cover everything” where the pins are at the edges and the block is completely covered with obstruction. For the latter to work, the router has to be smart enough to route to covered pins and drc has to know that covered pins on the edge are ok too. It’s good practice to have pins on the edge of blocks anyways. - -### maliberty -You can see gcd_abstract* in https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/odb/test for two examples. - -The idea of the bloat/shrink cycle is to merge nearby shapes. I've tried to quickly illustrate it with: -![image](https://user-images.githubusercontent.com/761514/180689779-273f4b34-d299-4251-a372-10437d7c246a.png) - -You can learn about Boost polygon at https://www.boost.org/doc/libs/1_79_0/libs/polygon/doc/index.htm (the docs aren't great). - -### maliberty -The red boxes in the middle image merge together into a single polygon - -### niv280 -Hi, I will love to get some help in 2 issues. -First I will need to import to boost::polygon library, in which file can I do it? Do other part of the code already import it? - -Second, I having trouble to understand how can I test my change, I gather all the shapes into kind of list and I now write it into the lef file instead the whole block boundary bbox, but I probably got some mistake so I want to run some test to debug it. -There is any tutorial how can I do it? - -### niv280 -Hi, So I make some progress with the abstract lef. -But I encounter on some problem that I would like to get some help. - -So I modify the abstract lef that in order to write the merge between all the rect that intersect ( after bloat ). -To demonstrate it I edit the picture from above: - -![image](https://user-images.githubusercontent.com/61157132/186626392-73d8ee81-e11e-4ba1-8e75-b7668e319b47.png) - -The green rect is currently my OBS which isn't very efficient, but i didn't found any easy way to do it with the utils in the rect class. - -So I am guessing that I need to go back to your first suggestion which is use boost polygon to OR all the rect, my problem is that is after that I will need to convert it back into different rects, there is any easy way to do that? - - - -### stefanottili -https://www.boost.org/doc/libs/1_79_0/libs/polygon/doc/gtl_polygon_90_set_concept.htm - -Have a look at get_rectangles and get_max_rectangles - -On Aug 25, 2022, at 02:20, niv280 ***@***.***> wrote: - - -Hi, So I make some progress with the abstract lef. -But I encounter on some problem that I would like to get some help. - -So I modify the abstract lef that contained the merge between all the rect that intersect. -To demonstrate I edit the picture above: - - - -The green rect is currently my OBS which isn't very efficient, but i didn't found any easy way to do it with the utils in the rect class. -So I am guessing that I need to go back to your first suggestion which is use boost polygon to OR all the rect, my problem is that is after that I will need to convert is back into different rects, there is any easy way to do that? - -— -Reply to this email directly, view it on GitHub, or unsubscribe. -You are receiving this because you commented. - -### maliberty -get_rectangles would be the better choice as get_max_rectangles may produce overlapping rectangles. You an experiment with the slicing direction to see what produces a more minimal result. My guess is the non-preferred routing direction will work best. - diff --git a/gh_discussions/Query/2745.md b/gh_discussions/Query/2745.md deleted file mode 100644 index b6f7bfd53e0b21b0ad170a57a99eee24851d4f1f..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/2745.md +++ /dev/null @@ -1,305 +0,0 @@ -# Options in the Python API - -Tool: Global Placement - -Subcategory: Usage question - -## Conversation - -### maliberty -The python api differs from tcl in being more OO (objects/methods) rather than command oriented. I'd like to discuss standardizing how that API accept options. Current APIs are variable: -- Some use state building commands. For example pdn has define_pdn_grid, add_pdn_stripe, etc. -- Some persistently hold an options object that can be modified by the user. For example TritonCTS::getParms() -- Some take their options as arguments. For example Resizer::repairHold(...) - -Complicating cases are: -- Tools that call other tools. For example gpl calls grt and rsz -- Incremental operations that retain state between invocations. For example grt and sta - -My best thought on how to standardize is to have a persistent set of default options and the ability to pass an overriding set. A sketch of the idea: -``` -class ToolOptions -{ -public: - ToolOptions(); // a well-defined default state - void setOptionA(int value); - void setOptionB(bool value); -}; - -class Tool -{ -public: - static ToolOptions* getDefaultOptions(); - - // if options is nullptr then the default options are used. - void task(ToolOptions* options = nullptr); - -private: - static ToolOptions* default_options_; -}; -``` - -One use model would be pre-configuration (in C++ but similarly in python) -``` -// setup -auto default_options = Tool::getDefaultOptions(); -default_options.setOptionB(false); - -// later -tool->task(); -``` - -Another use model could be -``` -ToolOptions options; -options.setOptionB(false); -tool->task(options); -``` - -This can be extended to the case of one tool calling another internally with an API like: -``` -void task(ToolOptions* options = nullptr, - AnotherToolOptions* options = nullptr); -``` - -For a sufficiently complicated tool the options object could itself become a sub-configuration builder. For example: -``` -class PdnOptions -{ -public: - RingOptions* add_ring(); -}; -``` - -The case of an incremental tool is tricky. If asked to do an update I think it should do so according to the last set of options (default or not) that it used. This implies that it must keep a copy of any non-default options object. - -I'm open to other ideas or improvements. I'd love to hear from folks @gadfort @macd @QuantamHD @cdleary @osamahammad21 @antonblanchard @donn @rovinski - -### maliberty -@proppy - -### QuantamHD -I like the idea, but I think I would make a modification to a builder architecture, which I think makes sense for two reasons. - -1. It allows you to do more validation in your builder which would give us the ability ensure that a user can never create an invalid tool configuration. For example creating a PDN that has straps repeat at a greater pitch than the width of the chip (Which I've run into) -2. I like the idea of `ToolOptions` being an Immutable object. It means that a tool cannot modify the options which I think reduces the possibility of tools doing weird things with user provided options. - -```c++ -class ToolOptionsBuilder : OptionBuilder { -public: - /* - * Not necessarily required in all cases, but could help build default options for a particular PDK, or - * core size etc. - */ - ToolOptionsBuilder(Design *); - - void setOptionA(int A); - void setOptionB(bool B); - ErrorOr create(); // could also throw an exception. -} - -class ToolOptions : ToolOption{ -private: - ToolOptions(int A, bool B); // a well-defined default state - -public: - int getOptionA(); - bool getOptionB(); -}; - -class Tool { -public: - static ToolOptions* getDefaultOptions(); // calls ToolOptionsBuilder(...).create(); - - // if options is nullptr then the default options are used. - void task(ToolOptions* options = nullptr); -}; -``` - - - -> ```c++ -> // setup -> auto default_options = Tool::getDefaultOptions(); -> default_options.setOptionB(false); -> -> // later -> tool->task(); -> ``` -I don't like the idea of modifying the default options object, seems very error prone. - - - -> Another use model could be -> -> ```c++ -> ToolOptionsBuilder options; -> options.setOptionB(false); -> tool->task(options.create()); -> ``` -I like this model, but with the builder pattern. - - -> This can be extended to the case of one tool calling another internally with an API like: -> -> ```c++ -> void task(ToolOptions* options = nullptr, -> AnotherToolOptions* options = nullptr); -> ``` -I think this is a greate idea too. - - -> For a sufficiently complicated tool the options object could itself become a sub-configuration builder. For example: -> -> ```c++ -> class PdnOptions -> { -> public: -> RingOptions* getRing(); -> }; -> ``` -I like this but again should be constructed using builders. - - -> The case of an incremental tool is tricky. If asked to do an update I think it should do so according to the last set of options (default or not) that it used. This implies that it must keep a copy of any non-default options object. - -I think there's also another problem -1. The common use mode of the tools is to do one step then dump an ODB file. I don't think we can get rid of this use mode, because then it would be impossible to run the tool incrementally. Which is making me feel like we need to serialize them into the database. - -I've thought about it a bunch, and I think storing a hidden only history from a user is probably not the right API instead I suggest. - -```c++ -class Tool { -public: - static ToolOptions* getDefaultOptions(); // calls ToolOptionsBuilder(...).create(); - set incrementalOptions(ToolOptions* options); - - // if options is nullptr then the default options are used. - void task(ToolOptions* options = nullptr); - -private: - ToolOptions* incremental_options_; - -}; -``` - -On construction the incrementalOptions are set to what's provided in the constructor, or can be updated by the user. - -This brings up another question about incremental APIs. @maliberty how do you envision a tool getting access to a `Tool` object will the user need to pass one into the options, or something else? - - -### rovinski -It's a very interesting question and I feel like I've become jaded because of how inconsistent commercial tools are. It seems like tools (both commercial and OpenROAD) always consist of some combination of the three options you mentioned. What's worse is that commercial tools can be some kind of weird blend of global variables, app variables, tool variables, etc. all with different methods for accessing them... it can get overwhelming. - -I think for the most part, I like the idea of doing away with arguments to commands and having all options passed through some kind of options object. The caveat is that I am split on whether that's appropriate for very simple commands that only take one parameter, like `read_odb [filename]`. - -Whatever the decision is, I _definitely_ want to see a common command / interface that lets a user easily query all parameters that can be set for a tool. For example: -``` -openroad> list_parameters Tool -Parameters for command 'Tool': -Parameter Type Value Default Description -------------------------------------------- -A int 1 1 Short description of A -B bool 1 0 Short description of B -------------------------------------------- -Use 'help Tool' for more information on this command's parameters - -openroad> help Tool -Parameter Definition ------------------------- -A This is a long-form description of A. Here are the valid values, maybe some tips, etc. - The description could be multiple lines. - -B This is a long-form description of B. Here are the valid values, maybe some tips, etc. - -Use 'list_parameters Tool' to list the current values for this command's parameters -``` - -Hidden state / parameters is one of the things I hate the most about commercial tools. At the same time, a user definitely shouldn't _need_ to set parameters they don't know about, like bin grid size for GPL. - -These comments are mostly concerning the user-side interface. As for the developer / C++ API, I don't think I have strong opinions. I think the proposed interface sounds ok. - -### maliberty -I'm lukewarm on a builder. Your two arguments for it were: - -"It allows you to do more validation in your builder". You can just as easily do this validation in the task. If you want to do it in the builder then you will have to restrict when it can be used (ie not before the db is populated) which seems awkward. The builder itself will have to be constructed by the tool to give it enough state for validation. - -"I like the idea of ToolOptions being an Immutable object. It means that a tool cannot modify the options which I think reduces the possibility of tools doing weird things with user provided options." I see two problems. The tool can always clone the options object and do "weird things". In gpl for example we set options before calling grt (see https://github.com/The-OpenROAD-Project/OpenROAD/blob/b632f9f5177bc27fe7323beb1e5a97a8c904ccee/src/gpl/src/routeBase.cpp#L374). I wouldn't want to force the user to know to do so. - -### maliberty -re "I don't like the idea of modifying the default options object, seems very error prone." - -I have a somewhat similar feeling but I'm also afraid of producing very complex API calls (eg gpl). I think some people would prefer to setup the tools upfront. Also interactively it will save a lot of typing. However I am fine to remove it if there is a consensus that it isn't useful. - -### maliberty -Putting the options in the db will open it up to tons of schema updates which is undesirable. Or we would have to make the storage extremely generic which will push the validation on load problem to each tool which isn't much better. Its also error prone for the user. - -I lean toward saying that on reload you don't get any incremental operations. We are living with that today, sta is not incremental across restart. - -### donn -Sorry it's taken me a minute to respond to this- perhaps I can offer a bit of a different perspective being more on the user side, but: - -* Lukewarm on the builder, too. I don't see the utility outside of a niche case where I may elect to build and serialize the options in OpenLane then use it in OpenROAD, but I'm fairly sure that won't be possible regardless. -* I like the idea of immutability vs. modifying a global variable. I get that means more typing, but I think it's worth it just to have less surprises. i.e. I wholeheartedly endorse this model: -```c++ -ToolOptions options; -options.setOptionB(false); -tool->task(options); -``` - -From where I stand, the above model would let me write a single common file to convert OpenLane variables to an OpenROAD ToolOptions object generator, which can then be passed onto other tools. - -### maliberty -@rovinski tcl is a completely different API with lots of manual coding. Converting it look like python, if possible, would introduce the same friction of it looking nothing like usual EDA tools' tcl interface. I don't think it is worth the effort to maintain two sets of APIs. Klayout supporting both python & ruby is much simpler since they are both OO languages. We could do that too more easily (though I have no desire to). - -### maliberty -Based on the discussions I'm wondering if it is preferrable to eliminate the global state and use only explicit options with a default arg: -``` -class Tool -{ -public: - void task(const ToolOptions& options = ToolOptions()); - void complex_task(const ToolOptions& options = ToolOptions(), - const AnotherToolOptions& other_options = AnotherToolOptions()); -}; -``` - -### donn -Should probably add- syntactic sugar in the form of - -```c++ -auto options = ToolOptions { - {"a", "value1"}, - {"b", "value2"} -}; -``` - -i.e., one that basically takes a dict, with the appropriate bridging to python: - -```python -options = ToolOptions( - a="value1", - b="value2", -) -``` - -would be pretty cool - -### maliberty -For a next step I want to make a concrete example. Looking at gpl it fits this model well is it is a single task (placement) with many options. - -When I look at ifp it is more problematic. It is a tool with multiple semi-related tasks: initFloorplan, insertTieCells, and makeTracks. I don't feel it makes sense to have a single options object to cover such diverse tasks. Perhaps this would be better formulated as TaskOptions rather than ToolOptions. A TaskOptions could replace the need for overloaded methods. - -This does run the risk of a proliferation of classes - worst case is one for every method. I am hopeful that the number of tasks is fairly limited per tool today. - -### maliberty -I created https://github.com/The-OpenROAD-Project/OpenROAD/pull/2809 as a example of what the revised API for gpl could look like. The user tcl layer is unchanged but python and c++ see a new options object. Replace has way too many options so it produces a very large object interface. - -Having made the change I'm a bit on the fence about keeping it like this versus making either (1) a code generator from a description file or (2) a more weakly typed interface using string (or enum) keys with a variant value and a single get/set method. I'm glad to hear opinions. - -### maliberty -Any thoughts on either the existing approach or my other suggestion? - -### maliberty -I came across https://abseil.io/tips/173 which gives some nice ideas for using designated initializers - diff --git a/gh_discussions/Query/2800.md b/gh_discussions/Query/2800.md deleted file mode 100644 index 41ab6167645cff5873a8754f42a5060ea315e7a6..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/2800.md +++ /dev/null @@ -1,24 +0,0 @@ -# [developer docs] Errors thrown in C++ test files? - -Subcategory: Best practices - -## Conversation - -### cdleary -I presume for errors in C++ test code (e.g. fixtures and similar) it's ok to throw more "bare" errors (vs the scheme used with the logger and explicitly enumerated exceptions) -- that is, it's ok to throw a derived class from `std::runtime_error` if something goes wrong in test fixture scaffolding? - -If so I'll update the developer docs with a small note, but I wanted to check this seemed ok. - -CC @maliberty - -### cdleary -(Or if non-exception-code is preferred in test code, that'd be fine too, just let me know what the preferred way to fatal-error-with-message would be.) - -### cdleary -(Or possibly we use logger with an error ID of 0 for a testing use cases like this?) - -Apologies for the stream of conscious of possibilities. :-) - -### maliberty -What do you mean by "explicitly enumerated exceptions"? In general I'm ok with your initial statement. - diff --git a/gh_discussions/Query/2868.md b/gh_discussions/Query/2868.md deleted file mode 100644 index 4982a929cce87c908c230d543b33c843f985d041..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/2868.md +++ /dev/null @@ -1,130 +0,0 @@ -# How do I figure out valid macro coordinates for manual placement? - -Tool: Initialize Floorplan - -Subcategory: Macro placement - -## Conversation - -### oharboe -I'm trying to find out valid coordinates to put macros onto. The pins of the macros must align on the routing grid. - -From ASAP 7 LEF files, I see that pins are on M4 and M5 layer. From make_tracks.tcl, I see offsets and pitches. - -From that information, I should be able to come up with some formulae of valid macro positions.... - -I just seem to be unable to connect the dots here to what the formulae should be: - -M4 is horizontal pins and M5 is vertical pins (or vice versa, I could see in the GUI, but I don't know how to tell from the LEF file): - - -The pins are from a macro, so I know the pin coordinates below are correct: - -``` - PIN foo[50] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 144.818 86.208 145.152 86.232 ; - END - END foo[50] - - PIN bar - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M5 ; - RECT 101.76 144.818 101.784 145.152 ; - END - END bar -``` - -from make_tracks.tcl: - -``` -make_tracks M4 -x_offset [expr 0.009 * $multiplier] -x_pitch [expr 0.036 * $multiplier] -y_offset [expr 0.012 * $multiplier] -y_pitch [expr 0.048 * $multiplier] -make_tracks M5 -x_offset [expr 0.012 * $multiplier] -x_pitch [expr 0.048 * $multiplier] -y_offset [expr 0.012 * $multiplier] -y_pitch [expr 0.048 * $multiplier] -``` - - -### yupferris -@maliberty mentioned in our discussion yesterday that the routing grid is defined in the tech lef for the PDK. For ASAP7 we have to look at the [generated tech lef in ORFS](https://github.com/The-OpenROAD-Project/asap7/issues/19#issuecomment-1115712485) which should be `OpenROAD-flow-scripts/flow/platforms/asap7/lef/asap7_tech_1x_201209.lef`: - -``` -LAYER M4 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 0.048 ; - WIDTH 0.024 ; - SPACING 0.024 ; - - OFFSET 0.003 ; - - AREA 0.008 ; - - PROPERTY LEF58_SPACING " - SPACING 0.024 ENDOFLINE 0.025 WITHIN 0.04 ENDTOEND 0.04 ; " ; - - PROPERTY LEF58_WIDTHTABLE - " WIDTHTABLE 0.024 0.12 0.216 0.312 0.408 ; " ; - - PROPERTY LEF58_CORNERSPACING " - CORNERSPACING CONVEXCORNER CORNERONLY 0.048 - WIDTH 0.0 SPACING 0.04 ; - " ; - - PROPERTY LEF58_EOLKEEPOUT " - EOLKEEPOUT 0.025 EXTENSION 0.048 0.02425 0.048 CORNERONLY ; - " ; - - # spacing table is required for the rule that has wide metal requires a 72nm (288 scaled) - # spacing between wide and minimum metals - - SPACINGTABLE - PARALLELRUNLENGTH 0.0 - WIDTH 0.0 0.024 - WIDTH 0.025 0.072 ; - - PROPERTY LEF58_RIGHTWAYONGRIDONLY " - RIGHTWAYONGRIDONLY ; - " ; - - PROPERTY LEF58_RECTONLY " - RECTONLY ; - " ; - -END M4 -``` - -From this we can indeed see that M4 is horizontal and M5 is vertical (not shown above but the definitions for M5 are below those for M4 in the file). We can also see that the pitch is `0.048` which lines up with the `-y_pitch` arg in the `make_tracks.tcl` code above, among other things. However, I'm also a bit confused at how to use this information. - -Some specific questions: - - - Where does `0.012` for the `-y_offset` arg in `make_tracks.tcl` come from? I would have assumed it would be `0.003` from the `OFFSET` in the tech lef. - - How does offset/pitch relate to macro position? I would assume that the bottom-left of a macro is the origin (0, 0), and that if we respect `PITCH` and `OFFSET` from the tech lef above for IO y-positions (eg. `my_io_y = OFFSET + some_integer * PITCH`) we can then place that macro at a position which ensures those constraints are still respected (eg. `my_macro_y = some_integer * PITCH - OFFSET`). Is this correct? - -"Bonus" question: What's the difference between the 1x and 4x .lef files in the PDK? - - -### maliberty -In the LEF you can see the preferred routing direction from: -``` -LAYER M4 - DIRECTION HORIZONTAL ; - -LAYER M5 - DIRECTION VERTICAL ; -``` - -If you look at M1 you'll see it has an offset of 0 which makes the first track unusable (a wire would be half outside the bounds if that track were used). So in make_tracks it was setup to make the first track usable by using a 1/2 width offset. Similarly the other layers need adjusting. Its mostly a matter of style and either could have been used. - -M2 has a track pattern too complex to express in the LEF format so make_tracks.tcl is required in any case. - -If you place a macro a (0,0) the tracks should align since they would be built the way way. Moving the macro by a multiple of the pitch should keep it aligned. You would use the m4 pitch vertically and the m5 pitch horizontally. - -You can check your work by turning on m4 & m5 visibility in the GUI, turning on the display of the preferred tracks and look at your pins to see that the tracks go through the center. - -### maliberty -Bonus: 1X and 4X can be ignored as OR is only using 1X. The origin is that some academic users may not have the advanced node licenses for proprietary tools required to use a 7nm process. The 4X library makes it appear like a 28nm library by making all dimensions 4X larger as a workaround. Since OR has no licensing 4X is not required. - diff --git a/gh_discussions/Query/2923.md b/gh_discussions/Query/2923.md deleted file mode 100644 index 00e870f46a9d35e7c9079e014c078d73db52a7d1..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/2923.md +++ /dev/null @@ -1,55 +0,0 @@ -# Using a regex for set_io_pin_constraint -names - -Tool: Pin Placer - -Subcategory: Usage question - -## Conversation - -### oharboe -How can I get a list of the names of the pins, such that I can pass in a list of names to set_io_pin_constraint that match a regex? - -Something like: - -``` -set_io_pin_constraint ... -names [lsearch -all -inline $pins $regex] -``` - -Answering myself.. - -This will do it: - -``` -proc match_pins { regex } { - set pins {} - foreach pin [sta::find_port_pins_matching $regex 1 0] { - lappend pins [get_property $pin name] - } - return $pins -} - -set_io_pin_constraint -region top:* -pin_names [match_pins someregex] -``` - - -### maliberty -See discussion in https://github.com/The-OpenROAD-Project/OpenROAD/pull/2839 - -### maliberty -The point being there isn't a default mechanism right now but rather a discussion of how best to do it. get_pins will return a list of pins objects rather than names. You could convert them to names or you could use the odb APIs to traverse the db yourself. - -### oharboe -This will do it: - -``` -set_io_pin_constraint ... -names [sta::find_port_pins_matching $regex 1 0] -``` - - - -### maliberty -What do you mean by "verilog pin names"? Those look ok to me for instance pins - -### maliberty -Perhaps you want get_ports? I would call those port names as Verilog includes the instance pins as well. - diff --git a/gh_discussions/Query/2927.md b/gh_discussions/Query/2927.md deleted file mode 100644 index aaf882d58812482a919e4f0dbd04a842077d888b..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/2927.md +++ /dev/null @@ -1,22 +0,0 @@ -# Iterating on top level floorplan with macro pin constraints - -Tool: Initialize Floorplan - -Subcategory: Flow customization - -## Conversation - -### oharboe -I would like to iterate on the floorplan of the top level of our design. In doing so, I want to change the pin constraints for the macros used at the top level. - -However, ```make generate_abstract``` goes all the way to detailed routing before producing a .gds, .lef and .lib file. This takes a long time. - -Is there a way to run generate_abstract after IO pin placement on the macro without going through detailed route? - - -### maliberty -The flow itself doesn't have a mechanism but the command should work at that point (though it hasn't been tested). You could add a flow option if needed. - -### oharboe -Solution implemented: `make skip_cts skip_route generate_abstract` - diff --git a/gh_discussions/Query/2965.md b/gh_discussions/Query/2965.md deleted file mode 100644 index b052ab21591ab52b5ceed71a037f7a2d856b5a56..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/2965.md +++ /dev/null @@ -1,33 +0,0 @@ -# Open a sample project in the OpenROAD GUI - -Tool: Graphical User Interface - -Subcategory: Usage question - -## Conversation - -### vic4key -Hi everybody, - -I already build OpenROAD GUI to run on Ubuntu Linux. Now I'm looking for a sample project that can open directly via main menu `File > Open DB` in OpenROAD GUI (like the below image), I have spent a lot of time to find the way (reading read-me, watching video, etc) to do it, but I did not complete. -I found a data test at https://github.com/TILOS-AI-Institute/MacroPlacement/tree/main/Flows/NanGate45/ariane133 but seems it cannot open directly by OpenROAD and maybe need to do several pre-processing steps before can open in OpenROAD GUI. -Could you please help me to know how to do it or give me detail instructions to open this test data in the OpenROAD GUI? -Thanks. - -![sample](https://user-images.githubusercontent.com/5672864/222308822-2fc0204a-440c-4593-a04b-a4e82f591073.png) - - -### QuantamHD -Hi @vic4key, - -It's not clear what's failing, and what you would like to see? It would also be helpful if you uploaded the data you could upload your test data in a zip folder and post it here. So that we can debug th issue. - -### vijayank88 -@vic4key -Same design implemented in OpenROAD-flow-scripts. https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow/designs/nangate45/ariane136 -All you need to install OpenROAD-flow-scripts and run the design and view it in OpenROAD GUI. -Installation document available here: https://openroad-flow-scripts.readthedocs.io/en/latest/user/BuildLocally.html - -### maliberty -cuda will make almost no difference to runtime. I would start by running gcd as it is the smallest test case. - diff --git a/gh_discussions/Query/3023.md b/gh_discussions/Query/3023.md deleted file mode 100644 index 86d494c02ce8aeb720f99e4523abf06f720a8b1a..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/3023.md +++ /dev/null @@ -1,18 +0,0 @@ -# Clock Division - -Tool: OpenSTA - -Subcategory: Constraint definition - -## Conversation - -### Ziad-cyber -How to define a constraint on a generated clock that's divided by 2 from a master clock source? - -### vijayank88 -OpenROAD flow accepts all standard SDC formats. Just browse it and implement the same. -OpenSTA doc found [here](https://github.com/The-OpenROAD-Project/OpenSTA/blob/master/doc/OpenSTA.pdf) - -### maliberty -In particular see create_generated_clock - diff --git a/gh_discussions/Query/3029.md b/gh_discussions/Query/3029.md deleted file mode 100644 index 215c5a46f1cc13eb9a3a1dd79438bd6ee062a0ae..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/3029.md +++ /dev/null @@ -1,56 +0,0 @@ -# how to get timing path information - -Tool: OpenSTA - -Subcategory: Usage question - -## Conversation - -### msingh9 -I am interested to find out my worst timing path. I can run following command to get path objects, but how do I get full report like start point, logic gates in between and end point. - -openroad> find_timing_paths -from * -to * -group_count 10 -sort_by_slack -_d02fb74000000000_p_PathEnd _1005b54000000000_p_PathEnd _1040b44000000000_p_PathEnd _1006b54000000000_p_PathEnd _3071b64000000000_p_PathEnd _b0bfb54000000000_p_PathEnd _d0173d3f00000000_p_PathEnd _20cdb54000000000_p_PathEnd _9091bc4000000000_p_PathEnd _003db64000000000_p_PathEnd - - -### maliberty -From the docs for find_timing_paths https://github.com/The-OpenROAD-Project/OpenSTA/blob/master/doc/OpenSTA.pdf - -``` -Use the get_property function to access properties of the paths. -``` - - -### msingh9 -Thank you very much for prompt response. This works fantastically. I wrote a small TCL function to nicely print complete timing path with the arrival time. Maybe, it will be helpful to someone. - -``` -### Document this #### -Usage: report_timing_paths -Example: report_timing_paths -from * -to * -group_count 2 -sort_by_slack - -proc report_timing_paths {args} { - set path_ends [sta::find_timing_paths_cmd "find_timing_paths" args] - set pathno 1 - foreach path_end $path_ends { - set start_clock [get_property [get_property $path_end startpoint_clock] full_name] - set start_point [get_property [get_property $path_end startPoint] full_name] - set end_point [get_property [get_property $path_end endPoint] full_name] - set end_clock [get_property [get_property $path_end endpoint_clock] full_name] - set slack [get_property $path_end slack] - puts "Path ${pathno} : " - puts " [format "%-80s" $start_point], ${start_clock}" - set points [get_property $path_end points] - foreach point $points { - set arrival [get_property $point arrival] - set pin [get_property [get_property $point pin] full_name] - set cslack [get_property $point slack] - puts " [format "%-80s" $pin], $arrival" - } - puts " [format "%-80s" $end_point], ${end_clock}, [format "%.3f" $slack]" - incr pathno - puts "" - } -} -``` - diff --git a/gh_discussions/Query/3030.md b/gh_discussions/Query/3030.md deleted file mode 100644 index e6abd5d784b9a461cc5f6fba572a200113a0a1a6..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/3030.md +++ /dev/null @@ -1,28 +0,0 @@ -# How to view macro to macro and macro to pin connections in openroad gui mode? - -Tool: Graphical User Interface - -Subcategory: Visualization - -## Conversation - -### khaledhasanzami -I am having some error showing macros can not connect to some pins. - -I can't figure out how to view macro to macro connections (flightline) and macro to pin connections in gui mode. - -Help me if anyone figured this out! - -### vijayank88 -Use `net` name to view in GUI using `Find` menu. It was explained here: https://openroad-flow-scripts.readthedocs.io/en/latest/tutorials/FlowTutorial.html#tracing-the-clock-tree - -### khaledhasanzami -I was looking for macro to macro connection. - -I got the solution though. - -We have to select a macro, right click, highlight, go to all nets and chose a group. - -Thank you for the suggestions though. - - diff --git a/gh_discussions/Query/3033.md b/gh_discussions/Query/3033.md deleted file mode 100644 index 8ed1ca6782e8b0bc2034818231e83d35102d2e9b..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/3033.md +++ /dev/null @@ -1,123 +0,0 @@ -# Using each tools (i.e. OpenDB, RePlAce, OpenDP..) as a submodule - -Tool: OpenDB - -Subcategory: Usage question - -## Conversation - -### ApeachM -Now I'd like to use OpenDB Framework and am searching for how to use each tool (i.e. OpenDB, OpenDB, etc) in **the OpenROAD repository** as a submodule for my open-source project. - -For example, I'm using the OpenDB Framework as [this repository](https://github.com/ApeachM/EDA-API). -In that repository, I only can know how to use the [legacy one](https://github.com/The-OpenROAD-Project/OpenDB) as a submodule, but couldn't find how to set the OpenROAD repository as a submodule. - -I would be very appreciative if there is any recommended way to use each tool (like RePlAce, OpenDP, ..) in the OpenROAD repository which is now updated recently, and if you let me know them. - -Thank you for reading my question. - -Best regards. - - - -### maliberty -We do not offer each tool as a submodule. It is a lot of overhead to manage submodules (we did that initially). You could make OR itself a submodule and link to the portions you wish. - -### maliberty -You should be able to reference our libraries from your app like - -target_link_libraries( - PUBLIC - odb -) - -you would need to include src/CMakeLists.txt - -### maliberty -@QuantamHD what do you think about applying your library separation work to mpl2? - -### ApeachM -@QuantamHD -> @ApeachM I'll ask you for a favor back. If you do end up running mpl2 in your project can you contribute some C++ unit tests back to the project? https://github.com/The-OpenROAD-Project/OpenROAD/pull/3109/files#diff-24b9bab7be8fe0944c3ae7ccbd1d8700449a2e965d33d624fd7f8e3315ebdc9e - -I'd like to do the favor that you mentioned, but I have a question for you. -Now I'm struggling to construct the unit test for mpl2, but there are several problems with making it. - -### 1. The construction dependency exists. - -At least calling `void MacroPlacer2::init(sta::dbNetwork* network, odb::dbDatabase* db, sta::dbSta* sta, utl::Logger* logger, par::PartitionMgr* tritonpart)` function, I need `sta::dbNetwork` and `sta::dbSta` in the test code like below. - -```cpp -#include - -#include - -#include "gtest/gtest.h" -#include "mpl2/rtl_mp.h" -#include "db_sta/dbSta.hh" -#include "par/PartitionMgr.h" -#include "utl/Logger.h" - -namespace mpl2 { - -TEST(Mpl2, CanConstruct) -{ - MacroPlacer2(); -} - -TEST(Mpl2, init){ - MacroPlacer2 macro_placer_2{}; - - sta::dbSta* db_sta = new sta::dbSta; - sta::dbNetwork* db_network = db_sta->getDbNetwork(); - odb::dbDatabase* db_database = odb::dbDatabase::create(); - utl::Logger logger; - par::PartitionMgr partition_mgr; - - /** - * Construct some data in dbDatabase and dbSta by parsing or calling their methods.. - * */ - partition_mgr.init(db_database, db_network, db_sta, &logger); - macro_placer_2.init(db_network, db_database, db_sta, &logger, &partition_mgr); -} -}; // namespace mpl2 -``` - - - -But at `line 21`: `sta::dbSta* db_sta = new sta::dbSta;` an error occurs with the below message. - -```shell -OpenROAD/src/mpl2/test/cpp/mpl2_test.cc:21: undefined reference to `sta::dbSta::dbSta()' -``` - - - -I think this problem is due to a linking issue; `dbSta_lib` library doesn’t link `dbSta.cc`, but links only `dbSta.hh`. - -The `DbSta.cc` file is dependent on `ord::OpenRoad::Observer::Observer()`, so it’s a pretty tricky thing to link with `mpl2_test` library and `sta::dbSta`. - -Is there any proposed method to use `sta::dbSta` in the `OpenROAD/src/mpl2/test/cpp/mpl2_test.cc` file? Unless, I think I can’t make unit test for the one after `mpl2.init(sta::dbNetwork, ..., utl::Logger)`. - - - -### 2. Unless editing code in mpl2/src/*.cpp, there aren’t many things to make unit test. - -For making the unit test for `MacroPlacer2`, I can only call Constructor, Destructor, `init()`, and `place()`. - -Even though the assumption of linking the `mpl2_test` library and `hier_rtlmp.h, hier_rtlmp.cpp`, the `HierRTLMP` has public functions only for setters (`setGlobalFence`, …,`setDebug`) and the top interface (`hierRTLMacroPlacer()`). - -To test whether the `HierRTLMP` is properly working, I think I need to make some accessors to private variables (like `getGlobalFence` …). But I can’t assure you that it’s okay for me to edit the codes in mpl2/src/*.cpp. - -### - -### Conclusion - -If the first problem is solved, the second problem says there are not so many things to make unit test unless I edit the codes. - -I’d like to ask how I can solve problem 1 (the linking issue for `sta::dbSta`), and whether it’s okay or not to edit the code except the test code. - - - -Thank you for reading my questions. - diff --git a/gh_discussions/Query/3037.md b/gh_discussions/Query/3037.md deleted file mode 100644 index bca2fb42846acbe1d0ab031c71fab2fb58ff5e48..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/3037.md +++ /dev/null @@ -1,27 +0,0 @@ -# confusion over where worst slacks are stored and populated - -Tool: Gate Resizer - -Subcategory: Code understanding - -## Conversation - -### cshi15 -Hello, I'm an undergrad who has been trying to add some new functionality and thus trying to learn how the codebase works. - -Right now, I am working in Resizer and trying to write a function that will print out the top failing (negative slack) paths. I was studying the code for worst slacks by studying the `worstSlack` functions in `Search.cc` and `WorstSlack.cc`, and also the `findResizeSlacks()` function in `Resizer.cc`. Looking at the `findResizeSlacks1()` function in `Resizer.cc`, it appears to populate the `worst_slack_nets_` field. However, when I try to access `worst_slack_nets_` in my function, it appears to be empty. - -Is there something that I need to call before this to populate the field? Should I even be trying to access `worst_slack_nets_` at all? - -### rovinski -@openroadie @maliberty any ideas here? - -@cshi15 maybe take a quick look at #3045 to see if there was anything useful there. -Also maybe if you can commit what you have to a fork then it will make it easier to understand what you have tried so far. - -### maliberty -I'm guessing you need to call Resizer::resizePreamble() first. - -### maliberty -Can you put the code on a branch somewhere? - diff --git a/gh_discussions/Query/3040.md b/gh_discussions/Query/3040.md deleted file mode 100644 index 80179387f49979e4cc56fe40db25217422c35263..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/3040.md +++ /dev/null @@ -1,62 +0,0 @@ -# Can I import yosys netlists in the openroad GUI and examine timing? - -Tool: OpenSTA - -Subcategory: Timing analysis - -## Conversation - -### oharboe -I realize this is an open ended question: How can I import Yosys netlists into OpenROAD and identify any timing concerns in the design? - -Is there any documentation, tutorials or examples I can look at? - -I think I have seen an ability to select interesting paths and drill down using "select" (yosys command? opensta command?) and filter timing paths, but I don't recall where. - -Ideally using ORFS. - -This would be more convenient than invoking yosys + open sta directly and interacting with the shell in either. - -### maliberty -You can use 'make gui_floorplan' to open the results after the floorplan step which is pretty quick. We could add an way to directly load the yosys output. In either case you won't see any layout as nothing has been placed but you can use the usual timing path viewer. - -You can't use yosys commands in OR as they are different tools. - -### maliberty -In the GUI from Windows->Timing Report you can get the path viewer. When you select items in the path viewer you can see them in the inspector if you need to get more physical/netlist details. - -### maliberty -@vijayank88 are there any tutorials for timing debug? - -### maliberty -Fwiw https://www.youtube.com/watch?v=5lkKp-gL1Ow - -### vijayank88 -@oharboe -Only after placement you can trace timing path in OpenROAD gui. -You can refer `logs/nangate45/gcd/base/2_1_floorplan.log` (gcd example). It is the first OpenSTA timing report post synthesis. - - -### maliberty -You can really only do back annotation after you reach a fully routed result. There is nothing to back annotate before that. That is already supported in ORFS and the make gui_final will load the parasitics automatically. - -You can generate timing report at any step of the flow. Pre-placement you will get wire load models. Later in the flow we use estimate_parasitics with -placement (after CTS) or -global_routing (after global routing). Post-routing we use rcx extracted values. - -Yosys 'schematics' are a capability of yosys and have nothing to do with OR. The timing report already contains a list of all the cells/ports/nets so a schematic doesn't add much for a path. In general generating schematics for arbitrary chunks of logic is hard and is essentially another P&R problem itself. Even the proprietary tools aren't great at this beyond a small amount of logic. - -### maliberty -If you have layout you can use the inspector to look at an ITerm and there are buttons to show the fanin and fanout cones -![image](https://user-images.githubusercontent.com/761514/226408803-ae3cef35-4855-4909-9786-e7b4f569a8af.png) - - -### maliberty -Here is a tightly package cone on gcd: -![image](https://user-images.githubusercontent.com/761514/226409401-157a4b9b-7384-4e75-b43c-ed0b6d099e6e.png) - - -### maliberty -@oharboe is this sufficient info or do you need something more? - -### oharboe -Will open new more specific questions in the future as needed. This was helpful to improve our understanding meanwhile. - diff --git a/gh_discussions/Query/3068.md b/gh_discussions/Query/3068.md deleted file mode 100644 index 02cb729adb73250c1e116c2c8bbe786cdd5334c2..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/3068.md +++ /dev/null @@ -1,27 +0,0 @@ -# openroad gui - -Tool: Graphical User Interface - -Subcategory: Usage question - -## Conversation - -### msingh9 -If ran openroad without gui, can I bring gui on later on after few steps from flow.tcl? I could save the design db and then open that design in gui, but I am just wondering if I can bring gui on from within openroad prompt. - -1) openroad -log log -2) source .tcl -3) After few steps of flow -4) I want to open the design in gui - -### QuantamHD -You can open the gui at anytime with `gui::show` - -### msingh9 -This works like a charm. Thank you for comment. - -### maliberty -FYI you can go the other way with "Hide GUI": -![image](https://user-images.githubusercontent.com/761514/227319100-b11dc3c6-bf82-4464-aac2-318293c43c13.png) - - diff --git a/gh_discussions/Query/3121.md b/gh_discussions/Query/3121.md deleted file mode 100644 index b72f02ac71d5929056af5c9abae2b0e944c470b3..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/3121.md +++ /dev/null @@ -1,24 +0,0 @@ -# How much time for tritonroute to run the benchmarks of ispd2018 and ispd2019? - -Tool: TritonPart - -Subcategory: Usage question - -## Conversation - -### gilgamsh -I am using https://github.com/The-OpenROAD-Project/TritonRoute to run the benchmarks of ispd2018&2019. However I found Multithreaded acceleration is almost useless. Does the legacy code in https://github.com/The-OpenROAD-Project/TritonRoute support Multithreaded acceleration ? - -### maliberty -How are you enabling the multi threading? It should make a large difference - -### maliberty -The standalone TritonRoute is archived and not under any active development or support. If that meets you needs that's fine but the integrated version in OR is continuing to be improved. - -### maliberty -Since you are interested in contests I would look at -https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/drt/test/ispd18_sample.tcl -https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/drt/test/run-ispd.py - -as examples - diff --git a/gh_discussions/Query/3174.md b/gh_discussions/Query/3174.md deleted file mode 100644 index 1fc4240239d630384d817f5ab050471a65d43d87..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/3174.md +++ /dev/null @@ -1,32 +0,0 @@ -# Meandering wires in a void - -Tool: Detailed Routing - -Subcategory: Detailed routing strategy - -## Conversation - -### oharboe -I'm doing some exploration of floorplanning, which means that I sometimes have a LOT of free space after detailed routing. - -I saw this net, which I thought was curious: a meandering wire in the void... - -Wouldn't a single vertical + horizontal wire be faster? - -I'm curious as to why the detailed router meanders in this way. - -![image](https://user-images.githubusercontent.com/2798822/231722490-7eeb540d-5004-424b-bca1-f29bc53fa899.png) - - -### maliberty -what does the route guide look like for this wire? - -### oharboe -I know what is going on. That wire has a lot of flip-flops on it. - -This is a holdover from FPGA design. In the FPGA design, we used global synthesis and we had a synchronous reset with a LARGE fan-out. That large fan-out was handled by adding a number of flip-flops to it so that the tools would be able to create a synchronous reset tree to deal with the fanout and reset congestion. This is congruent with the recommendation in Quartus to use the HyperFlex architecture where there are bypassable registers in the routing. To use those, you basically add a bunch of pipeline stages to your synchronous reset. Basically the more modern Intel FPGAs now recommend synchronous reset over asynchronous reset for this reason. - -https://www.intel.com/content/www/us/en/docs/programmable/683353/21-3/fpga-architecture-introduction.html - -The above with the caveat that I'm not an FPGA expert when it comes to detail, I just write RTL, follow some high level guidelines, and the tools handle the rest... - diff --git a/gh_discussions/Query/3178.md b/gh_discussions/Query/3178.md deleted file mode 100644 index d916fb9159c552f631340459efbe73612909ade2..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/3178.md +++ /dev/null @@ -1,39 +0,0 @@ -# How to attach/add a new load to a net? - -Tool: Design for Test - -Subcategory: Usage question - -## Conversation - -### fgaray -Hello, - -In the DFT tool, I am trying to connect a new created scan_out port at the top level module with the scan out of a scan cell. - -The scan out of the cell is previously connected to a functional path, so I am doing something like: - -``` -odb::dbNet* functional_net = scan_out_cell->getNet(); -scan_out_module->connect(functional_net); -``` -When I print the BTerms of the net, I get both, the scan_out of the module and the previous connected port. - -However, I doesn't seems to work if I write the verilog, as I am only seeing it being connected to the original functional port instead of being connected to both of them: scan out and functional port. - -Is there something that am I missing? - -Thanks, -Felipe - -### maliberty -What is the type of scan_out_module ? - -### maliberty -An issue with a test case might be better as it doesn't sound like an unusual operation. - -### fgaray -This was addressed in https://github.com/The-OpenROAD-Project/OpenROAD/issues/3183 - -However, @maliberty was right in that ticket and we don't really need to punch a new port for scan out, we can just reuse the already existing port. So, we only need to punch a new scan out port if there is funcional logic before scan insertion and there are only ITerms in the net. - diff --git a/gh_discussions/Query/3262.md b/gh_discussions/Query/3262.md deleted file mode 100644 index 77d830cfd09998b07436007ffb7de9a62f53cc38..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/3262.md +++ /dev/null @@ -1,38 +0,0 @@ -# How can I find the net for a wire? - -Tool: Graphical User Interface - -Subcategory: Usage question - -## Conversation - -### oharboe -I am currently dealing with an issue related to unexpected congestion in a design that has me stumped. It appears that there might be incorrect constraints on some I/O pins of a macro. - -When I try to probe deeper into the congested area by clicking on the wires, the details provided are fairly vague – something along the lines of "wire4940/A". I'm led to believe that this wire is simply a segment of a larger net. - -Ideally, I would be able to trace this wire segment back to its origin and endpoint within the RTL design, which would help me identify the exact register/pin it connects from and to. However, I'm unsure of how to proceed with this. - -![image](https://user-images.githubusercontent.com/2798822/235071472-965d37ef-93e0-453b-95d3-92e085d45064.png) - - -### rovinski -`wire4940/A` is an iTerm (instance terminal) meaning that `wire4940` is the name of a cell, not a wire segment. I believe `wire####` is the generated name for buffers which are inserted due to max wirelength targets. - -The net that you have selected is connecting two iTerms, most likely buffers. - -There should be a GUI display item called "Buffer Tree" which should show you what you want. See #2781 and #2824 for discussion. - -### maliberty -wireXXX will be part of multiple nets and they will be show next to the iterm name. - -Buffer tree only shows up if one is detected. To detect buffers we need the liberty to be loaded. If you used GUI_NO_TIMING=1 then it will not appear. - -### oharboe -Works very well! - -When I click on the buffer tree, I get the terminals (endpoints), which I can relate to my Verilog easily. - -![image](https://user-images.githubusercontent.com/2798822/235290247-50079b66-d746-47db-b511-470cfe18260d.png) - - diff --git a/gh_discussions/Query/3291.md b/gh_discussions/Query/3291.md deleted file mode 100644 index ea9153a4aba39b2d3a0c3fa5a7d9c46af0c98a9a..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/3291.md +++ /dev/null @@ -1,41 +0,0 @@ -# Can these warnings be removed? - -Tool: OpenSTA - -Subcategory: Warning handling - -## Conversation - -### oharboe -I've found myself ignoring warnings when I shouldn't... - -In that regard, it would be helpful to fix some warnings that are always there, so I pay more attention... - -Can these be fixed? - -``` -[WARNING STA-0164] /OpenROAD-flow-scripts/flow/platforms/asap7/lib/asap7sc7p5t_SIMPLE_RVT_TT_nldm_211120.lib.gz line 13178, timing group from output port. -[WARNING STA-0164] /OpenROAD-flow-scripts/flow/platforms/asap7/lib/asap7sc7p5t_SIMPLE_RVT_TT_nldm_211120.lib.gz line 13211, timing group from output port. -[WARNING STA-0164] /OpenROAD-flow-scripts/flow/platforms/asap7/lib/asap7sc7p5t_SIMPLE_RVT_TT_nldm_211120.lib.gz line 13244, timing group from output port. -[WARNING STA-0164] /OpenROAD-flow-scripts/flow/platforms/asap7/lib/asap7sc7p5t_SIMPLE_RVT_TT_nldm_211120.lib.gz line 13277, timing group from output port. -[WARNING STA-0164] /OpenROAD-flow-scripts/flow/platforms/asap7/lib/asap7sc7p5t_SIMPLE_RVT_TT_nldm_211120.lib.gz line 13310, timing group from output port. -[WARNING STA-0164] /OpenROAD-flow-scripts/flow/platforms/asap7/lib/asap7sc7p5t_SIMPLE_RVT_TT_nldm_211120.lib.gz line 13343, timing group from output port. -[WARNING STA-0164] /OpenROAD-flow-scripts/flow/platforms/asap7/lib/asap7sc7p5t_SIMPLE_RVT_TT_nldm_211120.lib.gz line 13376, timing group from output port. -[WARNING STA-0164] /OpenROAD-flow-scripts/flow/platforms/asap7/lib/asap7sc7p5t_SIMPLE_RVT_TT_nldm_211120.lib.gz line 14772, timing group from output port. -[WARNING STA-0164] /OpenROAD-flow-scripts/flow/platforms/asap7/lib/asap7sc7p5t_SIMPLE_RVT_TT_nldm_211120.lib.gz line 14805, timing group from output port. -[WARNING STA-0164] /OpenROAD-flow-scripts/flow/platforms/asap7/lib/asap7sc7p5t_SIMPLE_RVT_TT_nldm_211120.lib.gz line 14838, timing group from output port. -``` - - -### rovinski -They cannot, the warnings are due to the structure of the cells in the PDK and the way they were characterized into a timing model. You can, however, stop the warnings from showing up by using `suppress_message STA 164`. - -### vijayank88 -I have discussed about this `WARNING STA-016` month back with Tom. Replied: -``` -The output to output timing edges in the liberty cause this warning. -If it's just this one cell, you could add it to the don't use list. -I think this warning means the timing will be less accurate. -If you are doing experiments it may also be safe to ignore. -``` - diff --git a/gh_discussions/Query/3298.md b/gh_discussions/Query/3298.md deleted file mode 100644 index 78c2c9ac9f6f403fc752a8d9f0b8c0349ad584c7..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/3298.md +++ /dev/null @@ -1,219 +0,0 @@ -# Running times in detailed routing as a function of design parameters - -Tool: Detailed Routing - -Subcategory: Performance analysis - -## Conversation - -### oharboe -mock-array-big has 3 essential parameters that can be adjusted: array area(number of elements), element size (area) and data width (bits). - -I thought it would be interesting to see how detailed routing (TritonRoute) varies across these parameters, so I made a python snippet(https://github.com/Pinata-Consulting/OpenROAD-flow-scripts/commits/plot-running-times) to gather some data and plot them - -The graph below is interactive(measured on a machine with 16 threads and 64gByte of RAM, where memory consumption appears to peak at 20gByte), which helps in terms of understanding the 4 dimensions being represented: - -Video: https://drive.google.com/file/d/1pmkIZh6tUOrWhAkVRgm0fxCD7yaf766Q/view - -Snapshot: - -![image](https://user-images.githubusercontent.com/2798822/236807617-6c48df46-609a-4614-937e-539cbf7c5ce7.png) - -**8 x 8 64 bit array detailed route times plotted against threads** - -![image](https://user-images.githubusercontent.com/2798822/236921035-c2ac6218-b515-4c83-b342-0c3d2f677f99.png) - -**Conclusion so far** - -Detailed routing is surprisingly slow when the area is large, but everything else is the same. - -This run takes 40 minutes or so, `APTOS_MOCK_PITCH_SCALE=20 make FLOW_VARIANT=scale-20 route DESIGN_CONFIG=designs/asap7/mock-array-big/config.mk` whereas `APTOS_MOCK_PITCH_SCALE=2 make FLOW_VARIANT=scale-2 DESIGN_CONFIG=designs/asap7/mock-array-big/config.mk` completes in a few minutes - - -**Detailed of testing...** - -It looks like the performance of detailed routing is sensitive to area: - -``` -MOCK_ARRAY_PITCH_SCALE=2 make OPENROAD_EXE="perf record -o perf.data ~/OpenROAD-flow-scripts/tools/install/OpenROAD/bin/openroad" DESIGN_CONFIG=designs/asap7/mock-array-big/config.mk FLOW_VARIANT=scale-2 route -``` - -``` -Samples: 15M of event 'cycles', Event count (approx.): 14285585618565 -Overhead Command Shared Object Symbol - 16,94% openroad openroad [.] fr::FlexGridGraph::initEdges - 8,38% openroad openroad [.] fr::FlexGridGraph::outOfDieVia - 7,46% openroad openroad [.] fr::FlexDRWorker::modMinSpacingCostVia - 5,92% openroad openroad [.] fr::FlexGCWorker::Impl::isCornerOverlap - 4,62% openroad libstdc++.so.6.0.30 [.] std::_Rb_tree_increment - 4,23% openroad [unknown] [k] 0xffffffffa7b87f27 - 4,20% openroad openroad [.] fr::FlexDRWorker::modMinSpacingCostPlanar - 3,31% openroad openroad [.] fr::frLayer::getMinSpacingValue - 3,22% openroad openroad [.] fr::FlexGridGraph::getIdx - 2,93% openroad openroad [.] fr::FlexGCWorker::Impl::initNet_pins_polygonCorners_helper - 2,48% openroad openroad [.] fr::FlexDRWorker::modMinSpacingCostVia_eol - 2,46% openroad openroad [.] box2boxDistSquareNew - 2,37% openroad openroad [.] fr::FlexDRWorker::modBlockedPlanar - 2,17% openroad openroad [.] fr::FlexGridGraph::addFixedShapeCostVia - 1,71% openroad openroad [.] odb::dbTransform::apply - 1,45% openroad openroad [.] fr::FlexGridGraph::isEdgeInBox - 1,43% openroad openroad [.] odb::dbTransform::apply - 1,28% openroad openroad [.] fr::FlexDRWorker::modBlockedVia - 1,25% openroad openroad [.] std::vector Hello! I have a few questions about ORFS capabilities. -> -> 1. Does OpenROAD support libraries with CCS driver model? - -Only NLDM is currently supported but CCS is under development. - -> 2. Is incremental flow supported? - -That can have a lot of meanings. We do support restarting the flow at a given step. - -> 3. Does OpenSTA in OpenROAD support all sdc commands? - -Yes afaik but be careful that there are many proprietary commands that are not in SDC. - -> 4. Is SystemVerilog support limited to the constructs that Yosys supports? - -Yes. The is the surelog plugin that has a good amount of SV support - -> 5. Does OpenROAD do only DRC analysis or also DRV and DFM? Of the DFM analysis I have only seen an antenna rule check. - -OR does max slew/cap/fanout if that's what you mean by DRV. There is no DFM. - -> 6. Does OpenROAD provide corner-based optimisation, or it can only show us the characteristics, like wns, for different corners? - -OR can be setup for multi-corner analysis. ORFS doesn't take advantage of that today. - -> 7. Are OCVs supported? - -Yes but see 6 - -> 8. Does OpenROAD support crosstalk delay/noise analysis? - -No. Once we have CCS for delay it would be natural to tackle this next. - -> -> Thank you for your answers! - - - -### dralabeing -> @dralabeing. Should we curate this and ask Jack to add it to OR and ORFS FAQs? - -Yes, this is a good idea. Let's add this to the FAQs - diff --git a/gh_discussions/Query/3454.md b/gh_discussions/Query/3454.md deleted file mode 100644 index de862c8a711d37f409183e2edc42ca381d4e9be3..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/3454.md +++ /dev/null @@ -1,40 +0,0 @@ -# How can I go from timing reports to Verilog? - -Tool: OpenSTA - -Subcategory: Tracing timing paths - -## Conversation - -### oharboe -I have a timing path in the OpenROAD GUI that I want to understand. - -How can I go from the timing report in the GUI to the Verilog? - -### maliberty -https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/pull/1129 should help with naming once merged. - -There is no direct link today so you'll have to work back from the names. @QuantamHD has some work to store line numbers that is hopefully going to land but has been tied up in OSS licensing issues. - -### oharboe -@maliberty Here is an example of how it is hard to get from the static timing report to the Verilog: - -Build the design with ` make DESIGN_CONFIG=designs/asap7/mock-array-big/config.mk`, then look at the Element `make DESIGN_CONFIG=designs/asap7/mock-array-big/Element/config.mk gui_final`. - -How, in general, do I find my way to the Verilog code? - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/840713c0-f33a-484f-b156-9a79e4aad50d) - - - - -### maliberty -If you use the rename PR I mentioned then the register should have a name matching the Element.v to some degree. Does that work here? - -### oharboe -What I've heard is that tracking from timing reports back to RTL is an "unsolved problem in EDA tools", so https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/pull/1129 is probably as good as it gets for now. - -To go beyond this, I suppose Yosys has to grow some sophistication w.r.t. tracking back to the original Verilog. - -One of the goals of https://circt.llvm.org/ is to provide an improved infrastructure for RTL as it goes through a number of tools in a flow. Perhaps, one day, yosys will support https://circt.llvm.org/. Ideally this would give Yosys more input languages and better "debug information" through synthesis and technology mapping... - diff --git a/gh_discussions/Query/3562.md b/gh_discussions/Query/3562.md deleted file mode 100644 index cb3b501f52f466d40c08f119fbca0c41c64f1be4..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/3562.md +++ /dev/null @@ -1,29 +0,0 @@ -# About Local Density Penalty Described in the Original RePlace Paper - -Tool: Global Placement - -Subcategory: Code implementation query - -## Conversation - -### by1e11 -Hi, guys - -After reading the paper and browsing the source codes, I cannot figure out which parts of the codes reflect the local density penalty described in the paper, could you please suggest where can I find that in the implementation? - -Thanks a lot for the nice work. - -Bo - -### maliberty -@mgwoo can you answer this? - -### mangohehe -A method related density computation seems to be removed in the CL https://github.com/The-OpenROAD-Project/OpenROAD/commit/0f82f83049733938c2fb5d6141b291409aa4678f , in which the original design calls updateDensityForceBin inside NesterovPlace::doNesterovPlace. (not sure if this can be related) - -@ahmadelrouby could you help understand the changes? thanks - -### mgwoo -I didn't decipher the local density features because of unstable issues. -Please check the standalone repo for the local density calculation: https://github.com/The-OpenROAD-Project/RePlAce/blob/7c07cffdf419c4dbd315c73c235ec5d670fb0240/src/ns.cpp#L1011 - diff --git a/gh_discussions/Query/3598.md b/gh_discussions/Query/3598.md deleted file mode 100644 index 954069cbe89d9aebe4ebad84fb0252e06aa086e7..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/3598.md +++ /dev/null @@ -1,43 +0,0 @@ -# Detailed routing time for mock-array as a function of area - -Tool: Detailed Routing - -Subcategory: Performance analysis - -## Conversation - -### oharboe -Using https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/pull/1211 and https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/pull/1212, I've plotted detailed routing times for the same Verilog 8x8 8 bit datapath mock-array, changing only the size of the element macros. - -Any thoughts on these running times for the mock-array for detailed routing? Expected? Unexpected? - -The algorithm seems to be MUCH faster for smaller areas - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/c2e92b32-302f-4ac5-9381-1178c6520b76) - - -Biggest array: - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/a7ca8cb1-030d-488a-99c7-c80809e46529) - -The element-element wires are not straight, lots of little deviations from horizontal/vertical: - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/67bb32ef-cd99-4369-bd27-becaabd73e8d) - -Smallest array: - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/8b5ce6e6-c647-4623-9fa9-26420ec0d7a8) - - -"All" element to element wires are horizontal/vertical (didn't check exhaustively): - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/4e3f7f0e-ae10-451e-bb61-a012a48c28bd) - - - -### maliberty -How do the number of routing iterations and iter0 DRCs compare between datapoints? - -### oharboe -I wasn't able to follow up on this in a timely manner. - diff --git a/gh_discussions/Query/3608.md b/gh_discussions/Query/3608.md deleted file mode 100644 index ee2a98a9b6173982ed5019faa8c4fe39d437417f..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/3608.md +++ /dev/null @@ -1,147 +0,0 @@ -# How do I find and view the nets that are causing hold and setup violations? - -Tool: OpenSTA - -Subcategory: Timing analysis - -## Conversation - -### oharboe -It want to find and view nets that cause hold violations. - -Today I have to wait and hope for a global routing failure to be able to view the nets that cause hold violations in DRC viewer there. - -``` -Repair setup and hold violations... -TNS end percent 5 -[INFO RSZ-0041] Resized 2 instances. -[WARNING RSZ-0062] Unable to repair all setup violations. -[INFO RSZ-0046] Found 2957 endpoints with hold violations. -[INFO RSZ-0032] Inserted 40106 hold buffers. -Placement Analysis -``` - - -### vvbandeira -```tcl -find_timing_paths -path_delay min -slack_max 0 -``` -@oharboe, Would this work for you? -Note that RSZ just said it had found `2957` hold violations; after inserting the `40106` buffers, there's no warning. -So it is likely that all have been fixed -- see the warning in the line above for a contrast about setup violations. - -For setup you would do: -```tcl -find_timing_paths -path_delay max -slack_max 0 -``` - -### oharboe -Found an approach... Here is what I did: - -1. create some hold failures by reducing the clock period from 2000 to 1000ps in mock-array, using diff below. -2. There are no timing violations in placement, the timing violations happen after CTS. -3. Modify cts.tcl to write out an ODB file *before* hold cells are inserted and the design is repair. Post repair in CTS there are no violations. - -Now I can run commands to examine minimum hold time violations, which will lead to hold cells being inserted. - - -``` -report_checks -path_delay min -Startpoint: io_insRight_0[61] (input port clocked by clock) -Endpoint: ces_0_0 (rising edge-triggered flip-flop clocked by clock) -Path Group: clock -Path Type: min - - Delay Time Description ---------------------------------------------------------- - 0.00 0.00 clock clock (rise edge) - 0.00 0.00 clock network delay (propagated) - 200.00 200.00 ^ input external delay - 0.00 200.00 ^ io_insRight_0[61] (in) - 10.45 210.45 ^ input1082/Y (BUFx2_ASAP7_75t_R) - 0.04 210.48 ^ ces_0_0/io_ins_right[61] (Element) - 210.48 data arrival time - - 0.00 0.00 clock clock (rise edge) - 337.72 337.72 clock network delay (propagated) - 0.00 337.72 clock reconvergence pessimism - 337.72 ^ ces_0_0/clock (Element) - 102.40 440.11 library hold time - 440.11 data required time ---------------------------------------------------------- - 440.11 data required time - -210.48 data arrival time ---------------------------------------------------------- - -229.63 slack (VIOLATED) -``` - -``` -foreach path [find_timing_paths -slack_max 0 -group_count 10 -path_delay min] {puts "[get_property $path slack] [get_property [get_property $path endpoint] full_name]"} --229.630280 ces_0_0/io_ins_right[61] --229.599152 ces_0_0/io_ins_right[3] --229.596451 ces_0_0/io_ins_right[56] --229.570663 ces_0_0/io_ins_right[51] --229.570786 ces_0_0/io_ins_right[53] --229.568649 ces_0_0/io_ins_right[1] --229.561371 ces_0_0/io_ins_right[14] --229.517380 ces_0_0/io_ins_right[30] --229.512604 ces_0_0/io_ins_right[5] --229.509186 ces_7_0/io_ins_right[61] -``` - - - -``` -diff --git a/flow/designs/asap7/mock-array/Element/constraints.sdc b/flow/designs/asap7/mock-array/Element/constraints.sdc -index be545b8f..0a66e62e 100644 ---- a/flow/designs/asap7/mock-array/Element/constraints.sdc -+++ b/flow/designs/asap7/mock-array/Element/constraints.sdc -@@ -4,7 +4,7 @@ set cols [expr {[info exists ::env(MOCK_ARRAY_COLS)] ? $::env(MOCK_ARRAY_COLS) : - - set clk_name clock - set clk_port_name clock --set clk_period 2000 -+set clk_period 1000 - - set clk_port [get_ports $clk_port_name] - create_clock -period $clk_period -waveform [list 0 [expr $clk_period / 2]] -name $clk_name $clk_port -diff --git a/flow/designs/asap7/mock-array/constraints.sdc b/flow/designs/asap7/mock-array/constraints.sdc -index 5d33c792..46b20e5b 100644 ---- a/flow/designs/asap7/mock-array/constraints.sdc -+++ b/flow/designs/asap7/mock-array/constraints.sdc -@@ -1,6 +1,6 @@ - set sdc_version 2.0 - --set clk_period 2000 -+set clk_period 1000 - create_clock [get_ports clock] -period $clk_period -waveform [list 0 [expr $clk_period/2]] - - set clk_name clock -diff --git a/flow/scripts/cts.tcl b/flow/scripts/cts.tcl -index 0b7c56b8..2c0c6fef 100644 ---- a/flow/scripts/cts.tcl -+++ b/flow/scripts/cts.tcl -@@ -45,6 +45,8 @@ estimate_parasitics -placement - report_metrics "cts pre-repair" - utl::pop_metrics_stage - -+write_db $::env(RESULTS_DIR)/4_1_cts_pre_repair.odb -+ - repair_clock_nets - - utl::push_metrics_stage "cts__{}__post_repair" -``` - - -### oharboe -`make gui_cts` ctrl-f and searching for instance `*hold*` is helpful. :-) - -From there I can go to the buffer tree, then find the endpoints. - - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/bcfc601b-55b6-4a91-aa4c-e58f630c647e) - - -### maliberty -Various useful patterns at https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/2734e98ee7c0f6888a686c2ef2445c0bb837ed0f/flow/scripts/save_images.tcl#L59 - diff --git a/gh_discussions/Query/3644.md b/gh_discussions/Query/3644.md deleted file mode 100644 index 53fa0332872de1ea0bb2b7a10042e937c268ca65..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/3644.md +++ /dev/null @@ -1,53 +0,0 @@ -# ODB:: Is there any way to unfrozen the master? (Changing the size of dbMaster during the code is running) - -Tool: OpenDB - -Subcategory: Usage question - -## Conversation - -### ApeachM -```c++ -// master setting -dbMaster *master = dbMaster::create(db_lib, lib_cell_name.c_str()); -master->setWidth(width); -master->setHeight(height); -master->setType(dbMasterType::CORE); -... -master->setFrozen(); -// connect inst to the master - -dbInst* inst = dbInst::create(db_block, master, instance_info->inst_name.c_str()); - -// now I want to change the size of inst, by unfrozen master and resize width and height -// Is my intention of the below pseudo-code possible? -master->setUnFrozen(); -master->setWidth(new_width); -master->setHeight(new_height); -master->setFrozen(); -``` - -**I would like to know whether the above pseudo-code is possible.** - -**I want to resize the cell size** after the cell size is already determined. (For example, after parsing lef and def). -But it seems like not to exist function for unfreezing. - -If I want to change the cell size, then should I -1. re-construct the instance, -2. re-construct the new dbMaster, -3. deleting the original instance, -4. and re-connecting the new dbInst to the nets, which was connected with the original one? - -I would like to know whether **is there another way, which is more simple**. - - -Thanks for the time for reading my question. - -Sincerely. - -### maliberty -Why are you freezing it in the first place? - -### maliberty -setWidth & setHeight don't care about the frozen status afaik. The key thing is that the port list is frozen. You can't add a dbMTerm to a frozen master. - diff --git a/gh_discussions/Query/3731.md b/gh_discussions/Query/3731.md deleted file mode 100644 index a297c0ef0ebefe21c467d11efda7bd0cb05e25b2..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/3731.md +++ /dev/null @@ -1,30 +0,0 @@ -# Meta file/format to describe a PDK? - -Subcategory: PDK integration - -## Conversation - -### nrichaud -Hello everyone, -I am new to the project but I have some experience with with PDK and enablement PDK in design flow. - -I was wondering how is structured the interface between the PDK file and the flow. - ->Do you know if there is a kind of **meta file/format** to describe the PDK and maybe "explain" to the flow where to pick the right file/tools? -Like a kind of python `requirement.txt` file so it could be easy to integrate new PDK and switch from one technology to an other? - -Today, my impression is that it is still kind of challenging to have all the pieces or components of a PDK working together with the right version and right place to pick the files. - -Thanks - - -### rovinski -I don't know of any specific standard for PDK distribution. The main issue is that tools / formats are continuously coming in and out of vogue based on the process technology. Many PDKs may be "incomplete" due to lack of enablement for certain tools. - -https://github.com/RTimothyEdwards/open_pdks tries to create a standardized directory structure and format for PDKs, but of course there is effort in taking what the vendor provides and trying to fit it into that model because every PDK vendor is different. - -[ORFS](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts) simply uses Make variables to point at the necessary files. - -### maliberty -I think it is better to accept the PDK as provided than to mess with it as open_pdks requires. PDKs should be read-only. - diff --git a/gh_discussions/Query/3732.md b/gh_discussions/Query/3732.md deleted file mode 100644 index 8ae7a57d8d144f7c17bbb2f06b73cc423865d3b7..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/3732.md +++ /dev/null @@ -1,25 +0,0 @@ -# insert_buffer - -Subcategory: Usage question - -## Conversation - -### AayushiRV -I am inserting buffers to my design. How can I find that buffers are being inserted? I cannot find anything in my design's netlist. - -### maliberty -How are you inserting the buffers? - -### maliberty -There is no such command in OR: -``` -openroad> insert_buffer -invalid command name "insert_buffer" -while evaluating insert_buffer -``` - -### vijayank88 -@AayushiRV -`insert_buffer` is maintained by OpenLane. Check this example: https://github.com/The-OpenROAD-Project/OpenLane/blob/master/tests/1007/interactive.tcl -So OpenROAD nothing to do with that. - diff --git a/gh_discussions/Query/3733.md b/gh_discussions/Query/3733.md deleted file mode 100644 index 3c90b600eb0c6723b6a4a1dddb4d887b6ad28e2f..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/3733.md +++ /dev/null @@ -1,98 +0,0 @@ -# Why invertors in front of the flip-flops in a mock-array clock tree? - -Tool: Clock Tree Synthesis - -Subcategory: Design explanation - -## Conversation - -### oharboe -For mock-array, I ran `make cts && make gui_cts` and pasted the clock tree below. - -I'm curious: why is there an inverter in front of every flip-flop and no invertor in front of the macros? - -I checked by hovering over a number of the pink dots at the leaf of the clock tree that the flip-flops are the leaf points with an invertor in front. - - - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/9a268a21-6f3b-4777-b10d-940090081cbb) - - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/8a96024d-9038-445b-8826-c13354ca9264) - - -The clock period is 1000ps and the skew is 50ps, by gleaning at the clockd tree. - - - -### oharboe -I have tried to find some documentation on the `report_checks` output format, but lacking that I'm making some guesses.... - -The below is a report from mock-array/Element, where I notice the `clock clock' (fall edge)`, but mock-array is positive edge triggered, so why falling edge? - -Could it be that my design is positive edge triggered, but that the flip-flop is in fact negative edge triggered? - -That would explain the inverter in front of every flip-flop in the clock-tree above too... - -I beleve the first path below is the data required path from macro input pin to the flip flop input pin and that the second path is the clock input pin on the macro to the flip flop input pin. - -What does `(propagated)` mean? - -I find `data required time` a bit confusing for the clock propagation path, but my guess that's just the chosen terminology and that the `data required time` for the clock is in fact the clock required time in my mind of thinking. - -``` ->>> report_checks -path_delay min -from io_ins_right[0] -Startpoint: io_ins_right[0] (input port clocked by clock) -Endpoint: _557_ (falling edge-triggered flip-flop clocked by clock') -Path Group: clock -Path Type: min - - Delay Time Description ---------------------------------------------------------- - 0.00 0.00 clock clock (rise edge) - 0.00 0.00 clock network delay (propagated) - 50.00 50.00 ^ input external delay - 2.24 52.24 ^ io_ins_right[0] (in) - 11.98 64.22 ^ hold1749/Y (BUFx2_ASAP7_75t_R) - 11.38 75.59 ^ hold745/Y (BUFx2_ASAP7_75t_R) - 11.43 87.02 ^ hold1750/Y (BUFx2_ASAP7_75t_R) - 11.95 98.97 ^ input129/Y (BUFx2_ASAP7_75t_R) - 12.69 111.66 ^ hold1751/Y (BUFx2_ASAP7_75t_R) - 12.88 124.54 ^ hold746/Y (BUFx2_ASAP7_75t_R) - 12.83 137.37 ^ hold1752/Y (BUFx2_ASAP7_75t_R) - 0.18 137.55 ^ _557_/D (DFFLQNx2_ASAP7_75t_R) - 137.55 data arrival time - - 0.00 0.00 clock clock' (fall edge) - 99.73 99.73 clock network delay (propagated) - 20.00 119.73 clock uncertainty - 0.00 119.73 clock reconvergence pessimism - 119.73 v _557_/CLK (DFFLQNx2_ASAP7_75t_R) - 10.65 130.38 library hold time - 130.38 data required time ---------------------------------------------------------- - 130.38 data required time - -137.55 data arrival time ---------------------------------------------------------- - 7.16 slack (MET) - -``` - - -### maliberty -Is this at the top or in the element? - -### maliberty -propagated means you are post-cts and "set_propagated_clock [all_clocks]" has been used. The delay is calculated from the actual clock network. The opposite is ideal clocks from before CTS. - -### maliberty -If you look at DFFLQNx2_ASAP7_75t_R you'll see -``` - ff (IQN,IQNN) { - clocked_on : "!CLK"; - next_state : "!D"; - power_down_function : "(!VDD) + (VSS)"; - } -``` -so it is on the negative edge. The ff choice is made during synthesis - diff --git a/gh_discussions/Query/3746.md b/gh_discussions/Query/3746.md deleted file mode 100644 index a3de10dfdeb5edd711e5b9e5d5d4e889731eebc7..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/3746.md +++ /dev/null @@ -1,199 +0,0 @@ -# Can I calculate the delay for a macro based on the .lib file? - -Tool: OpenSTA - -Subcategory: Understanding delay calculation - -## Conversation - -### oharboe -I would like to understand the .lib file format a bit better. It is my understanding that I should be able to calculate the delay of the macro output based on what is in the .lib file. - -For the mock-array, we have 183.19 ps delay for driving the io_outs_left[0] output. Looking at the .lib file, I can't figure out where 183.19ps comes from. - -``` - 183.19 486.43 ^ ces_7_0/io_outs_left[0] (Element) -``` - -From mock-array: - -``` ->>> report_checks -path_delay max -to io_outs_left_7[0] -format full -format full_clock_expanded -Startpoint: ces_7_0 (rising edge-triggered flip-flop clocked by clock) -Endpoint: io_outs_left_7[0] (output port clocked by clock) -Path Group: clock -Path Type: max - - Delay Time Description ---------------------------------------------------------- - 0.00 0.00 clock clock (rise edge) - 0.00 0.00 clock source latency - 0.00 0.00 ^ clock (in) - 38.29 38.29 ^ wire65/Y (BUFx16f_ASAP7_75t_R) - 43.22 81.50 ^ clkbuf_0_clock/Y (BUFx4_ASAP7_75t_R) - 39.84 121.35 ^ clkbuf_1_1_0_clock/Y (BUFx4_ASAP7_75t_R) - 29.43 150.78 ^ clkbuf_2_2_0_clock/Y (BUFx4_ASAP7_75t_R) - 32.00 182.78 ^ clkbuf_3_5_0_clock/Y (BUFx4_ASAP7_75t_R) - 39.23 222.00 ^ clkbuf_4_10_0_clock/Y (BUFx4_ASAP7_75t_R) - 16.70 238.70 ^ max_length67/Y (BUFx12f_ASAP7_75t_R) - 30.80 269.51 ^ max_length66/Y (BUFx12f_ASAP7_75t_R) - 33.73 303.24 ^ ces_7_0/clock (Element) - 183.19 486.43 ^ ces_7_0/io_outs_left[0] (Element) - 18.46 504.89 ^ output3073/Y (BUFx2_ASAP7_75t_R) - 0.88 505.77 ^ io_outs_left_7[0] (out) - 505.77 data arrival time - -1000.00 1000.00 clock clock (rise edge) - 0.00 1000.00 clock network delay (propagated) - 0.00 1000.00 clock reconvergence pessimism --200.00 800.00 output external delay - 800.00 data required time ---------------------------------------------------------- - 800.00 data required time - -505.77 data arrival time ---------------------------------------------------------- - 294.23 slack (MET) -``` - -If I look in the Element, I can get a full report of what is driving that pin. However, my understanding is that some detail(I don't know what) is lost in the Element.lib representation: - -``` ->>> report_checks -path_delay max -to io_outs_left[0] -Startpoint: _749_ (falling edge-triggered flip-flop clocked by clock') -Endpoint: io_outs_left[0] (output port clocked by clock) -Path Group: clock -Path Type: max - - Delay Time Description ---------------------------------------------------------- - 0.00 0.00 clock clock' (fall edge) - 108.94 108.94 clock network delay (propagated) - 0.00 108.94 v _749_/CLK (DFFLQNx2_ASAP7_75t_R) - 47.39 156.33 v _749_/QN (DFFLQNx2_ASAP7_75t_R) - 12.65 168.98 ^ _496_/Y (INVx3_ASAP7_75t_R) - 18.89 187.86 ^ _777_/Y (BUFx2_ASAP7_75t_R) - 18.21 206.07 ^ output336/Y (BUFx2_ASAP7_75t_R) - 0.75 206.82 ^ io_outs_left[0] (out) - 206.82 data arrival time - -1000.00 1000.00 clock clock (rise edge) - 0.00 1000.00 clock network delay (propagated) - -20.00 980.00 clock uncertainty - 0.00 980.00 clock reconvergence pessimism - -50.00 930.00 output external delay - 930.00 data required time ---------------------------------------------------------- - 930.00 data required time - -206.82 data arrival time ---------------------------------------------------------- - 723.18 slack (MET) -``` - -Here the latency is 206.82, so that's not the same as 183.19 above... - - -Here is the pin from the .lib file... Since the above is a rising transition, I think something in the "rise" part should add up to 183.19? - -``` -library (Element) { - comment : ""; - delay_model : table_lookup; - simulation : false; - capacitive_load_unit (1,fF); - leakage_power_unit : 1pW; - current_unit : "1A"; - pulling_resistance_unit : "1kohm"; - time_unit : "1ps"; - voltage_unit : "1v"; - library_features(report_delay_calculation); - - input_threshold_pct_rise : 50; - input_threshold_pct_fall : 50; - output_threshold_pct_rise : 50; - output_threshold_pct_fall : 50; - slew_lower_threshold_pct_rise : 10; - slew_lower_threshold_pct_fall : 10; - slew_upper_threshold_pct_rise : 90; - slew_upper_threshold_pct_fall : 90; - slew_derate_from_library : 1.0; - - - nom_process : 1.0; - nom_temperature : 0.0; - nom_voltage : 0.77; - - lu_table_template(template_1) { - variable_1 : total_output_net_capacitance; - index_1 ("1.44000, 2.88000, 5.76000, 11.52000, 23.04000, 46.08000, 92.16000"); - } -[deleted] - type ("io_outs_left") { - base_type : array; - data_type : bit; - bit_width : 64; - bit_from : 63; - bit_to : 0; - } -[deleted] - pin("io_outs_left[0]") { - direction : output; - capacitance : 0.0000; - timing() { - related_pin : "clock"; - timing_type : rising_edge; - cell_rise(template_1) { - values("179.22894,181.54152,185.64272,193.40265,208.65739,239.04976,299.74982"); - } - rise_transition(template_1) { - values("7.61338,11.68247,19.95989,36.84301,71.06670,139.93100,277.88907"); - } - cell_fall(template_1) { - values("176.95767,179.16806,182.98384,189.92587,203.38441,230.16859,283.65878"); - } - fall_transition(template_1) { - values("6.99804,10.42909,17.26771,31.14958,59.35967,116.35495,230.77396"); - } - } - } -``` - -When I look at mock-array, I see that the wire is highlighted in yellow when I clock on the Element delay. - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/092fe3d1-a379-4937-b6b3-408fa28d3000) - -But when I click on the next line, that wire segment is also highlighted. - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/5c812814-acfc-4093-9238-6ef7af09c91b) - - -So I guess the wire segments are associated with some of the lines in the timing list, but I can't see what the delay is due to the wire and I don't know which item that delay is associated with. I have seen separate "wire" lines in the timing report for `make gui_final`, but not in this case... - - - -### maliberty -You might try report_dcalc. Also ```report_checks -path_delay min -fields {slew cap input nets fanout} ``` helps to break out the gate and net delay. - -In general it isn't a simple calculation when there are wire parasitics. With a simple capacitive load you just look at the table and interpolate. - -In this case I would suspect input slews might be different between block and top level. - -### rovinski -Maybe take a read of this article to help understand the non-linear delay model (NLDM) for .lib: -https://www.physicaldesign4u.com/2020/05/non-linear-delay-model-nldm-in-vlsi.html - -The "exact number" will never appear in the .lib file. The .lib file creates a series of lookup tables. The inputs to those lookup tables are the capacitance of the wiring on the output and the input slew. If the inputs are not exactly one of the keys in the lookup table (which they usually aren't because of floating point numbers) then the output is interpolated. You will almost never see the "exact" delay value appear in the .lib file itself. - -### maliberty -```report_dcalc -from output3073/A -to output3073/Y``` -works but the report is not simple to interpret - -### maliberty -What is your goal in this process? Likely there is more calculation in the interconnect side of the delay. - -You can only use it on a single arc and not along a path. - -### oharboe -I am looking at some numbers that are concerning and I wanted to understand this well enough that I can find out if OpenROAD/STA are probably working correctly or if the numbers are off and it is worth digging in to. - -I think I do now. - diff --git a/gh_discussions/Query/3763.md b/gh_discussions/Query/3763.md deleted file mode 100644 index 9cde43b1de728e02c874796aef88563a76030f30..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/3763.md +++ /dev/null @@ -1,63 +0,0 @@ -# How can I set a false path within a macro? - -Tool: OpenSTA - -Subcategory: Usage question - -## Conversation - -### oharboe -I want to set a false path for two pins on a macro, but not at the macro's level, but rather at the containing macros level. - -I looked at -https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/bf9f1e81bfabb85c0bfe794d18a4ea82dda83872/flow/designs/tsmc65lp/vanilla5/constraint.sdc#L724 - -and thought it was supported. Though when I read https://github.com/The-OpenROAD-Project/OpenSTA/blob/3275a304e17092895b7d7721148edc7dc67ba3aa/search/Sta.cc#L2080, it looks like I can only use the ports of the macro for the constraints.sdc file as `-to` and `-from`. - -No changes are intended for mock-array w.r.t. this, I'm only using mock-array to illustrate what I'm trying to find the syntax for: - -``` ->>> set_false_path -from [get_pins ces_6_6/io_ins_right*] -to [get_pins ces_6_6/io_outs_right*] -[WARNING STA-0018] 'ces_6_6/io_ins_right[0]' is not a valid start point. -[WARNING STA-0018] 'ces_6_6/io_ins_right[10]' is not a valid start point. -[WARNING STA-0018] 'ces_6_6/io_ins_right[11]' is not a valid start point. -[WARNING STA-0018] 'ces_6_6/io_ins_right[12]' is not a valid start point. -``` - - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/65c8550d-3187-4503-a1b7-2e35c81ccba6) - - -### vijayank88 -@oharboe -I got this from OpenSTA user guide: -``` -from_list A list of clocks, instances, ports or pins. -through_list A list of instances, pins or nets. -to_list A list of clocks, instances, ports or pins. -``` -So as per this you can provide `pins` also. -``` -The **set_false_path** command disables timing along a path from, through and to a group of design objects. - -Objects in **from_list** can be clocks, register/latch instances, or register/latch clock pins. The -rise_from -and -fall_from keywords restrict the false paths to a specific clock edge. - -Objects in **through_list** can be nets, instances, instance pins, or hierarchical pins,. The -rise_through -and -fall_through keywords restrict the false paths to a specific path edge that traverses through the -object. - -Objects in **to_list** can be clocks, register/latch instances, or register/latch clock pins. The -rise_to and - -fall_to keywords restrict the false paths to a specific transition at the path end. -``` - -### maliberty -You probably need to use -through as those points are not the beginning or end of a timing path. - -### maliberty -I suspect you want - -set_false_path -through [get_pins ces_6_6/io_ins_right*] -through [get_pins ces_6_6/io_outs_right*] - - - diff --git a/gh_discussions/Query/3766.md b/gh_discussions/Query/3766.md deleted file mode 100644 index 130fedb4dded2a54286b402abce93f6e55e46135..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/3766.md +++ /dev/null @@ -1,35 +0,0 @@ -# What does "time given to startpoint" mean? - -Tool: OpenSTA - -Subcategory: Timing analysis - -## Conversation - -### oharboe -Silly question... - -``` ->>> report_checks -path_delay max -through [get_pins foo*] -format full_clock_expanded -fields {net slew cap} -Startpoint: yyy (positive level-sensitive latch clocked by clock) -Endpoint: zzz (output port clocked by clock) -Path Group: clock -Path Type: max - -Fanout Cap Slew Delay Time Description ------------------------------------------------------------------------------ - 0.00 0.00 clock clock (rise edge) - 0.00 0.00 clock source latency - 0.00 0.00 0.00 ^ clock (in) -[deleted] - 580.10 4606.57 time given to startpoint -[deleted] -´´´ - - -### maliberty -I think you want to resolve "positive level-sensitive latch" first. I think it relates to latch transparency. - -### oharboe -Fixed in #3762 - diff --git a/gh_discussions/Query/3771.md b/gh_discussions/Query/3771.md deleted file mode 100644 index c858c2d3972aa9ea2bc3dfaa164524b3b0128841..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/3771.md +++ /dev/null @@ -1,24 +0,0 @@ -# Generate report - -Tool: OpenSTA - -Subcategory: Reporting - -## Conversation - -### AayushiRV -Is there any way to generate a report for max cap, max fanout and max slew after “repair_design” is applied? - -### maliberty -If you are using ORFS then we already do that in 3_4_place_resized.log. If any flow you can insert the relevant commands. - -### AayushiRV -I am not using ORFS. - -### maliberty -You can add ``` report_check_types -max_slew -max_capacitance -max_fanout``` to whatever you are using then - -### AayushiRV -OK, I am using this, if after using this command nothing is shown does that means all the violations are cleared? - - diff --git a/gh_discussions/Query/3772.md b/gh_discussions/Query/3772.md deleted file mode 100644 index e53cb0e58cbd2e23d5e5b4912bc7bbc80245f262..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/3772.md +++ /dev/null @@ -1,151 +0,0 @@ -# Reducing slew on clock tree with set_max_transition? - -Tool: Gate Resizer - -Subcategory: Usage question - -## Conversation - -### oharboe -With `make DESIGN_CONFIG=designs/asap7/sram-64x16/config.mk` I get a lot of slew and I heard about `set_max_transition` and found it used in some designs in ORFS, so I thought I would see what it did... - - -``` -========================================================================== -resizer pre report_checks -path_delay max --------------------------------------------------------------------------- -Startpoint: _358_ (falling edge-triggered flip-flop clocked by io_clk') -Endpoint: io_ram_dout2[43] (output port clocked by io_clk) -Path Group: io_clk -Path Type: max - -Fanout Cap Slew Delay Time Description ------------------------------------------------------------------------------ - 0.00 0.00 0.00 clock io_clk' (fall edge) - 0.00 0.00 clock network delay (ideal) - 0.00 0.00 0.00 v _358_/CLK (DFFLQNx1_ASAP7_75t_R) - 95.79 123.37 123.37 v _358_/QN (DFFLQNx1_ASAP7_75t_R) - 1 6.79 _038_ (net) - 96.33 4.05 127.42 v _173_/A (INVx3_ASAP7_75t_R) - 45.29 35.23 162.65 ^ _173_/Y (INVx3_ASAP7_75t_R) - 1 3.94 io_ram_dout2[43] (net) - 45.43 1.45 164.10 ^ io_ram_dout2[43] (out) - 164.10 data arrival time - - 0.00 500.00 500.00 clock io_clk (rise edge) - 0.00 500.00 clock network delay (ideal) - 0.00 500.00 clock reconvergence pessimism - -100.00 400.00 output external delay - 400.00 data required time ------------------------------------------------------------------------------ - 400.00 data required time - -164.10 data arrival time ------------------------------------------------------------------------------ - 235.90 slack (MET) -``` - - -0.050 ns seems to be a good place to start to bring down the slew from 95.79 above. - -When I add `set_max_transition 0.05 [current_design]` to the constraints.sdc, the flow seems to get stuck: - -``` -Perform port buffering... -[INFO RSZ-0027] Inserted 79 input buffers. -[INFO RSZ-0028] Inserted 128 output buffers. -Perform buffer insertion... -[INFO RSZ-0058] Using max wire length 232um. -[no further output after 10 minutes or so] -``` - -maybe the units are picoseconds? `set_max_transition 50 [current_design]`, same result, resizing doesn't seem to complete. - -Created a draft pull request to check if it completes... https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/pull/1315 - - -### maliberty -You are setting it 0.05ps not ns which is an impossibly fast target. - -### oharboe -`set_max_transition 80 [current_design]` is as low as I could get and `make cts` completing in a reasonable amount of time. - -Lots of violations: - -``` -========================================================================== -cts final report_check_types -max_slew -max_cap -max_fanout -violators --------------------------------------------------------------------------- -max slew - -Pin Limit Slew Slack ------------------------------------------------------------- -_8_44/A 80.00 330.31 -250.31 (VIOLATED) -_8_46/A 80.00 309.18 -229.18 (VIOLATED) -clkbuf_4_4_0_io_clk/Y 80.00 294.55 -214.55 (VIOLATED) -SRAM2RW16x32_2/CE1 80.00 249.22 -169.22 (VIOLATED) -SRAM2RW16x32_2/CE2 80.00 249.17 -169.17 (VIOLATED) -SRAM2RW16x32/CE1 80.00 224.86 -144.86 (VIOLATED) -SRAM2RW16x32/CE2 80.00 224.83 -144.83 (VIOLATED) -_58_73/A 80.00 193.42 -113.42 (VIOLATED) -_58_74/A 80.00 193.40 -113.40 (VIOLATED) -_8_52/A 80.00 193.35 -113.35 (VIOLATED) -_8_51/A 80.00 193.32 -113.32 (VIOLATED) -_8_48/A 80.00 193.25 -113.25 (VIOLATED) -_8_53/A 80.00 193.22 -113.22 (VIOLATED) -_8_50/A 80.00 193.03 -113.03 (VIOLATED) -_58_66/A 80.00 192.96 -112.96 (VIOLATED) -_58/A 80.00 192.91 -112.91 (VIOLATED) -_58_71/A 80.00 192.76 -112.76 (VIOLATED) -_58_60/A 80.00 192.65 -112.65 (VIOLATED) -_58_67/A 80.00 192.64 -112.64 (VIOLATED) -_8_17/A 80.00 192.28 -112.28 (VIOLATED) -_8_18/A 80.00 192.23 -112.23 (VIOLATED) -clkbuf_4_11_0_io_clk/Y 80.00 191.85 -111.85 (VIOLATED) -_8_55/A 80.00 154.73 -74.73 (VIOLATED) -_8_24/A 80.00 154.72 -74.72 (VIOLATED) -_58_70/A 80.00 154.72 -74.72 (VIOLATED) -_58_77/A 80.00 154.71 -74.71 (VIOLATED) -_8_54/A 80.00 154.67 -74.67 (VIOLATED) -_8_49/A 80.00 154.66 -74.66 (VIOLATED) -_8_57/A 80.00 154.55 -74.55 (VIOLATED) -_58_75/A 80.00 154.42 -74.42 (VIOLATED) -_58_63/A 80.00 154.36 -74.36 (VIOLATED) -clkbuf_4_10_0_io_clk/Y 80.00 153.74 -73.74 (VIOLATED) -SRAM2RW16x32_3/CE1 80.00 148.30 -68.30 (VIOLATED) -_8_19/A 80.00 142.96 -62.96 (VIOLATED) -_8_36/A 80.00 142.96 -62.96 (VIOLATED) -clkbuf_4_2_0_io_clk/Y 80.00 142.96 -62.96 (VIOLATED) -clkbuf_4_9_0_io_clk/A 80.00 140.76 -60.76 (VIOLATED) -clkbuf_4_8_0_io_clk/A 80.00 140.75 -60.75 (VIOLATED) -clkbuf_4_10_0_io_clk/A 80.00 139.69 -59.69 (VIOLATED) -clkbuf_4_4_0_io_clk/A 80.00 139.66 -59.66 (VIOLATED) -clkbuf_4_5_0_io_clk/A 80.00 139.65 -59.65 (VIOLATED) -clkbuf_4_11_0_io_clk/A 80.00 139.64 -59.64 (VIOLATED) -clkbuf_4_6_0_io_clk/A 80.00 139.22 -59.22 (VIOLATED) -clkbuf_4_7_0_io_clk/A 80.00 139.19 -59.19 (VIOLATED) -clkbuf_4_0_0_io_clk/A 80.00 138.58 -58.58 (VIOLATED) -clkbuf_4_1_0_io_clk/A 80.00 138.12 -58.12 (VIOLATED) -clkbuf_4_15_0_io_clk/A 80.00 137.02 -57.02 (VIOLATED) -clkbuf_4_14_0_io_clk/A 80.00 137.02 -57.02 (VIOLATED) -clkbuf_4_13_0_io_clk/A 80.00 137.01 -57.01 (VIOLATED) -clkbuf_4_12_0_io_clk/A 80.00 136.99 -56.99 (VIOLATED) -clkbuf_4_3_0_io_clk/A 80.00 136.86 -56.86 (VIOLATED) -clkbuf_4_2_0_io_clk/A 80.00 136.22 -56.22 (VIOLATED) -clkbuf_0_io_clk/Y 80.00 132.32 -52.32 (VIOLATED) -SRAM2RW16x32_2/O2[23] 0.23 45.42 -45.19 (VIOLATED) -SRAM2RW16x32_2/O2[24] 0.23 45.26 -45.04 (VIOLATED) -SRAM2RW16x32_2/O2[16] 0.23 41.77 -41.54 (VIOLATED) -SRAM2RW16x32_3/CE2 80.00 120.37 -40.37 (VIOLATED) -SRAM2RW16x32_2/O2[30] 0.23 40.24 -40.01 (VIOLATED) -SRAM2RW16x32_2/O2[26] 0.23 38.87 -38.65 (VIOLATED) -SRAM2RW16x32_2/O2[29] 0.23 38.54 -38.31 (VIOLATED) -SRAM2RW16x32_2/O2[12] 0.23 38.16 -37.93 (VIOLATED) -SRAM2RW16x32_2/O2[17] 0.23 36.78 -36.55 (VIOLATED) -SRAM2RW16x32_2/O2[7] 0.23 36.69 -36.46 (VIOLATED) -``` - -### oharboe -This PR uses set_max_transition. I have an example to study now, so closing. - -https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/pull/1311 - diff --git a/gh_discussions/Query/3800.md b/gh_discussions/Query/3800.md deleted file mode 100644 index e4ee9f98afe1e7645da944155515de7fd662b30d..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/3800.md +++ /dev/null @@ -1,170 +0,0 @@ -# Why three buffers for a through signal in mock-array/Element? - -Tool: Verilog to DB - -Subcategory: Usage question - -## Conversation - -### oharboe -Using https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/pull/1322(soon to be merged, but the same issue exists in master), I looked at a path going through Element (no registers, just a signal going from left to right through the Element): - -There are three buffers in this path: input, a middle buffer inserted by synthesis, and an output buffer. The input and output buffers are introduced by OpenROAD. What motivates synthesis to introduce this middle buffer? Isn't that the job of resizing? - -From 1_synth.v we see the middle buffer: - -``` - BUFx2_ASAP7_75t_R _776_ ( - .A(io_lsbIns_5), - .Y(io_lsbOuts_4) - ); -``` - -The buffer is inserted by this code: - -https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/4a6fdcebf8361481090acde05d596e8db946c806/flow/scripts/synth.tcl#L96 - -``` ->>> report_checks -path_delay max -to io_lsbOuts_4 -fields {slew net cap} -Startpoint: io_lsbIns_5 (input port) -Endpoint: io_lsbOuts_4 (output port) -Path Group: path delay -Path Type: max - -Fanout Cap Slew Delay Time Description ------------------------------------------------------------------------------ - 0.00 0.00 v input external delay - 6.80 0.80 0.80 v io_lsbIns_5 (in) - 1 0.83 io_lsbIns_5 (net) - 4.97 12.72 13.52 v input261/Y (BUFx2_ASAP7_75t_R) - 1 0.79 net261 (net) - 13.54 15.20 28.72 v _776_/Y (BUFx3_ASAP7_75t_R) - 1 5.63 net268 (net) - 17.44 23.37 52.09 v output268/Y (BUFx4f_ASAP7_75t_R) - 1 10.23 io_lsbOuts_4 (net) - 17.59 0.91 53.00 v io_lsbOuts_4 (out) - 53.00 data arrival time - - 29.60 29.60 max_delay - 0.00 29.60 output external delay - 29.60 data required time ------------------------------------------------------------------------------ - 29.60 data required time - -53.00 data arrival time ------------------------------------------------------------------------------ - -23.40 slack (VIOLATED) - -``` - -Overview: - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/bd71b9bc-4f8e-4b36-a922-825c52c25fbd) - -The two nearly back-to-back buffers on the output: - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/c5eb763c-10c1-4be0-8b8d-1279242608c7) - - -Moreover: there are two buffers(synthesis introduced buffer + output buffer) nearly back to back at the output. The Element is routed by abutment horizontall, so we get a third input buffer immediately from the Element to the right. - - -If I disable https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/4a6fdcebf8361481090acde05d596e8db946c806/flow/scripts/synth.tcl#L96, I get no buffers, which was unexpected as OpenROAD, not synthesis inserts input and output buffers... - -``` ->>> report_checks -path_delay max -to io_lsbOuts_4 -fields {slew net cap} -Startpoint: io_lsbIns_5 (input port) -Endpoint: io_lsbOuts_4 (output port) -Path Group: path delay -Path Type: max - -Fanout Cap Slew Delay Time Description ------------------------------------------------------------------------------ - 0.00 0.00 ^ input external delay - 31.60 16.96 16.96 ^ io_lsbIns_5 (in) - 1 15.09 io_lsbIns_5 (net) - 42.77 0.00 16.96 ^ io_lsbOuts_4 (out) - 16.96 data arrival time - - 29.60 29.60 max_delay - 0.00 29.60 output external delay - 29.60 data required time ------------------------------------------------------------------------------ - 29.60 data required time - -16.96 data arrival time ------------------------------------------------------------------------------ - 12.64 slack (MET) -``` - -At the mock-array level, I see something unexpected, 0 delay for the in-out paths: - -``` ->>> report_checks -path_delay max -through ces_7_1/io_lsbIns_* -fields {net cap slew} -Startpoint: ces_7_0 (rising edge-triggered flip-flop clocked by clock) -Endpoint: ces_7_4 (rising edge-triggered flip-flop clocked by clock) -Path Group: clock -Path Type: max - -Fanout Cap Slew Delay Time Description ------------------------------------------------------------------------------ - 0.00 0.00 clock clock (rise edge) - 287.91 287.91 clock network delay (propagated) - 83.67 0.00 287.91 ^ ces_7_0/clock (Element) - 3.44 164.65 452.56 v ces_7_0/io_lsbOuts_7 (Element) - 1 0.00 ces_7_0_io_lsbOuts_7 (net) - 5.80 0.00 452.56 v ces_7_1/io_lsbOuts_6 (Element) - 1 0.00 ces_7_1_io_lsbOuts_6 (net) - 5.80 0.00 452.56 v ces_7_2/io_lsbOuts_5 (Element) - 1 0.00 ces_7_2_io_lsbOuts_5 (net) - 5.80 0.00 452.56 v ces_7_3/io_lsbOuts_4 (Element) - 1 0.69 ces_7_3_io_lsbOuts_4 (net) - 5.80 0.00 452.56 v ces_7_4/io_lsbIns_4 (Element) - 452.56 data arrival time - - 300.00 300.00 clock clock (rise edge) - 238.74 538.74 clock network delay (propagated) - -10.00 528.74 clock uncertainty - 1.40 530.14 clock reconvergence pessimism - 530.14 ^ ces_7_4/clock (Element) - 70.02 600.16 library setup time - 600.16 data required time ------------------------------------------------------------------------------ - 600.16 data required time - -452.56 data arrival time ------------------------------------------------------------------------------ - 147.59 slack (MET) -``` - - - - -### maliberty -The third buffer buffer looks to have been from yosys. I imagine the incoming netlist was a single buffer (_776_). The other two come from buffer_ports. You could skip that if you want a single buffer. - -### oharboe -> The third buffer buffer looks to have been from yosys. - -Yep. - -> I imagine the incoming netlist was a single buffer (_776_). The other two come from buffer_ports. You could skip that if you want a single buffer. - -Surprisingly, the input output buffers go away if I disable yosys buffer insertions. Any thoughts about why that is happening? - -It sounds like you only expected input/output buffers in this case... - -How can I disable output/input buffers for only in-out paths and is it a good idea in this case? - -Also, I didn't expect zero propagation time when there are no buffers, is that expected? - - - - - - - -### oharboe -@maliberty One last question, why is this line in synth.tcl? I understand what it does, I just don't know why it is there. - -``` -insbuf -buf {*}$::env(MIN_BUF_CELL_AND_PORTS) -``` - diff --git a/gh_discussions/Query/3846.md b/gh_discussions/Query/3846.md deleted file mode 100644 index 75d1f2420ecc93aab9e0eaad07da0c41a82cbd89..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/3846.md +++ /dev/null @@ -1,61 +0,0 @@ -# Does TritonRoute support all design rules in ISPD 2014/2015 tech files? - -Tool: Detailed Routing - -Subcategory: Design rule support - -## Conversation - -### liangrj2014 -We wonder whether TritonRoute support all design rules in ISPD 2014/2015 tech files (https://www.ispd.cc/contests/14/web/benchmarks.html)? Example design rules are as follows: - -1. PROPERTY LEF57_MINSTEP "MINSTEP 0.100 MAXEDGES 1 ;" ; -2. MINIMUMCUT 2 WIDTH 0.400 ; -3. MINENCLOSEDAREA 0.30 ; -4. PROPERTY LEF57_SPACING "SPACING 0.13 PARALLELOVERLAP ;”; - - -### maliberty -We test with ispd 18&19 but not those. 2 is only relevant for pdn and I know we support 3. @osamahammad21 would you check on 1 & 4 - -### refaay -We currently parse for LEF58 rules. We don't parse LEF57 (by looking at /src/odb/src/lefin/lefin.cpp and /src/drt/src/io/io.cpp). -I will start a PR for parsing LEF57. - -Also, we don't support PARALLELOVERLAP option for LEF58_SPACING in drt according to io.cpp: - -``` -case odb::dbTechLayerCutSpacingRule::CutSpacingType::PARALLELOVERLAP: - logger_->warn(utl::DRT, - 260, - "Unsupported LEF58_SPACING rule for layer {} of type " - "PARALLELOVERLAP.", - layer->getName()); - break; -``` - -We support MAXEDGES for LEF58_MINSTEP as in io.cpp: - -``` -for (auto rule : layer->getTechLayerMinStepRules()) { - auto con = make_unique(); - con->setMinStepLength(rule->getMinStepLength()); - con->setMaxEdges(rule->isMaxEdgesValid() ? rule->getMaxEdges() : -1); - con->setMinAdjacentLength( - rule->isMinAdjLength1Valid() ? rule->getMinAdjLength1() : -1); - con->setEolWidth(rule->isNoBetweenEol() ? rule->getEolWidth() : -1); - tmpLayer->addLef58MinStepConstraint(con.get()); - tech_->addUConstraint(std::move(con)); - } -``` - -### maliberty -We could add support for new rules if there is strong interest - -### refaay -Hi @liangrj2014 , we added support for PROPERTY LEF57_MINSTEP & PROPERTY LEF57_SPACING. -Also, support for PARALLELOVERLAP will be added soon. - -### refaay -@liangrj2014 PARALLELOVERLAP is now supported for LEF57_SPACING &LEF58_SPACING properties. - diff --git a/gh_discussions/Query/3871.md b/gh_discussions/Query/3871.md deleted file mode 100644 index 2174e4745ac57b7cf95c4aae454d24124c071bc6..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/3871.md +++ /dev/null @@ -1,47 +0,0 @@ -# Where can I find the block findInst implementation? - -Tool: OpenDB - -Subcategory: Implementation details - -## Conversation - -### oharboe -Silly question: where do I find the source code for `findInst`? - -I seem unable to find it in the OpenROAD source code. - -``` - set inst [$block findInst [format "ces_%d_%d" $row $col]] -``` - -https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/f90d853b3705338fa2d142acd20ac57626c71f12/flow/designs/asap7/mock-array/macro-placement.tcl#L10 - - - -### QuantamHD -Header: https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/odb/include/odb/db.h#L992 -Impl: https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/odb/src/db/dbBlock.cpp#L1790 -Hidden Impl: https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/odb/src/db/dbBlock.h#L173 - -### oharboe -So `findInst` doesn't throw an exception if the element doesn't exist, like https://cplusplus.com/reference/map/map/at/ does. - -This leads to a lot of repetition and context unique error messages and in tcl very poor error messages like: - -``` -Error: macro-placement.tcl, 27 invalid command name "NULL" -``` - -`std::map` has explicit accessors that either creates an element if it doesn't exist(returns empty by default) and another that throws an exception if it doesn't exist. - -The equivalent here would be that findInst() threw an exception with an error message and the name, and that another hasInst() that doesn't and allows the user to handle it. try/catch is not approperiate because both findInst() that throws exception and hasInst() that checks for presence would both be part of normal exception. - -### maliberty -The odb code is old and was written without the use of exceptions. I would be fine to change that but it will require testing the full app to see if problems arise and resolving them. There are a number of similar APIs that return nullptr on failure. - -### oharboe -I see. I was just curious and surprised: there are LOT of methods in that .h file that are exposed in .tcl. - -Not all of them are obviously compatible with a .tcl calling convention or even intended for .tcl? - diff --git a/gh_discussions/Query/3881.md b/gh_discussions/Query/3881.md deleted file mode 100644 index b7372c7c3cb2e64e969c7bbc49732f24753b6806..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/3881.md +++ /dev/null @@ -1,121 +0,0 @@ -# Comparing ASAP7 and sky130hd with respect to ALU operations - -Subcategory: Usage question - -## Conversation - -### oharboe -The [mock-alu](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow/designs/src/mock-alu) allows studying the speed and area of various typical ALU operations. - -The mock-alu has two 64 bit inputs and one 64 bit output. The inputs and outputs are registered within the mock-alu. This is to have clear boundary conditions when studying the guts of the mock-alu. - -The mock-alu implements a number of operations and variants of these operations to study the area and minimum clock period for these operations. - -The operations fall into a couple of categories: - -- *add, subtract and compare*: ADD, SUB, SETCC_EQ(equal), SETCC_NE (not equal), SETCC_LT (less than), SETT_LE (less than or equal), SETCC_ULT (unsigned less than), SETCC_ULE(unsigned less than or equal) -- *barrel shifter*: SHR(logical shift right), SRA(arithmetic shift right), SHL(shift left) -- *bitwise logic*: OR(bitwise or), AND(bitwise and), XOR(bitwise xor) -- *multiplication*: 64 bit multiply. There are various algorithms used, default Han Carlson. The implementation is PDK specific and comes from https://github.com/antonblanchard/vlsiffra/ -- *multiplexor*: MUX1..8. This is not really an ALU operation. All that is happening here is that bits from the input as selected using a mux and put into the output. This allows studying the performance of the mux that sits before the output of an ALU, which is selecting between the various supported operations. - -Next, the mock-alu allows implementing any combination of these operations. This allows implementing an ALU that only supports the shift operations, which can be labelled "SHR,SHL,SRA". This shift operation only mock-alu has a single shared barrelshifter. Similarly, a bitwise logic only mock-alu, can be labelled "OR,AND,XOR". - -At this point, we can plot various mock-alu implementations for ASAP7 and sky130hd: - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/b9234684-43f4-4a74-98dd-81cf8b74f9ce) - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/fefae238-58ed-4bfe-a307-780046acdb83) - -Here 8,16,32 and 64 wide ADD operations are plotted: - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/f4a837e6-700c-4436-81ac-221bdfafdb57) - -Various multiplication algorithms for 64 bit multiplication, 4 pipeline stages: - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/0a8d6518-5999-4d18-87fa-38a13857764f) - -Plotting Han Carlson multiply algorithm with 8, 16, 32 and 64 bit bit width: - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/97fb01d7-e535-4578-9fe9-cdb80a4e945f) - -Thoughts? - -### maliberty -Its interesting that the various multiply algorithms have the same delay (excluding ripple). - -I don't see a MULT for sky130 - -### oharboe -Here are the `vlsi-adder` algorith, excluding ripple that was ca. 2000+ ps. It would have made the graph harder to read: - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/07c8e764-81d1-48fe-858a-39175a1d3c68) - - -### maliberty -Do all your runs end in negative slack at the end of the cts & the complete flow? Once we reach zero slack we stop optimizing. - -### maliberty -One thing worth noting is that asap7 doesn't have a full or half adder cells in the library (sky130 does). - -### mithro -BTW Have you seen Teo's spreadsheet @ https://docs.google.com/spreadsheets/d/1pTGzZo5XYU7iuUryxorfzJwNuE9rM3le5t44wmLohy4/edit#gid=126548956 ? - -### mithro -BTW I would love to get a similar spreadsheet to Teo's for GF180MCU and ASAP7 too. - -Sadly, Teo got distracted by the mathematical theory and then was stolen by NVIDIA before he could get to that. - -### tspyrou -@oharboe did you try using set_clock_uncertainty to force the slack to be negative and make the tool work harder. -As @maliberty mentioned optimization will stop once timing passes. - -### mithro -@oharboe - Any chance you could do a write up of what you discovered? - -### oharboe -> There is a lot bunch of back and forth and I'm unclear what the final results are (and exactly how you produced them). -> -> Various questions include; -> -> * How do I reproduce your results and graphs? - -Run this script: https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/flow/designs/src/mock-alu/plot-area-min-clock-period.py - -Some tinkering required. - -> * What settings did you end up using and why did you end up using those settings? (Particularly around making the tool work harder?) - -I didn't study how to make a best possible ALU, I was only interested the relationship between the ALU operations. - -> * How do the various implementations compare? Do you understand why the compare this way? - -The various implementation of additions and multiplications? - -It is a mystery why there is essentially no difference between multiplication implementation clock periods... - -> * How do SKY130 and ASAP7 compare in the end here? - -The lessons learned on the relative size and speed of ALU operations appear to be much the same with SKY130 and ASAP7. Which is surprising. Ca. 15 years separate them... - -> * Do the relative "positions" between the implementations hold across SKY130 and ASAP7? - -Pretty much. - -> * What was the most interesting / unexpected thing you discovered? - -That relative size and speed of simple ALU operations are essentially unchanged across process nodes. - -Also, it would appear that if an ALU operation is 200ps on x86 7nm, yielding 5GHz, then one could choose to divide clock period of ASAP7+OpenROAD by 4 for simple ALU operations when one models and decide to take the lessons learned and apply them to architectural exploration. Further choose to treat the speed of ASAP7+OpenROAD as not terribly important in terms of making architctural choices as the choices will be the same if everything is optimized. - -By this I mean that to drive your architctural exploration, as a [first order approximation](https://en.wikipedia.org/wiki/Order_of_approximation#First-order), write the RTL in an idiomatic way, run them through ASAP7+OpenROAD and if your design is 4x the desired clock period, your design isn't completely off. - -Nobody who have information on commercial tools and PDKs can challenge me here. :-) Not because I'm right, but because PDKs and commercial tools are under strict NDAs... This also explains why there are a lot of unsaid things in this thread... - -> Writing it up as a nice coherent blog post would be pretty awesome but totally understand if you do nt have the time to do so. - -Agreed. At least I summarize a bit here. I'm happy to hear that there are some that are interested in this. - -Perhaps you would like to write a blog-post using the script above? - - diff --git a/gh_discussions/Query/3915.md b/gh_discussions/Query/3915.md deleted file mode 100644 index 91100c398a200cf7cf2dccdc2ceca3442719f5b7..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/3915.md +++ /dev/null @@ -1,28 +0,0 @@ -# Slack histogram horizontal axis - -Tool: Graphical User Interface - -Subcategory: Visualization issue - -## Conversation - -### oharboe -What is the horizontal axis? - -I would have thought picoseconds, but the horizontal axis is not labeled... - - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/9b5c6daa-25f6-42b7-adf4-e11c30bf3234) - -This is from `make gui_place` in #3910 - -### oharboe -Also, when I click on "Endpoint slack" upper left corner, it looks like there should have been more than one choice? - -https://drive.google.com/file/d/1xCo_SBrhFjxZfQ-IOakjJyKaGkyZcZIP/view?usp=sharing - -### maliberty -It looks like -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/761514/202fee93-b91e-4c1c-a8da-65d0e27a213c) - is in the wrong place @AcKoucher any idea why? - diff --git a/gh_discussions/Query/3931.md b/gh_discussions/Query/3931.md deleted file mode 100644 index 1b5fa40b29b43a44f33767ca42ae7314331e0a53..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/3931.md +++ /dev/null @@ -1,16 +0,0 @@ -# about the meaning of frBlockObjectEnum - -Subcategory: Code understanding - -## Conversation - -### gilgamsh -in src/frBaseTypes.h , there is a enum class called frBlockObjectEnum, and it has lots of types. I want to know the prefix meanings. Such as `frc`,`drc`,`tac`,`gcc` - -### maliberty -The c is for constant. fr = base types, dr = detailed router, ta = track assignment, gc = drc (these correspond to the subdirs of src/). - - -### gilgamsh -Thank you very much - diff --git a/gh_discussions/Query/3955.md b/gh_discussions/Query/3955.md deleted file mode 100644 index d592172317fe170ecd360668c0ab1c01ec9eb06f..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/3955.md +++ /dev/null @@ -1,22 +0,0 @@ -# `-balance_levels` - -Tool: Clock Tree Synthesis - -Subcategory: Tool usage - -## Conversation - -### kareefardi -`-balance_levels` is not documented. What is does this flag do and what are the uses of it? -Edit: -More context: It is a flag for `clock_tree_synthesis` command - -### vvbandeira -@luarss -did we miss this flag? - -### maliberty -When you have a non-register in the clock tree (eg clock-gate or inverter) then it attempts to ensure the are similar number of levels in the tree across that object. The idea is captured in this image -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/761514/eddb3913-086a-4c3f-8744-7a3cadc90543) - - diff --git a/gh_discussions/Query/4061.md b/gh_discussions/Query/4061.md deleted file mode 100644 index 4636830ff0088c03cdc1b810a532f71d0cfbd800..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/4061.md +++ /dev/null @@ -1,35 +0,0 @@ -# How does OpenROAD computes the number of possible locations for IO's ? - -Tool: Pin Placer - -Subcategory: Pin placement - -## Conversation - -### lustefan97 -Hello, - -I have a question to know how does OpenROAD computes the possible IO pin locations, when placed on the top-most metal layer. I use the ASAP7 PDK, I already routed a "hello world" design using the ibex core which has 264 IO pins. Now I want to test a bit the capabilities of OpenROAD and start doing increasingly bigger designs. - -Right now I have a design that has 4100 IO pins to place on the top layer. The die size is 20um x 20um more or less which, since I want to place the IO's on the Pad Layer whose track pitch is 0.08um, would give me more or less 62 tracks on which I can place my pins (mind you I place the pins with a minimum width of 0.32um). The M9 metal layer also has a track pitch of 0.08, so I could think that I would also have 62 tracks on which I could have a pin routed (on top). This would give me 62 x 62 = 3844 potential pin locations with this die size, but the tool give me the following error : - -`[ERROR PPL-0024] Number of IO pins (4100) exceeds maximum number of available positions (788).` - -Which is far less than what I expect, so my questions are as follows : - -1. How does OpenROAD compute those available positions ? -2. Could those locations be linked to an oversight/mistake in my synthesis script ? -3. If I am mistaken in the way to compute the "potential location", how does one compute it properly based of the design size (number of cells/die area) ? - -### maliberty -@eder-matheus please help - -### rovinski -I don't know how the pin capacity is calculated exactly, but I know that the pin placer only works on edges of the die, not across an area. The total pins on the top layer would be around the perimeter, i.e. 62 * 4 = 248. -But, usually PPL does not want to place pins on edges that do not correspond to the preferred direction of that layer. PAD layers may or may not have a preferred direction. The other pins in the 788 reported may be coming from other layers along the edge of the die. - -But anyways, you are probably looking at the wrong tool. You want to be looking at the [PAD tool](https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/pad/README.md) which is meant for bump placement on flip-chip designs, which is much closer to what you are trying to do. - -### maliberty -We support pins over the top of the core area through define_pin_shape_pattern. The number of pins locations will be determined by the region and the x/y step given. If you need to actually place bumps at specific locations that is different than pin placement. What is your goal? - diff --git a/gh_discussions/Query/4062.md b/gh_discussions/Query/4062.md deleted file mode 100644 index 45db4f9c8b7344e25565276784195dce31f85479..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/4062.md +++ /dev/null @@ -1,20 +0,0 @@ -# Openroad compatibility with multi vt cells and mmmc - -Tool: OpenSTA - -Subcategory: Tool compatibility - -## Conversation - -### faisaladilquadery -Can openroad work with multi VT cells ( HVT , LVT , SVT ) and swap between them in a single run ? -also can openroad work with MultiModeMulti Corner File (mmmc) ? - -### maliberty -OR can swap between VT cells. OR supports multi-corner but not multi-mode STA. - -### rovinski -> can openroad work with MultiModeMulti Corner File (mmmc) ? - -If you are asking about MMMC files from commercial vendors, those are proprietary formats which we don't support. We support multi-corner analysis as mentioned. You can look in the [OpenSTA manual](https://github.com/The-OpenROAD-Project/OpenSTA/blob/master/doc/OpenSTA.pdf) to find the relevant commands. - diff --git a/gh_discussions/Query/4155.md b/gh_discussions/Query/4155.md deleted file mode 100644 index 49e4470c0a6312d754514b4674ddcf71b597e4a1..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/4155.md +++ /dev/null @@ -1,50 +0,0 @@ -# PPL vs PAD for IO - -Tool: Pin Placer - -Subcategory: Tool usage clarification - -## Conversation - -### lustefan97 -Hello, - -I have a question regarding the differences between the PPL and PAD tools, especially the PAD bump placement for flip chip designs. I don't really get the differences between the PPL and PAD tools when it comes to IO placed on the top metal layer, and their "relationship" with the GPL tool. - -I am right now doing some tests using different designs using the PPL tool. It is used with GPL first by placing the IO without considering GPL, then doing Global PLacement followed by a Pin PLacement after it, finishing by a final GPL. I read that it was due to some circular dependency between the two tools, so this was the way things were done. -Now I am using PPL to do some 3D Face-to-Face implementation, and am using the `define_pin_shape_pattern` command to place the IO on the top metal layer. - -From what I understood PPL doesn't have/need a LEF object for the bump as it will create a metal shape in place of the pin, based off of the constraint given to the tool by the user before being routed in the subsequent steps. - - -I am now trying to understand what the PAD tool really is about, how it differs from what PPL is and what his use case may be, but I am a bit confused when it comes to 3D interconnect. - -I understand that PAD is used for chip level connection, which raise a question for me (that is asked below), that requires a LEF object for top layer bumps. -When it comes to flip chip design, the PAD tool seems to be the default candidate but something is bothering me, it is simply that there is no pin position optimization in it as opposed to PPL (which would probably not give a minimal "3D" wire length), that the bump assignement is done manually, and that in the example script given in _OpenROAD/src/pad/test_ link the bumps to an IO ring which I don't think is the goal in my application. - -About the pin position optimization, I was told by @rovinski in #4061 that GPL will still do some HPWL optimization (and that the team would probably be interested in implementing 3D interconnect as part of the PPL tool), but at first sight it doesn't seem to be the most optimal way to proceed for "3D" routing since the assignement will be done manually. This leads me to the second question about assignment : Since I will probably need to have thousands of IOs on the top layer, manual assignment seems tedious if not even suboptimal due to the lack of automatic bump repositioning. -I get that using a tool for flip-chip design would be make more sense but I must say that, when it comes to top layer bumps, I don't see really the interest in going for PAD rather than PPL - - - -My questions thus are : - -0) What are the exact mechanisms that OpenROAD use to minimize wire length w.r.t. IO pins ? -1) If PAD is used for chip level connections then what is the use case for PPL ? -2) What are the inherent differences between PAD and PPL ? -3) If PAD is the default for flip-chip design, why implementing such a thing as part of PPL ? -4) Does will OpenROAD route differently when using PAD or PPL ? Especially when talking about memory usage ? -5) Will the use of a LEF object in the PAD tool create a difference with regard to the pin created by PPL ? Could I use a LEF object for PPL instead to benefit from the placement optimization? -6) Could we imaging eventually a flow mixing PAD and PPL, where the PPL tool is used for 3D interconnections ? - - - - -### maliberty -What is driving the bumps? Usually you need an IO driver and that means you need to use pad. - -### QuantamHD -I think the biggest difference between pad and ppl is that pad tries to deal with io cells. Typically the foundry will require you to place specialized io cells that deal with esd and what not. - -ppl does a similar pin placement, but doesn't deal with io cells. If you don't need io cells between your dies then ppl probably is the solution you should use or enhance - diff --git a/gh_discussions/Query/4165.md b/gh_discussions/Query/4165.md deleted file mode 100644 index 4e392eb492dd240248edf1327b4e74f92024844a..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/4165.md +++ /dev/null @@ -1,17 +0,0 @@ -# fastroute: What is the minimum number of metal layers OpenROAD can route in? - -Tool: Detailed Routing - -Subcategory: Routing capabilities - -## Conversation - -### Sleighbells64 -My apologies if this is an obvious question. I am working with a fab trying to develop a new process that currently has 2 metal layers, and we were wondering if we could use OpenROAD/OpenLANE to build test chips. I was unable to find an answer in the documentation, but if it is there I would love to know where to look. Thank you for your help! - -### maliberty -In theory we could route in two layers but we've never tried it. We don't have a specialized channel router. My expectation is that we will hit some issues and have to iterate. If the PDK is closed it will be harder to do so. - -### JackFz -I'm sure that Fastroute and TritonRoute are capable of routing on two layers. - diff --git a/gh_discussions/Query/4287.md b/gh_discussions/Query/4287.md deleted file mode 100644 index 085202a2e8e5ff2fec31b9591e63d321b28f659a..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/4287.md +++ /dev/null @@ -1,17 +0,0 @@ -# OpenRCX query - -Tool: Parasitics Extraction - -Subcategory: Tool functionality - -## Conversation - -### faisaladilquadery -I just want to know if OpenRCX a engine integrated in OpenRoad or is it a RC signoff tool like Cadence Quantas - -### maliberty -It is integrated with OR but aspires to be signoff quality. During optimization we use estimated parasitics. - -### faisaladilquadery -thankyou @maliberty - diff --git a/gh_discussions/Query/4329.md b/gh_discussions/Query/4329.md deleted file mode 100644 index ef13aebdcbdcba417eed680bb8a35a8174e2ccfb..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/4329.md +++ /dev/null @@ -1,28 +0,0 @@ -# Design area utilization seems misleading - -Tool: Graphical User Interface - -Subcategory: Terminology clarification - -## Conversation - -### TanjIsGray -I realized that size of my designs is not matching "design area" reported. On the GUI view I can see my design uses a rectangular space of around 24 um2 (not including the halo) but - - finish report_design_area - Design area 15 u^2 60% utilization. - -was in the log. So, that seems to mean that the macros placed totaled 15 um2 of space but packed into 24 um2 of silicon. It is useful to know both numbers but I think the size of the space inside the halo is more practical to know. It certainly seems that space would be the most likely expectation for the meaning of "design area". - -Just calling attention to this. Not a bug, but users could be easily misled about what it means. - -### rovinski -This is standard terminology. -"Design area": total area consumed by instances. -"Core area": total area in which instances can be placed. -"Die area": the total area of the chip. -Die area >= core area >= design area. Design area utilization (the 60% in the above) is also always expressed as (design area)/(core area) - -### maliberty -By 'halo' do you mean the area between the core and the die area? - diff --git a/gh_discussions/Query/4417.md b/gh_discussions/Query/4417.md deleted file mode 100644 index 9940a072c39203bfeb21c2c72f9912a5c2a9467a..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/4417.md +++ /dev/null @@ -1,26 +0,0 @@ -# How do I get the power for each Instance？ - -Tool: OpenSTA - -Subcategory: Power analysis - -## Conversation - -### LT-HB -How do I get the power for each Instance？I have no power report after reading the odb file in gui. -![power_report](https://github.com/The-OpenROAD-Project/OpenROAD/assets/107295305/d747e889-1ea2-448e-ba0b-11b6c08e2b52) - - - -### maliberty -```report_power -instances [get_cells *]``` should do it. - -### b224hisl -can I get the power of each module? - -### maliberty -There is no per-module report today. If you can express what you want in terms of instance names you could do something like `report_power -instances [get_cells a/b/*]` - -### maliberty -get_cells comes from SDC where a 'cell' is another (poor) name for an instance. - diff --git a/gh_discussions/Query/4532.md b/gh_discussions/Query/4532.md deleted file mode 100644 index a1fab8481ee2c0133b23687e06a1aa9de759d2a4..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/4532.md +++ /dev/null @@ -1,30 +0,0 @@ -# RTLMP_FLOW=True and HIREARCHICAL_SYNTHESIS=1 - -Tool: Hierarchical Macro Placement - -Subcategory: Tool usage - -## Conversation - -### oharboe -Why are these used in combination? - -What happens if I don't? - -https://github.com/The-OpenROAD-Project/OpenROAD/discussions/4529 has an fMax of 125, which isn't enormously impressive. There are 79 levels of logic in the longest path, which indicates to me that something isn't being optimized in synthesis... - -BOOMv documents that it relies heavily on [register retiming](https://docs.boom-core.org/en/latest/sections/physical-realization.html#physical-realization) and I've also observed that it needs [register cloning](https://github.com/The-OpenROAD-Project/OpenROAD/discussions/4522#discussioncomment-8106429) for synchronous reset. - -Hence, I want to try disabling hierarchical synthesis on MegaBoom, but given the long turnaround times, 40 hours, it would be nice to know a little bit about what I'm doing and what I should expect... - -### rovinski -I believe that RTLMP requires hierarchy in the netlist to work at all. If the netlist is flat, RTLMP won't work. - -### oharboe -> At least no public tests. We would have to run the private ones as well. - - - -### gadfort -@oharboe the retiming doesn't work in Yosys (and not in OpenROAD), so that is going to be a limitation. We ran into this as well with something else from the Chisel team folks and there isn't a good solution at the moment - diff --git a/gh_discussions/Query/4602.md b/gh_discussions/Query/4602.md deleted file mode 100644 index 8b45c3ea7f96baf39f944741c1db3ba98175015c..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/4602.md +++ /dev/null @@ -1,17 +0,0 @@ -# About routing constant values to VDD/VSS power rails - -Subcategory: Design optimization - -## Conversation - -### OuDret -Is there any way to route logical constant 1 & 0 to Vdd & Vss power rails instead of using tie cells? Right now I'm using a cell with short circuit between output and power pins, which is really bad in terms of area. - -### maliberty -No there is no facility for that. The supply rails are often noisy and the tie cell provides a more stable output. What is the issue with using a tie cell? - -### stefanottili -Constant propagation should be able to remove all constants unless they're connected to ram/rom/pad/analog macro's, no ? -Which synthesis tool has been used to create the netlist ? -Can yosys do constant propagation ? If so, is it on by default or does it need to be enabled ? - diff --git a/gh_discussions/Query/4660.md b/gh_discussions/Query/4660.md deleted file mode 100644 index bc58f07d6a4f487fe5887364718095ec3f16ea37..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/4660.md +++ /dev/null @@ -1,241 +0,0 @@ -# An inverter + a buffer before an output, superfluous? - -Tool: Gate Resizer - -Subcategory: Design optimization - -## Conversation - -### oharboe -I thought inverters were good at amplifying signals? So is an inverter + buffer on output superfluous? - -I'm not suggesting a change, I'm just trying to learn what is possible/common vs. what OpenROAD is doing. - - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/65b87224-0bb8-497a-bf34-b89ca348d8c7) - -The buffer is added in resizing. - -1. untar [resize.tar.gz](https://github.com/The-OpenROAD-Project/OpenROAD/files/14265925/resize.tar.gz) -2. `./run-me-mock-array_Element-asap7-base.sh` -3. Enter `report_checks -to io_lsbOuts_7` - -``` -$ ./run-me-mock-array_Element-asap7-base.sh -OpenROAD v2.0-12176-g735d54b79 -This program is licensed under the BSD-3 license. See the LICENSE file for details. -Components of this program may be licensed under more restrictive licenses which must be honored. -Warning: There are 7 input ports missing set_input_delay. -Warning: There are 6 output ports missing set_output_delay. -Warning: There is 1 unconstrained endpoint. - -========================================================================== -resizer pre report_design_area --------------------------------------------------------------------------- -Design area 105 u^2 6% utilization. - -========================================================================== -instance_count --------------------------------------------------------------------------- -902 - -========================================================================== -pin_count --------------------------------------------------------------------------- -1299 - -Perform port buffering... -[INFO RSZ-0027] Inserted 257 input buffers. -[INFO RSZ-0028] Inserted 264 output buffers. -Perform buffer insertion... -[INFO RSZ-0058] Using max wire length 162um. -[INFO RSZ-0039] Resized 526 instances. -Repair tie lo fanout... -Repair tie hi fanout... - -========================================================================== -report_floating_nets --------------------------------------------------------------------------- -Warning: There are 7 input ports missing set_input_delay. -Warning: There are 6 output ports missing set_output_delay. -Warning: There is 1 unconstrained endpoint. - -========================================================================== -resizer report_design_area --------------------------------------------------------------------------- -Design area 159 u^2 9% utilization. - -========================================================================== -instance_count --------------------------------------------------------------------------- -1423 - -========================================================================== -pin_count --------------------------------------------------------------------------- -2341 - -openroad> report_checks -to io_lsbOuts_7 -Startpoint: _755_ (rising edge-triggered flip-flop clocked by clock) -Endpoint: io_lsbOuts_7 (output port clocked by clock_vir) -Path Group: clock_vir -Path Type: max - - Delay Time Description ---------------------------------------------------------- - 0.00 0.00 clock clock (rise edge) - 0.00 0.00 clock network delay (ideal) - 0.00 0.00 ^ _755_/CLK (DFFHQNx2_ASAP7_75t_R) - 40.03 40.03 v _755_/QN (DFFHQNx2_ASAP7_75t_R) - 11.28 51.31 ^ _435_/Y (INVx3_ASAP7_75t_R) - 22.51 73.82 ^ output265/Y (BUFx4f_ASAP7_75t_R) - 0.27 74.09 ^ io_lsbOuts_7 (out) - 74.09 data arrival time - - 300.00 300.00 clock clock_vir (rise edge) - 0.00 300.00 clock network delay (ideal) - -20.00 280.00 clock uncertainty - 0.00 280.00 clock reconvergence pessimism - -60.00 220.00 output external delay - 220.00 data required time ---------------------------------------------------------- - 220.00 data required time - -74.09 data arrival time ---------------------------------------------------------- - 145.91 slack (MET) - - -openroad> -``` - - -Checking that this buffer isn't there before resizing: - -``` -$ . vars-mock-array_Element-asap7-base.sh -$ ODB_FILE=results/asap7/mock-array_Element/base/3_3_place_gp.odb openroad -no_init -gui scripts/gui.tcl -OpenROAD v2.0-12176-g735d54b79 -This program is licensed under the BSD-3 license. See the LICENSE file for details. -Components of this program may be licensed under more restrictive licenses which must be honored. -Estimating parasitics ->>> report_checks -to io_lsbOuts_7 -Startpoint: _755_ (rising edge-triggered flip-flop clocked by clock) -Endpoint: io_lsbOuts_7 (output port clocked by clock_vir) -Path Group: clock_vir -Path Type: max - - Delay Time Description ---------------------------------------------------------- - 0.00 0.00 clock clock (rise edge) - 0.00 0.00 clock network delay (ideal) - 0.00 0.00 ^ _755_/CLK (DFFHQNx1_ASAP7_75t_R) - 36.60 36.60 v _755_/QN (DFFHQNx1_ASAP7_75t_R) - 17.65 54.25 ^ _435_/Y (INVx3_ASAP7_75t_R) - 7.12 61.38 ^ io_lsbOuts_7 (out) - 61.38 data arrival time - - 300.00 300.00 clock clock_vir (rise edge) - 0.00 300.00 clock network delay (ideal) - -20.00 280.00 clock uncertainty - 0.00 280.00 clock reconvergence pessimism - -60.00 220.00 output external delay - 220.00 data required time ---------------------------------------------------------- - 220.00 data required time - -61.38 data arrival time ---------------------------------------------------------- - 158.62 slack (MET) -``` - - -### oharboe -There is an option not to buffer ports, but I don't see it used anywhere, nor documented. `buffer_ports` is documented. - -``` -$ DONT_BUFFER_PORTS=1 ./run-me-mock-array_Element-asap7-base.sh -OpenROAD v2.0-12176-g735d54b79 -This program is licensed under the BSD-3 license. See the LICENSE file for details. -Components of this program may be licensed under more restrictive licenses which must be honored. -Warning: There are 7 input ports missing set_input_delay. -Warning: There are 6 output ports missing set_output_delay. -Warning: There is 1 unconstrained endpoint. - -========================================================================== -resizer pre report_design_area --------------------------------------------------------------------------- -Design area 105 u^2 6% utilization. - -========================================================================== -instance_count --------------------------------------------------------------------------- -902 - -========================================================================== -pin_count --------------------------------------------------------------------------- -1299 - -Perform buffer insertion... -[INFO RSZ-0058] Using max wire length 162um. -[INFO RSZ-0039] Resized 521 instances. -Repair tie lo fanout... -Repair tie hi fanout... - -========================================================================== -report_floating_nets --------------------------------------------------------------------------- -Warning: There are 7 input ports missing set_input_delay. -Warning: There are 6 output ports missing set_output_delay. -Warning: There is 1 unconstrained endpoint. - -========================================================================== -resizer report_design_area --------------------------------------------------------------------------- -Design area 155 u^2 9% utilization. - -========================================================================== -instance_count --------------------------------------------------------------------------- -902 - -========================================================================== -pin_count --------------------------------------------------------------------------- -1299 - -openroad> report_checks -to io_lsbOuts_7 -Startpoint: _755_ (rising edge-triggered flip-flop clocked by clock) -Endpoint: io_lsbOuts_7 (output port clocked by clock_vir) -Path Group: clock_vir -Path Type: max - - Delay Time Description ---------------------------------------------------------- - 0.00 0.00 clock clock (rise edge) - 0.00 0.00 clock network delay (ideal) - 0.00 0.00 ^ _755_/CLK (DFFHQNx2_ASAP7_75t_R) - 48.38 48.38 v _755_/QN (DFFHQNx2_ASAP7_75t_R) - 12.54 60.92 ^ _435_/Y (CKINVDCx8_ASAP7_75t_R) - 6.63 67.55 ^ io_lsbOuts_7 (out) - 67.55 data arrival time - - 300.00 300.00 clock clock_vir (rise edge) - 0.00 300.00 clock network delay (ideal) - -20.00 280.00 clock uncertainty - 0.00 280.00 clock reconvergence pessimism - -60.00 220.00 output external delay - 220.00 data required time ---------------------------------------------------------- - 220.00 data required time - -67.55 data arrival time ---------------------------------------------------------- - 152.45 slack (MET) - - -openroad> -``` - - -### maliberty -That option comes from https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/pull/1431 and I don't really remember why we needed it at all. Tom said "I think that the need for this variable should go away when we improve the automatic code." but I don't know what improvement was needed and there is no issue referenced. I don't think it is a good option to have. Do you remember more? - diff --git a/gh_discussions/Query/4742.md b/gh_discussions/Query/4742.md deleted file mode 100644 index 834311faba61e20549ddbd7b390028fda29f35a0..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/4742.md +++ /dev/null @@ -1,24 +0,0 @@ -# Highlight cells belonging to a module - -Tool: Graphical User Interface - -Subcategory: Usage question - -## Conversation - -### scorbetta -Hello all, - -is there a way in the GUI to highlight all standard cells that belong to a given module within the hierarchy? - -### maliberty -You can use the 'Hierarchy Browser' from the 'Windows' menu. If you see -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/761514/979243d1-d259-41ed-b50f-7403f9fbffa6) - -click it to the on the highlighting. An example: -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/761514/5e659e20-c91f-4a76-8c99-544abd423c63) - - -### maliberty -Are you using ORFS? If so set SYNTH_HIERARCHICAL=1 in your config - diff --git a/gh_discussions/Query/4743.md b/gh_discussions/Query/4743.md deleted file mode 100644 index caad3814776911a8825a3f6d768be8138a29c113..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/4743.md +++ /dev/null @@ -1,85 +0,0 @@ -# Using multiple DBs? - -Tool: OpenDB - -Subcategory: Usage question - -## Conversation - -### donn -In issue #4692: - -> If you use `db = odb.dbDatabase.create()` then you get a db with no Logger that can't issue messages. I suggest you just use the API that works. - -The problem with that is while `odb.dbDatabase.create()` allows multiple DBs to exist simultaneously, the new API does not. We do have a number of scripts that operate on two databases simultaneously. Problem is, now we have three ways of doing this, none of which are ideal: - -1. This fails with "No logger is installed in odb." - - ```python3 - def _2r1w_db_old(db1_in, db2_in, db_out): - db1 = odb.dbDatabase.create() - db1 = odb.read_db(db1, db1_in) - db2 = odb.dbDatabase.create() - db2 = odb.read_db(db2, db2_in) - odb.write_db(db1, db_out) - ``` - -2. This fails with "You can't load a new db file as the db is already populated" - - ```python3 - def _2r1w_db_new(db1_in, db2_in, db_out): - ord_tech1 = Tech() - design1 = Design(ord_tech1) - design1.readDb(db1_in) - - ord_tech2 = Tech() - design2 = Design(ord_tech2) - design2.readDb(db2_in) - - design1.writeDb(db_out) - ``` - -3. This works, but is horrifying and is likely to fail for multiple reasons in the future. - - ```python3 - def _2r1w_db_mix(db1_in, db2_in, db_out): - ord_tech1 = Tech() - design1 = Design(ord_tech1) - design1.readDb(db1_in) - - db2 = odb.dbDatabase.create() - db2.setLogger(design1.getLogger()) - db2 = odb.read_db(db2, db2_in) - - design1.writeDb(db_out) - ``` - -Advice? - -### maliberty -I'm curious what your use case is for multiple dbs. I guess you are only use odb APIs as nothing else in OR is likely to work in such a scenario. - -We could add an API to setup the logger. - -### maliberty -Does this satisfy your needs -``` -from openroad import Design, Tech -import odb - -ord_tech1 = Tech() -design1 = Design(ord_tech1) -design1.readDb('odb/test/data/design.odb') - -db2 = Design.createDetachedDb() -db2 = odb.read_db(db2, 'odb/test/data/design.odb') - -design1.writeDb('db1.odb') -odb.write_db(db2, 'db2.odb') -``` - -### maliberty -Done #4749 - -The odb APIs should be fine. - diff --git a/gh_discussions/Query/4890.md b/gh_discussions/Query/4890.md deleted file mode 100644 index 591cf59082cea773075d777da21945773fb38ea4..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/4890.md +++ /dev/null @@ -1,25 +0,0 @@ -# Defaults for PPL values? - -Tool: Pin Placer - -Subcategory: Parameter defaults - -## Conversation - -### donn -For these flags in PPL: - -* `set_pin_length -hor_length` -* `set_pin_length -ver_length` -* `place_pins -min_distance` - -It isn't super clear from the documentation what the default values are/where they would be obtained from otherwise. Does anyone have any idea? - -### maliberty -@eder-matheus please respond when you can - -### eder-matheus -@donn I created this PR https://github.com/The-OpenROAD-Project/OpenROAD/pull/4891 updating the documentation with this data. In summary, the default length of the pins is the minimum necessary to respect the minimum area of the layer a pin was placed, considering that the width of a pin is the min width of the layer the pin was placed. - -About the min distance, the default is the length of two tracks between each pin. - diff --git a/gh_discussions/Query/5087.md b/gh_discussions/Query/5087.md deleted file mode 100644 index bcb7c6b143f3e5cfe61dc8321d15ea6fc1658f79..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/5087.md +++ /dev/null @@ -1,23 +0,0 @@ -# Add rectangle through odb scripting - -Tool: OpenDB - -Subcategory: Scripting question - -## Conversation - -### OuDret -Hello, - -I was trying to place some rectangles/boxes using odb scripting but I did not manage to make it work. - -Is it even possible? - -### maliberty -What sort of rectange/box are you trying to add? The odb api from db.h is swig'ed to tcl. - -### maliberty -> Which is not exactly what pdn ring do. - -What do you get with a ring? - diff --git a/gh_discussions/Query/5249.md b/gh_discussions/Query/5249.md deleted file mode 100644 index 20952dad06e3de1e472bdd1274dbcd62377cadfd..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/5249.md +++ /dev/null @@ -1,42 +0,0 @@ -# Want to know semantics of blockages - -Tool: Global Routing - -Subcategory: Routing resource reduction - -## Conversation - -### doo3yoon -Hi - -I applied routing blockages before global routing stage using command lines below for the whole design area, - -set_global_routing_region_adjustment [list 0.1 0.1 237.4 140] -layer 2 -adjustment 0.2 -set_global_routing_region_adjustment [list 0.1 0.1 237.4 140] -layer 3 -adjustment 0.2 -set_global_routing_region_adjustment [list 0.1 0.1 237.4 140] -layer 4 -adjustment 0.2 -set_global_routing_region_adjustment [list 0.1 0.1 237.4 140] -layer 5 -adjustment 0.2 - -and compared its routing resource reduction with the one without routing blockage (refer to the table below). - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/102841960/69b52af8-806c-4f18-bb1e-4059ade2d953) - -But, I couldn't find a clear connection between blockage value and resource reduction. -For example, when I reduce 20% for metal2, its derated resource was from 0.89% to 29.75%. - -Could you explain about how the routing blockage affects routing resource reduction? - -Thanks and looking forward to hearing from you, - -Dooseok - - -### maliberty -@eder-matheus please comment - -### eder-matheus -@doo3yoon The resource reduction you see in the run without applying `set_global_routing_region_adjustment` comes from the design obstructions, like PWR/GND nets, instance obstructions, macros, etc. - -The percentage shown in the report does not match your reduction because it operates over integer values, and we always floor the result. So the global router will always be pessimistic with your reduction value, which can lead to a higher reduction percentage. - -You can see that the higher layers have more impact because their pitch values are already high, meaning that the original resources will be smaller when compared to the lower layers. When we floor the resources after applying the reduction for these upper layers, we could end with a more significant reduction than the other layers. - diff --git a/gh_discussions/Query/5451.md b/gh_discussions/Query/5451.md deleted file mode 100644 index 2d0bc8d0cfed675624f2f70cbe847cfc64e5d930..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/5451.md +++ /dev/null @@ -1,21 +0,0 @@ -# OpenRoad db query - -Tool: OpenDB - -Subcategory: Cell statistics report - -## Conversation - -### CathedralsOfSand -How do you dump detailed cell usage statistics from a finished database? - -I have the cell stats from the yosys synth run but want similar data from the timing closed routed db. - -Thanks - -### maliberty -`report_cell_usage` is the simplest - -### maliberty -https://github.com/The-OpenROAD-Project/OpenROAD/pull/5455 is quick stab at this. What do you think of https://github.com/The-OpenROAD-Project/OpenROAD/pull/5455/files#diff-2da4a6ba84e5e60ce2a822063c4acd592ca2c6fc35f81f3d3d966f78ba7e1675 ? - diff --git a/gh_discussions/Query/625.md b/gh_discussions/Query/625.md deleted file mode 100644 index b6b2a923aa6c6008399e3673b44b4340003f6fd9..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/625.md +++ /dev/null @@ -1,157 +0,0 @@ -# Where is PA pattern generation in FlexPA::main in TritonRoute? How to dump out AP info for TA? - -Tool: Detailed Routing - -Subcategory: Usage question - -## Conversation - -### Raynchowkw -Hi, I want to find the step of "pin access pattern generation" in the TritonRoute/src/pa code and dump out the pattern information after pin access analysis. I don't see pin access pattern generation function in FlexPA::main(). Could anyone tell me where is this step? -Is there template or sample of extracting pin access points information for TA? Thanks. - -### maliberty -The calls to init() and prep() do the work of computing the access points. If you just want to dump the result you would do so after those steps finish. You can just look at frInstTerm::getAccessPoints() for the result. - -### maliberty -Btw, what is your high level goal? - -### maliberty -Anything on stdout will be copied to the log file in 5_2_TritonRoute.log. - -Matt - -On Tue, May 18, 2021 at 2:02 PM Raynchowkw ***@***.***> wrote: - -> Hi, I have built the flow locally and made modification to the -> FlexPA_prep.cpp to add the "cout" code provided by @Stephanommg -> in previous reply -> -> and rebuilt only the openroad tool. -> I run 'make' for a sample design, and from the output scripts in terminal, -> I cannot find any information which is assumed to be produced by 'cout'. I -> look through the part from '[INFO DRT-0194] start detail routing ...' to -> '[INFO DRT-0198] complete detail routing', also use "Ctrl+Shift+F" to find -> "layerNum ", but fail to find any aps information. -> Am I supposed to run TritonRoute individually to output the message? -> -> — -> You are receiving this because you commented. -> Reply to this email directly, view it on GitHub -> , -> or unsubscribe -> -> . -> - - -### Raynchowkw -How to interpret the aps info printed by 'cout << bp << "layerNum " << ap->getLayerNum() << "\n";'? -It looks like: ( the first paragraph) -``` -( ( ( ( ( 84550 23940 )layerNum 2 -( 84550 9025072770 23940 )75810layerNum ( ( ( 86450883502 68590 70490 23940 - )239402394023800 )( 23940 )layerNum 23940 )layerNum 272770 )layerNum -( 86450238002layerNum )23940layerNum 23800 )2layerNum - )2 -( ) -( layerNum 70490 23800layerNum 222 -( 90250 - )2 -( 86450 24080 )68590 -layerNum layerNum ( layerNum ( ( 238002275810 23800 -``` -It's not something like (X,Y,Z). -Which part of code should I read to understand this data structure? -How can I know the net_id, pin_id, pin_x, pin_y, pin_layer according to this? -Thanks. - - - -### Raynchowkw -Thanks. - -On Fri, May 28, 2021 at 5:36 PM Stephanommg ***@***.***> -wrote: - -> By container I meant something that contains things. For instance: a -> vector. -> -> Yes this operator. -> -> Learning C++ will surely help you. After that you will be better able to -> understand the code. -> -> I really cant code for you right now, and I think my previous comment -> already answered you last question (at least in part). You will have to use -> the first code to iterate the access points in combination with the last -> code to iterate over the nets. -> -> for each net -> for each instTerm -> get access points like the 1st code -> for each term -> get access points like the 1st code (with differences that it is up to up -> to check) -> -> — -> You are receiving this because you authored the thread. -> Reply to this email directly, view it on GitHub -> , -> or unsubscribe -> -> . -> - - --- -Best, -Raynchow - - -### maliberty -@Raynchowkw the project has limited resources and I think you need to put in more effort to solve your issues before requesting help. Many of the requests don't require in depth knowledge of OpenRoad and are basic software development skills you need to develop. - -### maliberty -You can think of a term as a port of a verilog module; an instance as an instance of a verilog module; and an instTerm as the connection point on the instance reflecting the port of the module instantiated. - -### Raynchowkw -Hi, After working hard on learning C++, I still have some questions. -One that blocks my understanding is `pin.get()` etc. -What's the `.get()` here and where's its definition? I cannot find one in their class def. - -### maliberty -No problem - -On Thu, Jun 10, 2021 at 11:48 AM Raynchowkw ***@***.***> -wrote: - -> You need to iterate over the frNets and then iterate over their -> frInstTerms and frTerms (similar to the for I placed here before). Do this -> after pin access and before DR. You can do this inf FlexDR::main() before -> the searchRepair functions. To get all nets, use -> design_->getTopBlock()->getNets(). -> -> Hi, I want to dump out aps before TA. I check TritonRoute::main. dr is -> later than ta. So I want to dump out at the end of FlexPA::main. Would that -> incur unexpected problems? -> -> — -> You are receiving this because you commented. -> Reply to this email directly, view it on GitHub -> , -> or unsubscribe -> -> . -> - - -### Raynchowkw -After one week of understanding code, I find the logic of assigning one ap to one pin by this [line](https://github.com/The-OpenROAD-Project/OpenROAD/blob/c27d7cea8981bc917deaaa4d8cc83a6f9285c0e7/src/TritonRoute/src/pa/FlexPA_prep.cpp#L1579) in genInstPattern_commit. -The code @Stephanommg wrote to get aps is `for (auto& ap : pin->getPinAccess(inst->getPinAccessIdx())->getAccessPoints())`. I had a hard time understanding what frPinAccess is doing. I just find its uses in the [FlexPA::initPinAccess](https://github.com/The-OpenROAD-Project/OpenROAD/blob/c27d7cea8981bc917deaaa4d8cc83a6f9285c0e7/src/TritonRoute/src/pa/FlexPA_init.cpp#L232) in and [FlexPA::prepPoint](https://github.com/The-OpenROAD-Project/OpenROAD/blob/c27d7cea8981bc917deaaa4d8cc83a6f9285c0e7/src/TritonRoute/src/pa/FlexPA_prep.cpp#L1248) in FlexPA::prepPattern and [revertAccessPoints](https://github.com/The-OpenROAD-Project/OpenROAD/blob/c27d7cea8981bc917deaaa4d8cc83a6f9285c0e7/src/TritonRoute/src/pa/FlexPA_prep.cpp#L1455) and [prepPattern_inst](https://github.com/The-OpenROAD-Project/OpenROAD/blob/c27d7cea8981bc917deaaa4d8cc83a6f9285c0e7/src/TritonRoute/src/pa/FlexPA_prep.cpp#L1816). -It looks like these are before genInstPattern_commit and just for coord manipulation purpose. So I think frPinAccess doesn't filter ap selected for each pin. -So in order to get ap for each pin in each net, can I do loop through net -> instTerms ->getAccessPoints() ? -I am not sure the meaning of "net" and what's relationship between pin and net. Can I understand as this: a net connects some instTerms, each instTerm has some pins, so instTerms' pins are linked to that one net exclusively? Or pins in one instTerm can be linked to -different nets? -Thanks. - diff --git a/gh_discussions/Query/683.md b/gh_discussions/Query/683.md deleted file mode 100644 index 7e1d5416b4567828934b7a917b2f3b411c6b5175..0000000000000000000000000000000000000000 --- a/gh_discussions/Query/683.md +++ /dev/null @@ -1,30 +0,0 @@ -# What's the workflow of developing in submodules? - -Subcategory: Submodule management - -## Conversation - -### Raynchowkw -I git clone --recursive the parent repo "openroad-flow-scripts" so I get all the code including submodules in the local. -And then I use "git remote rename origin upstream" and "git remote add origin to let it point to my repo. (I only create one repo for the openroad-flow-script. I didn't create repo for submodules.) -After I made changes in submodule /tools/openroad/src, I do git `add` and `commit` in the directory of submodule tools/openroad, and then in the parent directory /openroad-flow-scripts, I do `git add tools/openroad`, `commit`, `push`. I can see it does push something to somewhere[![push result](https://i.postimg.cc/jSrTz9Ry/We-Chat-Image-20210526015324.png)](https://postimg.cc/kBwLCT65), but I cannot find it on github.com, on which the directory url points to 404 [![404page](https://i.postimg.cc/FF3DfsHF/404.png)](https://postimg.cc/fkWxpsd1)page. I am wondering where the submodules go when I do the `git remote add origin `. Is there a way to create the submodule repo automatically in my repo? - -### maliberty -It isn't clear in which repo you are runing which steps. Please give a specific set of steps to replay to see your problem. - -I think the simplest is to fork ORFS & OR. - -### maliberty -When the submodule is checked out it will be a specific commit that is checked out not the HEAD. You can just 'it checkout master' and commit your change. Then in ORFS you can update the submodule to point to your new commit. - -### maliberty -In ORFS you should see that the submodule is modified and you git add/commit it as usual. - -### maliberty -yes - -### Raynchowkw -When I want to get the update of submodules, I do `git pull --recurse-submodule`, [![gitpullsubmodulecheckout.png](https://i.postimg.cc/hPpJ5z1G/gitpullsubmodulecheckout.png)](https://postimg.cc/svGDB28F), -but it checkouts the commit id it originally points to. [![submodulepointtocommit.png](https://i.postimg.cc/5tF6yPdH/submodulepointtocommit.png)](https://postimg.cc/Y4MpyzSk). -How to let it point to my OR git master branch? Otherwise, I need to go into that submodule directory to do the `git checkout master` every time. - diff --git a/gh_discussions/Runtime/1164.md b/gh_discussions/Runtime/1164.md deleted file mode 100644 index 2415d587059ccdb2974932362d461d8d78ac9982..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/1164.md +++ /dev/null @@ -1,66 +0,0 @@ -# how to run ICeWall test examples - -Tool: Chip-level Connections - -Subcategory: Crash report - -## Conversation - -### vijayank88 -Hi, - -I am trying to run OpenROAD/src/ICeWall/test examples. Used below command inside openroad and stopped with error - -openroad 1> source soc_bsg_black_parrot_nangate45.tcl -[WARNING ODB-0229] Error: library (NangateOpenCellLibrary.mod) already exists -[WARNING ODB-0229] Error: library (dummy_pads) already exists -[WARNING STA-0053] dummy_pads.lib line 7, library dummy_pads_worst_case already exists. -Segmentation fault (core dumped) - -Anyone can explain how to run this flow and to view DEF file klayout to view my chip level io connection created by ICeWall - -Thanks in advance - - -### maliberty -@Colin-Holehouse @ibrahimkhairy can you help? - -### maliberty -@jjcherry56 the crash is in - -sta::ConcreteInstance::deletePin -sta::ConcreteNetwork::deletePin -sta::ConcreteNetwork::deleteInstance -sta::ConcreteNetwork::deleteTopInstance -sta::ConcreteNetwork::linkNetwork -ord::dbLinkDesign - -reproduce by going to src/ICeWall/test and running -% openroad soc_bsg_black_parrot_nangate45.tcl -[at OR prompt] source soc_bsg_black_parrot_nangate45.tcl - -### vijayank88 -[vijayan@ctpl-hp11 test]$ ../../../build/src/openroad -OpenROAD 1 3a8b060d9026de9b35e4f35ee59157ce9416c3ff -This program is licensed under the BSD-3 license. See the LICENSE file for details. -Components of this program may be licensed under more restrictive licenses which must be honored. -openroad 1> source soc_bsg_black_parrot_nangate45.tcl -[INFO ODB-0222] Reading LEF file: NangateOpenCellLibrary.mod.lef -[INFO ODB-0223] Created 22 technology layers -[INFO ODB-0224] Created 27 technology vias -[INFO ODB-0225] Created 134 library cells -[INFO ODB-0226] Finished LEF file: NangateOpenCellLibrary.mod.lef -[INFO ODB-0222] Reading LEF file: dummy_pads.lef -[INFO ODB-0225] Created 24 library cells -[INFO ODB-0226] Finished LEF file: dummy_pads.lef -[INFO IFP-0001] Added 1885 rows of 13893 sites. -[INFO PAD-0053] Creating padring nets: RETN_10, RETN_11, RETN_12, RETN_13, RETN_14, RETN_15, RETN_16, RETN_17, RETN_18, RETN_19, RETN_20, RETN_0, RETN_1, RETN_2, RETN_3, RETN_4, RETN_5, RETN_6, RETN_7, RETN_8, RETN_9, SNS_10, SNS_11, SNS_12, SNS_13, SNS_14, SNS_15, SNS_16, SNS_0, SNS_17, SNS_1, SNS_18, SNS_2, SNS_19, SNS_20, SNS_3, SNS_4, SNS_5, SNS_6, SNS_7, SNS_8, SNS_9, DVSS_0, DVSS_1, DVDD_0, DVDD_1. -[INFO PAD-0051] Creating padring net: VSS. -[INFO PAD-0051] Creating padring net: VDD. -No differences found. - -Is the above log right? - -### maliberty -"No differences found. " tells you it is right. - diff --git a/gh_discussions/Runtime/2445.md b/gh_discussions/Runtime/2445.md deleted file mode 100644 index 27abba6caaf0c19cb2291bee4af641aea48539be..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/2445.md +++ /dev/null @@ -1,46 +0,0 @@ -# rtl-mp - -Tool: TritonPart - -Subcategory: Error during execution - -## Conversation - -### bittnada -Hello, - -I am trying to do floorplanning with OpenROAD with ISPD benchmark superblue16, but I am struggling with so many problems. -I am quite new to this filed, so my knowledge for this filed is not high enough. -I uploaded .lef, .def. and .v field given by ISPD and tried to do floorplan, but this error line "LEF MASTER ~CELL HAS NO LIBERTY CELL" appeared and does not work at all. -I am glad if anyone has any idea about this error and how to work with this kind of open bench mark. - -Thanks - -### maliberty -I don't see any uploaded files. Based on the message you have a cell called "~CELL" that exists in LEF but for which you have no .lib. - -### bittnada -Thanks to all of you -I followed the order of commands that @QuantamHD recommended and it worked although LEF file seems to have some syntax errors. -Global placement (GPL) worked well, so I am very happy with this result. As @rovinski mentioned, global placement also worked without importing .lib file. Regarding with global placement, I have none of problem. I appreciate to all of you. - -I am also trying to run floorplanning with openroad as I want to follow the paper (https://vlsicad.ucsd.edu/Publications/Conferences/389/c389.pdf), embedded in the floorplan machine for openroad. - -Although the ISPD contest porblem is provided as "floorplan" finished, I want to re-floorplan with openroad and -compare the results between openroad and as it is given. - -I tried the commands as shown below, -``` -read_verilog superblue16.v -read_lef tech.lef -read_lef superblue16.lef -read_lib superblue16_Early.lib -link_design superblue16 -write_def superblue16.def -read_def superblue16.def -floorplan_initialize -partition_design -max_num_inst 1000 -min_num_inst 200 -max_num_macro 1 -min_num_macro 0 -net_threshold 0 -virtual_weight 500 -report_directory . -report_file report -``` -Am I on the right track? - - - diff --git a/gh_discussions/Runtime/2754.md b/gh_discussions/Runtime/2754.md deleted file mode 100644 index 2c65bf171d5108835a898252c619fd114ccebb80..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/2754.md +++ /dev/null @@ -1,187 +0,0 @@ -# How can I find out where the routing congestion is? - -Tool: Global Routing - -Subcategory: Routing congestion - -## Conversation - -### oharboe -Any tips? - -I'm trying a larger version & different version of https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/pull/743 and it fails in global routing. - -``` -[INFO GRT-0101] Running extra iterations to remove overflow. -[WARNING GRT-0227] Reached 20 congestion iterations with less than 15% of reduction between iterations. -[INFO GRT-0197] Via related to pin nodes: 1126254 -[INFO GRT-0198] Via related Steiner nodes: 39 -[INFO GRT-0199] Via filling finished. -[INFO GRT-0111] Final number of vias: 2236520 -[INFO GRT-0112] Final usage 3D: 15578444 -[ERROR GRT-0118] Routing congestion too high. Check the congestion heatmap in the GUI. -Error: global_route.tcl, 19 GRT-0118 -``` - -The most recent .odb file to be written is 4_cts.odb, but when I load it and look at the routing congestion map, I don't see anything suspicious. Such arrays have a lot of routing to do, but the routing is simple conceptually: point to point between the array elements. - -I'm learning a few tricks with OpenROAD-flow-scripts: - -1. read documentation, if you can find it. -2. read the OpenROAD-flow-scripts/flow/*.tcl script for the step. It is normally quite short. From here you can find out what reports are being saved and also what to search for in other examples. - - -Looking at congestion.rpt, it is full of these. There's nothing in that area, just filler cells. Sometimes overflow is as high as 20. - -``` -violation type: Horizontal congestion - srcs: - congestion information: capacity:16 usage:17 overflow:1 - bbox = ( 1544.4, 45.9 ) - ( 1544.94, 46.44) on Layer - -``` - - - -### maliberty -The violations are related to routing congestion so they can occur over fill cells. Do you not see congested areas in the heatmap? I'm not sure what "anything suspicious" means. - -Also you could play with the layer derates in grt. Reducing them makes it more likely you'll get past grt but also more likely you'll have trouble in drt. We set them more conservatively in the PDK. - -### maliberty -Something doesn't make sense. It fails to route due to congestion but you don't see any in the congestion map. If you load the congestion report in the drc viewer you should be able to see where the congestion is. - -### maliberty -Can you show a local image of the area? If you click the underlined heat map you'll get an options dialog. You can investigate on what layers/directions the congestion is happening in. - -### oharboe -I'm going to investigate something else... Could it be that the PDN is overlaying the pins at the top of the macro? - -Here the blue line (from PDN) is not overlaying the pins at the top of the macro. - -![image](https://user-images.githubusercontent.com/2798822/212607947-ac115c6b-dec6-47e2-87f1-17f8da092f63.png) - -The vertical PDN lines go all the way to the top, but the horizontal not all the way to the right edge. That's an assymetry that I find puzzling. - -The screenshot below is the upper right corner of the design I'm tinkering with: - -![image](https://user-images.githubusercontent.com/2798822/212608610-bb1d7d24-7eb3-4d7f-9a1d-6815b7689330.png) - -The routing congestion heat map shows that there's a lot of routing at the top (orange). There's nothing there... - -![image](https://user-images.githubusercontent.com/2798822/212611152-9861946b-337e-43cb-9153-671785c873a8.png) - - - -### oharboe -I scaled down the design (fewer wires) and then I can see gui_route. - -Although there's only horizontal routes between the inner macro's right edge and the top level design's right edge, there's this spagetti just before the input/outputs on the right side... - -No wonder this doesn't work if you scale up the number of wires. - -I wonder what is going on here... - - -![image](https://user-images.githubusercontent.com/2798822/212673682-743d7cf8-fe27-435a-9982-f709a7e6ef42.png) - -zoom in: - - -![image](https://user-images.githubusercontent.com/2798822/212674518-062cec9c-ab11-4eeb-92d1-2902cbd6419a.png) - - - - -``` -set sdc_version 2.0 -create_clock [get_ports clock] -period 4000 -waveform {0 2000} - -set clk_name clock -set clk_port_name clock -set clk_period 250 -set clk_io_pct 0.2 - -set clk_port [get_ports $clk_port_name] - -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] - -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs -set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] - -``` - -### oharboe -@rovinski @maliberty I've polished up a test case https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/pull/764. - -This array is open source and big enough to exhibit the problems, though less pronounced, seen above that will appear as you go from from mock-array-big to a bigger version, yet it will build in a more reasonable amount of time. - -In this pull request, I increase the datapath from 8 to 64 bits, at which point global routing fails: https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/pull/774 - - - - -### maliberty -I looked at https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/pull/764. I see a path like: -![image](https://user-images.githubusercontent.com/761514/212960378-5042926e-b92f-4ea5-8493-1424c25f7294.png) - -The input arrives at 50ps (20% of your 250ps clock period). The capture clock path is at nearly 200ps with 44ps of hold from the liberty: -``` ->>> report_checks -through hold2693/A -path_delay min -format full_clock_expanded -Startpoint: io_insVertical_0_2[4] (input port clocked by clock) -Endpoint: ces_2_7 (rising edge-triggered flip-flop clocked by clock) -Path Group: clock -Path Type: min - - Delay Time Description ---------------------------------------------------------- - 0.00 0.00 clock clock (rise edge) - 0.00 0.00 clock network delay (propagated) - 50.00 50.00 ^ input external delay - 0.00 50.00 ^ io_insVertical_0_2[4] (in) - 10.10 60.10 ^ hold3918/Y (BUFx2_ASAP7_75t_R) - 11.76 71.86 ^ hold2691/Y (BUFx2_ASAP7_75t_R) - 11.77 83.63 ^ hold3919/Y (BUFx2_ASAP7_75t_R) - 11.61 95.24 ^ hold1087/Y (BUFx2_ASAP7_75t_R) - 11.64 106.88 ^ hold2692/Y (BUFx2_ASAP7_75t_R) - 11.81 118.69 ^ hold245/Y (BUFx2_ASAP7_75t_R) - 11.74 130.43 ^ hold2693/Y (BUFx2_ASAP7_75t_R) - 11.65 142.08 ^ hold1088/Y (BUFx2_ASAP7_75t_R) - 11.75 153.83 ^ hold2694/Y (BUFx2_ASAP7_75t_R) - 11.95 165.78 ^ input149/Y (BUFx2_ASAP7_75t_R) - 12.04 177.82 ^ hold2695/Y (BUFx2_ASAP7_75t_R) - 12.02 189.84 ^ hold1089/Y (BUFx2_ASAP7_75t_R) - 12.10 201.94 ^ hold2696/Y (BUFx2_ASAP7_75t_R) - 12.11 214.05 ^ hold246/Y (BUFx2_ASAP7_75t_R) - 12.07 226.12 ^ hold2697/Y (BUFx2_ASAP7_75t_R) - 11.89 238.01 ^ hold1090/Y (BUFx2_ASAP7_75t_R) - 12.17 250.19 ^ hold2698/Y (BUFx2_ASAP7_75t_R) - 0.05 250.24 ^ ces_2_7/io_ins_1[4] (Element) - 250.24 data arrival time - - 0.00 0.00 clock clock (rise edge) - 0.00 0.00 clock source latency - 0.00 0.00 ^ clock (in) - 16.72 16.72 ^ wire1/Y (BUFx12f_ASAP7_75t_R) - 74.94 91.66 ^ clkbuf_0_clock/Y (BUFx4_ASAP7_75t_R) - 51.85 143.51 ^ clkbuf_2_1_0_clock/Y (BUFx4_ASAP7_75t_R) - 44.16 187.67 ^ clkbuf_3_3__f_clock/Y (BUFx4_ASAP7_75t_R) - 8.97 196.64 ^ ces_2_7/clock (Element) - 0.00 196.64 clock reconvergence pessimism - 44.22 240.86 library hold time - 240.86 data required time ---------------------------------------------------------- - 240.86 data required time - -250.24 data arrival time ---------------------------------------------------------- - 9.39 slack (MET) -``` - -So you'll need 200ps of hold buffering to make this pass. BUFx2 is ~12ps so you need a good number to meet your hold constraint. I don't see anything wrong here other than inputs that arrive quite early relative to the macro's requirements. - -The clock path doesn't look unreasonable: -![image](https://user-images.githubusercontent.com/761514/212962157-a2e3bc6e-911d-4243-a648-39f7e10343d2.png) - - -### maliberty -The most forgiving would be to put no i/o timings at all aside from clock. Then only paths internal to the block would be checked. Another option would be to give different min/max timings where they are both forgiving. - diff --git a/gh_discussions/Runtime/2790.md b/gh_discussions/Runtime/2790.md deleted file mode 100644 index a3e6e52230a6a2524453b4e1cfbdcfb41a285a3c..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/2790.md +++ /dev/null @@ -1,45 +0,0 @@ -# Inserting PDN takes a lot of time - -Tool: Power Distribution Network Generator - -Subcategory: Performance issue - -## Conversation - -### oharboe -Is it expected that inserting PDN (last part of make floorplan) should take a lot of time for designs that start to approach 1mm^2 in ASAP7? - -It would be helpful if "make floorplan" was faster, because then it is quicker to iterate on the floorplan, after which the build can normally be left alone without human interaction for longer runs. - -I ran it in the debugger and it looks like a lot of time is spent building this ShapeTree: https://github.com/The-OpenROAD-Project/OpenROAD/blob/b99d7d2c3db8b72a3fc35da9bd6c3a203c3b8306/src/pdn/src/shape.cpp#L637 - -Afterwards, this line seems to almost always return false https://github.com/The-OpenROAD-Project/OpenROAD/blob/b99d7d2c3db8b72a3fc35da9bd6c3a203c3b8306/src/pdn/src/shape.cpp#L640) - -I made a few fleeting vain attempts to rewrite the code, such that the common case, https://github.com/The-OpenROAD-Project/OpenROAD/blob/b99d7d2c3db8b72a3fc35da9bd6c3a203c3b8306/src/pdn/src/shape.cpp#L627, returning false, would not require building the ShapeTree. - - - - -### maliberty -There could be a lot of factors. Are you using the asap7 default pdn? -@gadfort - -### oharboe -Still running, 1 hr 35 minutes... - -``` -01:35:49 /OpenROAD-flow-scripts/tools/install/OpenROAD/bin/openroad -exit -no_init ./scripts/pdn.tcl -metrics ./logs/asap7/doohickey/base/2_6_pdn.json -``` - -### maliberty -In asap7 the m1/m2 stripes introduce a ton of vias. @gadfort could help skip the add_pdn_connect for M1/M2 or would that produce an error. It wouldn't matter much for prototyping whether we have the vias or not. - -### gadfort -@oharboe @maliberty it shouldn't take that long, there has always been some inefficiency when building those obstruction sets and maybe it's a good idea to revisit how that is done and find a better solution that is faster. - -### oharboe -@maliberty @gadfort Example of ```[INFO PDN-0001] Inserting grid: top``` taking at least 12 hours, after which I stopped it. https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/pull/779 - -### oharboe -PDN insertion is MUCH faster than it used to be, but it can still be an issue. - diff --git a/gh_discussions/Runtime/2804.md b/gh_discussions/Runtime/2804.md deleted file mode 100644 index e783a0cccda3b74365f89db9d6eb71fa59b43a46..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/2804.md +++ /dev/null @@ -1,28 +0,0 @@ -# Problems with detailed routing violations with an array of macros - -Tool: Detailed Routing - -Subcategory: Routing violations - -## Conversation - -### oharboe -In this pull request, I've added a design that has a problem with detailed routing. I *suspect* there are some alignment requirements for macro positioning, but I don't understand what those requirements are. - -Any tips? - -https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/pull/782 - - -![image](https://user-images.githubusercontent.com/2798822/213920736-10b8a7f8-0b71-466a-9357-178dbb9b52b7.png) - - -### maliberty -My first guess would be to look at the macro pins and whether they are on grid - -### khaledhasanzami -Same issue, any solution reached yet? - -### oharboe -We're not seeing these problems currently with latest master - diff --git a/gh_discussions/Runtime/2821.md b/gh_discussions/Runtime/2821.md deleted file mode 100644 index cdb2ba9e1604ab8115461989137cee1dec95f1c3..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/2821.md +++ /dev/null @@ -1,77 +0,0 @@ -# Slow detailed routing convergence - -Tool: Detailed Routing - -Subcategory: Performance issue - -## Conversation - -### oharboe -I was curious what was difficult about detailed routing for a design, so I stopped detailed routing after 4 iterations, using https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/pull/791, then looked at 5_route_drc.rpt. - -Here it seems like there is a lot of congestion at the top of macros because the power strip is running inside the halo (?) of the macro. - -![image](https://user-images.githubusercontent.com/2798822/215082762-af8767ce-7118-48cb-a7a3-c9913369defc.png) - -Howevever here is a macro, just like the one above where detailed routing doesn't seem to have a problem dealing with this issue: - -![image](https://user-images.githubusercontent.com/2798822/215083592-634bcdef-9a15-45c7-ad5b-b34820f0a94e.png) - - -Perhaps nothing is wrong here and it just takes a while to do detailed routing. - -Is there anything to learn or that I can do different here? - -### maliberty -How many iterations does it take to complete? In general drt is the slowest step of the flow but it also looks like something is going on here. - -In the lower picture the wires appear to go straight in on m5 but in the upper the go up to a higher layer and then try to drop down (which is blocked by the strap). I'm not clear why they can't go straight in from the image. Can you tell? - -### oharboe -I can see the same problem on https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow/designs/asap7/mock-array-big - - -![image](https://user-images.githubusercontent.com/2798822/215114565-abeebeab-8247-4fb0-81eb-8259fbad3390.png) - - -Zooming in, we can see that different metal is being used: - -![image](https://user-images.githubusercontent.com/2798822/215114709-80ae1615-95c6-4bb3-bfaa-a25c3bc339b9.png) - - -To reproduce the image above, first build, but abort after 5 iterations in detailed routing, then load the 5_route_drc.rpt and zoom in: - -``` -make DESIGN_CONFIG=designs/asap7/mock-array-big/Element/config.mk generate_abstract -make DESIGN_CONFIG=designs/asap7/mock-array-big/config.mk DETAILED_ROUTE_ARGS=\"-bottom_routing_layer M2 -top_routing_layer M7 -save_guide_updates -verbose 1 -droute_end_iter 5\" -make DESIGN_CONFIG=designs/asap7/mock-array-big/config.mk -``` - - - - - - - -### maliberty -@osamahammad21 I think looking at this issue in the context of asap7/mock-array-big fits with your other drt performance work. - -### maliberty -Your pins are off the routing grid: -![image](https://user-images.githubusercontent.com/761514/215116042-68838f95-3670-47af-8cc8-e03d6748a470.png) - -which I guess is why the router is gyrating to hit them. - -### maliberty -@osamahammad21 with the PRs from this morning this case now finishes with 0 drvs. However it reaches 2 drvs by the end of iter 4 but takes until iter 13 to reach zero. At the end of iter5 I see two cut spacing violations. They both look easy to fix, eg -![image](https://user-images.githubusercontent.com/761514/216147952-499d6ec6-11d2-4d60-b8e7-27cdf28104ef.png) - -you should readily move the via to the right by one track. I guess this is a costing issue. - - -### antonblanchard -I missed this because it was hiding in discussions. I have noticed various issues with via spacing in drt, eg https://github.com/The-OpenROAD-Project/OpenROAD/issues/2827 and https://github.com/The-OpenROAD-Project/OpenROAD/pull/2844, so likely issues in both route cost and GC (drc). - -### oharboe -Near as I know all of these issues are resolved on master. - diff --git a/gh_discussions/Runtime/2870.md b/gh_discussions/Runtime/2870.md deleted file mode 100644 index 562622b46733ff8054e479ef73c15dbe014bf15e..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/2870.md +++ /dev/null @@ -1,45 +0,0 @@ -# Question about straight wire routing between macros - -Tool: Global Routing - -Subcategory: Routing problem - -## Conversation - -### oharboe -Below are two macros next to eachother where I have mirrored the pins, so the connections are nice and horizontal. - -The pins are on ASAP7 M4, but the route is on M2. - -Looking at the image, I'm curious as to why M4 wasn't just used in a straight line across? Why go via M2? - -The reason I'm asking about this is that my design does detailed routing quickly when I scale it down, but as I scale up, add more macros and a wider data path, it seems like detailed routing has to spend more time(ca. 20x longer) getting signals from M2, to M4 and back to M2 to do the routing between macros. I believe there is non-linear increase(with datapath width) in complexity with getting signals from M4 to M2 and back to M2. - -![image](https://user-images.githubusercontent.com/2798822/217489650-65aa3930-5241-4c6f-affe-adc68a99a9be.png) - - -### maliberty -does this happen on the mock array? - -### maliberty -If you select one of the nets, in the inspector there is an option to show the route guide. It would be interesting to see what the guide for one of these nets looks like. - -### maliberty -The global router prefers to put wires on lower layers, which is a good strategy for standard cell connections. It isn't so good here. - -@eder-matheus I think we should update the 3d embedding in grt to handle the case where the pins being connected are all at layer N or above to avoid layers below N if possible. Would you take care of this or work with Luis or Arthur to do so. - -### eder-matheus -@oharboe Could you try this branch: https://github.com/eder-matheus/OpenROAD/tree/grt_upper_layer_nets? - -### maliberty -@eder-matheus he does not have access to the private repo. Please sync it to public in a PR. - -### maliberty -If you had an obs that you couldn't go over or around then it could be an issue. However it is similar to the clock net constraints we already have that are similar. Probably we would need to introduce a costing scheme to allow out of range layers to be used in extreme cases but that seems like a separate enhancement. - -The motivating case is simply two m4 pins that have an easy planar connection but we drop down to m2 for no good reason (the router prefers lower layers on the erroneous assumption that pins are on the lower layer). - -### oharboe -Master is MUCH better with this now. If the route is not straight, there's generally a reason, like powergrid in the way, buffers added at edge of design before pins, or something. - diff --git a/gh_discussions/Runtime/2880.md b/gh_discussions/Runtime/2880.md deleted file mode 100644 index 77d815e978cb7243ec0a2f1144ffe71a78d66fec..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/2880.md +++ /dev/null @@ -1,26 +0,0 @@ -# estimate_parasitics -global_routing on a post-global_route design loaded via read_db - -Tool: Parasitics Extraction - -Subcategory: Global routing error - -## Conversation - -### nayiri-k -Is it possible to run `estimate_parasitics -global_routing` on a post-global_route design that's been loaded via the `read_db` command? As in, `global_route` has been run on the design before it was saved with `write_db`, but `global_route` has not been run in this current OpenROAD session. I keep getting this error: - -``` ->>> read_db post_global_route ->>> estimate_parasitics -global_routing -[ERROR RSZ-0005] Run global_route before estimating parasitics for global routing. -``` - -### maliberty -@eder-matheus I thought this was possible. Please comment - -### maliberty -Are you using a very old version of OR for this? The guides should be saved in the db. - -### maliberty -OR improves a lot over time so it is a good practice to test with a current version when you find a problem. - diff --git a/gh_discussions/Runtime/2888.md b/gh_discussions/Runtime/2888.md deleted file mode 100644 index 320c508b649c97d1aeee96d48da7ab50dd21908f..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/2888.md +++ /dev/null @@ -1,26 +0,0 @@ -# Using deltaDebug.py to whittle down detailed routing example - -Tool: Detailed Routing - -Subcategory: Detailed routing issue - -## Conversation - -### oharboe -I have some violations that detailed routing isn't able to deal with, that I really think it should be able to deal with. - -Normally, deltaDebug.py needs an error message to look for to do it's bisection. - -However, a detailed route can succeed after 64 iterations, even if all violations are not sorted out, so there's no error message for deltaDebug.py to use for it's bisection. - -Tips? - -### maliberty -Can you use --use_stdout & --error_string to check the final drcs? - -### maliberty -You could make a temporary change to scripts/detail_route.tcl to call detailed_route_num_drvs and issue an error message if >0. Then you could delta on that. - -### oharboe -Various bugs have been fixed and improvements made to deltaDebug.py since this post. - diff --git a/gh_discussions/Runtime/2889.md b/gh_discussions/Runtime/2889.md deleted file mode 100644 index 67592c5611e906614a6179e5407374f7f5d8443c..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/2889.md +++ /dev/null @@ -1,28 +0,0 @@ -# [INFO GRT-0101] Running extra iterations to remove overflow - taking a long time - -Tool: Global Routing - -Subcategory: Global routing issue - -## Conversation - -### oharboe -What does this step actually do? - -Any hints on how to figure out what is going on here, what to look at? - -When I zoom in on the design, I see an ocean of thinly spread fiddlybits: - -![image](https://user-images.githubusercontent.com/2798822/218471305-7312e5f8-afbf-454d-9dbd-87a75d5197e5.png) - - -### rovinski -GRT is the global router. It means your design is very dense (at least within some areas). It is attempting to assign nets to routing tracks, but there are too many nets within an area (overflow) so it is trying to reroute nets to avoid this. - -GRT runs for a fixed number of iterations before giving up and erroring if it can't resolve the overflow. - -The best first thing to check is the global routing heatmap to see congestion hotspots. In your case, it is likely that the density is simply too high and you need to reduce the placement density %. - -### maliberty -You should also check how many buffers are being inserted as it possible that can cause extra congestion if you have very bad timing. - diff --git a/gh_discussions/Runtime/2925.md b/gh_discussions/Runtime/2925.md deleted file mode 100644 index 3358c3960a394851e374387189586af9df277060..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/2925.md +++ /dev/null @@ -1,21 +0,0 @@ -# [ERROR GRT-0076] Net foo.bar\[13\] not properly covered. - -Tool: Global Routing - -Subcategory: Error message clarification - -## Conversation - -### oharboe -What does this error message mean? - -### maliberty -@eder-matheus please respond - -### eder-matheus -@oharboe That means the guides don't cover at least one pin of this net. I will update this error message to clarify what pin is not covered. -Could you share what commit you are using in this run? This error should not be happening at all and could be a side effect of an update I've made. - -### oharboe -I don't recall the details, but this was fixed on master. - diff --git a/gh_discussions/Runtime/3014.md b/gh_discussions/Runtime/3014.md deleted file mode 100644 index c1553f3d7ac18cb041337f2266406a938aed1daa..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/3014.md +++ /dev/null @@ -1,35 +0,0 @@ -# Hold wns resulting infinite - -Tool: OpenSTA - -Subcategory: Timing analysis issue - -## Conversation - -### khaledhasanzami -I was running the riscv model with default setup. When I was trying to find wns for hold after the full run (or in cts, route). It is returning as INF. - -Command: -``` -report_worst_slack -min -``` -Returns `worst slack INF` - -**pdk:** asap7 -**design:** riscv32i - -Any idea why is that and how to solve it? - -### maliberty -In which PDK? How did you load the design? Please give specific steps to reproduce the issue. - -### maliberty -I guess you meant ```make gui_6_final.odb``` without the 'e'. I get: - -``` ->>> report_worst_slack -min -worst slack 40.29 -``` - -What commit id are you using for OR & ORFS? This would have worked better as an issue with the required info. - diff --git a/gh_discussions/Runtime/3044.md b/gh_discussions/Runtime/3044.md deleted file mode 100644 index 416d6f64472199c319f2b3887458657d72a698a3..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/3044.md +++ /dev/null @@ -1,31 +0,0 @@ -# Custom Macro placement detailed route issue: Maze Route cannot find path of net - -Tool: Detailed Routing - -Subcategory: Detailed routing failure - -## Conversation - -### khaledhasanzami -I am using a custom macro placement script. Changing the macro position from default to any other formation causing error in detailed routing. - -`[ERROR DRT-0255] Maze Route cannot find path of net (some net) in worker of routeBox (34000 75000) (41000 45000)` - -Is it an algorithm error, any idea? - - -### vijayank88 -Is automatic macro placement creating that error? - -### maliberty -This is a problem in detailed routing that would require a test case to investigate. Can you provide one? - -### maliberty -I don't expect this error from the router even with a bad macro placement. - -### msingh9 -How do you do custom macro placement? - -### maliberty -It would be great to have a test case for this problem as is so we can fix it in addition to any workarounds in placement to avoid it. - diff --git a/gh_discussions/Runtime/3073.md b/gh_discussions/Runtime/3073.md deleted file mode 100644 index 9c8ae7566abc475881f62798506a3c135375a508..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/3073.md +++ /dev/null @@ -1,21 +0,0 @@ -# repair_design hanging - -Tool: Detailed Routing - -Subcategory: Hanging issue - -## Conversation - -### msingh9 -I have "repair_design" to repair slew and cap, but this has been running for long time with no output. I think it is hanging. My design is not that big. I think it will be useful to get some sense of how much work has been completed, like work progress from these functions. Maybe I should file this a enhancement request? Is there a way to print some message while it is working? - -### maliberty -You could file it as an enhancement request or try to tackle it yourself and file a PR. - -### vijayank88 -@msingh9 -Are you using standalone OpenROAD or with OpenROAD-flow-scripts? - -### maliberty -How large is your design? - diff --git a/gh_discussions/Runtime/3129.md b/gh_discussions/Runtime/3129.md deleted file mode 100644 index 3c1432b3290c8cfba2110c387fb3a2ab985937c7..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/3129.md +++ /dev/null @@ -1,133 +0,0 @@ -# [INFO GPL-0075] Routability numCall: 1 inflationIterCnt: 1 bloatIterCnt: 0 - -Tool: Global Routing - -Subcategory: Stuck in routine - -## Conversation - -### oharboe -So I thought my run was almost finished, it went fairly quickly for a while, but then it got stuck in "Routeability" below. - -5 minutes until it got to the GPL-0075 progress message, then stuck there for at least 30 minutes. - -What does this mean and what can I do about it? - -The floorplan in my case looks quite reasonable and generous. - -https://github.com/The-OpenROAD-Project/OpenROAD/blob/580bd35a8b17f0ea7ff8afafb6cf6d23b757063e/src/gpl/src/routeBase.cpp#L557 - -``` -[NesterovSolve] Iter: 370 overflow: 0.254754 HPWL: 19171375971 -[NesterovSolve] Iter: 380 overflow: 0.250836 HPWL: 18915207500 -[NesterovSolve] Iter: 390 overflow: 0.225598 HPWL: 18784146027 -[NesterovSolve] Iter: 400 overflow: 0.201047 HPWL: 18784861983 -[INFO GPL-0075] Routability numCall: 1 inflationIterCnt: 1 bloatIterCnt: 0 -``` - - -### oharboe -A little bit of suspend/resume profiling using latest OpenROAD and release build... - -Hmmm... curious. I don't think this is a performance problem, but there were a lot of exceptions thrown, so I had to turn off breakpoints on exceptions. - -``` -__cxa_throw (@__cxa_throw:3) - -sta::DmpAlg::findDriverParams(double) (.cold) (@sta::DmpAlg::findDriverParams(double) (.cold):14) -sta::DmpPi::gateDelaySlew(double&, double&) (.cold) (@sta::DmpPi::gateDelaySlew(double&, double&) (.cold):50) -sta::DmpCeffDelayCalc::gateDelay(sta::LibertyCell const*, sta::TimingArc const*, float const&, float, sta::Parasitic const*, float, sta::Pvt const*, sta::DcalcAnalysisPt const*, float&, float&) (@sta::DmpCeffDelayCalc::gateDelay(sta::LibertyCell const*, sta::TimingArc const*, float const&, float, sta::Parasitic const*, float, sta::Pvt const*, sta::DcalcAnalysisPt const*, float&, float&):88) -sta::GraphDelayCalc1::findArcDelay(sta::LibertyCell*, sta::Pin const*, sta::Vertex*, sta::MultiDrvrNet*, sta::TimingArc*, sta::Parasitic*, float, sta::Vertex*, sta::Edge*, sta::Pvt const*, sta::DcalcAnalysisPt const*, sta::ArcDelayCalc*) (@sta::GraphDelayCalc1::findArcDelay(sta::LibertyCell*, sta::Pin const*, sta::Vertex*, sta::MultiDrvrNet*, sta::TimingArc*, sta::Parasitic*, float, sta::Vertex*, sta::Edge*, sta::Pvt const*, sta::DcalcAnalysisPt const*, sta::ArcDelayCalc*):112) -sta::GraphDelayCalc1::findDriverEdgeDelays(sta::LibertyCell*, sta::Instance*, sta::Pin const*, sta::Vertex*, sta::MultiDrvrNet*, sta::Edge*, sta::ArcDelayCalc*) (@sta::GraphDelayCalc1::findDriverEdgeDelays(sta::LibertyCell*, sta::Instance*, sta::Pin const*, sta::Vertex*, sta::MultiDrvrNet*, sta::Edge*, sta::ArcDelayCalc*):105) -sta::GraphDelayCalc1::findDriverDelays1(sta::Vertex*, bool, sta::MultiDrvrNet*, sta::ArcDelayCalc*) (@sta::GraphDelayCalc1::findDriverDelays1(sta::Vertex*, bool, sta::MultiDrvrNet*, sta::ArcDelayCalc*):108) -sta::GraphDelayCalc1::findDriverDelays(sta::Vertex*, sta::ArcDelayCalc*) (@sta::GraphDelayCalc1::findDriverDelays(sta::Vertex*, sta::ArcDelayCalc*):63) -sta::FindVertexDelays::visit(sta::Vertex*) (@sta::FindVertexDelays::visit(sta::Vertex*):74) -sta::BfsIterator::visit(int, sta::VertexVisitor*) (@sta::BfsIterator::visit(int, sta::VertexVisitor*):71) -sta::GraphDelayCalc1::findDelays(int) (@sta::GraphDelayCalc1::findDelays(int):47) -sta::Sta::checkSlewLimitPreamble() (@sta::Sta::checkSlewLimitPreamble():82) -rsz::RepairDesign::repairDesign(double, double, double, int&, int&, int&, int&, int&) (@rsz::RepairDesign::repairDesign(double, double, double, int&, int&, int&, int&, int&):65) -rsz::Resizer::findResizeSlacks() (@rsz::Resizer::findResizeSlacks():24) -gpl::TimingBase::updateGNetWeights(float) (@gpl::TimingBase::updateGNetWeights(float):18) -gpl::NesterovPlace::doNesterovPlace(int) (@gpl::NesterovPlace::doNesterovPlace(int):1262) -_wrap_replace_nesterov_place_cmd (@_wrap_replace_nesterov_place_cmd:20) -TclNRRunCallbacks (@TclNRRunCallbacks:37) -___lldb_unnamed_symbol1504 (@___lldb_unnamed_symbol1504:315) -Tcl_EvalEx (@Tcl_EvalEx:9) -``` - -Ooops.... from within the debugger(attaching) to the release build, I ran into an recursive loop below and a SEGFAULT. - -Curiously, this infinite stack recursion does not appear with the debug build, which makes for an interesting debug exercise... - -``` -rsz::RepairDesign::repairNetJunc(std::shared_ptr, int, int&, sta::Vector&) (@rsz::RepairDesign::repairNetJunc(std::shared_ptr, int, int&, sta::Vector&):16) -rsz::RepairDesign::repairNet(std::shared_ptr, int, int&, sta::Vector&) (@rsz::RepairDesign::repairNet(std::shared_ptr, int, int&, sta::Vector&):82) -[deleted 100s if not 1000s of these] -(@rsz::RepairDesign::repairNet(std::shared_ptr, sta::Pin const*, float, int, sta::Corner const*):29) -rsz::RepairDesign::repairNet(sta::Net*, sta::Pin const*, sta::Vertex*, bool, bool, bool, int, bool, int&, int&, int&, int&, int&) (@rsz::RepairDesign::repairNet(sta::Net*, sta::Pin const*, sta::Vertex*, bool, bool, bool, int, bool, int&, int&, int&, int&, int&):356) -rsz::RepairDesign::repairDesign(double, double, double, int&, int&, int&, int&, int&) (@rsz::RepairDesign::repairDesign(double, double, double, int&, int&, int&, int&, int&):195) -rsz::Resizer::findResizeSlacks() (@rsz::Resizer::findResizeSlacks():24) -gpl::TimingBase::updateGNetWeights(float) (@gpl::TimingBase::updateGNetWeights(float):18) -gpl::NesterovPlace::doNesterovPlace(int) (@gpl::NesterovPlace::doNesterovPlace(int):1262) -_wrap_replace_nesterov_place_cmd (@_wrap_replace_nesterov_place_cmd:20) -TclNRRunCallbacks (@TclNRRunCallbacks:37) -___lldb_unnamed_symbol1504 (@___lldb_unnamed_symbol1504:315) -Tcl_EvalEx (@Tcl_EvalEx:9) -Tcl_Eval (@Tcl_Eval:11) -sta::sourceTclFile(char const*, bool, bool, Tcl_Interp*) (@sta::sourceTclFile(char const*, bool, bool, Tcl_Interp*):31) -ord::tclAppInit(Tcl_Interp*) (@ord::tclAppInit(Tcl_Interp*):128) -Tcl_MainEx (@Tcl_MainEx:111) -main (@main:742) -__libc_start_call_main (@__libc_start_call_main:29) -__libc_start_main_impl (@__libc_start_main@@GLIBC_2.34:43) -_start (@_start:15) -``` - - - - -### oharboe -Letting it run for a while, debug is MUCH slower than release, I see when I suspend in the debugger. There are 200000 nets to process in gen_brk_RSMT(), coeffADJ() is going through double loops for a total of 10000000 iterations... - -![image](https://user-images.githubusercontent.com/2798822/229814542-0e59488f-6f61-46ca-9219-fe4cea5fb085.png) - - -``` -grt::FastRouteCore::getEdgeCapacity(grt::FrNet*, int, int, grt::EdgeDirection) (/home/oyvind/ascenium/OpenROAD-flow-scripts/tools/OpenROAD/src/grt/src/fastroute/src/FastRoute.cpp:592) -grt::FastRouteCore::coeffADJ(int) (/home/oyvind/ascenium/OpenROAD-flow-scripts/tools/OpenROAD/src/grt/src/fastroute/src/RSMT.cpp:616) -grt::FastRouteCore::gen_brk_RSMT(bool, bool, bool, bool, bool) (/home/oyvind/ascenium/OpenROAD-flow-scripts/tools/OpenROAD/src/grt/src/fastroute/src/RSMT.cpp:662) -grt::FastRouteCore::run() (/home/oyvind/ascenium/OpenROAD-flow-scripts/tools/OpenROAD/src/grt/src/fastroute/src/FastRoute.cpp:766) -grt::GlobalRouter::findRouting(std::vector>&, int, int) (/home/oyvind/ascenium/OpenROAD-flow-scripts/tools/OpenROAD/src/grt/src/GlobalRouter.cpp:397) -grt::GlobalRouter::globalRoute(bool) (/home/oyvind/ascenium/OpenROAD-flow-scripts/tools/OpenROAD/src/grt/src/GlobalRouter.cpp:285) -gpl::RouteBase::getGlobalRouterResult() (/home/oyvind/ascenium/OpenROAD-flow-scripts/tools/OpenROAD/src/gpl/src/routeBase.cpp:378) -gpl::RouteBase::routability() (/home/oyvind/ascenium/OpenROAD-flow-scripts/tools/OpenROAD/src/gpl/src/routeBase.cpp:566) -gpl::NesterovPlace::doNesterovPlace(int) (/home/oyvind/ascenium/OpenROAD-flow-scripts/tools/OpenROAD/src/gpl/src/nesterovPlace.cpp:699) -gpl::Replace::doNesterovPlace(int) (/home/oyvind/ascenium/OpenROAD-flow-scripts/tools/OpenROAD/src/gpl/src/replace.cpp:343) -replace_nesterov_place_cmd() (/home/oyvind/ascenium/OpenROAD-flow-scripts/tools/OpenROAD/build/src/gpl/CMakeFiles/gpl.dir/replaceTCL_wrap.cxx:1740) -::_wrap_replace_nesterov_place_cmd(ClientData, Tcl_Interp *, int, Tcl_Obj *const *) (/home/oyvind/ascenium/OpenROAD-flow-scripts/tools/OpenROAD/build/src/gpl/CMakeFiles/gpl.dir/replaceTCL_wrap.cxx:2190) -TclNRRunCallbacks (@TclNRRunCallbacks:37) -___lldb_unnamed_symbol1504 (@___lldb_unnamed_symbol1504:315) -Tcl_EvalEx (@Tcl_EvalEx:9) -Tcl_Eval (@Tcl_Eval:11) -sta::sourceTclFile(char const*, bool, bool, Tcl_Interp*) (/home/oyvind/ascenium/OpenROAD-flow-scripts/tools/OpenROAD/src/sta/app/StaMain.cc:95) -::tclAppInit(int &, char **, const char *, Tcl_Interp *) (/home/oyvind/ascenium/OpenROAD-flow-scripts/tools/OpenROAD/src/Main.cc:412) -ord::tclAppInit(Tcl_Interp*) (/home/oyvind/ascenium/OpenROAD-flow-scripts/tools/OpenROAD/src/Main.cc:440) -Tcl_MainEx (@Tcl_MainEx:111) -``` - -![image](https://user-images.githubusercontent.com/2798822/229812113-27d8013b-9fbc-4727-93ee-18fed95d3702.png) - - - -### maliberty -You could try disabling each of these in turn to localize the cause -``` -if {$::env(GPL_ROUTABILITY_DRIVEN)} { - append global_placement_args " -routability_driven" -} -if {$::env(GPL_TIMING_DRIVEN)} { - append global_placement_args " -timing_driven" -} -``` -The stacks in rsz/sta are related to timing_driven. If you see a stack in grt that is related to routability_driven. - diff --git a/gh_discussions/Runtime/3208.md b/gh_discussions/Runtime/3208.md deleted file mode 100644 index ae435c04574b1e26198a4a4275894f8e665ff7de..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/3208.md +++ /dev/null @@ -1,75 +0,0 @@ -# About the runtime of archived TritonRoute and TritonRoute in OpenROAD - -Tool: Detailed Routing - -Subcategory: Performance degradation - -## Conversation - -### gilgamsh -I have tried both of them and running the same ispd19 benchmark. I have noticed that the runtime of TritonRoute in OpenROAD is quite larger than that in archived TritonRoute. -The specific data is -In ispd19_testcase1 , with single thread - TritonRoute in OpenROAD : Elapsed Time: 643.091s - archived TritonRoute. :Elapsed Time: 236.032s - -I have noticed that, in TritonRoute in OpenROAD ,the pin analysis time and design rule checking time increase dramatically. -pin analysis time in OpenROAD, about 300s, pin analysis time in archived TritonRoute, about 10s. -Is there a normal situation? Maybe there is something wrong about my scripts. - -I use the openroad scripts like below -``` -read_lef ../benchmarks//ispd2019/ispd19_test1/ispd19_test1.input.lef -read_def ../benchmarks//ispd2019/ispd19_test1/ispd19_test1.input.def -read_guides ../benchmarks//ispd2019/ispd19_test1/ispd19_test1.guide -detailed_route -write_def ispd19_test1.solution.def -exit -``` - - - - -### gilgamsh -another question, If i want to learn the code of `TritonRoute-WXL: The Open Source Router with Integrated DRC Engine`. Can i use the archived TritonRoute, thinking it implemented the functions mentioned in this paper(not including the gr)? - -### maliberty -Have you enabled a similar number of threads in both runs? In OR use ```set_thread_count ``` - -The archived version should match the paper but any further improvements will not be present. - -### maliberty -That should be fine. Are you using a similar number of threads in standalone TR? - -### antonblanchard -Are you running a recent version of OpenROAD with the following fix: https://github.com/The-OpenROAD-Project/OpenROAD/commit/0cf19963d358347bcf06a2cd803ea883f8c46f27 - -That issue isn't in the original TritonRoute source, and can cause significantly more runtime in the pin access code. - -### antonblanchard -@vijayank88 did you mean to close this? I just checked, and we are spending significantly more time in genInstRowPattern vs TritonRoute. - -### antonblanchard -Most of the problem appears to be 5fada4c44b2d4aba09185eb1217f928645c32c4b. Start up time for ispd19_test1 goes from 17 seconds to 280 seconds. I haven't got far enough to understand if all that overhead is required. FYI @maliberty @osamahammad21 - - -### maliberty -Its not obvious to me how that change triggers the issue but its @osamahammad21 change so he might have an idea. - -### antonblanchard -I'm not sure why, but the problem is caused by filtering out other instances when generating our preferred access points: - -``` -- hasVio = !genPatterns_gc({prevInst, currInst}, objs, Edge); -+ // hasVio = !genPatterns_gc({prevInst, currInst}, objs, Edge); -+ hasVio = !genPatterns_gc({}, objs, Edge); -``` - -I would have expected this to take less time, unless the act of filtering out other instances is taking lots of time. - -### oharboe -@gilgamsh It would be interesting to see a profile of both cases to see where the difference in time is. That should tell us something of the nature of the difference to corroborate the suspicions on what differences in code that can cause this. - -### maliberty -Note that a fair number of enhancements and bug fixes have gone into the OR version. It is possible you are not observing equivalent results. - diff --git a/gh_discussions/Runtime/3216.md b/gh_discussions/Runtime/3216.md deleted file mode 100644 index 728c025e18b18ebb46b0c3a33b8b5a1d2ce61ff6..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/3216.md +++ /dev/null @@ -1,42 +0,0 @@ -# DRC errors in detailed routing - "Metal spacing violation" - -Tool: Detailed Routing - -Subcategory: DRC violation - -## Conversation - -### oharboe -I think this is happening because two macros that need straight vertical wires between them don't have IO pins lined up and then the wires between the macros are criss-crossing. - - -What is the difference and purpose of `MACRO_PLACE_HALO` vs `MACRO_PLACE_CHANNEL` and where do I use them, in the macro or where I'm using the macro from? - - -Some thoughts on what I might do: - -- I could modify the halo macro to have a big enough "halo" (black area) where the wires can move horizontally to line up better with their destination pin in the other macro. -- I could fix the io pin locations and floorplan so the router is able to use straight vertical wires instead of crisscrossing between two macros. This would reduce the need for a big halo. - -![image](https://user-images.githubusercontent.com/2798822/233312554-d99551bf-439f-47f9-85da-21b601517284.png) - - - -### vijayank88 -@oharboe -Variable description found here: https://openroad-flow-scripts.readthedocs.io/en/latest/user/FlowVariables.html#floorplan - -### maliberty -Note that mpl distinguished halo vs channel but mpl2 just uses halo. The distinction is that a channel is the space between two macros but the halo applies on all sides of the macro. - -I can't tell much from the picture. - -### maliberty -The setting are for x & y separately. Usually they are the same - -### maliberty -Imagine channel=10 and halo=5. Then macros must be 10 apart but standard cells must be 5 away from a macro. It is moot with mpl2. - -### oharboe -Updated docs in pull request based on the above: https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/pull/1007 - diff --git a/gh_discussions/Runtime/3346.md b/gh_discussions/Runtime/3346.md deleted file mode 100644 index f5b6fc13454dbd28408b810f79b89410c01591d2..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/3346.md +++ /dev/null @@ -1,35 +0,0 @@ -# Can I ask global route to fail early? - -Tool: Global Routing - -Subcategory: Global routing timeout - -## Conversation - -### oharboe -@nerriav Global routing takes very little time for the project I am working on. However, when I make changes, these sometimes can make global routing impossible and I have to tweak my change. - -When global routing fails, it doesnt fail quickly, it just runs "forever"(hours compared to minutes) before it ultimately fails. - -Can I adjust a setting such that global route fails quickly so that I dont waste server build resources and I can quickly load the routing congestion report in the DRC viewer to drill down to the problem? - -### rovinski -In OR you can use the `-congestion_interations` argument which translates to `GLOBAL_ROUTE_ARGS=" -congestion_iterations X "` in ORFS. X is a positive integer. The default is 100. - -### oharboe -Syntax subtleties... `export GLOBAL_ROUTE_ARGS="-congestion_iterations 10 -verbose"`, failed with `[ERROR STA-0402] global_route -congestion_iterations 10 -verbose is not a known keyword or flag.` - -`export GLOBAL_ROUTE_ARGS=-congestion_iterations 10 -verbose` worked... - -It is still stuck on: - -``` -[INFO GRT-0101] Running extra iterations to remove overflow. -``` - -With `export GLOBAL_ROUTE_ARGS=-congestion_iterations 2 -verbose` it fails after 2:30 minutes. - -I'll see how high I can make it until it "runs forever". If it fails after 10 minutes, then I have something I can try out. If there is nothing wrong, I would expect it to complete in ca. 3 minutes. - -I'm curious if 10 iterations is enough for all the designs under test... https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/pull/1076 - diff --git a/gh_discussions/Runtime/3353.md b/gh_discussions/Runtime/3353.md deleted file mode 100644 index ffa50e1d7acaef31214187f68dd94b2e24a88014..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/3353.md +++ /dev/null @@ -1,80 +0,0 @@ -# Build times for our design - -Tool: Detailed Routing - -Subcategory: Performance analysis - -## Conversation - -### oharboe -There is no question here, just a demonstration of the use of the build time summary for a design that has one top level macro and 5 macros at the top level. What is being built here are mock abstracts for the macros at the top level as we are only interested in regression testing the top level on our build servers. - -The top level is the slowest in detailed routing and we have 5 macros at the top level. - -We are not currently building the macros at the top level in parallel, though we intend to, but it would only cut the running time by 50%. - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/4cf1cdad-6896-4d2f-9ad2-af2944e50761) - - -This is the command I run to build a summary of all the build times `find -regex ./logs/.*/base -type d -exec python3 util/genElapsedTime.py -d {} \; | sort -hr -k2` - - - - - - - - -Stage | time/s --- | -- -5_2_TritonRoute | 21313 -5_2_TritonRoute | 7284 -5_2_TritonRoute | 4744 -5_2_TritonRoute | 2964 -5_2_TritonRoute | 1825 -5_2_TritonRoute | 1482 -3_3_place_gp | 1274 -4_1_cts | 1158 -3_3_place_gp | 666 -1_1_yosys | 617 -4_1_cts | 379 -6_report | 332 -3_3_place_gp | 312 -5_2_TritonRoute | 294 -3_5_opendp | 293 -1_1_yosys | 287 -5_2_TritonRoute | 282 -3_3_place_gp | 278 -4_1_cts | 273 -3_4_resizer | 224 -4_1_cts | 203 -5_1_fastroute | 198 -6_report | 164 -5_1_fastroute | 164 -1_1_yosys | 160 -5_1_fastroute | 142 -3_1_place_gp_skip_io | 132 -5_1_fastroute | 126 -3_4_resizer | 123 -6_report | 116 -3_5_opendp | 109 -... | ... - - - - - - - -### maliberty -That is average behaviour as drt is costly. It does scale pretty well with threads so more CPUs helps. We do have some work to do distributed drt if you want to test it out but it isn't in the flow currently due to the extra setup overhead. - -### maliberty -How many threads in your data above? - -### oharboe -No question or suggestions here, just a datapoint that I thought it might have some value in sharing. - -### maliberty -Fwiw we test with 40 cpus and I know Google often uses 96. We have tested with several hundred in distributed mode. - diff --git a/gh_discussions/Runtime/3593.md b/gh_discussions/Runtime/3593.md deleted file mode 100644 index c5acfb118d956e82e87c1ee8e80ade7301956e44..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/3593.md +++ /dev/null @@ -1,40 +0,0 @@ -# Running times for 6_report as a function of area - -Tool: Global Routing - -Subcategory: Performance issue - -## Conversation - -### oharboe -Using https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/pull/1211 and executing `python util/plot-running-times.py`, I've plotted some running times against area: - -`6_report` running time in seconds below. Note that the x axis is um^2, but that it is multiplied by 1e6 (as can be seen in the lower right corner). - -As can be seen, the running time is worse than proportional to area and I imagine that there could be some low hanging fruit as I would expect reporting not to be on the order of detailed routing times. - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/499880aa-0e07-4772-9e10-73dddcf9ef51) - - -``` -cat /proc/cpuinfo | grep processor | wc -l -12 -``` - -### oharboe -Same for `2_6_pdn`, here running time is proportional to area: - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/12bf57a3-9670-47d3-a19e-98c35f023ac1) - - -### oharboe -`5_2_TritonRoute` running times are misleading as there's some sort of problem with DRC errors #3592 - -However, since I have the data, I include the plot here anyway. - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/80e6d705-994a-408d-9847-461b75cfaa37) - - -### oharboe -A feature request has been filed to improve reporting times #3599 - diff --git a/gh_discussions/Runtime/3604.md b/gh_discussions/Runtime/3604.md deleted file mode 100644 index 1f23c159feb9a63a59e99f989e5d154d109d2bcf..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/3604.md +++ /dev/null @@ -1,76 +0,0 @@ -# How do I find out which nets detailed placed failed on? - -Tool: Detailed Placement - -Subcategory: Timing constraint issue - -## Conversation - -### oharboe -If I try to bump mock-array frequency from 8000ps to 1000ps, I get detailed placement errors. - -How do I find out which nets detailed placement is failing for? - -``` -[INFO DPL-0035] hold7527 -[INFO DPL-0035] hold7527 -[INFO DPL-0035] hold19172 -[INFO DPL-0035] hold33345 -[INFO DPL-0035] hold33345 -[INFO DPL-0035] hold33346 -[INFO DPL-0035] hold1805 -[INFO DPL-0035] hold19173 -[INFO DPL-0035] hold7528 -[INFO DPL-0035] input2044 -[ERROR DPL-0036] Detailed placement failed. -Error: cts.tcl, 90 DPL-0036 -Command exited with non-zero status 1 -Elapsed time: 1:53.31[h:]min:sec. CPU time: user 113.09 sys 0.19 (99%). Peak memory: 792296KB. -make: *** [Makefile:579: results/asap7/mock-array/base/4_1_cts.odb] Error 1 -``` - - -### oharboe -Change I tried: - -``` -$ git show -commit be3fd43658747fa25b16fd7fb7317a36e92d7362 (HEAD) -Author: Øyvind Harboe -Date: Tue Jul 11 09:01:30 2023 +0200 - - mock-array: reduce clock period to 1000ps from 8000ps - - Signed-off-by: Øyvind Harboe - -diff --git a/flow/designs/asap7/mock-array/Element/constraints.sdc b/flow/designs/asap7/mock-array/Element/constraints.sdc -index 1d817bb8..0a66e62e 100644 ---- a/flow/designs/asap7/mock-array/Element/constraints.sdc -+++ b/flow/designs/asap7/mock-array/Element/constraints.sdc -@@ -4,7 +4,7 @@ set cols [expr {[info exists ::env(MOCK_ARRAY_COLS)] ? $::env(MOCK_ARRAY_COLS) : - - set clk_name clock - set clk_port_name clock --set clk_period 8000 -+set clk_period 1000 - - set clk_port [get_ports $clk_port_name] - create_clock -period $clk_period -waveform [list 0 [expr $clk_period / 2]] -name $clk_name $clk_port -diff --git a/flow/designs/asap7/mock-array/constraints.sdc b/flow/designs/asap7/mock-array/constraints.sdc -index ad66e12c..7370cc7f 100644 ---- a/flow/designs/asap7/mock-array/constraints.sdc -+++ b/flow/designs/asap7/mock-array/constraints.sdc -@@ -1,6 +1,6 @@ - set sdc_version 2.0 - --set clk_period 8000 -+set clk_period 1000 - create_clock [get_ports clock] -period $clk_period -waveform [list 0 [expr $clk_period/2]] - - set clk_name clock -``` - - -### maliberty -Was this after the abutment PR? If so you should retry again after https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/pull/1221 as that opens up rows in the core. - diff --git a/gh_discussions/Runtime/3694.md b/gh_discussions/Runtime/3694.md deleted file mode 100644 index 425ee350ae69396392b0e1a6088347074c02e8d7..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/3694.md +++ /dev/null @@ -1,32 +0,0 @@ -# report_worst_slack returns INF - -Tool: OpenSTA - -Subcategory: Timing analysis issue - -## Conversation - -### xiaosinju -I have run the following script: -``` -read_lef ispd19_test6.input.lef -read_def ispd19_test6.input.def -set thread_count 8 -global_route -detailed_route -write_db route.db -report wns ->> wns 0 -report tns ->> tns 0 -report worst_slack ->> worst slack INF -``` -Did anything go wrong? How can I get correct metrics? Thanks a lot! - -### vijayank88 -Do estimate parasitic and then report the metrics. Refer here: https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/test/flow.tcl#L264-L280 @xiaosinju - -### maliberty -This is a routing test case and has no timing information (no .lib or .sdc). What are you trying to accomplish? - diff --git a/gh_discussions/Runtime/3745.md b/gh_discussions/Runtime/3745.md deleted file mode 100644 index 691b90852d4563bae6ebdde167b2b6d1c23ab665..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/3745.md +++ /dev/null @@ -1,76 +0,0 @@ -# mock-array placement is very different from row to row - -Tool: Global Placement - -Subcategory: Unexpected placement behavior - -## Conversation - -### oharboe -I'm curious as to why the placement gives so different results for a situation that should be identical. - -The rows in mock-array are identical and there are io_lsbs_* on the right of mock-array that are fed flip flops. - -A snapshot from `make gui_place`: - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/91c718ad-7392-4af6-8ed4-ce2184e6ef80) - -If I zoom in on the upper right row, I see that the io_lsbs_*, fed by a flipflop that is placed right next to the outputs are somewhat spread out: - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/25d2393c-d316-4ca0-a50c-9bdeef629066) - -If I look at the row below and to the right, I see that the io_lsbs_* are clustered together, which looks neat. - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/f5530a21-1135-4ad3-9f60-3304f2538d2f) - -At the bottom row to the right, the io_lsbs_* are mixed into the other pins: - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/5b4d25a7-567f-480f-bf58-736cb65bb0e3) - - - -Side-note: make foo_issue doesn't work out of the box on mock-array because the size of the tar.gz file is ca. 100mBytes. This complicates filing bug reports and feature requests. - -Side-note: the io_lsbs_* are driven by a flip flop, then go to an output cell and are finally buffered before they go to the pin of the macro. Silly question: what does an output cell do and why does it need to be buffered? Can't the flip-flop drive the output pin directly? - - -### maliberty -Global placement isn't a process that will produce identical results in all areas, even if they have symmetry. We could look at specific areas if they seem to be suboptimal. - -You can put the issue in google drive and put a link in the issue. - -We buffer the inputs and outputs by default but it isn't strictly mandatory. FF often don't have a large amount of drive strength for driving output signals. However with no output loading in the sdc it probably doesn't matter but is a bit unrealistic. - -Btw, I still find there is too much hold buffering due to the unrealistically io constraints. - -### oharboe -> Global placement isn't a process that will produce identical results in all areas, even if they have symmetry. We could look at specific areas if they seem to be suboptimal. - -I was just curious how much difference is considered pathological. If, looking at the pictures, this variation is expected, then I don't think there is anything more to investigate here. - -`make global_place_issue` generated a 120mByte .tar.gz file, but zipping just the 3_place.odb file gave me 2 mByte .zip file: [place.zip](https://github.com/The-OpenROAD-Project/OpenROAD/files/12225008/place.zip) - -To generate it locally, run `make DESIGN_CONFIG=designs/asap7/mock-array/config.mk place` - -If there is something interesting here, then this discussion can be converted to a feature request with the click of a button... - -> You can put the issue in google drive and put a link in the issue. -> -> We buffer the inputs and outputs by default but it isn't strictly mandatory. FF often don't have a large amount of drive strength for driving output signals. However with no output loading in the sdc it probably doesn't matter but is a bit unrealistic. - -I imagine that a flip flop with a lot of drive strength would be bigger and slower... seems sensible to create a small, fast and weak flip flop and leave buffering to buffers and inverters... - -> -> Btw, I still find there is too much hold buffering due to the unrealistically io constraints. - -Yes... I've got changes locally removes that, but I need to understand the clock tree generation better first. That's separate concern to placement though. - -### maliberty -If I look at the current mock array the areas around the IOs are so filled with hold cells that the variation isn't as interesting as you show above as they are packed with cell, eg -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/761514/85c19478-10dc-4e52-98e0-79af467df0f0) - -Also the IOs are not placed symmetrically with respect to the macros which will influence global placement. - -### oharboe -If this behavior exists when the hold cells are gone, then it's worth a second look. - diff --git a/gh_discussions/Runtime/3811.md b/gh_discussions/Runtime/3811.md deleted file mode 100644 index e9b9f17e0d5029b8f98b05941ae82793415a893f..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/3811.md +++ /dev/null @@ -1,97 +0,0 @@ -# A lot of slew in asap7/sram-64x16 - -Tool: Clock Tree Synthesis - -Subcategory: Timing analysis issue - -## Conversation - -### oharboe -Is this amount of slew expected on the clock pin to the SRAM? - -`SRAM2RW16x32_2/CE2` is one of two clocks to the SRAM, the SRAM has one read and one write port. - -``` -make DESIGN_CONFIG=designs/asap7/sram-64x16/config.mk -``` - -``` ->>> report_checks -path_delay max -fields {slew net cap} -to _351_/D -Startpoint: SRAM2RW16x32_2 (rising edge-triggered flip-flop clocked by io_clk) -Endpoint: _351_ (falling edge-triggered flip-flop clocked by io_clk') -Path Group: io_clk -Path Type: max - -Fanout Cap Slew Delay Time Description ------------------------------------------------------------------------------ - 0.00 0.00 clock io_clk (rise edge) - 241.44 241.44 clock network delay (propagated) - 150.83 0.00 241.44 ^ SRAM2RW16x32_2/CE2 (SRAM2RW16x32) - 40.24 202.07 443.51 v SRAM2RW16x32_2/O2[4] (SRAM2RW16x32) - 1 9.73 _SRAM2RW16x32_2_O2[4] (net) - 53.97 5.14 448.65 v _351_/D (DFFLQNx1_ASAP7_75t_R) - 448.65 data arrival time - - 500.00 500.00 clock io_clk' (fall edge) - 186.47 686.47 clock network delay (propagated) - 0.52 686.99 clock reconvergence pessimism - 686.99 v _351_/CLK (DFFLQNx1_ASAP7_75t_R) - -22.88 664.11 library setup time - 664.11 data required time ------------------------------------------------------------------------------ - 664.11 data required time - -448.65 data arrival time ------------------------------------------------------------------------------ - 215.46 slack (MET) -``` - - -### maliberty -Probably not but without a test case not much more can be said. - -### oharboe -`make DESIGN_CONFIG=designs/asap7/sram-64x16/config.mk issue_cts` standalone testcase: - -1. Unzip (note! bzip2 compression so that it would fit into github limit) [slew.zip](https://github.com/The-OpenROAD-Project/OpenROAD/files/12294012/slew.zip) -2. run `./run*.sh` -3. Enter `report_checks -path_delay max -fields {slew net cap} -to _351_/D` in the GUI - -You should get: - - -``` ->>> report_checks -path_delay max -fields {slew net cap} -to _351_/D -Startpoint: SRAM2RW16x32_2 (rising edge-triggered flip-flop clocked by io_clk) -Endpoint: _351_ (falling edge-triggered flip-flop clocked by io_clk') -Path Group: io_clk -Path Type: max - -Fanout Cap Slew Delay Time Description ------------------------------------------------------------------------------ - 0.00 0.00 clock io_clk (rise edge) - 274.66 274.66 clock network delay (propagated) - 186.64 0.00 274.66 ^ SRAM2RW16x32_2/CE2 (SRAM2RW16x32) - 35.53 205.56 480.22 v SRAM2RW16x32_2/O2[4] (SRAM2RW16x32) - 1 7.54 _SRAM2RW16x32_2_O2[4] (net) - 47.76 5.26 485.49 v _351_/D (DFFLQNx1_ASAP7_75t_R) - 485.49 data arrival time - - 500.00 500.00 clock io_clk' (fall edge) - 212.33 712.33 clock network delay (propagated) - 0.00 712.33 clock reconvergence pessimism - 712.33 v _351_/CLK (DFFLQNx1_ASAP7_75t_R) - -21.20 691.13 library setup time - 691.13 data required time ------------------------------------------------------------------------------ - 691.13 data required time - -485.49 data arrival time ------------------------------------------------------------------------------ - 205.64 slack (MET) - -``` - - - -### maliberty -Converted to an issue https://github.com/The-OpenROAD-Project/OpenROAD/issues/3817 - diff --git a/gh_discussions/Runtime/3953.md b/gh_discussions/Runtime/3953.md deleted file mode 100644 index d3b5a1abb4550672eedc1b00e22f2fb4c1ed3b41..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/3953.md +++ /dev/null @@ -1,31 +0,0 @@ -# Odd looking placement density in designs/nangate45/gcd - -Tool: Graphical User Interface - -Subcategory: Visualization issue - -## Conversation - -### oharboe -Run `make designs/nangate45/gcd/config.mk && make designs/nangate45/gcd/config.mk gui_final` and enable placement heat map. - -This looks odd. There is less going on in the top and right edges, but it still "looks wrong" to me. - -Thoughts? - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/532929ca-34bd-4bce-b3b2-df547ff91e26) - - -### maliberty -It does look a bit odd. @AcKoucher can you take a look? - -### AcKoucher -With nets being draw it's a bit hard to see. I just ran master in nangate45/gcd and as far as I see, everything looks ok. -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/104802710/28693f96-c91d-4b92-a1af-4985741156c5) - - - - -### AcKoucher -I just realized in the discussion name it says Placement Density, but in your image we see Routing Congestion. - diff --git a/gh_discussions/Runtime/3974.md b/gh_discussions/Runtime/3974.md deleted file mode 100644 index a21b10a67c708bc69f68d3676ca6e1942a228605..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/3974.md +++ /dev/null @@ -1,47 +0,0 @@ -# Scaling the detailed router to handle circuits with 50 million cells - -Tool: Detailed Routing - -Subcategory: Performance scalability - -## Conversation - -### liangrj2014 -Any ideas in scaling the detailed router to handle circuits with 50 million cells? The memory footprint and runtime will be serious concerns. Blows are suggestions from ChatGPT :) - -1. Parallelization: Leverage parallel processing techniques to distribute the routing tasks across multiple CPU cores or GPUs. Multithreading and GPU acceleration can significantly speed up the routing process. -2. Hierarchical Routing: Implement hierarchical routing techniques that break down the routing problem into smaller, more manageable subproblems. This reduces the complexity of routing large circuits. -3. Incremental Routing: Instead of routing the entire circuit in one go, use incremental routing where you route smaller sections of the circuit at a time. This can improve efficiency and reduce memory requirements. -4. Advanced Algorithms: Explore advanced routing algorithms that are optimized for large-scale circuits. Some algorithms are specifically designed to handle massive designs efficiently. -5. Memory Management: Optimize memory usage by employing data structures and algorithms that reduce memory overhead. Use memory-efficient representations of the circuit. -6. Distributed Computing: Consider distributed computing approaches where the routing task is distributed across multiple machines or nodes in a cluster. This can further speed up routing for large circuits. -7. Machine Learning: Investigate the use of machine learning techniques to predict and guide the routing process. Machine learning can help in making routing decisions more efficiently. -8. Resource-Aware Routing: Develop routing algorithms that are aware of available resources (e.g., routing tracks, vias) and can make intelligent decisions to optimize routing. -9. Algorithmic Improvements: Continuously research and implement algorithmic improvements and optimizations specific to global and detailed routing for large-scale circuits. -10. Hardware Acceleration: Explore the use of specialized hardware accelerators, such as FPGA-based routers, to handle the routing tasks efficiently. -11. Circuit Abstraction: Utilize abstraction techniques to reduce the complexity of the circuit during routing without sacrificing the quality of the final solution. -12. Memory Hierarchy: Optimize the use of cache and memory hierarchies to minimize data access latencies during the routing process. -13. Benchmarking and Profiling: Regularly benchmark and profile the routing tool to identify performance bottlenecks and areas for improvement. -14. User Guidance: Provide options for users to guide the router's behavior, allowing them to make trade-offs between runtime and routing quality. -15. Incremental Updates: Implement mechanisms for incremental updates, allowing users to modify parts of the design without rerouting the entire circuit. - - -### maliberty -If the goal is detailed routing then you could look at the work we have done for distributed detailed routing. It doesn't solve the memory concern but it does allow you to apply a lot more CPU to the runtime. - -### maliberty -@osamahammad21 would you run (or have Ahmed run) bsg_chip and mempool_group from [ISPD2024_benchmarks](https://drive.google.com/drive/u/2/folders/1afrsbeS_KuSeHEVfuQOuLWPuuZqlDVlw) on a 96-core machine on GCP to get a runtime & memory baseline. Also run with the distributed router to see how much it helps with runtime as you have before. - -### osamahammad21 -bsg_chip: - -- Machine: 96-CPU 360GB RAM -- Total RUNTIME: 04:14:16 -- Peak Memory: 24.5GB -- Pin Access: - - [INFO DRT-0267] cpu time = 18:12:07, elapsed time = 00:33:37, memory = 8956.00 (MB), peak = 9547.98 (MB) -- Detailed Routing: - - [INFO DRT-0267] cpu time = 80:21:46, elapsed time = 03:26:59, memory = 19989.62 (MB), peak = 24497.96 (MB) -- Converged After 57 Iterations -- Did not set a min/max routing layer - diff --git a/gh_discussions/Runtime/4001.md b/gh_discussions/Runtime/4001.md deleted file mode 100644 index 06be75aadc6708e92a8a739d304b1fac1d7dfabe..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/4001.md +++ /dev/null @@ -1,108 +0,0 @@ -# I have some trouble when running Openroad tools for foreign pdk. - -Tool: Initialize Floorplan - -Subcategory: Floorplan initialization issue - -## Conversation - -### OuDret -Hello, I have been reading documentation and trying stuff with given pdks for about two weeks. My goal was to run OpenRoadFlowScripts but, since there is a lot of stuff, I’ve took its makefile, config files and scripts and just extracted the openroad commands that I really need, so I can exactly know what args and what files i need and create them. Also running the commands 1 by 1 alongside GUI application helps me understanding what’s going on. - -When calling the commands tho, I had some issues i could not solve. If you have an idea of any of the following problems I'm facing or any advice let me know. - -**1. I didn’t manage to initialize floorplan with custom die area. It doesn’t matter which values I use as die_are or core_area, it just doesn’t work properly.** - -When I run something like the command below, having stdSite size defined as 400 by 400 um it just does nothing. The verilog file provided is a simple inverter already synthesized using yosys into a single NAND cell which size is set in .lef as 200 by 200. - -Screenshot 2023-09-15 101107 - - -Meanwhile, if I just let openroad to decide what size to give it just works for small core utilization value, which kinda makes sense. - -Screenshot 2023-09-15 101209 - - -Do you think I’m forgetting any step? The commands I run before getting to that point are the following: - -``` -read_liberty /path/lib/NandCellLibrary.lib -read_lef /path/lef/NandCellLibrary.tech.lef -read_lef /path/lef/NandCellLibrary.macro.lef -read_verilog /path//inverter.v -link_design inverter -read_sdc /path/constraint.sdc - -initialize_floorplan -die_area {0 0 10000 10000} -core_area {1000 1000 5000 5000} -site stdSite -``` - -**2. I have no macros stored in odb despite having them declared in lef/NandCellLibrary.macro.lef** - -If I just use utilization_area **floorplan_initialization** and keep running the following commands all seems to be working properly - -``` -make_tracks met1 -x_offset 10 -x_pitch 10 -y_offset 10 -y_pitch 10 -make_tracks met2 -x_offset 10 -x_pitch 10 -y_offset 10 -y_pitch 10 -make_tracks met3 -x_offset 10 -x_pitch 10 -y_offset 10 -y_pitch 10 -remove_buffers -place_pins -hor_layer met2 -ver_layer met3 -random -global_placement -density 0.5 -pad_left 0 -pad_right 0 -``` - -Screenshot 2023-09-15 101442 - -until I try to run macro placement - -Screenshot 2023-09-15 101654 - -the error raised means that when running the following tcl procedure it has not found any macro -``` -proc find_macros {} { - set macros "" - - set db [ord::get_db] - set block [[$db getChip] getBlock] - foreach inst [$block getInsts] { - set inst_master [$inst getMaster] - - # BLOCK means MACRO cells - if { [string match [$inst_master getType] "BLOCK"] } { - append macros " " $inst - } - } - return $macros -} -``` - -the thing is that I have the NAND macro and another one called FILL defined in my .lefs and .lib . Then why could it be that there is no macro in db ? - -**Some things to be said.** -When running **read_liberty**, it prints 1 into terminal. Does it mean that there’s an error? It seems I can keep running things. If so, is there any way to properly debug it? -It also happens if I run **check_status** command after reading all input files, which I didn’t even find in documentation, so I just ignored it. - -Again, if you had any idea or advice of what I’m doing wrong, if I skipt some important step, etc. let me know, please. - -If i manage to make it work i will try to post the whole flow command by command. It may help someone someday - -Thank you. - - - -### maliberty -What is the size of stdSite? Is this a PDK you can share or is it proprietary? - -Do you have any instances of the macro in your netlist? - -### maliberty -``` -SITE stdSite - SYMMETRY Y ; - CLASS CORE ; - SIZE 500 BY 500 ; -END stdSite -``` -is a huge site (500um x 500um) - I'm guessing that is a mistake though it doesn't explain the problem. - -### maliberty -Your LEF is missing the units for " DATABASE MICRONS \;". There is a bug when this is unspecified that I'll fix but you should set it (the LEF default value is very old). - diff --git a/gh_discussions/Runtime/4096.md b/gh_discussions/Runtime/4096.md deleted file mode 100644 index db5343b260dee5c699e47fe8e95c0cce1f98f367..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/4096.md +++ /dev/null @@ -1,39 +0,0 @@ -# Detailed Routing abort on libc.so.6 - -Tool: Detailed Routing - -Subcategory: Crash report - -## Conversation - -### marcopoles -Hi , -I'm working on tsmc 40nm porting and the flow stops to work on detailed routing with this error: - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/24896919/7c4d6959-f126-4b62-940f-2b3ec59e3d26) - -Do you have any suggestion about the problem? - -Thanks - -PS: working on not open source PDK I can't submit a testcase - -### maliberty -@osamahammad21 any guesses? - - -### osamahammad21 -@marcopoles Could you build openroad in DEBUG mode so that I can locate exactly at which line does this happen? - -### marcopoles -Hi, here the new output: -image - - -### osamahammad21 -@refaay Could you start a PR to ignore via definitions that include masterslice layers in DRT? - -### refaay -Submitted PR #4149 to ignore masterslice vias in drt. -PR #4149 merged. - diff --git a/gh_discussions/Runtime/4249.md b/gh_discussions/Runtime/4249.md deleted file mode 100644 index ee7794156dd7d909ca8320ea409a4cd0fa121f71..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/4249.md +++ /dev/null @@ -1,49 +0,0 @@ -# Unknown layer VV while reading tech file - -Tool: Detailed Routing - -Subcategory: Layer parsing issue - -## Conversation - -### msingh9 -I am trying to use a proprietary pdk and I hit issue when running command pin_access. - -# Global routing -pin_access -bottom_routing_layer $min_routing_layer \ - -top_routing_layer $max_routing_layer - -From the error message, it looks like layer "VV" is not recognized. However, while reading tech file (earlier in the flow), It did find this layer. There are lots of warnings during tech file read but I see similar warnings for other layers too. - -This is the error message I get: -[WARNING DRT-0124] Via VV with unused layer VV_XX_450_450_450_450_VV will be ignored. -[ERROR DRT-0129] Unknown layer VV for viarule VV_VIAGEN. - -These are some of information and warnings while reading tech file. -[WARNING ODB-0279] parse mismatch in layer property LEF58_TYPE for layer II_QM_BOT : "TYPE SPECIALCUT LAYER IA QM ;" -[INFO ODB-0388] unsupported LEF58_ANTENNAGATEPLUSDIFF property for layer VV :"ANTENNAGATEPLUSDIFF OXIDE1 5.0 ; " - -My question is - -It seems to read tech file without error at the beginning of the flow. Then why is it reading tech and libs again with the command pin_access. First time it didn't error out, but it generates error during this step. - -# Global routing -pin_access -bottom_routing_layer $min_routing_layer \ - -top_routing_layer $max_routing_layer -[INFO DRT-0149] Reading tech and libs. - -I have checked that layer VV is defined in the tech file. - -Any suggestions and ideas on what I can try to bypass this error. - -I am only interested in rough timing and area results after global routing. - - - - - -### maliberty -If you only want rough results you can skip the pin_access command. The LEF was read earlier but the interpretation is being made now and some issue is being flagged. The exact issue is hard to say from this info. - -### msingh9 -Thanks for suggestion. This enabled me to get past this point and finish global route. - diff --git a/gh_discussions/Runtime/4258.md b/gh_discussions/Runtime/4258.md deleted file mode 100644 index 6540e7d89cfd22dde5526636cd5f64f0bbd74543..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/4258.md +++ /dev/null @@ -1,44 +0,0 @@ -# Need help in custom cell placement since they overlap with power grip - -Tool: Detailed Placement - -Subcategory: Placement conflict - -## Conversation - -### OuDret -Hello, - -I'm trying to use openroad commands to place custom pdk cells but they overlap with power grid. - -Here in https://github.com/OuDret/my_pdk/tree/main you can see all the files I'm using. - -There are also all the commands I'm running in ./flow.txt. You can simply copy-paste all the lines in flow.txt file into OpenRoad command line at once to reproduce the case. - -Unfortunately I'm using absolute path when loading tech and design so you may need to change it. - -I'm trying to simplify the flow as much as I can so I may have forgotten to run some important steps. - -Thank you for any advice you can provide - -[EDIT] I forgot to show the 2 warnings that are raised when I run ```improve_placement``` which must be related to the overlap issue. -``` - [WARNING DPO-0201] Placement check failure during legalization. - [WARNING DPO-0381] Encountered 57 issues when orienting cells for rows. -``` - -![cell_overlap_power_grid](https://github.com/The-OpenROAD-Project/OpenROAD/assets/74424277/43d68ad2-28ab-4749-968d-c9cfd65a4397) -![counter_design](https://github.com/The-OpenROAD-Project/OpenROAD/assets/74424277/849b8ffe-5426-4157-b8a2-60d43c628e38) - - -### maliberty -Where is this process are you manually placing these cells? Are you marking them as fixed? - -### maliberty -I tried to run flow.txt but I get in global placement: -``` -[ERROR GRT-0126] Layers met2 and met3 have the same preferred routing direction -(VERTICAL). -``` -This seems wrong - can you explain what the intention is? - diff --git a/gh_discussions/Runtime/4325.md b/gh_discussions/Runtime/4325.md deleted file mode 100644 index 1e98f8585b631adfa111b7775d80e218253f3d7a..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/4325.md +++ /dev/null @@ -1,57 +0,0 @@ -# place_pins positional arguments not supported - -Tool: Pin Placer - -Subcategory: Tool behavior issue - -## Conversation - -### TanjIsGray -I see from chatter here that some folks use place_pins, but it seems not to work for me, with the error message showing in the title. My io.tcl is: ------ - -set leftPins {} -foreach port [get_ports _l_*] { - lappend leftPins [get_property $port name] -} - -set_io_pin_constraint -region left:* -pin_names $leftPins - -set_io_pin_constraint -region right:* -pin_names { - _r_h_in _r_g_in _r_f_in _r_e_rot25 _r_e_rot11 _r_e_rot06 _r_e_in - _r_d_in _r_c_in _r_l_in _r_a_rot22 _r_a_rot13 _r_a_rot02 _r_a_in - _r_KW0_in -} - -set_io_pin_constraint -region top:* -pin_names { - _t_aCarryIn0 _t_aCarryIn1 _t_aCpropIn - _t_eCarryIn0 _t_eCarryIn1 _t_eCarryIn2 _t_eCpropIn -} - -set_io_pin_constraint -region bottom:* -pin_names { - _b_aCarryOut0 _b_aCarryOut1 _b_aCpropOut - _b_eCarryOut0 _b_eCarryOut1 _b_eCarryOut2 _b_eCpropOut -} - -place_pins -hor_layers metal4 -ver_layers metal5 -min_distance_in_tracks 4 ---- - -which works fine until I added the place_pins command. - -I also used M4 and M5 for layer names (ASAP7) since those are what the openroad -gui viewer shows. - -Is this command blocked by something else? Is the track-multiplier not supported? -Thanks! - -### maliberty -You might try the recent -annealing options. @eder-matheus any further comments? - -### maliberty -Would you include a screen shot of what you are seeing? Note that -min_distance means pin can be that close together at a minimum, not that they will necessarily be that close together if there is extra space available. - -### eder-matheus -@TanjIsGray Do you have a reproducible you can share regarding the minimum distance not being respected? We have a bunch of unit tests with different minimum distance values, and all seem to work properly. - -### TanjIsGray -I can share the source, make and tcl. These are not large, a few hundred lines of verilog. - diff --git a/gh_discussions/Runtime/4442.md b/gh_discussions/Runtime/4442.md deleted file mode 100644 index c3daad5cdb8710b7e2d930dd41b6d2dc04ecec31..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/4442.md +++ /dev/null @@ -1,39 +0,0 @@ -# Custom Placement of Two-Row Tall Cells - -Tool: Detailed Placement - -Subcategory: Placement violation - -## Conversation - -### harshkhandeparkar -In the OpenFASoC [LDO generator](https://github.com/idea-fasoc/OpenFASOC/tree/main/openfasoc/generators/ldo-gen), a two-row tall comparator latch is custom placed using the `place_cell` command in a [tcl script](https://github.com/idea-fasoc/OpenFASOC/blob/f7b3440c485ff2accbf549aa11a12a75c01186c1/openfasoc/generators/ldo-gen/flow/scripts/openfasoc/custom_place.tcl#L7). - -This used to work in earlier versions of OpenROAD, but recently the CI is [failing](https://github.com/idea-fasoc/OpenFASOC/actions/runs/7301239627/job/19897490889#step:4:1990) with the following error: -``` -[ERROR DPL-0017] cannot place instance cmp1. -``` - The custom placement is done before running the `detailed_placement` command in the [detail_place.tcl](https://github.com/idea-fasoc/OpenFASOC/blob/main/openfasoc/generators/ldo-gen/flow/scripts/detail_place.tcl) script. If the `detailed_placement` command is removed, the following error is returned: -``` -[ERROR DPL-0044] Cell cmp1 with height 8140 is taller than any row. -Error: detail_place.tcl, 26 DPL-0044 -``` - -Relevant Information: -- OpenROAD Version hash: `e89829335596b351ce665dcc3b73619c0b191c14` -- Comparator Latch Cell: [LEF](https://github.com/idea-fasoc/OpenFASOC/blob/main/openfasoc/generators/ldo-gen/blocks/sky130hvl/lef/LDO_COMPARATOR_LATCH.lef) / [GDS](https://github.com/idea-fasoc/OpenFASOC/blob/main/openfasoc/generators/ldo-gen/blocks/sky130hvl/gds/LDO_COMPARATOR_LATCH.gds) -- Custom placement script: [custom_place.tcl](https://github.com/idea-fasoc/OpenFASOC/blob/main/openfasoc/generators/ldo-gen/flow/scripts/openfasoc/custom_place.tcl) - -Is there a way to place this cell (not as a macro) without placement violations? - -cc: @msaligane - -### rovinski -Have you tried marking the cells as `FIXED` instead of `PLACED`? - -### maliberty -We have recently being doing work related to multi-height cells. The error indicates that the detailed placer is trying to legalize this instance which is sounds like you don't want. FIRM should work for that purpose. Can you provide a test case? - -### maliberty -Your other option is to provide double height site rows. - diff --git a/gh_discussions/Runtime/4445.md b/gh_discussions/Runtime/4445.md deleted file mode 100644 index c4057f385fd8780463343f5eaa338acaeadc48da..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/4445.md +++ /dev/null @@ -1,351 +0,0 @@ -# Creating a mock 8192x64 SRAM for megaboom - -Tool: Global Placement - -Subcategory: Performance issue - -## Conversation - -### oharboe -I'm trying to create a mock SRAM for the L2 in https://github.com/The-OpenROAD-Project/megaboom - -Here is the behavioral model: - -```verilog -module cc_banks_8192x64( - input [12:0] RW0_addr, - input RW0_en, - RW0_clk, - RW0_wmode, - input [63:0] RW0_wdata, - output [63:0] RW0_rdata -); - - reg [63:0] Memory[0:8191]; - reg [12:0] _RW0_raddr_d0; - reg _RW0_ren_d0; - reg _RW0_rmode_d0; - always @(posedge RW0_clk) begin - _RW0_raddr_d0 <= RW0_addr; - _RW0_ren_d0 <= RW0_en; - _RW0_rmode_d0 <= RW0_wmode; - if (RW0_en & RW0_wmode) - Memory[RW0_addr] <= RW0_wdata; - end // always @(posedge) - assign RW0_rdata = _RW0_ren_d0 & ~_RW0_rmode_d0 ? Memory[_RW0_raddr_d0] : 64'bx; -endmodule -``` - -`8192 rows x 64 bits = 5*10^5 bits`. This yields `2.7*10^6` instances. At CORE_UTILIZATION=40%, this yields the following floorplan 640um * 1400um. - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/c86a5532-5e36-4b32-a3aa-5bbf0f4396e1) - -The build times for this module become prohibitive. Synthesis is ca. 6000s, 30000s for global placement, and at least as long for CTS. So I really don't want to run through more than the floorplan and at that point create an abstract. - -I have some work in progress where I can mock a smaller area: https://github.com/The-OpenROAD-Project/megaboom/pull/9 - -I don't have a way to mock a realistic clock period for the .lib file that comes out of the floorplan, nor do I know exactly what is realistic for such an SRAM on ASAP7. - -90ps minimum clock period for a 8192x64 SRAM seems pretty good... - -``` ->>> report_clock_min_period -RW0_clk period min = 89.24 fmax 11206.30 -``` - -I can't reconcile the min period of 90ps with what is observed in Timing Report: - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/f397f170-1746-4e77-8dfc-f2fd34ef50d7) - -I wonder if the .lib file that comes out of the floorplan can be useful in architectural exploration. - -This raises a rather open ended question... - -Q: How does the .lib file that comes out of the floorplan compare to a realistic .lib file? - -Is it a "simple matter of scaling" the .lib file, like I can scale area to get something that is something that is in the range of what I want in my architectural exploration? - - - - - - - -### maliberty -I believe the min clock period is based on internal reg-to-reg paths and not reg-IO paths as shown above. - -Using a memory generator is a better idea as this will only get worse the bigger you make the rams. - -### maliberty -Expecting to build to build 2.5M instance blocks quickly will be very difficult in any tool. - -### oharboe -Trying a different approach... Since all I care about is to mock area and timing(creating realistic SRAMs is a separate concern that I'm not tackling now), it doens't matter what the Verilog actually does. Below I have reduced the size of the Memory while I'm using all the address bits. - -``` -module cc_banks_8192x64( - input [12:0] RW0_addr, - input RW0_en, - RW0_clk, - RW0_wmode, - input [63:0] RW0_wdata, - output [63:0] RW0_rdata -); - - reg [63:0] Memory[0:127]; // Smaller memory array - reg [12:0] _RW0_raddr_d0; - reg _RW0_ren_d0; - reg _RW0_rmode_d0; - // XOR high and low bits of the address to use all bits - wire [6:0] effective_addr = RW0_addr[6:0] ^ RW0_addr[12:7]; - always @(posedge RW0_clk) begin - _RW0_raddr_d0 <= effective_addr; - _RW0_ren_d0 <= RW0_en; - _RW0_rmode_d0 <= RW0_wmode; - if (RW0_en & RW0_wmode) - Memory[effective_addr] <= RW0_wdata; - end // always @(posedge) - assign RW0_rdata = _RW0_ren_d0 & ~_RW0_rmode_d0 ? Memory[_RW0_raddr_d0] : 64'bx; -endmodule -``` - -After a few minutes, I have some area and timing for a mock SRAM that should allow me to see what else is going on in this design... - -If I want more aggressive timing, I can adjust the Verilog to be even simpler. Area can be scaled up and down, using the mock_area feature. - -After CTS: - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/e59c2ccd-b58f-4940-8c8c-96bf9286e638) - - - -### oharboe -So with the above approach, I can easily mock large SRAMs and I also have a way to mock the area. - -This allows me to set aside the SRAM concerns to investigate what else is going on in the design and learn something interesting. - -Setting aside the SRAM concern, I can see a lot of logic and high fanout in the timing path for the FpPipeline in the megaboom design. - -What timing closure does this have in commercial tools at a small node? It seems like a lot to ask that PDK and improved post synthesis stages are going to get this to GHz frequencies. Could it be a synthesis problem? Perhaps this version of MegaBoom is missing a pipeline stage or two here? Could there be some structure that has to be specialized in floating point units just like SRAM must be? - -From `make DESIGN_NAME=FpPipeline gui_place`: - -``` ->>> report_checks -rise_from io_flush_pipeline -rise_through input504/A -rise_through input504/Y -rise_through wire12207/A -rise_through wire12207/Y -rise_through max_length12204/A -rise_through max_length12204/Y -rise_through fp_issue_unit/_46407_/B -fall_through fp_issue_unit/_46407_/Y -fall_through fp_issue_unit/_46408_/B -rise_through fp_issue_unit/_46408_/Y -rise_through max_length4078/A -rise_through max_length4078/Y -rise_through fp_issue_unit/_46439_/C -rise_through fp_issue_unit/_46439_/Y -rise_through fp_issue_unit/_46571_/A -fall_through fp_issue_unit/_46571_/Y -fall_through fp_issue_unit/_47883_/A -rise_through fp_issue_unit/_47883_/Y -rise_through fp_issue_unit/_47884_/B -rise_through fp_issue_unit/_47884_/Y -rise_through fp_issue_unit/_47885_/C -rise_through fp_issue_unit/_47885_/Y -rise_through fp_issue_unit/_47886_/D -rise_through fp_issue_unit/_47886_/Y -rise_through fp_issue_unit/_47887_/C -rise_through fp_issue_unit/_47887_/Y -rise_through fp_issue_unit/_47888_/C ... -Startpoint: io_flush_pipeline (input port clocked by clock_vir) -Endpoint: fp_issue_unit/_89827_ - (rising edge-triggered flip-flop clocked by clock) -Path Group: clock -Path Type: max - -Fanout Cap Slew Delay Time Description ------------------------------------------------------------------------------ - 0.00 0.00 0.00 clock clock_vir (rise edge) - 400.00 400.00 clock network delay (ideal) - 300.00 700.00 ^ input external delay - 1 0.79 0.00 0.00 700.00 ^ io_flush_pipeline (in) - io_flush_pipeline (net) - 0.06 0.02 700.02 ^ input504/A (BUFx2_ASAP7_75t_R) - 1 4.55 17.58 15.46 715.48 ^ input504/Y (BUFx2_ASAP7_75t_R) - net504 (net) - 17.89 1.29 716.77 ^ wire12207/A (BUFx16f_ASAP7_75t_R) - 24 53.86 28.61 18.16 734.93 ^ wire12207/Y (BUFx16f_ASAP7_75t_R) - net12207 (net) - 83.92 25.50 760.43 ^ max_length12204/A (BUFx16f_ASAP7_75t_R) - 32 49.26 12.98 29.13 789.57 ^ max_length12204/Y (BUFx16f_ASAP7_75t_R) - net12204 (net) - 220.31 69.86 859.42 ^ fp_issue_unit/_46407_/B (AOI211x1_ASAP7_75t_R) - 3 3.74 59.98 45.43 904.85 v fp_issue_unit/_46407_/Y (AOI211x1_ASAP7_75t_R) - fp_issue_unit/_44478_ (net) - 59.98 0.21 905.07 v fp_issue_unit/_46408_/B (NAND2x2_ASAP7_75t_R) - 26 33.42 134.87 68.93 973.99 ^ fp_issue_unit/_46408_/Y (NAND2x2_ASAP7_75t_R) - fp_issue_unit/_44479_ (net) - 134.89 1.12 975.12 ^ max_length4078/A (BUFx16f_ASAP7_75t_R) - 22 31.72 20.83 33.87 1008.99 ^ max_length4078/Y (BUFx16f_ASAP7_75t_R) - net4078 (net) - 22.31 2.51 1011.50 ^ fp_issue_unit/_46439_/C (AND4x2_ASAP7_75t_R) - 5 7.55 36.45 46.10 1057.60 ^ fp_issue_unit/_46439_/Y (AND4x2_ASAP7_75t_R) - fp_issue_unit/_44510_ (net) - 36.56 1.15 1058.76 ^ fp_issue_unit/_46571_/A (NAND2x2_ASAP7_75t_R) - 4 3.26 16.65 13.84 1072.59 v fp_issue_unit/_46571_/Y (NAND2x2_ASAP7_75t_R) - fp_issue_unit/_44641_ (net) - 16.66 0.11 1072.70 v fp_issue_unit/_47883_/A (INVx1_ASAP7_75t_R) - 2 1.33 12.37 10.21 1082.91 ^ fp_issue_unit/_47883_/Y (INVx1_ASAP7_75t_R) - fp_issue_unit/_45951_ (net) - 12.37 0.02 1082.93 ^ fp_issue_unit/_47884_/B (AND4x2_ASAP7_75t_R) - 3 5.96 30.73 40.69 1123.62 ^ fp_issue_unit/_47884_/Y (AND4x2_ASAP7_75t_R) - fp_issue_unit/_45952_ (net) - 30.87 1.14 1124.77 ^ fp_issue_unit/_47885_/C (AND3x4_ASAP7_75t_R) - 3 5.79 18.52 31.17 1155.94 ^ fp_issue_unit/_47885_/Y (AND3x4_ASAP7_75t_R) - fp_issue_unit/_45953_ (net) - 19.20 1.89 1157.83 ^ fp_issue_unit/_47886_/D (AND4x2_ASAP7_75t_R) - 3 5.98 31.11 42.40 1200.23 ^ fp_issue_unit/_47886_/Y (AND4x2_ASAP7_75t_R) - fp_issue_unit/_45954_ (net) - 31.45 1.82 1202.06 ^ fp_issue_unit/_47887_/C (AND3x4_ASAP7_75t_R) - 3 5.71 17.88 31.40 1233.46 ^ fp_issue_unit/_47887_/Y (AND3x4_ASAP7_75t_R) - fp_issue_unit/_45955_ (net) - 18.17 1.22 1234.68 ^ fp_issue_unit/_47888_/C (AND3x4_ASAP7_75t_R) - 2 5.25 17.00 29.05 1263.73 ^ fp_issue_unit/_47888_/Y (AND3x4_ASAP7_75t_R) - fp_issue_unit/_45956_ (net) - 17.11 0.76 1264.49 ^ fp_issue_unit/_47889_/B (NAND2x2_ASAP7_75t_R) - 3 3.85 15.69 11.87 1276.36 v fp_issue_unit/_47889_/Y (NAND2x2_ASAP7_75t_R) - fp_issue_unit/_45957_ (net) - 15.84 0.84 1277.19 v fp_issue_unit/_47890_/B (OR2x2_ASAP7_75t_R) - 2 3.01 13.61 25.21 1302.41 v fp_issue_unit/_47890_/Y (OR2x2_ASAP7_75t_R) - fp_issue_unit/_45958_ (net) - 13.61 0.09 1302.50 v fp_issue_unit/_47907_/C (OR3x4_ASAP7_75t_R) - 105 99.41 170.82 89.41 1391.91 v fp_issue_unit/_47907_/Y (OR3x4_ASAP7_75t_R) - fp_issue_unit/_45975_ (net) - 172.27 9.22 1401.13 v fp_issue_unit/_47909_/C (NAND3x2_ASAP7_75t_R) - 4 5.43 62.45 62.61 1463.73 ^ fp_issue_unit/_47909_/Y (NAND3x2_ASAP7_75t_R) - fp_issue_unit/_45977_ (net) - 62.45 0.14 1463.88 ^ fp_issue_unit/_47962_/A (NAND3x2_ASAP7_75t_R) - 2 3.47 24.56 17.68 1481.56 v fp_issue_unit/_47962_/Y (NAND3x2_ASAP7_75t_R) - fp_issue_unit/_46030_ (net) - 24.59 0.45 1482.00 v fp_issue_unit/_47966_/B (OR3x2_ASAP7_75t_R) - 3 3.30 17.68 37.03 1519.04 v fp_issue_unit/_47966_/Y (OR3x2_ASAP7_75t_R) - fp_issue_unit/_46034_ (net) - 17.73 0.51 1519.55 v fp_issue_unit/_47971_/C (OR4x2_ASAP7_75t_R) - 7 20.75 71.34 71.67 1591.22 v fp_issue_unit/_47971_/Y (OR4x2_ASAP7_75t_R) - fp_issue_unit/_46039_ (net) - 71.41 1.35 1592.57 v fp_issue_unit/_47972_/A (CKINVDCx16_ASAP7_75t_R) - 32 25.55 28.08 16.95 1609.51 ^ fp_issue_unit/_47972_/Y (CKINVDCx16_ASAP7_75t_R) - fp_issue_unit/_46040_ (net) - 28.08 0.03 1609.55 ^ fp_issue_unit/_47975_/B (OR3x4_ASAP7_75t_R) - 4 5.14 14.79 26.50 1636.05 ^ fp_issue_unit/_47975_/Y (OR3x4_ASAP7_75t_R) - fp_issue_unit/_46043_ (net) - 15.26 1.43 1637.47 ^ fp_issue_unit/_47976_/B (OR2x2_ASAP7_75t_R) - 2 2.90 13.93 21.14 1658.61 ^ fp_issue_unit/_47976_/Y (OR2x2_ASAP7_75t_R) - fp_issue_unit/_46044_ (net) - 13.93 0.13 1658.74 ^ fp_issue_unit/_47980_/B (OR3x2_ASAP7_75t_R) - 2 3.24 14.84 19.30 1678.04 ^ fp_issue_unit/_47980_/Y (OR3x2_ASAP7_75t_R) - fp_issue_unit/_46048_ (net) - 14.93 0.63 1678.68 ^ fp_issue_unit/_47985_/C (OR4x2_ASAP7_75t_R) - 21 25.71 98.46 51.90 1730.57 ^ fp_issue_unit/_47985_/Y (OR4x2_ASAP7_75t_R) - fp_issue_unit/_46053_ (net) - 98.46 0.42 1730.99 ^ load_slew1306/A (BUFx16f_ASAP7_75t_R) - 28 30.02 16.08 30.35 1761.34 ^ load_slew1306/Y (BUFx16f_ASAP7_75t_R) - net1306 (net) - 17.27 1.57 1762.91 ^ fp_issue_unit/_48140_/B (NAND2x1_ASAP7_75t_R) - 2 1.81 14.47 11.73 1774.64 v fp_issue_unit/_48140_/Y (NAND2x1_ASAP7_75t_R) - fp_issue_unit/_06668_ (net) - 14.47 0.03 1774.67 v fp_issue_unit/_48141_/B (OR3x2_ASAP7_75t_R) - 3 3.52 18.24 35.07 1809.73 v fp_issue_unit/_48141_/Y (OR3x2_ASAP7_75t_R) - fp_issue_unit/_06669_ (net) - 18.24 0.11 1809.84 v fp_issue_unit/_48142_/D (OR4x2_ASAP7_75t_R) - 13 37.62 133.19 75.35 1885.19 v fp_issue_unit/_48142_/Y (OR4x2_ASAP7_75t_R) - fp_issue_unit/_06670_ (net) - 133.22 1.49 1886.68 v load_slew1217/A (BUFx16f_ASAP7_75t_R) - 25 39.76 25.02 40.53 1927.21 v load_slew1217/Y (BUFx16f_ASAP7_75t_R) - net1217 (net) - 25.03 0.48 1927.69 v fp_issue_unit/_48144_/B (AND2x2_ASAP7_75t_R) - 3 3.40 13.73 25.88 1953.57 v fp_issue_unit/_48144_/Y (AND2x2_ASAP7_75t_R) - fp_issue_unit/_06672_ (net) - 13.73 0.05 1953.63 v fp_issue_unit/_48145_/B (NOR2x2_ASAP7_75t_R) - 3 2.92 20.73 12.02 1965.65 ^ fp_issue_unit/_48145_/Y (NOR2x2_ASAP7_75t_R) - fp_issue_unit/_06673_ (net) - 20.73 0.02 1965.66 ^ fp_issue_unit/_48146_/A2 (AOI21x1_ASAP7_75t_R) - 6 10.17 53.11 27.64 1993.30 v fp_issue_unit/_48146_/Y (AOI21x1_ASAP7_75t_R) - fp_issue_unit/_06674_ (net) - 53.17 1.07 1994.37 v fp_issue_unit/_65458_/A (NAND2x2_ASAP7_75t_R) - 7 16.17 72.15 46.53 2040.90 ^ fp_issue_unit/_65458_/Y (NAND2x2_ASAP7_75t_R) - fp_issue_unit/_22642_ (net) - 72.97 4.40 2045.30 ^ wire1108/A (BUFx16f_ASAP7_75t_R) - 30 37.30 21.35 27.72 2073.02 ^ wire1108/Y (BUFx16f_ASAP7_75t_R) - net1108 (net) - 75.70 23.26 2096.27 ^ fp_issue_unit/_65465_/A (NAND2x2_ASAP7_75t_R) - 13 21.19 71.00 42.21 2138.48 v fp_issue_unit/_65465_/Y (NAND2x2_ASAP7_75t_R) - fp_issue_unit/_22649_ (net) - 71.33 2.88 2141.36 v load_slew1091/A (BUFx16f_ASAP7_75t_R) - 25 35.92 17.57 30.98 2172.34 v load_slew1091/Y (BUFx16f_ASAP7_75t_R) - net1091 (net) - 78.63 24.44 2196.78 v fp_issue_unit/_67437_/B (AO21x2_ASAP7_75t_R) - 1 4.12 17.15 34.88 2231.66 v fp_issue_unit/_67437_/Y (AO21x2_ASAP7_75t_R) - fp_issue_unit/_46219_ (net) - 17.44 1.21 2232.86 v fp_issue_unit/_89797_/A (FAx1_ASAP7_75t_R) - 1 6.02 144.25 107.03 2339.89 v fp_issue_unit/_89797_/SN (FAx1_ASAP7_75t_R) - fp_issue_unit/_46223_ (net) - 144.48 3.10 2343.00 v fp_issue_unit/_89798_/A (FAx1_ASAP7_75t_R) - 1 2.72 73.82 58.15 2401.14 ^ fp_issue_unit/_89798_/CON (FAx1_ASAP7_75t_R) - fp_issue_unit/_46254_ (net) - 1 1.06 45.86 22.62 2423.76 v fp_issue_unit/_89798_/SN (FAx1_ASAP7_75t_R) - fp_issue_unit/_00644_ (net) - 45.86 0.06 2423.83 v fp_issue_unit/_67461_/A (INVx1_ASAP7_75t_R) - 1 2.41 25.51 20.41 2444.24 ^ fp_issue_unit/_67461_/Y (INVx1_ASAP7_75t_R) - fp_issue_unit/_46226_ (net) - 25.51 0.10 2444.34 ^ fp_issue_unit/_89799_/B (FAx1_ASAP7_75t_R) - 1 1.65 36.10 24.28 2468.62 v fp_issue_unit/_89799_/CON (FAx1_ASAP7_75t_R) - fp_issue_unit/_46261_ (net) - 1 0.86 37.25 19.10 2487.72 ^ fp_issue_unit/_89799_/SN (FAx1_ASAP7_75t_R) - fp_issue_unit/_46232_ (net) - 37.25 0.03 2487.75 ^ fp_issue_unit/_67462_/A (INVx1_ASAP7_75t_R) - 1 2.56 21.51 16.75 2504.50 v fp_issue_unit/_67462_/Y (INVx1_ASAP7_75t_R) - fp_issue_unit/_46229_ (net) - 21.51 0.24 2504.74 v fp_issue_unit/_89800_/A (FAx1_ASAP7_75t_R) - 1 1.68 39.83 26.98 2531.72 ^ fp_issue_unit/_89800_/CON (FAx1_ASAP7_75t_R) - fp_issue_unit/_46264_ (net) - 1 0.90 25.69 17.11 2548.83 v fp_issue_unit/_89800_/SN (FAx1_ASAP7_75t_R) - fp_issue_unit/_46244_ (net) - 25.69 0.03 2548.86 v fp_issue_unit/_89787_/A (INVx1_ASAP7_75t_R) - 1 2.56 21.35 16.40 2565.26 ^ fp_issue_unit/_89787_/Y (INVx1_ASAP7_75t_R) - fp_issue_unit/_46231_ (net) - 21.36 0.17 2565.43 ^ fp_issue_unit/_89803_/B (FAx1_ASAP7_75t_R) - 1 2.30 44.45 26.10 2591.54 v fp_issue_unit/_89803_/CON (FAx1_ASAP7_75t_R) - fp_issue_unit/_46267_ (net) - 1 0.78 39.67 20.18 2611.72 ^ fp_issue_unit/_89803_/SN (FAx1_ASAP7_75t_R) - fp_issue_unit/_46249_ (net) - 39.67 0.01 2611.73 ^ fp_issue_unit/_89786_/A (INVx1_ASAP7_75t_R) - 1 1.74 17.87 14.14 2625.88 v fp_issue_unit/_89786_/Y (INVx1_ASAP7_75t_R) - fp_issue_unit/_46243_ (net) - 17.87 0.04 2625.92 v fp_issue_unit/_89804_/CI (FAx1_ASAP7_75t_R) - 1 0.76 33.65 19.73 2645.65 ^ fp_issue_unit/_89804_/CON (FAx1_ASAP7_75t_R) - fp_issue_unit/_00646_ (net) - 1 0.74 28.73 15.02 2660.67 v fp_issue_unit/_89804_/SN (FAx1_ASAP7_75t_R) - fp_issue_unit/_00645_ (net) - 28.73 0.01 2660.68 v fp_issue_unit/_67482_/A (INVx1_ASAP7_75t_R) - 1 1.02 13.34 11.32 2672.00 ^ fp_issue_unit/_67482_/Y (INVx1_ASAP7_75t_R) - fp_issue_unit/_46248_ (net) - 13.34 0.02 2672.02 ^ fp_issue_unit/_89817_/B (HAxp5_ASAP7_75t_R) - 1 0.78 21.67 12.77 2684.79 v fp_issue_unit/_89817_/CON (HAxp5_ASAP7_75t_R) - fp_issue_unit/_00647_ (net) - 21.67 0.01 2684.80 v fp_issue_unit/_89769_/A (INVx1_ASAP7_75t_R) - 1 2.06 17.70 13.87 2698.68 ^ fp_issue_unit/_89769_/Y (INVx1_ASAP7_75t_R) - fp_issue_unit/_46269_ (net) - 17.70 0.03 2698.70 ^ fp_issue_unit/_89811_/A (FAx1_ASAP7_75t_R) - 2 2.91 47.02 26.02 2724.72 v fp_issue_unit/_89811_/CON (FAx1_ASAP7_75t_R) - fp_issue_unit/_46274_ (net) - 47.02 0.08 2724.80 v fp_issue_unit/_89814_/A (FAx1_ASAP7_75t_R) - 1 1.69 43.76 33.26 2758.06 ^ fp_issue_unit/_89814_/CON (FAx1_ASAP7_75t_R) - fp_issue_unit/_04309_ (net) - 43.76 0.01 2758.07 ^ fp_issue_unit/_48635_/B (XOR2x1_ASAP7_75t_R) - 1 1.16 22.73 24.82 2782.89 ^ fp_issue_unit/_48635_/Y (XOR2x1_ASAP7_75t_R) - fp_issue_unit/_07145_ (net) - 22.73 0.02 2782.92 ^ fp_issue_unit/_48636_/B (NAND2x1_ASAP7_75t_R) - 2 1.32 14.09 11.34 2794.26 v fp_issue_unit/_48636_/Y (NAND2x1_ASAP7_75t_R) - fp_issue_unit/_07146_ (net) - 14.09 0.02 2794.27 v fp_issue_unit/_48637_/B (OR2x2_ASAP7_75t_R) - 3 2.18 11.43 23.11 2817.38 v fp_issue_unit/_48637_/Y (OR2x2_ASAP7_75t_R) - fp_issue_unit/_07147_ (net) - 11.43 0.05 2817.43 v fp_issue_unit/_48639_/C (OR3x1_ASAP7_75t_R) - 1 0.71 10.68 24.49 2841.92 v fp_issue_unit/_48639_/Y (OR3x1_ASAP7_75t_R) - fp_issue_unit/_00000_ (net) - 10.68 0.01 2841.93 v fp_issue_unit/_89827_/D (DFFHQNx2_ASAP7_75t_R) - 2841.93 data arrival time - - 0.00 1500.00 1500.00 clock clock (rise edge) - 0.00 1500.00 clock network delay (ideal) - -10.00 1490.00 clock uncertainty - 0.00 1490.00 clock reconvergence pessimism - 1490.00 ^ fp_issue_unit/_89827_/CLK (DFFHQNx2_ASAP7_75t_R) - -7.35 1482.65 library setup time - 1482.65 data required time ------------------------------------------------------------------------------ - 1482.65 data required time - -2841.93 data arrival time ------------------------------------------------------------------------------ - -1359.27 slack (VIOLATED) - - -``` - - diff --git a/gh_discussions/Runtime/4461.md b/gh_discussions/Runtime/4461.md deleted file mode 100644 index 6b8d6beebdf38a2148103b0222e2d6f930449673..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/4461.md +++ /dev/null @@ -1,391 +0,0 @@ -# MegaBoom clock skew - -Tool: OpenSTA - -Subcategory: Clock skew issue - -## Conversation - -### oharboe -I get a lot of clock skew with https://github.com/The-OpenROAD-Project/megaboom/commit/f5dd1af7841cf1c811a51206bda6f36b446ff335 - - - -``` ->>> report_clock_skew -Clock auto_prci_ctrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock -Latency CRPR Skew -prci_ctrl_domain/_0952_/CLK ^ - 11.20 -tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_095958_/CLK ^ -2185.78 0.00 -2174.58 - -Clock clock -No launch/capture paths found. - -Clock clock_vir -No launch/capture paths found. - -Clock debug_clock -Latency CRPR Skew -tlDM/dmInner/_0926_/CLK ^ - 118.89 -tlDM/dmInner/dmInner/_13930_/CLK ^ - 143.67 0.00 -24.78 -``` - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/faff2190-acda-4d7f-a513-7d4a3c847cdd) - -However, a simple clock skew number doesn't really tell me if the clock skew is a problem. This presentation talks about that: https://www.eng.biu.ac.il/temanad/files/2017/02/Lecture-8-CTS.pdf - -The clock skew is a problem if two flip flops that have a path between them have a large clock skew. Overcompensating for clock skew is bad for power/area/performance. - -Though, it is hard to believe that 2000ps clock skew isn't going to be an issue.... - - -Looking at the max path, ignoring all the hold elements(clock skew?), it seems like a very deep logic path going from the reorder buffer, through the load store unit and back into the rename stage. I can definitely see how this needs to be flattened in synthesis. - -``` -Startpoint: tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_095683_ - (rising edge-triggered flip-flop clocked by auto_prci_ctrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock) -Endpoint: tile_prci_domain/tile_reset_domain/boom_tile/core/rename_stage/freelist/_44863_ - (rising edge-triggered flip-flop clocked by auto_prci_ctrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock) -Path Group: auto_prci_ctrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock -Path Type: max - - Delay Time Description ---------------------------------------------------------- - 0.00 0.00 clock auto_prci_ctrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock (rise edge) -1958.08 1958.08 clock network delay (propagated) - 0.00 1958.08 ^ tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_095683_/CLK (DFFHQNx2_ASAP7_75t_R) - 82.49 2040.56 v tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_095683_/QN (DFFHQNx2_ASAP7_75t_R) - 80.51 2121.07 ^ tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_052821_/Y (CKINVDCx20_ASAP7_75t_R) - 86.15 2207.22 v tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_095639_/CON (HAxp5_ASAP7_75t_R) - 37.20 2244.42 v load_slew37373/Y (BUFx6f_ASAP7_75t_R) - 19.23 2263.65 ^ tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_052860_/Y (CKINVDCx9p33_ASAP7_75t_R) - 24.44 2288.08 ^ tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_064857_/Y (AND2x2_ASAP7_75t_R) - 88.61 2376.70 v tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_095641_/CON (HAxp5_ASAP7_75t_R) - 51.73 2428.42 v max_cap29793/Y (BUFx10_ASAP7_75t_R) - 34.45 2462.87 v tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_053096_/Y (OA222x2_ASAP7_75t_R) - 20.54 2483.41 v tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_053100_/Y (AND5x1_ASAP7_75t_R) - 25.37 2508.78 v tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_053118_/Y (AND3x4_ASAP7_75t_R) - 49.24 2558.02 v tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_053120_/Y (AND2x6_ASAP7_75t_R) - 46.31 2604.33 v tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_053122_/Y (AND4x2_ASAP7_75t_R) - 72.25 2676.58 ^ tile_prci_domain/tile_reset_domain/boom_tile/core/_09441_/Y (NAND2x1_ASAP7_75t_R) - 23.28 2699.86 ^ tile_prci_domain/tile_reset_domain/boom_tile/core/_09452_/Y (OA21x2_ASAP7_75t_R) - 6.13 2705.99 v tile_prci_domain/tile_reset_domain/boom_tile/core/_09453_/Y (INVx1_ASAP7_75t_R) - 14.46 2720.45 v tile_prci_domain/tile_reset_domain/boom_tile/core/_09455_/Y (AND4x2_ASAP7_75t_R) - 12.60 2733.05 v hold3456/Y (BUFx2_ASAP7_75t_R) - 12.42 2745.47 v hold3147/Y (BUFx2_ASAP7_75t_R) - 12.35 2757.83 v hold3457/Y (BUFx2_ASAP7_75t_R) - 12.25 2770.08 v hold2749/Y (BUFx2_ASAP7_75t_R) - 12.23 2782.31 v hold3458/Y (BUFx2_ASAP7_75t_R) - 12.22 2794.54 v hold3148/Y (BUFx2_ASAP7_75t_R) - 12.34 2806.88 v hold3459/Y (BUFx2_ASAP7_75t_R) - 12.28 2819.16 v hold2589/Y (BUFx2_ASAP7_75t_R) - 12.26 2831.41 v hold3460/Y (BUFx2_ASAP7_75t_R) - 12.22 2843.64 v hold3149/Y (BUFx2_ASAP7_75t_R) - 12.29 2855.93 v hold3461/Y (BUFx2_ASAP7_75t_R) - 12.30 2868.23 v hold2750/Y (BUFx2_ASAP7_75t_R) - 12.57 2880.80 v hold3462/Y (BUFx2_ASAP7_75t_R) - 13.60 2894.40 v hold3150/Y (BUFx2_ASAP7_75t_R) - 13.82 2908.22 v hold3463/Y (BUFx2_ASAP7_75t_R) - 27.44 2935.66 v tile_prci_domain/tile_reset_domain/boom_tile/core/_10541_/Y (AND3x4_ASAP7_75t_R) - 18.64 2954.30 v wire17733/Y (BUFx16f_ASAP7_75t_R) - 89.70 3044.00 v wire17732/Y (BUFx16f_ASAP7_75t_R) - 119.92 3163.91 v max_length17731/Y (BUFx16f_ASAP7_75t_R) - 30.15 3194.06 v wire17730/Y (BUFx16f_ASAP7_75t_R) - 91.23 3285.29 v wire17729/Y (BUFx16f_ASAP7_75t_R) - 79.50 3364.80 v tile_prci_domain/tile_reset_domain/boom_tile/lsu/_139693_/Y (AND2x2_ASAP7_75t_R) - 30.15 3394.94 ^ tile_prci_domain/tile_reset_domain/boom_tile/lsu/_139694_/Y (NAND2x2_ASAP7_75t_R) - 54.32 3449.26 v tile_prci_domain/tile_reset_domain/boom_tile/lsu/_139729_/Y (AOI21x1_ASAP7_75t_R) - 27.75 3477.02 v max_cap15253/Y (BUFx12f_ASAP7_75t_R) - 108.62 3585.63 ^ tile_prci_domain/tile_reset_domain/boom_tile/lsu/_267045_/CON (HAxp5_ASAP7_75t_R) - 21.51 3607.14 v tile_prci_domain/tile_reset_domain/boom_tile/lsu/_139732_/Y (CKINVDCx12_ASAP7_75t_R) - 28.07 3635.22 ^ tile_prci_domain/tile_reset_domain/boom_tile/lsu/_267043_/CON (HAxp5_ASAP7_75t_R) - 15.42 3650.63 v tile_prci_domain/tile_reset_domain/boom_tile/lsu/_267017_/Y (INVx1_ASAP7_75t_R) - 53.40 3704.04 ^ tile_prci_domain/tile_reset_domain/boom_tile/lsu/_267041_/CON (HAxp5_ASAP7_75t_R) - 35.49 3739.53 v tile_prci_domain/tile_reset_domain/boom_tile/lsu/_267041_/SN (HAxp5_ASAP7_75t_R) - 31.36 3770.89 v tile_prci_domain/tile_reset_domain/boom_tile/lsu/_149214_/Y (XNOR2x1_ASAP7_75t_R) - 31.07 3801.95 v tile_prci_domain/tile_reset_domain/boom_tile/lsu/_149219_/Y (AND5x2_ASAP7_75t_R) - 20.78 3822.73 v wire11834/Y (BUFx12f_ASAP7_75t_R) - 81.40 3904.13 v tile_prci_domain/tile_reset_domain/boom_tile/core/_09445_/Y (AO221x2_ASAP7_75t_R) - 25.17 3929.30 v wire11643/Y (BUFx16f_ASAP7_75t_R) - 70.74 4000.04 v wire11642/Y (BUFx16f_ASAP7_75t_R) - 84.41 4084.45 v tile_prci_domain/tile_reset_domain/boom_tile/core/_09446_/Y (OR5x2_ASAP7_75t_R) - 15.55 4100.01 v hold2875/Y (BUFx2_ASAP7_75t_R) - 12.67 4112.67 v hold2611/Y (BUFx2_ASAP7_75t_R) - 12.70 4125.38 v hold2876/Y (BUFx2_ASAP7_75t_R) - 12.45 4137.83 v hold2489/Y (BUFx2_ASAP7_75t_R) - 12.41 4150.23 v hold2877/Y (BUFx2_ASAP7_75t_R) - 12.47 4162.71 v hold2612/Y (BUFx2_ASAP7_75t_R) - 14.28 4176.98 v hold2878/Y (BUFx2_ASAP7_75t_R) - 6.16 4183.14 ^ tile_prci_domain/tile_reset_domain/boom_tile/core/_09447_/Y (INVx1_ASAP7_75t_R) - 12.17 4195.32 ^ hold2613/Y (BUFx2_ASAP7_75t_R) - 11.66 4206.97 ^ hold2490/Y (BUFx2_ASAP7_75t_R) - 11.89 4218.86 ^ hold2614/Y (BUFx2_ASAP7_75t_R) - 12.66 4231.52 ^ tile_prci_domain/tile_reset_domain/boom_tile/core/_09449_/Y (AO21x1_ASAP7_75t_R) - 12.91 4244.43 ^ hold2615/Y (BUFx2_ASAP7_75t_R) - 11.74 4256.17 ^ hold2491/Y (BUFx2_ASAP7_75t_R) - 13.34 4269.51 ^ hold2616/Y (BUFx2_ASAP7_75t_R) - 21.75 4291.26 ^ tile_prci_domain/tile_reset_domain/boom_tile/core/_10540_/Y (AND3x4_ASAP7_75t_R) - 12.97 4304.23 ^ hold2753/Y (BUFx2_ASAP7_75t_R) - 12.13 4316.36 ^ hold2617/Y (BUFx2_ASAP7_75t_R) - 12.16 4328.52 ^ hold2754/Y (BUFx2_ASAP7_75t_R) - 12.13 4340.65 ^ hold2591/Y (BUFx2_ASAP7_75t_R) - 12.20 4352.86 ^ hold2755/Y (BUFx2_ASAP7_75t_R) - 12.19 4365.04 ^ hold2618/Y (BUFx2_ASAP7_75t_R) - 12.19 4377.23 ^ hold2756/Y (BUFx2_ASAP7_75t_R) - 12.13 4389.36 ^ hold2492/Y (BUFx2_ASAP7_75t_R) - 12.22 4401.58 ^ hold2757/Y (BUFx2_ASAP7_75t_R) - 12.31 4413.89 ^ hold2619/Y (BUFx2_ASAP7_75t_R) - 12.35 4426.24 ^ hold2758/Y (BUFx2_ASAP7_75t_R) - 25.20 4451.44 ^ hold2592/Y (BUFx2_ASAP7_75t_R) - 39.44 4490.88 ^ wire10835/Y (BUFx16f_ASAP7_75t_R) - 118.30 4609.18 ^ wire10834/Y (BUFx16f_ASAP7_75t_R) - 42.72 4651.90 ^ wire10832/Y (BUFx16f_ASAP7_75t_R) - 92.03 4743.92 ^ tile_prci_domain/tile_reset_domain/boom_tile/lsu/_139741_/Y (AND3x4_ASAP7_75t_R) - 131.71 4875.63 ^ tile_prci_domain/tile_reset_domain/boom_tile/lsu/_139752_/Y (XNOR2x2_ASAP7_75t_R) - 23.62 4899.25 v tile_prci_domain/tile_reset_domain/boom_tile/lsu/_200474_/Y (INVx13_ASAP7_75t_R) - 25.32 4924.57 v max_length9483/Y (BUFx16f_ASAP7_75t_R) - 70.19 4994.76 ^ tile_prci_domain/tile_reset_domain/boom_tile/lsu/_267079_/CON (HAxp5_ASAP7_75t_R) - 16.21 5010.97 v tile_prci_domain/tile_reset_domain/boom_tile/lsu/_139765_/Y (CKINVDCx6p67_ASAP7_75t_R) - 31.91 5042.88 v tile_prci_domain/tile_reset_domain/boom_tile/lsu/_139770_/Y (AND3x1_ASAP7_75t_R) - 106.34 5149.23 v tile_prci_domain/tile_reset_domain/boom_tile/lsu/_267049_/SN (HAxp5_ASAP7_75t_R) - 44.98 5194.21 v tile_prci_domain/tile_reset_domain/boom_tile/lsu/_149221_/Y (XNOR2x1_ASAP7_75t_R) - 33.17 5227.38 v tile_prci_domain/tile_reset_domain/boom_tile/lsu/_149226_/Y (AND5x2_ASAP7_75t_R) - 25.28 5252.66 v wire7254/Y (BUFx12f_ASAP7_75t_R) - 77.52 5330.18 v tile_prci_domain/tile_reset_domain/boom_tile/core/_09462_/Y (AO221x2_ASAP7_75t_R) - 21.54 5351.72 v wire7115/Y (BUFx16f_ASAP7_75t_R) - 69.67 5421.39 v wire7114/Y (BUFx16f_ASAP7_75t_R) - 74.63 5496.02 v tile_prci_domain/tile_reset_domain/boom_tile/core/_09468_/Y (OR4x1_ASAP7_75t_R) - 14.86 5510.88 v hold3695/Y (BUFx2_ASAP7_75t_R) - 12.38 5523.26 v hold2552/Y (BUFx2_ASAP7_75t_R) - 12.33 5535.59 v hold3696/Y (BUFx2_ASAP7_75t_R) - 12.31 5547.89 v hold2504/Y (BUFx2_ASAP7_75t_R) - 12.31 5560.21 v hold3697/Y (BUFx2_ASAP7_75t_R) - 13.56 5573.77 v hold2553/Y (BUFx2_ASAP7_75t_R) - 5.94 5579.70 ^ tile_prci_domain/tile_reset_domain/boom_tile/core/_13953_/Y (INVx1_ASAP7_75t_R) - 12.23 5591.93 ^ hold2554/Y (BUFx2_ASAP7_75t_R) - 11.66 5603.59 ^ hold2505/Y (BUFx2_ASAP7_75t_R) - 11.73 5615.32 ^ hold2555/Y (BUFx2_ASAP7_75t_R) - 28.61 5643.93 ^ tile_prci_domain/tile_reset_domain/boom_tile/core/_13955_/Y (AND4x2_ASAP7_75t_R) - 13.70 5657.64 ^ hold2883/Y (BUFx2_ASAP7_75t_R) - 11.87 5669.51 ^ hold2556/Y (BUFx2_ASAP7_75t_R) - 11.76 5681.27 ^ hold2884/Y (BUFx2_ASAP7_75t_R) - 11.68 5692.95 ^ hold2525/Y (BUFx2_ASAP7_75t_R) - 11.99 5704.94 ^ hold2885/Y (BUFx2_ASAP7_75t_R) - 12.13 5717.06 ^ hold2557/Y (BUFx2_ASAP7_75t_R) - 12.07 5729.14 ^ hold2886/Y (BUFx2_ASAP7_75t_R) - 11.83 5740.97 ^ hold2506/Y (BUFx2_ASAP7_75t_R) - 11.69 5752.66 ^ hold2887/Y (BUFx2_ASAP7_75t_R) - 11.82 5764.48 ^ hold2558/Y (BUFx2_ASAP7_75t_R) - 11.91 5776.39 ^ hold2888/Y (BUFx2_ASAP7_75t_R) - 11.94 5788.33 ^ hold2526/Y (BUFx2_ASAP7_75t_R) - 12.00 5800.33 ^ hold2889/Y (BUFx2_ASAP7_75t_R) - 16.89 5817.22 ^ hold2559/Y (BUFx2_ASAP7_75t_R) - 34.94 5852.15 ^ hold2890/Y (BUFx2_ASAP7_75t_R) - 26.15 5878.30 ^ max_length6496/Y (BUFx16f_ASAP7_75t_R) - 13.60 5891.91 ^ hold2891/Y (BUFx2_ASAP7_75t_R) - 12.02 5903.93 ^ hold2560/Y (BUFx2_ASAP7_75t_R) - 11.87 5915.80 ^ hold2892/Y (BUFx2_ASAP7_75t_R) - 11.74 5927.54 ^ hold2527/Y (BUFx2_ASAP7_75t_R) - 11.79 5939.33 ^ hold2893/Y (BUFx2_ASAP7_75t_R) - 11.81 5951.14 ^ hold2561/Y (BUFx2_ASAP7_75t_R) - 11.96 5963.09 ^ hold2894/Y (BUFx2_ASAP7_75t_R) - 11.93 5975.03 ^ hold2507/Y (BUFx2_ASAP7_75t_R) - 11.94 5986.97 ^ hold2895/Y (BUFx2_ASAP7_75t_R) - 11.87 5998.84 ^ hold2562/Y (BUFx2_ASAP7_75t_R) - 11.96 6010.80 ^ hold2896/Y (BUFx2_ASAP7_75t_R) - 11.88 6022.68 ^ hold2528/Y (BUFx2_ASAP7_75t_R) - 11.83 6034.51 ^ hold2897/Y (BUFx2_ASAP7_75t_R) - 29.92 6064.43 ^ hold2563/Y (BUFx2_ASAP7_75t_R) - 64.30 6128.72 ^ wire6494/Y (BUFx12f_ASAP7_75t_R) - 65.09 6193.82 ^ wire6493/Y (BUFx16f_ASAP7_75t_R) - 75.13 6268.94 ^ tile_prci_domain/tile_reset_domain/boom_tile/lsu/_139772_/Y (AND2x2_ASAP7_75t_R) - 30.93 6299.88 v tile_prci_domain/tile_reset_domain/boom_tile/lsu/_139794_/Y (NAND2x2_ASAP7_75t_R) - 37.31 6337.19 v max_length5802/Y (BUFx16f_ASAP7_75t_R) - 41.02 6378.21 v load_slew5800/Y (BUFx16f_ASAP7_75t_R) - 20.76 6398.97 ^ tile_prci_domain/tile_reset_domain/boom_tile/lsu/_145708_/Y (NOR2x1_ASAP7_75t_R) - 55.06 6454.03 v tile_prci_domain/tile_reset_domain/boom_tile/lsu/_145709_/Y (XNOR2x2_ASAP7_75t_R) - 103.05 6557.08 ^ tile_prci_domain/tile_reset_domain/boom_tile/lsu/_193309_/Y (NOR2x2_ASAP7_75t_R) - 50.56 6607.64 ^ tile_prci_domain/tile_reset_domain/boom_tile/lsu/_212054_/Y (AND2x2_ASAP7_75t_R) - 26.07 6633.71 v tile_prci_domain/tile_reset_domain/boom_tile/lsu/_267110_/CON (HAxp5_ASAP7_75t_R) - 25.60 6659.31 ^ tile_prci_domain/tile_reset_domain/boom_tile/lsu/_267110_/SN (HAxp5_ASAP7_75t_R) - 25.32 6684.63 ^ tile_prci_domain/tile_reset_domain/boom_tile/lsu/_149203_/Y (XOR2x1_ASAP7_75t_R) - 58.24 6742.87 ^ tile_prci_domain/tile_reset_domain/boom_tile/lsu/_149205_/Y (AND5x2_ASAP7_75t_R) - 57.64 6800.51 ^ wire3875/Y (BUFx16f_ASAP7_75t_R) - 78.48 6878.99 ^ tile_prci_domain/tile_reset_domain/boom_tile/core/_09474_/Y (AO221x2_ASAP7_75t_R) - 34.79 6913.78 ^ wire3865/Y (BUFx16f_ASAP7_75t_R) - 56.61 6970.39 ^ tile_prci_domain/tile_reset_domain/boom_tile/core/_09475_/Y (OR4x1_ASAP7_75t_R) - 13.02 6983.41 ^ hold3416/Y (BUFx2_ASAP7_75t_R) - 11.71 6995.11 ^ hold2992/Y (BUFx2_ASAP7_75t_R) - 11.65 7006.76 ^ hold3417/Y (BUFx2_ASAP7_75t_R) - 11.64 7018.40 ^ hold2679/Y (BUFx2_ASAP7_75t_R) - 11.69 7030.09 ^ hold3418/Y (BUFx2_ASAP7_75t_R) - 11.66 7041.75 ^ hold2993/Y (BUFx2_ASAP7_75t_R) - 11.77 7053.52 ^ hold3419/Y (BUFx2_ASAP7_75t_R) - 14.52 7068.04 ^ tile_prci_domain/tile_reset_domain/boom_tile/core/_09476_/Y (AO22x2_ASAP7_75t_R) - 12.18 7080.22 ^ hold3699/Y (BUFx2_ASAP7_75t_R) - 11.67 7091.90 ^ hold2994/Y (BUFx2_ASAP7_75t_R) - 11.66 7103.56 ^ hold3700/Y (BUFx2_ASAP7_75t_R) - 11.73 7115.29 ^ hold2680/Y (BUFx2_ASAP7_75t_R) - 11.77 7127.06 ^ hold3701/Y (BUFx2_ASAP7_75t_R) - 11.84 7138.90 ^ hold2995/Y (BUFx2_ASAP7_75t_R) - 11.86 7150.75 ^ hold3702/Y (BUFx2_ASAP7_75t_R) - 16.27 7167.03 ^ hold3420/Y (BUFx2_ASAP7_75t_R) - 6.40 7173.43 v tile_prci_domain/tile_reset_domain/boom_tile/core/_09477_/Y (INVx1_ASAP7_75t_R) - 12.83 7186.26 v hold2996/Y (BUFx2_ASAP7_75t_R) - 12.44 7198.70 v hold2681/Y (BUFx2_ASAP7_75t_R) - 13.05 7211.75 v hold2997/Y (BUFx2_ASAP7_75t_R) - 23.94 7235.69 v tile_prci_domain/tile_reset_domain/boom_tile/core/_09480_/Y (AND3x4_ASAP7_75t_R) - 17.05 7252.74 v hold3703/Y (BUFx2_ASAP7_75t_R) - 13.73 7266.47 v hold2998/Y (BUFx2_ASAP7_75t_R) - 13.82 7280.29 v hold3704/Y (BUFx2_ASAP7_75t_R) - 13.62 7293.91 v hold2682/Y (BUFx2_ASAP7_75t_R) - 13.64 7307.54 v hold3705/Y (BUFx2_ASAP7_75t_R) - 13.25 7320.80 v hold2999/Y (BUFx2_ASAP7_75t_R) - 12.85 7333.65 v hold3706/Y (BUFx2_ASAP7_75t_R) - 36.78 7370.43 v hold3421/Y (BUFx2_ASAP7_75t_R) - 38.82 7409.25 v hold3707/Y (BUFx2_ASAP7_75t_R) - 15.66 7424.91 v max_length3853/Y (BUFx12f_ASAP7_75t_R) - 11.90 7436.81 v hold3708/Y (BUFx2_ASAP7_75t_R) - 12.17 7448.98 v hold3000/Y (BUFx2_ASAP7_75t_R) - 12.28 7461.26 v hold3709/Y (BUFx2_ASAP7_75t_R) - 12.32 7473.58 v hold2683/Y (BUFx2_ASAP7_75t_R) - 12.42 7486.00 v hold3710/Y (BUFx2_ASAP7_75t_R) - 12.22 7498.22 v hold3001/Y (BUFx2_ASAP7_75t_R) - 12.30 7510.52 v hold3711/Y (BUFx2_ASAP7_75t_R) - 30.05 7540.57 v hold3422/Y (BUFx2_ASAP7_75t_R) - 34.72 7575.29 v tile_prci_domain/tile_reset_domain/boom_tile/core/_14044_/Y (AND2x6_ASAP7_75t_R) - 17.31 7592.60 v hold4909/Y (BUFx2_ASAP7_75t_R) - 17.42 7610.02 v hold3002/Y (BUFx2_ASAP7_75t_R) - 17.51 7627.53 v hold4910/Y (BUFx2_ASAP7_75t_R) - 17.30 7644.84 v hold2684/Y (BUFx2_ASAP7_75t_R) - 16.93 7661.77 v hold4911/Y (BUFx2_ASAP7_75t_R) - 15.77 7677.54 v hold3003/Y (BUFx2_ASAP7_75t_R) - 14.70 7692.24 v hold4912/Y (BUFx2_ASAP7_75t_R) - 27.90 7720.14 v hold3423/Y (BUFx2_ASAP7_75t_R) - 56.26 7776.40 v wire3837/Y (BUFx16f_ASAP7_75t_R) - 43.71 7820.11 ^ tile_prci_domain/tile_reset_domain/boom_tile/core/rename_stage/_05007_/Y (INVx1_ASAP7_75t_R) - 27.46 7847.57 ^ tile_prci_domain/tile_reset_domain/boom_tile/core/rename_stage/_05009_/Y (OR3x4_ASAP7_75t_R) - 41.42 7889.00 ^ wire3756/Y (BUFx16f_ASAP7_75t_R) - 91.66 7980.65 v tile_prci_domain/tile_reset_domain/boom_tile/core/rename_stage/_05011_/Y (CKINVDCx20_ASAP7_75t_R) - 48.71 8029.36 v wire3438/Y (BUFx12f_ASAP7_75t_R) - 70.54 8099.90 v wire3437/Y (BUFx16f_ASAP7_75t_R) - 146.90 8246.80 v tile_prci_domain/tile_reset_domain/boom_tile/core/rename_stage/freelist/_25600_/Y (AND3x4_ASAP7_75t_R) - 29.19 8275.99 v max_length2710/Y (BUFx12f_ASAP7_75t_R) - 38.04 8314.04 v wire2709/Y (BUFx16f_ASAP7_75t_R) - 127.32 8441.35 v tile_prci_domain/tile_reset_domain/boom_tile/core/rename_stage/freelist/_25735_/Y (AND3x4_ASAP7_75t_R) - 44.12 8485.47 v tile_prci_domain/tile_reset_domain/boom_tile/core/rename_stage/freelist/_25736_/Y (AO21x2_ASAP7_75t_R) - 48.25 8533.72 v tile_prci_domain/tile_reset_domain/boom_tile/core/rename_stage/freelist/_25737_/Y (AO21x2_ASAP7_75t_R) - 66.41 8600.12 ^ tile_prci_domain/tile_reset_domain/boom_tile/core/rename_stage/freelist/_25738_/Y (AOI21x1_ASAP7_75t_R) - 40.95 8641.07 ^ max_cap481/Y (BUFx10_ASAP7_75t_R) - 12.72 8653.80 v tile_prci_domain/tile_reset_domain/boom_tile/core/rename_stage/freelist/_38380_/Y (OAI21x1_ASAP7_75t_R) - 18.12 8671.91 v tile_prci_domain/tile_reset_domain/boom_tile/core/rename_stage/freelist/_38384_/Y (AO21x1_ASAP7_75t_R) - 0.01 8671.92 v tile_prci_domain/tile_reset_domain/boom_tile/core/rename_stage/freelist/_44863_/D (DFFHQNx2_ASAP7_75t_R) - 8671.92 data arrival time - -8500.00 8500.00 clock auto_prci_ctrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock (rise edge) - 201.71 8701.71 clock network delay (propagated) - -10.00 8691.71 clock uncertainty - 0.00 8691.71 clock reconvergence pessimism - 8691.71 ^ tile_prci_domain/tile_reset_domain/boom_tile/core/rename_stage/freelist/_44863_/CLK (DFFHQNx2_ASAP7_75t_R) - 15.71 8707.42 library setup time - 8707.42 data required time ---------------------------------------------------------- - 8707.42 data required time - -8671.92 data arrival time ---------------------------------------------------------- - 35.50 slack (MET) -``` - - -If I strip away everything but the logic, I get: - -``` - Delay Time Description ---------------------------------------------------------- - 82.49 2040.56 v tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_095683_/QN (DFFHQNx2_ASAP7_75t_R) - 80.51 2121.07 ^ tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_052821_/Y (CKINVDCx20_ASAP7_75t_R) - 86.15 2207.22 v tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_095639_/CON (HAxp5_ASAP7_75t_R) - 19.23 2263.65 ^ tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_052860_/Y (CKINVDCx9p33_ASAP7_75t_R) - 24.44 2288.08 ^ tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_064857_/Y (AND2x2_ASAP7_75t_R) - 88.61 2376.70 v tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_095641_/CON (HAxp5_ASAP7_75t_R) - 34.45 2462.87 v tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_053096_/Y (OA222x2_ASAP7_75t_R) - 20.54 2483.41 v tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_053100_/Y (AND5x1_ASAP7_75t_R) - 25.37 2508.78 v tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_053118_/Y (AND3x4_ASAP7_75t_R) - 49.24 2558.02 v tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_053120_/Y (AND2x6_ASAP7_75t_R) - 46.31 2604.33 v tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_053122_/Y (AND4x2_ASAP7_75t_R) - 72.25 2676.58 ^ tile_prci_domain/tile_reset_domain/boom_tile/core/_09441_/Y (NAND2x1_ASAP7_75t_R) - 23.28 2699.86 ^ tile_prci_domain/tile_reset_domain/boom_tile/core/_09452_/Y (OA21x2_ASAP7_75t_R) - 6.13 2705.99 v tile_prci_domain/tile_reset_domain/boom_tile/core/_09453_/Y (INVx1_ASAP7_75t_R) - 14.46 2720.45 v tile_prci_domain/tile_reset_domain/boom_tile/core/_09455_/Y (AND4x2_ASAP7_75t_R) - 27.44 2935.66 v tile_prci_domain/tile_reset_domain/boom_tile/core/_10541_/Y (AND3x4_ASAP7_75t_R) - 79.50 3364.80 v tile_prci_domain/tile_reset_domain/boom_tile/lsu/_139693_/Y (AND2x2_ASAP7_75t_R) - 30.15 3394.94 ^ tile_prci_domain/tile_reset_domain/boom_tile/lsu/_139694_/Y (NAND2x2_ASAP7_75t_R) - 54.32 3449.26 v tile_prci_domain/tile_reset_domain/boom_tile/lsu/_139729_/Y (AOI21x1_ASAP7_75t_R) - 108.62 3585.63 ^ tile_prci_domain/tile_reset_domain/boom_tile/lsu/_267045_/CON (HAxp5_ASAP7_75t_R) - 21.51 3607.14 v tile_prci_domain/tile_reset_domain/boom_tile/lsu/_139732_/Y (CKINVDCx12_ASAP7_75t_R) - 28.07 3635.22 ^ tile_prci_domain/tile_reset_domain/boom_tile/lsu/_267043_/CON (HAxp5_ASAP7_75t_R) - 15.42 3650.63 v tile_prci_domain/tile_reset_domain/boom_tile/lsu/_267017_/Y (INVx1_ASAP7_75t_R) - 53.40 3704.04 ^ tile_prci_domain/tile_reset_domain/boom_tile/lsu/_267041_/CON (HAxp5_ASAP7_75t_R) - 35.49 3739.53 v tile_prci_domain/tile_reset_domain/boom_tile/lsu/_267041_/SN (HAxp5_ASAP7_75t_R) - 31.36 3770.89 v tile_prci_domain/tile_reset_domain/boom_tile/lsu/_149214_/Y (XNOR2x1_ASAP7_75t_R) - 31.07 3801.95 v tile_prci_domain/tile_reset_domain/boom_tile/lsu/_149219_/Y (AND5x2_ASAP7_75t_R) - 81.40 3904.13 v tile_prci_domain/tile_reset_domain/boom_tile/core/_09445_/Y (AO221x2_ASAP7_75t_R) - 84.41 4084.45 v tile_prci_domain/tile_reset_domain/boom_tile/core/_09446_/Y (OR5x2_ASAP7_75t_R) - 6.16 4183.14 ^ tile_prci_domain/tile_reset_domain/boom_tile/core/_09447_/Y (INVx1_ASAP7_75t_R) - 12.66 4231.52 ^ tile_prci_domain/tile_reset_domain/boom_tile/core/_09449_/Y (AO21x1_ASAP7_75t_R) - 21.75 4291.26 ^ tile_prci_domain/tile_reset_domain/boom_tile/core/_10540_/Y (AND3x4_ASAP7_75t_R) - 92.03 4743.92 ^ tile_prci_domain/tile_reset_domain/boom_tile/lsu/_139741_/Y (AND3x4_ASAP7_75t_R) - 131.71 4875.63 ^ tile_prci_domain/tile_reset_domain/boom_tile/lsu/_139752_/Y (XNOR2x2_ASAP7_75t_R) - 23.62 4899.25 v tile_prci_domain/tile_reset_domain/boom_tile/lsu/_200474_/Y (INVx13_ASAP7_75t_R) - 70.19 4994.76 ^ tile_prci_domain/tile_reset_domain/boom_tile/lsu/_267079_/CON (HAxp5_ASAP7_75t_R) - 16.21 5010.97 v tile_prci_domain/tile_reset_domain/boom_tile/lsu/_139765_/Y (CKINVDCx6p67_ASAP7_75t_R) - 31.91 5042.88 v tile_prci_domain/tile_reset_domain/boom_tile/lsu/_139770_/Y (AND3x1_ASAP7_75t_R) - 106.34 5149.23 v tile_prci_domain/tile_reset_domain/boom_tile/lsu/_267049_/SN (HAxp5_ASAP7_75t_R) - 44.98 5194.21 v tile_prci_domain/tile_reset_domain/boom_tile/lsu/_149221_/Y (XNOR2x1_ASAP7_75t_R) - 33.17 5227.38 v tile_prci_domain/tile_reset_domain/boom_tile/lsu/_149226_/Y (AND5x2_ASAP7_75t_R) - 77.52 5330.18 v tile_prci_domain/tile_reset_domain/boom_tile/core/_09462_/Y (AO221x2_ASAP7_75t_R) - 74.63 5496.02 v tile_prci_domain/tile_reset_domain/boom_tile/core/_09468_/Y (OR4x1_ASAP7_75t_R) - 5.94 5579.70 ^ tile_prci_domain/tile_reset_domain/boom_tile/core/_13953_/Y (INVx1_ASAP7_75t_R) - 28.61 5643.93 ^ tile_prci_domain/tile_reset_domain/boom_tile/core/_13955_/Y (AND4x2_ASAP7_75t_R) - 75.13 6268.94 ^ tile_prci_domain/tile_reset_domain/boom_tile/lsu/_139772_/Y (AND2x2_ASAP7_75t_R) - 30.93 6299.88 v tile_prci_domain/tile_reset_domain/boom_tile/lsu/_139794_/Y (NAND2x2_ASAP7_75t_R) - 20.76 6398.97 ^ tile_prci_domain/tile_reset_domain/boom_tile/lsu/_145708_/Y (NOR2x1_ASAP7_75t_R) - 55.06 6454.03 v tile_prci_domain/tile_reset_domain/boom_tile/lsu/_145709_/Y (XNOR2x2_ASAP7_75t_R) - 103.05 6557.08 ^ tile_prci_domain/tile_reset_domain/boom_tile/lsu/_193309_/Y (NOR2x2_ASAP7_75t_R) - 50.56 6607.64 ^ tile_prci_domain/tile_reset_domain/boom_tile/lsu/_212054_/Y (AND2x2_ASAP7_75t_R) - 26.07 6633.71 v tile_prci_domain/tile_reset_domain/boom_tile/lsu/_267110_/CON (HAxp5_ASAP7_75t_R) - 25.60 6659.31 ^ tile_prci_domain/tile_reset_domain/boom_tile/lsu/_267110_/SN (HAxp5_ASAP7_75t_R) - 25.32 6684.63 ^ tile_prci_domain/tile_reset_domain/boom_tile/lsu/_149203_/Y (XOR2x1_ASAP7_75t_R) - 58.24 6742.87 ^ tile_prci_domain/tile_reset_domain/boom_tile/lsu/_149205_/Y (AND5x2_ASAP7_75t_R) - 78.48 6878.99 ^ tile_prci_domain/tile_reset_domain/boom_tile/core/_09474_/Y (AO221x2_ASAP7_75t_R) - 56.61 6970.39 ^ tile_prci_domain/tile_reset_domain/boom_tile/core/_09475_/Y (OR4x1_ASAP7_75t_R) - 14.52 7068.04 ^ tile_prci_domain/tile_reset_domain/boom_tile/core/_09476_/Y (AO22x2_ASAP7_75t_R) - 6.40 7173.43 v tile_prci_domain/tile_reset_domain/boom_tile/core/_09477_/Y (INVx1_ASAP7_75t_R) - 23.94 7235.69 v tile_prci_domain/tile_reset_domain/boom_tile/core/_09480_/Y (AND3x4_ASAP7_75t_R) - 34.72 7575.29 v tile_prci_domain/tile_reset_domain/boom_tile/core/_14044_/Y (AND2x6_ASAP7_75t_R) - 43.71 7820.11 ^ tile_prci_domain/tile_reset_domain/boom_tile/core/rename_stage/_05007_/Y (INVx1_ASAP7_75t_R) - 27.46 7847.57 ^ tile_prci_domain/tile_reset_domain/boom_tile/core/rename_stage/_05009_/Y (OR3x4_ASAP7_75t_R) - 91.66 7980.65 v tile_prci_domain/tile_reset_domain/boom_tile/core/rename_stage/_05011_/Y (CKINVDCx20_ASAP7_75t_R) - 146.90 8246.80 v tile_prci_domain/tile_reset_domain/boom_tile/core/rename_stage/freelist/_25600_/Y (AND3x4_ASAP7_75t_R) - 127.32 8441.35 v tile_prci_domain/tile_reset_domain/boom_tile/core/rename_stage/freelist/_25735_/Y (AND3x4_ASAP7_75t_R) - 44.12 8485.47 v tile_prci_domain/tile_reset_domain/boom_tile/core/rename_stage/freelist/_25736_/Y (AO21x2_ASAP7_75t_R) - 48.25 8533.72 v tile_prci_domain/tile_reset_domain/boom_tile/core/rename_stage/freelist/_25737_/Y (AO21x2_ASAP7_75t_R) - 66.41 8600.12 ^ tile_prci_domain/tile_reset_domain/boom_tile/core/rename_stage/freelist/_25738_/Y (AOI21x1_ASAP7_75t_R) - 12.72 8653.80 v tile_prci_domain/tile_reset_domain/boom_tile/core/rename_stage/freelist/_38380_/Y (OAI21x1_ASAP7_75t_R) - 18.12 8671.91 v tile_prci_domain/tile_reset_domain/boom_tile/core/rename_stage/freelist/_38384_/Y (AO21x1_ASAP7_75t_R) - 0.01 8671.92 v tile_prci_domain/tile_reset_domain/boom_tile/core/rename_stage/freelist/_44863_/D (DFFHQNx2_ASAP7_75t_R) -``` - -This is a delay of 70 levels of logic yielding 3445.12ps. The fanout of a number of these levels are in the 10-20 range. - - -### oharboe -@precisionmoon FYI - -### maliberty -The reported clock skew from sta considers only ff that have a path between them. - diff --git a/gh_discussions/Runtime/4464.md b/gh_discussions/Runtime/4464.md deleted file mode 100644 index d03088257a76b16dd628f6c57f02ccc899d83a1c..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/4464.md +++ /dev/null @@ -1,37 +0,0 @@ -# Avoiding overallocation of CPU and memory for OpenROAD builds - -Subcategory: Resource management - -## Conversation - -### oharboe -I am running into problems with too many OpenROAD binaries running in parallel when using Bazel ORFS layer. - -I'm looking into whether I can get Bazel not to overuse CPUs in the system: https://groups.google.com/g/bazel-discuss/c/KVDcZ-EDfZw - -What other options are there? Surely this is not a new problem. What does other types of toolchains do? - -However, could and should OpenROAD be modified so that it communicates with other OpenROAD instances in the system and throttles usage to avoid overallocation of CPU and memory? - -Idea: - -- add new option to openroad `-limit ` -- this would cause openroad instances to communicate with eachother not to overallocate CPU and memory - -### maliberty -This seems to be more about job scheduling than OR. Usually a job scheduler will have some ability to specify the required resources for a job. OR itself will allow you to give a max number of threads if that's helpful. - -For example in [condor](https://htcondor.readthedocs.io/en/latest/users-manual/submitting-a-job.html): -``` -request_cpus = 1 -request_memory = 1024M -request_disk = 10240K -``` - -I don't think OR should try to solve this as you can run into the same issue between unrelated tools (yosys, klayout, or, etc). - -### oharboe -Turns out there is an infinite loop, probably, in DRC. I thought things ground to a halt because of CPU thrashing, but the detailed router might actually be stuck here. https://github.com/The-OpenROAD-Project/OpenROAD/issues/4466 - -If there is some performance degradation like 30-50% when running multiple detailed routing in parallel, that's tolerable. - diff --git a/gh_discussions/Runtime/4490.md b/gh_discussions/Runtime/4490.md deleted file mode 100644 index b8ccd55d2ee7b5d04ff77f27193bf7fd1770dfc3..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/4490.md +++ /dev/null @@ -1,499 +0,0 @@ -# Any thoughts on what to do to solve the global routing problems in MegaBoom? - -Tool: Global Routing - -Subcategory: Global routing congestion - -## Conversation - -### oharboe -I would like to get https://github.com/The-OpenROAD-Project/megaboom to the point where it goes through a full build and then incrementally improve. - -The idea with such big projects is to get the build under CI, separate concerns and continously improve... - -Currently it stops in global routing: - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/02068fde-3bb1-4ae7-a7b2-45f9a83db528) - -Current options for DigitalTop: - -https://github.com/The-OpenROAD-Project/megaboom/blob/391bbbd8d59b93b15b1cdb850294696a60d2dd4f/BUILD.bazel#L1636 - -- the yellow are hold cells. Given the 2000+ps skew in the clock tree, I don't find it shocking that there's ca. 100000 hold cells. I have set clock_latency to 3300, which I could try to change to 1000 to be closer to what is actually going on, but that still leaves 1000ps of clock skew on either side of that... There is the familiar hold cell log jam at the pins... -- there is a lot of congestion on top of the macro. What does that mean and how can it be fixed? -- reduce placement density? -- Increase number of global routing iterations from 30 to 100? - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/f32c23ae-cb26-4b40-a649-c47071f3a21b) - -If you want to have a look... - -1. Build OpenROAD https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/docs/user/BuildLocally.md -2. download. 1.3gByte. https://drive.google.com/file/d/1HcAU-pOsPvhcMGKdSWvy_mV17By0qH65/view?usp=sharing -3. untar -4. run: - -``` -$ . ~/OpenROAD-flow-scripts/env.sh -OPENROAD: /home/oyvind/OpenROAD-flow-scripts/tools/OpenROAD -$ ./run-me-DigitalTop-asap7-base.sh -``` - - - -### rovinski -Some miscellaneous thoughts: - -* The keep-out region around the macros seems higher than necessary. Can it be shrunk? -* Is there a way to push the macros all the way to the edges? If there are no pins on one side, then it should be fine to push it all the way to the edge. Right now, the gap between the macro and the edge is just wasted space. - -> ![image](https://private-user-images.githubusercontent.com/2798822/294173465-f32c23ae-cb26-4b40-a649-c47071f3a21b.png?jwt=eyJhbGciOiJIUzI1NiIsInR5cCI6IkpXVCJ9.eyJpc3MiOiJnaXRodWIuY29tIiwiYXVkIjoicmF3LmdpdGh1YnVzZXJjb250ZW50LmNvbSIsImtleSI6ImtleTUiLCJleHAiOjE3MDQzODc5MjUsIm5iZiI6MTcwNDM4NzYyNSwicGF0aCI6Ii8yNzk4ODIyLzI5NDE3MzQ2NS1mMzJjMjNhZS1jYjI2LTRiNDAtYTY0OS1jNDcwNzFmM2EyMWIucG5nP1gtQW16LUFsZ29yaXRobT1BV1M0LUhNQUMtU0hBMjU2JlgtQW16LUNyZWRlbnRpYWw9QUtJQVZDT0RZTFNBNTNQUUs0WkElMkYyMDI0MDEwNCUyRnVzLWVhc3QtMSUyRnMzJTJGYXdzNF9yZXF1ZXN0JlgtQW16LURhdGU9MjAyNDAxMDRUMTcwMDI1WiZYLUFtei1FeHBpcmVzPTMwMCZYLUFtei1TaWduYXR1cmU9NTc2NGJiMzAxYjU3ZmFkMzc3ZDk4OWExM2M2ZWY3NzhiOTdhMDJmMjc0N2MwZDllNzU0MzEyZDA0NzY5ZjI2ZiZYLUFtei1TaWduZWRIZWFkZXJzPWhvc3QmYWN0b3JfaWQ9MCZrZXlfaWQ9MCZyZXBvX2lkPTAifQ.1T6oUzQvPgbEHYZep6GOnSjXk8Xz7V07M8CsSou38jI) - -* I'm assuming the highlighted yellow are the hold cells? If so, it looks like they are feeding towards the I/Os. You should double check that your I/O constraints are in reference to the clock tree latency so that they are reasonable. For example, if the input constraint is 50ps, but the capture register has a 2000ps clock latency, then the tools need to insert 1950ps of hold buffers. If the output constraint is 50ps and the launch register clock latency is 2000ps, the best it could do is -1950ps slack. -* Do your large macros have the clock tree latency annotated in them when extracted? I believe that CTS support for this was added to help balancing, but I am not sure if the GUI or the skew report reflect this. If a macro and a register have 1000ps of skew, it could be totally fine if the macro has an internal clock tree of 1000ps. -* Even with that consideration, the clock tree looks very unbalanced. There might be something breaking down with the algorithm. - -### maliberty -I think resolve the clock skew will go a long way to resolving the other problems so let's start there. Even without insertion delay the tree is quite skewed. - -MACRO_PLACE_HALO="20 20" seems rather large. How did you pick those? - -### oharboe -Still cooking, but 100 global routing iterations + some fixes from the list above and only 6 violations. Lets see if it can push through... - -Many more things to test and tweak in the design, this is just intended to be a baseline. - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/9fc2d3e7-1d39-4615-b3ae-2a714bcb1f32) - - -### maliberty -In looking at auto_prci_ctrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock it goes into a user buffer prci_ctrl_domain/_1019_. I'm not clear why we would have a user buffer in the clock tree. Did you skip remove_buffers in floorplanning? - -### maliberty -How did you run cts? I see 75 instances named 'cklbuf*'. The clkbuf seem only related to a small area (showing only 'Clock tree' instances): -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/761514/4dfbc6d9-ab65-4b1a-8e4a-a1d3ed27c2dd) - -I see 7535 instances named 'load_slew*'. It seems most of the tree is not actually clock buffers: -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/761514/05340a29-8d33-42b8-a98b-9c65969a1d56) - - -### oharboe -@maliberty So it seems to me that outputting the clock from a module, so that you have the clock coming in with 0 insertion latency and the clock output with the clock tree leaf insertion latency would be useful to deal with a very large clock tree latency as follows: - -Create FIFOs on the outside that take the input clock for the module with large clock tree insertion latency as well as the output clock. Now you have two clock domains, use this FIFO to cross the two clock domain. The input/output pins of the module with large clock tree insertion latency can now have a clock latency constraints that is approximately equal to the clock tree insertion latency, which relaxes the constraints within the module. - -It is a bit annoying to set up that .sdc file, because you can't know the clock tree insertion latency until after you have run CTS, so a few iterations are probably needed... - - -### oharboe -Another datapoint, running times for this design (macros not included): - -``` -Log Elapsed seconds -1_1_yosys 2614 -1_1_yosys_hier_report 2518 -2_1_floorplan 186 -2_2_floorplan_io 6 -2_4_floorplan_macro 312 -2_5_floorplan_tapcell 108 -2_6_floorplan_pdn 234 -3_1_place_gp_skip_io 322 -3_2_place_iop 12 -3_3_place_gp 2904 -3_4_place_resized 590 -3_5_place_dp 683 -4_1_cts 5259 -``` - - -### maliberty -The cts runtime is likely mostly comprised of rsz runtime buffering that huge clock net. - -I haven't looked at the floorplan test case but I think I know what's going on. remove_buffers will not remove a buffer that is between a primary input and output (that would leave a pure feedthru which is a generally a bad thing). So it likely removes all the buffers but one as you have both in and out clock ports tied together. - -CTS sees the buffer and assumes you have a manually constructed tree and skips as shown above. - -This is not a methodology that OR supports. It seems a difficult one to do in general as you have no real idea what the skew requirement on the output pin should be. I don't understand chipyard or this design so I'm not sure what to suggest here. - -re "However, Yosys can't compile ChipTop, nor flatten the entire design(it would run forever), so I only build DigitalTop and hence we get clocks going out at the top level." Can you flatten just DigitalTop into ChipTop and not the whole design? - -### oharboe -@rovinski -> Bad logical designs can absolutely hamper physical design, and this is one example. It is taking away options from the algorithms and defecting to the user to make the proper decision, which is the opposite of what is wanted for automated design and design space exploration. -> -> I have done a decent amount of clock tree structuring for taped out chips, and this is simply a bad methodology except in very specific hand-tuned circumstances. It only works if you ensure the tree is manually balanced and the only reason to do it is to save clock power by reducing the branching factor and/or to reduce clock tree jitter for specific endpoints. - -Don't take my word for what MegaBoom is doing and not doing and why. I just have a default assumption that the authors knew what they were doing and did what they did the way they did for a reason... - -Since I know they are making a CPU, it makes sense to me(a default assumption until I learn more) that the memory master interface of that CPU is running on a different clock domain and that it is providing the clock which slave devices must use is an output. - -Or.... perhaps I'm not generating the Verilog in the right way...? The AXI output clock for the memory master interface might be there for the simulation test harness rather than synthesis? - -This Hammer file is for SonicBOOM (a smaller design than MegaBoom), it doesn't offer any clues as to what the AXI output clock means... - -https://github.com/ucb-bar/chipyard/blob/main/vlsi/example-designs/sky130-openroad.yml - -### oharboe -This is a screenshot from after global route of ChipTop.sv: - -- Standalone reproduction case for CTS in this case which includes the global routing result & congestion report: https://drive.google.com/file/d/1sAFbG_MpjmaN4inulYWUqbeuPsYLqx73/view?usp=sharing -- I was wrong that ChipTop.sv didn't go through synthesis with Yosys. I can't recall what problems I was having, though there are some simulation only .sv files that won't go through Yosys that are not used by ChipTop, perhaps I was confused by those? -- Only two global route failures indicated (white crosses) -- How can I tell if I have a clock tree? -- There are significant caveats still in that the macro abstracts are mocked: they only went through floorplan. I'll do a full build later. Still it is possible to learn something at this stage. -- clock_uncore_clock is fed through to axi4_mem_0_clock and the text says that it is clocked by clock_uncore_clock_vir, which makes sense. clock_uncore_clock_vir is clock_uncore_clock + source latency. - -``` -Startpoint: clock_uncore_clock (clock source 'clock_uncore_clock') -Endpoint: axi4_mem_0_clock (output port clocked by clock_uncore_clock_vir) -``` - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/abb63910-5d13-4ef2-b837-cb8060439fd1) - -There is a second clock into the design, but my guess is that this has something to do with a peripheral or other, not the CPU: - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/66e066a5-c2b6-4054-994c-7e02b7a74da1) - -``` -OpenROAD v2.0-11704-gfb0df7fb7 -This program is licensed under the BSD-3 license. See the LICENSE file for details. -Components of this program may be licensed under more restrictive licenses which must be honored. -[WARNING STA-0357] virtual clock clock_uncore_clock_vir can not be propagated. -Estimating parasitics -[WARNING GUI-0076] QXcbConnection: XCB error: 3 (BadWindow), sequence: 3175, resource id: 16788675, major code: 40 (TranslateCoords), minor code: 0 ->>> report_checks -path_delay max -fields {fanout skew} -Startpoint: reset_io (input port clocked by clock_uncore_clock_vir) -Endpoint: system/prci_ctrl_domain/_0952_ - (recovery check against rising-edge clock clock_uncore_clock) -Path Group: asynchronous -Path Type: max - -Fanout Delay Time Description ---------------------------------------------------------------- - 0.00 0.00 clock clock_uncore_clock_vir (rise edge) - 1000.00 1000.00 clock network delay (ideal) - 1700.00 2700.00 v input external delay - 1 0.00 2700.00 v reset_io (in) - 1 12.54 2712.54 v input87/Y (BUFx12f_ASAP7_75t_R) - 1 70.17 2782.71 v wire49778/Y (BUFx16f_ASAP7_75t_R) - 4 59.30 2842.00 ^ system/prci_ctrl_domain/_0722_/Y (INVx2_ASAP7_75t_R) - 0.53 2842.54 ^ system/prci_ctrl_domain/_0952_/SETN (DFFASRHQNx1_ASAP7_75t_R) - 2842.54 data arrival time - - 8500.00 8500.00 clock clock_uncore_clock (rise edge) - 871.54 9371.54 clock network delay (propagated) - -10.00 9361.54 clock uncertainty - 0.00 9361.54 clock reconvergence pessimism - 9361.54 ^ system/prci_ctrl_domain/_0952_/CLK (DFFASRHQNx1_ASAP7_75t_R) - 15.79 9377.33 library recovery time - 9377.33 data required time ---------------------------------------------------------------- - 9377.33 data required time - -2842.54 data arrival time ---------------------------------------------------------------- - 6534.79 slack (MET) - - -Startpoint: _32_ (negative level-sensitive latch clocked by clock_uncore_clock) -Endpoint: _10_ - (rising clock gating-check end-point clocked by clock_uncore_clock) -Path Group: gated clock -Path Type: max - -Fanout Delay Time Description ---------------------------------------------------------------- - 4250.00 4250.00 clock clock_uncore_clock (fall edge) - 532.14 4782.14 clock network delay (propagated) - 0.00 4782.14 v _32_/CLK (DLLx1_ASAP7_75t_R) - 1 45.86 4828.00 v _32_/Q (DLLx1_ASAP7_75t_R) - 0.02 4828.02 v _10_/B (AND2x4_ASAP7_75t_R) - 4828.02 data arrival time - - 8500.00 8500.00 clock clock_uncore_clock (rise edge) - 492.25 8992.25 clock network delay (propagated) - -10.00 8982.25 clock uncertainty - 0.00 8982.25 clock reconvergence pessimism - 8982.25 ^ _10_/A (AND2x4_ASAP7_75t_R) - 0.00 8982.25 clock gating setup time - 8982.25 data required time ---------------------------------------------------------------- - 8982.25 data required time - -4828.02 data arrival time ---------------------------------------------------------------- - 4154.23 slack (MET) - - -Startpoint: system/tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_095120_ - (rising edge-triggered flip-flop clocked by clock_uncore_clock) -Endpoint: system/tile_prci_domain/tile_reset_domain/boom_tile/core/fp_rename_stage/maptable/_80484_ - (rising edge-triggered flip-flop clocked by clock_uncore_clock) -Path Group: clock_uncore_clock -Path Type: max - -Fanout Delay Time Description ---------------------------------------------------------------- - 0.00 0.00 clock clock_uncore_clock (rise edge) - 1899.28 1899.28 clock network delay (propagated) - 0.00 1899.28 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_095120_/CLK (DFFHQNx2_ASAP7_75t_R) - 6 75.38 1974.65 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_095120_/QN (DFFHQNx2_ASAP7_75t_R) - 1 22.16 1996.82 ^ hold78251/Y (BUFx2_ASAP7_75t_R) - 3 20.28 2017.09 ^ hold24171/Y (BUFx2_ASAP7_75t_R) - 1 18.71 2035.80 ^ hold78252/Y (BUFx2_ASAP7_75t_R) - 6 44.43 2080.23 ^ hold14462/Y (BUFx2_ASAP7_75t_R) - 14 32.26 2112.50 v system/tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_052537_/Y (CKINVDCx20_ASAP7_75t_R) - 10 114.99 2227.49 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_095077_/CON (HAxp5_ASAP7_75t_R) - 4 27.96 2255.44 v system/tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_052831_/Y (INVx4_ASAP7_75t_R) - 2 30.15 2285.59 v system/tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_064284_/Y (AND2x2_ASAP7_75t_R) - 6 64.65 2350.24 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_095079_/CON (HAxp5_ASAP7_75t_R) - 6 43.78 2394.03 ^ wire30543/Y (BUFx12_ASAP7_75t_R) - 2 20.98 2415.01 v system/tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_052672_/Y (INVx11_ASAP7_75t_R) - 3 15.28 2430.28 v max_length29072/Y (BUFx12f_ASAP7_75t_R) - 3 32.78 2463.06 v max_length29071/Y (BUFx10_ASAP7_75t_R) - 13 69.31 2532.38 v system/tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_052686_/Y (OR4x2_ASAP7_75t_R) - 2 63.47 2595.85 v system/tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_052855_/Y (OR3x4_ASAP7_75t_R) - 2 43.49 2639.34 v system/tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_052856_/Y (AND3x4_ASAP7_75t_R) - 16 17.48 2656.82 v wire25227/Y (BUFx16f_ASAP7_75t_R) - 4 89.89 2746.71 v system/tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_052858_/Y (AND4x2_ASAP7_75t_R) - 1 21.42 2768.12 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/core/_09468_/Y (NAND2x2_ASAP7_75t_R) - 3 27.61 2795.74 ^ wire22599/Y (BUFx12f_ASAP7_75t_R) - 2 63.18 2858.92 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/core/_09478_/Y (OA21x2_ASAP7_75t_R) - 1 21.19 2880.10 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/core/_09481_/Y (OR3x4_ASAP7_75t_R) - 1 15.57 2895.67 ^ hold11148/Y (BUFx2_ASAP7_75t_R) - 1 15.93 2911.60 ^ hold8869/Y (BUFx2_ASAP7_75t_R) - 3 22.93 2934.53 ^ hold11149/Y (BUFx2_ASAP7_75t_R) - 5 33.02 2967.55 v system/tile_prci_domain/tile_reset_domain/boom_tile/core/_10524_/Y (NOR3x2_ASAP7_75t_R) - 2 32.14 2999.70 v wire20615/Y (BUFx16f_ASAP7_75t_R) - 19 76.62 3076.32 v wire20614/Y (BUFx16f_ASAP7_75t_R) - 30 123.33 3199.65 v wire20613/Y (BUFx16f_ASAP7_75t_R) - 16 26.25 3225.90 v wire20612/Y (BUFx16f_ASAP7_75t_R) - 1 60.57 3286.46 v system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_140035_/Y (AND3x1_ASAP7_75t_R) - 9 19.01 3305.47 v wire19271/Y (BUFx16f_ASAP7_75t_R) - 1 89.99 3395.47 v system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_140050_/Y (AND2x2_ASAP7_75t_R) - 7 36.72 3432.19 v system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_140051_/Y (AO21x2_ASAP7_75t_R) - 6 51.35 3483.53 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_140087_/Y (INVx13_ASAP7_75t_R) - 5 35.71 3519.24 ^ wire16755/Y (BUFx16f_ASAP7_75t_R) - 7 104.20 3623.44 v system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_267695_/CON (HAxp5_ASAP7_75t_R) - 5 26.52 3649.96 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_140053_/Y (INVx3_ASAP7_75t_R) - 2 31.74 3681.71 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_140060_/Y (AND3x1_ASAP7_75t_R) - 2 23.56 3705.27 v system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_267682_/CON (HAxp5_ASAP7_75t_R) - 2 24.40 3729.67 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_267682_/SN (HAxp5_ASAP7_75t_R) - 1 28.23 3757.89 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_149590_/Y (XNOR2x1_ASAP7_75t_R) - 1 43.36 3801.25 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_149594_/Y (AND5x2_ASAP7_75t_R) - 1 24.45 3825.70 ^ wire13571/Y (BUFx12f_ASAP7_75t_R) - 1 64.03 3889.73 ^ wire13570/Y (BUFx16f_ASAP7_75t_R) - 1 79.93 3969.66 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/core/_09472_/Y (AO221x2_ASAP7_75t_R) - 1 68.57 4038.23 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/core/_09473_/Y (OR5x2_ASAP7_75t_R) - 1 13.72 4051.94 ^ hold11977/Y (BUFx2_ASAP7_75t_R) - 1 12.26 4064.20 ^ hold7674/Y (BUFx2_ASAP7_75t_R) - 2 14.63 4078.84 ^ hold11978/Y (BUFx2_ASAP7_75t_R) - 1 15.72 4094.55 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/core/_09475_/Y (OA21x2_ASAP7_75t_R) - 2 20.63 4115.18 ^ hold7675/Y (BUFx2_ASAP7_75t_R) - 5 24.11 4139.29 v system/tile_prci_domain/tile_reset_domain/boom_tile/core/_10522_/Y (NOR3x2_ASAP7_75t_R) - 1 22.06 4161.35 v hold18417/Y (BUFx2_ASAP7_75t_R) - 1 12.68 4174.03 v hold10243/Y (BUFx2_ASAP7_75t_R) - 1 12.21 4186.24 v hold18418/Y (BUFx2_ASAP7_75t_R) - 2 20.53 4206.77 v hold7676/Y (BUFx2_ASAP7_75t_R) - 1 18.19 4224.96 v hold18419/Y (BUFx2_ASAP7_75t_R) - 1 12.59 4237.55 v hold10244/Y (BUFx2_ASAP7_75t_R) - 1 15.38 4252.93 v hold18420/Y (BUFx2_ASAP7_75t_R) - 2 13.31 4266.24 v load_slew12502/Y (BUFx12f_ASAP7_75t_R) - 1 15.05 4281.29 v hold18421/Y (BUFx2_ASAP7_75t_R) - 1 15.37 4296.67 v hold10245/Y (BUFx2_ASAP7_75t_R) - 1 15.35 4312.02 v hold18422/Y (BUFx2_ASAP7_75t_R) - 1 15.30 4327.32 v hold7677/Y (BUFx2_ASAP7_75t_R) - 1 15.27 4342.59 v hold18423/Y (BUFx2_ASAP7_75t_R) - 3 30.80 4373.39 v hold10246/Y (BUFx2_ASAP7_75t_R) - 3 35.71 4409.10 v max_length12501/Y (BUFx16f_ASAP7_75t_R) - 17 68.42 4477.52 v wire12498/Y (BUFx16f_ASAP7_75t_R) - 29 122.51 4600.04 v max_length12497/Y (BUFx16f_ASAP7_75t_R) - 18 24.10 4624.14 v max_length12496/Y (BUFx16f_ASAP7_75t_R) - 3 67.14 4691.28 v system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_140063_/Y (AND3x4_ASAP7_75t_R) - 10 59.39 4750.67 v max_length12300/Y (BUFx16f_ASAP7_75t_R) - 3 72.57 4823.25 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_140076_/Y (XNOR2x2_ASAP7_75t_R) - 9 20.37 4843.61 ^ load_slew11681/Y (BUFx16f_ASAP7_75t_R) - 5 23.34 4866.96 v system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_201351_/Y (CKINVDCx16_ASAP7_75t_R) - 3 45.17 4912.12 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_267727_/CON (HAxp5_ASAP7_75t_R) - 3 20.27 4932.39 v system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_140092_/Y (INVx2_ASAP7_75t_R) - 1 21.44 4953.83 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_267721_/CON (HAxp5_ASAP7_75t_R) - 2 16.81 4970.65 v system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_267668_/Y (INVx1_ASAP7_75t_R) - 2 57.58 5028.23 v system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_267723_/SN (HAxp5_ASAP7_75t_R) - 1 30.13 5058.35 v system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_149595_/Y (XNOR2x1_ASAP7_75t_R) - 1 35.26 5093.62 v system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_149601_/Y (AND5x2_ASAP7_75t_R) - 1 34.85 5128.46 v wire8234/Y (BUFx16f_ASAP7_75t_R) - 1 69.42 5197.89 v wire8233/Y (BUFx16f_ASAP7_75t_R) - 1 86.50 5284.38 v system/tile_prci_domain/tile_reset_domain/boom_tile/core/_09501_/Y (AO221x2_ASAP7_75t_R) - 1 64.90 5349.29 v system/tile_prci_domain/tile_reset_domain/boom_tile/core/_09502_/Y (OR4x2_ASAP7_75t_R) - 1 15.04 5364.33 v hold11691/Y (BUFx2_ASAP7_75t_R) - 1 12.71 5377.04 v hold8103/Y (BUFx2_ASAP7_75t_R) - 2 15.24 5392.28 v hold11692/Y (BUFx2_ASAP7_75t_R) - 1 8.30 5400.59 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/core/_09503_/Y (NOR2x1_ASAP7_75t_R) - 1 16.07 5416.66 ^ hold11693/Y (BUFx2_ASAP7_75t_R) - 1 11.98 5428.63 ^ hold8104/Y (BUFx2_ASAP7_75t_R) - 2 14.25 5442.89 ^ hold11694/Y (BUFx2_ASAP7_75t_R) - 6 33.66 5476.55 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/core/_13871_/Y (AND3x4_ASAP7_75t_R) - 1 19.94 5496.49 ^ hold17405/Y (BUFx2_ASAP7_75t_R) - 1 12.17 5508.66 ^ hold11980/Y (BUFx2_ASAP7_75t_R) - 1 11.81 5520.46 ^ hold17406/Y (BUFx2_ASAP7_75t_R) - 1 11.68 5532.14 ^ hold11695/Y (BUFx2_ASAP7_75t_R) - 1 11.84 5543.97 ^ hold11981/Y (BUFx2_ASAP7_75t_R) - 1 11.84 5555.81 ^ hold8105/Y (BUFx2_ASAP7_75t_R) - 1 11.69 5567.50 ^ hold11982/Y (BUFx2_ASAP7_75t_R) - 1 11.65 5579.15 ^ hold11696/Y (BUFx2_ASAP7_75t_R) - 1 14.92 5594.07 ^ hold11983/Y (BUFx2_ASAP7_75t_R) - 2 13.10 5607.17 ^ max_length7476/Y (BUFx12f_ASAP7_75t_R) - 1 16.07 5623.24 ^ hold11984/Y (BUFx2_ASAP7_75t_R) - 1 15.88 5639.12 ^ hold11697/Y (BUFx2_ASAP7_75t_R) - 1 15.95 5655.07 ^ hold11985/Y (BUFx2_ASAP7_75t_R) - 1 15.87 5670.94 ^ hold8106/Y (BUFx2_ASAP7_75t_R) - 1 15.89 5686.83 ^ hold11986/Y (BUFx2_ASAP7_75t_R) - 2 26.49 5713.32 ^ hold11698/Y (BUFx2_ASAP7_75t_R) - 2 26.12 5739.44 ^ hold11987/Y (BUFx2_ASAP7_75t_R) - 3 20.02 5759.46 ^ wire7475/Y (BUFx16f_ASAP7_75t_R) - 6 50.30 5809.76 ^ max_length7474/Y (BUFx12f_ASAP7_75t_R) - 2 66.91 5876.68 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_140099_/Y (AND2x2_ASAP7_75t_R) - 1 17.15 5893.83 v system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_140100_/Y (NAND2x2_ASAP7_75t_R) - 8 30.84 5924.67 v wire6776/Y (BUFx16f_ASAP7_75t_R) - 13 114.72 6039.39 v load_slew6775/Y (BUFx16f_ASAP7_75t_R) - 1 54.63 6094.02 v system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_146049_/Y (OR2x2_ASAP7_75t_R) - 7 41.21 6135.24 v system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_146050_/Y (OA21x2_ASAP7_75t_R) - 9 39.67 6174.90 v wire5396/Y (BUFx16f_ASAP7_75t_R) - 5 51.31 6226.22 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_267763_/CON (HAxp5_ASAP7_75t_R) - 5 17.32 6243.54 v system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_149526_/Y (INVx5_ASAP7_75t_R) - 1 56.08 6299.62 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_267765_/CON (HAxp5_ASAP7_75t_R) - 2 29.02 6328.63 v system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_267663_/Y (INVx1_ASAP7_75t_R) - 2 126.39 6455.02 v system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_267767_/SN (HAxp5_ASAP7_75t_R) - 1 54.46 6509.49 v system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_149603_/Y (XNOR2x1_ASAP7_75t_R) - 1 37.55 6547.04 v system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_149608_/Y (AND5x2_ASAP7_75t_R) - 1 37.85 6584.88 v wire4143/Y (BUFx16f_ASAP7_75t_R) - 1 69.84 6654.72 v wire4142/Y (BUFx16f_ASAP7_75t_R) - 1 84.81 6739.53 v system/tile_prci_domain/tile_reset_domain/boom_tile/core/_09493_/Y (AO221x2_ASAP7_75t_R) - 1 57.90 6797.43 v system/tile_prci_domain/tile_reset_domain/boom_tile/core/_09494_/Y (OR4x2_ASAP7_75t_R) - 1 14.94 6812.38 v hold30872/Y (BUFx2_ASAP7_75t_R) - 1 12.79 6825.17 v hold13130/Y (BUFx2_ASAP7_75t_R) - 2 14.65 6839.82 v hold30873/Y (BUFx2_ASAP7_75t_R) - 2 20.21 6860.03 v system/tile_prci_domain/tile_reset_domain/boom_tile/core/_09495_/Y (OR2x2_ASAP7_75t_R) - 1 14.23 6874.25 v hold30874/Y (BUFx2_ASAP7_75t_R) - 1 12.10 6886.36 v hold13131/Y (BUFx2_ASAP7_75t_R) - 1 12.38 6898.74 v hold30875/Y (BUFx2_ASAP7_75t_R) - 1 13.47 6912.20 v system/tile_prci_domain/tile_reset_domain/boom_tile/core/_09505_/Y (AO21x1_ASAP7_75t_R) - 1 12.83 6925.03 v hold30876/Y (BUFx2_ASAP7_75t_R) - 1 12.37 6937.40 v hold13132/Y (BUFx2_ASAP7_75t_R) - 1 15.35 6952.75 v hold30877/Y (BUFx2_ASAP7_75t_R) - 17 31.60 6984.35 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/core/_09506_/Y (NOR3x2_ASAP7_75t_R) - 1 22.33 7006.68 ^ hold32043/Y (BUFx2_ASAP7_75t_R) - 1 12.37 7019.06 ^ hold30878/Y (BUFx2_ASAP7_75t_R) - 4 22.96 7042.02 ^ hold13133/Y (BUFx2_ASAP7_75t_R) - 35 24.88 7066.90 ^ load_slew4133/Y (BUFx16f_ASAP7_75t_R) - 2 26.42 7093.32 ^ hold13134/Y (BUFx2_ASAP7_75t_R) - 5 31.12 7124.44 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/core/_13971_/Y (AND2x6_ASAP7_75t_R) - 2 27.47 7151.91 v system/tile_prci_domain/tile_reset_domain/boom_tile/core/fp_rename_stage/_3835_/Y (INVx2_ASAP7_75t_R) - 1 14.40 7166.30 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/core/fp_rename_stage/_5294_/Y (NOR2x2_ASAP7_75t_R) - 5 17.30 7183.60 ^ wire3988/Y (BUFx16f_ASAP7_75t_R) - 1 84.04 7267.64 ^ wire3987/Y (BUFx16f_ASAP7_75t_R) - 8 66.05 7333.69 ^ wire3986/Y (BUFx16f_ASAP7_75t_R) - 9 136.20 7469.90 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/core/fp_rename_stage/maptable/_52698_/Y (AND4x2_ASAP7_75t_R) - 6 60.97 7530.87 ^ wire3601/Y (BUFx16f_ASAP7_75t_R) - 10 86.11 7616.98 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/core/fp_rename_stage/maptable/_54157_/Y (AND2x6_ASAP7_75t_R) - 14 23.34 7640.32 ^ wire2977/Y (BUFx16f_ASAP7_75t_R) - 8 50.78 7691.10 ^ max_length2976/Y (BUFx12f_ASAP7_75t_R) - 16 39.60 7730.70 ^ max_length2975/Y (BUFx16f_ASAP7_75t_R) - 14 17.45 7748.16 ^ wire2974/Y (BUFx16f_ASAP7_75t_R) - 16 29.41 7777.57 ^ wire2973/Y (BUFx16f_ASAP7_75t_R) - 3 77.98 7855.55 ^ wire2972/Y (BUFx16f_ASAP7_75t_R) - 2 82.43 7937.98 v system/tile_prci_domain/tile_reset_domain/boom_tile/core/fp_rename_stage/maptable/_54165_/Y (NOR2x2_ASAP7_75t_R) - 10 30.56 7968.54 v max_length1585/Y (BUFx16f_ASAP7_75t_R) - 12 70.74 8039.28 v load_slew1584/Y (BUFx12f_ASAP7_75t_R) - 8 18.25 8057.53 v max_length1583/Y (BUFx12f_ASAP7_75t_R) - 11 46.63 8104.16 v load_slew1582/Y (BUFx16f_ASAP7_75t_R) - 12 55.12 8159.28 v wire1580/Y (BUFx16f_ASAP7_75t_R) - 12 57.79 8217.07 v max_length1579/Y (BUFx16f_ASAP7_75t_R) - 1 39.31 8256.38 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/core/fp_rename_stage/maptable/_54636_/Y (AOI221x1_ASAP7_75t_R) - 0.01 8256.39 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/core/fp_rename_stage/maptable/_80484_/D (DFFHQNx2_ASAP7_75t_R) - 8256.39 data arrival time - - 8500.00 8500.00 clock clock_uncore_clock (rise edge) - 380.41 8880.41 clock network delay (propagated) - -10.00 8870.41 clock uncertainty - 0.00 8870.41 clock reconvergence pessimism - 8870.41 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/core/fp_rename_stage/maptable/_80484_/CLK (DFFHQNx2_ASAP7_75t_R) - -5.21 8865.20 library setup time - 8865.20 data required time ---------------------------------------------------------------- - 8865.20 data required time - -8256.39 data arrival time ---------------------------------------------------------------- - 608.81 slack (MET) - - -Startpoint: clock_uncore_clock (clock source 'clock_uncore_clock') -Endpoint: axi4_mem_0_clock (output port clocked by clock_uncore_clock_vir) -Path Group: clock_uncore_clock_vir -Path Type: max - -Fanout Delay Time Description ---------------------------------------------------------------- - 4250.00 4250.00 clock clock_uncore_clock (fall edge) - 1775.06 6025.06 clock network delay - 6025.06 v axi4_mem_0_clock (out) - 6025.06 data arrival time - - 8500.00 8500.00 clock clock_uncore_clock_vir (rise edge) - 1000.00 9500.00 clock network delay (ideal) - -10.00 9490.00 clock uncertainty - 0.00 9490.00 clock reconvergence pessimism - -1700.00 7790.00 output external delay - 7790.00 data required time ---------------------------------------------------------------- - 7790.00 data required time - -6025.06 data arrival time ---------------------------------------------------------------- - 1764.93 slack (MET) - - -Startpoint: serial_tl_bits_out_ready - (input port clocked by clock_uncore_clock_vir) -Endpoint: system/subsystem_fbus/out_async/_1122_ - (rising edge-triggered flip-flop clocked by serial_tl_clock) -Path Group: serial_tl_clock -Path Type: max - -Fanout Delay Time Description ---------------------------------------------------------------- - 0.00 0.00 clock clock_uncore_clock_vir (rise edge) - 1000.00 1000.00 clock network delay (ideal) - 1700.00 2700.00 v input external delay - 1 0.00 2700.00 v serial_tl_bits_out_ready (in) - 1 11.42 2711.42 v input121/Y (BUFx2_ASAP7_75t_R) - 1 21.57 2733.00 v system/subsystem_fbus/out_async/_0655_/Y (AND2x6_ASAP7_75t_R) - 1 27.18 2760.18 ^ system/subsystem_fbus/out_async/_1119_/CON (HAxp5_ASAP7_75t_R) - 1 9.72 2769.90 v system/subsystem_fbus/out_async/_1118_/Y (INVx1_ASAP7_75t_R) - 1 13.58 2783.48 ^ system/subsystem_fbus/out_async/_1120_/CON (HAxp5_ASAP7_75t_R) - 1 8.76 2792.23 v system/subsystem_fbus/out_async/_1117_/Y (INVx1_ASAP7_75t_R) - 12 204.22 2996.46 v system/subsystem_fbus/out_async/_1121_/SN (HAxp5_ASAP7_75t_R) - 12 53.79 3050.25 v load_slew27103/Y (BUFx6f_ASAP7_75t_R) - 2 24.58 3074.83 v system/subsystem_fbus/out_async/_0587_/Y (XNOR2x1_ASAP7_75t_R) - 1 26.20 3101.02 v system/subsystem_fbus/out_async/_0588_/Y (OR3x1_ASAP7_75t_R) - 33 54.44 3155.46 v system/subsystem_fbus/out_async/_0593_/Y (AO22x2_ASAP7_75t_R) - 33 113.80 3269.27 ^ system/subsystem_fbus/out_async/_0594_/Y (NAND2x2_ASAP7_75t_R) - 1 46.55 3315.82 ^ system/subsystem_fbus/out_async/_0679_/Y (OA21x2_ASAP7_75t_R) - 0.02 3315.84 ^ system/subsystem_fbus/out_async/_1122_/D (DFFHQNx2_ASAP7_75t_R) - 3315.84 data arrival time - - 8500.00 8500.00 clock serial_tl_clock (rise edge) - 191.14 8691.14 clock network delay (propagated) - -10.00 8681.14 clock uncertainty - 0.00 8681.14 clock reconvergence pessimism - 8681.14 ^ system/subsystem_fbus/out_async/_1122_/CLK (DFFHQNx2_ASAP7_75t_R) - -5.07 8676.07 library setup time - 8676.07 data required time ---------------------------------------------------------------- - 8676.07 data required time - -3315.84 data arrival time ---------------------------------------------------------------- - 5360.23 slack (MET) -``` - - -### oharboe -I've posted a question to Chipyard: https://groups.google.com/g/chipyard/c/BXsafsGlhJ0 - diff --git a/gh_discussions/Runtime/4504.md b/gh_discussions/Runtime/4504.md deleted file mode 100644 index ed98ba918d1c316f808dcfa238f109f32d8e8a67..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/4504.md +++ /dev/null @@ -1,987 +0,0 @@ -# MegaBoom with clock tree - -Tool: Clock Tree Synthesis - -Subcategory: Clock tree issue - -## Conversation - -### oharboe -Looks much more reasonable now. There are H-clock trees after CTS. - -`make cts_issue`; CTS takes ca. 25000 seconds on my machine: https://drive.google.com/file/d/13eenpP2JgzXJD0uP3KIpX4QLArBVjzT2/view?usp=sharing - -This is apples and oranges comparision, but ... Minimum clock period is 5000ps, whereas I've seen claims on the order of 1000ps with commercial tools for the most similar design I know of to MegaBoom: https://carrv.github.io/2020/papers/CARRV2020_paper_15_Zhao.pdf - -``` ->>> report_clock_min_period -clock period_min = 5403.70 fmax = 185.06 -clock_vir period_min = 0.00 fmax = inf -fake_pll_clk period_min = 5403.70 fmax = 185.06 -serial_tl_0_clock period_min = 953.62 fmax = 1048.63 -``` - -Yellow are hold cells, very reasonable... Clock tree looks odd. Those leaf nodes on the right side are flip flops. It would be nice if there was some clear visual indication of macros vs. flip flop endpoints in the CTS view.... - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/5837af84-df29-4b34-adbe-c8f9b1a48e14) - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/6f0037fa-6c26-4904-88a0-e31fc5312cb0) - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/3d39c96e-5d49-4a5e-add6-6e6517d4ccf8) - - -``` -report_checks -path_delay max -fields {fanout skew} -Startpoint: reset (input port clocked by clock_vir) -Endpoint: system/prci_ctrl_domain/_3041_ - (recovery check against rising-edge clock fake_pll_clk) -Path Group: asynchronous -Path Type: max - -Fanout Delay Time Description ---------------------------------------------------------------- - 0.00 0.00 clock clock_vir (rise edge) - 1000.00 1000.00 clock network delay (ideal) - 1700.00 2700.00 v input external delay - 1 0.00 2700.00 v reset (in) - 1 10.58 2710.58 v hold4662/Y (BUFx2_ASAP7_75t_R) - 1 12.61 2723.18 v hold4387/Y (BUFx2_ASAP7_75t_R) - 1 12.49 2735.67 v hold4663/Y (BUFx2_ASAP7_75t_R) - 1 12.65 2748.32 v hold4335/Y (BUFx2_ASAP7_75t_R) - 1 12.65 2760.97 v hold4664/Y (BUFx2_ASAP7_75t_R) - 1 12.72 2773.69 v hold4388/Y (BUFx2_ASAP7_75t_R) - 1 12.81 2786.50 v hold4665/Y (BUFx2_ASAP7_75t_R) - 1 12.50 2799.00 v hold64/Y (BUFx2_ASAP7_75t_R) - 1 12.66 2811.66 v hold4666/Y (BUFx2_ASAP7_75t_R) - 1 12.66 2824.31 v hold4389/Y (BUFx2_ASAP7_75t_R) - 1 12.59 2836.91 v hold4667/Y (BUFx2_ASAP7_75t_R) - 1 12.71 2849.61 v hold4336/Y (BUFx2_ASAP7_75t_R) - 1 12.48 2862.09 v hold4668/Y (BUFx2_ASAP7_75t_R) - 1 12.39 2874.48 v hold4390/Y (BUFx2_ASAP7_75t_R) - 1 12.40 2886.88 v hold4669/Y (BUFx2_ASAP7_75t_R) - 1 12.34 2899.21 v hold56/Y (BUFx2_ASAP7_75t_R) - 1 12.32 2911.54 v hold4670/Y (BUFx2_ASAP7_75t_R) - 1 12.23 2923.77 v hold4391/Y (BUFx2_ASAP7_75t_R) - 1 12.45 2936.22 v hold4671/Y (BUFx2_ASAP7_75t_R) - 1 12.49 2948.71 v hold4337/Y (BUFx2_ASAP7_75t_R) - 1 12.35 2961.06 v hold4672/Y (BUFx2_ASAP7_75t_R) - 1 12.16 2973.22 v hold4392/Y (BUFx2_ASAP7_75t_R) - 1 12.26 2985.48 v hold4673/Y (BUFx2_ASAP7_75t_R) - 1 12.38 2997.87 v hold65/Y (BUFx2_ASAP7_75t_R) - 1 12.25 3010.12 v hold4674/Y (BUFx2_ASAP7_75t_R) - 1 12.19 3022.31 v hold4393/Y (BUFx2_ASAP7_75t_R) - 1 12.21 3034.52 v hold4675/Y (BUFx2_ASAP7_75t_R) - 1 12.21 3046.72 v hold4338/Y (BUFx2_ASAP7_75t_R) - 1 12.47 3059.19 v hold4676/Y (BUFx2_ASAP7_75t_R) - 1 12.59 3071.78 v hold4394/Y (BUFx2_ASAP7_75t_R) - 1 15.63 3087.41 v hold4677/Y (BUFx2_ASAP7_75t_R) - 1 18.70 3106.12 v input5/Y (BUFx24_ASAP7_75t_R) - 1 13.56 3119.68 v hold4678/Y (BUFx2_ASAP7_75t_R) - 1 14.47 3134.15 v hold4395/Y (BUFx2_ASAP7_75t_R) - 1 15.29 3149.44 v hold4339/Y (BUFx2_ASAP7_75t_R) - 1 15.29 3164.73 v hold4396/Y (BUFx2_ASAP7_75t_R) - 1 15.27 3180.00 v hold66/Y (BUFx2_ASAP7_75t_R) - 1 15.29 3195.29 v hold4397/Y (BUFx2_ASAP7_75t_R) - 1 15.25 3210.53 v hold4340/Y (BUFx2_ASAP7_75t_R) - 1 15.21 3225.74 v hold4398/Y (BUFx2_ASAP7_75t_R) - 1 15.29 3241.03 v hold57/Y (BUFx2_ASAP7_75t_R) - 1 15.30 3256.34 v hold4399/Y (BUFx2_ASAP7_75t_R) - 1 15.23 3271.56 v hold4341/Y (BUFx2_ASAP7_75t_R) - 1 15.26 3286.82 v hold4400/Y (BUFx2_ASAP7_75t_R) - 1 15.29 3302.12 v hold67/Y (BUFx2_ASAP7_75t_R) - 1 15.24 3317.35 v hold4401/Y (BUFx2_ASAP7_75t_R) - 1 15.20 3332.56 v hold4342/Y (BUFx2_ASAP7_75t_R) - 1 17.90 3350.46 v hold4402/Y (BUFx2_ASAP7_75t_R) - 1 16.93 3367.38 v wire96200/Y (BUFx16f_ASAP7_75t_R) - 1 14.22 3381.60 v hold4403/Y (BUFx2_ASAP7_75t_R) - 1 15.14 3396.75 v hold4343/Y (BUFx2_ASAP7_75t_R) - 1 15.26 3412.01 v hold4404/Y (BUFx2_ASAP7_75t_R) - 1 15.29 3427.30 v hold68/Y (BUFx2_ASAP7_75t_R) - 1 15.19 3442.49 v hold4405/Y (BUFx2_ASAP7_75t_R) - 1 15.21 3457.70 v hold4344/Y (BUFx2_ASAP7_75t_R) - 1 15.28 3472.98 v hold4406/Y (BUFx2_ASAP7_75t_R) - 1 15.24 3488.22 v hold58/Y (BUFx2_ASAP7_75t_R) - 1 15.18 3503.40 v hold4407/Y (BUFx2_ASAP7_75t_R) - 1 15.24 3518.64 v hold4345/Y (BUFx2_ASAP7_75t_R) - 1 15.23 3533.87 v hold4408/Y (BUFx2_ASAP7_75t_R) - 1 15.18 3549.06 v hold69/Y (BUFx2_ASAP7_75t_R) - 1 15.15 3564.21 v hold4409/Y (BUFx2_ASAP7_75t_R) - 1 15.13 3579.33 v hold4346/Y (BUFx2_ASAP7_75t_R) - 1 17.89 3597.22 v hold4410/Y (BUFx2_ASAP7_75t_R) - 1 16.94 3614.16 v wire96199/Y (BUFx16f_ASAP7_75t_R) - 1 14.34 3628.51 v hold4411/Y (BUFx2_ASAP7_75t_R) - 1 15.29 3643.80 v hold4347/Y (BUFx2_ASAP7_75t_R) - 1 15.28 3659.08 v hold4412/Y (BUFx2_ASAP7_75t_R) - 1 15.28 3674.36 v hold70/Y (BUFx2_ASAP7_75t_R) - 1 15.29 3689.65 v hold4413/Y (BUFx2_ASAP7_75t_R) - 1 15.29 3704.94 v hold4348/Y (BUFx2_ASAP7_75t_R) - 1 15.24 3720.18 v hold4414/Y (BUFx2_ASAP7_75t_R) - 1 15.31 3735.49 v hold59/Y (BUFx2_ASAP7_75t_R) - 1 15.33 3750.82 v hold4415/Y (BUFx2_ASAP7_75t_R) - 1 15.27 3766.08 v hold4349/Y (BUFx2_ASAP7_75t_R) - 1 15.24 3781.32 v hold4416/Y (BUFx2_ASAP7_75t_R) - 1 15.21 3796.53 v hold71/Y (BUFx2_ASAP7_75t_R) - 1 15.32 3811.85 v hold4417/Y (BUFx2_ASAP7_75t_R) - 1 15.36 3827.21 v hold4350/Y (BUFx2_ASAP7_75t_R) - 1 17.90 3845.10 v hold4418/Y (BUFx2_ASAP7_75t_R) - 1 16.84 3861.95 v wire96198/Y (BUFx16f_ASAP7_75t_R) - 1 14.33 3876.27 v hold4419/Y (BUFx2_ASAP7_75t_R) - 1 15.34 3891.61 v hold4351/Y (BUFx2_ASAP7_75t_R) - 1 15.31 3906.92 v hold4420/Y (BUFx2_ASAP7_75t_R) - 1 15.21 3922.13 v hold72/Y (BUFx2_ASAP7_75t_R) - 1 15.30 3937.43 v hold4421/Y (BUFx2_ASAP7_75t_R) - 1 15.29 3952.73 v hold4352/Y (BUFx2_ASAP7_75t_R) - 1 15.20 3967.93 v hold4422/Y (BUFx2_ASAP7_75t_R) - 1 15.33 3983.26 v hold60/Y (BUFx2_ASAP7_75t_R) - 1 15.31 3998.57 v hold4423/Y (BUFx2_ASAP7_75t_R) - 1 15.31 4013.88 v hold4353/Y (BUFx2_ASAP7_75t_R) - 1 15.28 4029.16 v hold4424/Y (BUFx2_ASAP7_75t_R) - 1 15.17 4044.33 v hold73/Y (BUFx2_ASAP7_75t_R) - 1 15.24 4059.57 v hold4425/Y (BUFx2_ASAP7_75t_R) - 1 15.37 4074.94 v hold4354/Y (BUFx2_ASAP7_75t_R) - 1 17.95 4092.90 v hold4426/Y (BUFx2_ASAP7_75t_R) - 1 16.85 4109.75 v wire96197/Y (BUFx16f_ASAP7_75t_R) - 1 14.32 4124.07 v hold4427/Y (BUFx2_ASAP7_75t_R) - 1 15.33 4139.40 v hold4355/Y (BUFx2_ASAP7_75t_R) - 1 15.37 4154.77 v hold4428/Y (BUFx2_ASAP7_75t_R) - 1 15.24 4170.01 v hold74/Y (BUFx2_ASAP7_75t_R) - 1 15.19 4185.20 v hold4429/Y (BUFx2_ASAP7_75t_R) - 1 15.26 4200.45 v hold4356/Y (BUFx2_ASAP7_75t_R) - 1 15.22 4215.67 v hold4430/Y (BUFx2_ASAP7_75t_R) - 1 15.31 4230.98 v hold61/Y (BUFx2_ASAP7_75t_R) - 1 15.27 4246.25 v hold4431/Y (BUFx2_ASAP7_75t_R) - 1 15.28 4261.53 v hold4357/Y (BUFx2_ASAP7_75t_R) - 1 15.33 4276.86 v hold4432/Y (BUFx2_ASAP7_75t_R) - 1 15.29 4292.15 v hold75/Y (BUFx2_ASAP7_75t_R) - 1 15.21 4307.35 v hold4433/Y (BUFx2_ASAP7_75t_R) - 1 15.23 4322.59 v hold4358/Y (BUFx2_ASAP7_75t_R) - 1 17.96 4340.55 v hold4434/Y (BUFx2_ASAP7_75t_R) - 1 20.57 4361.13 v wire96196/Y (BUFx24_ASAP7_75t_R) - 1 14.76 4375.89 v hold4435/Y (BUFx2_ASAP7_75t_R) - 1 15.31 4391.20 v hold4359/Y (BUFx2_ASAP7_75t_R) - 1 15.29 4406.49 v hold4436/Y (BUFx2_ASAP7_75t_R) - 1 15.27 4421.75 v hold76/Y (BUFx2_ASAP7_75t_R) - 1 15.27 4437.02 v hold4437/Y (BUFx2_ASAP7_75t_R) - 1 15.24 4452.26 v hold4360/Y (BUFx2_ASAP7_75t_R) - 1 15.26 4467.52 v hold4438/Y (BUFx2_ASAP7_75t_R) - 1 15.27 4482.79 v hold62/Y (BUFx2_ASAP7_75t_R) - 1 15.20 4497.99 v hold4439/Y (BUFx2_ASAP7_75t_R) - 1 15.18 4513.17 v hold4361/Y (BUFx2_ASAP7_75t_R) - 1 15.25 4528.42 v hold4440/Y (BUFx2_ASAP7_75t_R) - 1 15.24 4543.66 v hold77/Y (BUFx2_ASAP7_75t_R) - 1 15.22 4558.88 v hold4441/Y (BUFx2_ASAP7_75t_R) - 1 15.35 4574.23 v hold4362/Y (BUFx2_ASAP7_75t_R) - 1 22.85 4597.08 v hold4442/Y (BUFx2_ASAP7_75t_R) - 15 15.42 4612.50 ^ system/prci_ctrl_domain/_1567_/Y (INVx11_ASAP7_75t_R) - 2.22 4614.72 ^ system/prci_ctrl_domain/_3041_/SETN (DFFASRHQNx1_ASAP7_75t_R) - 4614.72 data arrival time - - 8500.00 8500.00 clock fake_pll_clk (rise edge) - 474.60 8974.60 clock network delay (propagated) - -10.00 8964.60 clock uncertainty - 0.00 8964.60 clock reconvergence pessimism - 8964.60 ^ system/prci_ctrl_domain/_3041_/CLK (DFFASRHQNx1_ASAP7_75t_R) - 4.83 8969.43 library recovery time - 8969.43 data required time ---------------------------------------------------------------- - 8969.43 data required time - -4614.72 data arrival time ---------------------------------------------------------------- - 4354.71 slack (MET) - - -Startpoint: system/prci_ctrl_domain/_2967_ - (rising edge-triggered flip-flop clocked by clock) -Endpoint: system/prci_ctrl_domain/_1576_ - (rising clock gating-check end-point clocked by fake_pll_clk) -Path Group: gated clock -Path Type: max - -Fanout Delay Time Description ---------------------------------------------------------------- - 0.00 0.00 clock clock (rise edge) - 983.66 983.66 clock network delay (propagated) - 0.00 983.66 ^ system/prci_ctrl_domain/_2967_/CLK (DFFASRHQNx1_ASAP7_75t_R) - 29 134.66 1118.32 v system/prci_ctrl_domain/_2967_/QN (DFFASRHQNx1_ASAP7_75t_R) - 1 41.06 1159.38 v hold6293/Y (BUFx2_ASAP7_75t_R) - 1 14.10 1173.47 v hold6165/Y (BUFx2_ASAP7_75t_R) - 1 12.29 1185.77 v hold6294/Y (BUFx2_ASAP7_75t_R) - 1 12.31 1198.07 v hold6101/Y (BUFx2_ASAP7_75t_R) - 1 12.29 1210.37 v hold6295/Y (BUFx2_ASAP7_75t_R) - 1 12.26 1222.63 v hold6166/Y (BUFx2_ASAP7_75t_R) - 1 12.25 1234.88 v hold6296/Y (BUFx2_ASAP7_75t_R) - 1 12.29 1247.17 v hold5379/Y (BUFx2_ASAP7_75t_R) - 1 12.23 1259.39 v hold6297/Y (BUFx2_ASAP7_75t_R) - 1 12.35 1271.74 v hold6167/Y (BUFx2_ASAP7_75t_R) - 1 12.36 1284.10 v hold6298/Y (BUFx2_ASAP7_75t_R) - 1 12.28 1296.38 v hold6102/Y (BUFx2_ASAP7_75t_R) - 1 12.26 1308.63 v hold6299/Y (BUFx2_ASAP7_75t_R) - 1 12.46 1321.09 v hold6168/Y (BUFx2_ASAP7_75t_R) - 1 12.73 1333.82 v hold6300/Y (BUFx2_ASAP7_75t_R) - 1 12.52 1346.34 v hold4926/Y (BUFx2_ASAP7_75t_R) - 1 12.20 1358.54 v hold6301/Y (BUFx2_ASAP7_75t_R) - 1 12.31 1370.85 v hold6169/Y (BUFx2_ASAP7_75t_R) - 1 12.27 1383.12 v hold6302/Y (BUFx2_ASAP7_75t_R) - 1 12.41 1395.53 v hold6103/Y (BUFx2_ASAP7_75t_R) - 1 12.73 1408.26 v hold6303/Y (BUFx2_ASAP7_75t_R) - 1 12.77 1421.03 v hold6170/Y (BUFx2_ASAP7_75t_R) - 1 12.69 1433.72 v hold6304/Y (BUFx2_ASAP7_75t_R) - 1 12.68 1446.40 v hold5380/Y (BUFx2_ASAP7_75t_R) - 1 12.80 1459.19 v hold6305/Y (BUFx2_ASAP7_75t_R) - 1 12.82 1472.02 v hold6171/Y (BUFx2_ASAP7_75t_R) - 1 12.57 1484.59 v hold6306/Y (BUFx2_ASAP7_75t_R) - 1 12.37 1496.96 v hold6104/Y (BUFx2_ASAP7_75t_R) - 1 12.26 1509.22 v hold6307/Y (BUFx2_ASAP7_75t_R) - 1 12.70 1521.92 v hold6172/Y (BUFx2_ASAP7_75t_R) - 1 12.82 1534.74 v hold6308/Y (BUFx2_ASAP7_75t_R) - 1 12.61 1547.36 v hold4681/Y (BUFx2_ASAP7_75t_R) - 1 12.39 1559.74 v hold6309/Y (BUFx2_ASAP7_75t_R) - 1 12.25 1572.00 v hold6173/Y (BUFx2_ASAP7_75t_R) - 1 12.30 1584.30 v hold6310/Y (BUFx2_ASAP7_75t_R) - 1 12.77 1597.06 v hold6105/Y (BUFx2_ASAP7_75t_R) - 1 12.51 1609.57 v hold6311/Y (BUFx2_ASAP7_75t_R) - 1 12.16 1621.73 v hold6174/Y (BUFx2_ASAP7_75t_R) - 1 12.80 1634.53 v hold6312/Y (BUFx2_ASAP7_75t_R) - 1 13.18 1647.71 v hold5381/Y (BUFx2_ASAP7_75t_R) - 1 13.15 1660.86 v hold6313/Y (BUFx2_ASAP7_75t_R) - 1 13.14 1674.00 v hold6175/Y (BUFx2_ASAP7_75t_R) - 1 13.11 1687.12 v hold6314/Y (BUFx2_ASAP7_75t_R) - 1 12.64 1699.76 v hold6106/Y (BUFx2_ASAP7_75t_R) - 1 12.21 1711.97 v hold6315/Y (BUFx2_ASAP7_75t_R) - 1 12.33 1724.29 v hold6176/Y (BUFx2_ASAP7_75t_R) - 1 13.02 1737.31 v hold6316/Y (BUFx2_ASAP7_75t_R) - 1 12.61 1749.93 v hold4927/Y (BUFx2_ASAP7_75t_R) - 1 12.77 1762.70 v hold6317/Y (BUFx2_ASAP7_75t_R) - 1 12.54 1775.24 v hold6177/Y (BUFx2_ASAP7_75t_R) - 1 12.73 1787.97 v hold6318/Y (BUFx2_ASAP7_75t_R) - 1 13.09 1801.06 v hold6107/Y (BUFx2_ASAP7_75t_R) - 1 13.16 1814.23 v hold6319/Y (BUFx2_ASAP7_75t_R) - 1 12.82 1827.04 v hold6178/Y (BUFx2_ASAP7_75t_R) - 1 12.89 1839.94 v hold6320/Y (BUFx2_ASAP7_75t_R) - 1 12.49 1852.42 v hold5382/Y (BUFx2_ASAP7_75t_R) - 1 12.64 1865.07 v hold6321/Y (BUFx2_ASAP7_75t_R) - 1 12.48 1877.55 v hold6179/Y (BUFx2_ASAP7_75t_R) - 1 12.30 1889.85 v hold6322/Y (BUFx2_ASAP7_75t_R) - 1 13.04 1902.89 v hold6108/Y (BUFx2_ASAP7_75t_R) - 1 13.16 1916.05 v hold6323/Y (BUFx2_ASAP7_75t_R) - 1 12.63 1928.68 v hold6180/Y (BUFx2_ASAP7_75t_R) - 1 12.66 1941.34 v hold6324/Y (BUFx2_ASAP7_75t_R) - 1 12.54 1953.88 v hold4532/Y (BUFx2_ASAP7_75t_R) - 1 12.28 1966.16 v hold6325/Y (BUFx2_ASAP7_75t_R) - 1 12.24 1978.40 v hold6181/Y (BUFx2_ASAP7_75t_R) - 1 12.20 1990.60 v hold6326/Y (BUFx2_ASAP7_75t_R) - 1 12.16 2002.76 v hold6109/Y (BUFx2_ASAP7_75t_R) - 1 12.10 2014.86 v hold6327/Y (BUFx2_ASAP7_75t_R) - 1 12.99 2027.85 v hold6182/Y (BUFx2_ASAP7_75t_R) - 1 12.77 2040.62 v hold6328/Y (BUFx2_ASAP7_75t_R) - 1 12.22 2052.84 v hold5383/Y (BUFx2_ASAP7_75t_R) - 1 12.31 2065.15 v hold6329/Y (BUFx2_ASAP7_75t_R) - 1 12.26 2077.41 v hold6183/Y (BUFx2_ASAP7_75t_R) - 1 12.30 2089.71 v hold6330/Y (BUFx2_ASAP7_75t_R) - 1 12.27 2101.98 v hold6110/Y (BUFx2_ASAP7_75t_R) - 1 12.33 2114.31 v hold6331/Y (BUFx2_ASAP7_75t_R) - 1 12.93 2127.24 v hold6184/Y (BUFx2_ASAP7_75t_R) - 1 12.67 2139.92 v hold6332/Y (BUFx2_ASAP7_75t_R) - 1 12.34 2152.26 v hold4928/Y (BUFx2_ASAP7_75t_R) - 1 12.52 2164.78 v hold6333/Y (BUFx2_ASAP7_75t_R) - 1 12.63 2177.41 v hold6185/Y (BUFx2_ASAP7_75t_R) - 1 12.58 2189.99 v hold6334/Y (BUFx2_ASAP7_75t_R) - 1 12.50 2202.48 v hold6111/Y (BUFx2_ASAP7_75t_R) - 1 12.76 2215.24 v hold6335/Y (BUFx2_ASAP7_75t_R) - 1 12.58 2227.82 v hold6186/Y (BUFx2_ASAP7_75t_R) - 1 13.00 2240.82 v hold6336/Y (BUFx2_ASAP7_75t_R) - 1 13.26 2254.08 v hold5384/Y (BUFx2_ASAP7_75t_R) - 1 13.10 2267.18 v hold6337/Y (BUFx2_ASAP7_75t_R) - 1 12.87 2280.06 v hold6187/Y (BUFx2_ASAP7_75t_R) - 1 12.40 2292.45 v hold6338/Y (BUFx2_ASAP7_75t_R) - 1 12.68 2305.14 v hold6112/Y (BUFx2_ASAP7_75t_R) - 1 13.17 2318.31 v hold6339/Y (BUFx2_ASAP7_75t_R) - 1 13.24 2331.55 v hold6188/Y (BUFx2_ASAP7_75t_R) - 1 12.95 2344.49 v hold6340/Y (BUFx2_ASAP7_75t_R) - 1 12.87 2357.37 v hold4682/Y (BUFx2_ASAP7_75t_R) - 1 13.08 2370.45 v hold6341/Y (BUFx2_ASAP7_75t_R) - 1 13.06 2383.51 v hold6189/Y (BUFx2_ASAP7_75t_R) - 1 12.44 2395.95 v hold6342/Y (BUFx2_ASAP7_75t_R) - 1 13.11 2409.06 v hold6113/Y (BUFx2_ASAP7_75t_R) - 1 13.52 2422.58 v hold6343/Y (BUFx2_ASAP7_75t_R) - 1 12.74 2435.33 v hold6190/Y (BUFx2_ASAP7_75t_R) - 1 13.02 2448.35 v hold6344/Y (BUFx2_ASAP7_75t_R) - 1 12.79 2461.14 v hold5385/Y (BUFx2_ASAP7_75t_R) - 1 12.31 2473.46 v hold6345/Y (BUFx2_ASAP7_75t_R) - 1 12.86 2486.32 v hold6191/Y (BUFx2_ASAP7_75t_R) - 1 13.72 2500.04 v hold6346/Y (BUFx2_ASAP7_75t_R) - 1 14.03 2514.08 v hold6114/Y (BUFx2_ASAP7_75t_R) - 1 13.71 2527.79 v hold6347/Y (BUFx2_ASAP7_75t_R) - 1 12.74 2540.53 v hold6192/Y (BUFx2_ASAP7_75t_R) - 1 12.77 2553.30 v hold6348/Y (BUFx2_ASAP7_75t_R) - 1 13.31 2566.61 v hold4929/Y (BUFx2_ASAP7_75t_R) - 1 13.47 2580.08 v hold6349/Y (BUFx2_ASAP7_75t_R) - 1 13.34 2593.42 v hold6193/Y (BUFx2_ASAP7_75t_R) - 1 13.42 2606.83 v hold6350/Y (BUFx2_ASAP7_75t_R) - 1 13.19 2620.02 v hold6115/Y (BUFx2_ASAP7_75t_R) - 1 12.63 2632.66 v hold6351/Y (BUFx2_ASAP7_75t_R) - 1 12.33 2644.99 v hold6194/Y (BUFx2_ASAP7_75t_R) - 1 12.72 2657.71 v hold6352/Y (BUFx2_ASAP7_75t_R) - 1 12.57 2670.28 v hold5386/Y (BUFx2_ASAP7_75t_R) - 1 12.49 2682.76 v hold6353/Y (BUFx2_ASAP7_75t_R) - 1 13.07 2695.84 v hold6195/Y (BUFx2_ASAP7_75t_R) - 1 13.42 2709.26 v hold6354/Y (BUFx2_ASAP7_75t_R) - 1 13.18 2722.44 v hold6116/Y (BUFx2_ASAP7_75t_R) - 1 12.61 2735.05 v hold6355/Y (BUFx2_ASAP7_75t_R) - 1 12.58 2747.62 v hold6196/Y (BUFx2_ASAP7_75t_R) - 1 12.33 2759.95 v hold6356/Y (BUFx2_ASAP7_75t_R) - 1 12.24 2772.19 v hold4317/Y (BUFx2_ASAP7_75t_R) - 1 13.23 2785.42 v hold6357/Y (BUFx2_ASAP7_75t_R) - 1 13.00 2798.42 v hold6197/Y (BUFx2_ASAP7_75t_R) - 1 12.88 2811.30 v hold6358/Y (BUFx2_ASAP7_75t_R) - 1 13.39 2824.69 v hold6117/Y (BUFx2_ASAP7_75t_R) - 1 13.02 2837.72 v hold6359/Y (BUFx2_ASAP7_75t_R) - 1 12.42 2850.13 v hold6198/Y (BUFx2_ASAP7_75t_R) - 1 12.99 2863.12 v hold6360/Y (BUFx2_ASAP7_75t_R) - 1 13.56 2876.68 v hold5387/Y (BUFx2_ASAP7_75t_R) - 1 12.89 2889.57 v hold6361/Y (BUFx2_ASAP7_75t_R) - 1 12.29 2901.86 v hold6199/Y (BUFx2_ASAP7_75t_R) - 1 13.09 2914.95 v hold6362/Y (BUFx2_ASAP7_75t_R) - 1 13.65 2928.60 v hold6118/Y (BUFx2_ASAP7_75t_R) - 1 14.02 2942.62 v hold6363/Y (BUFx2_ASAP7_75t_R) - 1 14.33 2956.95 v hold6200/Y (BUFx2_ASAP7_75t_R) - 1 14.03 2970.98 v hold6364/Y (BUFx2_ASAP7_75t_R) - 1 13.62 2984.61 v hold4930/Y (BUFx2_ASAP7_75t_R) - 1 13.56 2998.16 v hold6365/Y (BUFx2_ASAP7_75t_R) - 1 13.70 3011.86 v hold6201/Y (BUFx2_ASAP7_75t_R) - 1 13.86 3025.72 v hold6366/Y (BUFx2_ASAP7_75t_R) - 1 12.95 3038.67 v hold6119/Y (BUFx2_ASAP7_75t_R) - 1 12.52 3051.19 v hold6367/Y (BUFx2_ASAP7_75t_R) - 1 12.61 3063.79 v hold6202/Y (BUFx2_ASAP7_75t_R) - 1 12.90 3076.69 v hold6368/Y (BUFx2_ASAP7_75t_R) - 1 12.52 3089.21 v hold5388/Y (BUFx2_ASAP7_75t_R) - 1 12.63 3101.85 v hold6369/Y (BUFx2_ASAP7_75t_R) - 1 13.31 3115.16 v hold6203/Y (BUFx2_ASAP7_75t_R) - 1 12.79 3127.95 v hold6370/Y (BUFx2_ASAP7_75t_R) - 1 13.18 3141.13 v hold6120/Y (BUFx2_ASAP7_75t_R) - 1 13.51 3154.64 v hold6371/Y (BUFx2_ASAP7_75t_R) - 1 12.84 3167.48 v hold6204/Y (BUFx2_ASAP7_75t_R) - 1 12.30 3179.78 v hold6372/Y (BUFx2_ASAP7_75t_R) - 1 12.56 3192.33 v hold4683/Y (BUFx2_ASAP7_75t_R) - 1 13.37 3205.71 v hold6373/Y (BUFx2_ASAP7_75t_R) - 1 12.88 3218.58 v hold6205/Y (BUFx2_ASAP7_75t_R) - 1 13.30 3231.89 v hold6374/Y (BUFx2_ASAP7_75t_R) - 1 13.23 3245.11 v hold6121/Y (BUFx2_ASAP7_75t_R) - 1 12.90 3258.02 v hold6375/Y (BUFx2_ASAP7_75t_R) - 1 12.57 3270.59 v hold6206/Y (BUFx2_ASAP7_75t_R) - 1 12.22 3282.80 v hold6376/Y (BUFx2_ASAP7_75t_R) - 1 12.93 3295.74 v hold5389/Y (BUFx2_ASAP7_75t_R) - 1 12.63 3308.36 v hold6377/Y (BUFx2_ASAP7_75t_R) - 1 13.22 3321.59 v hold6207/Y (BUFx2_ASAP7_75t_R) - 1 13.04 3334.63 v hold6378/Y (BUFx2_ASAP7_75t_R) - 1 13.57 3348.20 v hold6122/Y (BUFx2_ASAP7_75t_R) - 1 13.15 3361.35 v hold6379/Y (BUFx2_ASAP7_75t_R) - 1 13.45 3374.80 v hold6208/Y (BUFx2_ASAP7_75t_R) - 1 13.14 3387.94 v hold6380/Y (BUFx2_ASAP7_75t_R) - 1 12.35 3400.29 v hold4931/Y (BUFx2_ASAP7_75t_R) - 1 12.88 3413.17 v hold6381/Y (BUFx2_ASAP7_75t_R) - 1 12.98 3426.15 v hold6209/Y (BUFx2_ASAP7_75t_R) - 1 12.53 3438.68 v hold6382/Y (BUFx2_ASAP7_75t_R) - 1 12.92 3451.60 v hold6123/Y (BUFx2_ASAP7_75t_R) - 1 13.50 3465.10 v hold6383/Y (BUFx2_ASAP7_75t_R) - 1 12.85 3477.95 v hold6210/Y (BUFx2_ASAP7_75t_R) - 1 12.95 3490.90 v hold6384/Y (BUFx2_ASAP7_75t_R) - 1 13.25 3504.15 v hold5390/Y (BUFx2_ASAP7_75t_R) - 1 12.53 3516.69 v hold6385/Y (BUFx2_ASAP7_75t_R) - 1 12.35 3529.04 v hold6211/Y (BUFx2_ASAP7_75t_R) - 1 13.55 3542.59 v hold6386/Y (BUFx2_ASAP7_75t_R) - 1 13.29 3555.88 v hold6124/Y (BUFx2_ASAP7_75t_R) - 1 12.40 3568.28 v hold6387/Y (BUFx2_ASAP7_75t_R) - 1 13.06 3581.34 v hold6212/Y (BUFx2_ASAP7_75t_R) - 1 12.90 3594.24 v hold6388/Y (BUFx2_ASAP7_75t_R) - 1 12.66 3606.90 v hold4533/Y (BUFx2_ASAP7_75t_R) - 1 12.85 3619.75 v hold6389/Y (BUFx2_ASAP7_75t_R) - 1 12.50 3632.25 v hold6213/Y (BUFx2_ASAP7_75t_R) - 1 12.53 3644.78 v hold6390/Y (BUFx2_ASAP7_75t_R) - 1 12.88 3657.66 v hold6125/Y (BUFx2_ASAP7_75t_R) - 1 13.42 3671.08 v hold6391/Y (BUFx2_ASAP7_75t_R) - 1 12.85 3683.93 v hold6214/Y (BUFx2_ASAP7_75t_R) - 1 12.78 3696.70 v hold6392/Y (BUFx2_ASAP7_75t_R) - 1 13.18 3709.88 v hold5391/Y (BUFx2_ASAP7_75t_R) - 1 13.83 3723.71 v hold6393/Y (BUFx2_ASAP7_75t_R) - 1 14.31 3738.02 v hold6215/Y (BUFx2_ASAP7_75t_R) - 1 13.03 3751.05 v hold6394/Y (BUFx2_ASAP7_75t_R) - 1 13.15 3764.20 v hold6126/Y (BUFx2_ASAP7_75t_R) - 1 13.54 3777.74 v hold6216/Y (BUFx2_ASAP7_75t_R) - 1 13.35 3791.09 v hold4932/Y (BUFx2_ASAP7_75t_R) - 1 12.76 3803.85 v hold6217/Y (BUFx2_ASAP7_75t_R) - 1 12.29 3816.14 v hold6127/Y (BUFx2_ASAP7_75t_R) - 1 12.26 3828.40 v hold6218/Y (BUFx2_ASAP7_75t_R) - 1 12.61 3841.01 v hold5392/Y (BUFx2_ASAP7_75t_R) - 1 12.96 3853.97 v hold6219/Y (BUFx2_ASAP7_75t_R) - 1 12.73 3866.70 v hold6128/Y (BUFx2_ASAP7_75t_R) - 1 12.69 3879.39 v hold6220/Y (BUFx2_ASAP7_75t_R) - 1 12.46 3891.85 v hold4684/Y (BUFx2_ASAP7_75t_R) - 1 12.43 3904.28 v hold6221/Y (BUFx2_ASAP7_75t_R) - 1 12.24 3916.52 v hold6129/Y (BUFx2_ASAP7_75t_R) - 1 12.46 3928.99 v hold6222/Y (BUFx2_ASAP7_75t_R) - 1 12.54 3941.53 v hold5393/Y (BUFx2_ASAP7_75t_R) - 1 12.28 3953.81 v hold6223/Y (BUFx2_ASAP7_75t_R) - 1 12.93 3966.75 v hold6130/Y (BUFx2_ASAP7_75t_R) - 1 14.08 3980.82 v hold6224/Y (BUFx2_ASAP7_75t_R) - 1 14.56 3995.38 v hold4933/Y (BUFx2_ASAP7_75t_R) - 1 13.17 4008.56 v hold6225/Y (BUFx2_ASAP7_75t_R) - 1 12.25 4020.80 v hold6131/Y (BUFx2_ASAP7_75t_R) - 1 13.36 4034.16 v hold6226/Y (BUFx2_ASAP7_75t_R) - 1 12.93 4047.10 v hold5394/Y (BUFx2_ASAP7_75t_R) - 1 12.47 4059.57 v hold6227/Y (BUFx2_ASAP7_75t_R) - 1 12.61 4072.18 v hold6132/Y (BUFx2_ASAP7_75t_R) - 1 12.43 4084.61 v hold6228/Y (BUFx2_ASAP7_75t_R) - 1 12.41 4097.02 v hold55/Y (BUFx2_ASAP7_75t_R) - 1 12.59 4109.60 v hold6229/Y (BUFx2_ASAP7_75t_R) - 1 12.92 4122.52 v hold6133/Y (BUFx2_ASAP7_75t_R) - 1 12.95 4135.47 v hold6230/Y (BUFx2_ASAP7_75t_R) - 1 12.91 4148.38 v hold5395/Y (BUFx2_ASAP7_75t_R) - 1 13.30 4161.68 v hold6231/Y (BUFx2_ASAP7_75t_R) - 1 13.06 4174.74 v hold6134/Y (BUFx2_ASAP7_75t_R) - 1 13.38 4188.13 v hold6232/Y (BUFx2_ASAP7_75t_R) - 1 12.81 4200.93 v hold4934/Y (BUFx2_ASAP7_75t_R) - 1 12.26 4213.19 v hold6233/Y (BUFx2_ASAP7_75t_R) - 1 12.33 4225.52 v hold6135/Y (BUFx2_ASAP7_75t_R) - 1 12.53 4238.05 v hold6234/Y (BUFx2_ASAP7_75t_R) - 1 12.39 4250.45 v hold5396/Y (BUFx2_ASAP7_75t_R) - 1 12.20 4262.65 v hold6235/Y (BUFx2_ASAP7_75t_R) - 1 12.24 4274.89 v hold6136/Y (BUFx2_ASAP7_75t_R) - 1 12.60 4287.49 v hold6236/Y (BUFx2_ASAP7_75t_R) - 1 12.72 4300.21 v hold4685/Y (BUFx2_ASAP7_75t_R) - 1 13.12 4313.32 v hold6237/Y (BUFx2_ASAP7_75t_R) - 1 13.48 4326.80 v hold6137/Y (BUFx2_ASAP7_75t_R) - 1 13.50 4340.29 v hold6238/Y (BUFx2_ASAP7_75t_R) - 1 12.69 4352.98 v hold5397/Y (BUFx2_ASAP7_75t_R) - 1 12.85 4365.83 v hold6239/Y (BUFx2_ASAP7_75t_R) - 1 13.29 4379.13 v hold6138/Y (BUFx2_ASAP7_75t_R) - 1 12.71 4391.84 v hold6240/Y (BUFx2_ASAP7_75t_R) - 1 12.26 4404.10 v hold4935/Y (BUFx2_ASAP7_75t_R) - 1 12.25 4416.35 v hold6241/Y (BUFx2_ASAP7_75t_R) - 1 12.19 4428.54 v hold6139/Y (BUFx2_ASAP7_75t_R) - 1 13.16 4441.69 v hold6242/Y (BUFx2_ASAP7_75t_R) - 1 13.98 4455.68 v hold5398/Y (BUFx2_ASAP7_75t_R) - 1 13.93 4469.61 v hold6243/Y (BUFx2_ASAP7_75t_R) - 1 12.80 4482.41 v hold6140/Y (BUFx2_ASAP7_75t_R) - 1 13.14 4495.55 v hold6244/Y (BUFx2_ASAP7_75t_R) - 1 13.52 4509.07 v hold4534/Y (BUFx2_ASAP7_75t_R) - 1 12.57 4521.64 v hold6245/Y (BUFx2_ASAP7_75t_R) - 1 12.23 4533.86 v hold6141/Y (BUFx2_ASAP7_75t_R) - 1 12.52 4546.38 v hold6246/Y (BUFx2_ASAP7_75t_R) - 1 12.67 4559.05 v hold5399/Y (BUFx2_ASAP7_75t_R) - 1 12.70 4571.76 v hold6247/Y (BUFx2_ASAP7_75t_R) - 1 12.39 4584.15 v hold6142/Y (BUFx2_ASAP7_75t_R) - 1 13.20 4597.34 v hold6248/Y (BUFx2_ASAP7_75t_R) - 1 12.86 4610.20 v hold4936/Y (BUFx2_ASAP7_75t_R) - 1 12.20 4622.40 v hold6249/Y (BUFx2_ASAP7_75t_R) - 1 12.49 4634.89 v hold6143/Y (BUFx2_ASAP7_75t_R) - 1 12.36 4647.24 v hold6250/Y (BUFx2_ASAP7_75t_R) - 1 12.34 4659.58 v hold5400/Y (BUFx2_ASAP7_75t_R) - 1 12.43 4672.01 v hold6251/Y (BUFx2_ASAP7_75t_R) - 1 12.28 4684.29 v hold6144/Y (BUFx2_ASAP7_75t_R) - 1 13.40 4697.68 v hold6252/Y (BUFx2_ASAP7_75t_R) - 1 12.97 4710.66 v hold4686/Y (BUFx2_ASAP7_75t_R) - 1 13.25 4723.91 v hold6253/Y (BUFx2_ASAP7_75t_R) - 1 13.75 4737.67 v hold6145/Y (BUFx2_ASAP7_75t_R) - 1 12.94 4750.60 v hold6254/Y (BUFx2_ASAP7_75t_R) - 1 12.31 4762.91 v hold5401/Y (BUFx2_ASAP7_75t_R) - 1 12.14 4775.05 v hold6255/Y (BUFx2_ASAP7_75t_R) - 1 12.37 4787.42 v hold6146/Y (BUFx2_ASAP7_75t_R) - 1 12.57 4799.99 v hold6256/Y (BUFx2_ASAP7_75t_R) - 1 12.98 4812.96 v hold4937/Y (BUFx2_ASAP7_75t_R) - 1 12.65 4825.62 v hold6257/Y (BUFx2_ASAP7_75t_R) - 1 13.30 4838.91 v hold6147/Y (BUFx2_ASAP7_75t_R) - 1 13.89 4852.81 v hold6258/Y (BUFx2_ASAP7_75t_R) - 1 13.08 4865.89 v hold5402/Y (BUFx2_ASAP7_75t_R) - 1 12.39 4878.28 v hold6259/Y (BUFx2_ASAP7_75t_R) - 1 12.81 4891.10 v hold6148/Y (BUFx2_ASAP7_75t_R) - 1 12.84 4903.94 v hold6260/Y (BUFx2_ASAP7_75t_R) - 1 12.36 4916.29 v hold4318/Y (BUFx2_ASAP7_75t_R) - 1 12.23 4928.52 v hold6261/Y (BUFx2_ASAP7_75t_R) - 1 13.05 4941.57 v hold6149/Y (BUFx2_ASAP7_75t_R) - 1 13.76 4955.33 v hold6262/Y (BUFx2_ASAP7_75t_R) - 1 13.92 4969.26 v hold5403/Y (BUFx2_ASAP7_75t_R) - 1 13.94 4983.20 v hold6263/Y (BUFx2_ASAP7_75t_R) - 1 12.94 4996.14 v hold6150/Y (BUFx2_ASAP7_75t_R) - 1 12.27 5008.41 v hold6264/Y (BUFx2_ASAP7_75t_R) - 1 13.32 5021.72 v hold4938/Y (BUFx2_ASAP7_75t_R) - 1 13.09 5034.82 v hold6265/Y (BUFx2_ASAP7_75t_R) - 1 12.31 5047.13 v hold6151/Y (BUFx2_ASAP7_75t_R) - 1 13.24 5060.37 v hold6266/Y (BUFx2_ASAP7_75t_R) - 1 13.45 5073.81 v hold5404/Y (BUFx2_ASAP7_75t_R) - 1 13.32 5087.13 v hold6267/Y (BUFx2_ASAP7_75t_R) - 1 13.48 5100.61 v hold6152/Y (BUFx2_ASAP7_75t_R) - 1 13.47 5114.08 v hold6268/Y (BUFx2_ASAP7_75t_R) - 1 13.50 5127.58 v hold4687/Y (BUFx2_ASAP7_75t_R) - 1 13.76 5141.34 v hold6269/Y (BUFx2_ASAP7_75t_R) - 1 13.92 5155.26 v hold6153/Y (BUFx2_ASAP7_75t_R) - 1 12.90 5168.17 v hold6270/Y (BUFx2_ASAP7_75t_R) - 1 13.02 5181.19 v hold5405/Y (BUFx2_ASAP7_75t_R) - 1 12.68 5193.87 v hold6271/Y (BUFx2_ASAP7_75t_R) - 1 12.33 5206.20 v hold6154/Y (BUFx2_ASAP7_75t_R) - 1 12.82 5219.02 v hold6272/Y (BUFx2_ASAP7_75t_R) - 1 13.08 5232.10 v hold4939/Y (BUFx2_ASAP7_75t_R) - 1 12.63 5244.73 v hold6273/Y (BUFx2_ASAP7_75t_R) - 1 12.49 5257.22 v hold6155/Y (BUFx2_ASAP7_75t_R) - 1 12.94 5270.15 v hold6274/Y (BUFx2_ASAP7_75t_R) - 1 12.64 5282.79 v hold5406/Y (BUFx2_ASAP7_75t_R) - 1 12.62 5295.42 v hold6275/Y (BUFx2_ASAP7_75t_R) - 1 12.66 5308.07 v hold6156/Y (BUFx2_ASAP7_75t_R) - 1 12.73 5320.81 v hold6276/Y (BUFx2_ASAP7_75t_R) - 1 13.22 5334.03 v hold4535/Y (BUFx2_ASAP7_75t_R) - 1 13.47 5347.49 v hold6277/Y (BUFx2_ASAP7_75t_R) - 1 12.64 5360.13 v hold6157/Y (BUFx2_ASAP7_75t_R) - 1 12.46 5372.59 v hold6278/Y (BUFx2_ASAP7_75t_R) - 1 12.60 5385.19 v hold5407/Y (BUFx2_ASAP7_75t_R) - 1 12.39 5397.58 v hold6279/Y (BUFx2_ASAP7_75t_R) - 1 12.30 5409.88 v hold6158/Y (BUFx2_ASAP7_75t_R) - 1 12.46 5422.34 v hold6280/Y (BUFx2_ASAP7_75t_R) - 1 12.32 5434.65 v hold4940/Y (BUFx2_ASAP7_75t_R) - 1 12.14 5446.79 v hold6281/Y (BUFx2_ASAP7_75t_R) - 1 12.39 5459.18 v hold6159/Y (BUFx2_ASAP7_75t_R) - 1 12.48 5471.66 v hold6282/Y (BUFx2_ASAP7_75t_R) - 1 13.29 5484.95 v hold5408/Y (BUFx2_ASAP7_75t_R) - 1 13.66 5498.61 v hold6283/Y (BUFx2_ASAP7_75t_R) - 1 12.76 5511.37 v hold6160/Y (BUFx2_ASAP7_75t_R) - 1 12.90 5524.28 v hold6284/Y (BUFx2_ASAP7_75t_R) - 1 12.92 5537.19 v hold4688/Y (BUFx2_ASAP7_75t_R) - 1 12.60 5549.79 v hold6285/Y (BUFx2_ASAP7_75t_R) - 1 12.30 5562.09 v hold6161/Y (BUFx2_ASAP7_75t_R) - 1 12.50 5574.59 v hold6286/Y (BUFx2_ASAP7_75t_R) - 1 12.39 5586.98 v hold5409/Y (BUFx2_ASAP7_75t_R) - 1 12.57 5599.54 v hold6287/Y (BUFx2_ASAP7_75t_R) - 1 12.79 5612.33 v hold6162/Y (BUFx2_ASAP7_75t_R) - 1 12.72 5625.05 v hold6288/Y (BUFx2_ASAP7_75t_R) - 1 12.32 5637.37 v hold4941/Y (BUFx2_ASAP7_75t_R) - 1 12.26 5649.62 v hold6289/Y (BUFx2_ASAP7_75t_R) - 1 12.30 5661.93 v hold6163/Y (BUFx2_ASAP7_75t_R) - 1 12.76 5674.69 v hold6290/Y (BUFx2_ASAP7_75t_R) - 1 12.90 5687.59 v hold5410/Y (BUFx2_ASAP7_75t_R) - 1 12.56 5700.14 v hold6291/Y (BUFx2_ASAP7_75t_R) - 1 12.33 5712.48 v hold6164/Y (BUFx2_ASAP7_75t_R) - 1 12.32 5724.80 v hold6292/Y (BUFx2_ASAP7_75t_R) - 0.02 5724.82 v system/prci_ctrl_domain/_1576_/A (AND2x2_ASAP7_75t_R) - 5724.82 data arrival time - - 8500.00 8500.00 clock fake_pll_clk (rise edge) - 898.15 9398.15 clock network delay (propagated) - -10.00 9388.15 clock uncertainty - 0.00 9388.15 clock reconvergence pessimism - 9388.15 ^ system/prci_ctrl_domain/_1576_/B (AND2x2_ASAP7_75t_R) - 0.00 9388.15 clock gating setup time - 9388.15 data required time ---------------------------------------------------------------- - 9388.15 data required time - -5724.82 data arrival time ---------------------------------------------------------------- - 3663.32 slack (MET) - - -Startpoint: system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_100801_ - (rising edge-triggered flip-flop clocked by clock) -Endpoint: system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_3405_ - (rising edge-triggered flip-flop clocked by clock) -Path Group: clock -Path Type: max - -Fanout Delay Time Description ---------------------------------------------------------------- - 0.00 0.00 clock clock (rise edge) - 1459.67 1459.67 clock network delay (propagated) - 0.00 1459.67 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_100801_/CLK (DFFHQNx2_ASAP7_75t_R) - 16 87.80 1547.47 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_100801_/QN (DFFHQNx2_ASAP7_75t_R) - 8 25.27 1572.74 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_055753_/Y (INVx13_ASAP7_75t_R) - 3 21.71 1594.45 v max_length80840/Y (BUFx12f_ASAP7_75t_R) - 10 106.10 1700.55 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_100755_/CON (HAxp5_ASAP7_75t_R) - 5 38.99 1739.54 ^ load_slew77788/Y (BUFx12f_ASAP7_75t_R) - 6 18.39 1757.93 ^ load_slew77787/Y (BUFx12f_ASAP7_75t_R) - 24 74.82 1832.75 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_055925_/Y (OR4x2_ASAP7_75t_R) - 1 52.70 1885.46 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_055926_/Y (OA22x2_ASAP7_75t_R) - 1 32.11 1917.56 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_055940_/Y (AND5x1_ASAP7_75t_R) - 4 40.36 1957.93 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_055972_/Y (AND4x2_ASAP7_75t_R) - 21 41.38 1999.31 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_055973_/Y (NAND2x2_ASAP7_75t_R) - 3 92.34 2091.65 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_056022_/Y (OR3x4_ASAP7_75t_R) - 4 34.23 2125.88 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_056088_/Y (NOR3x2_ASAP7_75t_R) - 1 82.97 2208.86 ^ wire54325/Y (BUFx16f_ASAP7_75t_R) - 3 79.05 2287.91 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09171_/Y (NAND2x2_ASAP7_75t_R) - 2 72.45 2360.36 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09366_/Y (OA21x2_ASAP7_75t_R) - 1 30.95 2391.30 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09368_/Y (OR4x1_ASAP7_75t_R) - 2 43.84 2435.15 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09369_/Y (OR4x2_ASAP7_75t_R) - 5 41.86 2477.01 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_10984_/Y (NOR3x2_ASAP7_75t_R) - 20 54.43 2531.44 ^ wire46500/Y (BUFx16f_ASAP7_75t_R) - 3 113.22 2644.66 ^ wire46499/Y (BUFx16f_ASAP7_75t_R) - 2 74.22 2718.88 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383170_/Y (AND2x2_ASAP7_75t_R) - 14 24.78 2743.66 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383188_/Y (NAND2x2_ASAP7_75t_R) - 12 63.17 2806.83 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383224_/Y (AO21x2_ASAP7_75t_R) - 5 24.83 2831.66 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_479882_/Y (CKINVDCx20_ASAP7_75t_R) - 11 84.15 2915.81 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_732259_/CON (HAxp5_ASAP7_75t_R) - 3 31.45 2947.26 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383227_/Y (INVx2_ASAP7_75t_R) - 2 25.01 2972.27 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383231_/Y (AND2x2_ASAP7_75t_R) - 2 22.19 2994.46 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_732246_/CON (HAxp5_ASAP7_75t_R) - 2 31.03 3025.49 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_732246_/SN (HAxp5_ASAP7_75t_R) - 1 31.95 3057.44 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_393218_/Y (XNOR2x1_ASAP7_75t_R) - 1 40.29 3097.73 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_393222_/Y (AND5x2_ASAP7_75t_R) - 1 38.93 3136.66 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09361_/Y (AO22x2_ASAP7_75t_R) - 1 60.29 3196.95 ^ wire32998/Y (BUFx16f_ASAP7_75t_R) - 1 63.16 3260.11 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09362_/Y (OR4x2_ASAP7_75t_R) - 1 16.20 3276.31 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09363_/Y (OR4x1_ASAP7_75t_R) - 1 19.72 3296.03 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09371_/Y (AO22x1_ASAP7_75t_R) - 3 10.78 3306.81 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09372_/Y (INVx2_ASAP7_75t_R) - 5 32.27 3339.08 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_10980_/Y (AND3x4_ASAP7_75t_R) - 2 32.46 3371.54 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_10981_/Y (AND2x6_ASAP7_75t_R) - 6 26.61 3398.15 v wire30552/Y (BUFx16f_ASAP7_75t_R) - 3 117.06 3515.20 v wire30547/Y (BUFx16f_ASAP7_75t_R) - 2 79.46 3594.66 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383202_/Y (AND2x2_ASAP7_75t_R) - 13 30.10 3624.76 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383232_/Y (NAND2x2_ASAP7_75t_R) - 37 104.44 3729.20 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383277_/Y (AO21x2_ASAP7_75t_R) - 8 123.99 3853.19 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383285_/Y (NOR2x2_ASAP7_75t_R) - 2 69.54 3922.74 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383289_/Y (AND2x2_ASAP7_75t_R) - 2 70.43 3993.16 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_732263_/SN (HAxp5_ASAP7_75t_R) - 1 35.94 4029.10 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_393224_/Y (XNOR2x1_ASAP7_75t_R) - 1 33.88 4062.98 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_393228_/Y (AND5x2_ASAP7_75t_R) - 1 22.63 4085.61 v wire18339/Y (BUFx12f_ASAP7_75t_R) - 1 90.65 4176.26 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09348_/Y (AO221x2_ASAP7_75t_R) - 1 78.25 4254.51 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09352_/Y (OR4x1_ASAP7_75t_R) - 2 12.50 4267.01 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09353_/Y (INVx1_ASAP7_75t_R) - 2 29.33 4296.34 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_13707_/Y (AND3x4_ASAP7_75t_R) - 2 16.51 4312.85 ^ max_length17970/Y (BUFx12f_ASAP7_75t_R) - 2 58.75 4371.60 ^ wire17968/Y (BUFx16f_ASAP7_75t_R) - 4 69.67 4441.27 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383260_/Y (AND2x4_ASAP7_75t_R) - 8 22.60 4463.87 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383290_/Y (NAND2x2_ASAP7_75t_R) - 25 39.78 4503.65 v load_slew17553/Y (BUFx16f_ASAP7_75t_R) - 8 52.97 4556.62 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_389614_/Y (OA21x2_ASAP7_75t_R) - 15 27.29 4583.91 v max_length15743/Y (BUFx16f_ASAP7_75t_R) - 6 44.22 4628.14 v wire15739/Y (BUFx16f_ASAP7_75t_R) - 2 96.47 4724.61 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_732319_/CON (HAxp5_ASAP7_75t_R) - 10 26.31 4750.92 ^ wire10637/Y (BUFx12f_ASAP7_75t_R) - 9 28.31 4779.22 ^ wire10635/Y (BUFx12f_ASAP7_75t_R) - 5 23.85 4803.08 ^ wire10634/Y (BUFx16f_ASAP7_75t_R) - 3 49.02 4852.10 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_393150_/Y (INVx3_ASAP7_75t_R) - 1 19.43 4871.53 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_732322_/CON (HAxp5_ASAP7_75t_R) - 2 13.70 4885.23 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_732225_/Y (INVx1_ASAP7_75t_R) - 2 54.56 4939.79 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_732324_/CON (HAxp5_ASAP7_75t_R) - 2 57.06 4996.85 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_732324_/SN (HAxp5_ASAP7_75t_R) - 1 39.36 5036.22 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_393230_/Y (XNOR2x1_ASAP7_75t_R) - 1 29.47 5065.69 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_393234_/Y (AND5x2_ASAP7_75t_R) - 1 38.32 5104.01 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09177_/Y (AO22x2_ASAP7_75t_R) - 1 65.68 5169.69 v wire10120/Y (BUFx16f_ASAP7_75t_R) - 1 85.75 5255.45 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09180_/Y (OR4x2_ASAP7_75t_R) - 1 47.72 5303.17 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09181_/Y (OR4x2_ASAP7_75t_R) - 1 14.50 5317.66 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09182_/Y (INVx1_ASAP7_75t_R) - 3 20.96 5338.62 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09346_/Y (AO31x2_ASAP7_75t_R) - 1 22.09 5360.71 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09357_/Y (AND2x2_ASAP7_75t_R) - 3 22.17 5382.88 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09375_/Y (NAND3x2_ASAP7_75t_R) - 2 44.87 5427.75 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_13855_/Y (NOR2x2_ASAP7_75t_R) - 4 31.84 5459.59 ^ max_length10066/Y (BUFx16f_ASAP7_75t_R) - 3 46.40 5505.98 ^ wire10064/Y (BUFx16f_ASAP7_75t_R) - 1 74.29 5580.27 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_14394_/Y (AND2x2_ASAP7_75t_R) - 1 5.61 5585.88 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/_065683_/Y (INVx1_ASAP7_75t_R) - 2 61.87 5647.75 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/_065702_/Y (OR5x2_ASAP7_75t_R) - 2 53.28 5701.03 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/_065722_/Y (NAND2x2_ASAP7_75t_R) - 24 24.22 5725.25 ^ max_length8441/Y (BUFx16f_ASAP7_75t_R) - 22 43.01 5768.26 ^ wire8439/Y (BUFx16f_ASAP7_75t_R) - 19 49.84 5818.10 ^ load_slew8429/Y (BUFx16f_ASAP7_75t_R) - 14 47.09 5865.20 ^ wire8426/Y (BUFx16f_ASAP7_75t_R) - 11 48.21 5913.41 ^ max_length8425/Y (BUFx16f_ASAP7_75t_R) - 10 58.85 5972.26 ^ wire8424/Y (BUFx16f_ASAP7_75t_R) - 10 61.11 6033.37 ^ max_length8423/Y (BUFx12f_ASAP7_75t_R) - 11 38.21 6071.58 ^ wire8422/Y (BUFx16f_ASAP7_75t_R) - 25 51.58 6123.15 ^ wire8421/Y (BUFx16f_ASAP7_75t_R) - 6 60.76 6183.91 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_1678_/Y (INVx11_ASAP7_75t_R) - 24 21.32 6205.24 v max_length4569/Y (BUFx16f_ASAP7_75t_R) - 11 62.98 6268.22 v wire4568/Y (BUFx16f_ASAP7_75t_R) - 10 53.54 6321.76 v wire4567/Y (BUFx16f_ASAP7_75t_R) - 12 73.47 6395.22 v wire4566/Y (BUFx16f_ASAP7_75t_R) - 35 109.03 6504.25 v max_length4564/Y (BUFx16f_ASAP7_75t_R) - 57 67.38 6571.63 v load_slew4563/Y (BUFx16f_ASAP7_75t_R) - 1 95.45 6667.09 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_1885_/Y (NAND2x1_ASAP7_75t_R) - 13 52.03 6719.12 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_1886_/Y (OA21x2_ASAP7_75t_R) - 1 30.21 6749.33 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_3041_/Y (XNOR2x1_ASAP7_75t_R) - 1 30.06 6779.38 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_3043_/Y (AND4x1_ASAP7_75t_R) - 1 32.88 6812.26 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_3047_/Y (AND5x1_ASAP7_75t_R) - 1 19.43 6831.69 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_3048_/Y (OR4x1_ASAP7_75t_R) - 1 29.64 6861.33 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_3133_/Y (OA31x2_ASAP7_75t_R) - 2.24 6863.57 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_3405_/D (DFFHQNx2_ASAP7_75t_R) - 6863.57 data arrival time - - 8500.00 8500.00 clock clock (rise edge) - 1476.29 9976.29 clock network delay (propagated) - -10.00 9966.29 clock uncertainty - 4.53 9970.81 clock reconvergence pessimism - 9970.81 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_3405_/CLK (DFFHQNx2_ASAP7_75t_R) - -10.95 9959.87 library setup time - 9959.87 data required time ---------------------------------------------------------------- - 9959.87 data required time - -6863.57 data arrival time ---------------------------------------------------------------- - 3096.30 slack (MET) - - -Startpoint: system/serial_tl_domain/_1142_ - (rising edge-triggered flip-flop clocked by clock) -Endpoint: serial_tl_0_bits_in_ready (output port clocked by clock_vir) -Path Group: clock_vir -Path Type: max - -Fanout Delay Time Description ---------------------------------------------------------------- - 0.00 0.00 clock clock (rise edge) - 1486.19 1486.19 clock network delay (propagated) - 0.00 1486.19 ^ system/serial_tl_domain/_1142_/CLK (DFFHQNx2_ASAP7_75t_R) - 3 50.71 1536.90 ^ system/serial_tl_domain/_1142_/QN (DFFHQNx2_ASAP7_75t_R) - 3 35.82 1572.72 v system/serial_tl_domain/_0641_/Y (NOR3x2_ASAP7_75t_R) - 1 61.16 1633.88 v output14/Y (BUFx2_ASAP7_75t_R) - 0.02 1633.90 v serial_tl_0_bits_in_ready (out) - 1633.90 data arrival time - - 8500.00 8500.00 clock clock_vir (rise edge) - 1000.00 9500.00 clock network delay (ideal) - -10.00 9490.00 clock uncertainty - 0.00 9490.00 clock reconvergence pessimism - -1700.00 7790.00 output external delay - 7790.00 data required time ---------------------------------------------------------------- - 7790.00 data required time - -1633.90 data arrival time ---------------------------------------------------------------- - 6156.10 slack (MET) - - -Startpoint: system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_100801_ - (rising edge-triggered flip-flop clocked by clock) -Endpoint: system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_3405_ - (rising edge-triggered flip-flop clocked by fake_pll_clk) -Path Group: fake_pll_clk -Path Type: max - -Fanout Delay Time Description ---------------------------------------------------------------- - 0.00 0.00 clock clock (rise edge) - 1459.67 1459.67 clock network delay (propagated) - 0.00 1459.67 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_100801_/CLK (DFFHQNx2_ASAP7_75t_R) - 16 87.80 1547.47 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_100801_/QN (DFFHQNx2_ASAP7_75t_R) - 8 25.27 1572.74 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_055753_/Y (INVx13_ASAP7_75t_R) - 3 21.71 1594.45 v max_length80840/Y (BUFx12f_ASAP7_75t_R) - 10 106.10 1700.55 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_100755_/CON (HAxp5_ASAP7_75t_R) - 5 38.99 1739.54 ^ load_slew77788/Y (BUFx12f_ASAP7_75t_R) - 6 18.39 1757.93 ^ load_slew77787/Y (BUFx12f_ASAP7_75t_R) - 24 74.82 1832.75 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_055925_/Y (OR4x2_ASAP7_75t_R) - 1 52.70 1885.46 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_055926_/Y (OA22x2_ASAP7_75t_R) - 1 32.11 1917.56 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_055940_/Y (AND5x1_ASAP7_75t_R) - 4 40.36 1957.93 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_055972_/Y (AND4x2_ASAP7_75t_R) - 21 41.38 1999.31 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_055973_/Y (NAND2x2_ASAP7_75t_R) - 3 92.34 2091.65 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_056022_/Y (OR3x4_ASAP7_75t_R) - 4 34.23 2125.88 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_056088_/Y (NOR3x2_ASAP7_75t_R) - 1 82.97 2208.86 ^ wire54325/Y (BUFx16f_ASAP7_75t_R) - 3 79.05 2287.91 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09171_/Y (NAND2x2_ASAP7_75t_R) - 2 72.45 2360.36 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09366_/Y (OA21x2_ASAP7_75t_R) - 1 30.95 2391.30 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09368_/Y (OR4x1_ASAP7_75t_R) - 2 43.84 2435.15 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09369_/Y (OR4x2_ASAP7_75t_R) - 5 41.86 2477.01 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_10984_/Y (NOR3x2_ASAP7_75t_R) - 20 54.43 2531.44 ^ wire46500/Y (BUFx16f_ASAP7_75t_R) - 3 113.22 2644.66 ^ wire46499/Y (BUFx16f_ASAP7_75t_R) - 2 74.22 2718.88 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383170_/Y (AND2x2_ASAP7_75t_R) - 14 24.78 2743.66 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383188_/Y (NAND2x2_ASAP7_75t_R) - 12 63.17 2806.83 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383224_/Y (AO21x2_ASAP7_75t_R) - 5 24.83 2831.66 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_479882_/Y (CKINVDCx20_ASAP7_75t_R) - 11 84.15 2915.81 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_732259_/CON (HAxp5_ASAP7_75t_R) - 3 31.45 2947.26 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383227_/Y (INVx2_ASAP7_75t_R) - 2 25.01 2972.27 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383231_/Y (AND2x2_ASAP7_75t_R) - 2 22.19 2994.46 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_732246_/CON (HAxp5_ASAP7_75t_R) - 2 31.03 3025.49 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_732246_/SN (HAxp5_ASAP7_75t_R) - 1 31.95 3057.44 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_393218_/Y (XNOR2x1_ASAP7_75t_R) - 1 40.29 3097.73 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_393222_/Y (AND5x2_ASAP7_75t_R) - 1 38.93 3136.66 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09361_/Y (AO22x2_ASAP7_75t_R) - 1 60.29 3196.95 ^ wire32998/Y (BUFx16f_ASAP7_75t_R) - 1 63.16 3260.11 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09362_/Y (OR4x2_ASAP7_75t_R) - 1 16.20 3276.31 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09363_/Y (OR4x1_ASAP7_75t_R) - 1 19.72 3296.03 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09371_/Y (AO22x1_ASAP7_75t_R) - 3 10.78 3306.81 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09372_/Y (INVx2_ASAP7_75t_R) - 5 32.27 3339.08 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_10980_/Y (AND3x4_ASAP7_75t_R) - 2 32.46 3371.54 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_10981_/Y (AND2x6_ASAP7_75t_R) - 6 26.61 3398.15 v wire30552/Y (BUFx16f_ASAP7_75t_R) - 3 117.06 3515.20 v wire30547/Y (BUFx16f_ASAP7_75t_R) - 2 79.46 3594.66 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383202_/Y (AND2x2_ASAP7_75t_R) - 13 30.10 3624.76 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383232_/Y (NAND2x2_ASAP7_75t_R) - 37 104.44 3729.20 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383277_/Y (AO21x2_ASAP7_75t_R) - 8 123.99 3853.19 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383285_/Y (NOR2x2_ASAP7_75t_R) - 2 69.54 3922.74 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383289_/Y (AND2x2_ASAP7_75t_R) - 2 70.43 3993.16 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_732263_/SN (HAxp5_ASAP7_75t_R) - 1 35.94 4029.10 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_393224_/Y (XNOR2x1_ASAP7_75t_R) - 1 33.88 4062.98 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_393228_/Y (AND5x2_ASAP7_75t_R) - 1 22.63 4085.61 v wire18339/Y (BUFx12f_ASAP7_75t_R) - 1 90.65 4176.26 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09348_/Y (AO221x2_ASAP7_75t_R) - 1 78.25 4254.51 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09352_/Y (OR4x1_ASAP7_75t_R) - 2 12.50 4267.01 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09353_/Y (INVx1_ASAP7_75t_R) - 2 29.33 4296.34 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_13707_/Y (AND3x4_ASAP7_75t_R) - 2 16.51 4312.85 ^ max_length17970/Y (BUFx12f_ASAP7_75t_R) - 2 58.75 4371.60 ^ wire17968/Y (BUFx16f_ASAP7_75t_R) - 4 69.67 4441.27 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383260_/Y (AND2x4_ASAP7_75t_R) - 8 22.60 4463.87 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_383290_/Y (NAND2x2_ASAP7_75t_R) - 25 39.78 4503.65 v load_slew17553/Y (BUFx16f_ASAP7_75t_R) - 8 52.97 4556.62 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_389614_/Y (OA21x2_ASAP7_75t_R) - 15 27.29 4583.91 v max_length15743/Y (BUFx16f_ASAP7_75t_R) - 6 44.22 4628.14 v wire15739/Y (BUFx16f_ASAP7_75t_R) - 2 96.47 4724.61 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_732319_/CON (HAxp5_ASAP7_75t_R) - 10 26.31 4750.92 ^ wire10637/Y (BUFx12f_ASAP7_75t_R) - 9 28.31 4779.22 ^ wire10635/Y (BUFx12f_ASAP7_75t_R) - 5 23.85 4803.08 ^ wire10634/Y (BUFx16f_ASAP7_75t_R) - 3 49.02 4852.10 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_393150_/Y (INVx3_ASAP7_75t_R) - 1 19.43 4871.53 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_732322_/CON (HAxp5_ASAP7_75t_R) - 2 13.70 4885.23 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_732225_/Y (INVx1_ASAP7_75t_R) - 2 54.56 4939.79 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_732324_/CON (HAxp5_ASAP7_75t_R) - 2 57.06 4996.85 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_732324_/SN (HAxp5_ASAP7_75t_R) - 1 39.36 5036.22 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_393230_/Y (XNOR2x1_ASAP7_75t_R) - 1 29.47 5065.69 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_393234_/Y (AND5x2_ASAP7_75t_R) - 1 38.32 5104.01 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09177_/Y (AO22x2_ASAP7_75t_R) - 1 65.68 5169.69 v wire10120/Y (BUFx16f_ASAP7_75t_R) - 1 85.75 5255.45 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09180_/Y (OR4x2_ASAP7_75t_R) - 1 47.72 5303.17 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09181_/Y (OR4x2_ASAP7_75t_R) - 1 14.50 5317.66 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09182_/Y (INVx1_ASAP7_75t_R) - 3 20.96 5338.62 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09346_/Y (AO31x2_ASAP7_75t_R) - 1 22.09 5360.71 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09357_/Y (AND2x2_ASAP7_75t_R) - 3 22.17 5382.88 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09375_/Y (NAND3x2_ASAP7_75t_R) - 2 44.87 5427.75 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_13855_/Y (NOR2x2_ASAP7_75t_R) - 4 31.84 5459.59 ^ max_length10066/Y (BUFx16f_ASAP7_75t_R) - 3 46.40 5505.98 ^ wire10064/Y (BUFx16f_ASAP7_75t_R) - 1 74.29 5580.27 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_14394_/Y (AND2x2_ASAP7_75t_R) - 1 5.61 5585.88 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/_065683_/Y (INVx1_ASAP7_75t_R) - 2 61.87 5647.75 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/_065702_/Y (OR5x2_ASAP7_75t_R) - 2 53.28 5701.03 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/_065722_/Y (NAND2x2_ASAP7_75t_R) - 24 24.22 5725.25 ^ max_length8441/Y (BUFx16f_ASAP7_75t_R) - 22 43.01 5768.26 ^ wire8439/Y (BUFx16f_ASAP7_75t_R) - 19 49.84 5818.10 ^ load_slew8429/Y (BUFx16f_ASAP7_75t_R) - 14 47.09 5865.20 ^ wire8426/Y (BUFx16f_ASAP7_75t_R) - 11 48.21 5913.41 ^ max_length8425/Y (BUFx16f_ASAP7_75t_R) - 10 58.85 5972.26 ^ wire8424/Y (BUFx16f_ASAP7_75t_R) - 10 61.11 6033.37 ^ max_length8423/Y (BUFx12f_ASAP7_75t_R) - 11 38.21 6071.58 ^ wire8422/Y (BUFx16f_ASAP7_75t_R) - 25 51.58 6123.15 ^ wire8421/Y (BUFx16f_ASAP7_75t_R) - 6 60.76 6183.91 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_1678_/Y (INVx11_ASAP7_75t_R) - 24 21.32 6205.24 v max_length4569/Y (BUFx16f_ASAP7_75t_R) - 11 62.98 6268.22 v wire4568/Y (BUFx16f_ASAP7_75t_R) - 10 53.54 6321.76 v wire4567/Y (BUFx16f_ASAP7_75t_R) - 12 73.47 6395.22 v wire4566/Y (BUFx16f_ASAP7_75t_R) - 35 109.03 6504.25 v max_length4564/Y (BUFx16f_ASAP7_75t_R) - 57 67.38 6571.63 v load_slew4563/Y (BUFx16f_ASAP7_75t_R) - 1 95.45 6667.09 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_1885_/Y (NAND2x1_ASAP7_75t_R) - 13 52.03 6719.12 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_1886_/Y (OA21x2_ASAP7_75t_R) - 1 30.21 6749.33 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_3041_/Y (XNOR2x1_ASAP7_75t_R) - 1 30.06 6779.38 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_3043_/Y (AND4x1_ASAP7_75t_R) - 1 32.88 6812.26 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_3047_/Y (AND5x1_ASAP7_75t_R) - 1 19.43 6831.69 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_3048_/Y (OR4x1_ASAP7_75t_R) - 1 29.64 6861.33 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_3133_/Y (OA31x2_ASAP7_75t_R) - 2.24 6863.57 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_3405_/D (DFFHQNx2_ASAP7_75t_R) - 6863.57 data arrival time - - 8500.00 8500.00 clock fake_pll_clk (rise edge) - 1445.94 9945.94 clock network delay (propagated) - -10.00 9935.94 clock uncertainty - 0.00 9935.94 clock reconvergence pessimism - 9935.94 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/mem_issue_unit/slots_23/_3405_/CLK (DFFHQNx2_ASAP7_75t_R) - -10.95 9924.99 library setup time - 9924.99 data required time ---------------------------------------------------------------- - 9924.99 data required time - -6863.57 data arrival time ---------------------------------------------------------------- - 3061.42 slack (MET) - - -Startpoint: serial_tl_0_bits_out_ready (input port clocked by clock_vir) -Endpoint: system/serial_tl_domain/_1190_ - (rising edge-triggered flip-flop clocked by serial_tl_0_clock) -Path Group: serial_tl_0_clock -Path Type: max - -Fanout Delay Time Description ---------------------------------------------------------------- - 0.00 0.00 clock clock_vir (rise edge) - 1000.00 1000.00 clock network delay (ideal) - 1700.00 2700.00 v input external delay - 1 0.00 2700.00 v serial_tl_0_bits_out_ready (in) - 1 12.09 2712.09 v input11/Y (BUFx2_ASAP7_75t_R) - 1 21.58 2733.66 v system/serial_tl_domain/_0823_/Y (AND2x6_ASAP7_75t_R) - 1 25.37 2759.03 v wire96183/Y (BUFx12f_ASAP7_75t_R) - 13 259.71 3018.74 v system/serial_tl_domain/_1128_/SN (HAxp5_ASAP7_75t_R) - 3 104.06 3122.80 v system/serial_tl_domain/_0882_/Y (OR3x4_ASAP7_75t_R) - 1 13.63 3136.44 ^ system/serial_tl_domain/_0897_/Y (AOI211x1_ASAP7_75t_R) - 1 22.32 3158.76 ^ system/serial_tl_domain/_0898_/Y (AO221x1_ASAP7_75t_R) - 1 23.94 3182.70 ^ system/serial_tl_domain/_0899_/Y (OR4x2_ASAP7_75t_R) - 1 20.19 3202.89 ^ system/serial_tl_domain/_0900_/Y (OA22x2_ASAP7_75t_R) - 0.01 3202.90 ^ system/serial_tl_domain/_1190_/D (DFFHQNx2_ASAP7_75t_R) - 3202.90 data arrival time - - 8500.00 8500.00 clock serial_tl_0_clock (rise edge) - 99.58 8599.58 clock network delay (propagated) - -10.00 8589.58 clock uncertainty - 0.00 8589.58 clock reconvergence pessimism - 8589.58 ^ system/serial_tl_domain/_1190_/CLK (DFFHQNx2_ASAP7_75t_R) - -5.33 8584.25 library setup time - 8584.25 data required time ---------------------------------------------------------------- - 8584.25 data required time - -3202.90 data arrival time ---------------------------------------------------------------- - 5381.35 slack (MET) -``` - - - -### oharboe -To get this to build in Yosys, I had to mock fake_pll_clk: - -https://github.com/The-OpenROAD-Project/megaboom/blob/931c2a882510bf5735dbf5efab1a8c474f838c49/mock/ChipTop.sv#L31 - -Whereas Chipyard has this clock coming out of a PLL: - -https://github.com/The-OpenROAD-Project/megaboom/blob/931c2a882510bf5735dbf5efab1a8c474f838c49/rtl/ChipTop.sv#L150 - -I don't know what the relationships are between these clocks, this is my first cut .sdc file that I used: - -https://github.com/The-OpenROAD-Project/megaboom/blob/main/constraints-chiptop.sdc - -### oharboe -I've reached out to Chipyard to get some help with the .sdc file for the clocks: https://groups.google.com/g/chipyard/c/PzVcnnqRwf8/m/t1pIDPnuAwAJ - -### oharboe -Failed in global routing, ca. 7000 seconds. - -`make macro_place_issue` reproducible case for mpl2: https://drive.google.com/file/d/1w_vIUNtWp7dBntP9i7WGEkgtGhTRD6M_/view?usp=sharing - -I suppose I could try to flatten the design for the two macros with contention, but if macro placement can't place these two bigger macros, what are the chances it can place many smaller macros(there are SRAMs inside the branch predictor and the data cache that have all the congestion on top)? - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/520a354a-1e5e-42a3-b3c4-090050a08c42) -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/a4a48871-f7c9-4445-aff2-4621b73f551a) -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/199c6c47-e6ba-4471-8f98-1befb9677a22) - -Intentionally, BranchPredictor has all the pins on the left side. This is to break the rotational and mirroring symmetry such that mpl2 can try different directions to find one that is better. - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/7272e784-c63e-4209-b0ac-3dd59f43b22d) - -This is odd... Why is the macro rotated R180? That puts the pins on the right hand side... I would have thought, looking at the floorplan, that having the pins on the left side was better, given the placement... - - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/c54e3016-9444-4b17-805f-9a82a1d003d7) - - -### maliberty -You can zoom in with the mouse wheel in the CTS view. If you do so on the odd branch on the right you can select the end points and see what they are. That would be helpful. - -The setup paths with tons of hold buffers are quite odd. I suspect an SDC issue. - -You might lower the placement density slightly to see if that helps with congestion. - -A test case for the flipping is needed to say much about it. Perhaps the connections go to pins on the right? - -### oharboe -Broke out #4513 and #4512 for further investigation - -### oharboe -So, I think I understand more or less what is going on. - -The Verilog is not the way I want it yet. It contains a fake PLL that is controlled via the TileLink interface at the top level that multiplies the top level clock to the core frequency. This PLL is set up out of bounds of a single core. - -https://github.com/ucb-bar/chipyard/blob/c9fa23edf049f35f9b8e6291b0e2b82b1056540b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala#L12 - diff --git a/gh_discussions/Runtime/4522.md b/gh_discussions/Runtime/4522.md deleted file mode 100644 index e3129d248619ffb6f33b7f0caafa6ec1d81e8a17..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/4522.md +++ /dev/null @@ -1,131 +0,0 @@ -# MegaBoom, clock trees, macro placement and global routing congestion - -Tool: Clock Tree Synthesis - -Subcategory: Clock tree and timing analysis - -## Conversation - -### oharboe -How can I tell if clock skew is increasing the minimum clock period for a design? - -Here is my current understanding: - -If two flip flops are not connected, then the clock skew between the clocks that drive those two flip flops doesn't matter because there is no timing path between these two flip flops. - -Skew can be good and it can be bad. If there is a long timing path between two flip flops, then a negative skew for the starting flip flops or postivive skew for the capturing flip flop would make it easier to meet timing. - -As a first order approximation though, the CTS will try to minimize clock skew, because in the end a very large clock skew will catch up with you and increase the minimum clock period. - -Latest MegaBoom update: - -I have [modified MegaBoom](https://github.com/The-OpenROAD-Project/megaboom/pull/18) so that it no longer has a PLL, but a clock for the TileLink (top level memory/peripheral interface) and for the RISC-V core. - -As I understand, though I don't know the code very well, the RISC-V core is connected to the TileLink via an asynchronous FIFO(or equivalent thereof). - -Therefore there are no ChipTop inputs/outputs that have an insertion point relative to the clock for the RISC-V core. This seems like a clever way of doing things, because then the insertion latency of the RISC-V clock doesn't matter(though clock uncertainty which I would expect to grow with a long clock insertation latency) for the clock period. - -``` ->>> report_clock_skew -Clock clock_uncore -Latency CRPR Skew -system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_728430_/CLK ^ - 882.50 -system/tile_prci_domain/tile_reset_domain_boom_tile/core/int_issue_unit/slots_32/_3607_/CLK ^ -1008.42 0.00 -125.92 - -Clock serial_tl_0_clock -Latency CRPR Skew -system/serial_tl_domain/_1154_/CLK ^ - 67.76 -system/serial_tl_domain/_1275_/CLK ^ - 64.77 0.00 2.99 -``` - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/1df082cd-b853-44f7-8b5e-7ebeb9e1409b) - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/e1288f3f-c699-4fa5-9148-40a2b85e5d43) - -Some notes: - -- The area of some of those macros are mocked to be smaller than they really are so as to fit this into 1000um x 1000um and have reasonable turnaround times in builds. The L2 is *tiny* in area... -- The longest timing path is part of the top level design(macros are not involved), so nothing material should be lost by ignoring what is inside the macros for now. The macros are abstracts from floorplan, so completely unrealistic. -- A quick test the other day put a flattened design at ca. 3mm^2 and 3 million instances(big caveat, as I write this from my flawed memory, I'm not currently studying a flattened design). To be revisited later maybe. -- W.r.t. the global placement congestion, macro placement has a fix coming up, so I don't think there's anything interesting to study w.r.t. macro placement and global routing congestion until a new build has been done after that fix. https://github.com/The-OpenROAD-Project/OpenROAD/pull/4519 -- almost no hold cells, 20, there used to be thousands or even tens of thousands. . :exploding_head: -- running time for CTS is now much more reasonable, 5000s down from 30000s. This is not entirely suprising: now that the clock tree is not pathologically formed, the repair job is probably quick. - - -``` -Log Elapsed seconds -1_0_mem 173 -1_1_yosys 3606 -1_1_yosys_hier_report 3542 -2_1_floorplan 277 -2_2_floorplan_io 8 -No elapsed time found in bazel-bin/logs/asap7/ChipTop/base/2_3_floorplan_tdms.log -2_4_floorplan_macro 496 -2_5_floorplan_tapcell 130 -2_6_floorplan_pdn 206 -3_1_place_gp_skip_io 448 -3_2_place_iop 14 -3_3_place_gp 4564 -3_4_place_resized 863 -3_5_place_dp 1033 -4_1_cts 5069 -5_1_grt 14525 -Total 34954 -``` - - -### rovinski -> If two flip flops are not connected, then the clock skew between the clocks that drive those two flip flops doesn't matter because there is no timing path between these two flip flops. - -Correct - -> Skew can be good and it can be bad. If there is a long timing path between two flip flops, then a negative skew for the starting flip flops or postivive skew for the capturing flip flop would make it easier to meet timing. - -Correct - -> As a first order approximation though, the CTS will try to minimize clock skew, because in the end a very large clock skew will catch up with you and increase the minimum clock period. - -The OR CTS engine tries to minimize skew because it is algorithmically simpler, but not necessarily the most optimal. Commercial engines use a technique called "concurrent clock optimization" which will look at the timing paths and purposefully skew certain registers if it makes timing better. - -Concurrent clock optimization has a similar effect to register retiming - the former shifts the clock so it borrows setup time from one stage to give to another stage. The latter shifts logic from one stage to another stage and therefore also shifts setup time. - -> As I understand, though I don't know the code very well, the RISC-V core is connected to the TileLink via an asynchronous FIFO(or equivalent thereof). - -Yes, async FIFOs or other clock domain crossings (CDCs) are convenient ways to break up and decouple clock trees. Clock trees cannot become too large, because the larger they are, the more power they consume and the more difficult it is to minimize skew/jitter/uncertainty. A clock tree can become so large that the jitter becomes larger than the clock period, in which case timing is impossible to meet. There is a design tradeoff between how many clock domains there are and data latency because the CDCs add one or more cycles when transmitting data across the interface. - -> How can I tell if clock skew is increasing the minimum clock period for a design? - -I might rephrase the question more simply as "How can I tell if clock skew is bad for a design?" because clock skew always impacts the clock period, as alluded above. This is one of the areas where it takes a lot of intuition, experimentation, and heuristics to evaluate because the answer is rarely clear. A soft and perhaps unuseful rule of thumb would be "when the clock skew/jitter/uncertainty becomes a significant fraction of the clock period". There are no hard rules of thumb, because sometimes high skew can be tolerated in order to keep the design fully synchronous. I personally start to get suspicious if the skew is eating more than 20-40% of the clock period. But the size of the clock tree also matters and how much skew you would _expect_ from a clock tree of that size. - -There are some red flags, though, to identify purely suboptimal results. One is if there are many, many hold buffers being inserted. This is usually due to bad timing constraints, but it could also be due to bad skew in the clock tree. - -Another red flag is if a path is failing both setup time _and_ hold time. This most often happens not because of skew but because of jitter caused by on-chip variation. Jitter can cause clock edges to be both early and late, which means that if a path is failing both then the jitter is too high. - -### oharboe -This is the [asynchronous connection](https://github.com/The-OpenROAD-Project/megaboom/blob/9d9d44d90545dd747f38f23d1f4c37045edb5d57/rtl/ClockSinkDomain_2.sv#L163C3-L163C3) between TileLink and the rest of the system is in the Verilog code. - -Here is [the expected gray counter](https://github.com/The-OpenROAD-Project/megaboom/blob/9d9d44d90545dd747f38f23d1f4c37045edb5d57/rtl/AsyncQueueSink_3.sv#L56C14-L56C34) and the corresponding [Chisel code](https://github.com/chipsalliance/rocket-chip/blob/50adbdb3e4e18c2b3de57693323f4174b60f9767/src/main/scala/util/AsyncQueue.scala#L145). - - - -### oharboe -I chased down the synchronous reset although it doesn't show up in the most critical path at the ChipTop level. - -For now, I have created a macro out of the BranchPredictor to rein in build times. In that macro the synchronous reset has a very large fanout, which obviously is a disaster for timing. - -After some investigation at the top level, I have found out that MegaBoom, [as documented](https://docs.boom-core.org/en/latest/sections/physical-realization.html#register-retiming), is relying heavily on register retiming and that the synchronous reset [is in fact pipelined](https://github.com/The-OpenROAD-Project/megaboom/blob/9d9d44d90545dd747f38f23d1f4c37045edb5d57/rtl/AsyncResetSynchronizerPrimitiveShiftReg_d3_i0.sv#L40). - -However, since the design is hierarchical and not flattened, the design won't be able to take advantage of these three pipeline stages. Also, yosys does not support retiming. - -Retiming in OpenROAD/yosys has been discussed in some detail [previously](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/discussions/1710#discussioncomment-7882745), I wanted to share the results of my investigation into synchronous reset specifically for MegaBoom. - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/205fd24f-9f6f-4153-ba6e-75a32f1f87a9) - - -### oharboe -For my part, the questions were answered so closing. - diff --git a/gh_discussions/Runtime/4529.md b/gh_discussions/Runtime/4529.md deleted file mode 100644 index e1d54a115614e4187823b472d9b544e57c664e79..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/4529.md +++ /dev/null @@ -1,470 +0,0 @@ -# MegaBoom flattened - -Tool: Global Routing - -Subcategory: Long run times - -## Conversation - -### oharboe -Based on https://github.com/The-OpenROAD-Project/megaboom/commit/a8e07eab7d4848057ac8e7993d5fee93b3d8653d - -After understanding the design better and a best effort to [generating Verilog](https://groups.google.com/g/chipyard/c/XPmGRK_CtZA) for the core with an asynchronous FIFO from the core to the surrounding memory system and buses such that the depth of the clock tree in the core isn't such an enormous issue + I have a report from yosys to list all RAMs and ROMs in the design such that I can be sure that I mock all ROM/RAMs larger than 1024 bits, it was time to try [MegaBoom flattened](https://github.com/The-OpenROAD-Project/megaboom/blob/1cce55c772d823ebca0bf8368f1d363a2e546044/BUILD.bazel#L1153)... - -The core here is MegaBoom up to and including L1 data/instruction cache. L2 & peripherals are excluded. - -Synthesis times are tolerable and not that far off non-flattened where I break out some macros for the larger parts of the core: ICache, DCache, branch predictor and floating point pipeline. - -``` -Log Elapsed seconds -1_1_yosys 4057 -1_1_yosys_hier_report 4063 -Total 8120 -``` - -From `make gui_synth`, I can see that the core is ca. 98% of the design measured in instances. The rest are buses and asynchronous bridges. - -`make memory` reports the table of roms and rams in the design. This report uses yosys and takes ca. 5 minutes to run, very acceptable. It would be *great* if synthesis could be run without optimizations quicky and then to view the results in the hierarchy view... - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/05c5ded4-19e6-417f-ba74-31c5c64aa6ea) - -The area of the instances is 250000um^2. I have been having trouble with 30% placement density, so I'm going to try 20% placement density. What is the relationship with CORE_UTILIZATION and placement density here...? - -Make that CORE_UTILIZATION=15 - -sqrt(2500000/0.15) => 1300um * 1300um - -Macro placement and estimated routing congestion for 2000um x 2000um. The macros seem to be pushed out to the corners, let's see how that works out in placement and routing... - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/03f9e101-6a6b-4362-a4f9-f93e142c11dc) - -Routing congestion in `make gui_place`. Why is the empty area yellow? Is power considered part of routing congestion? - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/cdef90ba-9366-4046-b86d-7cac7a1d476f) - -Estimated routing congestion RUDY. I guess RUDY excludes power? - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/203b5a86-3cd4-4c04-bf80-a0b204e98692) - -Clock tree looks good: - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/2363f35c-d12e-44b4-bbbb-5773d25b3426) - - -Global routing has taken 40000s so far, but it seems to have succeeded: - -``` -[INFO GRT-0101] Running extra iterations to remove overflow. -[INFO GRT-0197] Via related to pin nodes: 10765900 -[INFO GRT-0198] Via related Steiner nodes: 1028317 -[INFO GRT-0199] Via filling finished. -[INFO GRT-0111] Final number of vias: 14831285 -[INFO GRT-0112] Final usage 3D: 118911097 - -[INFO GRT-0096] Final congestion report: -Layer Resource Demand Usage (%) Max H / Max V / Total Overflow ---------------------------------------------------------------------------------------- -M1 0 0 0.00% 0 / 0 / 0 -M2 65189536 19765924 30.32% 0 / 0 / 0 -M3 88394705 29035790 32.85% 0 / 0 / 0 -M4 65419606 14163760 21.65% 0 / 0 / 0 -M5 58863583 8001905 13.59% 0 / 0 / 0 -M6 42524107 2674369 6.29% 0 / 0 / 0 -M7 52346733 775494 1.48% 0 / 0 / 0 ---------------------------------------------------------------------------------------- -Total 372738270 74417242 19.97% 0 / 0 / 0 - -[INFO GRT-0018] Total wirelength: 44969527 um -[INFO GRT-0014] Routed nets: 2043518 -Warning: There are 10 input ports missing set_input_delay. -Warning: There are 7 output ports missing set_output_delay. -Warning: There are 323 unclocked register/latch pins. -Warning: There are 4128 unconstrained endpoints. - -========================================================================== -global route pre repair design report_design_area --------------------------------------------------------------------------- -Design area 523197 u^2 13% utilization. -Perform buffer insertion... -[INFO RSZ-0058] Using max wire length 162um. -``` - - -Global route heat map: - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/504a1b08-d095-41f1-a8be-6392437eeaf5) - - -Detailed routing without power: - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/97c26702-6d81-472a-a79d-e15eb6cf1a9e) - - -Regarding the long global routing times, I set SKIP_INCREMENTAL_REPAIR=1 in detailed routing, whereas it is a global routing argument. I believe that will take care of the pathologically slow global routing... - -``` -- 'route': ['SKIP_INCREMENTAL_REPAIR=1'], -+ 'grt': ['SKIP_INCREMENTAL_REPAIR=1'] -``` - - -``` ->>> report_checks -path_delay max -Startpoint: system/prci_ctrl_domain/_853_ - (rising edge-triggered flip-flop clocked by clock_uncore) -Endpoint: system/_185_ (recovery check against rising-edge clock clock_uncore) -Path Group: asynchronous -Path Type: max - - Delay Time Description ---------------------------------------------------------- - 0.00 0.00 clock clock_uncore (rise edge) -1973.50 1973.50 clock network delay (propagated) - 0.00 1973.50 ^ system/prci_ctrl_domain/_853_/CLK (DFFASRHQNx1_ASAP7_75t_R) - 87.72 2061.22 v system/prci_ctrl_domain/_853_/QN (DFFASRHQNx1_ASAP7_75t_R) - 41.86 2103.08 v load_slew185637/Y (BUFx16f_ASAP7_75t_R) - 37.04 2140.12 v max_cap185634/Y (BUFx16f_ASAP7_75t_R) - 36.83 2176.95 v wire185631/Y (BUFx16f_ASAP7_75t_R) - 41.48 2218.44 v wire185630/Y (BUFx16f_ASAP7_75t_R) - 47.39 2265.83 v max_length185629/Y (BUFx16f_ASAP7_75t_R) - 39.69 2305.52 v wire185628/Y (BUFx16f_ASAP7_75t_R) - 81.35 2386.87 v max_length185627/Y (BUFx16f_ASAP7_75t_R) - 29.27 2416.13 v load_slew185625/Y (BUFx16f_ASAP7_75t_R) - 52.11 2468.25 v load_slew185624/Y (BUFx12f_ASAP7_75t_R) - 43.24 2511.49 v load_slew185618/Y (BUFx16f_ASAP7_75t_R) - 50.84 2562.32 v load_slew185615/Y (BUFx16f_ASAP7_75t_R) - 34.35 2596.68 v load_slew185559/Y (BUFx16f_ASAP7_75t_R) - 34.56 2631.24 v load_slew185558/Y (BUFx16f_ASAP7_75t_R) - 26.61 2657.85 v load_slew185557/Y (BUFx16f_ASAP7_75t_R) - 46.26 2704.11 v load_slew185556/Y (BUFx16f_ASAP7_75t_R) - 51.34 2755.46 v max_length185555/Y (BUFx12f_ASAP7_75t_R) - 41.44 2796.90 v wire185553/Y (BUFx16f_ASAP7_75t_R) - 51.64 2848.53 v load_slew185552/Y (BUFx16f_ASAP7_75t_R) - 34.46 2882.99 v wire185550/Y (BUFx16f_ASAP7_75t_R) - 51.12 2934.11 v wire185547/Y (BUFx16f_ASAP7_75t_R) - 64.89 2999.00 v load_slew185546/Y (BUFx16f_ASAP7_75t_R) - 37.84 3036.83 v wire185534/Y (BUFx16f_ASAP7_75t_R) - 88.57 3125.41 v wire185533/Y (BUFx3_ASAP7_75t_R) - 17.20 3142.60 v wire23908/Y (BUFx16f_ASAP7_75t_R) - 103.84 3246.44 v wire185532/Y (BUFx16f_ASAP7_75t_R) - 53.90 3300.35 v load_slew185531/Y (BUFx16f_ASAP7_75t_R) - 35.37 3335.71 v load_slew185522/Y (BUFx16f_ASAP7_75t_R) - 31.13 3366.84 v load_slew185507/Y (BUFx16f_ASAP7_75t_R) - 32.21 3399.06 v wire185505/Y (BUFx16f_ASAP7_75t_R) - 37.17 3436.23 v load_slew185504/Y (BUFx16f_ASAP7_75t_R) - 25.45 3461.69 v load_slew185494/Y (BUFx16f_ASAP7_75t_R) - 25.36 3487.04 v wire185486/Y (BUFx16f_ASAP7_75t_R) - 47.14 3534.18 v wire185485/Y (BUFx16f_ASAP7_75t_R) - 24.87 3559.05 v max_cap185484/Y (BUFx16f_ASAP7_75t_R) - 27.89 3586.94 v wire185483/Y (BUFx3_ASAP7_75t_R) - 16.61 3603.56 v wire19831/Y (BUFx16f_ASAP7_75t_R) - 105.13 3708.69 v wire185481/Y (BUFx3_ASAP7_75t_R) - 18.09 3726.78 v wire19408/Y (BUFx16f_ASAP7_75t_R) - 112.70 3839.48 ^ system/_107_/Y (INVx1_ASAP7_75t_R) - 0.03 3839.51 ^ system/_185_/SETN (DFFASRHQNx1_ASAP7_75t_R) - 3839.51 data arrival time - -8500.00 8500.00 clock clock_uncore (rise edge) -1969.03 10469.03 clock network delay (propagated) - -10.00 10459.03 clock uncertainty - 0.00 10459.03 clock reconvergence pessimism - 10459.03 ^ system/_185_/CLK (DFFASRHQNx1_ASAP7_75t_R) - 0.82 10459.85 library recovery time - 10459.85 data required time ---------------------------------------------------------- - 10459.85 data required time - -3839.51 data arrival time ---------------------------------------------------------- - 6620.34 slack (MET) - - -Startpoint: _32_ (negative level-sensitive latch clocked by clock_uncore) -Endpoint: _10_ (rising clock gating-check end-point clocked by clock_uncore) -Path Group: gated clock -Path Type: max - - Delay Time Description ---------------------------------------------------------- -4250.00 4250.00 clock clock_uncore (fall edge) -2156.12 6406.12 clock network delay (propagated) - 0.00 6406.12 v _32_/CLK (DLLx1_ASAP7_75t_R) - 32.10 6438.22 v _32_/Q (DLLx1_ASAP7_75t_R) - 0.01 6438.23 v _10_/B (AND2x4_ASAP7_75t_R) - 6438.23 data arrival time - -8500.00 8500.00 clock clock_uncore (rise edge) -1955.45 10455.45 clock network delay (propagated) - -10.00 10445.45 clock uncertainty - 0.00 10445.45 clock reconvergence pessimism - 10445.45 ^ _10_/A (AND2x4_ASAP7_75t_R) - 0.00 10445.45 clock gating setup time - 10445.45 data required time ---------------------------------------------------------- - 10445.45 data required time - -6438.23 data arrival time ---------------------------------------------------------- - 4007.22 slack (MET) - - -Startpoint: system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_100862_ - (rising edge-triggered flip-flop clocked by clock_uncore) -Endpoint: system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_719555_ - (rising edge-triggered flip-flop clocked by clock_uncore) -Path Group: clock_uncore -Path Type: max - - Delay Time Description ---------------------------------------------------------- - 0.00 0.00 clock clock_uncore (rise edge) -1977.51 1977.51 clock network delay (propagated) - 0.00 1977.51 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_100862_/CLK (DFFHQNx2_ASAP7_75t_R) - 97.74 2075.25 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_100862_/QN (DFFHQNx2_ASAP7_75t_R) - 26.79 2102.04 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_055781_/Y (CKINVDCx20_ASAP7_75t_R) - 123.43 2225.47 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_100818_/CON (HAxp5_ASAP7_75t_R) - 36.21 2261.68 ^ wire155277/Y (BUFx12f_ASAP7_75t_R) - 45.28 2306.96 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_055932_/Y (NOR2x2_ASAP7_75t_R) - 28.25 2335.21 v max_length142580/Y (BUFx16f_ASAP7_75t_R) - 104.72 2439.93 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_055933_/Y (NAND2x2_ASAP7_75t_R) - 59.96 2499.89 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_055934_/Y (OA22x2_ASAP7_75t_R) - 36.00 2535.89 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_055951_/Y (AND4x2_ASAP7_75t_R) - 12.14 2548.03 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_055963_/Y (NAND3x2_ASAP7_75t_R) - 70.12 2618.15 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_055964_/Y (AOI211x1_ASAP7_75t_R) - 55.95 2674.10 ^ load_slew117489/Y (BUFx12f_ASAP7_75t_R) - 53.80 2727.90 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_056077_/Y (AND3x4_ASAP7_75t_R) - 25.58 2753.48 ^ max_length114043/Y (BUFx16f_ASAP7_75t_R) - 32.81 2786.29 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_056130_/Y (AND2x6_ASAP7_75t_R) - 14.23 2800.52 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_056131_/Y (NAND2x1_ASAP7_75t_R) - 15.55 2816.06 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_056132_/Y (INVx1_ASAP7_75t_R) - 16.14 2832.21 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09390_/Y (NAND2x2_ASAP7_75t_R) - 28.51 2860.72 v wire99845/Y (BUFx16f_ASAP7_75t_R) - 70.62 2931.33 v wire99844/Y (BUFx16f_ASAP7_75t_R) - 56.99 2988.32 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09404_/Y (OAI21x1_ASAP7_75t_R) - 11.35 2999.67 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09407_/Y (NAND2x1_ASAP7_75t_R) - 44.90 3044.57 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09408_/Y (OR4x2_ASAP7_75t_R) - 57.29 3101.86 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09409_/Y (OR5x2_ASAP7_75t_R) - 39.18 3141.05 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_11025_/Y (NOR2x2_ASAP7_75t_R) - 25.42 3166.47 ^ wire85735/Y (BUFx3_ASAP7_75t_R) - 16.09 3182.56 ^ wire22108/Y (BUFx16f_ASAP7_75t_R) - 96.00 3278.56 ^ max_length85734/Y (BUFx12f_ASAP7_75t_R) - 59.41 3337.98 ^ wire85733/Y (BUFx3_ASAP7_75t_R) - 15.95 3353.92 ^ wire21265/Y (BUFx16f_ASAP7_75t_R) - 93.06 3446.99 ^ max_length85732/Y (BUFx16f_ASAP7_75t_R) - 52.88 3499.86 ^ wire85731/Y (BUFx12f_ASAP7_75t_R) - 61.48 3561.34 ^ wire85730/Y (BUFx12f_ASAP7_75t_R) - 94.55 3655.89 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_374889_/Y (AND3x4_ASAP7_75t_R) - 93.17 3749.07 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_374891_/Y (XNOR2x2_ASAP7_75t_R) - 33.79 3782.85 v max_length80723/Y (BUFx16f_ASAP7_75t_R) - 73.46 3856.31 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_715616_/CON (HAxp5_ASAP7_75t_R) - 16.66 3872.97 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_374906_/Y (INVx4_ASAP7_75t_R) - 24.46 3897.43 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_715614_/CON (HAxp5_ASAP7_75t_R) - 13.62 3911.05 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_715583_/Y (INVx1_ASAP7_75t_R) - 101.30 4012.35 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_715612_/SN (HAxp5_ASAP7_75t_R) - 45.01 4057.36 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_384513_/Y (XNOR2x1_ASAP7_75t_R) - 28.70 4086.05 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_384518_/Y (AND5x2_ASAP7_75t_R) - 31.22 4117.28 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09414_/Y (AO22x2_ASAP7_75t_R) - 32.81 4150.08 v wire55436/Y (BUFx12f_ASAP7_75t_R) - 66.68 4216.77 v wire55435/Y (BUFx12f_ASAP7_75t_R) - 67.25 4284.01 v wire55434/Y (BUFx12f_ASAP7_75t_R) - 66.32 4350.34 v wire55433/Y (BUFx12f_ASAP7_75t_R) - 67.31 4417.65 v wire55432/Y (BUFx12f_ASAP7_75t_R) - 71.71 4489.36 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09415_/Y (OR4x1_ASAP7_75t_R) - 50.77 4540.13 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09416_/Y (OR5x2_ASAP7_75t_R) - 50.72 4590.86 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09417_/Y (OR5x2_ASAP7_75t_R) - 33.49 4624.35 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_11022_/Y (AOI22x1_ASAP7_75t_R) - 26.99 4651.33 ^ load_slew51767/Y (BUFx16f_ASAP7_75t_R) - 59.33 4710.67 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_11023_/Y (AND2x6_ASAP7_75t_R) - 32.05 4742.72 ^ wire50793/Y (BUFx16f_ASAP7_75t_R) - 70.46 4813.18 ^ wire50792/Y (BUFx16f_ASAP7_75t_R) - 57.14 4870.32 ^ max_length50791/Y (BUFx12f_ASAP7_75t_R) - 57.90 4928.22 ^ wire50790/Y (BUFx16f_ASAP7_75t_R) - 89.00 5017.21 ^ wire50789/Y (BUFx16f_ASAP7_75t_R) - 65.37 5082.59 ^ wire50788/Y (BUFx12f_ASAP7_75t_R) - 62.25 5144.84 ^ wire50787/Y (BUFx12f_ASAP7_75t_R) - 73.66 5218.50 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_374879_/Y (AND2x2_ASAP7_75t_R) - 30.04 5248.54 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_374909_/Y (NAND2x2_ASAP7_75t_R) - 75.54 5324.08 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_374941_/Y (XNOR2x2_ASAP7_75t_R) - 47.25 5371.33 v wire46725/Y (BUFx3_ASAP7_75t_R) - 16.83 5388.16 v wire7813/Y (BUFx16f_ASAP7_75t_R) - 77.75 5465.91 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_715634_/CON (HAxp5_ASAP7_75t_R) - 20.02 5485.92 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_374961_/Y (INVx4_ASAP7_75t_R) - 27.92 5513.84 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_715636_/CON (HAxp5_ASAP7_75t_R) - 14.52 5528.36 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_715578_/Y (INVx1_ASAP7_75t_R) - 110.73 5639.08 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_715638_/SN (HAxp5_ASAP7_75t_R) - 46.55 5685.64 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_384519_/Y (XNOR2x1_ASAP7_75t_R) - 41.02 5726.65 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_384524_/Y (AND5x2_ASAP7_75t_R) - 63.15 5789.80 v wire30208/Y (BUFx12f_ASAP7_75t_R) - 83.85 5873.65 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09398_/Y (AO221x2_ASAP7_75t_R) - 31.18 5904.83 v wire29780/Y (BUFx12f_ASAP7_75t_R) - 67.42 5972.25 v wire29779/Y (BUFx12f_ASAP7_75t_R) - 66.73 6038.98 v wire29778/Y (BUFx12f_ASAP7_75t_R) - 66.08 6105.06 v wire29777/Y (BUFx12f_ASAP7_75t_R) - 99.39 6204.45 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09399_/Y (OR4x2_ASAP7_75t_R) - 52.91 6257.36 v wire29446/Y (BUFx12f_ASAP7_75t_R) - 74.94 6332.30 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09400_/Y (OR3x2_ASAP7_75t_R) - 11.77 6344.06 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_13817_/Y (NOR2x1_ASAP7_75t_R) - 36.79 6380.86 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_13818_/Y (AND3x4_ASAP7_75t_R) - 22.16 6403.01 ^ wire29198/Y (BUFx3_ASAP7_75t_R) - 16.12 6419.13 ^ wire4813/Y (BUFx16f_ASAP7_75t_R) - 79.70 6498.83 ^ wire29197/Y (BUFx3_ASAP7_75t_R) - 17.06 6515.89 ^ wire4798/Y (BUFx16f_ASAP7_75t_R) - 110.37 6626.27 ^ wire29196/Y (BUFx3_ASAP7_75t_R) - 17.81 6644.08 ^ wire4769/Y (BUFx16f_ASAP7_75t_R) - 71.73 6715.81 ^ wire29195/Y (BUFx12f_ASAP7_75t_R) - 63.73 6779.54 ^ wire29194/Y (BUFx16f_ASAP7_75t_R) - 82.80 6862.34 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_380843_/Y (AND3x4_ASAP7_75t_R) - 80.15 6942.49 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_380845_/Y (XNOR2x2_ASAP7_75t_R) - 40.14 6982.63 v wire24381/Y (BUFx3_ASAP7_75t_R) - 16.96 6999.59 v wire4637/Y (BUFx16f_ASAP7_75t_R) - 169.90 7169.49 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_715676_/CON (HAxp5_ASAP7_75t_R) - 22.93 7192.41 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_380978_/Y (INVx5_ASAP7_75t_R) - 39.12 7231.53 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_715678_/CON (HAxp5_ASAP7_75t_R) - 17.36 7248.89 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_715581_/Y (INVx1_ASAP7_75t_R) - 139.72 7388.61 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_715680_/SN (HAxp5_ASAP7_75t_R) - 46.63 7435.24 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_384526_/Y (XNOR2x1_ASAP7_75t_R) - 43.35 7478.59 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_384530_/Y (AND5x2_ASAP7_75t_R) - 21.89 7500.48 ^ wire14553/Y (BUFx16f_ASAP7_75t_R) - 60.38 7560.86 ^ wire14552/Y (BUFx12f_ASAP7_75t_R) - 78.29 7639.15 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09424_/Y (AO221x2_ASAP7_75t_R) - 46.92 7686.07 ^ wire14505/Y (BUFx12f_ASAP7_75t_R) - 61.68 7747.74 ^ wire14504/Y (BUFx12f_ASAP7_75t_R) - 63.66 7811.41 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09425_/Y (OR4x2_ASAP7_75t_R) - 18.88 7830.29 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09426_/Y (OA21x2_ASAP7_75t_R) - 9.19 7839.48 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_13964_/Y (NOR2x1_ASAP7_75t_R) - 32.41 7871.89 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_13965_/Y (AND3x4_ASAP7_75t_R) - 21.83 7893.72 v wire14423/Y (BUFx3_ASAP7_75t_R) - 16.60 7910.32 v wire2687/Y (BUFx16f_ASAP7_75t_R) - 76.26 7986.58 v wire14422/Y (BUFx3_ASAP7_75t_R) - 17.63 8004.21 v wire2673/Y (BUFx16f_ASAP7_75t_R) - 92.08 8096.29 v max_length14421/Y (BUFx16f_ASAP7_75t_R) - 48.26 8144.55 v wire14420/Y (BUFx12f_ASAP7_75t_R) - 65.64 8210.20 v wire14419/Y (BUFx12f_ASAP7_75t_R) - 78.20 8288.39 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_462481_/Y (AND2x2_ASAP7_75t_R) - 32.72 8321.11 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_462482_/Y (NAND2x2_ASAP7_75t_R) - 51.65 8372.77 ^ wire13868/Y (BUFx16f_ASAP7_75t_R) - 93.74 8466.51 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_463033_/Y (OR2x6_ASAP7_75t_R) - 66.52 8533.02 ^ wire13185/Y (BUFx16f_ASAP7_75t_R) - 125.00 8658.02 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_469024_/Y (NOR2x2_ASAP7_75t_R) - 73.88 8731.90 v wire7777/Y (BUFx16f_ASAP7_75t_R) - 117.54 8849.44 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_477305_/Y (OR3x4_ASAP7_75t_R) - 46.53 8895.97 v wire2121/Y (BUFx3_ASAP7_75t_R) - 16.26 8912.24 v wire1767/Y (BUFx16f_ASAP7_75t_R) - 100.49 9012.73 v max_length2120/Y (BUFx16f_ASAP7_75t_R) - 62.86 9075.59 v max_length2119/Y (BUFx16f_ASAP7_75t_R) - 21.06 9096.65 v wire2118/Y (BUFx16f_ASAP7_75t_R) - 76.88 9173.53 v max_length2117/Y (BUFx16f_ASAP7_75t_R) - 36.80 9210.33 v wire2116/Y (BUFx16f_ASAP7_75t_R) - 83.84 9294.17 v wire2115/Y (BUFx16f_ASAP7_75t_R) - 105.13 9399.30 v wire2101/Y (BUFx16f_ASAP7_75t_R) - 95.85 9495.16 v wire2100/Y (BUFx16f_ASAP7_75t_R) - 52.35 9547.50 v max_length2099/Y (BUFx16f_ASAP7_75t_R) - 38.11 9585.61 v wire2098/Y (BUFx3_ASAP7_75t_R) - 16.02 9601.62 v wire113/Y (BUFx16f_ASAP7_75t_R) - 127.64 9729.27 v max_length2096/Y (BUFx16f_ASAP7_75t_R) - 47.57 9776.84 v wire2094/Y (BUFx3_ASAP7_75t_R) - 16.12 9792.96 v wire70/Y (BUFx16f_ASAP7_75t_R) - 103.02 9895.98 v max_length2093/Y (BUFx16f_ASAP7_75t_R) - 51.33 9947.30 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_521833_/Y (NOR2x1_ASAP7_75t_R) - 14.62 9961.93 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_521834_/Y (AO21x1_ASAP7_75t_R) - 0.01 9961.94 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_719555_/D (DFFHQNx2_ASAP7_75t_R) - 9961.94 data arrival time - -8500.00 8500.00 clock clock_uncore (rise edge) -1952.03 10452.03 clock network delay (propagated) - -10.00 10442.03 clock uncertainty - 0.00 10442.03 clock reconvergence pessimism - 10442.03 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_719555_/CLK (DFFHQNx2_ASAP7_75t_R) - -6.09 10435.94 library setup time - 10435.94 data required time ---------------------------------------------------------- - 10435.94 data required time - -9961.94 data arrival time ---------------------------------------------------------- - 474.00 slack (MET) - - -Startpoint: system/serial_tl_domain/_1267_ - (rising edge-triggered flip-flop clocked by serial_tl_0_clock) -Endpoint: system/serial_tl_domain/_1188_ - (rising edge-triggered flip-flop clocked by serial_tl_0_clock) -Path Group: serial_tl_0_clock -Path Type: max - - Delay Time Description ---------------------------------------------------------- - 0.00 0.00 clock serial_tl_0_clock (rise edge) - 48.42 48.42 clock network delay (propagated) - 0.00 48.42 ^ system/serial_tl_domain/_1267_/CLK (DFFASRHQNx1_ASAP7_75t_R) - 130.15 178.57 ^ system/serial_tl_domain/_1267_/QN (DFFASRHQNx1_ASAP7_75t_R) - 69.41 247.98 v system/serial_tl_domain/_0676_/Y (NOR2x2_ASAP7_75t_R) - 39.09 287.06 v system/serial_tl_domain/_0823_/Y (AND2x4_ASAP7_75t_R) - 22.08 309.14 ^ system/serial_tl_domain/_1128_/CON (HAxp5_ASAP7_75t_R) - 9.17 318.32 v system/serial_tl_domain/_1125_/Y (INVx1_ASAP7_75t_R) - 13.54 331.85 ^ system/serial_tl_domain/_1129_/CON (HAxp5_ASAP7_75t_R) - 8.88 340.73 v system/serial_tl_domain/_1123_/Y (INVx1_ASAP7_75t_R) - 83.77 424.51 v system/serial_tl_domain/_1130_/SN (HAxp5_ASAP7_75t_R) - 41.84 466.35 v load_slew119094/Y (BUFx10_ASAP7_75t_R) - 24.78 491.13 v system/serial_tl_domain/_0863_/Y (AND2x2_ASAP7_75t_R) - 19.53 510.67 v system/serial_tl_domain/_0864_/Y (AND2x2_ASAP7_75t_R) - 23.33 534.00 v system/serial_tl_domain/_0866_/Y (AO32x1_ASAP7_75t_R) - 49.05 583.05 v system/serial_tl_domain/_0870_/Y (OR5x2_ASAP7_75t_R) - 22.11 605.16 v system/serial_tl_domain/_0872_/Y (OA22x2_ASAP7_75t_R) - 0.01 605.17 v system/serial_tl_domain/_1188_/D (DFFHQNx2_ASAP7_75t_R) - 605.17 data arrival time - -8500.00 8500.00 clock serial_tl_0_clock (rise edge) - 47.57 8547.57 clock network delay (propagated) - -10.00 8537.57 clock uncertainty - 0.00 8537.57 clock reconvergence pessimism - 8537.57 ^ system/serial_tl_domain/_1188_/CLK (DFFHQNx2_ASAP7_75t_R) - -4.26 8533.31 library setup time - 8533.31 data required time ---------------------------------------------------------- - 8533.31 data required time - -605.17 data arrival time ---------------------------------------------------------- - 7928.14 slack (MET) - -``` - -``` ->>> report_clock_min_period -clock_uncore period_min = 8026.00 fmax = 124.60 -serial_tl_0_clock period_min = 571.86 fmax = 1748.67 -``` - -``` -$ ./orfs make FLOW_VARIANT=flat elapsed -Log Elapsed seconds -1_1_yosys 4057 -1_1_yosys_hier_report 4063 -2_1_floorplan 393 -2_2_floorplan_io 12 -No elapsed time found in bazel-bin/logs/asap7/ChipTop/flat/2_3_floorplan_tdms.log -2_4_floorplan_macro 1817 -2_5_floorplan_tapcell 678 -2_6_floorplan_pdn 580 -3_1_place_gp_skip_io 877 -3_2_place_iop 38 -3_3_place_gp 7678 -3_4_place_resized 1341 -3_5_place_dp 1934 -4_1_cts 12699 -5_1_grt 68906 -5_2_fillcell 143 -5_3_route 20911 -6_1_merge 556 -6_report 7928 -generate_abstract 1166 -Total 135777 -``` - - -### oharboe -@gudeh Any idea why the colors are so different for estimated and actual routing congestion? The estimate appears to give a very similar looking image, but why is the actual estimated congestion different? - -### rovinski -@oharboe Just a thought, have you properly constrained the async FIFO in SDC? I found this line https://github.com/The-OpenROAD-Project/megaboom/blob/1cce55c772d823ebca0bf8368f1d363a2e546044/constraints-chiptop.sdc#L13. I'm not sure if this covers the async FIFO or not. This would be okay for design space exploration, but for a real implementation it isn't sufficient. See [this very good guide](https://gist.github.com/brabect1/7695ead3d79be47576890bbcd61fe426). - -### oharboe -Regarding the very long global routing times. The global routing is actually fast, it is incremental repair and [reporting times](https://github.com/The-OpenROAD-Project/OpenROAD/issues/4533) that are slow. - diff --git a/gh_discussions/Runtime/4672.md b/gh_discussions/Runtime/4672.md deleted file mode 100644 index 307aae9c095a697b4dd5aee6848e67707526b2f6..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/4672.md +++ /dev/null @@ -1,54 +0,0 @@ -# High congestion - asap7 . Many OA and AO combinational cells in the congestion areas. - -Tool: Global Placement - -Subcategory: Congestion issues - -## Conversation - -### Mudbhatkal -I'm seeing high congestion at global place for a design using asap7 libraries on Openroad. I tried using cell padding with 8 cell sites on the left and right. It helped reduce the congestion a bit, but not enough. I have set a max fanout and tightened the max capacitance in addition to the previous changes, and congestion is still there. I also changed the flow to congestion-driven instead of timing-driven and used the routability check overflow option but still see the congestion although it has decreased slightly. Any suggestions?  - -### maliberty -Can you provide a test case or at least some images of the problem? - -### Mudbhatkal -The RTL was generated through [OpenASIP ](http://openasip.org/) -By testcase do you mean odb file ? If not, how do I generate one ? -new_Cong -The image shows estimated congestion and is captured after detailed placement. - - -### maliberty -`make global_place_issue` should package the test case. Do not post if you are using any confidential data. - -### Mudbhatkal -Here is the testcase : https://tuni-my.sharepoint.com/:u:/g/personal/pooja_mudbhatkal_tuni_fi/EVDGc1VOxIZNhEfmDVLf1JcB56kh2ipprLFusncKTGhAWA?e=NnEMJh -Please let me know if you have access issues - -### maliberty -This design does have an very unusual distribution of cell types. I think you will need to enlarge the block and lower the placement density to compensate for it. - -@gudeh this could be an interesting case to test your routability improvements on. - -### maliberty -Btw, what sort of block is this? - -### gudeh -Hi @Mudbhatkal, I noticed from the log files in the make issue you uploaded that you used yosys version 0.33. Have you tried other Yosys versions? ORFS is currently using 0.38 from a recent update. If you have a local installation of ORFS you can use the 'build_openroad.sh' script. I usually use the following: `./build_openroad.sh --local`. - -Maybe this would provide a different set of logic gates and a different routing scenario. For some reason I was not able to run Yosys on my end with your files. - -### maliberty -Have you tried lowering PLACE_DENSITY as I suggested earlier? - -### stefanottili -vliw cores I’ve seen in the past had wide and deep muxes around the registers. If these are not isolated in a separate rtl hierarchy, synthesis tools tend to ignore mux levels and generate ao/oa spagetti netlists that no R&R tool can untangle. -Physical synthesis tools are supposed to be able to give you a better netlist, but since yosys isn’t one of them, you’ll have to rewrite the rtl of the muxes to get a P&R friendly netlist. -Put each mux level in a separate rtl hierarchy and make sure that synthesis doesn’t flatten them. Separate enables per level of muxing. You should be able to identify mux structures in your netlist. -P&R tools are usually bad at visualizing cone connectivity, but OR has timing critically color coded cone viewing as part of the timing debug. Use it after placement to look at your muxes. - -### Mudbhatkal -[big_tta_fixed.zip](https://github.com/The-OpenROAD-Project/OpenROAD/files/14486076/big_tta_fixed.zip) -This RTL has some fixes but I still see congestion issues. Also tried with synth_hierarchial set to 1. Attaching it here in case someone finds it useful. - diff --git a/gh_discussions/Runtime/4758.md b/gh_discussions/Runtime/4758.md deleted file mode 100644 index 14976836d6ac02741801176bb5c6db8217583949..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/4758.md +++ /dev/null @@ -1,74 +0,0 @@ -# flipflop + inverter + rebuffer + output buffer - -Tool: Clock Tree Synthesis - -Subcategory: Unexpected optimization - -## Conversation - -### oharboe -Is the "rebuffer" buffer superfluous here? - -The "rebuffer" buffer does not exist in placement, only after CTS. - -`make DESIGN_CONFIG=designs/asap7/mock-array/Element/config.mk gui_final`: - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/7a197d43-9270-4233-bebd-620b9cfd5fc8) - - -`make DESIGN_CONFIG=designs/asap7/mock-array/Element/config.mk gui_place`: - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/7d45e527-9062-4a14-b4d3-24125d3c0f46) - - -### maliberty -It is there for timing optimization as the path has negative slack which is addressed post-CTS. Is there a reason to think it superfluous? - -### oharboe -No extra buffers after removing `set_load -pin_load 10 [all_outputs]`: - -Untar [cts-nobuffer.tar.gz](https://github.com/The-OpenROAD-Project/OpenROAD/files/14554686/cts-nobuffer.tar.gz) - -``` -$ ./run-me-mock-array_Element-asap7-base.sh -OpenROAD v2.0-12488-g85f541bb6 -openroad> report_checks -to io_lsbOuts_7 -Startpoint: _755_ (rising edge-triggered flip-flop clocked by clock) -Endpoint: io_lsbOuts_7 (output port clocked by clock_vir) -Path Group: clock_vir -Path Type: max - - Delay Time Description ---------------------------------------------------------- - 0.00 0.00 clock clock (rise edge) - 74.98 74.98 clock network delay (propagated) - 0.00 74.98 ^ _755_/CLK (DFFHQNx2_ASAP7_75t_R) - 45.97 120.95 v _755_/QN (DFFHQNx2_ASAP7_75t_R) - 13.06 134.01 ^ _435_/Y (INVx4_ASAP7_75t_R) - 18.04 152.05 ^ output265/Y (BUFx2_ASAP7_75t_R) - 0.01 152.06 ^ io_lsbOuts_7 (out) - 152.06 data arrival time - - 300.00 300.00 clock clock_vir (rise edge) - 70.00 370.00 clock network delay (ideal) - -20.00 350.00 clock uncertainty - 0.00 350.00 clock reconvergence pessimism --240.00 110.00 output external delay - 110.00 data required time ---------------------------------------------------------- - 110.00 data required time - -152.06 data arrival time ---------------------------------------------------------- - -42.06 slack (VIOLATED) -``` - - -### maliberty -> How do I stop "don't touch" from removing the output buffer so I get the comparison I'm after? - -Set don't touch after the output buffer is created. - -> If I delete set_load -pin_load 10 [all_outputs], the extra buffer goes away. - -Probably the timing improves and the net no longer needs repair. Similarly with the set_driving_cell changing the timing. - diff --git a/gh_discussions/Runtime/4942.md b/gh_discussions/Runtime/4942.md deleted file mode 100644 index 200b188072c11c57265bef85de0fc51b40d44cfe..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/4942.md +++ /dev/null @@ -1,27 +0,0 @@ -# unplaced macros during PDN stage - -Tool: Power Distribution Network Generator - -Subcategory: Macro placement issue - -## Conversation - -### vijayank88 -@oharboe -I came across your test case https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/pdn/test/macros_cells_not_fixed.ok -I am also facing similar error with `macro_placement` command followed by PDN stage throws error. -``` -[WARNING PDN-0234] spm_inst_0 has not been placed and fixed. -[WARNING PDN-0234] spm_inst_1 has not been placed and fixed. -[ERROR PDN-0235] Design has unplaced macros. -PDN-0235 -``` -How to resolve this error? -Thanks in advance... - -### oharboe -@maliberty @vijayank88 I dont recall making this test case... - -### gadfort -@vijayank88 it means you have macros in your design that have not been placed. PDN will only consider placed and locked macros and therefore requires all macros to be locked. Look at your design to find the two macros that have not been placed and locked and fix that - diff --git a/gh_discussions/Runtime/4987.md b/gh_discussions/Runtime/4987.md deleted file mode 100644 index ff5bb6d857b364ad1aaeceaa4a09451cc0d661f6..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/4987.md +++ /dev/null @@ -1,61 +0,0 @@ -# Router violation with proprietary PDK - -Tool: Detailed Routing - -Subcategory: Routing violations - -## Conversation - -### sebinho -Hi Guys, - -I am posting here regarding an issue I am struggling with regarding the detailed routing of OR. -I am using a proprietary PDK, so it is difficult for me to share a complete example of the issue. - -I am constantly running into metal spacing violations on M1 with my 45nm PDK. I systematically get the same error, typically on the same net(s). Because of that, the router always goes up to the max number of iterations (64) and never finds a solution. -Here is a snapshot of the issue at hand. - -![Screenshot from 2024-04-23 17-07-03](https://github.com/The-OpenROAD-Project/OpenROAD/assets/5883454/760a2c49-1fcb-4f10-aa12-ccccc09f12c9) - -You can see on the bottom orange rectangle (this is a VIA between M1 and M2), that the metal spacing is 0.06um. This violates the metal spacing rule of 0.07. M1 is in dark blue. You can see M2 in cyan in the picture below. - -![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/5883454/6a93f3e6-8420-4407-8a70-54afad90ffb2) - -What I noticed is that the routing tool is able to select between 2 types of vias (on its own). Sometimes he selects a horizontal via (like the one that is problematic) and sometimes he takes a vertical via (like the one show in the upper part of the image where the 0.07um rule is respected). -The solution to the problem is quite straightforward when done manually. Simply replace the problematic via with its vertical version. But somehow the tool cannot see that. - -Is there something that can be done for such an issue @maliberty ? I understand that it is not easy to debug as I cannot share my PDK . Apologies for that. -Thanks for your help. - -### maliberty -You said to goes to 64 iterations. Does drt report these violation itself or are they only seen by another drc tool? - -Precision Innovations does provide paid support under NDA if that makes sense for you. - -@osamahammad21 any thoughts? - -### maliberty -Does the drc straddle the boundary of two different cells? (ie the pins are in different instances) - -### sebinho -I reran the tool with different settings and 1 get 1 violation for metal spacing. It is a different location in my design but once again it seems to be at the boundary between 2 different cells. See below red line for separation. - -![via_issue2](https://github.com/The-OpenROAD-Project/OpenROAD/assets/5883454/6e9d737f-dd9b-4bf7-aa9e-4184a338228b) - -Any clue how this could be solved? -Thanks a lot - -### sebinho -@maliberty do you have any recommendations on where to look first in order to speed up the routing for a proprietary PDK? -Now that I added an extra layer of complexity (custom DEF file to specify core/die size and pins locations, custom power grid), it often crash due to not being able to access pins. Or it takes forever to eventually not solve all violations. -Should I incrementally try to simplify the technology (.LEF) file? Any other things I should look into? -My test design (very small module) goes through Sky130/freepdk45 in a matter of minutes even with a very similar DEF file and power grid… -Thanks for your help - -### maliberty -> Should I have the assumption that it is possible to port any rules deck with OpenROAD? - -That's probably too strong a statement (eg we don't support all rules below 12nm) but for older nodes it should be possible. More rules certainly will slow down the router if they make it more difficult to find legal solutions. - -@osamahammad21 am I correct in thinkin we support ADJACENTCUTS / WITHIN? - diff --git a/gh_discussions/Runtime/5058.md b/gh_discussions/Runtime/5058.md deleted file mode 100644 index f5f4d34e4ea89e85e2973808e4a78bdc6edd2f03..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/5058.md +++ /dev/null @@ -1,67 +0,0 @@ -# Does an improved default policy for NUM_CORES in detailed routing exist? - -Tool: Detailed Routing - -Subcategory: Performance analysis - -## Conversation - -### oharboe -Some rough numbers and takeaways: - -First: virtual memory size is the total amount of memory allocated by the process. Resident memory size, measured by make elapsed, is the amount of physical memory in use. Measuring virtual memory size can not be done by the "time" command. - - -The current default policy of using all CPU cores, 48 in my case, vs. 6 below, doesn't have a material difference in memory usage (virtual memory size). I don't have accurate numbers from that, just what I recall from having observed detailed routing in the past on megaboom. In both cases, max resident set is near physical memory(90%+). - -The speed doesn't improve, nor deteriorate above 24 cores(50%). - -Since I don't care if I use virtual memory, I have to set it up anyway, then, based on the measurement below, it would seem that there is no improved policy that exists for megaboom, for the observable parameters I care about. - -It is surprising to me that memory usage in detailed routing isn't a function of number of cores. I don't know why, but I always thought so, to the point where I fooled myself to believing I heard it somewhere. Am I missing something? - - - -Numbers from "make elapsed", so seconds, then megabytes resident memory set. - -NUM_CORES=48 - -5_3_route                                17246          60673 -NUM_CORES=24 -5_3_route                                17516          61012 -NUM_CORES=12 -5_3_route                                28831          60868 -NUM_CORES=6 - -Still it uses more than 64gByte of virtual memory, runs for at least 40000 seconds(didn't finish yet, but I finished my investigations here). - -``` -    PID USER      PR  NI    VIRT    RES    SHR S  %CPU  %MEM     TIME+ COMMAND   -2368797 oyvind    20   0   76,0g  56,6g   1920 R 270,0  90,4     63,22 openroad  -``` - - -### maliberty -Not speeding up over 24 cpu suggests hitting the limit due to serial time per Amdahl. - -I expect most of the memory is in the netlist and segs/vias not the local per thread routing structures. In any case the RSS can't grow beyond the available memory so any excess would be in the virtual size which isn't measured here. - -### maliberty -OR could print vm size as well as rss size if that is useful. The data is available in /proc's statm (or stat or pid). - -### oharboe -Just one more datapoint. After detailed route completed with NUM_CORES=48, this is reported by "top": - -``` - PID USER PR NI VIRT RES SHR S %CPU %MEM TIME+ COMMAND -2424810 oyvind 20 0 80,3g 57,8g 9600 D 57,8 92,2 7d+2h openroad -``` - -From above, with NUM_CORES=6, essentially no difference. - -``` -    PID USER      PR  NI    VIRT    RES    SHR S  %CPU  %MEM     TIME+ COMMAND   -2368797 oyvind    20   0   76,0g  56,6g   1920 R 270,0  90,4     63,22 openroad  -``` - - diff --git a/gh_discussions/Runtime/5158.md b/gh_discussions/Runtime/5158.md deleted file mode 100644 index cbe01679e60e02c3d223f9c249073f048b476b9a..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/5158.md +++ /dev/null @@ -1,23 +0,0 @@ -# [WARNING PDN-0195] Removing 5 via(s) between M2 and M5 at (35.7900 um, 1291.9420 um) for VSS - -Tool: Power Distribution Network Generator - -Subcategory: Warning message - -## Conversation - -### oharboe -What does it mean and what should I do? - -From latest https://github.com/The-OpenROAD-Project/megaboom PDN - -### maliberty -@gadfort any comments? - -### oharboe -I see... Not an unfamiliar situation in EDA tools.... - -In C++ one can generally remove all warnings, not so in FPGA/EDA tools.... - -I going to forego filing a github issue on this case for now. - diff --git a/gh_discussions/Runtime/5168.md b/gh_discussions/Runtime/5168.md deleted file mode 100644 index b9b3fab3aacfffc0dbc312dba957b29f5debd2db..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/5168.md +++ /dev/null @@ -1,62 +0,0 @@ -# Move `_zero` to special nets - -Tool: Detailed Routing - -Subcategory: Routing issue - -## Conversation - -### Blebowski -Hi, -related to previous question, when I proceed to detailed routing, I get: -``` -detailed_route -bottom_routing_layer ME2 -top_routing_layer ME5 -``` -``` -[ERROR DRT-0305] Net zero_ of signal type GROUND is not routable by TritonRoute. Move to special nets. -[ERROR GUI-0070] DRT-0305 -``` - -Before, I created my voltage domain and power-grid like so: -``` -add_global_connection -net VDD -pin_pattern {^VDD$} -power -add_global_connection -net VSS -pin_pattern {^VSS$} -ground - -set_voltage_domain -name VDD_1V2 -power VDD -ground VSS - -define_pdn_grid -name "Core" - - -add_pdn_stripe -layer ME1 -followpins -width 0.2 - -add_pdn_ring -grid "Core" -layers {ME4 ME5} -widths 4.5 -spacings 1.0 -core_offsets {0 0} -add_connect - -add_pdn_stripe -layer ME4 -width 1.5 -pitch 20 -offset 0 -extend_to_core_ring -add_pdn_stripe -layer ME5 -width 1.5 -pitch 20 -offset 0 -extend_to_core_ring - -add_pdn_connect -layers {ME1 ME4} -add_pdn_connect -layers {ME1 ME5} - -pdngen -``` - -I thought that "moving zero_ to special nets" can be accomplished by something like: -``` -assign_ground_net -domain VDD_1V2 -net [get_nets zero_] -``` -But that throws me: -``` -[ERROR ODB-0335] group does not exist -[ERROR GUI-0070] ODB-0335 -``` - -Can you help me out here? -Probably I am just doing something super-stupid... - - -### maliberty -Generally _zero is avoided by using hilomap in yosys. If you are not using yosys then I suggest using insert_tiecells - -### Blebowski -Thanks :) - diff --git a/gh_discussions/Runtime/5273.md b/gh_discussions/Runtime/5273.md deleted file mode 100644 index bdb1ddb0a41d1f472cef46e84a7a74feaf065231..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/5273.md +++ /dev/null @@ -1,30 +0,0 @@ -# Different results locally(laptop, say 32 threads) and on the server(128 threads) - -Tool: Global Placement - -Subcategory: Parallelization issues - -## Conversation - -### oharboe -Q: what happens if we have different number of cores? Should we expect different results after `make place` even if we use manual placement? - -I suppose OpenROAD can use all available CPUs and not heed NUM_CORES in ORFS, so even if I set NUM_CORES to the same, that might not help me get the exact same results? - -I would expect partitioning to affect the results, is this true? - -If so, can I choose the same partitioning even if NUM_CORES differ? - -Any thoughts on different results locally and on the server in terms of what is expected behavior? - -### QuantamHD -It might be this issue https://github.com/The-OpenROAD-Project/OpenROAD/pull/5234 - -### oharboe -For now my assumption is a PEBCAK: that I am running two different versions of OpenROAD in CI and locally(multiple levels of docker hell). - -I tried locally with a single level of docker and got the same results on two machines and varying NUM_CORES. - -### maliberty -fwiw https://github.com/The-OpenROAD-Project/OpenROAD/pull/5234 is merged - diff --git a/gh_discussions/Runtime/5289.md b/gh_discussions/Runtime/5289.md deleted file mode 100644 index f110e43450f9f2f7a3d6a5b564845e360b742eb1..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/5289.md +++ /dev/null @@ -1,183 +0,0 @@ -# UPF support tested with openroad-2024-06-11 - -Tool: Unified Power Format (UPF) - -Subcategory: Missing functionality - -## Conversation - -### titan73 -I have problems reading the upf (2.1) for my design which is an hard IP. - -I have read https://github.com/The-OpenROAD-Project/OpenROAD/discussions/3531. Since it's mark as answered, I open a new one. - -Some command are missing: - - upf_version - - create_supply_port - - create_supply_net - - connect_supply_net - - create_supply_set - - set_port_attributes - - add_port_state - - create_pst - - add_pst_state - -And some commands have missing options: - - -include_scope and -supply missing from create_power_domain - - -isolation_supply, -sink and -source missing from set_isolation (set_level_shifter has sink and -source) - -I have also several questions. - -1) What upf version openroad is supposed to support? - -2) Same question for all examples in git? - - ./test/upf/mpd_top.upf - - ./test/upf/mpd_aes.upf - - ./src/upf/test/data/mpd_top/mpd_top_ls.upf - - ./src/upf/test/data/mpd_top/mpd_top.upf - - ./src/upf/test/data/mpd_top/mpd_top_combined.upf - - ./src/ifp/test/upf/mpd_top.upf - - ./src/ifp/test/upf/mpd_shifter.upf - -3) Are there reporting command related to upf (power domains, supply ports, ...)? I searched but didn't find any. - -4) set_level_shifter has 2 options -input_supply and -output_supply that take supply net. Where these nets are supposed to be defined? - Morover where do these options comes from? UPF 2.0 and 2.1 do no have them. They have -input_supply_set and -output_supply_set that take supply sets (and not nets). - -5) How supply ports are supposed to be created in openroad since there are no command create_supply_port. - -Thanks in advance - - -### maliberty - -I'm glad to have someone trying to use this functionality as we have developed it but need people to test and give feedback. - -UPF is a large standard (> 500 pages) and OR supports only a core set of functionality. OR is only concerned with the design creation aspects of UPF and not the functional behavior which it doesn't control. We are open to enhancing the set we support as the community needs but don't expect to reach 100% coverage anytime soon. We have worked off the 1801-2018 standard. - -Reporting commands are a hole. What would you like to see in this area? It shouldn't be hard to add some. You can query odb directly or use write_upf today. - -set_level_shifter takes -input_port -output_port. It looks like those should have been -input_supply/-output_supply. I'll fix that. - -Power nets either come in explicitly in the netlist or are created by pdn. You can look at set_voltage_domain in https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/pdn/test/power_switch_upf_regions.tcl as an example. We could add commands to create them from UPF though you will still need to configure pdn for an actual implementation as UPF is quite logical and not physical in its description. - -### titan73 -Great! I'm happy to help. - -I'll prepare a simplified upf of our design. -Note that we've just converted the power state table from 1.0 (using add_port_state, create_pst and add_pst_state which are deprecated) to 2.1 with add_power_state. This was planned for later but if something is done in openroad, it's better to implement something which is not deprecated. - -I'll think about with my colleage about what could be added for reporting. In the meantime, I'll try querying odb. How can I do that? I don't see any command that accesses the database. - -The input netlist from synthesis does not have any power information in our flow & tools although the level shifters are inserted. And Yosys does not support upf anyway. We'd like to create power ports in upf to kept compatibility with other flows & tools so we use the same upf everywhere. - - Thanks! - -### titan73 -Here is the simplified version with add_power_state: - -upf_version 2.1 - - -create_supply_port VDDD1V2 -create_supply_port -direction inout VDDD - - -create_supply_net VDDD -create_supply_net VDDD1V2 -create_supply_net GNDD - - -connect_supply_net -ports VDDD VDDD -connect_supply_net -ports VDDD1V2 VDDD1V2 -connect_supply_net -ports GNDD GNDD - - -create_supply_set ss_GNDD_VDDD1V2 -function {ground GNDD} -function {power VDDD1V2} -create_supply_set ss_GNDD_VDDD -function {ground GNDD} -function {power VDDD} - - -create_power_domain PD1 -include_scope -supply {primary ss_GNDD_VDDD} -create_power_domain PD2 -elements pd1v2 -supply {primary ss_GNDD_VDDD1V2} - - -# One signal does not have the default power of its power domain -set_port_attributes -ports out_signal_1v2 -receiver_supply ss_GNDD_VDDD1V2 - - -add_power_state ss_GNDD_VDDD1V2 \ - -state {on_1v2 -supply_expr {(power == {FULL_ON 1.08}) && (ground == {FULL_ON 0})}} \ - -state {off_1v2 -supply_expr {(power == {OFF})}} - -add_power_state ss_GNDD_VDDD \ - -state {on_std -supply_expr {(power == {FULL_ON 2.25}) && (ground == {FULL_ON 0})}} - -add_power_state PD1 \ - -state {dig_on -logic_expr { \ - (ss_GNDD_VDDD1V2 == on_1v2) && \ - (ss_GNDD_VDDD == on_std)}} \ - -state {dig_off -logic_expr { \ - (ss_GNDD_VDDD1V2 == off_1v2) && \ - (ss_GNDD_VDDD == on_std)}} - - -set_isolation iso_PD2_from_ss_GNDD_VDDD1V2_to_ss_GNDD_VDDD \ - -clamp_value 0 \ - -domain PD2 \ - -isolation_sense low \ - -isolation_signal pd1v2/i_isolation \ - -isolation_supply ss_GNDD_VDDD \ - -sink ss_GNDD_VDDD \ - -source ss_GNDD_VDDD1V2 - - -set_level_shifter ls_PD2_ss_GNDD_VDDD1V2_to_ss_GNDD_VDDD \ - -domain PD2 \ - -sink ss_GNDD_VDDD \ - -source ss_GNDD_VDDD1V2 - -set_level_shifter ls_PD2_ss_GNDD_VDDD_to_ss_GNDD_VDDD1V2 \ - -domain PD2 \ - -sink ss_GNDD_VDDD1V2 \ - -source ss_GNDD_VDDD - - -### titan73 -I tested and checked our upf with add_power_state with our design in our flow & tools and everything is fine. -So I can test openroad when it's available and check against our flow. - - -### titan73 -Not sure it worth it to implement legacy 1.0 support but in case you implement it in a row, as it does the same thing, here is the old code: - -add_port_state VDDD \ - -state [list VDDD_nom 2.25] - -add_port_state VDDD1V2 \ - -state [list VDDD1V2_nom 1.08] \ - -state [list VDDD1V2_off off] - -add_port_state GNDD \ - -state [list gnd_on 0] - -create_pst USB_pst -supplies {VDDD VDDD1V2 GNDD} -add_pst_state pd1v2_on -pst USB_pst -state {VDDD_nom VDDD1V2_nom gnd_on} -add_pst_state pd1v2_off -pst USB_pst -state {VDDD_nom VDDD1V2_off gnd_on} - - -### titan73 -Any news on this topic? - -### titan73 -Note that if power ports are not created in upf, the associated pins cannot be imported from floorplan .def file with read_def. -Since pdn is run after the .def import, we can't rely on pdn for power ports creation. - -[WARNING ODB-0247] skipping undefined pin VDDD1V2 encountered in FLOORPLAN DEF -[WARNING ODB-0247] skipping undefined pin GNDD encountered in FLOORPLAN DEF -[WARNING ODB-0247] skipping undefined pin VDDD_FTP encountered in FLOORPLAN DEF -[WARNING ODB-0247] skipping undefined pin GNDSUB encountered in FLOORPLAN DEF -[WARNING ODB-0247] skipping undefined pin GNDA_FTP encountered in FLOORPLAN DEF -[WARNING ODB-0247] skipping undefined pin VDDD encountered in FLOORPLAN DEF -[WARNING ODB-0247] skipping undefined pin VDDA_FTP encountered in FLOORPLAN DEF - - diff --git a/gh_discussions/Runtime/754.md b/gh_discussions/Runtime/754.md deleted file mode 100644 index 778952a17535c3ed0d747bdfa62784988ee7d0bf..0000000000000000000000000000000000000000 --- a/gh_discussions/Runtime/754.md +++ /dev/null @@ -1,56 +0,0 @@ -# [WARNING DPL-0004/5/6] Warning Details - -Tool: Detailed Placement - -Subcategory: Detailed Placement issue - -## Conversation - -### dineshannayya -Can any one give more details on the these WARNING & also how to solve these issue. - -[WARNING DPL-0004] Placed in rows check failed (4). -[WARNING DPL-0005] Overlap check failed (1). -[WARNING DPL-0006] Site check failed (4). - -I am trying to do detailed placement using openlane flow and 99% of block are hard core, only 32 cells are there at top-level -There is good amount of free space available. still tool fails with these error. - - - -### maliberty -It is a check at the end of placement to make sure the result is non-overlapping. It suggests a placement failure but its hard to say anything more without a test case. Can you provide one? - -### dineshannayya -The project had 99% hard macro with less than 32 other cells and there was -more than 30% free space. Still openroad detailed route was placing -overlapping cells with hard macros & giving DPL-4/5/6 warning. - -Finally I noticed the issue was resolved after changing -diamond_search_hight more than *250*. - -Can give more details on how increased diamond_search_hight value helped -here ? - - - -On Thu, Jun 17, 2021 at 7:17 PM Matt Liberty ***@***.***> -wrote: - -> It is a check at the end of placement to make sure the result is -> non-overlapping. It suggests a placement failure but its hard to say -> anything more without a test case. Can you provide one? -> -> — -> You are receiving this because you authored the thread. -> Reply to this email directly, view it on GitHub -> , -> or unsubscribe -> -> . -> - - -### maliberty -I would guess that global placement left cells very far from any legal location. You might look at a post global-placement def to see. - diff --git a/gh_discussions/mapping.json b/gh_discussions/mapping.json deleted file mode 100644 index ac1a6d30a482c581d7261b7a72d7ff9e8e87490e..0000000000000000000000000000000000000000 --- a/gh_discussions/mapping.json +++ /dev/null @@ -1,1034 +0,0 @@ -{ - "Query/5451.md": { - "url": "https://github.com/The-OpenROAD-Project/OpenROAD/discussions/5451", - "tool": "OpenDB", - "author": "CathedralsOfSand", - "date": "2024-07-25T20:58:09Z" - }, - "Feature Request/5420.md": { - "url": "https://github.com/The-OpenROAD-Project/OpenROAD/discussions/5420", - "tool": "Design for Test", - "author": "ThomasGeroudet", - "date": "2024-07-22T17:49:42Z" - }, - "Bug/5333.md": { - "url": "https://github.com/The-OpenROAD-Project/OpenROAD/discussions/5333", - "tool": "Power Distribution Network Generator", - "author": "titan73", - "date": "2024-07-03T17:20:45Z" - }, - "Runtime/5289.md": { - "url": "https://github.com/The-OpenROAD-Project/OpenROAD/discussions/5289", - "tool": "Unified Power Format (UPF)", - "author": "titan73", - "date": "2024-06-26T12:46:36Z" - }, - "Documentation/5312.md": { - "url": "https://github.com/The-OpenROAD-Project/OpenROAD/discussions/5312", - "tool": "OpenDB", - "author": "titan73", - "date": "2024-07-01T10:08:48Z" - }, - "Runtime/5273.md": { - "url": "https://github.com/The-OpenROAD-Project/OpenROAD/discussions/5273", - "tool": "Global Placement", - "author": "oharboe", - "date": "2024-06-22T12:24:35Z" - }, - "Query/5249.md": { - "url": "https://github.com/The-OpenROAD-Project/OpenROAD/discussions/5249", - "tool": "Global Routing", - "author": "doo3yoon", - "date": "2024-06-15T19:19:40Z" - }, - "Configuration/5213.md": { - "url": "https://github.com/The-OpenROAD-Project/OpenROAD/discussions/5213", - "tool": "OpenDB", - "author": "Dandy201", - "date": "2024-06-08T01:49:39Z" - }, - "Configuration/5199.md": { - "url": "https://github.com/The-OpenROAD-Project/OpenROAD/discussions/5199", - "tool": "Initialize Floorplan", - "author": "Blebowski", - "date": "2024-06-04T14:25:31Z" - }, - "Runtime/5168.md": { - "url": "https://github.com/The-OpenROAD-Project/OpenROAD/discussions/5168", - "tool": "Detailed Routing", - "author": "Blebowski", - "date": "2024-05-27T11:09:21Z" - }, - "Query/2745.md": { - "url": "https://github.com/The-OpenROAD-Project/OpenROAD/discussions/2745", - "tool": "Global Placement", - "author": "maliberty", - "date": "2023-01-13T00:19:27Z" - }, - "Runtime/5158.md": { - "url": "https://github.com/The-OpenROAD-Project/OpenROAD/discussions/5158", - "tool": "Power Distribution Network Generator", - "author": "oharboe", - "date": "2024-05-24T12:27:51Z" - }, - "Query/5087.md": { - "url": "https://github.com/The-OpenROAD-Project/OpenROAD/discussions/5087", - "tool": "OpenDB", - "author": "OuDret", - "date": "2024-05-10T15:07:48Z" - }, - "Build/5101.md": { - "url": "https://github.com/The-OpenROAD-Project/OpenROAD/discussions/5101", - "tool": null, - "author": "sebinho", - "date": "2024-05-14T09:34:01Z" - }, - "Runtime/5058.md": { - "url": "https://github.com/The-OpenROAD-Project/OpenROAD/discussions/5058", - "tool": "Detailed Routing", - "author": "oharboe", - "date": "2024-05-07T06:41:44Z" - }, - "Configuration/5065.md": { - "url": "https://github.com/The-OpenROAD-Project/OpenROAD/discussions/5065", - "tool": "OpenDB", - "author": "bittnada", - "date": "2024-05-08T03:04:19Z" - }, - "Feature Request/3531.md": { - "url": "https://github.com/The-OpenROAD-Project/OpenROAD/discussions/3531", - "tool": "Unified Power Format (UPF)", - "author": "kareefardi", - "date": "2023-06-26T14:57:14Z" - }, - "Feature Request/5041.md": { - "url": "https://github.com/The-OpenROAD-Project/OpenROAD/discussions/5041", - "tool": "Hierarchical Macro Placement", - "author": "vijayank88", - "date": "2024-05-03T10:30:40Z" - }, - "Runtime/4987.md": { - "url": "https://github.com/The-OpenROAD-Project/OpenROAD/discussions/4987", - "tool": "Detailed Routing", - "author": "sebinho", - "date": "2024-04-23T15:24:22Z" - }, - "Build/4956.md": { - "url": "https://github.com/The-OpenROAD-Project/OpenROAD/discussions/4956", - "tool": null, - "author": "sebinho", - "date": "2024-04-16T10:43:40Z" - }, - "Bug/4845.md": { - "url": "https://github.com/The-OpenROAD-Project/OpenROAD/discussions/4845", - "tool": "Initialize Floorplan", - "author": "b62833", - "date": "2024-03-23T23:52:02Z" - }, - "Runtime/4942.md": { - "url": "https://github.com/The-OpenROAD-Project/OpenROAD/discussions/4942", - "tool": "Power Distribution Network Generator", - "author": "vijayank88", - "date": "2024-04-12T07:43:32Z" - }, - "Query/4890.md": { - "url": "https://github.com/The-OpenROAD-Project/OpenROAD/discussions/4890", - "tool": "Pin Placer", - "author": "donn", - "date": "2024-04-02T18:35:57Z" - }, - "Query/4417.md": { - "url": "https://github.com/The-OpenROAD-Project/OpenROAD/discussions/4417", - "tool": "OpenSTA", - "author": "LT-HB", - "date": "2023-12-20T08:38:21Z" - }, - "Feature Request/4819.md": { - "url": "https://github.com/The-OpenROAD-Project/OpenROAD/discussions/4819", - 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