# A lot of slew in asap7/sram-64x16 Tool: Clock Tree Synthesis Subcategory: Timing analysis issue ## Conversation ### oharboe Is this amount of slew expected on the clock pin to the SRAM? `SRAM2RW16x32_2/CE2` is one of two clocks to the SRAM, the SRAM has one read and one write port. ``` make DESIGN_CONFIG=designs/asap7/sram-64x16/config.mk ``` ``` >>> report_checks -path_delay max -fields {slew net cap} -to _351_/D Startpoint: SRAM2RW16x32_2 (rising edge-triggered flip-flop clocked by io_clk) Endpoint: _351_ (falling edge-triggered flip-flop clocked by io_clk') Path Group: io_clk Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 clock io_clk (rise edge) 241.44 241.44 clock network delay (propagated) 150.83 0.00 241.44 ^ SRAM2RW16x32_2/CE2 (SRAM2RW16x32) 40.24 202.07 443.51 v SRAM2RW16x32_2/O2[4] (SRAM2RW16x32) 1 9.73 _SRAM2RW16x32_2_O2[4] (net) 53.97 5.14 448.65 v _351_/D (DFFLQNx1_ASAP7_75t_R) 448.65 data arrival time 500.00 500.00 clock io_clk' (fall edge) 186.47 686.47 clock network delay (propagated) 0.52 686.99 clock reconvergence pessimism 686.99 v _351_/CLK (DFFLQNx1_ASAP7_75t_R) -22.88 664.11 library setup time 664.11 data required time ----------------------------------------------------------------------------- 664.11 data required time -448.65 data arrival time ----------------------------------------------------------------------------- 215.46 slack (MET) ``` ### maliberty Probably not but without a test case not much more can be said. ### oharboe `make DESIGN_CONFIG=designs/asap7/sram-64x16/config.mk issue_cts` standalone testcase: 1. Unzip (note! bzip2 compression so that it would fit into github limit) [slew.zip](https://github.com/The-OpenROAD-Project/OpenROAD/files/12294012/slew.zip) 2. run `./run*.sh` 3. Enter `report_checks -path_delay max -fields {slew net cap} -to _351_/D` in the GUI You should get: ``` >>> report_checks -path_delay max -fields {slew net cap} -to _351_/D Startpoint: SRAM2RW16x32_2 (rising edge-triggered flip-flop clocked by io_clk) Endpoint: _351_ (falling edge-triggered flip-flop clocked by io_clk') Path Group: io_clk Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 clock io_clk (rise edge) 274.66 274.66 clock network delay (propagated) 186.64 0.00 274.66 ^ SRAM2RW16x32_2/CE2 (SRAM2RW16x32) 35.53 205.56 480.22 v SRAM2RW16x32_2/O2[4] (SRAM2RW16x32) 1 7.54 _SRAM2RW16x32_2_O2[4] (net) 47.76 5.26 485.49 v _351_/D (DFFLQNx1_ASAP7_75t_R) 485.49 data arrival time 500.00 500.00 clock io_clk' (fall edge) 212.33 712.33 clock network delay (propagated) 0.00 712.33 clock reconvergence pessimism 712.33 v _351_/CLK (DFFLQNx1_ASAP7_75t_R) -21.20 691.13 library setup time 691.13 data required time ----------------------------------------------------------------------------- 691.13 data required time -485.49 data arrival time ----------------------------------------------------------------------------- 205.64 slack (MET) ``` ### maliberty Converted to an issue https://github.com/The-OpenROAD-Project/OpenROAD/issues/3817