diff --git "a/verilog/High-Performance-Tensor-Processing-Engines_class_bench.jsonl" "b/verilog/High-Performance-Tensor-Processing-Engines_class_bench.jsonl" new file mode 100644--- /dev/null +++ "b/verilog/High-Performance-Tensor-Processing-Engines_class_bench.jsonl" @@ -0,0 +1,5 @@ +{"repo_name": "High-Performance-Tensor-Processing-Engines", "file_name": "/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/inv_unit_nor_out.v", "inference_info": {"prefix_code": "", "suffix_code": "", "middle_code": "module inv_unit_nor_out(\n input wire a ,\n input wire b ,\n output wire xor_o , \n output wire nor_o \n );\n wire a_AND_b ; \n wire a_NOR_b ; \n assign a_AND_b = a & b;\n assign a_NOR_b = ~(a | b);\n assign xor_o = ~(a_AND_b | a_NOR_b);\n assign nor_o = a_NOR_b;\nendmodule", "code_description": null, "fill_type": "CLASS_TYPE", "language_type": "verilog", "sub_task_type": null}, "context_code": [["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/inv_unit_nor_out.v", "module inv_unit_nor_out(\n input wire a ,\n input wire b ,\n \n output wire xor_o , \n output wire nor_o \n );\n \n\n wire a_AND_b ; \n wire a_NOR_b ; \n \n \n assign a_AND_b = a & b;\n \n \n assign a_NOR_b = ~(a | b);\n \n\n assign xor_o = ~(a_AND_b | a_NOR_b);\n assign nor_o = a_NOR_b;\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/inv_unit_nor_out.v", "module inv_unit_nor_out(\n input wire a ,\n input wire b ,\n \n output wire xor_o , \n output wire nor_o \n );\n \n\n wire a_AND_b ; \n wire a_NOR_b ; \n \n \n assign a_AND_b = a & b;\n \n \n assign a_NOR_b = ~(a | b);\n \n\n assign xor_o = ~(a_AND_b | a_NOR_b);\n assign nor_o = a_NOR_b;\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/inv_unit_nor_out.v", "module inv_unit_nor_out(\n input wire a ,\n input wire b ,\n \n output wire xor_o , \n output wire nor_o \n );\n \n\n wire a_AND_b ; \n wire a_NOR_b ; \n \n \n assign a_AND_b = a & b;\n \n \n assign a_NOR_b = ~(a | b);\n \n\n assign xor_o = ~(a_AND_b | a_NOR_b);\n assign nor_o = a_NOR_b;\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/inv_unit.v", "module inv_unit(\n input wire a ,\n input wire b ,\n output wire xor_o , \n output wire or_o \n );\n \n wire aORb ; \n wire aNANDb ; \n \n assign aORb = a | b;\n assign aNANDb = ~(a & b);\n assign xor_o = (aORb & aNANDb);\n assign or_o = aORb;\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/inv_unit.v", "module inv_unit(\n input wire a ,\n input wire b ,\n output wire xor_o , \n output wire or_o \n );\n \n wire aORb ; \n wire aNANDb ; \n \n assign aORb = a | b;\n assign aNANDb = ~(a & b);\n assign xor_o = (aORb & aNANDb);\n assign or_o = aORb;\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/inv_unit.v", "module inv_unit(\n input wire a ,\n input wire b ,\n output wire xor_o , \n output wire or_o \n );\n \n wire aORb ; \n wire aNANDb ; \n \n assign aORb = a | b;\n assign aNANDb = ~(a & b);\n assign xor_o = (aORb & aNANDb);\n assign or_o = aORb;\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/inv_unit.v", "module inv_unit(\n input wire a ,\n input wire b ,\n output wire xor_o , \n output wire or_o \n );\n \n wire aORb ; \n wire aNANDb ; \n \n assign aORb = a | b;\n assign aNANDb = ~(a & b);\n assign xor_o = (aORb & aNANDb);\n assign or_o = aORb;\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/booth_partial_product_generator.v", "module booth_partial_product_generator(\n input wire [2:0] operand_slice_a, \n input wire [7:0] operand_b, \n input wire [8:0] operand_b_neg, \n output wire [9:0] pp_out \n );\n \n wire [8:0] pp_source ;\n //----------------------------------------------------\n //| pp | flag_2x | flag_s1 | flag_s2 |\n //----------------------------------------------------\n //| operand_b | 0 | 0 | 1 |\n //| -operand_b | 0 | 1 | 0 |\n //| 2operand_b | 1 | 0 | 1 | \n //| -2operand_b | 1 | 1 | 0 |\n //| 0 | x | 0 | 0 | \n //----------------------------------------------------\n wire not_c2 ; \n wire c1_and_c0 ; \n wire c1_nor_c0 ; \n wire nor_o2 ; \n \n wire flag_2x ;\n wire flag_s1 ;\n wire flag_s2 ;\n \n assign not_c2 = ~operand_slice_a[2] ;\n assign c1_and_c0 = operand_slice_a[1] & operand_slice_a[0] ;\n assign c1_nor_c0 = ~(operand_slice_a[1] | operand_slice_a[0]) ;\n assign nor_o2 = ~(c1_and_c0 | c1_nor_c0) ;\n \n assign flag_2x = ~nor_o2 ;\n assign flag_s1 = ~(not_c2 | c1_and_c0) ;\n assign flag_s2 = ~(operand_slice_a[2] | c1_nor_c0) ;\n \n wire flag_not_2x = nor_o2; \n \n assign pp_source = (({{operand_b[7]}, operand_b} & {9{flag_s2}}) | (operand_b_neg & {9{flag_s1}}));\n assign pp_out[0] = (!flag_2x & pp_source[0]);\n assign pp_out[8:1] = (({8{flag_2x}} & pp_source[7:0]) | ({8{flag_not_2x}} & pp_source[8:1]));\n assign pp_out[9] = pp_source[8];\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/booth_partial_product_generator.v", "module booth_partial_product_generator(\n input wire [2:0] operand_slice_a, \n input wire [7:0] operand_b, \n input wire [8:0] operand_b_neg, \n output wire [9:0] pp_out \n );\n \n wire [8:0] pp_source ;\n //----------------------------------------------------\n //| pp | flag_2x | flag_s1 | flag_s2 |\n //----------------------------------------------------\n //| operand_b | 0 | 0 | 1 |\n //| -operand_b | 0 | 1 | 0 |\n //| 2operand_b | 1 | 0 | 1 | \n //| -2operand_b | 1 | 1 | 0 |\n //| 0 | x | 0 | 0 | \n //----------------------------------------------------\n \n //----------------------------------------------------\n //operand_slice_a[1] operand_slice_a[0] operand_slice_a[-1] | pp \n //----------------------------------------------------\n // 0 0 0 | 0 \n // 0 0 1 | operand_b \n // 0 1 0 | operand_b \n // 0 1 1 | 2operand_b \n // 1 0 0 | -2operand_b \n // 1 0 1 | -operand_b \n // 1 1 0 | -operand_b \n // 1 1 1 | 0 \n //----------------------------------------------------\n \n wire not_c2 ; \n wire c1_and_c0 ; \n wire c1_nor_c0 ; \n wire nor_o2 ; \n \n wire flag_2x ;\n wire flag_s1 ;\n wire flag_s2 ;\n \n assign not_c2 = ~operand_slice_a[2] ;\n assign c1_and_c0 = operand_slice_a[1] & operand_slice_a[0] ;\n assign c1_nor_c0 = ~(operand_slice_a[1] | operand_slice_a[0]) ;\n assign nor_o2 = ~(c1_and_c0 | c1_nor_c0) ;\n \n assign flag_2x = ~nor_o2 ;\n assign flag_s1 = ~(not_c2 | c1_and_c0) ;\n assign flag_s2 = ~(operand_slice_a[2] | c1_nor_c0) ;\n \n wire flag_not_2x = nor_o2; \n assign pp_source = (({{operand_b[7]}, operand_b} & {9{flag_s2}}) | (operand_b_neg & {9{flag_s1}}));\n assign pp_out[0] = (!flag_2x & pp_source[0]);\n assign pp_out[8:1] = (({8{flag_2x}} & pp_source[7:0]) | ({8{flag_not_2x}} & pp_source[8:1]));\n assign pp_out[9] = pp_source[8];\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/booth_partial_product_generator.v", "module booth_partial_product_generator(\n input wire [2:0] operand_slice_a, \n input wire [7:0] operand_b, \n input wire [8:0] operand_b_neg, \n output wire [9:0] pp_out \n );\n \n wire [8:0] pp_source ;\n //----------------------------------------------------\n //| pp | flag_2x | flag_s1 | flag_s2 |\n //----------------------------------------------------\n //| operand_b | 0 | 0 | 1 |\n //| -operand_b | 0 | 1 | 0 |\n //| 2operand_b | 1 | 0 | 1 | \n //| -2operand_b | 1 | 1 | 0 |\n //| 0 | x | 0 | 0 | \n //----------------------------------------------------\n \n //----------------------------------------------------\n //operand_slice_a[1] operand_slice_a[0] operand_slice_a[-1] | pp \n //----------------------------------------------------\n // 0 0 0 | 0 \n // 0 0 1 | operand_b \n // 0 1 0 | operand_b \n // 0 1 1 | 2operand_b \n // 1 0 0 | -2operand_b \n // 1 0 1 | -operand_b \n // 1 1 0 | -operand_b \n // 1 1 1 | 0 \n //----------------------------------------------------\n \n wire not_c2 ; \n wire c1_and_c0 ; \n wire c1_nor_c0 ; \n wire nor_o2 ; \n \n wire flag_2x ;\n wire flag_s1 ;\n wire flag_s2 ;\n \n assign not_c2 = ~operand_slice_a[2] ;\n assign c1_and_c0 = operand_slice_a[1] & operand_slice_a[0] ;\n assign c1_nor_c0 = ~(operand_slice_a[1] | operand_slice_a[0]) ;\n assign nor_o2 = ~(c1_and_c0 | c1_nor_c0) ;\n \n assign flag_2x = ~nor_o2 ;\n assign flag_s1 = ~(not_c2 | c1_and_c0) ;\n assign flag_s2 = ~(operand_slice_a[2] | c1_nor_c0) ;\n \n wire flag_not_2x = nor_o2; \n assign pp_source = (({{operand_b[7]}, operand_b} & {9{flag_s2}}) | (operand_b_neg & {9{flag_s1}}));\n assign pp_out[0] = (!flag_2x & pp_source[0]);\n assign pp_out[8:1] = (({8{flag_2x}} & pp_source[7:0]) | ({8{flag_not_2x}} & pp_source[8:1]));\n assign pp_out[9] = pp_source[8];\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/booth_partial_product_generator.v", "module booth_partial_product_generator(\n input wire [2:0] operand_slice_a, \n input wire [7:0] operand_b, \n input wire [8:0] operand_b_neg, \n output wire [9:0] pp_out \n );\n \n wire [8:0] pp_source ;\n //----------------------------------------------------\n //| pp | flag_2x | flag_s1 | flag_s2 |\n //----------------------------------------------------\n //| operand_b | 0 | 0 | 1 |\n //| -operand_b | 0 | 1 | 0 |\n //| 2operand_b | 1 | 0 | 1 | \n //| -2operand_b | 1 | 1 | 0 |\n //| 0 | x | 0 | 0 | \n //----------------------------------------------------\n \n //----------------------------------------------------\n //operand_slice_a[1] operand_slice_a[0] operand_slice_a[-1] | pp \n //----------------------------------------------------\n // 0 0 0 | 0 \n // 0 0 1 | operand_b \n // 0 1 0 | operand_b \n // 0 1 1 | 2operand_b \n // 1 0 0 | -2operand_b \n // 1 0 1 | -operand_b \n // 1 1 0 | -operand_b \n // 1 1 1 | 0 \n //----------------------------------------------------\n \n wire not_c2 ; \n wire c1_and_c0 ; \n wire c1_nor_c0 ; \n wire nor_o2 ; \n \n wire flag_2x ;\n wire flag_s1 ;\n wire flag_s2 ;\n \n assign not_c2 = ~operand_slice_a[2] ;\n assign c1_and_c0 = operand_slice_a[1] & operand_slice_a[0] ;\n assign c1_nor_c0 = ~(operand_slice_a[1] | operand_slice_a[0]) ;\n assign nor_o2 = ~(c1_and_c0 | c1_nor_c0) ;\n \n assign flag_2x = ~nor_o2 ;\n assign flag_s1 = ~(not_c2 | c1_and_c0) ;\n assign flag_s2 = ~(operand_slice_a[2] | c1_nor_c0) ;\n \n wire flag_not_2x = nor_o2; \n assign pp_source = (({{operand_b[7]}, operand_b} & {9{flag_s2}}) | (operand_b_neg & {9{flag_s1}}));\n assign pp_out[0] = (!flag_2x & pp_source[0]);\n assign pp_out[8:1] = (({8{flag_2x}} & pp_source[7:0]) | ({8{flag_not_2x}} & pp_source[8:1]));\n assign pp_out[9] = pp_source[8];\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/inv_conveter_8.v", "module inv_converter_8(\n input wire [7:0] data_i ,\n output wire[8:0] inv_o \n );\n \n wire [5:0] wire_cout ; \n wire not_o ; \n\n assign inv_o[0] = data_i[0];\n \n inv_unit inv_unit_bit1(\n .a (data_i[1] ),\n .b (data_i[0] ),\n .xor_o (inv_o[1] ), \n .or_o (wire_cout[0] ) \n );\n \n genvar i;\n generate \n for(i=2;i<=5;i=i+1) begin\n inv_unit inv_unit_inst(\n .a (data_i[i] ),\n .b (wire_cout[i-2] ),\n .xor_o (inv_o[i] ), \n .or_o (wire_cout[i-1] ) \n );\n end\n endgenerate\n \n inv_unit_nor_out inv_unit_nor_out_inst_6(\n .a (data_i[6] ),\n .b (wire_cout[4] ),\n .xor_o (inv_o[6] ), \n .nor_o (wire_cout[5] ) \n );\n \n inv_unit_nor_out inv_unit_nor_out_inst_7(\n .a (data_i[7] ),\n .b (not_o ), \n .xor_o (inv_o[7] ), \n .nor_o ( ) \n );\n \n \n\n assign not_o = ~wire_cout[5] ;\n \n\n assign inv_o[8] = ~(wire_cout[5] | data_i[7]);\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/inv_conveter_8.v", "// 取反 加1 （-1*A、-2*A 都要进行取反加1）\nmodule inv_converter_8(\n input wire [7:0] data_i ,\n output wire[8:0] inv_o \n );\n \n wire [5:0] wire_cout ; \n wire not_o ; \n\n assign inv_o[0] = data_i[0];\n \n inv_unit inv_unit_bit1(\n .a (data_i[1] ),\n .b (data_i[0] ),\n .xor_o (inv_o[1] ), \n .or_o (wire_cout[0] ) \n );\n \n genvar i;\n generate \n for(i=2;i<=5;i=i+1) begin\n inv_unit inv_unit_inst(\n .a (data_i[i] ),\n .b (wire_cout[i-2] ),\n .xor_o (inv_o[i] ), \n .or_o (wire_cout[i-1] ) \n );\n end\n endgenerate\n \n inv_unit_nor_out inv_unit_nor_out_inst_6(\n .a (data_i[6] ),\n .b (wire_cout[4] ),\n .xor_o (inv_o[6] ), \n .nor_o (wire_cout[5] ) \n );\n \n inv_unit_nor_out inv_unit_nor_out_inst_7(\n .a (data_i[7] ),\n .b (not_o ), \n .xor_o (inv_o[7] ), \n .nor_o ( ) \n );\n \n \n\n assign not_o = ~wire_cout[5] ;\n \n\n assign inv_o[8] = ~(wire_cout[5] | data_i[7]);\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/inv_conveter_8.v", "// 取反 加1 （-1*A、-2*A 都要进行取反加1）\nmodule inv_converter_8(\n input wire [7:0] data_i ,\n output wire[8:0] inv_o \n );\n \n wire [5:0] wire_cout ; \n wire not_o ; \n\n assign inv_o[0] = data_i[0];\n \n inv_unit inv_unit_bit1(\n .a (data_i[1] ),\n .b (data_i[0] ),\n .xor_o (inv_o[1] ), \n .or_o (wire_cout[0] ) \n );\n \n genvar i;\n generate \n for(i=2;i<=5;i=i+1) begin\n inv_unit inv_unit_inst(\n .a (data_i[i] ),\n .b (wire_cout[i-2] ),\n .xor_o (inv_o[i] ), \n .or_o (wire_cout[i-1] ) \n );\n end\n endgenerate\n \n inv_unit_nor_out inv_unit_nor_out_inst_6(\n .a (data_i[6] ),\n .b (wire_cout[4] ),\n .xor_o (inv_o[6] ), \n .nor_o (wire_cout[5] ) \n );\n \n inv_unit_nor_out inv_unit_nor_out_inst_7(\n .a (data_i[7] ),\n .b (not_o ), \n .xor_o (inv_o[7] ), \n .nor_o ( ) \n );\n \n \n\n assign not_o = ~wire_cout[5] ;\n \n\n assign inv_o[8] = ~(wire_cout[5] | data_i[7]);\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/inv_conveter_8.v", "// 取反 加1 （-1*A、-2*A 都要进行取反加1）\nmodule inv_converter_8(\n input wire [7:0] data_i ,\n output wire[8:0] inv_o \n );\n \n wire [5:0] wire_cout ; \n wire not_o ; \n\n assign inv_o[0] = data_i[0];\n \n inv_unit inv_unit_bit1(\n .a (data_i[1] ),\n .b (data_i[0] ),\n .xor_o (inv_o[1] ), \n .or_o (wire_cout[0] ) \n );\n \n genvar i;\n generate \n for(i=2;i<=5;i=i+1) begin\n inv_unit inv_unit_inst(\n .a (data_i[i] ),\n .b (wire_cout[i-2] ),\n .xor_o (inv_o[i] ), \n .or_o (wire_cout[i-1] ) \n );\n end\n endgenerate\n \n inv_unit_nor_out inv_unit_nor_out_inst_6(\n .a (data_i[6] ),\n .b (wire_cout[4] ),\n .xor_o (inv_o[6] ), \n .nor_o (wire_cout[5] ) \n );\n \n inv_unit_nor_out inv_unit_nor_out_inst_7(\n .a (data_i[7] ),\n .b (not_o ), \n .xor_o (inv_o[7] ), \n .nor_o ( ) \n );\n \n \n\n assign not_o = ~wire_cout[5] ;\n \n\n assign inv_o[8] = ~(wire_cout[5] | data_i[7]);\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT3_OPT4C/pe/sparse_encoder.v", "module sparse_encoder (\n input clk,\n input rst_n,\n input [7:0] en_multiplicand,\n input [3:0] sign_en_multiplicand,\n input encode_valid,\n output reg [1:0] partial_product_index, // to sparse_pe generate partial product\n output reg [1:0] position_0, // to prefetch operand b\n output [2:0] cal_cycle // to prefetch operand a \n);\n\nwire a ;\nwire b ;\nwire c ;\nwire d ;\n\nreg [7:0] cal_en_multiplicand;\nreg [1:0] position_1 ;\nreg [1:0] position_2 ;\nreg position_3 ;\n\nassign a = en_multiplicand[0] | en_multiplicand[1];\nassign b = en_multiplicand[2] | en_multiplicand[3];\nassign c = en_multiplicand[4] | en_multiplicand[5];\nassign d = en_multiplicand[6] | en_multiplicand[7];\n\n\nassign a_b_c_d = (a) & (b) & (c) & (d);\nassign cal_cycle = {a_b_c_d,(~a & ( (b & c) | (b & d) | (c & d) )) | (a & ( (b & ~c) | (~b & d) | (c & ~d) )),(a ^ b) ^ (c ^ d)};\n\n/**********************************************/\n/******** 00 | 01 | 10 | 11 | *********/\n/******** -2B | B | 2B | -B | *********/\n/**********************************************/\ngenvar i;\ngenerate\n for (i = 0 ; i < 4 ; i = i + 1) begin : gen_cal_encoder\n always @(posedge clk or negedge rst_n) begin\n\t if (!rst_n) begin\n cal_en_multiplicand[2*(i+1)-1:2*i] <= 0;\n\t end\n\t else begin\n if(encode_valid) begin\n if(sign_en_multiplicand[i]) begin\n cal_en_multiplicand[2*(i+1)-1:2*i] <= {~en_multiplicand[2*(i+1)-1],en_multiplicand[2*i]};\n end\n else\n cal_en_multiplicand[2*(i+1)-1:2*i] <= en_multiplicand[2*(i+1)-1:2*i];\n end else\n cal_en_multiplicand[2*(i+1)-1:2*i] <= cal_en_multiplicand[2*(i+1)-1:2*i] ;\n\t end\n end\n end\nendgenerate\n \n\n\nalways @(posedge clk or negedge rst_n) begin\n if (!rst_n) begin\n position_0 <= 2'b0 ; \n position_1 <= 2'b0 ; \n position_2 <= 2'b0 ; \n position_3 <= 1'b0 ;\n end\n else begin\n if(encode_valid) begin\n position_0 <= {(~a)&(~b), (~a & (b | ~c))};\n position_1 <= {( (a ^ b) & (c | d)) | ( (~a)&(c)&(d) ), (a & b) | ( d & ( ( (a ^ b) & ~c ) | ( ~a & ~b & c ) ))};\n position_2 <= {(c & d & (a | b)) | (a & b & (c | d)), d & ( (a&b | a&c | b&c) & ~(a&b&c) )};\n position_3 <= a_b_c_d;\n end\n else begin\n position_0 <= position_1;\n position_1 <= position_2;\n position_2 <= {position_3,position_3};\n position_3 <= 0;\n end\n end\nend\n\n\nalways @(posedge clk) begin\n case(position_0) \n 2'b00: partial_product_index <= cal_en_multiplicand[1:0];\n 2'b01: partial_product_index <= cal_en_multiplicand[3:2];\n 2'b10: partial_product_index <= cal_en_multiplicand[5:4];\n 2'b11: partial_product_index <= cal_en_multiplicand[7:6];\n endcase\nend\n\nendmodule\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/mac_pe/mac.v", "module mac #\n(\n parameter WIDTH = 8,\n parameter ACC_WIDTH = 32\n)\n(\n input wire rst_n,\n input wire clk,\n input wire signed [WIDTH-1 :0] a,\n input wire signed [WIDTH-1 :0] b,\n output reg signed [ACC_WIDTH-1 :0] result\n);\n\nwire signed [15:0] result_p;\nreg signed [7:0] operand_a;\nreg signed [7:0] operand_b;\n\nassign result_p = $signed(operand_a) * $signed(operand_b) ;\n\nalways @(posedge clk) begin\n operand_a <= a;\n operand_b <= b;\nend\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n result <= 0;\n end\n else begin\n result <= result + $signed(result_p);\n end\nend\n\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/PE.v", "// b = w * a\nmodule PE #\n(\n parameter WIDTH = 8,\n parameter ACC_WIDTH = 24\n)\n(\n input wire rst_n ,\n input wire clk ,\n input wire weight_wen ,\n input [WIDTH-1 :0] weight_din ,\n input wire signed [WIDTH-1 :0] a ,\n input wire signed [2*ACC_WIDTH-1 :0] partial_result , \n\n output reg signed [WIDTH-1 :0] col ,\n output reg signed [2*ACC_WIDTH-1 :0] row \n);\n\n\nreg signed [WIDTH-1 :0] weight;\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n weight <= 0;\n end\n else begin\n if(weight_wen) begin\n weight <= weight_din; \n end\n else begin\n weight <= weight;\n end\n end\nend\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n col <= 0;\n end\n else begin\n if(weight_wen) begin\n col <= weight_din; \n end\n else begin\n col <= a;\n end\n end\nend\n\nwire [ACC_WIDTH-1:0] acc_sum;\nwire [ACC_WIDTH-1:0] acc_carry;\nalways @(*) begin\n if(!rst_n) begin\n row <= 0;\n end\n else begin\n row <= {acc_sum, acc_carry}; // partial_result + weight * a;\n end\nend\nopt1_mac #(\n .ACC_WIDTH(ACC_WIDTH),\n .INPUT_PIP(0)\n) opt1_mac_test (\n .clk(clk),\n .rst_n(rst_n),\n .operand_a_in(a), \n .operand_b_in(weight), \n .partial_result(partial_result),\n .acc_sum(acc_sum),\n .acc_carry(acc_carry)\n);\n\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/pe.v", "module PE #\n(\n parameter WIDTH = 8,\n parameter ACC_WIDTH = 32\n)\n(\n input wire rst_n,\n input wire clk,\n input wire signed [WIDTH-1 :0] a,\n input wire signed [WIDTH-1 :0] b,\n input wire clc, // clean_result_cache\n\n output reg signed [WIDTH-1 :0] row,\n output reg signed [WIDTH-1 :0] col,\n output signed [2*ACC_WIDTH-1 :0] result\n);\n\n\nwire [ACC_WIDTH-1:0] acc_sum;\nwire [ACC_WIDTH-1:0] acc_carry;\nopt1_mac #(\n .ACC_WIDTH(ACC_WIDTH),\n .INPUT_PIP(0)\n) opt1_mac_test (\n .clk(clk),\n .rst_n(rst_n),\n .operand_a_in(a), \n .operand_b_in(b), \n .clc(clc), // input wire clean_result_cache\n .acc_sum(acc_sum),\n .acc_carry(acc_carry)\n);\nassign result = {acc_sum, acc_carry};\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n row <= 0;\n col <= 0;\n end\n else begin\n row <= a;\n col <= b;\n end\nend\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT3_OPT4C/array/top_pe_column.v", "module top_pe_column #(\n parameter N = 32,\n parameter ACC_WIDTH = 26\n\n)(\n input clk,\n input rst_n,\n input clr,\n input [7:0] en_multiplicand, // operand a\n input [3:0] sign_en_multiplicand,\n input encode_valid,\n input [8*N-1:0] operand_b, \n output [1:0] position, // to prefetch operand b \n output [2:0] cal_cycle, // to prefetch operand a \n output [52*N-1:0] pe_result \n);\n\nwire [1:0] partial_product_index;\n\ngenvar i;\nsparse_encoder sp_encoder(\n .clk(clk),\n .rst_n(rst_n),\n .en_multiplicand(en_multiplicand),\n .sign_en_multiplicand(sign_en_multiplicand),\n .encode_valid(encode_valid),\n .partial_product_index(partial_product_index), // to sparse_pe generate partial product\n .position_0(position), // to prefetch operand b\n .cal_cycle(cal_cycle) // to prefetch operand a \n);\n\ngenerate\nfor (i = 0 ; i < N ; i = i + 1) begin\n pe #(\n .ACC_WIDTH(26)\n ) sparse_pe (\n .clk(clk),\n .rst_n(rst_n),\n .clr(clr),\n .encoder_position_ins(partial_product_index),\n .operand_b_ins(operand_b[8*(i+1)-1:8*i]),\n .result(pe_result[52*(i+1)-1:52*i])\n );\nend\nendgenerate\n\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/PE.v", "`timescale 1ns / 1ps\n\n// b = w * a\nmodule PE #\n(\n parameter WIDTH = 8,\n parameter ACC_WIDTH = 24\n)\n(\n input wire rst_n,\n input wire clk,\n input wire signed [WIDTH-1 :0] i_z_a,\n input wire signed [WIDTH-1 :0] i_x_b,\n input wire signed [2*ACC_WIDTH-1 :0] i_y_p,\n\n output reg signed [WIDTH-1 :0] o_z_a,\n output reg signed [WIDTH-1 :0] o_x_b,\n output reg signed [2*ACC_WIDTH-1 :0] o_y_p\n);\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n o_z_a <= 0;\n o_x_b <= 0;\n end\n else begin\n o_z_a <= i_z_a; \n o_x_b <= i_x_b; \n end\nend\n\nwire [ACC_WIDTH-1:0] acc_sum;\nwire [ACC_WIDTH-1:0] acc_carry;\nalways @(*) begin\n if(!rst_n) begin\n o_y_p = 0;\n end\n else begin\n o_y_p = {acc_sum, acc_carry}; // partial_result + weight * a;\n end\nend\nopt1_mac #(\n .ACC_WIDTH(ACC_WIDTH),\n .INPUT_PIP(0)\n) opt1_mac_test (\n .clk(clk),\n .rst_n(rst_n),\n .operand_a_in(i_z_a), \n .operand_b_in(i_x_b), \n .partial_result(i_y_p),\n .acc_sum(acc_sum),\n .acc_carry(acc_carry)\n);\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_mac_based/PE.v", "// b = w * a\nmodule PE #\n(\n parameter WIDTH = 8,\n parameter ACC_WIDTH = 24\n)\n(\n input wire rst_n ,\n input wire clk ,\n input wire weight_wen ,\n input [WIDTH-1 :0] weight_din ,\n input wire signed [WIDTH-1 :0] a ,\n input wire signed [ACC_WIDTH-1 :0] partial_result , \n\n output reg signed [WIDTH-1 :0] col ,\n output reg signed [ACC_WIDTH-1 :0] row \n);\n\n\nreg signed [WIDTH-1 :0] weight;\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n weight <= 0;\n end\n else begin\n if(weight_wen) begin\n weight <= weight_din; \n end\n else begin\n weight <= weight;\n end\n end\nend\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n col <= 0;\n end\n else begin\n if(weight_wen) begin\n col <= weight_din; \n end\n else begin\n col <= a;\n end\n end\nend\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n row <= 0;\n end\n else begin\n row <= partial_result + weight * a;\n end\nend\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_mac_based/pe.v", "`timescale 1ns / 1ps\n\n// b = w * a\nmodule PE #\n(\n parameter WIDTH = 8,\n parameter ACC_WIDTH = 24\n)\n(\n input wire rst_n,\n input wire clk,\n input wire signed [WIDTH-1 :0] i_z_a,\n input wire signed [WIDTH-1 :0] i_x_b,\n input wire signed [ACC_WIDTH-1 :0] i_y_p,\n\n output reg signed [WIDTH-1 :0] o_z_a,\n output reg signed [WIDTH-1 :0] o_x_b,\n output reg signed [ACC_WIDTH-1 :0] o_y_p\n);\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n o_y_p <= 0;\n end\n else begin\n o_y_p <= i_y_p + i_z_a*i_x_b; \n end\nend\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n o_z_a <= 0;\n o_x_b <= 0;\n end\n else begin\n o_z_a <= i_z_a; \n o_x_b <= i_x_b; \n end\nend\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/booth_partial_product_generator_pp1.v", "module booth_partial_product_generator_pp1(\n input wire [1:0] operand_slice_a, \n input wire [7:0] operand_b, \n input wire [8:0] operand_b_neg, \n output wire [9:0] pp_out \n );\n \n wire [8:0] pp_source;\n wire not_code0;\n //----------------------------------------------------\n //| pp | flag_2x | flag_s1 | flag_s2 |\n //----------------------------------------------------\n //| operand_b | 0 | 0 | 1 |\n //| -operand_b | 0 | 1 | 0 |\n //| 2operand_b | 1 | 0 | 1 | \n //| -2operand_b | 1 | 1 | 0 |\n //| 0 | x | 0 | 0 | \n //----------------------------------------------------\n wire flag_2x;\n wire flag_s1;\n wire flag_s2; \n assign not_code0 = ~operand_slice_a[0]; \n assign flag_2x = not_code0; \n assign flag_s1 = operand_slice_a[1]; \n assign flag_s2 = ~(operand_slice_a[1] | not_code0); \n wire flag_not_2x = operand_slice_a[0];\n assign pp_source = (({{operand_b[7]}, operand_b} & {9{flag_s2}}) | (operand_b_neg & {9{flag_s1}}));\n assign pp_out[0] = (!flag_2x & pp_source[0]);\n assign pp_out[8:1] = (({8{flag_2x}} & pp_source[7:0]) | ({8{flag_not_2x}} & pp_source[8:1]));\n assign pp_out[9] = pp_source[8];\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT3_OPT4C/pe/top_pe.v", "module top_pe(\n input clk,\n input rst_n,\n input clr,\n input [7:0] en_multiplicand, // operand a\n input [3:0] sign_en_multiplicand,\n input encode_valid,\n input [7:0] operand_b, \n output [1:0] position, // to prefetch operand b \n output [2:0] cal_cycle, // to prefetch operand a \n output [51:0] pe_result \n);\n\nwire [1:0] partial_product_index;\n\nsparse_encoder sp_encoder(\n .clk(clk),\n .rst_n(rst_n),\n .en_multiplicand(en_multiplicand),\n .sign_en_multiplicand(sign_en_multiplicand),\n .encode_valid(encode_valid),\n .partial_product_index(partial_product_index), // to sparse_pe generate partial product\n .position_0(position), // to prefetch operand b\n .cal_cycle(cal_cycle) // to prefetch operand a \n);\n\n\npe #(\n .ACC_WIDTH(26)\n) sparse_pe (\n .clk(clk),\n .rst_n(rst_n),\n .clr(clr),\n .encoder_position_ins(partial_product_index),\n .operand_b_ins(operand_b),\n .result(pe_result)\n);\n\n\n\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/booth_partial_product_generator_pp1.v", "module booth_partial_product_generator_pp1(\n input wire [1:0] operand_slice_a, \n input wire [7:0] operand_b, \n input wire [8:0] operand_b_neg, \n output wire [9:0] pp_out \n );\n \n wire [8:0] pp_source;\n wire not_code0;\n //----------------------------------------------------\n //| pp | flag_2x | flag_s1 | flag_s2 |\n //----------------------------------------------------\n //| operand_b | 0 | 0 | 1 |\n //| -operand_b | 0 | 1 | 0 |\n //| 2operand_b | 1 | 0 | 1 | \n //| -2operand_b | 1 | 1 | 0 |\n //| 0 | x | 0 | 0 | \n //----------------------------------------------------\n \n //----------------------------------------------------\n //operand_slice_a[1] operand_slice_a[0] operand_slice_a[-1] | pp \n //----------------------------------------------------\n // 0 0 0 | 0 \n // 0 1 0 | operand_b \n // 1 0 0 | 2operand_b \n // 1 1 0 | -operand_b \n //----------------------------------------------------\n \n wire flag_2x;\n wire flag_s1;\n wire flag_s2; \n assign not_code0 = ~operand_slice_a[0]; \n assign flag_2x = not_code0; \n assign flag_s1 = operand_slice_a[1]; // 取反\n assign flag_s2 = ~(operand_slice_a[1] | not_code0); // A\n wire flag_not_2x = operand_slice_a[0];\n assign pp_source = (({{operand_b[7]}, operand_b} & {9{flag_s2}}) | (operand_b_neg & {9{flag_s1}})); // A or ~A or 0\n assign pp_out[0] = (!flag_2x & pp_source[0]);// x2 (<<1) pp_out[0]=0\n assign pp_out[8:1] = (({8{flag_2x}} & pp_source[7:0]) | ({8{flag_not_2x}} & pp_source[8:1]));\n assign pp_out[9] = pp_source[8];\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/booth_partial_product_generator_pp1.v", "module booth_partial_product_generator_pp1(\n input wire [1:0] operand_slice_a, \n input wire [7:0] operand_b, \n input wire [8:0] operand_b_neg, \n output wire [9:0] pp_out \n );\n \n wire [8:0] pp_source;\n wire not_code0;\n //----------------------------------------------------\n //| pp | flag_2x | flag_s1 | flag_s2 |\n //----------------------------------------------------\n //| operand_b | 0 | 0 | 1 |\n //| -operand_b | 0 | 1 | 0 |\n //| 2operand_b | 1 | 0 | 1 | \n //| -2operand_b | 1 | 1 | 0 |\n //| 0 | x | 0 | 0 | \n //----------------------------------------------------\n \n //----------------------------------------------------\n //operand_slice_a[1] operand_slice_a[0] operand_slice_a[-1] | pp \n //----------------------------------------------------\n // 0 0 0 | 0 \n // 0 1 0 | operand_b \n // 1 0 0 | 2operand_b \n // 1 1 0 | -operand_b \n //----------------------------------------------------\n \n wire flag_2x;\n wire flag_s1;\n wire flag_s2; \n assign not_code0 = ~operand_slice_a[0]; \n assign flag_2x = not_code0; \n assign flag_s1 = operand_slice_a[1]; // 取反\n assign flag_s2 = ~(operand_slice_a[1] | not_code0); // A\n wire flag_not_2x = operand_slice_a[0];\n assign pp_source = (({{operand_b[7]}, operand_b} & {9{flag_s2}}) | (operand_b_neg & {9{flag_s1}})); // A or ~A or 0\n assign pp_out[0] = (!flag_2x & pp_source[0]);// x2 (<<1) pp_out[0]=0\n assign pp_out[8:1] = (({8{flag_2x}} & pp_source[7:0]) | ({8{flag_not_2x}} & pp_source[8:1]));\n assign pp_out[9] = pp_source[8];\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/booth_partial_product_generator_pp1.v", "module booth_partial_product_generator_pp1(\n input wire [1:0] operand_slice_a, \n input wire [7:0] operand_b, \n input wire [8:0] operand_b_neg, \n output wire [9:0] pp_out \n );\n \n wire [8:0] pp_source;\n wire not_code0;\n //----------------------------------------------------\n //| pp | flag_2x | flag_s1 | flag_s2 |\n //----------------------------------------------------\n //| operand_b | 0 | 0 | 1 |\n //| -operand_b | 0 | 1 | 0 |\n //| 2operand_b | 1 | 0 | 1 | \n //| -2operand_b | 1 | 1 | 0 |\n //| 0 | x | 0 | 0 | \n //----------------------------------------------------\n \n //----------------------------------------------------\n //operand_slice_a[1] operand_slice_a[0] operand_slice_a[-1] | pp \n //----------------------------------------------------\n // 0 0 0 | 0 \n // 0 1 0 | operand_b \n // 1 0 0 | 2operand_b \n // 1 1 0 | -operand_b \n //----------------------------------------------------\n \n wire flag_2x;\n wire flag_s1;\n wire flag_s2; \n assign not_code0 = ~operand_slice_a[0]; \n assign flag_2x = not_code0; \n assign flag_s1 = operand_slice_a[1]; // 取反\n assign flag_s2 = ~(operand_slice_a[1] | not_code0); // A\n wire flag_not_2x = operand_slice_a[0];\n assign pp_source = (({{operand_b[7]}, operand_b} & {9{flag_s2}}) | (operand_b_neg & {9{flag_s1}})); // A or ~A or 0\n assign pp_out[0] = (!flag_2x & pp_source[0]);// x2 (<<1) pp_out[0]=0\n assign pp_out[8:1] = (({8{flag_2x}} & pp_source[7:0]) | ({8{flag_not_2x}} & pp_source[8:1]));\n assign pp_out[9] = pp_source[8];\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/booth_pp_gen.v", "module booth_pp_gen(\n input wire [7:0] operand_a, \n input wire [7:0] operand_b, \n output wire [9:0] pp1,\n output wire [9:0] pp2,\n output wire [9:0] pp3,\n output wire [9:0] pp4 \n );\n\n wire [1:0] operand_slice_a1 ;\n wire [2:0] operand_slice_a2 ;\n wire [2:0] operand_slice_a3 ;\n wire [2:0] operand_slice_a4 ;\n wire [8:0] operand_b_neg ;\n \n inv_converter_8 inv_converter_8_inst(\n .data_i (operand_b),\n .inv_o (operand_b_neg) \n );\n \n assign operand_slice_a1 = operand_a[1:0] ;\n assign operand_slice_a2 = operand_a[3:1] ;\n assign operand_slice_a3 = operand_a[5:3] ;\n assign operand_slice_a4 = operand_a[7:5] ;\n\n booth_partial_product_generator_pp1 ppg_1 (\n .operand_slice_a (operand_slice_a1), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp1) \n );\n\n booth_partial_product_generator ppg_2 (\n .operand_slice_a (operand_slice_a2), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp2) \n );\n\n booth_partial_product_generator ppg_3 (\n .operand_slice_a (operand_slice_a3), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp3) \n );\n\n booth_partial_product_generator ppg_4 (\n .operand_slice_a (operand_slice_a4), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp4) \n );\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/booth_pp_gen.v", "module booth_pp_gen(\n input wire [7:0] operand_a, \n input wire [7:0] operand_b, \n output wire [9:0] pp1,\n output wire [9:0] pp2,\n output wire [9:0] pp3,\n output wire [9:0] pp4 \n );\n\n wire [1:0] operand_slice_a1 ;\n wire [2:0] operand_slice_a2 ;\n wire [2:0] operand_slice_a3 ;\n wire [2:0] operand_slice_a4 ;\n wire [8:0] operand_b_neg ;\n \n inv_converter_8 inv_converter_8_inst(\n .data_i (operand_b),\n .inv_o (operand_b_neg) \n );\n \n assign operand_slice_a1 = operand_a[1:0] ;\n assign operand_slice_a2 = operand_a[3:1] ;\n assign operand_slice_a3 = operand_a[5:3] ;\n assign operand_slice_a4 = operand_a[7:5] ;\n\n booth_partial_product_generator_pp1 ppg_1 (\n .operand_slice_a (operand_slice_a1), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp1) \n );\n\n booth_partial_product_generator ppg_2 (\n .operand_slice_a (operand_slice_a2), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp2) \n );\n\n booth_partial_product_generator ppg_3 (\n .operand_slice_a (operand_slice_a3), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp3) \n );\n\n booth_partial_product_generator ppg_4 (\n .operand_slice_a (operand_slice_a4), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp4) \n );\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/booth_pp_gen.v", "module booth_pp_gen(\n input wire [7:0] operand_a, \n input wire [7:0] operand_b, \n output wire [9:0] pp1,\n output wire [9:0] pp2,\n output wire [9:0] pp3,\n output wire [9:0] pp4 \n );\n\n wire [1:0] operand_slice_a1 ;\n wire [2:0] operand_slice_a2 ;\n wire [2:0] operand_slice_a3 ;\n wire [2:0] operand_slice_a4 ;\n wire [8:0] operand_b_neg ;\n \n inv_converter_8 inv_converter_8_inst(\n .data_i (operand_b),\n .inv_o (operand_b_neg) \n );\n \n assign operand_slice_a1 = operand_a[1:0] ;\n assign operand_slice_a2 = operand_a[3:1] ;\n assign operand_slice_a3 = operand_a[5:3] ;\n assign operand_slice_a4 = operand_a[7:5] ;\n\n booth_partial_product_generator_pp1 ppg_1 (\n .operand_slice_a (operand_slice_a1), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp1) \n );\n\n booth_partial_product_generator ppg_2 (\n .operand_slice_a (operand_slice_a2), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp2) \n );\n\n booth_partial_product_generator ppg_3 (\n .operand_slice_a (operand_slice_a3), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp3) \n );\n\n booth_partial_product_generator ppg_4 (\n .operand_slice_a (operand_slice_a4), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp4) \n );\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/booth_pp_gen.v", "module booth_pp_gen(\n input wire [7:0] operand_a, \n input wire [7:0] operand_b, \n output wire [9:0] pp1,\n output wire [9:0] pp2,\n output wire [9:0] pp3,\n output wire [9:0] pp4 \n );\n\n wire [1:0] operand_slice_a1 ;\n wire [2:0] operand_slice_a2 ;\n wire [2:0] operand_slice_a3 ;\n wire [2:0] operand_slice_a4 ;\n wire [8:0] operand_b_neg ;\n \n inv_converter_8 inv_converter_8_inst(\n .data_i (operand_b),\n .inv_o (operand_b_neg) \n );\n \n assign operand_slice_a1 = operand_a[1:0] ;\n assign operand_slice_a2 = operand_a[3:1] ;\n assign operand_slice_a3 = operand_a[5:3] ;\n assign operand_slice_a4 = operand_a[7:5] ;\n\n booth_partial_product_generator_pp1 ppg_1 (\n .operand_slice_a (operand_slice_a1), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp1) \n );\n\n booth_partial_product_generator ppg_2 (\n .operand_slice_a (operand_slice_a2), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp2) \n );\n\n booth_partial_product_generator ppg_3 (\n .operand_slice_a (operand_slice_a3), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp3) \n );\n\n booth_partial_product_generator ppg_4 (\n .operand_slice_a (operand_slice_a4), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp4) \n );\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_mac_based/pe.v", "module PE #\n(\n parameter WIDTH = 8,\n parameter ACC_WIDTH = 32\n)\n(\n input wire rst_n,\n input wire clk,\n input wire signed [WIDTH-1 :0] a,\n input wire signed [WIDTH-1 :0] b,\n input wire clc, // clean_result_cache,\n\n output reg signed [WIDTH-1 :0] row,\n output reg signed [WIDTH-1 :0] col,\n output reg signed [ACC_WIDTH-1 :0] result\n);\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n result <= 0;\n end\n else begin\n if(clc)\n result <= 0;\n else\n result <= result + a * b ;\n end\nend\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n row <= 0;\n col <= 0;\n end\n else begin\n row <= a;\n col <= b;\n end\nend\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT2/vector_encoder.sv", "module vector_encoder(\n input clk,\n input [127:0] operand_a,\n output reg [3:0] bit_enable [0:15],\n output reg [7:0] partial_product_select [0:15]\n);\n\nwire [3:0] bit_valid [0:15];\nwire [7:0] encoder_nub [0:15];\nreg [127:0] sync_operand ;\n\ngenvar i;\ngenerate\n for(i = 0; i < 16; i = i + 1) begin\n en_t_encoder en_t_preencoder(\n .clk(clk),\n .multiplicand(sync_operand[8*(i+1)-1:8*i]),\n .cal_encode_nub(encoder_nub[i]),\n .bit_enable(bit_valid[i])\n );\n end \nendgenerate\n\nalways @(posedge clk) begin\n sync_operand <= operand_a;\n bit_enable <= bit_valid;\n partial_product_select <= encoder_nub;\nend\n\nendmodule\n\n\n\nmodule en_t_encoder(\n input clk,\n input [7:0] multiplicand, \n output reg [7:0] cal_encode_nub,\n output reg [3:0] bit_enable\n );\n\nwire [7:0] encode_input;\nwire [2:0] c_out;\nwire [7:0] encode_nub;\n\n// covert to bit_enable-Magnitude\nassign encode_input = multiplicand[7] ? ((multiplicand[6:0] == 0) ? 8'b10000000 : {1'b0,~multiplicand[6:0] + 1'b1}) : {1'b0,multiplicand[6:0]};\n\ngenvar i;\ngenerate for(i = 0; i < 4; i = i + 1) begin: gen_encode_nub \n if(i==0) begin\n assign encode_nub[1:0] = encode_input[1:0];\n end\n else if (i==1) begin\n encoder_1 en_t\n (.A(encode_input[2*i-1:2*i-2]),\n .B(encode_input[2*i+1:2*i]), \n .c_out(c_out[i]), \n .en_b(encode_nub[2*i+1:2*i])\n );\n end\n else if (i==3) begin\n encoder_3 en_t\n (.A(encode_input[2*i-1:2*i-2]),\n .c_in(c_out[i-1]), \n .B(encode_input[2*i+1:2*i]), \n .en_b(encode_nub[2*i+1:2*i])\n );\n end\n else begin\n encoder en_t\n (.A(encode_input[2*i-1:2*i-2]),\n .c_in(c_out[i-1]), \n .B(encode_input[2*i+1:2*i]), \n .c_out(c_out[i]), \n .en_b(encode_nub[2*i+1:2*i])\n );\n end \nend \nendgenerate \n\n\ngenerate \n for (i = 0 ; i < 4; i = i + 1) begin\n always @(posedge clk) begin\n if(encode_nub[2*i+1:2*i] == 2'b00) begin\n bit_enable[i] <= 0;\n cal_encode_nub[2*i+1:2*i] <= 0;\n end\n else begin\n bit_enable[i] <= 1;\n cal_encode_nub[2*i+1:2*i] <= {multiplicand[7]^encode_nub[2*i+1],encode_nub[2*i]};\n end\n end\n end\nendgenerate\n\nendmodule\n\n\nmodule encoder_1(A, B, c_out, en_b);\n\ninput wire [1:0] A;\ninput wire [1:0] B;\n \noutput wire c_out;\noutput wire [1:0] en_b;\n\nassign c_out = (A[0] & A[1]); \nassign en_b = B + c_out;\n\nendmodule\n\nmodule encoder(A, c_in, B, c_out, en_b);\n\ninput wire [1:0] A;\ninput wire c_in;\ninput wire [1:0] B;\n \noutput wire c_out;\noutput wire [1:0] en_b;\n\nassign c_out = (A[0] & A[1]) | (A[1] & c_in); \nassign en_b = B + c_out;\n\nendmodule\n\nmodule encoder_3(A, c_in, B, en_b);\n\ninput wire [1:0] A;\ninput wire c_in;\ninput wire [1:0] B;\noutput wire [1:0] en_b;\n\nwire c_out;\nassign c_out = (A[0] & A[1]) | (A[1] & c_in); \nassign en_b = B + c_out;\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT3_OPT4C/pe/pe.v", "module pe #(\n parameter ACC_WIDTH = 26 //due to the same bit-weight reduction\n)(\n input clk,\n input rst_n,\n input clr,\n input wire [1:0] encoder_position_ins,\n input wire [7:0] operand_b_ins,\n output wire [51:0] result\n);\n\nwire signed [ACC_WIDTH-1:0] sum;\nwire signed [ACC_WIDTH-1:0] carry;\nwire signed [ACC_WIDTH-1:0] sum_input;\nwire signed [ACC_WIDTH-1:0] carry_input;\nreg signed [ACC_WIDTH-1:0] acc_sum;\nreg signed [ACC_WIDTH-1:0] acc_carry;\nreg [1:0] encoder_position;\nreg signed [7:0] operand_b;\n\n\nwire signed [8:0] b;\nwire signed [8:0] b_2;\nwire signed [8:0] neg_b;\nwire signed [9:0] neg_b_2;\nreg signed [9:0] mux_select_b;\nwire signed [ACC_WIDTH-1:0] mux_extend_b;\nwire [3*ACC_WIDTH-1:0] csa_input;\n\nassign b = $signed(operand_b);\nassign b_2 = {operand_b,1'b0};\nassign neg_b = ~b + 1'b1;\nassign neg_b_2 = {neg_b,1'b0};\nassign mux_extend_b = mux_select_b;\nassign sum_input = !clr ? 0 : acc_sum;\nassign carry_input = !clr ? 0 : acc_carry;\nassign csa_input = {mux_extend_b,sum_input,carry_input};\n\nalways @(*) begin\n case (encoder_position)\n 2'd0: mux_select_b = $signed(neg_b_2);\n 2'd1: mux_select_b = $signed(b);\n 2'd2: mux_select_b = $signed(b_2);\n 2'd3: mux_select_b = $signed(neg_b);\n endcase\nend\n\nDW02_tree #(3,ACC_WIDTH, 1)\n U1 ( .INPUT(csa_input), .OUT0(sum), .OUT1(carry) );\n\n always @(posedge clk or negedge rst_n) begin\n\tif (!rst_n) begin\n encoder_position <=0;\n operand_b <=0;\n\tend\n\telse begin\n encoder_position <= encoder_position_ins;\n operand_b <= operand_b_ins;\n\tend\nend\n\nalways @(posedge clk) begin\n acc_sum <= sum ;\n acc_carry <= carry;\nend\n\nassign result = {acc_sum,acc_carry};\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT2/partial_product_select.sv", "module partial_product_select(\n input clk,\n input [7:0] weight,\n input [3:0] bit_enable,\n input [7:0] partial_product_select,\n output signed [9:0] partial_product [0:3] \n);\n\nwire signed [8:0] inv_b;\nwire signed [7:0] b;\nwire signed [8:0] b_2;\nwire signed [8:0] b_neg;\nwire signed [9:0] b_2_neg;\nwire [1:0] cal_partial_product_select [0:3];\nreg signed [9:0] partial_product_bw [0:3]; \n\nassign cal_partial_product_select[0] = partial_product_select[1:0];\nassign cal_partial_product_select[1] = partial_product_select[3:2];\nassign cal_partial_product_select[2] = partial_product_select[5:4];\nassign cal_partial_product_select[3] = partial_product_select[7:6];\nassign partial_product = partial_product_bw;\nassign b = $signed(weight);\nassign inv_b = $signed(~b);\nassign b_2 = {b,1'b0};\nassign b_neg = inv_b + 1'b1;\nassign b_2_neg = {b_neg,1'b0};\n\ngenvar i;\ngenerate \n for (i = 0 ; i < 4; i = i + 1) begin\n always @(posedge clk) begin\n if(bit_enable[i]) begin\n case(cal_partial_product_select[i])\n 2'b00: partial_product_bw[i] <= $signed(b_2_neg);\n 2'b01: partial_product_bw[i] <= $signed(b);\n 2'b10: partial_product_bw[i] <= $signed(b_2);\n 2'b11: partial_product_bw[i] <= $signed(b_neg);\n endcase\n end\n else\n partial_product_bw[i] <= 0;\n end\n end \nendgenerate\n\nendmodule\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_mac_based/top.v", "`timescale 1ns / 1ps\nmodule top #\n(\n parameter N = 8, //CHANGE\n parameter WIDTH = 8, \n parameter ACC_WIDTH = 2*WIDTH + $clog2(N) \n)\n(\n input wire rst_n ,\n input wire clk ,\n input wire [N*N*WIDTH-1 :0] A ,\n input wire [N*N*WIDTH-1 :0] B ,\n output wire [N*N*ACC_WIDTH-1 :0] result \n);\n\nreg [N*N*WIDTH-1 :0] A_reg ;\nreg [N*N*WIDTH-1 :0] B_reg ;\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n A_reg<={(N*N*WIDTH){1'b0}};\n B_reg<={(N*N*WIDTH){1'b0}};\n end\n else begin\n A_reg<=A;\n B_reg<=B;\n end\nend\n\n\nwire signed [WIDTH-1:0] d_x [0:N-1][0:N-1][0:N-1];\nwire signed [ACC_WIDTH-1:0] d_y [0:N-1][0:N-1][0:N-1];\nwire signed [WIDTH-1:0] d_z [0:N-1][0:N-1][0:N-1];\n\n\n genvar x, y, z;\n generate\n for (z = 0; z < N; z = z + 1 ) begin\n for(x = 0; x < N; x = x + 1) begin\n for (y = 0; y < N; y = y + 1 ) begin\n if(z==0) begin\n if(x==0) begin\n if(y==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE //(1)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p ({ACC_WIDTH{1'b0}} ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n ); \n end\n else if(y==N-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(3)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (result[N*ACC_WIDTH*z+(x+1)*ACC_WIDTH-1 : ACC_WIDTH*N*z+x*ACC_WIDTH] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(2)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n );\n end\n end\n else begin\n if(y==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE //(6)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p ({ACC_WIDTH{1'b0}} ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n ); \n end\n else if(y==N-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(5)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (result[N*ACC_WIDTH*z+(x+1)*ACC_WIDTH-1 : ACC_WIDTH*N*z+x*ACC_WIDTH] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(4)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n );\n end \n end\n end\n else begin\n if(x==0) begin\n if(y==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE //(7)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p ({ACC_WIDTH{1'b0}} ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n ); \n end\n else if(y==N-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(9)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (result[N*ACC_WIDTH*z+(x+1)*ACC_WIDTH-1 : ACC_WIDTH*N*z+x*ACC_WIDTH] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(8)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n );\n end\n end\n else begin\n if(y==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE //(10)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p ({ACC_WIDTH{1'b0}} ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n ); \n end\n else if(y==N-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(12)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (result[N*ACC_WIDTH*z+(x+1)*ACC_WIDTH-1 : ACC_WIDTH*N*z+x*ACC_WIDTH] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(11)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n );\n end \n end\n end\n end\n end\n end\n endgenerate\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/top.v", "`timescale 1ns / 1ps\n\n// Calculate matrix (A*B)\n// Size of A is (A_H*A_W), size of B is (B_H*B_W), and A_W = B_H\n// Size of output matirx A*B is (A_H*B_W)\n\nmodule top #\n(\n parameter N = 8, //CHANGE\n parameter WIDTH = 8, \n parameter ACC_WIDTH = 2*WIDTH + $clog2(N) \n)\n(\n input wire rst_n ,\n input wire clk ,\n input wire [N*N*WIDTH-1 :0] A ,\n input wire [N*N*WIDTH-1 :0] B ,\n output wire [N*N*2*ACC_WIDTH-1 :0] result \n);\n\nreg [N*N*WIDTH-1 :0] A_reg ;\nreg [N*N*WIDTH-1 :0] B_reg ;\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n A_reg<={(N*N*WIDTH){1'b0}};\n B_reg<={(N*N*WIDTH){1'b0}};\n end\n else begin\n A_reg<=A;\n B_reg<=B;\n end\nend\n\n\nwire signed [WIDTH-1:0] d_x [0:N-1][0:N-1][0:N-1];\nwire signed [2*ACC_WIDTH-1:0] d_y [0:N-1][0:N-1][0:N-1];\nwire signed [WIDTH-1:0] d_z [0:N-1][0:N-1][0:N-1];\n\n\n genvar x, y, z;\n generate\n for (z = 0; z < N; z = z + 1 ) begin\n for(x = 0; x < N; x = x + 1) begin\n for (y = 0; y < N; y = y + 1 ) begin\n if(z==0) begin\n if(x==0) begin\n if(y==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE //(1)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p ({2*ACC_WIDTH{1'b0}} ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n ); \n end\n else if(y==N-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(3)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (result[N*2*ACC_WIDTH*z+(x+1)*2*ACC_WIDTH-1 : 2*ACC_WIDTH*N*z+x*2*ACC_WIDTH] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(2)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n );\n end\n end\n else begin\n if(y==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE //(6)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p ({2*ACC_WIDTH{1'b0}} ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n ); \n end\n else if(y==N-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(5)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (result[N*2*ACC_WIDTH*z+(x+1)*2*ACC_WIDTH-1 : 2*ACC_WIDTH*N*z+x*2*ACC_WIDTH] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(4)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n );\n end \n end\n end\n else begin\n if(x==0) begin\n if(y==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE //(7)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p ({2*ACC_WIDTH{1'b0}} ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n ); \n end\n else if(y==N-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(9)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (result[N*2*ACC_WIDTH*z+(x+1)*2*ACC_WIDTH-1 : 2*ACC_WIDTH*N*z+x*2*ACC_WIDTH] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(8)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n );\n end\n end\n else begin\n if(y==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE //(10)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p ({2*ACC_WIDTH{1'b0}} ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n ); \n end\n else if(y==N-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(12)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (result[N*2*ACC_WIDTH*z+(x+1)*2*ACC_WIDTH-1 : 2*ACC_WIDTH*N*z+x*2*ACC_WIDTH] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(11)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n );\n end \n end\n end\n end\n end\n end\n endgenerate\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/DW02_tree.sv", "////////////////////////////////////////////////////////////////////////////////\n//\n// This confidential and proprietary software may be used only\n// as authorized by a licensing agreement from Synopsys Inc.\n// In the event of publication, the following notice is applicable:\n//\n// (C) COPYRIGHT 2000 - 2021 SYNOPSYS INC.\n// ALL RIGHTS RESERVED\n//\n// The entire notice above must be reproduced on all authorized\n// copies.\n//\n// AUTHOR: Rick Kelly 07/28/2000\n//\n// VERSION: Verilog Simulation Model for DW02_tree\n//\n// DesignWare_version: aacb4808\n// DesignWare_release: S-2021.06-DWBB_202106.4\n//\n////////////////////////////////////////////////////////////////////////////////\n\n//-----------------------------------------------------------------------------------\n//\n// ABSTRACT: Wallace Tree Summer with Carry Save output\n//\n// MODIFIED:\n// Aamir Farooqui 7/11/02\n// Corrected parameter checking, simplied sim model, and X_processing\n//\n//------------------------------------------------------------------------------\n//\n\n // synopsys translate_off\n// `ifdef VCS\n// `include \"DW02_tree.v\"\n// `else\n // synopsys translate_on\n\nmodule DW02_tree( INPUT, OUT0, OUT1 );\n\n// parameters\nparameter integer num_inputs = 8;\nparameter integer input_width = 8;\nparameter integer verif_en = 1;\n\n//-----------------------------------------------------------------------------\n// ports\ninput [num_inputs*input_width-1 : 0]\tINPUT;\noutput [input_width-1:0]\t\tOUT0, OUT1;\n\n//-----------------------------------------------------------------------------\n// synopsys translate_off\nreg [input_width-1:0]\t\tOII0OOOI, O001l0I0;\n\n//-----------------------------------------------------------------------------\n \n \n// initial begin : parameter_check\n// integer param_err_flg;\n\n// param_err_flg = 0;\n \n \n// if (num_inputs < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter num_inputs (lower bound: 1)\",\n// \tnum_inputs );\n// end\n \n// if (input_width < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter input_width (lower bound: 1)\",\n// \tinput_width );\n// end\n \n// if ( (verif_en < 0) || (verif_en > 1) ) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter verif_en (legal range: 0 to 1)\",\n// \tverif_en );\n// end\n \n// if ( param_err_flg == 1) begin\n// $display(\n// \"%m :\\n Simulation aborted due to invalid parameter value(s)\");\n// $finish;\n// end\n\n// end // parameter_check \n\n\n// `ifndef DW_SUPPRESS_WARN\n// initial begin : verif_en_warning\n// $display(\"The parameter verif_en is set to 0 for this simulator.\\nOther values for verif_en are enabled only for VCS.\");\n// end // verif_en_warning\n// `endif\n\n//-----------------------------------------------------------------------------\n\n\n\nalways @ (INPUT) begin : IIIIO1Ol\n reg [input_width-1 : 0] I0lII01I [0 : num_inputs-1];\n reg [input_width-1 : 0] l10III00 [0 : num_inputs-1];\n reg [input_width-1 : 0] IIIO00Ol, lI0OII0O;\n integer I1I1O00I, O1OIIOII, IlI01lIO;\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII=O1OIIOII+1) begin\n for (IlI01lIO=0 ; IlI01lIO < input_width ; IlI01lIO=IlI01lIO+1) begin\n IIIO00Ol[IlI01lIO] = INPUT[O1OIIOII*input_width+IlI01lIO];\n end // for IlI01lIO\n I0lII01I[O1OIIOII] = IIIO00Ol;\n end // for O1OIIOII\n\n I1I1O00I = num_inputs;\n\n while (I1I1O00I > 2)\n begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I/3) ; O1OIIOII = O1OIIOII+1) begin\n l10III00[O1OIIOII*2] = I0lII01I[O1OIIOII*3] ^ I0lII01I[O1OIIOII*3+1] ^ I0lII01I[O1OIIOII*3+2];\n\n lI0OII0O = (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+1]) |\n (I0lII01I[O1OIIOII*3+1] & I0lII01I[O1OIIOII*3+2]) |\n (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+2]);\n\n l10III00[O1OIIOII*2+1] = lI0OII0O << 1;\n end\n if ((I1I1O00I % 3) > 0) begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I % 3) ; O1OIIOII = O1OIIOII + 1)\n l10III00[2 * (I1I1O00I/3) + O1OIIOII] = I0lII01I[3 * (I1I1O00I/3) + O1OIIOII];\n end\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII = O1OIIOII + 1)\n I0lII01I[O1OIIOII] = l10III00[O1OIIOII];\n I1I1O00I = I1I1O00I - (I1I1O00I/3);\n end\n OII0OOOI = I0lII01I[0];\n if (I1I1O00I > 1)\n O001l0I0 = I0lII01I[1];\n else\n O001l0I0 = {input_width{1'b0}};\nend // IIIIO1Ol\n\n\nassign OUT0 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : OII0OOOI;\nassign OUT1 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : O001l0I0;\n\n// synopsys translate_on\n\nendmodule\n // synopsys translate_off\n// `endif\n // synopsys translate_on\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/DW02_tree.sv", "////////////////////////////////////////////////////////////////////////////////\n//\n// This confidential and proprietary software may be used only\n// as authorized by a licensing agreement from Synopsys Inc.\n// In the event of publication, the following notice is applicable:\n//\n// (C) COPYRIGHT 2000 - 2021 SYNOPSYS INC.\n// ALL RIGHTS RESERVED\n//\n// The entire notice above must be reproduced on all authorized\n// copies.\n//\n// AUTHOR: Rick Kelly 07/28/2000\n//\n// VERSION: Verilog Simulation Model for DW02_tree\n//\n// DesignWare_version: aacb4808\n// DesignWare_release: S-2021.06-DWBB_202106.4\n//\n////////////////////////////////////////////////////////////////////////////////\n\n//-----------------------------------------------------------------------------------\n//\n// ABSTRACT: Wallace Tree Summer with Carry Save output\n//\n// MODIFIED:\n// Aamir Farooqui 7/11/02\n// Corrected parameter checking, simplied sim model, and X_processing\n//\n//------------------------------------------------------------------------------\n//\n\n // synopsys translate_off\n// `ifdef VCS\n// `include \"DW02_tree.v\"\n// `else\n // synopsys translate_on\n\nmodule DW02_tree( INPUT, OUT0, OUT1 );\n\n// parameters\nparameter integer num_inputs = 8;\nparameter integer input_width = 8;\nparameter integer verif_en = 1;\n\n//-----------------------------------------------------------------------------\n// ports\ninput [num_inputs*input_width-1 : 0]\tINPUT;\noutput [input_width-1:0]\t\tOUT0, OUT1;\n\n//-----------------------------------------------------------------------------\n// synopsys translate_off\nreg [input_width-1:0]\t\tOII0OOOI, O001l0I0;\n\n//-----------------------------------------------------------------------------\n \n \n// initial begin : parameter_check\n// integer param_err_flg;\n\n// param_err_flg = 0;\n \n \n// if (num_inputs < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter num_inputs (lower bound: 1)\",\n// \tnum_inputs );\n// end\n \n// if (input_width < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter input_width (lower bound: 1)\",\n// \tinput_width );\n// end\n \n// if ( (verif_en < 0) || (verif_en > 1) ) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter verif_en (legal range: 0 to 1)\",\n// \tverif_en );\n// end\n \n// if ( param_err_flg == 1) begin\n// $display(\n// \"%m :\\n Simulation aborted due to invalid parameter value(s)\");\n// $finish;\n// end\n\n// end // parameter_check \n\n\n// `ifndef DW_SUPPRESS_WARN\n// initial begin : verif_en_warning\n// $display(\"The parameter verif_en is set to 0 for this simulator.\\nOther values for verif_en are enabled only for VCS.\");\n// end // verif_en_warning\n// `endif\n\n//-----------------------------------------------------------------------------\n\n\n\nalways @ (INPUT) begin : IIIIO1Ol\n reg [input_width-1 : 0] I0lII01I [0 : num_inputs-1];\n reg [input_width-1 : 0] l10III00 [0 : num_inputs-1];\n reg [input_width-1 : 0] IIIO00Ol, lI0OII0O;\n integer I1I1O00I, O1OIIOII, IlI01lIO;\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII=O1OIIOII+1) begin\n for (IlI01lIO=0 ; IlI01lIO < input_width ; IlI01lIO=IlI01lIO+1) begin\n IIIO00Ol[IlI01lIO] = INPUT[O1OIIOII*input_width+IlI01lIO];\n end // for IlI01lIO\n I0lII01I[O1OIIOII] = IIIO00Ol;\n end // for O1OIIOII\n\n I1I1O00I = num_inputs;\n\n while (I1I1O00I > 2)\n begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I/3) ; O1OIIOII = O1OIIOII+1) begin\n l10III00[O1OIIOII*2] = I0lII01I[O1OIIOII*3] ^ I0lII01I[O1OIIOII*3+1] ^ I0lII01I[O1OIIOII*3+2];\n\n lI0OII0O = (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+1]) |\n (I0lII01I[O1OIIOII*3+1] & I0lII01I[O1OIIOII*3+2]) |\n (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+2]);\n\n l10III00[O1OIIOII*2+1] = lI0OII0O << 1;\n end\n if ((I1I1O00I % 3) > 0) begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I % 3) ; O1OIIOII = O1OIIOII + 1)\n l10III00[2 * (I1I1O00I/3) + O1OIIOII] = I0lII01I[3 * (I1I1O00I/3) + O1OIIOII];\n end\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII = O1OIIOII + 1)\n I0lII01I[O1OIIOII] = l10III00[O1OIIOII];\n I1I1O00I = I1I1O00I - (I1I1O00I/3);\n end\n OII0OOOI = I0lII01I[0];\n if (I1I1O00I > 1)\n O001l0I0 = I0lII01I[1];\n else\n O001l0I0 = {input_width{1'b0}};\nend // IIIIO1Ol\n\n\nassign OUT0 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : OII0OOOI;\nassign OUT1 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : O001l0I0;\n\n// synopsys translate_on\n\nendmodule\n // synopsys translate_off\n// `endif\n // synopsys translate_on\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/DW02_tree.sv", "////////////////////////////////////////////////////////////////////////////////\n//\n// This confidential and proprietary software may be used only\n// as authorized by a licensing agreement from Synopsys Inc.\n// In the event of publication, the following notice is applicable:\n//\n// (C) COPYRIGHT 2000 - 2021 SYNOPSYS INC.\n// ALL RIGHTS RESERVED\n//\n// The entire notice above must be reproduced on all authorized\n// copies.\n//\n// AUTHOR: Rick Kelly 07/28/2000\n//\n// VERSION: Verilog Simulation Model for DW02_tree\n//\n// DesignWare_version: aacb4808\n// DesignWare_release: S-2021.06-DWBB_202106.4\n//\n////////////////////////////////////////////////////////////////////////////////\n\n//-----------------------------------------------------------------------------------\n//\n// ABSTRACT: Wallace Tree Summer with Carry Save output\n//\n// MODIFIED:\n// Aamir Farooqui 7/11/02\n// Corrected parameter checking, simplied sim model, and X_processing\n//\n//------------------------------------------------------------------------------\n//\n\n // synopsys translate_off\n// `ifdef VCS\n// `include \"DW02_tree.v\"\n// `else\n // synopsys translate_on\n\nmodule DW02_tree( INPUT, OUT0, OUT1 );\n\n// parameters\nparameter integer num_inputs = 8;\nparameter integer input_width = 8;\nparameter integer verif_en = 1;\n\n//-----------------------------------------------------------------------------\n// ports\ninput [num_inputs*input_width-1 : 0]\tINPUT;\noutput [input_width-1:0]\t\tOUT0, OUT1;\n\n//-----------------------------------------------------------------------------\n// synopsys translate_off\nreg [input_width-1:0]\t\tOII0OOOI, O001l0I0;\n\n//-----------------------------------------------------------------------------\n \n \n// initial begin : parameter_check\n// integer param_err_flg;\n\n// param_err_flg = 0;\n \n \n// if (num_inputs < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter num_inputs (lower bound: 1)\",\n// \tnum_inputs );\n// end\n \n// if (input_width < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter input_width (lower bound: 1)\",\n// \tinput_width );\n// end\n \n// if ( (verif_en < 0) || (verif_en > 1) ) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter verif_en (legal range: 0 to 1)\",\n// \tverif_en );\n// end\n \n// if ( param_err_flg == 1) begin\n// $display(\n// \"%m :\\n Simulation aborted due to invalid parameter value(s)\");\n// $finish;\n// end\n\n// end // parameter_check \n\n\n// `ifndef DW_SUPPRESS_WARN\n// initial begin : verif_en_warning\n// $display(\"The parameter verif_en is set to 0 for this simulator.\\nOther values for verif_en are enabled only for VCS.\");\n// end // verif_en_warning\n// `endif\n\n//-----------------------------------------------------------------------------\n\n\n\nalways @ (INPUT) begin : IIIIO1Ol\n reg [input_width-1 : 0] I0lII01I [0 : num_inputs-1];\n reg [input_width-1 : 0] l10III00 [0 : num_inputs-1];\n reg [input_width-1 : 0] IIIO00Ol, lI0OII0O;\n integer I1I1O00I, O1OIIOII, IlI01lIO;\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII=O1OIIOII+1) begin\n for (IlI01lIO=0 ; IlI01lIO < input_width ; IlI01lIO=IlI01lIO+1) begin\n IIIO00Ol[IlI01lIO] = INPUT[O1OIIOII*input_width+IlI01lIO];\n end // for IlI01lIO\n I0lII01I[O1OIIOII] = IIIO00Ol;\n end // for O1OIIOII\n\n I1I1O00I = num_inputs;\n\n while (I1I1O00I > 2)\n begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I/3) ; O1OIIOII = O1OIIOII+1) begin\n l10III00[O1OIIOII*2] = I0lII01I[O1OIIOII*3] ^ I0lII01I[O1OIIOII*3+1] ^ I0lII01I[O1OIIOII*3+2];\n\n lI0OII0O = (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+1]) |\n (I0lII01I[O1OIIOII*3+1] & I0lII01I[O1OIIOII*3+2]) |\n (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+2]);\n\n l10III00[O1OIIOII*2+1] = lI0OII0O << 1;\n end\n if ((I1I1O00I % 3) > 0) begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I % 3) ; O1OIIOII = O1OIIOII + 1)\n l10III00[2 * (I1I1O00I/3) + O1OIIOII] = I0lII01I[3 * (I1I1O00I/3) + O1OIIOII];\n end\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII = O1OIIOII + 1)\n I0lII01I[O1OIIOII] = l10III00[O1OIIOII];\n I1I1O00I = I1I1O00I - (I1I1O00I/3);\n end\n OII0OOOI = I0lII01I[0];\n if (I1I1O00I > 1)\n O001l0I0 = I0lII01I[1];\n else\n O001l0I0 = {input_width{1'b0}};\nend // IIIIO1Ol\n\n\nassign OUT0 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : OII0OOOI;\nassign OUT1 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : O001l0I0;\n\n// synopsys translate_on\n\nendmodule\n // synopsys translate_off\n// `endif\n // synopsys translate_on\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_mac_based/top.v", "module top #\n(\n parameter A_H = 16, \n parameter B_W = 16, \n parameter WIDTH = 8,\n parameter ACC_WIDTH = 32 \n)\n(\n input wire rst_n ,\n input wire clk ,\n input wire [A_H*WIDTH-1 :0] A ,\n input wire [B_W*WIDTH-1 :0] B ,\n input wire clc , // clean_result_cache,\n output wire [A_H*B_W*ACC_WIDTH-1 :0] result \n);\n\nreg [A_H*WIDTH-1 :0] A_reg ;\nreg [B_W*WIDTH-1 :0] B_reg ;\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n A_reg<={(A_H*WIDTH){1'b0}};\n B_reg<={(B_W*WIDTH){1'b0}};\n end\n else begin\n A_reg<=A;\n B_reg<=B;\n end\nend\n\nwire signed [WIDTH-1:0] row [0:A_H-1][0:B_W-1];\nwire signed [WIDTH-1:0] col [0:A_H-1][0:B_W-1];\n\n\n genvar i, j;\n generate\n for (i = 0; i < A_H; i = i + 1 ) begin\n for(j = 0; j < B_W; j = j + 1) begin\n if(i==0) begin\n if(j==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .a (A_reg[WIDTH-1 :0] ),\n .b (B_reg[WIDTH-1 :0] ),\n .clc (clc ),\n .row (row[i][j] ),\n .col (col[i][j] ),\n .result (result[(i*B_W+j+1)*ACC_WIDTH-1:(i*B_W+j)*ACC_WIDTH])\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .a (row[i][j-1] ),\n .b (B_reg[WIDTH*(j+1)-1 :WIDTH*j] ),\n .clc (clc ),\n .row (row[i][j] ),\n .col (col[i][j] ),\n .result (result[(i*B_W+j+1)*ACC_WIDTH-1:(i*B_W+j)*ACC_WIDTH])\n );\n end\n end\n else if (j==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .a (A_reg[WIDTH*(i+1)-1 :WIDTH*i] ),\n .b (col[i-1][j] ),\n .clc (clc ),\n .row (row[i][j] ),\n .col (col[i][j] ),\n .result (result[(i*B_W+j+1)*ACC_WIDTH-1:(i*B_W+j)*ACC_WIDTH])\n );\n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .a (row[i][j-1] ),\n .b (col[i-1][j] ),\n .clc (clc ),\n .row (row[i][j] ),\n .col (col[i][j] ),\n .result (result[(i*B_W+j+1)*ACC_WIDTH-1:(i*B_W+j)*ACC_WIDTH])\n ); \n \n end \n end\n end\n endgenerate\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/top.v", "module top #\n(\n parameter A_H = 16, //CHANGE\n parameter B_W = 16, //CHANGE\n parameter WIDTH = 8,\n parameter ACC_WIDTH = 32 //CHANGE\n)\n(\n input wire rst_n ,\n input wire clk ,\n input wire [A_H*WIDTH-1 :0] A ,\n input wire [B_W*WIDTH-1 :0] B ,\n input wire clc , // clean_result_cache\n// output wire [A_H*B_W*ACC_WIDTH-1 :0] result \n output wire [2*A_H*B_W*ACC_WIDTH-1 :0] result \n);\n\nreg [A_H*WIDTH-1 :0] A_reg ;\nreg [B_W*WIDTH-1 :0] B_reg ;\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n A_reg<={(A_H*WIDTH){1'b0}};\n B_reg<={(B_W*WIDTH){1'b0}};\n end\n else begin\n A_reg<=A;\n B_reg<=B;\n end\nend\n\nwire signed [WIDTH-1:0] row [0:A_H-1][0:B_W-1];\nwire signed [WIDTH-1:0] col [0:A_H-1][0:B_W-1];\n\n\n genvar i, j;\n generate\n for (i = 0; i < A_H; i = i + 1 ) begin\n for(j = 0; j < B_W; j = j + 1) begin\n if(i==0) begin\n if(j==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .a (A_reg[WIDTH-1 :0] ),\n .b (B_reg[WIDTH-1 :0] ),\n .clc (clc ), // input wire clean_result_cache\n .row (row[i][j] ),\n .col (col[i][j] ),\n// .result (result[(i*B_W+j+1)*ACC_WIDTH-1:(i*B_W+j)*ACC_WIDTH])\n .result (result[(i*B_W+j+1)*2*ACC_WIDTH-1:(i*B_W+j)*2*ACC_WIDTH])\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .a (row[i][j-1] ),\n .b (B_reg[WIDTH*(j+1)-1 :WIDTH*j] ),\n .clc (clc ), // input wire clean_result_cache\n .row (row[i][j] ),\n .col (col[i][j] ),\n// .result (result[(i*B_W+j+1)*ACC_WIDTH-1:(i*B_W+j)*ACC_WIDTH])\n .result (result[(i*B_W+j+1)*2*ACC_WIDTH-1:(i*B_W+j)*2*ACC_WIDTH])\n );\n end\n end\n else if (j==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .a (A_reg[WIDTH*(i+1)-1 :WIDTH*i] ),\n .b (col[i-1][j] ),\n .clc (clc ), // input wire clean_result_cache\n .row (row[i][j] ),\n .col (col[i][j] ),\n// .result (result[(i*B_W+j+1)*ACC_WIDTH-1:(i*B_W+j)*ACC_WIDTH])\n .result (result[(i*B_W+j+1)*2*ACC_WIDTH-1:(i*B_W+j)*2*ACC_WIDTH])\n );\n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .a (row[i][j-1] ),\n .b (col[i-1][j] ),\n .clc (clc ), // input wire clean_result_cache\n .row (row[i][j] ),\n .col (col[i][j] ),\n// .result (result[(i*B_W+j+1)*ACC_WIDTH-1:(i*B_W+j)*ACC_WIDTH])\n .result (result[(i*B_W+j+1)*2*ACC_WIDTH-1:(i*B_W+j)*2*ACC_WIDTH])\n ); \n \n end \n end\n end\n endgenerate\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/opt1_mac.v", "module opt1_mac #(\n parameter ACC_WIDTH = 32,\n parameter INPUT_PIP = 1\n)(\n input wire clk,\n input wire rst_n,\n input wire [7:0] operand_a_in, \n input wire [7:0] operand_b_in, \n input wire signed [2*ACC_WIDTH-1:0] partial_result, \n output reg [ACC_WIDTH-1:0] acc_sum,\n output reg [ACC_WIDTH-1:0] acc_carry\n);\n\nreg [7:0] operand_a;\nreg [7:0] operand_b;\n\nwire signed [9:0] pp1;\nwire signed [9:0] pp2;\nwire signed [9:0] pp3;\nwire signed [9:0] pp4;\nwire [6*ACC_WIDTH-1 : 0] mul_reduce_csa_input;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp1;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp2;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp3;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp4;\nwire signed [ACC_WIDTH-1:0] reduce_acc_sum;\nwire signed [ACC_WIDTH-1:0] reduce_acc_carry;\n\nassign sign_extend_pp4 = $signed({pp4,6'b0});\nassign sign_extend_pp3 = $signed({pp3,4'b0});\nassign sign_extend_pp2 = $signed({pp2,2'b0});\nassign sign_extend_pp1 = $signed(pp1);\n\nassign mul_reduce_csa_input = {sign_extend_pp4,sign_extend_pp3,sign_extend_pp2,sign_extend_pp1,partial_result[0+:ACC_WIDTH],partial_result[ACC_WIDTH+:ACC_WIDTH]};\n\nbooth_pp_gen booth_pp_gen_inst(\n .operand_a(operand_a), \n .operand_b(operand_b), \n .pp1(pp1),\n .pp2(pp2),\n .pp3(pp3),\n .pp4(pp4)\n);\n\nDW02_tree #(6, ACC_WIDTH, 1)\n U2 ( .INPUT(mul_reduce_csa_input), .OUT0(reduce_acc_sum), .OUT1(reduce_acc_carry) );\n\nalways @(posedge clk) begin\n if (!rst_n) begin\n acc_sum <= 0;\n acc_carry <= 0;\n end\n else begin\n acc_sum <= reduce_acc_sum;\n acc_carry <= reduce_acc_carry;\n end\nend\n\ngenerate\n if(INPUT_PIP == 1) begin\n always @(posedge clk) begin\n operand_a <= operand_a_in;\n operand_b <= operand_b_in;\n end\n end\n else begin\n always @(*) begin\n operand_a = operand_a_in;\n operand_b = operand_b_in;\n end\n end\nendgenerate\n\n// dff_async #(\n// .WIDTH(ACC_WIDTH)) acc_sum_reg (\n// .clk(clk),\n// .rst_n(rst_n),\n// .d(reduce_acc_sum),\n// .q(acc_sum)\n// );\n\n// dff_async #(\n// .WIDTH(ACC_WIDTH)) acc_carry_reg (\n// .clk(clk),\n// .rst_n(rst_n),\n// .d(reduce_acc_carry),\n// .q(acc_carry)\n// );\n\n\n\n \nendmodule\n\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/opt1_mac.v", "module opt1_mac #(\n parameter ACC_WIDTH = 32,\n parameter INPUT_PIP = 1\n)(\n input wire clk,\n input wire rst_n,\n input wire [7:0] operand_a_in, \n input wire [7:0] operand_b_in, \n input wire signed [2*ACC_WIDTH-1:0] partial_result, \n output reg [ACC_WIDTH-1:0] acc_sum,\n output reg [ACC_WIDTH-1:0] acc_carry\n);\n\nreg [7:0] operand_a;\nreg [7:0] operand_b;\n\nwire signed [9:0] pp1;\nwire signed [9:0] pp2;\nwire signed [9:0] pp3;\nwire signed [9:0] pp4;\nwire [6*ACC_WIDTH-1 : 0] mul_reduce_csa_input;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp1;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp2;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp3;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp4;\nwire signed [ACC_WIDTH-1:0] reduce_acc_sum;\nwire signed [ACC_WIDTH-1:0] reduce_acc_carry;\n\nassign sign_extend_pp4 = $signed({pp4,6'b0});\nassign sign_extend_pp3 = $signed({pp3,4'b0});\nassign sign_extend_pp2 = $signed({pp2,2'b0});\nassign sign_extend_pp1 = $signed(pp1);\n\nassign mul_reduce_csa_input = {sign_extend_pp4,sign_extend_pp3,sign_extend_pp2,sign_extend_pp1,partial_result[0+:ACC_WIDTH],partial_result[ACC_WIDTH+:ACC_WIDTH]};\n\nbooth_pp_gen booth_pp_gen_inst(\n .operand_a(operand_a), \n .operand_b(operand_b), \n .pp1(pp1),\n .pp2(pp2),\n .pp3(pp3),\n .pp4(pp4)\n);\n\nDW02_tree #(6, ACC_WIDTH, 1)\n U2 ( .INPUT(mul_reduce_csa_input), .OUT0(reduce_acc_sum), .OUT1(reduce_acc_carry) );\n\nalways @(posedge clk) begin\n if (!rst_n) begin\n acc_sum <= 0;\n acc_carry <= 0;\n end\n else begin\n acc_sum <= reduce_acc_sum;\n acc_carry <= reduce_acc_carry;\n end\nend\n\ngenerate\n if(INPUT_PIP == 1) begin\n always @(posedge clk) begin\n operand_a <= operand_a_in;\n operand_b <= operand_b_in;\n end\n end\n else begin\n always @(*) begin\n operand_a = operand_a_in;\n operand_b = operand_b_in;\n end\n end\nendgenerate\n\n// dff_async #(\n// .WIDTH(ACC_WIDTH)) acc_sum_reg (\n// .clk(clk),\n// .rst_n(rst_n),\n// .d(reduce_acc_sum),\n// .q(acc_sum)\n// );\n\n// dff_async #(\n// .WIDTH(ACC_WIDTH)) acc_carry_reg (\n// .clk(clk),\n// .rst_n(rst_n),\n// .d(reduce_acc_carry),\n// .q(acc_carry)\n// );\n\n\n\n \nendmodule\n\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_mac_based/top.v", "// Calculate matrix (A*B)\n// Size of A is (M*K), size of B is (K*N), and A_H = K, B_W = N, B is weight\n// Size of output matirx A*B is (M*N)\n\nmodule top #\n(\n parameter A_H = 16, \n parameter B_W = 16, \n parameter WIDTH = 8,\n // parameter ACC_WIDTH = 32 \n parameter ACC_WIDTH = 2*WIDTH + $clog2(A_H)\n)\n(\n input wire clk ,\n input wire rst_n ,\n input weight_wen ,\n input [A_H*WIDTH-1 :0] weight_din ,\n input wire [A_H*WIDTH-1 :0] A ,\n output wire [B_W*ACC_WIDTH-1 :0] result \n);\n\nreg [A_H*WIDTH-1 :0] A_reg ;\nreg [A_H*WIDTH-1 :0] weight_din_reg;\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n A_reg<={(A_H*WIDTH){1'b0}};\n weight_din_reg <= {(B_W*WIDTH){1'b0}};\n end\n else begin\n A_reg<=A;\n weight_din_reg <= weight_din;\n end\nend\n\n\nwire signed [ACC_WIDTH-1:0] row [0:B_W-1][0:A_H-1];\nwire signed [WIDTH-1:0] col [0:B_W-1][0:A_H-1];\n\n\n genvar i, j;\n generate\n for (i = 0; i < B_W; i = i + 1 ) begin\n for(j = 0; j < A_H; j = j + 1) begin\n if(j==0) begin\n if(i==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .weight_wen (weight_wen ),\n .weight_din (weight_din_reg[(j+1)*WIDTH-1:j*WIDTH] ),\n .a (A_reg[(j+1)*WIDTH-1:j*WIDTH] ),\n .partial_result ({ACC_WIDTH{1'b0}} ), // or input\n .row (row[i][j] ),\n .col (col[i][j] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .weight_wen (weight_wen ),\n .weight_din (col[i-1][j] ),\n .a (col[i-1][j] ),\n .partial_result ({ACC_WIDTH{1'b0}} ), // or input\n .row (row[i][j] ),\n .col (col[i][j] )\n ); \n end\n end\n else if (i==0) begin\n if(j==A_H-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .weight_wen (weight_wen ),\n .weight_din (weight_din_reg[(j+1)*WIDTH-1:j*WIDTH] ),\n .a (A_reg[(j+1)*WIDTH-1:j*WIDTH] ),\n .partial_result (row[i][j-1] ),\n .row (result[(i+1)*ACC_WIDTH-1 :i*ACC_WIDTH] ),\n .col (col[i][j] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .weight_wen (weight_wen ),\n .weight_din (weight_din_reg[(j+1)*WIDTH-1:j*WIDTH] ),\n .a (A_reg[(j+1)*WIDTH-1:j*WIDTH] ),\n .partial_result (row[i][j-1] ),\n .row (row[i][j] ),\n .col (col[i][j] )\n ); \n end\n end\n else if (j==A_H-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .weight_wen (weight_wen ),\n .weight_din (col[i-1][j] ),\n .a (col[i-1][j] ),\n .partial_result (row[i][j-1] ),\n .row (result[(i+1)*ACC_WIDTH-1 :i*ACC_WIDTH] ),\n .col (col[i][j] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .weight_wen (weight_wen ),\n .weight_din (col[i-1][j] ),\n .a (col[i-1][j] ),\n .partial_result (row[i][j-1] ),\n .row (row[i][j] ),\n .col (col[i][j] )\n ); \n end\n end\n end\nendgenerate\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/opt1_mac.v", "module opt1_mac #(\n parameter ACC_WIDTH = 32,\n parameter INPUT_PIP = 1\n)(\n input wire clk,\n input wire rst_n,\n input wire [7:0] operand_a_in, \n input wire [7:0] operand_b_in, \n input wire clc, // clean_result_cache\n output reg [ACC_WIDTH-1:0] acc_sum,\n output reg [ACC_WIDTH-1:0] acc_carry\n);\n\nreg [7:0] operand_a;\nreg [7:0] operand_b;\n\nwire signed [9:0] pp1;\nwire signed [9:0] pp2;\nwire signed [9:0] pp3;\nwire signed [9:0] pp4;\nwire [6*ACC_WIDTH-1 : 0] mul_reduce_csa_input;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp1;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp2;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp3;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp4;\nwire signed [ACC_WIDTH-1:0] reduce_acc_sum;\nwire signed [ACC_WIDTH-1:0] reduce_acc_carry;\n\nassign sign_extend_pp4 = $signed({pp4,6'b0});\nassign sign_extend_pp3 = $signed({pp3,4'b0});\nassign sign_extend_pp2 = $signed({pp2,2'b0});\nassign sign_extend_pp1 = $signed(pp1);\n\nassign mul_reduce_csa_input = {sign_extend_pp4,sign_extend_pp3,sign_extend_pp2,sign_extend_pp1,acc_carry,acc_sum};\n\nbooth_pp_gen booth_pp_gen_inst(\n .operand_a(operand_a), \n .operand_b(operand_b), \n .pp1(pp1),\n .pp2(pp2),\n .pp3(pp3),\n .pp4(pp4)\n);\n\nDW02_tree #(6, ACC_WIDTH, 1)\n U2 ( .INPUT(mul_reduce_csa_input), .OUT0(reduce_acc_sum), .OUT1(reduce_acc_carry) );\n\nalways @(posedge clk) begin\n if (!rst_n) begin\n acc_sum <= 0;\n acc_carry <= 0;\n end\n else begin\n if(clc) begin\n acc_sum <= 0;\n acc_carry <= 0;\n end\n else begin\n acc_sum <= reduce_acc_sum;\n acc_carry <= reduce_acc_carry;\n end\n end\nend\n\ngenerate\n if(INPUT_PIP == 1) begin\n always @(posedge clk) begin\n operand_a <= operand_a_in;\n operand_b <= operand_b_in;\n end\n end\n else begin\n always @(*) begin\n operand_a = operand_a_in;\n operand_b = operand_b_in;\n end\n end\nendgenerate\n\n// dff_async #(\n// .WIDTH(ACC_WIDTH)) acc_sum_reg (\n// .clk(clk),\n// .rst_n(rst_n),\n// .d(reduce_acc_sum),\n// .q(acc_sum)\n// );\n\n// dff_async #(\n// .WIDTH(ACC_WIDTH)) acc_carry_reg (\n// .clk(clk),\n// .rst_n(rst_n),\n// .d(reduce_acc_carry),\n// .q(acc_carry)\n// );\n\n\n\n \nendmodule\n\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/opt1_mac.v", "module opt1_mac #(\n parameter ACC_WIDTH = 32,\n parameter INPUT_PIP = 1\n)(\n input wire clk,\n input wire rst_n,\n input wire [7:0] operand_a_in, \n input wire [7:0] operand_b_in, \n output reg [ACC_WIDTH-1:0] acc_sum,\n output reg [ACC_WIDTH-1:0] acc_carry\n);\n\nreg [7:0] operand_a;\nreg [7:0] operand_b;\n\nwire signed [9:0] pp1;\nwire signed [9:0] pp2;\nwire signed [9:0] pp3;\nwire signed [9:0] pp4;\nwire [6*ACC_WIDTH-1 : 0] mul_reduce_csa_input;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp1;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp2;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp3;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp4;\nwire signed [ACC_WIDTH-1:0] reduce_acc_sum;\nwire signed [ACC_WIDTH-1:0] reduce_acc_carry;\n\nassign sign_extend_pp4 = $signed({pp4,6'b0});\nassign sign_extend_pp3 = $signed({pp3,4'b0});\nassign sign_extend_pp2 = $signed({pp2,2'b0});\nassign sign_extend_pp1 = $signed(pp1);\n\nassign mul_reduce_csa_input = {sign_extend_pp4,sign_extend_pp3,sign_extend_pp2,sign_extend_pp1,acc_carry, acc_sum};\n\nbooth_pp_gen booth_pp_gen_inst(\n .operand_a(operand_a), \n .operand_b(operand_b), \n .pp1(pp1),\n .pp2(pp2),\n .pp3(pp3),\n .pp4(pp4)\n);\n\nDW02_tree #(6, ACC_WIDTH, 1)\n U2 ( .INPUT(mul_reduce_csa_input), .OUT0(reduce_acc_sum), .OUT1(reduce_acc_carry) );\n\nalways @(posedge clk) begin\n if (!rst_n) begin\n acc_sum <= 0;\n acc_carry <= 0;\n end\n else begin\n acc_sum <= reduce_acc_sum;\n acc_carry <= reduce_acc_carry;\n end\nend\n\ngenerate\n if(INPUT_PIP == 1) begin\n always @(posedge clk) begin\n operand_a <= operand_a_in;\n operand_b <= operand_b_in;\n end\n end\n else begin\n always @(*) begin\n operand_a = operand_a_in;\n operand_b = operand_b_in;\n end\n end\nendgenerate\n\n// dff_async #(\n// .WIDTH(ACC_WIDTH)) acc_sum_reg (\n// .clk(clk),\n// .rst_n(rst_n),\n// .d(reduce_acc_sum),\n// .q(acc_sum)\n// );\n\n// dff_async #(\n// .WIDTH(ACC_WIDTH)) acc_carry_reg (\n// .clk(clk),\n// .rst_n(rst_n),\n// .d(reduce_acc_carry),\n// .q(acc_carry)\n// );\n\n\n\n \nendmodule\n\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT3_OPT4C/pe/encoder_multi_bit.v", "module encoder_multi_bit #(\n localparam WIDTH = 8,\n localparam ENCODER_WIDTH = WIDTH + (WIDTH+1)%2,\n localparam TIMES = (WIDTH-1)/2 + (WIDTH-1)%2\n)(\n input clk,\n input rst_n,\n input [WIDTH-1:0] multiplicand,\n input multiplicand_valid, \n output reg [WIDTH:0] en_multiplicand, // native EN-T encoding is sent to tensorcore local memory or local rf.\n output en_multiplicand_valid\n );\n\nwire [WIDTH-1:0] encoder_input;\nwire [ENCODER_WIDTH-1:0] en_multiplicand_ins;\nwire [TIMES-1:0] en_t_c_out;\nreg [WIDTH-1:0] multiplicand_reg;\n\nassign encoder_input = (multiplicand_reg != 8'b10000000) ? {1'b0,multiplicand_reg[WIDTH-2:0]} : 8'b10000000;\nassign en_multiplicand_ins[ENCODER_WIDTH-1] = multiplicand_reg[WIDTH-1];\n\ngenvar i;\ngenerate for(i = 0; i < TIMES; i = i + 1) begin: gen_encoder \n if(i==0) begin\n assign en_multiplicand_ins[1:0] = multiplicand_reg[1:0];\n end\n else if (i==1)begin\n encoder ins_encoder\n (.A(encoder_input[2*i-1:2*i-2]),\n .C_IN(1'b0), \n .B(encoder_input[2*i+1:2*i]), \n .en_t_c_out(en_t_c_out[i]), \n .EN_B(en_multiplicand_ins[2*i+1:2*i]));\n end\n else begin\n encoder ins_encoder\n (.A(encoder_input[2*i-1:2*i-2]),\n .C_IN(en_t_c_out[i-1]), \n .B(encoder_input[2*i+1:2*i]), \n .en_t_c_out(en_t_c_out[i]), \n .EN_B(en_multiplicand_ins[2*i+1:2*i]));\n end \nend \nendgenerate \n\n\nalways @(posedge clk or negedge rst_n) begin\n\tif (!rst_n) begin\n en_multiplicand <= 0;\n multiplicand_reg <= 0;\n end\n\telse begin\n en_multiplicand <= en_multiplicand_ins; \n //multiplicand belongs to [-128,127] range and operand with complement representation use this logic:\n multiplicand_reg <= (multiplicand[WIDTH-1] & (multiplicand[WIDTH-2:0] != 0)) ? ({1'b1,~multiplicand[WIDTH-2:0] + 1'b1}) : multiplicand; \n //multiplicand belongs to [-127,127] range and operand with sign-magnitude representation use this logic:\n //multiplicand_reg <= multiplicand; \n end\nend\n\nget_pipeline_mulwidth #(\n .N(2), \n .WIDTH(1) \n) pipeline_en_multiplicand_valid (\n .clk(clk), \n .rst_n(rst_n), \n .signal(multiplicand_valid), \n .pipeline_signal(en_multiplicand_valid) \n);\n\nendmodule\n\n\nmodule encoder(A, C_IN, B, en_t_c_out, EN_B);\n\ninput wire [1:0] A;\ninput wire C_IN;\ninput wire [1:0] B;\n\noutput wire en_t_c_out;\noutput wire [1:0] EN_B;\n\nassign en_t_c_out = (A[0] & A[1]) | (A[1] & C_IN); \nassign EN_B = B + en_t_c_out;\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT2/top_pe_tile.sv", "module top_pe_tile #(\n localparam RESULT_WIDTH = 20\n)(\n input clk,\n input weight_wen,\n input [7:0] weight_din,\n input [3:0] bit_enable [0:15],\n input [7:0] partial_product_select [0:15],\n output reg signed [RESULT_WIDTH-1:0] result,\n output reg [3:0] bit_enable_pip [0:15],\n output reg [7:0] partial_product_select_pip [0:15]\n);\n\nlocalparam REDUCE_WIDTH = 13;\n\n//*********range of partial_product in same bit-weight********/\n//** 9bit: -256 ≤ partial_product ≤ 254 /\n//** 13bit: -4096 ≤ 16 * partial_product ≤ 4064 /\n//************************************************************/\nwire [7:0] weight [0:15];\nwire signed [9:0] partial_product [0:15][0:3]; \nwire signed [REDUCE_WIDTH-1:0] csa_extend [0:15][0:3];\nwire [16*REDUCE_WIDTH-1:0] csa_input [0:3];\nwire [4*REDUCE_WIDTH-1:0] mid_result [0:3];\nwire signed [REDUCE_WIDTH-1:0] result_bw [0:3];\nwire signed [RESULT_WIDTH-1:0] bw_0;\nwire signed [RESULT_WIDTH-1:0] bw_1;\nwire signed [RESULT_WIDTH-1:0] bw_2;\nwire signed [RESULT_WIDTH-1:0] bw_3;\n\n\nweight_rf weight_buffer(\n .clk(clk),\n .wen(weight_wen),\n .din(weight_din),\n .weight(weight) \n);\n\ngenvar i,j;\ngenerate\n for (i=0;i<16;i=i+1) begin\n partial_product_select pps (\n .clk(clk),\n .weight(weight[i]),\n .bit_enable(bit_enable_pip[i]),\n .partial_product_select(partial_product_select_pip[i]),\n .partial_product(partial_product[i])\n );\n end\nendgenerate\n\ngenerate\n for (i=0;i<16;i=i+1) begin\n for (j=0;j<4;j=j+1) begin\n assign csa_extend[i][j] = $signed(partial_product[i][j]);\n end\n end\nendgenerate\n\ngenerate\n for (i=0;i<4;i=i+1) begin\n for (j=0;j<16;j=j+1) begin\n assign csa_input[i][(j+1)*REDUCE_WIDTH-1:j*REDUCE_WIDTH] = csa_extend[j][i];\n end\n end\nendgenerate\n\n\ngenerate\n for (i=0;i<4;i=i+1) begin\n\n tree_full_sum #(\n .K(4),\n .WIDTH(REDUCE_WIDTH)\n ) tree_stage_1_0 (\n .clk(clk),\n .csa_input({csa_input[i][1*REDUCE_WIDTH-1:0],\n csa_input[i][2*REDUCE_WIDTH-1:1*REDUCE_WIDTH],\n csa_input[i][3*REDUCE_WIDTH-1:2*REDUCE_WIDTH],\n csa_input[i][4*REDUCE_WIDTH-1:3*REDUCE_WIDTH]}),\n .full_sum(mid_result[i][1*REDUCE_WIDTH-1:0*REDUCE_WIDTH])\n );\n tree_full_sum #(\n .K(4),\n .WIDTH(REDUCE_WIDTH)\n ) tree_stage_1_1 (\n .clk(clk),\n .csa_input({csa_input[i][5*REDUCE_WIDTH-1:4*REDUCE_WIDTH],\n csa_input[i][6*REDUCE_WIDTH-1:5*REDUCE_WIDTH],\n csa_input[i][7*REDUCE_WIDTH-1:6*REDUCE_WIDTH],\n csa_input[i][8*REDUCE_WIDTH-1:7*REDUCE_WIDTH]}),\n .full_sum(mid_result[i][2*REDUCE_WIDTH-1:1*REDUCE_WIDTH])\n );\n tree_full_sum #(\n .K(4),\n .WIDTH(REDUCE_WIDTH)\n ) tree_stage_1_2 (\n .clk(clk),\n .csa_input({csa_input[i][9*REDUCE_WIDTH-1:8*REDUCE_WIDTH],\n csa_input[i][10*REDUCE_WIDTH-1:9*REDUCE_WIDTH],\n csa_input[i][11*REDUCE_WIDTH-1:10*REDUCE_WIDTH],\n csa_input[i][12*REDUCE_WIDTH-1:11*REDUCE_WIDTH]}),\n .full_sum(mid_result[i][3*REDUCE_WIDTH-1:2*REDUCE_WIDTH])\n );\n tree_full_sum #(\n .K(4),\n .WIDTH(REDUCE_WIDTH)\n ) tree_stage_1_3 (\n .clk(clk),\n .csa_input({csa_input[i][13*REDUCE_WIDTH-1:12*REDUCE_WIDTH],\n csa_input[i][14*REDUCE_WIDTH-1:13*REDUCE_WIDTH],\n csa_input[i][15*REDUCE_WIDTH-1:14*REDUCE_WIDTH],\n csa_input[i][16*REDUCE_WIDTH-1:15*REDUCE_WIDTH]}),\n .full_sum(mid_result[i][4*REDUCE_WIDTH-1:3*REDUCE_WIDTH])\n );\n end\nendgenerate\n\n\ngenerate\n for (i=0;i<4;i=i+1) begin\n tree_full_sum #(\n .K(4),\n .WIDTH(REDUCE_WIDTH)\n ) tree_stage_2 (\n .clk(clk),\n .csa_input({mid_result[i][1*REDUCE_WIDTH-1:0],\n mid_result[i][2*REDUCE_WIDTH-1:1*REDUCE_WIDTH],\n mid_result[i][3*REDUCE_WIDTH-1:2*REDUCE_WIDTH],\n mid_result[i][4*REDUCE_WIDTH-1:3*REDUCE_WIDTH]}),\n .full_sum(result_bw[i])\n );\n end\nendgenerate\n\n\nassign bw_0 = $signed(result_bw[0]);\nassign bw_1 = $signed({result_bw[1],2'b0});\nassign bw_2 = $signed({result_bw[2],4'b0});\nassign bw_3 = $signed({result_bw[3],6'b0});\n\ntree_full_sum #(\n .K(4),\n .WIDTH(RESULT_WIDTH)\n) tree_stage_3 (\n .clk(clk),\n .csa_input({bw_0,bw_1,bw_2,bw_3}),\n .full_sum(result)\n );\n\n// pipeline the bit_enable and partial_product_select\nalways @(posedge clk) begin\n bit_enable_pip <= bit_enable;\n partial_product_select_pip <= partial_product_select;\nend\n\nendmodule\n\n\n\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_mac_based/get_pipline_mulwidth.v", "module get_pipeline_mulwidth #(\n parameter N = 4,\n parameter WIDTH = 8 \n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] signal,\n output wire [WIDTH-1:0] pipeline_signal\n);\n\n\n reg [WIDTH-1:0] pipeline_regs [N-1:0];\n\n\n genvar i;\n generate\n for (i = 0; i < N; i = i + 1) begin : pipeline_stage\n always @(posedge clk) begin\n if(~rst_n) \n pipeline_regs[i] <= 0;\n else begin\n if (i == 0) begin\n pipeline_regs[i] <= signal; \n end else begin\n pipeline_regs[i] <= pipeline_regs[i-1]; \n end\n end\n end\n end\n endgenerate\n\n\n assign pipeline_signal = pipeline_regs[N-1];\n\nendmodule\n\n\n// // 实例化 get_pipeline_mulwidth 模块\n// get_pipeline_mulwidth #(\n// .N(4), // 设置流水线深度为 4\n// .WIDTH(8) // 设置信号宽度为 8 位\n// ) pipeline_inst (\n// .clk(clk), // 连接时钟信号\n// .rst_n(rst_n), // 连接复位信号\n// .signal(input_signal), // 连接输入信号\n// .pipeline_signal(output_signal) // 连接输出信号\n// );\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/get_pipline_mulwidth.v", "module get_pipeline_mulwidth #(\n parameter N = 4,\n parameter WIDTH = 8 \n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] signal,\n output wire [WIDTH-1:0] pipeline_signal\n);\n\n\n reg [WIDTH-1:0] pipeline_regs [N-1:0];\n\n\n genvar i;\n generate\n for (i = 0; i < N; i = i + 1) begin : pipeline_stage\n always @(posedge clk) begin\n if(~rst_n) \n pipeline_regs[i] <= 0;\n else begin\n if (i == 0) begin\n pipeline_regs[i] <= signal; \n end else begin\n pipeline_regs[i] <= pipeline_regs[i-1]; \n end\n end\n end\n end\n endgenerate\n\n\n assign pipeline_signal = pipeline_regs[N-1];\n\nendmodule\n\n\n// // 实例化 get_pipeline_mulwidth 模块\n// get_pipeline_mulwidth #(\n// .N(4), // 设置流水线深度为 4\n// .WIDTH(8) // 设置信号宽度为 8 位\n// ) pipeline_inst (\n// .clk(clk), // 连接时钟信号\n// .rst_n(rst_n), // 连接复位信号\n// .signal(input_signal), // 连接输入信号\n// .pipeline_signal(output_signal) // 连接输出信号\n// );\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/get_pipline_mulwidth.v", "module get_pipeline_mulwidth #(\n parameter N = 4,\n parameter WIDTH = 8 \n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] signal,\n output wire [WIDTH-1:0] pipeline_signal\n);\n\n\n reg [WIDTH-1:0] pipeline_regs [N-1:0];\n\n\n genvar i;\n generate\n for (i = 0; i < N; i = i + 1) begin : pipeline_stage\n always @(posedge clk) begin\n if(~rst_n) \n pipeline_regs[i] <= 0;\n else begin\n if (i == 0) begin\n pipeline_regs[i] <= signal; \n end else begin\n pipeline_regs[i] <= pipeline_regs[i-1]; \n end\n end\n end\n end\n endgenerate\n\n\n assign pipeline_signal = pipeline_regs[N-1];\n\nendmodule\n\n\n// // 实例化 get_pipeline_mulwidth 模块\n// get_pipeline_mulwidth #(\n// .N(4), // 设置流水线深度为 4\n// .WIDTH(8) // 设置信号宽度为 8 位\n// ) pipeline_inst (\n// .clk(clk), // 连接时钟信号\n// .rst_n(rst_n), // 连接复位信号\n// .signal(input_signal), // 连接输入信���\n// .pipeline_signal(output_signal) // 连接输出信号\n// );\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_mac_based/get_pipline_mulwidth.v", "module get_pipeline_mulwidth #(\n parameter N = 4,\n parameter WIDTH = 8 \n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] signal,\n output wire [WIDTH-1:0] pipeline_signal\n);\n\n\n reg [WIDTH-1:0] pipeline_regs [N-1:0];\n\n\n genvar i;\n generate\n for (i = 0; i < N; i = i + 1) begin : pipeline_stage\n always @(posedge clk) begin\n if(~rst_n) \n pipeline_regs[i] <= 0;\n else begin\n if (i == 0) begin\n pipeline_regs[i] <= signal; \n end else begin\n pipeline_regs[i] <= pipeline_regs[i-1]; \n end\n end\n end\n end\n endgenerate\n\n\n assign pipeline_signal = pipeline_regs[N-1];\n\nendmodule\n\n\n// // 实例化 get_pipeline_mulwidth 模块\n// get_pipeline_mulwidth #(\n// .N(4), // 设置流水线深度为 4\n// .WIDTH(8) // 设置信号宽度为 8 位\n// ) pipeline_inst (\n// .clk(clk), // 连接时钟信号\n// .rst_n(rst_n), // 连接复位信号\n// .signal(input_signal), // 连接输入信号\n// .pipeline_signal(output_signal) // 连接输出信号\n// );\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/get_pipline_mulwidth.v", "module get_pipeline_mulwidth #(\n parameter N = 4,\n parameter WIDTH = 8 \n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] signal,\n output wire [WIDTH-1:0] pipeline_signal\n);\n\n\n reg [WIDTH-1:0] pipeline_regs [N-1:0];\n\n\n genvar i;\n generate\n for (i = 0; i < N; i = i + 1) begin : pipeline_stage\n always @(posedge clk) begin\n if(~rst_n) \n pipeline_regs[i] <= 0;\n else begin\n if (i == 0) begin\n pipeline_regs[i] <= signal; \n end else begin\n pipeline_regs[i] <= pipeline_regs[i-1]; \n end\n end\n end\n end\n endgenerate\n\n\n assign pipeline_signal = pipeline_regs[N-1];\n\nendmodule\n\n\n// // 实例化 get_pipeline_mulwidth 模块\n// get_pipeline_mulwidth #(\n// .N(4), // 设置流水线深度为 4\n// .WIDTH(8) // 设置信号宽度为 8 位\n// ) pipeline_inst (\n// .clk(clk), // 连接时钟信号\n// .rst_n(rst_n), // 连接复位信号\n// .signal(input_signal), // 连接输入信号\n// .pipeline_signal(output_signal) // 连接输出信号\n// );\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_mac_based/get_pipline_mulwidth.v", "module get_pipeline_mulwidth #(\n parameter N = 4,\n parameter WIDTH = 8 \n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] signal,\n output wire [WIDTH-1:0] pipeline_signal\n);\n\n\n reg [WIDTH-1:0] pipeline_regs [N-1:0];\n\n\n genvar i;\n generate\n for (i = 0; i < N; i = i + 1) begin : pipeline_stage\n always @(posedge clk) begin\n if(~rst_n) \n pipeline_regs[i] <= 0;\n else begin\n if (i == 0) begin\n pipeline_regs[i] <= signal; \n end else begin\n pipeline_regs[i] <= pipeline_regs[i-1]; \n end\n end\n end\n end\n endgenerate\n\n\n assign pipeline_signal = pipeline_regs[N-1];\n\nendmodule\n\n\n// // 实例化 get_pipeline_mulwidth 模块\n// get_pipeline_mulwidth #(\n// .N(4), // 设置流水线深度为 4\n// .WIDTH(8) // 设置信号宽度为 8 位\n// ) pipeline_inst (\n// .clk(clk), // 连接时钟信号\n// .rst_n(rst_n), // 连接复位信号\n// .signal(input_signal), // 连接输入信号\n// .pipeline_signal(output_signal) // 连接输出信号\n// );\n"], ["/High-Performance-Tensor-Processing-Engines/OPT3_OPT4C/pe/DW02_tree.sv", "//-----------------------------------------------------------------------------------\n//\n// ABSTRACT: Wallace Tree Summer with Carry Save output\n//\n//------------------------------------------------------------------------------\n//\n\n // synopsys translate_off\n// `ifdef VCS\n// `include \"DW02_tree.v\"\n// `else\n // synopsys translate_on\n\nmodule DW02_tree( INPUT, OUT0, OUT1 );\n\n// parameters\nparameter integer num_inputs = 8;\nparameter integer input_width = 8;\nparameter integer verif_en = 1;\n\n//-----------------------------------------------------------------------------\n// ports\ninput [num_inputs*input_width-1 : 0]\tINPUT;\noutput [input_width-1:0]\t\tOUT0, OUT1;\n\n//-----------------------------------------------------------------------------\n// synopsys translate_off\nreg [input_width-1:0]\t\tOII0OOOI, O001l0I0;\n\n//-----------------------------------------------------------------------------\n \n \n// initial begin : parameter_check\n// integer param_err_flg;\n\n// param_err_flg = 0;\n \n \n// if (num_inputs < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter num_inputs (lower bound: 1)\",\n// \tnum_inputs );\n// end\n \n// if (input_width < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter input_width (lower bound: 1)\",\n// \tinput_width );\n// end\n \n// if ( (verif_en < 0) || (verif_en > 1) ) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter verif_en (legal range: 0 to 1)\",\n// \tverif_en );\n// end\n \n// if ( param_err_flg == 1) begin\n// $display(\n// \"%m :\\n Simulation aborted due to invalid parameter value(s)\");\n// $finish;\n// end\n\n// end // parameter_check \n\n\n// `ifndef DW_SUPPRESS_WARN\n// initial begin : verif_en_warning\n// $display(\"The parameter verif_en is set to 0 for this simulator.\\nOther values for verif_en are enabled only for VCS.\");\n// end // verif_en_warning\n// `endif\n\n//-----------------------------------------------------------------------------\n\n\n\nalways @ (INPUT) begin : IIIIO1Ol\n reg [input_width-1 : 0] I0lII01I [0 : num_inputs-1];\n reg [input_width-1 : 0] l10III00 [0 : num_inputs-1];\n reg [input_width-1 : 0] IIIO00Ol, lI0OII0O;\n integer I1I1O00I, O1OIIOII, IlI01lIO;\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII=O1OIIOII+1) begin\n for (IlI01lIO=0 ; IlI01lIO < input_width ; IlI01lIO=IlI01lIO+1) begin\n IIIO00Ol[IlI01lIO] = INPUT[O1OIIOII*input_width+IlI01lIO];\n end // for IlI01lIO\n I0lII01I[O1OIIOII] = IIIO00Ol;\n end // for O1OIIOII\n\n I1I1O00I = num_inputs;\n\n while (I1I1O00I > 2)\n begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I/3) ; O1OIIOII = O1OIIOII+1) begin\n l10III00[O1OIIOII*2] = I0lII01I[O1OIIOII*3] ^ I0lII01I[O1OIIOII*3+1] ^ I0lII01I[O1OIIOII*3+2];\n\n lI0OII0O = (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+1]) |\n (I0lII01I[O1OIIOII*3+1] & I0lII01I[O1OIIOII*3+2]) |\n (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+2]);\n\n l10III00[O1OIIOII*2+1] = lI0OII0O << 1;\n end\n if ((I1I1O00I % 3) > 0) begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I % 3) ; O1OIIOII = O1OIIOII + 1)\n l10III00[2 * (I1I1O00I/3) + O1OIIOII] = I0lII01I[3 * (I1I1O00I/3) + O1OIIOII];\n end\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII = O1OIIOII + 1)\n I0lII01I[O1OIIOII] = l10III00[O1OIIOII];\n I1I1O00I = I1I1O00I - (I1I1O00I/3);\n end\n OII0OOOI = I0lII01I[0];\n if (I1I1O00I > 1)\n O001l0I0 = I0lII01I[1];\n else\n O001l0I0 = {input_width{1'b0}};\nend // IIIIO1Ol\n\n\nassign OUT0 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : OII0OOOI;\nassign OUT1 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : O001l0I0;\n\n// synopsys translate_on\n\nendmodule\n // synopsys translate_off\n// `endif\n // synopsys translate_on\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/DW02_tree.sv", "//-----------------------------------------------------------------------------------\n//\n// ABSTRACT: Wallace Tree Summer with Carry Save output\n//\n//------------------------------------------------------------------------------\n//\n\n // synopsys translate_off\n// `ifdef VCS\n// `include \"DW02_tree.v\"\n// `else\n // synopsys translate_on\n\nmodule DW02_tree( INPUT, OUT0, OUT1 );\n\n// parameters\nparameter integer num_inputs = 8;\nparameter integer input_width = 8;\nparameter integer verif_en = 1;\n\n//-----------------------------------------------------------------------------\n// ports\ninput [num_inputs*input_width-1 : 0]\tINPUT;\noutput [input_width-1:0]\t\tOUT0, OUT1;\n\n//-----------------------------------------------------------------------------\n// synopsys translate_off\nreg [input_width-1:0]\t\tOII0OOOI, O001l0I0;\n\n//-----------------------------------------------------------------------------\n \n \n// initial begin : parameter_check\n// integer param_err_flg;\n\n// param_err_flg = 0;\n \n \n// if (num_inputs < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter num_inputs (lower bound: 1)\",\n// \tnum_inputs );\n// end\n \n// if (input_width < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter input_width (lower bound: 1)\",\n// \tinput_width );\n// end\n \n// if ( (verif_en < 0) || (verif_en > 1) ) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter verif_en (legal range: 0 to 1)\",\n// \tverif_en );\n// end\n \n// if ( param_err_flg == 1) begin\n// $display(\n// \"%m :\\n Simulation aborted due to invalid parameter value(s)\");\n// $finish;\n// end\n\n// end // parameter_check \n\n\n// `ifndef DW_SUPPRESS_WARN\n// initial begin : verif_en_warning\n// $display(\"The parameter verif_en is set to 0 for this simulator.\\nOther values for verif_en are enabled only for VCS.\");\n// end // verif_en_warning\n// `endif\n\n//-----------------------------------------------------------------------------\n\n\n\nalways @ (INPUT) begin : IIIIO1Ol\n reg [input_width-1 : 0] I0lII01I [0 : num_inputs-1];\n reg [input_width-1 : 0] l10III00 [0 : num_inputs-1];\n reg [input_width-1 : 0] IIIO00Ol, lI0OII0O;\n integer I1I1O00I, O1OIIOII, IlI01lIO;\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII=O1OIIOII+1) begin\n for (IlI01lIO=0 ; IlI01lIO < input_width ; IlI01lIO=IlI01lIO+1) begin\n IIIO00Ol[IlI01lIO] = INPUT[O1OIIOII*input_width+IlI01lIO];\n end // for IlI01lIO\n I0lII01I[O1OIIOII] = IIIO00Ol;\n end // for O1OIIOII\n\n I1I1O00I = num_inputs;\n\n while (I1I1O00I > 2)\n begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I/3) ; O1OIIOII = O1OIIOII+1) begin\n l10III00[O1OIIOII*2] = I0lII01I[O1OIIOII*3] ^ I0lII01I[O1OIIOII*3+1] ^ I0lII01I[O1OIIOII*3+2];\n\n lI0OII0O = (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+1]) |\n (I0lII01I[O1OIIOII*3+1] & I0lII01I[O1OIIOII*3+2]) |\n (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+2]);\n\n l10III00[O1OIIOII*2+1] = lI0OII0O << 1;\n end\n if ((I1I1O00I % 3) > 0) begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I % 3) ; O1OIIOII = O1OIIOII + 1)\n l10III00[2 * (I1I1O00I/3) + O1OIIOII] = I0lII01I[3 * (I1I1O00I/3) + O1OIIOII];\n end\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII = O1OIIOII + 1)\n I0lII01I[O1OIIOII] = l10III00[O1OIIOII];\n I1I1O00I = I1I1O00I - (I1I1O00I/3);\n end\n OII0OOOI = I0lII01I[0];\n if (I1I1O00I > 1)\n O001l0I0 = I0lII01I[1];\n else\n O001l0I0 = {input_width{1'b0}};\nend // IIIIO1Ol\n\n\nassign OUT0 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : OII0OOOI;\nassign OUT1 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : O001l0I0;\n\n// synopsys translate_on\n\nendmodule\n // synopsys translate_off\n// `endif\n // synopsys translate_on\n"], ["/High-Performance-Tensor-Processing-Engines/OPT2/DW02_tree.sv", "//-----------------------------------------------------------------------------------\n//\n// ABSTRACT: Wallace Tree Summer with Carry Save output\n//\n//------------------------------------------------------------------------------\n//\n\n // synopsys translate_off\n// `ifdef VCS\n// `include \"DW02_tree.v\"\n// `else\n // synopsys translate_on\n\nmodule DW02_tree( INPUT, OUT0, OUT1 );\n\n// parameters\nparameter integer num_inputs = 8;\nparameter integer input_width = 8;\nparameter integer verif_en = 1;\n\n//-----------------------------------------------------------------------------\n// ports\ninput [num_inputs*input_width-1 : 0]\tINPUT;\noutput [input_width-1:0]\t\tOUT0, OUT1;\n\n//-----------------------------------------------------------------------------\n// synopsys translate_off\nreg [input_width-1:0]\t\tOII0OOOI, O001l0I0;\n\n//-----------------------------------------------------------------------------\n \n \n// initial begin : parameter_check\n// integer param_err_flg;\n\n// param_err_flg = 0;\n \n \n// if (num_inputs < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter num_inputs (lower bound: 1)\",\n// \tnum_inputs );\n// end\n \n// if (input_width < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter input_width (lower bound: 1)\",\n// \tinput_width );\n// end\n \n// if ( (verif_en < 0) || (verif_en > 1) ) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter verif_en (legal range: 0 to 1)\",\n// \tverif_en );\n// end\n \n// if ( param_err_flg == 1) begin\n// $display(\n// \"%m :\\n Simulation aborted due to invalid parameter value(s)\");\n// $finish;\n// end\n\n// end // parameter_check \n\n\n// `ifndef DW_SUPPRESS_WARN\n// initial begin : verif_en_warning\n// $display(\"The parameter verif_en is set to 0 for this simulator.\\nOther values for verif_en are enabled only for VCS.\");\n// end // verif_en_warning\n// `endif\n\n//-----------------------------------------------------------------------------\n\n\n\nalways @ (INPUT) begin : IIIIO1Ol\n reg [input_width-1 : 0] I0lII01I [0 : num_inputs-1];\n reg [input_width-1 : 0] l10III00 [0 : num_inputs-1];\n reg [input_width-1 : 0] IIIO00Ol, lI0OII0O;\n integer I1I1O00I, O1OIIOII, IlI01lIO;\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII=O1OIIOII+1) begin\n for (IlI01lIO=0 ; IlI01lIO < input_width ; IlI01lIO=IlI01lIO+1) begin\n IIIO00Ol[IlI01lIO] = INPUT[O1OIIOII*input_width+IlI01lIO];\n end // for IlI01lIO\n I0lII01I[O1OIIOII] = IIIO00Ol;\n end // for O1OIIOII\n\n I1I1O00I = num_inputs;\n\n while (I1I1O00I > 2)\n begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I/3) ; O1OIIOII = O1OIIOII+1) begin\n l10III00[O1OIIOII*2] = I0lII01I[O1OIIOII*3] ^ I0lII01I[O1OIIOII*3+1] ^ I0lII01I[O1OIIOII*3+2];\n\n lI0OII0O = (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+1]) |\n (I0lII01I[O1OIIOII*3+1] & I0lII01I[O1OIIOII*3+2]) |\n (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+2]);\n\n l10III00[O1OIIOII*2+1] = lI0OII0O << 1;\n end\n if ((I1I1O00I % 3) > 0) begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I % 3) ; O1OIIOII = O1OIIOII + 1)\n l10III00[2 * (I1I1O00I/3) + O1OIIOII] = I0lII01I[3 * (I1I1O00I/3) + O1OIIOII];\n end\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII = O1OIIOII + 1)\n I0lII01I[O1OIIOII] = l10III00[O1OIIOII];\n I1I1O00I = I1I1O00I - (I1I1O00I/3);\n end\n OII0OOOI = I0lII01I[0];\n if (I1I1O00I > 1)\n O001l0I0 = I0lII01I[1];\n else\n O001l0I0 = {input_width{1'b0}};\nend // IIIIO1Ol\n\n\nassign OUT0 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : OII0OOOI;\nassign OUT1 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : O001l0I0;\n\n// synopsys translate_on\n\nendmodule\n // synopsys translate_off\n// `endif\n // synopsys translate_on\n"], ["/High-Performance-Tensor-Processing-Engines/OPT2/get_pipline_mulwidth.v", "module get_pipeline_mulwidth #(\n parameter N = 4,\n parameter WIDTH = 8 \n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] signal,\n output wire [WIDTH-1:0] pipeline_signal\n);\n\n\nreg [WIDTH-1:0] pipeline_regs [N-1:0];\n\n\n genvar i;\n generate\n for (i = 0; i < N; i = i + 1) begin : pipeline_stage\n always @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n pipeline_regs[i] <= 0; \n end else begin\n if (i == 0) begin\n pipeline_regs[i] <= signal; \n end else begin\n pipeline_regs[i] <= pipeline_regs[i-1]; \n end\n end\n end\n end\n endgenerate\n\n\n assign pipeline_signal = pipeline_regs[N-1];\n\nendmodule\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT3_OPT4C/pe/get_pipline_mulwidth.v", "module get_pipeline_mulwidth #(\n parameter N = 4,\n parameter WIDTH = 8 \n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] signal,\n output wire [WIDTH-1:0] pipeline_signal\n);\n\n\nreg [WIDTH-1:0] pipeline_regs [N-1:0];\n\n\n genvar i;\n generate\n for (i = 0; i < N; i = i + 1) begin : pipeline_stage\n always @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n pipeline_regs[i] <= 0; \n end else begin\n if (i == 0) begin\n pipeline_regs[i] <= signal; \n end else begin\n pipeline_regs[i] <= pipeline_regs[i-1]; \n end\n end\n end\n end\n endgenerate\n\n\n assign pipeline_signal = pipeline_regs[N-1];\n\nendmodule\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT2/tree_full_sum.sv", "module tree_full_sum #(\n parameter K = 16,\n parameter WIDTH = 13\n)(\n input clk,\n input [K*WIDTH-1:0] csa_input,\n output reg signed [WIDTH-1:0] full_sum\n);\n\nwire signed [WIDTH-1:0] acc_sum;\nwire signed [WIDTH-1:0] acc_carry;\n\ngenvar i;\ngenerate\n if(K == 4) begin\n always @(posedge clk) begin\n full_sum <= $signed(csa_input[1*WIDTH-1:0*WIDTH]) + $signed(csa_input[2*WIDTH-1:1*WIDTH]) + $signed(csa_input[3*WIDTH-1:2*WIDTH]) + $signed(csa_input[4*WIDTH-1:3*WIDTH]);\n end\n end\n else begin\n DW02_tree #(K, WIDTH, 1)\n ins_tree ( .INPUT(csa_input), .OUT0(acc_sum), .OUT1(acc_carry));\n always @(posedge clk) begin\n full_sum <= $signed(acc_sum) + $signed(acc_carry);\n end\n end\nendgenerate\n\n\n\n\nendmodule\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT2/top_tpe.sv", "module top_tpe #(\n parameter N = 32,\n localparam RESULT_WIDTH = 20\n)(\n \n input clk,\n input [127:0] operand_a,\n input weight_wen,\n input [8*N-1:0] weight_din,\n output [RESULT_WIDTH*N-1:0] result\n\n);\n\nwire [3:0] bit_enable [0:15];\nwire [7:0] partial_product_select [0:15];\nwire [3:0] bit_enable_pip [0:N-1][0:15];\nwire [7:0] partial_product_select_pip [0:N-1][0:15];\n\nvector_encoder encoder(\n .clk(clk),\n .operand_a(operand_a),\n .bit_enable(bit_enable),\n .partial_product_select(partial_product_select)\n);\n\ngenvar i;\ngenerate \n for (i = 0 ; i < N ; i = i + 1) begin\n if(i == 0) begin\n top_pe_tile pe_tile(\n .clk(clk),\n .weight_wen(weight_wen),\n .weight_din(weight_din[8*(i+1)-1:8*i]),\n .bit_enable(bit_enable),\n .partial_product_select(partial_product_select),\n .result(result[RESULT_WIDTH*(i+1)-1:RESULT_WIDTH*i]),\n .bit_enable_pip(bit_enable_pip[i]),\n .partial_product_select_pip(partial_product_select_pip[i])\n );\n end\n else begin\n top_pe_tile pe_tile(\n .clk(clk),\n .weight_wen(weight_wen),\n .weight_din(weight_din[8*(i+1)-1:8*i]),\n .bit_enable(bit_enable_pip[i-1]),\n .partial_product_select(partial_product_select_pip[i-1]),\n .result(result[RESULT_WIDTH*(i+1)-1:RESULT_WIDTH*i]),\n .bit_enable_pip(bit_enable_pip[i]),\n .partial_product_select_pip(partial_product_select_pip[i])\n );\n end\n end\nendgenerate\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/dff_async.v", "module dff_async #(\n parameter WIDTH = 8\n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] d,\n output reg [WIDTH-1:0] q\n);\n\nalways @(posedge clk or negedge rst_n) begin\n if (!rst_n) begin\n q <= 0;\n end\n else begin\n q <= d;\n end\nend\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT2/weight_rf.sv", "module weight_rf (\n input clk,\n input wen,\n input [7:0] din,\n output [7:0] weight [0:15]\n);\n\nreg [7:0] buffer [0:15];\n\nassign weight = buffer;\n\ngenvar i;\ngenerate\n for (i = 0; i < 16; i = i + 1) begin\n always @(posedge clk) begin\n if(wen) begin\n if (i==15)\n buffer[i] <= din;\n else \n buffer[i] <= buffer[i+1];\n end\n else\n buffer[i] <= buffer[i];\n end\n end\nendgenerate\n\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT3_OPT4C/pe/get_negedge.sv", "module get_negedge(\n input clk,\n input signal,\n output negedge_signal\n );\n\nreg save;\n\nalways @(posedge clk) begin\n save <= signal;\nend\n\nassign negedge_signal = ~signal & save;\n\nendmodule\n\n// get_negedge get_hit(\n// .clk(clk),\n// .signal(cache_hit),\n// .negedge_signal(negedge_cache_hit)\n// );"]], "task_instance_info": {"created_time": "2025-08-21 04:17:40", "created_task_model": "DeepSeek-R1", "class_skeleton": "module inv_unit_nor_out (\n input wire a ,\n input wire b ,\n \n output wire xor_o , \n output wire nor_o \n ) ; endmodule", "code_description": "This code segment functions to: Generate dual logical operation results from two binary input signals, producing both an exclusive-OR combination and a joint negation of their inclusive disjunction."}, "inference_content": {"inference_model": "DeepSeek-R1", "inference_result": "```verilog\n[TASK_BEGIN]\nmodule inv_unit_nor_out (\n input wire a ,\n input wire b ,\n \n output wire xor_o , \n output wire nor_o \n) ;\n assign xor_o = a ^ b;\n assign nor_o = ~(a | b);\nendmodule\n[TASK_END]\n```", "inference_time": "2025-08-21 04-18-04"}, "editdistance_info": {"edit_distance": 41.4414, "calculate_time": "2025-08-21 04:18:04", "true_code_clean": "module inv_unit_nor_out(\n input wire a ,\n input wire b ,\n output wire xor_o , \n output wire nor_o \n );\n wire a_AND_b ; \n wire a_NOR_b ; \n assign a_AND_b = a & b;\n assign a_NOR_b = ~(a | b);\n assign xor_o = ~(a_AND_b | a_NOR_b);\n assign nor_o = a_NOR_b;\nendmodule", "predict_code_clean": "module inv_unit_nor_out (\n input wire a ,\n input wire b ,\n output wire xor_o , \n output wire nor_o \n) ;\n assign xor_o = a ^ b;\n assign nor_o = ~(a | b);\nendmodule"}} +{"repo_name": "High-Performance-Tensor-Processing-Engines", "file_name": "/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/DW02_tree.sv", "inference_info": {"prefix_code": "////////////////////////////////////////////////////////////////////////////////\n//\n// This confidential and proprietary software may be used only\n// as authorized by a licensing agreement from Synopsys Inc.\n// In the event of publication, the following notice is applicable:\n//\n// (C) COPYRIGHT 2000 - 2021 SYNOPSYS INC.\n// ALL RIGHTS RESERVED\n//\n// The entire notice above must be reproduced on all authorized\n// copies.\n//\n// AUTHOR: Rick Kelly 07/28/2000\n//\n// VERSION: Verilog Simulation Model for DW02_tree\n//\n// DesignWare_version: aacb4808\n// DesignWare_release: S-2021.06-DWBB_202106.4\n//\n////////////////////////////////////////////////////////////////////////////////\n\n//-----------------------------------------------------------------------------------\n//\n// ABSTRACT: Wallace Tree Summer with Carry Save output\n//\n// MODIFIED:\n// Aamir Farooqui 7/11/02\n// Corrected parameter checking, simplied sim model, and X_processing\n//\n//------------------------------------------------------------------------------\n//\n\n // synopsys translate_off\n// `ifdef VCS\n// `include \"DW02_tree.v\"\n// `else\n // synopsys translate_on\n\n", "suffix_code": "\n // synopsys translate_off\n// `endif\n // synopsys translate_on\n", "middle_code": "module DW02_tree( INPUT, OUT0, OUT1 );\nparameter integer num_inputs = 8;\nparameter integer input_width = 8;\nparameter integer verif_en = 1;\ninput [num_inputs*input_width-1 : 0]\tINPUT;\noutput [input_width-1:0]\t\tOUT0, OUT1;\nreg [input_width-1:0]\t\tOII0OOOI, O001l0I0;\nalways @ (INPUT) begin : IIIIO1Ol\n reg [input_width-1 : 0] I0lII01I [0 : num_inputs-1];\n reg [input_width-1 : 0] l10III00 [0 : num_inputs-1];\n reg [input_width-1 : 0] IIIO00Ol, lI0OII0O;\n integer I1I1O00I, O1OIIOII, IlI01lIO;\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII=O1OIIOII+1) begin\n for (IlI01lIO=0 ; IlI01lIO < input_width ; IlI01lIO=IlI01lIO+1) begin\n IIIO00Ol[IlI01lIO] = INPUT[O1OIIOII*input_width+IlI01lIO];\n end \n I0lII01I[O1OIIOII] = IIIO00Ol;\n end \n I1I1O00I = num_inputs;\n while (I1I1O00I > 2)\n begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I/3) ; O1OIIOII = O1OIIOII+1) begin\n l10III00[O1OIIOII*2] = I0lII01I[O1OIIOII*3] ^ I0lII01I[O1OIIOII*3+1] ^ I0lII01I[O1OIIOII*3+2];\n lI0OII0O = (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+1]) |\n (I0lII01I[O1OIIOII*3+1] & I0lII01I[O1OIIOII*3+2]) |\n (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+2]);\n l10III00[O1OIIOII*2+1] = lI0OII0O << 1;\n end\n if ((I1I1O00I % 3) > 0) begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I % 3) ; O1OIIOII = O1OIIOII + 1)\n l10III00[2 * (I1I1O00I/3) + O1OIIOII] = I0lII01I[3 * (I1I1O00I/3) + O1OIIOII];\n end\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII = O1OIIOII + 1)\n I0lII01I[O1OIIOII] = l10III00[O1OIIOII];\n I1I1O00I = I1I1O00I - (I1I1O00I/3);\n end\n OII0OOOI = I0lII01I[0];\n if (I1I1O00I > 1)\n O001l0I0 = I0lII01I[1];\n else\n O001l0I0 = {input_width{1'b0}};\nend \nassign OUT0 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : OII0OOOI;\nassign OUT1 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : O001l0I0;\nendmodule", "code_description": null, "fill_type": "CLASS_TYPE", "language_type": "verilog", "sub_task_type": null}, "context_code": [["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/DW02_tree.sv", "////////////////////////////////////////////////////////////////////////////////\n//\n// This confidential and proprietary software may be used only\n// as authorized by a licensing agreement from Synopsys Inc.\n// In the event of publication, the following notice is applicable:\n//\n// (C) COPYRIGHT 2000 - 2021 SYNOPSYS INC.\n// ALL RIGHTS RESERVED\n//\n// The entire notice above must be reproduced on all authorized\n// copies.\n//\n// AUTHOR: Rick Kelly 07/28/2000\n//\n// VERSION: Verilog Simulation Model for DW02_tree\n//\n// DesignWare_version: aacb4808\n// DesignWare_release: S-2021.06-DWBB_202106.4\n//\n////////////////////////////////////////////////////////////////////////////////\n\n//-----------------------------------------------------------------------------------\n//\n// ABSTRACT: Wallace Tree Summer with Carry Save output\n//\n// MODIFIED:\n// Aamir Farooqui 7/11/02\n// Corrected parameter checking, simplied sim model, and X_processing\n//\n//------------------------------------------------------------------------------\n//\n\n // synopsys translate_off\n// `ifdef VCS\n// `include \"DW02_tree.v\"\n// `else\n // synopsys translate_on\n\nmodule DW02_tree( INPUT, OUT0, OUT1 );\n\n// parameters\nparameter integer num_inputs = 8;\nparameter integer input_width = 8;\nparameter integer verif_en = 1;\n\n//-----------------------------------------------------------------------------\n// ports\ninput [num_inputs*input_width-1 : 0]\tINPUT;\noutput [input_width-1:0]\t\tOUT0, OUT1;\n\n//-----------------------------------------------------------------------------\n// synopsys translate_off\nreg [input_width-1:0]\t\tOII0OOOI, O001l0I0;\n\n//-----------------------------------------------------------------------------\n \n \n// initial begin : parameter_check\n// integer param_err_flg;\n\n// param_err_flg = 0;\n \n \n// if (num_inputs < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter num_inputs (lower bound: 1)\",\n// \tnum_inputs );\n// end\n \n// if (input_width < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter input_width (lower bound: 1)\",\n// \tinput_width );\n// end\n \n// if ( (verif_en < 0) || (verif_en > 1) ) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter verif_en (legal range: 0 to 1)\",\n// \tverif_en );\n// end\n \n// if ( param_err_flg == 1) begin\n// $display(\n// \"%m :\\n Simulation aborted due to invalid parameter value(s)\");\n// $finish;\n// end\n\n// end // parameter_check \n\n\n// `ifndef DW_SUPPRESS_WARN\n// initial begin : verif_en_warning\n// $display(\"The parameter verif_en is set to 0 for this simulator.\\nOther values for verif_en are enabled only for VCS.\");\n// end // verif_en_warning\n// `endif\n\n//-----------------------------------------------------------------------------\n\n\n\nalways @ (INPUT) begin : IIIIO1Ol\n reg [input_width-1 : 0] I0lII01I [0 : num_inputs-1];\n reg [input_width-1 : 0] l10III00 [0 : num_inputs-1];\n reg [input_width-1 : 0] IIIO00Ol, lI0OII0O;\n integer I1I1O00I, O1OIIOII, IlI01lIO;\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII=O1OIIOII+1) begin\n for (IlI01lIO=0 ; IlI01lIO < input_width ; IlI01lIO=IlI01lIO+1) begin\n IIIO00Ol[IlI01lIO] = INPUT[O1OIIOII*input_width+IlI01lIO];\n end // for IlI01lIO\n I0lII01I[O1OIIOII] = IIIO00Ol;\n end // for O1OIIOII\n\n I1I1O00I = num_inputs;\n\n while (I1I1O00I > 2)\n begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I/3) ; O1OIIOII = O1OIIOII+1) begin\n l10III00[O1OIIOII*2] = I0lII01I[O1OIIOII*3] ^ I0lII01I[O1OIIOII*3+1] ^ I0lII01I[O1OIIOII*3+2];\n\n lI0OII0O = (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+1]) |\n (I0lII01I[O1OIIOII*3+1] & I0lII01I[O1OIIOII*3+2]) |\n (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+2]);\n\n l10III00[O1OIIOII*2+1] = lI0OII0O << 1;\n end\n if ((I1I1O00I % 3) > 0) begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I % 3) ; O1OIIOII = O1OIIOII + 1)\n l10III00[2 * (I1I1O00I/3) + O1OIIOII] = I0lII01I[3 * (I1I1O00I/3) + O1OIIOII];\n end\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII = O1OIIOII + 1)\n I0lII01I[O1OIIOII] = l10III00[O1OIIOII];\n I1I1O00I = I1I1O00I - (I1I1O00I/3);\n end\n OII0OOOI = I0lII01I[0];\n if (I1I1O00I > 1)\n O001l0I0 = I0lII01I[1];\n else\n O001l0I0 = {input_width{1'b0}};\nend // IIIIO1Ol\n\n\nassign OUT0 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : OII0OOOI;\nassign OUT1 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : O001l0I0;\n\n// synopsys translate_on\n\nendmodule\n // synopsys translate_off\n// `endif\n // synopsys translate_on\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/DW02_tree.sv", "////////////////////////////////////////////////////////////////////////////////\n//\n// This confidential and proprietary software may be used only\n// as authorized by a licensing agreement from Synopsys Inc.\n// In the event of publication, the following notice is applicable:\n//\n// (C) COPYRIGHT 2000 - 2021 SYNOPSYS INC.\n// ALL RIGHTS RESERVED\n//\n// The entire notice above must be reproduced on all authorized\n// copies.\n//\n// AUTHOR: Rick Kelly 07/28/2000\n//\n// VERSION: Verilog Simulation Model for DW02_tree\n//\n// DesignWare_version: aacb4808\n// DesignWare_release: S-2021.06-DWBB_202106.4\n//\n////////////////////////////////////////////////////////////////////////////////\n\n//-----------------------------------------------------------------------------------\n//\n// ABSTRACT: Wallace Tree Summer with Carry Save output\n//\n// MODIFIED:\n// Aamir Farooqui 7/11/02\n// Corrected parameter checking, simplied sim model, and X_processing\n//\n//------------------------------------------------------------------------------\n//\n\n // synopsys translate_off\n// `ifdef VCS\n// `include \"DW02_tree.v\"\n// `else\n // synopsys translate_on\n\nmodule DW02_tree( INPUT, OUT0, OUT1 );\n\n// parameters\nparameter integer num_inputs = 8;\nparameter integer input_width = 8;\nparameter integer verif_en = 1;\n\n//-----------------------------------------------------------------------------\n// ports\ninput [num_inputs*input_width-1 : 0]\tINPUT;\noutput [input_width-1:0]\t\tOUT0, OUT1;\n\n//-----------------------------------------------------------------------------\n// synopsys translate_off\nreg [input_width-1:0]\t\tOII0OOOI, O001l0I0;\n\n//-----------------------------------------------------------------------------\n \n \n// initial begin : parameter_check\n// integer param_err_flg;\n\n// param_err_flg = 0;\n \n \n// if (num_inputs < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter num_inputs (lower bound: 1)\",\n// \tnum_inputs );\n// end\n \n// if (input_width < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter input_width (lower bound: 1)\",\n// \tinput_width );\n// end\n \n// if ( (verif_en < 0) || (verif_en > 1) ) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter verif_en (legal range: 0 to 1)\",\n// \tverif_en );\n// end\n \n// if ( param_err_flg == 1) begin\n// $display(\n// \"%m :\\n Simulation aborted due to invalid parameter value(s)\");\n// $finish;\n// end\n\n// end // parameter_check \n\n\n// `ifndef DW_SUPPRESS_WARN\n// initial begin : verif_en_warning\n// $display(\"The parameter verif_en is set to 0 for this simulator.\\nOther values for verif_en are enabled only for VCS.\");\n// end // verif_en_warning\n// `endif\n\n//-----------------------------------------------------------------------------\n\n\n\nalways @ (INPUT) begin : IIIIO1Ol\n reg [input_width-1 : 0] I0lII01I [0 : num_inputs-1];\n reg [input_width-1 : 0] l10III00 [0 : num_inputs-1];\n reg [input_width-1 : 0] IIIO00Ol, lI0OII0O;\n integer I1I1O00I, O1OIIOII, IlI01lIO;\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII=O1OIIOII+1) begin\n for (IlI01lIO=0 ; IlI01lIO < input_width ; IlI01lIO=IlI01lIO+1) begin\n IIIO00Ol[IlI01lIO] = INPUT[O1OIIOII*input_width+IlI01lIO];\n end // for IlI01lIO\n I0lII01I[O1OIIOII] = IIIO00Ol;\n end // for O1OIIOII\n\n I1I1O00I = num_inputs;\n\n while (I1I1O00I > 2)\n begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I/3) ; O1OIIOII = O1OIIOII+1) begin\n l10III00[O1OIIOII*2] = I0lII01I[O1OIIOII*3] ^ I0lII01I[O1OIIOII*3+1] ^ I0lII01I[O1OIIOII*3+2];\n\n lI0OII0O = (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+1]) |\n (I0lII01I[O1OIIOII*3+1] & I0lII01I[O1OIIOII*3+2]) |\n (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+2]);\n\n l10III00[O1OIIOII*2+1] = lI0OII0O << 1;\n end\n if ((I1I1O00I % 3) > 0) begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I % 3) ; O1OIIOII = O1OIIOII + 1)\n l10III00[2 * (I1I1O00I/3) + O1OIIOII] = I0lII01I[3 * (I1I1O00I/3) + O1OIIOII];\n end\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII = O1OIIOII + 1)\n I0lII01I[O1OIIOII] = l10III00[O1OIIOII];\n I1I1O00I = I1I1O00I - (I1I1O00I/3);\n end\n OII0OOOI = I0lII01I[0];\n if (I1I1O00I > 1)\n O001l0I0 = I0lII01I[1];\n else\n O001l0I0 = {input_width{1'b0}};\nend // IIIIO1Ol\n\n\nassign OUT0 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : OII0OOOI;\nassign OUT1 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : O001l0I0;\n\n// synopsys translate_on\n\nendmodule\n // synopsys translate_off\n// `endif\n // synopsys translate_on\n"], ["/High-Performance-Tensor-Processing-Engines/OPT3_OPT4C/pe/DW02_tree.sv", "//-----------------------------------------------------------------------------------\n//\n// ABSTRACT: Wallace Tree Summer with Carry Save output\n//\n//------------------------------------------------------------------------------\n//\n\n // synopsys translate_off\n// `ifdef VCS\n// `include \"DW02_tree.v\"\n// `else\n // synopsys translate_on\n\nmodule DW02_tree( INPUT, OUT0, OUT1 );\n\n// parameters\nparameter integer num_inputs = 8;\nparameter integer input_width = 8;\nparameter integer verif_en = 1;\n\n//-----------------------------------------------------------------------------\n// ports\ninput [num_inputs*input_width-1 : 0]\tINPUT;\noutput [input_width-1:0]\t\tOUT0, OUT1;\n\n//-----------------------------------------------------------------------------\n// synopsys translate_off\nreg [input_width-1:0]\t\tOII0OOOI, O001l0I0;\n\n//-----------------------------------------------------------------------------\n \n \n// initial begin : parameter_check\n// integer param_err_flg;\n\n// param_err_flg = 0;\n \n \n// if (num_inputs < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter num_inputs (lower bound: 1)\",\n// \tnum_inputs );\n// end\n \n// if (input_width < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter input_width (lower bound: 1)\",\n// \tinput_width );\n// end\n \n// if ( (verif_en < 0) || (verif_en > 1) ) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter verif_en (legal range: 0 to 1)\",\n// \tverif_en );\n// end\n \n// if ( param_err_flg == 1) begin\n// $display(\n// \"%m :\\n Simulation aborted due to invalid parameter value(s)\");\n// $finish;\n// end\n\n// end // parameter_check \n\n\n// `ifndef DW_SUPPRESS_WARN\n// initial begin : verif_en_warning\n// $display(\"The parameter verif_en is set to 0 for this simulator.\\nOther values for verif_en are enabled only for VCS.\");\n// end // verif_en_warning\n// `endif\n\n//-----------------------------------------------------------------------------\n\n\n\nalways @ (INPUT) begin : IIIIO1Ol\n reg [input_width-1 : 0] I0lII01I [0 : num_inputs-1];\n reg [input_width-1 : 0] l10III00 [0 : num_inputs-1];\n reg [input_width-1 : 0] IIIO00Ol, lI0OII0O;\n integer I1I1O00I, O1OIIOII, IlI01lIO;\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII=O1OIIOII+1) begin\n for (IlI01lIO=0 ; IlI01lIO < input_width ; IlI01lIO=IlI01lIO+1) begin\n IIIO00Ol[IlI01lIO] = INPUT[O1OIIOII*input_width+IlI01lIO];\n end // for IlI01lIO\n I0lII01I[O1OIIOII] = IIIO00Ol;\n end // for O1OIIOII\n\n I1I1O00I = num_inputs;\n\n while (I1I1O00I > 2)\n begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I/3) ; O1OIIOII = O1OIIOII+1) begin\n l10III00[O1OIIOII*2] = I0lII01I[O1OIIOII*3] ^ I0lII01I[O1OIIOII*3+1] ^ I0lII01I[O1OIIOII*3+2];\n\n lI0OII0O = (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+1]) |\n (I0lII01I[O1OIIOII*3+1] & I0lII01I[O1OIIOII*3+2]) |\n (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+2]);\n\n l10III00[O1OIIOII*2+1] = lI0OII0O << 1;\n end\n if ((I1I1O00I % 3) > 0) begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I % 3) ; O1OIIOII = O1OIIOII + 1)\n l10III00[2 * (I1I1O00I/3) + O1OIIOII] = I0lII01I[3 * (I1I1O00I/3) + O1OIIOII];\n end\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII = O1OIIOII + 1)\n I0lII01I[O1OIIOII] = l10III00[O1OIIOII];\n I1I1O00I = I1I1O00I - (I1I1O00I/3);\n end\n OII0OOOI = I0lII01I[0];\n if (I1I1O00I > 1)\n O001l0I0 = I0lII01I[1];\n else\n O001l0I0 = {input_width{1'b0}};\nend // IIIIO1Ol\n\n\nassign OUT0 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : OII0OOOI;\nassign OUT1 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : O001l0I0;\n\n// synopsys translate_on\n\nendmodule\n // synopsys translate_off\n// `endif\n // synopsys translate_on\n"], ["/High-Performance-Tensor-Processing-Engines/OPT2/DW02_tree.sv", "//-----------------------------------------------------------------------------------\n//\n// ABSTRACT: Wallace Tree Summer with Carry Save output\n//\n//------------------------------------------------------------------------------\n//\n\n // synopsys translate_off\n// `ifdef VCS\n// `include \"DW02_tree.v\"\n// `else\n // synopsys translate_on\n\nmodule DW02_tree( INPUT, OUT0, OUT1 );\n\n// parameters\nparameter integer num_inputs = 8;\nparameter integer input_width = 8;\nparameter integer verif_en = 1;\n\n//-----------------------------------------------------------------------------\n// ports\ninput [num_inputs*input_width-1 : 0]\tINPUT;\noutput [input_width-1:0]\t\tOUT0, OUT1;\n\n//-----------------------------------------------------------------------------\n// synopsys translate_off\nreg [input_width-1:0]\t\tOII0OOOI, O001l0I0;\n\n//-----------------------------------------------------------------------------\n \n \n// initial begin : parameter_check\n// integer param_err_flg;\n\n// param_err_flg = 0;\n \n \n// if (num_inputs < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter num_inputs (lower bound: 1)\",\n// \tnum_inputs );\n// end\n \n// if (input_width < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter input_width (lower bound: 1)\",\n// \tinput_width );\n// end\n \n// if ( (verif_en < 0) || (verif_en > 1) ) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter verif_en (legal range: 0 to 1)\",\n// \tverif_en );\n// end\n \n// if ( param_err_flg == 1) begin\n// $display(\n// \"%m :\\n Simulation aborted due to invalid parameter value(s)\");\n// $finish;\n// end\n\n// end // parameter_check \n\n\n// `ifndef DW_SUPPRESS_WARN\n// initial begin : verif_en_warning\n// $display(\"The parameter verif_en is set to 0 for this simulator.\\nOther values for verif_en are enabled only for VCS.\");\n// end // verif_en_warning\n// `endif\n\n//-----------------------------------------------------------------------------\n\n\n\nalways @ (INPUT) begin : IIIIO1Ol\n reg [input_width-1 : 0] I0lII01I [0 : num_inputs-1];\n reg [input_width-1 : 0] l10III00 [0 : num_inputs-1];\n reg [input_width-1 : 0] IIIO00Ol, lI0OII0O;\n integer I1I1O00I, O1OIIOII, IlI01lIO;\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII=O1OIIOII+1) begin\n for (IlI01lIO=0 ; IlI01lIO < input_width ; IlI01lIO=IlI01lIO+1) begin\n IIIO00Ol[IlI01lIO] = INPUT[O1OIIOII*input_width+IlI01lIO];\n end // for IlI01lIO\n I0lII01I[O1OIIOII] = IIIO00Ol;\n end // for O1OIIOII\n\n I1I1O00I = num_inputs;\n\n while (I1I1O00I > 2)\n begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I/3) ; O1OIIOII = O1OIIOII+1) begin\n l10III00[O1OIIOII*2] = I0lII01I[O1OIIOII*3] ^ I0lII01I[O1OIIOII*3+1] ^ I0lII01I[O1OIIOII*3+2];\n\n lI0OII0O = (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+1]) |\n (I0lII01I[O1OIIOII*3+1] & I0lII01I[O1OIIOII*3+2]) |\n (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+2]);\n\n l10III00[O1OIIOII*2+1] = lI0OII0O << 1;\n end\n if ((I1I1O00I % 3) > 0) begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I % 3) ; O1OIIOII = O1OIIOII + 1)\n l10III00[2 * (I1I1O00I/3) + O1OIIOII] = I0lII01I[3 * (I1I1O00I/3) + O1OIIOII];\n end\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII = O1OIIOII + 1)\n I0lII01I[O1OIIOII] = l10III00[O1OIIOII];\n I1I1O00I = I1I1O00I - (I1I1O00I/3);\n end\n OII0OOOI = I0lII01I[0];\n if (I1I1O00I > 1)\n O001l0I0 = I0lII01I[1];\n else\n O001l0I0 = {input_width{1'b0}};\nend // IIIIO1Ol\n\n\nassign OUT0 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : OII0OOOI;\nassign OUT1 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : O001l0I0;\n\n// synopsys translate_on\n\nendmodule\n // synopsys translate_off\n// `endif\n // synopsys translate_on\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/DW02_tree.sv", "//-----------------------------------------------------------------------------------\n//\n// ABSTRACT: Wallace Tree Summer with Carry Save output\n//\n//------------------------------------------------------------------------------\n//\n\n // synopsys translate_off\n// `ifdef VCS\n// `include \"DW02_tree.v\"\n// `else\n // synopsys translate_on\n\nmodule DW02_tree( INPUT, OUT0, OUT1 );\n\n// parameters\nparameter integer num_inputs = 8;\nparameter integer input_width = 8;\nparameter integer verif_en = 1;\n\n//-----------------------------------------------------------------------------\n// ports\ninput [num_inputs*input_width-1 : 0]\tINPUT;\noutput [input_width-1:0]\t\tOUT0, OUT1;\n\n//-----------------------------------------------------------------------------\n// synopsys translate_off\nreg [input_width-1:0]\t\tOII0OOOI, O001l0I0;\n\n//-----------------------------------------------------------------------------\n \n \n// initial begin : parameter_check\n// integer param_err_flg;\n\n// param_err_flg = 0;\n \n \n// if (num_inputs < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter num_inputs (lower bound: 1)\",\n// \tnum_inputs );\n// end\n \n// if (input_width < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter input_width (lower bound: 1)\",\n// \tinput_width );\n// end\n \n// if ( (verif_en < 0) || (verif_en > 1) ) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter verif_en (legal range: 0 to 1)\",\n// \tverif_en );\n// end\n \n// if ( param_err_flg == 1) begin\n// $display(\n// \"%m :\\n Simulation aborted due to invalid parameter value(s)\");\n// $finish;\n// end\n\n// end // parameter_check \n\n\n// `ifndef DW_SUPPRESS_WARN\n// initial begin : verif_en_warning\n// $display(\"The parameter verif_en is set to 0 for this simulator.\\nOther values for verif_en are enabled only for VCS.\");\n// end // verif_en_warning\n// `endif\n\n//-----------------------------------------------------------------------------\n\n\n\nalways @ (INPUT) begin : IIIIO1Ol\n reg [input_width-1 : 0] I0lII01I [0 : num_inputs-1];\n reg [input_width-1 : 0] l10III00 [0 : num_inputs-1];\n reg [input_width-1 : 0] IIIO00Ol, lI0OII0O;\n integer I1I1O00I, O1OIIOII, IlI01lIO;\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII=O1OIIOII+1) begin\n for (IlI01lIO=0 ; IlI01lIO < input_width ; IlI01lIO=IlI01lIO+1) begin\n IIIO00Ol[IlI01lIO] = INPUT[O1OIIOII*input_width+IlI01lIO];\n end // for IlI01lIO\n I0lII01I[O1OIIOII] = IIIO00Ol;\n end // for O1OIIOII\n\n I1I1O00I = num_inputs;\n\n while (I1I1O00I > 2)\n begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I/3) ; O1OIIOII = O1OIIOII+1) begin\n l10III00[O1OIIOII*2] = I0lII01I[O1OIIOII*3] ^ I0lII01I[O1OIIOII*3+1] ^ I0lII01I[O1OIIOII*3+2];\n\n lI0OII0O = (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+1]) |\n (I0lII01I[O1OIIOII*3+1] & I0lII01I[O1OIIOII*3+2]) |\n (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+2]);\n\n l10III00[O1OIIOII*2+1] = lI0OII0O << 1;\n end\n if ((I1I1O00I % 3) > 0) begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I % 3) ; O1OIIOII = O1OIIOII + 1)\n l10III00[2 * (I1I1O00I/3) + O1OIIOII] = I0lII01I[3 * (I1I1O00I/3) + O1OIIOII];\n end\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII = O1OIIOII + 1)\n I0lII01I[O1OIIOII] = l10III00[O1OIIOII];\n I1I1O00I = I1I1O00I - (I1I1O00I/3);\n end\n OII0OOOI = I0lII01I[0];\n if (I1I1O00I > 1)\n O001l0I0 = I0lII01I[1];\n else\n O001l0I0 = {input_width{1'b0}};\nend // IIIIO1Ol\n\n\nassign OUT0 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : OII0OOOI;\nassign OUT1 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : O001l0I0;\n\n// synopsys translate_on\n\nendmodule\n // synopsys translate_off\n// `endif\n // synopsys translate_on\n"], ["/High-Performance-Tensor-Processing-Engines/OPT2/vector_encoder.sv", "module vector_encoder(\n input clk,\n input [127:0] operand_a,\n output reg [3:0] bit_enable [0:15],\n output reg [7:0] partial_product_select [0:15]\n);\n\nwire [3:0] bit_valid [0:15];\nwire [7:0] encoder_nub [0:15];\nreg [127:0] sync_operand ;\n\ngenvar i;\ngenerate\n for(i = 0; i < 16; i = i + 1) begin\n en_t_encoder en_t_preencoder(\n .clk(clk),\n .multiplicand(sync_operand[8*(i+1)-1:8*i]),\n .cal_encode_nub(encoder_nub[i]),\n .bit_enable(bit_valid[i])\n );\n end \nendgenerate\n\nalways @(posedge clk) begin\n sync_operand <= operand_a;\n bit_enable <= bit_valid;\n partial_product_select <= encoder_nub;\nend\n\nendmodule\n\n\n\nmodule en_t_encoder(\n input clk,\n input [7:0] multiplicand, \n output reg [7:0] cal_encode_nub,\n output reg [3:0] bit_enable\n );\n\nwire [7:0] encode_input;\nwire [2:0] c_out;\nwire [7:0] encode_nub;\n\n// covert to bit_enable-Magnitude\nassign encode_input = multiplicand[7] ? ((multiplicand[6:0] == 0) ? 8'b10000000 : {1'b0,~multiplicand[6:0] + 1'b1}) : {1'b0,multiplicand[6:0]};\n\ngenvar i;\ngenerate for(i = 0; i < 4; i = i + 1) begin: gen_encode_nub \n if(i==0) begin\n assign encode_nub[1:0] = encode_input[1:0];\n end\n else if (i==1) begin\n encoder_1 en_t\n (.A(encode_input[2*i-1:2*i-2]),\n .B(encode_input[2*i+1:2*i]), \n .c_out(c_out[i]), \n .en_b(encode_nub[2*i+1:2*i])\n );\n end\n else if (i==3) begin\n encoder_3 en_t\n (.A(encode_input[2*i-1:2*i-2]),\n .c_in(c_out[i-1]), \n .B(encode_input[2*i+1:2*i]), \n .en_b(encode_nub[2*i+1:2*i])\n );\n end\n else begin\n encoder en_t\n (.A(encode_input[2*i-1:2*i-2]),\n .c_in(c_out[i-1]), \n .B(encode_input[2*i+1:2*i]), \n .c_out(c_out[i]), \n .en_b(encode_nub[2*i+1:2*i])\n );\n end \nend \nendgenerate \n\n\ngenerate \n for (i = 0 ; i < 4; i = i + 1) begin\n always @(posedge clk) begin\n if(encode_nub[2*i+1:2*i] == 2'b00) begin\n bit_enable[i] <= 0;\n cal_encode_nub[2*i+1:2*i] <= 0;\n end\n else begin\n bit_enable[i] <= 1;\n cal_encode_nub[2*i+1:2*i] <= {multiplicand[7]^encode_nub[2*i+1],encode_nub[2*i]};\n end\n end\n end\nendgenerate\n\nendmodule\n\n\nmodule encoder_1(A, B, c_out, en_b);\n\ninput wire [1:0] A;\ninput wire [1:0] B;\n \noutput wire c_out;\noutput wire [1:0] en_b;\n\nassign c_out = (A[0] & A[1]); \nassign en_b = B + c_out;\n\nendmodule\n\nmodule encoder(A, c_in, B, c_out, en_b);\n\ninput wire [1:0] A;\ninput wire c_in;\ninput wire [1:0] B;\n \noutput wire c_out;\noutput wire [1:0] en_b;\n\nassign c_out = (A[0] & A[1]) | (A[1] & c_in); \nassign en_b = B + c_out;\n\nendmodule\n\nmodule encoder_3(A, c_in, B, en_b);\n\ninput wire [1:0] A;\ninput wire c_in;\ninput wire [1:0] B;\noutput wire [1:0] en_b;\n\nwire c_out;\nassign c_out = (A[0] & A[1]) | (A[1] & c_in); \nassign en_b = B + c_out;\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT2/top_pe_tile.sv", "module top_pe_tile #(\n localparam RESULT_WIDTH = 20\n)(\n input clk,\n input weight_wen,\n input [7:0] weight_din,\n input [3:0] bit_enable [0:15],\n input [7:0] partial_product_select [0:15],\n output reg signed [RESULT_WIDTH-1:0] result,\n output reg [3:0] bit_enable_pip [0:15],\n output reg [7:0] partial_product_select_pip [0:15]\n);\n\nlocalparam REDUCE_WIDTH = 13;\n\n//*********range of partial_product in same bit-weight********/\n//** 9bit: -256 ≤ partial_product ≤ 254 /\n//** 13bit: -4096 ≤ 16 * partial_product ≤ 4064 /\n//************************************************************/\nwire [7:0] weight [0:15];\nwire signed [9:0] partial_product [0:15][0:3]; \nwire signed [REDUCE_WIDTH-1:0] csa_extend [0:15][0:3];\nwire [16*REDUCE_WIDTH-1:0] csa_input [0:3];\nwire [4*REDUCE_WIDTH-1:0] mid_result [0:3];\nwire signed [REDUCE_WIDTH-1:0] result_bw [0:3];\nwire signed [RESULT_WIDTH-1:0] bw_0;\nwire signed [RESULT_WIDTH-1:0] bw_1;\nwire signed [RESULT_WIDTH-1:0] bw_2;\nwire signed [RESULT_WIDTH-1:0] bw_3;\n\n\nweight_rf weight_buffer(\n .clk(clk),\n .wen(weight_wen),\n .din(weight_din),\n .weight(weight) \n);\n\ngenvar i,j;\ngenerate\n for (i=0;i<16;i=i+1) begin\n partial_product_select pps (\n .clk(clk),\n .weight(weight[i]),\n .bit_enable(bit_enable_pip[i]),\n .partial_product_select(partial_product_select_pip[i]),\n .partial_product(partial_product[i])\n );\n end\nendgenerate\n\ngenerate\n for (i=0;i<16;i=i+1) begin\n for (j=0;j<4;j=j+1) begin\n assign csa_extend[i][j] = $signed(partial_product[i][j]);\n end\n end\nendgenerate\n\ngenerate\n for (i=0;i<4;i=i+1) begin\n for (j=0;j<16;j=j+1) begin\n assign csa_input[i][(j+1)*REDUCE_WIDTH-1:j*REDUCE_WIDTH] = csa_extend[j][i];\n end\n end\nendgenerate\n\n\ngenerate\n for (i=0;i<4;i=i+1) begin\n\n tree_full_sum #(\n .K(4),\n .WIDTH(REDUCE_WIDTH)\n ) tree_stage_1_0 (\n .clk(clk),\n .csa_input({csa_input[i][1*REDUCE_WIDTH-1:0],\n csa_input[i][2*REDUCE_WIDTH-1:1*REDUCE_WIDTH],\n csa_input[i][3*REDUCE_WIDTH-1:2*REDUCE_WIDTH],\n csa_input[i][4*REDUCE_WIDTH-1:3*REDUCE_WIDTH]}),\n .full_sum(mid_result[i][1*REDUCE_WIDTH-1:0*REDUCE_WIDTH])\n );\n tree_full_sum #(\n .K(4),\n .WIDTH(REDUCE_WIDTH)\n ) tree_stage_1_1 (\n .clk(clk),\n .csa_input({csa_input[i][5*REDUCE_WIDTH-1:4*REDUCE_WIDTH],\n csa_input[i][6*REDUCE_WIDTH-1:5*REDUCE_WIDTH],\n csa_input[i][7*REDUCE_WIDTH-1:6*REDUCE_WIDTH],\n csa_input[i][8*REDUCE_WIDTH-1:7*REDUCE_WIDTH]}),\n .full_sum(mid_result[i][2*REDUCE_WIDTH-1:1*REDUCE_WIDTH])\n );\n tree_full_sum #(\n .K(4),\n .WIDTH(REDUCE_WIDTH)\n ) tree_stage_1_2 (\n .clk(clk),\n .csa_input({csa_input[i][9*REDUCE_WIDTH-1:8*REDUCE_WIDTH],\n csa_input[i][10*REDUCE_WIDTH-1:9*REDUCE_WIDTH],\n csa_input[i][11*REDUCE_WIDTH-1:10*REDUCE_WIDTH],\n csa_input[i][12*REDUCE_WIDTH-1:11*REDUCE_WIDTH]}),\n .full_sum(mid_result[i][3*REDUCE_WIDTH-1:2*REDUCE_WIDTH])\n );\n tree_full_sum #(\n .K(4),\n .WIDTH(REDUCE_WIDTH)\n ) tree_stage_1_3 (\n .clk(clk),\n .csa_input({csa_input[i][13*REDUCE_WIDTH-1:12*REDUCE_WIDTH],\n csa_input[i][14*REDUCE_WIDTH-1:13*REDUCE_WIDTH],\n csa_input[i][15*REDUCE_WIDTH-1:14*REDUCE_WIDTH],\n csa_input[i][16*REDUCE_WIDTH-1:15*REDUCE_WIDTH]}),\n .full_sum(mid_result[i][4*REDUCE_WIDTH-1:3*REDUCE_WIDTH])\n );\n end\nendgenerate\n\n\ngenerate\n for (i=0;i<4;i=i+1) begin\n tree_full_sum #(\n .K(4),\n .WIDTH(REDUCE_WIDTH)\n ) tree_stage_2 (\n .clk(clk),\n .csa_input({mid_result[i][1*REDUCE_WIDTH-1:0],\n mid_result[i][2*REDUCE_WIDTH-1:1*REDUCE_WIDTH],\n mid_result[i][3*REDUCE_WIDTH-1:2*REDUCE_WIDTH],\n mid_result[i][4*REDUCE_WIDTH-1:3*REDUCE_WIDTH]}),\n .full_sum(result_bw[i])\n );\n end\nendgenerate\n\n\nassign bw_0 = $signed(result_bw[0]);\nassign bw_1 = $signed({result_bw[1],2'b0});\nassign bw_2 = $signed({result_bw[2],4'b0});\nassign bw_3 = $signed({result_bw[3],6'b0});\n\ntree_full_sum #(\n .K(4),\n .WIDTH(RESULT_WIDTH)\n) tree_stage_3 (\n .clk(clk),\n .csa_input({bw_0,bw_1,bw_2,bw_3}),\n .full_sum(result)\n );\n\n// pipeline the bit_enable and partial_product_select\nalways @(posedge clk) begin\n bit_enable_pip <= bit_enable;\n partial_product_select_pip <= partial_product_select;\nend\n\nendmodule\n\n\n\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT3_OPT4C/pe/encoder_multi_bit.v", "module encoder_multi_bit #(\n localparam WIDTH = 8,\n localparam ENCODER_WIDTH = WIDTH + (WIDTH+1)%2,\n localparam TIMES = (WIDTH-1)/2 + (WIDTH-1)%2\n)(\n input clk,\n input rst_n,\n input [WIDTH-1:0] multiplicand,\n input multiplicand_valid, \n output reg [WIDTH:0] en_multiplicand, // native EN-T encoding is sent to tensorcore local memory or local rf.\n output en_multiplicand_valid\n );\n\nwire [WIDTH-1:0] encoder_input;\nwire [ENCODER_WIDTH-1:0] en_multiplicand_ins;\nwire [TIMES-1:0] en_t_c_out;\nreg [WIDTH-1:0] multiplicand_reg;\n\nassign encoder_input = (multiplicand_reg != 8'b10000000) ? {1'b0,multiplicand_reg[WIDTH-2:0]} : 8'b10000000;\nassign en_multiplicand_ins[ENCODER_WIDTH-1] = multiplicand_reg[WIDTH-1];\n\ngenvar i;\ngenerate for(i = 0; i < TIMES; i = i + 1) begin: gen_encoder \n if(i==0) begin\n assign en_multiplicand_ins[1:0] = multiplicand_reg[1:0];\n end\n else if (i==1)begin\n encoder ins_encoder\n (.A(encoder_input[2*i-1:2*i-2]),\n .C_IN(1'b0), \n .B(encoder_input[2*i+1:2*i]), \n .en_t_c_out(en_t_c_out[i]), \n .EN_B(en_multiplicand_ins[2*i+1:2*i]));\n end\n else begin\n encoder ins_encoder\n (.A(encoder_input[2*i-1:2*i-2]),\n .C_IN(en_t_c_out[i-1]), \n .B(encoder_input[2*i+1:2*i]), \n .en_t_c_out(en_t_c_out[i]), \n .EN_B(en_multiplicand_ins[2*i+1:2*i]));\n end \nend \nendgenerate \n\n\nalways @(posedge clk or negedge rst_n) begin\n\tif (!rst_n) begin\n en_multiplicand <= 0;\n multiplicand_reg <= 0;\n end\n\telse begin\n en_multiplicand <= en_multiplicand_ins; \n //multiplicand belongs to [-128,127] range and operand with complement representation use this logic:\n multiplicand_reg <= (multiplicand[WIDTH-1] & (multiplicand[WIDTH-2:0] != 0)) ? ({1'b1,~multiplicand[WIDTH-2:0] + 1'b1}) : multiplicand; \n //multiplicand belongs to [-127,127] range and operand with sign-magnitude representation use this logic:\n //multiplicand_reg <= multiplicand; \n end\nend\n\nget_pipeline_mulwidth #(\n .N(2), \n .WIDTH(1) \n) pipeline_en_multiplicand_valid (\n .clk(clk), \n .rst_n(rst_n), \n .signal(multiplicand_valid), \n .pipeline_signal(en_multiplicand_valid) \n);\n\nendmodule\n\n\nmodule encoder(A, C_IN, B, en_t_c_out, EN_B);\n\ninput wire [1:0] A;\ninput wire C_IN;\ninput wire [1:0] B;\n\noutput wire en_t_c_out;\noutput wire [1:0] EN_B;\n\nassign en_t_c_out = (A[0] & A[1]) | (A[1] & C_IN); \nassign EN_B = B + en_t_c_out;\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT3_OPT4C/pe/sparse_encoder.v", "module sparse_encoder (\n input clk,\n input rst_n,\n input [7:0] en_multiplicand,\n input [3:0] sign_en_multiplicand,\n input encode_valid,\n output reg [1:0] partial_product_index, // to sparse_pe generate partial product\n output reg [1:0] position_0, // to prefetch operand b\n output [2:0] cal_cycle // to prefetch operand a \n);\n\nwire a ;\nwire b ;\nwire c ;\nwire d ;\n\nreg [7:0] cal_en_multiplicand;\nreg [1:0] position_1 ;\nreg [1:0] position_2 ;\nreg position_3 ;\n\nassign a = en_multiplicand[0] | en_multiplicand[1];\nassign b = en_multiplicand[2] | en_multiplicand[3];\nassign c = en_multiplicand[4] | en_multiplicand[5];\nassign d = en_multiplicand[6] | en_multiplicand[7];\n\n\nassign a_b_c_d = (a) & (b) & (c) & (d);\nassign cal_cycle = {a_b_c_d,(~a & ( (b & c) | (b & d) | (c & d) )) | (a & ( (b & ~c) | (~b & d) | (c & ~d) )),(a ^ b) ^ (c ^ d)};\n\n/**********************************************/\n/******** 00 | 01 | 10 | 11 | *********/\n/******** -2B | B | 2B | -B | *********/\n/**********************************************/\ngenvar i;\ngenerate\n for (i = 0 ; i < 4 ; i = i + 1) begin : gen_cal_encoder\n always @(posedge clk or negedge rst_n) begin\n\t if (!rst_n) begin\n cal_en_multiplicand[2*(i+1)-1:2*i] <= 0;\n\t end\n\t else begin\n if(encode_valid) begin\n if(sign_en_multiplicand[i]) begin\n cal_en_multiplicand[2*(i+1)-1:2*i] <= {~en_multiplicand[2*(i+1)-1],en_multiplicand[2*i]};\n end\n else\n cal_en_multiplicand[2*(i+1)-1:2*i] <= en_multiplicand[2*(i+1)-1:2*i];\n end else\n cal_en_multiplicand[2*(i+1)-1:2*i] <= cal_en_multiplicand[2*(i+1)-1:2*i] ;\n\t end\n end\n end\nendgenerate\n \n\n\nalways @(posedge clk or negedge rst_n) begin\n if (!rst_n) begin\n position_0 <= 2'b0 ; \n position_1 <= 2'b0 ; \n position_2 <= 2'b0 ; \n position_3 <= 1'b0 ;\n end\n else begin\n if(encode_valid) begin\n position_0 <= {(~a)&(~b), (~a & (b | ~c))};\n position_1 <= {( (a ^ b) & (c | d)) | ( (~a)&(c)&(d) ), (a & b) | ( d & ( ( (a ^ b) & ~c ) | ( ~a & ~b & c ) ))};\n position_2 <= {(c & d & (a | b)) | (a & b & (c | d)), d & ( (a&b | a&c | b&c) & ~(a&b&c) )};\n position_3 <= a_b_c_d;\n end\n else begin\n position_0 <= position_1;\n position_1 <= position_2;\n position_2 <= {position_3,position_3};\n position_3 <= 0;\n end\n end\nend\n\n\nalways @(posedge clk) begin\n case(position_0) \n 2'b00: partial_product_index <= cal_en_multiplicand[1:0];\n 2'b01: partial_product_index <= cal_en_multiplicand[3:2];\n 2'b10: partial_product_index <= cal_en_multiplicand[5:4];\n 2'b11: partial_product_index <= cal_en_multiplicand[7:6];\n endcase\nend\n\nendmodule\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/top.v", "module top #\n(\n parameter A_H = 16, //CHANGE\n parameter B_W = 16, //CHANGE\n parameter WIDTH = 8,\n parameter ACC_WIDTH = 32 //CHANGE\n)\n(\n input wire rst_n ,\n input wire clk ,\n input wire [A_H*WIDTH-1 :0] A ,\n input wire [B_W*WIDTH-1 :0] B ,\n input wire clc , // clean_result_cache\n// output wire [A_H*B_W*ACC_WIDTH-1 :0] result \n output wire [2*A_H*B_W*ACC_WIDTH-1 :0] result \n);\n\nreg [A_H*WIDTH-1 :0] A_reg ;\nreg [B_W*WIDTH-1 :0] B_reg ;\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n A_reg<={(A_H*WIDTH){1'b0}};\n B_reg<={(B_W*WIDTH){1'b0}};\n end\n else begin\n A_reg<=A;\n B_reg<=B;\n end\nend\n\nwire signed [WIDTH-1:0] row [0:A_H-1][0:B_W-1];\nwire signed [WIDTH-1:0] col [0:A_H-1][0:B_W-1];\n\n\n genvar i, j;\n generate\n for (i = 0; i < A_H; i = i + 1 ) begin\n for(j = 0; j < B_W; j = j + 1) begin\n if(i==0) begin\n if(j==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .a (A_reg[WIDTH-1 :0] ),\n .b (B_reg[WIDTH-1 :0] ),\n .clc (clc ), // input wire clean_result_cache\n .row (row[i][j] ),\n .col (col[i][j] ),\n// .result (result[(i*B_W+j+1)*ACC_WIDTH-1:(i*B_W+j)*ACC_WIDTH])\n .result (result[(i*B_W+j+1)*2*ACC_WIDTH-1:(i*B_W+j)*2*ACC_WIDTH])\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .a (row[i][j-1] ),\n .b (B_reg[WIDTH*(j+1)-1 :WIDTH*j] ),\n .clc (clc ), // input wire clean_result_cache\n .row (row[i][j] ),\n .col (col[i][j] ),\n// .result (result[(i*B_W+j+1)*ACC_WIDTH-1:(i*B_W+j)*ACC_WIDTH])\n .result (result[(i*B_W+j+1)*2*ACC_WIDTH-1:(i*B_W+j)*2*ACC_WIDTH])\n );\n end\n end\n else if (j==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .a (A_reg[WIDTH*(i+1)-1 :WIDTH*i] ),\n .b (col[i-1][j] ),\n .clc (clc ), // input wire clean_result_cache\n .row (row[i][j] ),\n .col (col[i][j] ),\n// .result (result[(i*B_W+j+1)*ACC_WIDTH-1:(i*B_W+j)*ACC_WIDTH])\n .result (result[(i*B_W+j+1)*2*ACC_WIDTH-1:(i*B_W+j)*2*ACC_WIDTH])\n );\n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .a (row[i][j-1] ),\n .b (col[i-1][j] ),\n .clc (clc ), // input wire clean_result_cache\n .row (row[i][j] ),\n .col (col[i][j] ),\n// .result (result[(i*B_W+j+1)*ACC_WIDTH-1:(i*B_W+j)*ACC_WIDTH])\n .result (result[(i*B_W+j+1)*2*ACC_WIDTH-1:(i*B_W+j)*2*ACC_WIDTH])\n ); \n \n end \n end\n end\n endgenerate\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_mac_based/top.v", "// Calculate matrix (A*B)\n// Size of A is (M*K), size of B is (K*N), and A_H = K, B_W = N, B is weight\n// Size of output matirx A*B is (M*N)\n\nmodule top #\n(\n parameter A_H = 16, \n parameter B_W = 16, \n parameter WIDTH = 8,\n // parameter ACC_WIDTH = 32 \n parameter ACC_WIDTH = 2*WIDTH + $clog2(A_H)\n)\n(\n input wire clk ,\n input wire rst_n ,\n input weight_wen ,\n input [A_H*WIDTH-1 :0] weight_din ,\n input wire [A_H*WIDTH-1 :0] A ,\n output wire [B_W*ACC_WIDTH-1 :0] result \n);\n\nreg [A_H*WIDTH-1 :0] A_reg ;\nreg [A_H*WIDTH-1 :0] weight_din_reg;\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n A_reg<={(A_H*WIDTH){1'b0}};\n weight_din_reg <= {(B_W*WIDTH){1'b0}};\n end\n else begin\n A_reg<=A;\n weight_din_reg <= weight_din;\n end\nend\n\n\nwire signed [ACC_WIDTH-1:0] row [0:B_W-1][0:A_H-1];\nwire signed [WIDTH-1:0] col [0:B_W-1][0:A_H-1];\n\n\n genvar i, j;\n generate\n for (i = 0; i < B_W; i = i + 1 ) begin\n for(j = 0; j < A_H; j = j + 1) begin\n if(j==0) begin\n if(i==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .weight_wen (weight_wen ),\n .weight_din (weight_din_reg[(j+1)*WIDTH-1:j*WIDTH] ),\n .a (A_reg[(j+1)*WIDTH-1:j*WIDTH] ),\n .partial_result ({ACC_WIDTH{1'b0}} ), // or input\n .row (row[i][j] ),\n .col (col[i][j] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .weight_wen (weight_wen ),\n .weight_din (col[i-1][j] ),\n .a (col[i-1][j] ),\n .partial_result ({ACC_WIDTH{1'b0}} ), // or input\n .row (row[i][j] ),\n .col (col[i][j] )\n ); \n end\n end\n else if (i==0) begin\n if(j==A_H-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .weight_wen (weight_wen ),\n .weight_din (weight_din_reg[(j+1)*WIDTH-1:j*WIDTH] ),\n .a (A_reg[(j+1)*WIDTH-1:j*WIDTH] ),\n .partial_result (row[i][j-1] ),\n .row (result[(i+1)*ACC_WIDTH-1 :i*ACC_WIDTH] ),\n .col (col[i][j] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .weight_wen (weight_wen ),\n .weight_din (weight_din_reg[(j+1)*WIDTH-1:j*WIDTH] ),\n .a (A_reg[(j+1)*WIDTH-1:j*WIDTH] ),\n .partial_result (row[i][j-1] ),\n .row (row[i][j] ),\n .col (col[i][j] )\n ); \n end\n end\n else if (j==A_H-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .weight_wen (weight_wen ),\n .weight_din (col[i-1][j] ),\n .a (col[i-1][j] ),\n .partial_result (row[i][j-1] ),\n .row (result[(i+1)*ACC_WIDTH-1 :i*ACC_WIDTH] ),\n .col (col[i][j] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .weight_wen (weight_wen ),\n .weight_din (col[i-1][j] ),\n .a (col[i-1][j] ),\n .partial_result (row[i][j-1] ),\n .row (row[i][j] ),\n .col (col[i][j] )\n ); \n end\n end\n end\nendgenerate\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/opt1_mac.v", "module opt1_mac #(\n parameter ACC_WIDTH = 32,\n parameter INPUT_PIP = 1\n)(\n input wire clk,\n input wire rst_n,\n input wire [7:0] operand_a_in, \n input wire [7:0] operand_b_in, \n input wire signed [2*ACC_WIDTH-1:0] partial_result, \n output reg [ACC_WIDTH-1:0] acc_sum,\n output reg [ACC_WIDTH-1:0] acc_carry\n);\n\nreg [7:0] operand_a;\nreg [7:0] operand_b;\n\nwire signed [9:0] pp1;\nwire signed [9:0] pp2;\nwire signed [9:0] pp3;\nwire signed [9:0] pp4;\nwire [6*ACC_WIDTH-1 : 0] mul_reduce_csa_input;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp1;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp2;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp3;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp4;\nwire signed [ACC_WIDTH-1:0] reduce_acc_sum;\nwire signed [ACC_WIDTH-1:0] reduce_acc_carry;\n\nassign sign_extend_pp4 = $signed({pp4,6'b0});\nassign sign_extend_pp3 = $signed({pp3,4'b0});\nassign sign_extend_pp2 = $signed({pp2,2'b0});\nassign sign_extend_pp1 = $signed(pp1);\n\nassign mul_reduce_csa_input = {sign_extend_pp4,sign_extend_pp3,sign_extend_pp2,sign_extend_pp1,partial_result[0+:ACC_WIDTH],partial_result[ACC_WIDTH+:ACC_WIDTH]};\n\nbooth_pp_gen booth_pp_gen_inst(\n .operand_a(operand_a), \n .operand_b(operand_b), \n .pp1(pp1),\n .pp2(pp2),\n .pp3(pp3),\n .pp4(pp4)\n);\n\nDW02_tree #(6, ACC_WIDTH, 1)\n U2 ( .INPUT(mul_reduce_csa_input), .OUT0(reduce_acc_sum), .OUT1(reduce_acc_carry) );\n\nalways @(posedge clk) begin\n if (!rst_n) begin\n acc_sum <= 0;\n acc_carry <= 0;\n end\n else begin\n acc_sum <= reduce_acc_sum;\n acc_carry <= reduce_acc_carry;\n end\nend\n\ngenerate\n if(INPUT_PIP == 1) begin\n always @(posedge clk) begin\n operand_a <= operand_a_in;\n operand_b <= operand_b_in;\n end\n end\n else begin\n always @(*) begin\n operand_a = operand_a_in;\n operand_b = operand_b_in;\n end\n end\nendgenerate\n\n// dff_async #(\n// .WIDTH(ACC_WIDTH)) acc_sum_reg (\n// .clk(clk),\n// .rst_n(rst_n),\n// .d(reduce_acc_sum),\n// .q(acc_sum)\n// );\n\n// dff_async #(\n// .WIDTH(ACC_WIDTH)) acc_carry_reg (\n// .clk(clk),\n// .rst_n(rst_n),\n// .d(reduce_acc_carry),\n// .q(acc_carry)\n// );\n\n\n\n \nendmodule\n\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/opt1_mac.v", "module opt1_mac #(\n parameter ACC_WIDTH = 32,\n parameter INPUT_PIP = 1\n)(\n input wire clk,\n input wire rst_n,\n input wire [7:0] operand_a_in, \n input wire [7:0] operand_b_in, \n input wire signed [2*ACC_WIDTH-1:0] partial_result, \n output reg [ACC_WIDTH-1:0] acc_sum,\n output reg [ACC_WIDTH-1:0] acc_carry\n);\n\nreg [7:0] operand_a;\nreg [7:0] operand_b;\n\nwire signed [9:0] pp1;\nwire signed [9:0] pp2;\nwire signed [9:0] pp3;\nwire signed [9:0] pp4;\nwire [6*ACC_WIDTH-1 : 0] mul_reduce_csa_input;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp1;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp2;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp3;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp4;\nwire signed [ACC_WIDTH-1:0] reduce_acc_sum;\nwire signed [ACC_WIDTH-1:0] reduce_acc_carry;\n\nassign sign_extend_pp4 = $signed({pp4,6'b0});\nassign sign_extend_pp3 = $signed({pp3,4'b0});\nassign sign_extend_pp2 = $signed({pp2,2'b0});\nassign sign_extend_pp1 = $signed(pp1);\n\nassign mul_reduce_csa_input = {sign_extend_pp4,sign_extend_pp3,sign_extend_pp2,sign_extend_pp1,partial_result[0+:ACC_WIDTH],partial_result[ACC_WIDTH+:ACC_WIDTH]};\n\nbooth_pp_gen booth_pp_gen_inst(\n .operand_a(operand_a), \n .operand_b(operand_b), \n .pp1(pp1),\n .pp2(pp2),\n .pp3(pp3),\n .pp4(pp4)\n);\n\nDW02_tree #(6, ACC_WIDTH, 1)\n U2 ( .INPUT(mul_reduce_csa_input), .OUT0(reduce_acc_sum), .OUT1(reduce_acc_carry) );\n\nalways @(posedge clk) begin\n if (!rst_n) begin\n acc_sum <= 0;\n acc_carry <= 0;\n end\n else begin\n acc_sum <= reduce_acc_sum;\n acc_carry <= reduce_acc_carry;\n end\nend\n\ngenerate\n if(INPUT_PIP == 1) begin\n always @(posedge clk) begin\n operand_a <= operand_a_in;\n operand_b <= operand_b_in;\n end\n end\n else begin\n always @(*) begin\n operand_a = operand_a_in;\n operand_b = operand_b_in;\n end\n end\nendgenerate\n\n// dff_async #(\n// .WIDTH(ACC_WIDTH)) acc_sum_reg (\n// .clk(clk),\n// .rst_n(rst_n),\n// .d(reduce_acc_sum),\n// .q(acc_sum)\n// );\n\n// dff_async #(\n// .WIDTH(ACC_WIDTH)) acc_carry_reg (\n// .clk(clk),\n// .rst_n(rst_n),\n// .d(reduce_acc_carry),\n// .q(acc_carry)\n// );\n\n\n\n \nendmodule\n\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_mac_based/top.v", "module top #\n(\n parameter A_H = 16, \n parameter B_W = 16, \n parameter WIDTH = 8,\n parameter ACC_WIDTH = 32 \n)\n(\n input wire rst_n ,\n input wire clk ,\n input wire [A_H*WIDTH-1 :0] A ,\n input wire [B_W*WIDTH-1 :0] B ,\n input wire clc , // clean_result_cache,\n output wire [A_H*B_W*ACC_WIDTH-1 :0] result \n);\n\nreg [A_H*WIDTH-1 :0] A_reg ;\nreg [B_W*WIDTH-1 :0] B_reg ;\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n A_reg<={(A_H*WIDTH){1'b0}};\n B_reg<={(B_W*WIDTH){1'b0}};\n end\n else begin\n A_reg<=A;\n B_reg<=B;\n end\nend\n\nwire signed [WIDTH-1:0] row [0:A_H-1][0:B_W-1];\nwire signed [WIDTH-1:0] col [0:A_H-1][0:B_W-1];\n\n\n genvar i, j;\n generate\n for (i = 0; i < A_H; i = i + 1 ) begin\n for(j = 0; j < B_W; j = j + 1) begin\n if(i==0) begin\n if(j==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .a (A_reg[WIDTH-1 :0] ),\n .b (B_reg[WIDTH-1 :0] ),\n .clc (clc ),\n .row (row[i][j] ),\n .col (col[i][j] ),\n .result (result[(i*B_W+j+1)*ACC_WIDTH-1:(i*B_W+j)*ACC_WIDTH])\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .a (row[i][j-1] ),\n .b (B_reg[WIDTH*(j+1)-1 :WIDTH*j] ),\n .clc (clc ),\n .row (row[i][j] ),\n .col (col[i][j] ),\n .result (result[(i*B_W+j+1)*ACC_WIDTH-1:(i*B_W+j)*ACC_WIDTH])\n );\n end\n end\n else if (j==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .a (A_reg[WIDTH*(i+1)-1 :WIDTH*i] ),\n .b (col[i-1][j] ),\n .clc (clc ),\n .row (row[i][j] ),\n .col (col[i][j] ),\n .result (result[(i*B_W+j+1)*ACC_WIDTH-1:(i*B_W+j)*ACC_WIDTH])\n );\n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .a (row[i][j-1] ),\n .b (col[i-1][j] ),\n .clc (clc ),\n .row (row[i][j] ),\n .col (col[i][j] ),\n .result (result[(i*B_W+j+1)*ACC_WIDTH-1:(i*B_W+j)*ACC_WIDTH])\n ); \n \n end \n end\n end\n endgenerate\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/top.v", "`timescale 1ns / 1ps\n\n// Calculate matrix (A*B)\n// Size of A is (A_H*A_W), size of B is (B_H*B_W), and A_W = B_H\n// Size of output matirx A*B is (A_H*B_W)\n\nmodule top #\n(\n parameter N = 8, //CHANGE\n parameter WIDTH = 8, \n parameter ACC_WIDTH = 2*WIDTH + $clog2(N) \n)\n(\n input wire rst_n ,\n input wire clk ,\n input wire [N*N*WIDTH-1 :0] A ,\n input wire [N*N*WIDTH-1 :0] B ,\n output wire [N*N*2*ACC_WIDTH-1 :0] result \n);\n\nreg [N*N*WIDTH-1 :0] A_reg ;\nreg [N*N*WIDTH-1 :0] B_reg ;\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n A_reg<={(N*N*WIDTH){1'b0}};\n B_reg<={(N*N*WIDTH){1'b0}};\n end\n else begin\n A_reg<=A;\n B_reg<=B;\n end\nend\n\n\nwire signed [WIDTH-1:0] d_x [0:N-1][0:N-1][0:N-1];\nwire signed [2*ACC_WIDTH-1:0] d_y [0:N-1][0:N-1][0:N-1];\nwire signed [WIDTH-1:0] d_z [0:N-1][0:N-1][0:N-1];\n\n\n genvar x, y, z;\n generate\n for (z = 0; z < N; z = z + 1 ) begin\n for(x = 0; x < N; x = x + 1) begin\n for (y = 0; y < N; y = y + 1 ) begin\n if(z==0) begin\n if(x==0) begin\n if(y==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE //(1)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p ({2*ACC_WIDTH{1'b0}} ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n ); \n end\n else if(y==N-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(3)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (result[N*2*ACC_WIDTH*z+(x+1)*2*ACC_WIDTH-1 : 2*ACC_WIDTH*N*z+x*2*ACC_WIDTH] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(2)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n );\n end\n end\n else begin\n if(y==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE //(6)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p ({2*ACC_WIDTH{1'b0}} ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n ); \n end\n else if(y==N-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(5)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (result[N*2*ACC_WIDTH*z+(x+1)*2*ACC_WIDTH-1 : 2*ACC_WIDTH*N*z+x*2*ACC_WIDTH] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(4)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n );\n end \n end\n end\n else begin\n if(x==0) begin\n if(y==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE //(7)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p ({2*ACC_WIDTH{1'b0}} ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n ); \n end\n else if(y==N-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(9)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (result[N*2*ACC_WIDTH*z+(x+1)*2*ACC_WIDTH-1 : 2*ACC_WIDTH*N*z+x*2*ACC_WIDTH] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(8)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n );\n end\n end\n else begin\n if(y==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE //(10)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p ({2*ACC_WIDTH{1'b0}} ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n ); \n end\n else if(y==N-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(12)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (result[N*2*ACC_WIDTH*z+(x+1)*2*ACC_WIDTH-1 : 2*ACC_WIDTH*N*z+x*2*ACC_WIDTH] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(11)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n );\n end \n end\n end\n end\n end\n end\n endgenerate\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/opt1_mac.v", "module opt1_mac #(\n parameter ACC_WIDTH = 32,\n parameter INPUT_PIP = 1\n)(\n input wire clk,\n input wire rst_n,\n input wire [7:0] operand_a_in, \n input wire [7:0] operand_b_in, \n input wire clc, // clean_result_cache\n output reg [ACC_WIDTH-1:0] acc_sum,\n output reg [ACC_WIDTH-1:0] acc_carry\n);\n\nreg [7:0] operand_a;\nreg [7:0] operand_b;\n\nwire signed [9:0] pp1;\nwire signed [9:0] pp2;\nwire signed [9:0] pp3;\nwire signed [9:0] pp4;\nwire [6*ACC_WIDTH-1 : 0] mul_reduce_csa_input;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp1;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp2;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp3;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp4;\nwire signed [ACC_WIDTH-1:0] reduce_acc_sum;\nwire signed [ACC_WIDTH-1:0] reduce_acc_carry;\n\nassign sign_extend_pp4 = $signed({pp4,6'b0});\nassign sign_extend_pp3 = $signed({pp3,4'b0});\nassign sign_extend_pp2 = $signed({pp2,2'b0});\nassign sign_extend_pp1 = $signed(pp1);\n\nassign mul_reduce_csa_input = {sign_extend_pp4,sign_extend_pp3,sign_extend_pp2,sign_extend_pp1,acc_carry,acc_sum};\n\nbooth_pp_gen booth_pp_gen_inst(\n .operand_a(operand_a), \n .operand_b(operand_b), \n .pp1(pp1),\n .pp2(pp2),\n .pp3(pp3),\n .pp4(pp4)\n);\n\nDW02_tree #(6, ACC_WIDTH, 1)\n U2 ( .INPUT(mul_reduce_csa_input), .OUT0(reduce_acc_sum), .OUT1(reduce_acc_carry) );\n\nalways @(posedge clk) begin\n if (!rst_n) begin\n acc_sum <= 0;\n acc_carry <= 0;\n end\n else begin\n if(clc) begin\n acc_sum <= 0;\n acc_carry <= 0;\n end\n else begin\n acc_sum <= reduce_acc_sum;\n acc_carry <= reduce_acc_carry;\n end\n end\nend\n\ngenerate\n if(INPUT_PIP == 1) begin\n always @(posedge clk) begin\n operand_a <= operand_a_in;\n operand_b <= operand_b_in;\n end\n end\n else begin\n always @(*) begin\n operand_a = operand_a_in;\n operand_b = operand_b_in;\n end\n end\nendgenerate\n\n// dff_async #(\n// .WIDTH(ACC_WIDTH)) acc_sum_reg (\n// .clk(clk),\n// .rst_n(rst_n),\n// .d(reduce_acc_sum),\n// .q(acc_sum)\n// );\n\n// dff_async #(\n// .WIDTH(ACC_WIDTH)) acc_carry_reg (\n// .clk(clk),\n// .rst_n(rst_n),\n// .d(reduce_acc_carry),\n// .q(acc_carry)\n// );\n\n\n\n \nendmodule\n\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/opt1_mac.v", "module opt1_mac #(\n parameter ACC_WIDTH = 32,\n parameter INPUT_PIP = 1\n)(\n input wire clk,\n input wire rst_n,\n input wire [7:0] operand_a_in, \n input wire [7:0] operand_b_in, \n output reg [ACC_WIDTH-1:0] acc_sum,\n output reg [ACC_WIDTH-1:0] acc_carry\n);\n\nreg [7:0] operand_a;\nreg [7:0] operand_b;\n\nwire signed [9:0] pp1;\nwire signed [9:0] pp2;\nwire signed [9:0] pp3;\nwire signed [9:0] pp4;\nwire [6*ACC_WIDTH-1 : 0] mul_reduce_csa_input;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp1;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp2;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp3;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp4;\nwire signed [ACC_WIDTH-1:0] reduce_acc_sum;\nwire signed [ACC_WIDTH-1:0] reduce_acc_carry;\n\nassign sign_extend_pp4 = $signed({pp4,6'b0});\nassign sign_extend_pp3 = $signed({pp3,4'b0});\nassign sign_extend_pp2 = $signed({pp2,2'b0});\nassign sign_extend_pp1 = $signed(pp1);\n\nassign mul_reduce_csa_input = {sign_extend_pp4,sign_extend_pp3,sign_extend_pp2,sign_extend_pp1,acc_carry, acc_sum};\n\nbooth_pp_gen booth_pp_gen_inst(\n .operand_a(operand_a), \n .operand_b(operand_b), \n .pp1(pp1),\n .pp2(pp2),\n .pp3(pp3),\n .pp4(pp4)\n);\n\nDW02_tree #(6, ACC_WIDTH, 1)\n U2 ( .INPUT(mul_reduce_csa_input), .OUT0(reduce_acc_sum), .OUT1(reduce_acc_carry) );\n\nalways @(posedge clk) begin\n if (!rst_n) begin\n acc_sum <= 0;\n acc_carry <= 0;\n end\n else begin\n acc_sum <= reduce_acc_sum;\n acc_carry <= reduce_acc_carry;\n end\nend\n\ngenerate\n if(INPUT_PIP == 1) begin\n always @(posedge clk) begin\n operand_a <= operand_a_in;\n operand_b <= operand_b_in;\n end\n end\n else begin\n always @(*) begin\n operand_a = operand_a_in;\n operand_b = operand_b_in;\n end\n end\nendgenerate\n\n// dff_async #(\n// .WIDTH(ACC_WIDTH)) acc_sum_reg (\n// .clk(clk),\n// .rst_n(rst_n),\n// .d(reduce_acc_sum),\n// .q(acc_sum)\n// );\n\n// dff_async #(\n// .WIDTH(ACC_WIDTH)) acc_carry_reg (\n// .clk(clk),\n// .rst_n(rst_n),\n// .d(reduce_acc_carry),\n// .q(acc_carry)\n// );\n\n\n\n \nendmodule\n\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT2/tree_full_sum.sv", "module tree_full_sum #(\n parameter K = 16,\n parameter WIDTH = 13\n)(\n input clk,\n input [K*WIDTH-1:0] csa_input,\n output reg signed [WIDTH-1:0] full_sum\n);\n\nwire signed [WIDTH-1:0] acc_sum;\nwire signed [WIDTH-1:0] acc_carry;\n\ngenvar i;\ngenerate\n if(K == 4) begin\n always @(posedge clk) begin\n full_sum <= $signed(csa_input[1*WIDTH-1:0*WIDTH]) + $signed(csa_input[2*WIDTH-1:1*WIDTH]) + $signed(csa_input[3*WIDTH-1:2*WIDTH]) + $signed(csa_input[4*WIDTH-1:3*WIDTH]);\n end\n end\n else begin\n DW02_tree #(K, WIDTH, 1)\n ins_tree ( .INPUT(csa_input), .OUT0(acc_sum), .OUT1(acc_carry));\n always @(posedge clk) begin\n full_sum <= $signed(acc_sum) + $signed(acc_carry);\n end\n end\nendgenerate\n\n\n\n\nendmodule\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT2/partial_product_select.sv", "module partial_product_select(\n input clk,\n input [7:0] weight,\n input [3:0] bit_enable,\n input [7:0] partial_product_select,\n output signed [9:0] partial_product [0:3] \n);\n\nwire signed [8:0] inv_b;\nwire signed [7:0] b;\nwire signed [8:0] b_2;\nwire signed [8:0] b_neg;\nwire signed [9:0] b_2_neg;\nwire [1:0] cal_partial_product_select [0:3];\nreg signed [9:0] partial_product_bw [0:3]; \n\nassign cal_partial_product_select[0] = partial_product_select[1:0];\nassign cal_partial_product_select[1] = partial_product_select[3:2];\nassign cal_partial_product_select[2] = partial_product_select[5:4];\nassign cal_partial_product_select[3] = partial_product_select[7:6];\nassign partial_product = partial_product_bw;\nassign b = $signed(weight);\nassign inv_b = $signed(~b);\nassign b_2 = {b,1'b0};\nassign b_neg = inv_b + 1'b1;\nassign b_2_neg = {b_neg,1'b0};\n\ngenvar i;\ngenerate \n for (i = 0 ; i < 4; i = i + 1) begin\n always @(posedge clk) begin\n if(bit_enable[i]) begin\n case(cal_partial_product_select[i])\n 2'b00: partial_product_bw[i] <= $signed(b_2_neg);\n 2'b01: partial_product_bw[i] <= $signed(b);\n 2'b10: partial_product_bw[i] <= $signed(b_2);\n 2'b11: partial_product_bw[i] <= $signed(b_neg);\n endcase\n end\n else\n partial_product_bw[i] <= 0;\n end\n end \nendgenerate\n\nendmodule\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_mac_based/top.v", "`timescale 1ns / 1ps\nmodule top #\n(\n parameter N = 8, //CHANGE\n parameter WIDTH = 8, \n parameter ACC_WIDTH = 2*WIDTH + $clog2(N) \n)\n(\n input wire rst_n ,\n input wire clk ,\n input wire [N*N*WIDTH-1 :0] A ,\n input wire [N*N*WIDTH-1 :0] B ,\n output wire [N*N*ACC_WIDTH-1 :0] result \n);\n\nreg [N*N*WIDTH-1 :0] A_reg ;\nreg [N*N*WIDTH-1 :0] B_reg ;\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n A_reg<={(N*N*WIDTH){1'b0}};\n B_reg<={(N*N*WIDTH){1'b0}};\n end\n else begin\n A_reg<=A;\n B_reg<=B;\n end\nend\n\n\nwire signed [WIDTH-1:0] d_x [0:N-1][0:N-1][0:N-1];\nwire signed [ACC_WIDTH-1:0] d_y [0:N-1][0:N-1][0:N-1];\nwire signed [WIDTH-1:0] d_z [0:N-1][0:N-1][0:N-1];\n\n\n genvar x, y, z;\n generate\n for (z = 0; z < N; z = z + 1 ) begin\n for(x = 0; x < N; x = x + 1) begin\n for (y = 0; y < N; y = y + 1 ) begin\n if(z==0) begin\n if(x==0) begin\n if(y==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE //(1)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p ({ACC_WIDTH{1'b0}} ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n ); \n end\n else if(y==N-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(3)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (result[N*ACC_WIDTH*z+(x+1)*ACC_WIDTH-1 : ACC_WIDTH*N*z+x*ACC_WIDTH] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(2)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n );\n end\n end\n else begin\n if(y==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE //(6)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p ({ACC_WIDTH{1'b0}} ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n ); \n end\n else if(y==N-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(5)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (result[N*ACC_WIDTH*z+(x+1)*ACC_WIDTH-1 : ACC_WIDTH*N*z+x*ACC_WIDTH] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(4)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n );\n end \n end\n end\n else begin\n if(x==0) begin\n if(y==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE //(7)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p ({ACC_WIDTH{1'b0}} ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n ); \n end\n else if(y==N-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(9)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (result[N*ACC_WIDTH*z+(x+1)*ACC_WIDTH-1 : ACC_WIDTH*N*z+x*ACC_WIDTH] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(8)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n );\n end\n end\n else begin\n if(y==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE //(10)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p ({ACC_WIDTH{1'b0}} ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n ); \n end\n else if(y==N-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(12)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (result[N*ACC_WIDTH*z+(x+1)*ACC_WIDTH-1 : ACC_WIDTH*N*z+x*ACC_WIDTH] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(11)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n );\n end \n end\n end\n end\n end\n end\n endgenerate\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT3_OPT4C/pe/pe.v", "module pe #(\n parameter ACC_WIDTH = 26 //due to the same bit-weight reduction\n)(\n input clk,\n input rst_n,\n input clr,\n input wire [1:0] encoder_position_ins,\n input wire [7:0] operand_b_ins,\n output wire [51:0] result\n);\n\nwire signed [ACC_WIDTH-1:0] sum;\nwire signed [ACC_WIDTH-1:0] carry;\nwire signed [ACC_WIDTH-1:0] sum_input;\nwire signed [ACC_WIDTH-1:0] carry_input;\nreg signed [ACC_WIDTH-1:0] acc_sum;\nreg signed [ACC_WIDTH-1:0] acc_carry;\nreg [1:0] encoder_position;\nreg signed [7:0] operand_b;\n\n\nwire signed [8:0] b;\nwire signed [8:0] b_2;\nwire signed [8:0] neg_b;\nwire signed [9:0] neg_b_2;\nreg signed [9:0] mux_select_b;\nwire signed [ACC_WIDTH-1:0] mux_extend_b;\nwire [3*ACC_WIDTH-1:0] csa_input;\n\nassign b = $signed(operand_b);\nassign b_2 = {operand_b,1'b0};\nassign neg_b = ~b + 1'b1;\nassign neg_b_2 = {neg_b,1'b0};\nassign mux_extend_b = mux_select_b;\nassign sum_input = !clr ? 0 : acc_sum;\nassign carry_input = !clr ? 0 : acc_carry;\nassign csa_input = {mux_extend_b,sum_input,carry_input};\n\nalways @(*) begin\n case (encoder_position)\n 2'd0: mux_select_b = $signed(neg_b_2);\n 2'd1: mux_select_b = $signed(b);\n 2'd2: mux_select_b = $signed(b_2);\n 2'd3: mux_select_b = $signed(neg_b);\n endcase\nend\n\nDW02_tree #(3,ACC_WIDTH, 1)\n U1 ( .INPUT(csa_input), .OUT0(sum), .OUT1(carry) );\n\n always @(posedge clk or negedge rst_n) begin\n\tif (!rst_n) begin\n encoder_position <=0;\n operand_b <=0;\n\tend\n\telse begin\n encoder_position <= encoder_position_ins;\n operand_b <= operand_b_ins;\n\tend\nend\n\nalways @(posedge clk) begin\n acc_sum <= sum ;\n acc_carry <= carry;\nend\n\nassign result = {acc_sum,acc_carry};\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT2/top_tpe.sv", "module top_tpe #(\n parameter N = 32,\n localparam RESULT_WIDTH = 20\n)(\n \n input clk,\n input [127:0] operand_a,\n input weight_wen,\n input [8*N-1:0] weight_din,\n output [RESULT_WIDTH*N-1:0] result\n\n);\n\nwire [3:0] bit_enable [0:15];\nwire [7:0] partial_product_select [0:15];\nwire [3:0] bit_enable_pip [0:N-1][0:15];\nwire [7:0] partial_product_select_pip [0:N-1][0:15];\n\nvector_encoder encoder(\n .clk(clk),\n .operand_a(operand_a),\n .bit_enable(bit_enable),\n .partial_product_select(partial_product_select)\n);\n\ngenvar i;\ngenerate \n for (i = 0 ; i < N ; i = i + 1) begin\n if(i == 0) begin\n top_pe_tile pe_tile(\n .clk(clk),\n .weight_wen(weight_wen),\n .weight_din(weight_din[8*(i+1)-1:8*i]),\n .bit_enable(bit_enable),\n .partial_product_select(partial_product_select),\n .result(result[RESULT_WIDTH*(i+1)-1:RESULT_WIDTH*i]),\n .bit_enable_pip(bit_enable_pip[i]),\n .partial_product_select_pip(partial_product_select_pip[i])\n );\n end\n else begin\n top_pe_tile pe_tile(\n .clk(clk),\n .weight_wen(weight_wen),\n .weight_din(weight_din[8*(i+1)-1:8*i]),\n .bit_enable(bit_enable_pip[i-1]),\n .partial_product_select(partial_product_select_pip[i-1]),\n .result(result[RESULT_WIDTH*(i+1)-1:RESULT_WIDTH*i]),\n .bit_enable_pip(bit_enable_pip[i]),\n .partial_product_select_pip(partial_product_select_pip[i])\n );\n end\n end\nendgenerate\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT3_OPT4C/array/top_pe_column.v", "module top_pe_column #(\n parameter N = 32,\n parameter ACC_WIDTH = 26\n\n)(\n input clk,\n input rst_n,\n input clr,\n input [7:0] en_multiplicand, // operand a\n input [3:0] sign_en_multiplicand,\n input encode_valid,\n input [8*N-1:0] operand_b, \n output [1:0] position, // to prefetch operand b \n output [2:0] cal_cycle, // to prefetch operand a \n output [52*N-1:0] pe_result \n);\n\nwire [1:0] partial_product_index;\n\ngenvar i;\nsparse_encoder sp_encoder(\n .clk(clk),\n .rst_n(rst_n),\n .en_multiplicand(en_multiplicand),\n .sign_en_multiplicand(sign_en_multiplicand),\n .encode_valid(encode_valid),\n .partial_product_index(partial_product_index), // to sparse_pe generate partial product\n .position_0(position), // to prefetch operand b\n .cal_cycle(cal_cycle) // to prefetch operand a \n);\n\ngenerate\nfor (i = 0 ; i < N ; i = i + 1) begin\n pe #(\n .ACC_WIDTH(26)\n ) sparse_pe (\n .clk(clk),\n .rst_n(rst_n),\n .clr(clr),\n .encoder_position_ins(partial_product_index),\n .operand_b_ins(operand_b[8*(i+1)-1:8*i]),\n .result(pe_result[52*(i+1)-1:52*i])\n );\nend\nendgenerate\n\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/inv_conveter_8.v", "// 取反 加1 （-1*A、-2*A 都要进行取反加1）\nmodule inv_converter_8(\n input wire [7:0] data_i ,\n output wire[8:0] inv_o \n );\n \n wire [5:0] wire_cout ; \n wire not_o ; \n\n assign inv_o[0] = data_i[0];\n \n inv_unit inv_unit_bit1(\n .a (data_i[1] ),\n .b (data_i[0] ),\n .xor_o (inv_o[1] ), \n .or_o (wire_cout[0] ) \n );\n \n genvar i;\n generate \n for(i=2;i<=5;i=i+1) begin\n inv_unit inv_unit_inst(\n .a (data_i[i] ),\n .b (wire_cout[i-2] ),\n .xor_o (inv_o[i] ), \n .or_o (wire_cout[i-1] ) \n );\n end\n endgenerate\n \n inv_unit_nor_out inv_unit_nor_out_inst_6(\n .a (data_i[6] ),\n .b (wire_cout[4] ),\n .xor_o (inv_o[6] ), \n .nor_o (wire_cout[5] ) \n );\n \n inv_unit_nor_out inv_unit_nor_out_inst_7(\n .a (data_i[7] ),\n .b (not_o ), \n .xor_o (inv_o[7] ), \n .nor_o ( ) \n );\n \n \n\n assign not_o = ~wire_cout[5] ;\n \n\n assign inv_o[8] = ~(wire_cout[5] | data_i[7]);\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/inv_conveter_8.v", "// 取反 加1 （-1*A、-2*A 都要进行取反加1）\nmodule inv_converter_8(\n input wire [7:0] data_i ,\n output wire[8:0] inv_o \n );\n \n wire [5:0] wire_cout ; \n wire not_o ; \n\n assign inv_o[0] = data_i[0];\n \n inv_unit inv_unit_bit1(\n .a (data_i[1] ),\n .b (data_i[0] ),\n .xor_o (inv_o[1] ), \n .or_o (wire_cout[0] ) \n );\n \n genvar i;\n generate \n for(i=2;i<=5;i=i+1) begin\n inv_unit inv_unit_inst(\n .a (data_i[i] ),\n .b (wire_cout[i-2] ),\n .xor_o (inv_o[i] ), \n .or_o (wire_cout[i-1] ) \n );\n end\n endgenerate\n \n inv_unit_nor_out inv_unit_nor_out_inst_6(\n .a (data_i[6] ),\n .b (wire_cout[4] ),\n .xor_o (inv_o[6] ), \n .nor_o (wire_cout[5] ) \n );\n \n inv_unit_nor_out inv_unit_nor_out_inst_7(\n .a (data_i[7] ),\n .b (not_o ), \n .xor_o (inv_o[7] ), \n .nor_o ( ) \n );\n \n \n\n assign not_o = ~wire_cout[5] ;\n \n\n assign inv_o[8] = ~(wire_cout[5] | data_i[7]);\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/inv_conveter_8.v", "// 取反 加1 （-1*A、-2*A 都要进行取反加1）\nmodule inv_converter_8(\n input wire [7:0] data_i ,\n output wire[8:0] inv_o \n );\n \n wire [5:0] wire_cout ; \n wire not_o ; \n\n assign inv_o[0] = data_i[0];\n \n inv_unit inv_unit_bit1(\n .a (data_i[1] ),\n .b (data_i[0] ),\n .xor_o (inv_o[1] ), \n .or_o (wire_cout[0] ) \n );\n \n genvar i;\n generate \n for(i=2;i<=5;i=i+1) begin\n inv_unit inv_unit_inst(\n .a (data_i[i] ),\n .b (wire_cout[i-2] ),\n .xor_o (inv_o[i] ), \n .or_o (wire_cout[i-1] ) \n );\n end\n endgenerate\n \n inv_unit_nor_out inv_unit_nor_out_inst_6(\n .a (data_i[6] ),\n .b (wire_cout[4] ),\n .xor_o (inv_o[6] ), \n .nor_o (wire_cout[5] ) \n );\n \n inv_unit_nor_out inv_unit_nor_out_inst_7(\n .a (data_i[7] ),\n .b (not_o ), \n .xor_o (inv_o[7] ), \n .nor_o ( ) \n );\n \n \n\n assign not_o = ~wire_cout[5] ;\n \n\n assign inv_o[8] = ~(wire_cout[5] | data_i[7]);\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/PE.v", "// b = w * a\nmodule PE #\n(\n parameter WIDTH = 8,\n parameter ACC_WIDTH = 24\n)\n(\n input wire rst_n ,\n input wire clk ,\n input wire weight_wen ,\n input [WIDTH-1 :0] weight_din ,\n input wire signed [WIDTH-1 :0] a ,\n input wire signed [2*ACC_WIDTH-1 :0] partial_result , \n\n output reg signed [WIDTH-1 :0] col ,\n output reg signed [2*ACC_WIDTH-1 :0] row \n);\n\n\nreg signed [WIDTH-1 :0] weight;\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n weight <= 0;\n end\n else begin\n if(weight_wen) begin\n weight <= weight_din; \n end\n else begin\n weight <= weight;\n end\n end\nend\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n col <= 0;\n end\n else begin\n if(weight_wen) begin\n col <= weight_din; \n end\n else begin\n col <= a;\n end\n end\nend\n\nwire [ACC_WIDTH-1:0] acc_sum;\nwire [ACC_WIDTH-1:0] acc_carry;\nalways @(*) begin\n if(!rst_n) begin\n row <= 0;\n end\n else begin\n row <= {acc_sum, acc_carry}; // partial_result + weight * a;\n end\nend\nopt1_mac #(\n .ACC_WIDTH(ACC_WIDTH),\n .INPUT_PIP(0)\n) opt1_mac_test (\n .clk(clk),\n .rst_n(rst_n),\n .operand_a_in(a), \n .operand_b_in(weight), \n .partial_result(partial_result),\n .acc_sum(acc_sum),\n .acc_carry(acc_carry)\n);\n\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/PE.v", "`timescale 1ns / 1ps\n\n// b = w * a\nmodule PE #\n(\n parameter WIDTH = 8,\n parameter ACC_WIDTH = 24\n)\n(\n input wire rst_n,\n input wire clk,\n input wire signed [WIDTH-1 :0] i_z_a,\n input wire signed [WIDTH-1 :0] i_x_b,\n input wire signed [2*ACC_WIDTH-1 :0] i_y_p,\n\n output reg signed [WIDTH-1 :0] o_z_a,\n output reg signed [WIDTH-1 :0] o_x_b,\n output reg signed [2*ACC_WIDTH-1 :0] o_y_p\n);\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n o_z_a <= 0;\n o_x_b <= 0;\n end\n else begin\n o_z_a <= i_z_a; \n o_x_b <= i_x_b; \n end\nend\n\nwire [ACC_WIDTH-1:0] acc_sum;\nwire [ACC_WIDTH-1:0] acc_carry;\nalways @(*) begin\n if(!rst_n) begin\n o_y_p = 0;\n end\n else begin\n o_y_p = {acc_sum, acc_carry}; // partial_result + weight * a;\n end\nend\nopt1_mac #(\n .ACC_WIDTH(ACC_WIDTH),\n .INPUT_PIP(0)\n) opt1_mac_test (\n .clk(clk),\n .rst_n(rst_n),\n .operand_a_in(i_z_a), \n .operand_b_in(i_x_b), \n .partial_result(i_y_p),\n .acc_sum(acc_sum),\n .acc_carry(acc_carry)\n);\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/inv_conveter_8.v", "module inv_converter_8(\n input wire [7:0] data_i ,\n output wire[8:0] inv_o \n );\n \n wire [5:0] wire_cout ; \n wire not_o ; \n\n assign inv_o[0] = data_i[0];\n \n inv_unit inv_unit_bit1(\n .a (data_i[1] ),\n .b (data_i[0] ),\n .xor_o (inv_o[1] ), \n .or_o (wire_cout[0] ) \n );\n \n genvar i;\n generate \n for(i=2;i<=5;i=i+1) begin\n inv_unit inv_unit_inst(\n .a (data_i[i] ),\n .b (wire_cout[i-2] ),\n .xor_o (inv_o[i] ), \n .or_o (wire_cout[i-1] ) \n );\n end\n endgenerate\n \n inv_unit_nor_out inv_unit_nor_out_inst_6(\n .a (data_i[6] ),\n .b (wire_cout[4] ),\n .xor_o (inv_o[6] ), \n .nor_o (wire_cout[5] ) \n );\n \n inv_unit_nor_out inv_unit_nor_out_inst_7(\n .a (data_i[7] ),\n .b (not_o ), \n .xor_o (inv_o[7] ), \n .nor_o ( ) \n );\n \n \n\n assign not_o = ~wire_cout[5] ;\n \n\n assign inv_o[8] = ~(wire_cout[5] | data_i[7]);\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/booth_partial_product_generator.v", "module booth_partial_product_generator(\n input wire [2:0] operand_slice_a, \n input wire [7:0] operand_b, \n input wire [8:0] operand_b_neg, \n output wire [9:0] pp_out \n );\n \n wire [8:0] pp_source ;\n //----------------------------------------------------\n //| pp | flag_2x | flag_s1 | flag_s2 |\n //----------------------------------------------------\n //| operand_b | 0 | 0 | 1 |\n //| -operand_b | 0 | 1 | 0 |\n //| 2operand_b | 1 | 0 | 1 | \n //| -2operand_b | 1 | 1 | 0 |\n //| 0 | x | 0 | 0 | \n //----------------------------------------------------\n wire not_c2 ; \n wire c1_and_c0 ; \n wire c1_nor_c0 ; \n wire nor_o2 ; \n \n wire flag_2x ;\n wire flag_s1 ;\n wire flag_s2 ;\n \n assign not_c2 = ~operand_slice_a[2] ;\n assign c1_and_c0 = operand_slice_a[1] & operand_slice_a[0] ;\n assign c1_nor_c0 = ~(operand_slice_a[1] | operand_slice_a[0]) ;\n assign nor_o2 = ~(c1_and_c0 | c1_nor_c0) ;\n \n assign flag_2x = ~nor_o2 ;\n assign flag_s1 = ~(not_c2 | c1_and_c0) ;\n assign flag_s2 = ~(operand_slice_a[2] | c1_nor_c0) ;\n \n wire flag_not_2x = nor_o2; \n \n assign pp_source = (({{operand_b[7]}, operand_b} & {9{flag_s2}}) | (operand_b_neg & {9{flag_s1}}));\n assign pp_out[0] = (!flag_2x & pp_source[0]);\n assign pp_out[8:1] = (({8{flag_2x}} & pp_source[7:0]) | ({8{flag_not_2x}} & pp_source[8:1]));\n assign pp_out[9] = pp_source[8];\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/booth_partial_product_generator_pp1.v", "module booth_partial_product_generator_pp1(\n input wire [1:0] operand_slice_a, \n input wire [7:0] operand_b, \n input wire [8:0] operand_b_neg, \n output wire [9:0] pp_out \n );\n \n wire [8:0] pp_source;\n wire not_code0;\n //----------------------------------------------------\n //| pp | flag_2x | flag_s1 | flag_s2 |\n //----------------------------------------------------\n //| operand_b | 0 | 0 | 1 |\n //| -operand_b | 0 | 1 | 0 |\n //| 2operand_b | 1 | 0 | 1 | \n //| -2operand_b | 1 | 1 | 0 |\n //| 0 | x | 0 | 0 | \n //----------------------------------------------------\n \n //----------------------------------------------------\n //operand_slice_a[1] operand_slice_a[0] operand_slice_a[-1] | pp \n //----------------------------------------------------\n // 0 0 0 | 0 \n // 0 1 0 | operand_b \n // 1 0 0 | 2operand_b \n // 1 1 0 | -operand_b \n //----------------------------------------------------\n \n wire flag_2x;\n wire flag_s1;\n wire flag_s2; \n assign not_code0 = ~operand_slice_a[0]; \n assign flag_2x = not_code0; \n assign flag_s1 = operand_slice_a[1]; // 取反\n assign flag_s2 = ~(operand_slice_a[1] | not_code0); // A\n wire flag_not_2x = operand_slice_a[0];\n assign pp_source = (({{operand_b[7]}, operand_b} & {9{flag_s2}}) | (operand_b_neg & {9{flag_s1}})); // A or ~A or 0\n assign pp_out[0] = (!flag_2x & pp_source[0]);// x2 (<<1) pp_out[0]=0\n assign pp_out[8:1] = (({8{flag_2x}} & pp_source[7:0]) | ({8{flag_not_2x}} & pp_source[8:1]));\n assign pp_out[9] = pp_source[8];\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/booth_partial_product_generator_pp1.v", "module booth_partial_product_generator_pp1(\n input wire [1:0] operand_slice_a, \n input wire [7:0] operand_b, \n input wire [8:0] operand_b_neg, \n output wire [9:0] pp_out \n );\n \n wire [8:0] pp_source;\n wire not_code0;\n //----------------------------------------------------\n //| pp | flag_2x | flag_s1 | flag_s2 |\n //----------------------------------------------------\n //| operand_b | 0 | 0 | 1 |\n //| -operand_b | 0 | 1 | 0 |\n //| 2operand_b | 1 | 0 | 1 | \n //| -2operand_b | 1 | 1 | 0 |\n //| 0 | x | 0 | 0 | \n //----------------------------------------------------\n \n //----------------------------------------------------\n //operand_slice_a[1] operand_slice_a[0] operand_slice_a[-1] | pp \n //----------------------------------------------------\n // 0 0 0 | 0 \n // 0 1 0 | operand_b \n // 1 0 0 | 2operand_b \n // 1 1 0 | -operand_b \n //----------------------------------------------------\n \n wire flag_2x;\n wire flag_s1;\n wire flag_s2; \n assign not_code0 = ~operand_slice_a[0]; \n assign flag_2x = not_code0; \n assign flag_s1 = operand_slice_a[1]; // 取反\n assign flag_s2 = ~(operand_slice_a[1] | not_code0); // A\n wire flag_not_2x = operand_slice_a[0];\n assign pp_source = (({{operand_b[7]}, operand_b} & {9{flag_s2}}) | (operand_b_neg & {9{flag_s1}})); // A or ~A or 0\n assign pp_out[0] = (!flag_2x & pp_source[0]);// x2 (<<1) pp_out[0]=0\n assign pp_out[8:1] = (({8{flag_2x}} & pp_source[7:0]) | ({8{flag_not_2x}} & pp_source[8:1]));\n assign pp_out[9] = pp_source[8];\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/booth_partial_product_generator_pp1.v", "module booth_partial_product_generator_pp1(\n input wire [1:0] operand_slice_a, \n input wire [7:0] operand_b, \n input wire [8:0] operand_b_neg, \n output wire [9:0] pp_out \n );\n \n wire [8:0] pp_source;\n wire not_code0;\n //----------------------------------------------------\n //| pp | flag_2x | flag_s1 | flag_s2 |\n //----------------------------------------------------\n //| operand_b | 0 | 0 | 1 |\n //| -operand_b | 0 | 1 | 0 |\n //| 2operand_b | 1 | 0 | 1 | \n //| -2operand_b | 1 | 1 | 0 |\n //| 0 | x | 0 | 0 | \n //----------------------------------------------------\n \n //----------------------------------------------------\n //operand_slice_a[1] operand_slice_a[0] operand_slice_a[-1] | pp \n //----------------------------------------------------\n // 0 0 0 | 0 \n // 0 1 0 | operand_b \n // 1 0 0 | 2operand_b \n // 1 1 0 | -operand_b \n //----------------------------------------------------\n \n wire flag_2x;\n wire flag_s1;\n wire flag_s2; \n assign not_code0 = ~operand_slice_a[0]; \n assign flag_2x = not_code0; \n assign flag_s1 = operand_slice_a[1]; // 取反\n assign flag_s2 = ~(operand_slice_a[1] | not_code0); // A\n wire flag_not_2x = operand_slice_a[0];\n assign pp_source = (({{operand_b[7]}, operand_b} & {9{flag_s2}}) | (operand_b_neg & {9{flag_s1}})); // A or ~A or 0\n assign pp_out[0] = (!flag_2x & pp_source[0]);// x2 (<<1) pp_out[0]=0\n assign pp_out[8:1] = (({8{flag_2x}} & pp_source[7:0]) | ({8{flag_not_2x}} & pp_source[8:1]));\n assign pp_out[9] = pp_source[8];\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/booth_partial_product_generator.v", "module booth_partial_product_generator(\n input wire [2:0] operand_slice_a, \n input wire [7:0] operand_b, \n input wire [8:0] operand_b_neg, \n output wire [9:0] pp_out \n );\n \n wire [8:0] pp_source ;\n //----------------------------------------------------\n //| pp | flag_2x | flag_s1 | flag_s2 |\n //----------------------------------------------------\n //| operand_b | 0 | 0 | 1 |\n //| -operand_b | 0 | 1 | 0 |\n //| 2operand_b | 1 | 0 | 1 | \n //| -2operand_b | 1 | 1 | 0 |\n //| 0 | x | 0 | 0 | \n //----------------------------------------------------\n \n //----------------------------------------------------\n //operand_slice_a[1] operand_slice_a[0] operand_slice_a[-1] | pp \n //----------------------------------------------------\n // 0 0 0 | 0 \n // 0 0 1 | operand_b \n // 0 1 0 | operand_b \n // 0 1 1 | 2operand_b \n // 1 0 0 | -2operand_b \n // 1 0 1 | -operand_b \n // 1 1 0 | -operand_b \n // 1 1 1 | 0 \n //----------------------------------------------------\n \n wire not_c2 ; \n wire c1_and_c0 ; \n wire c1_nor_c0 ; \n wire nor_o2 ; \n \n wire flag_2x ;\n wire flag_s1 ;\n wire flag_s2 ;\n \n assign not_c2 = ~operand_slice_a[2] ;\n assign c1_and_c0 = operand_slice_a[1] & operand_slice_a[0] ;\n assign c1_nor_c0 = ~(operand_slice_a[1] | operand_slice_a[0]) ;\n assign nor_o2 = ~(c1_and_c0 | c1_nor_c0) ;\n \n assign flag_2x = ~nor_o2 ;\n assign flag_s1 = ~(not_c2 | c1_and_c0) ;\n assign flag_s2 = ~(operand_slice_a[2] | c1_nor_c0) ;\n \n wire flag_not_2x = nor_o2; \n assign pp_source = (({{operand_b[7]}, operand_b} & {9{flag_s2}}) | (operand_b_neg & {9{flag_s1}}));\n assign pp_out[0] = (!flag_2x & pp_source[0]);\n assign pp_out[8:1] = (({8{flag_2x}} & pp_source[7:0]) | ({8{flag_not_2x}} & pp_source[8:1]));\n assign pp_out[9] = pp_source[8];\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/booth_partial_product_generator.v", "module booth_partial_product_generator(\n input wire [2:0] operand_slice_a, \n input wire [7:0] operand_b, \n input wire [8:0] operand_b_neg, \n output wire [9:0] pp_out \n );\n \n wire [8:0] pp_source ;\n //----------------------------------------------------\n //| pp | flag_2x | flag_s1 | flag_s2 |\n //----------------------------------------------------\n //| operand_b | 0 | 0 | 1 |\n //| -operand_b | 0 | 1 | 0 |\n //| 2operand_b | 1 | 0 | 1 | \n //| -2operand_b | 1 | 1 | 0 |\n //| 0 | x | 0 | 0 | \n //----------------------------------------------------\n \n //----------------------------------------------------\n //operand_slice_a[1] operand_slice_a[0] operand_slice_a[-1] | pp \n //----------------------------------------------------\n // 0 0 0 | 0 \n // 0 0 1 | operand_b \n // 0 1 0 | operand_b \n // 0 1 1 | 2operand_b \n // 1 0 0 | -2operand_b \n // 1 0 1 | -operand_b \n // 1 1 0 | -operand_b \n // 1 1 1 | 0 \n //----------------------------------------------------\n \n wire not_c2 ; \n wire c1_and_c0 ; \n wire c1_nor_c0 ; \n wire nor_o2 ; \n \n wire flag_2x ;\n wire flag_s1 ;\n wire flag_s2 ;\n \n assign not_c2 = ~operand_slice_a[2] ;\n assign c1_and_c0 = operand_slice_a[1] & operand_slice_a[0] ;\n assign c1_nor_c0 = ~(operand_slice_a[1] | operand_slice_a[0]) ;\n assign nor_o2 = ~(c1_and_c0 | c1_nor_c0) ;\n \n assign flag_2x = ~nor_o2 ;\n assign flag_s1 = ~(not_c2 | c1_and_c0) ;\n assign flag_s2 = ~(operand_slice_a[2] | c1_nor_c0) ;\n \n wire flag_not_2x = nor_o2; \n assign pp_source = (({{operand_b[7]}, operand_b} & {9{flag_s2}}) | (operand_b_neg & {9{flag_s1}}));\n assign pp_out[0] = (!flag_2x & pp_source[0]);\n assign pp_out[8:1] = (({8{flag_2x}} & pp_source[7:0]) | ({8{flag_not_2x}} & pp_source[8:1]));\n assign pp_out[9] = pp_source[8];\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/booth_partial_product_generator.v", "module booth_partial_product_generator(\n input wire [2:0] operand_slice_a, \n input wire [7:0] operand_b, \n input wire [8:0] operand_b_neg, \n output wire [9:0] pp_out \n );\n \n wire [8:0] pp_source ;\n //----------------------------------------------------\n //| pp | flag_2x | flag_s1 | flag_s2 |\n //----------------------------------------------------\n //| operand_b | 0 | 0 | 1 |\n //| -operand_b | 0 | 1 | 0 |\n //| 2operand_b | 1 | 0 | 1 | \n //| -2operand_b | 1 | 1 | 0 |\n //| 0 | x | 0 | 0 | \n //----------------------------------------------------\n \n //----------------------------------------------------\n //operand_slice_a[1] operand_slice_a[0] operand_slice_a[-1] | pp \n //----------------------------------------------------\n // 0 0 0 | 0 \n // 0 0 1 | operand_b \n // 0 1 0 | operand_b \n // 0 1 1 | 2operand_b \n // 1 0 0 | -2operand_b \n // 1 0 1 | -operand_b \n // 1 1 0 | -operand_b \n // 1 1 1 | 0 \n //----------------------------------------------------\n \n wire not_c2 ; \n wire c1_and_c0 ; \n wire c1_nor_c0 ; \n wire nor_o2 ; \n \n wire flag_2x ;\n wire flag_s1 ;\n wire flag_s2 ;\n \n assign not_c2 = ~operand_slice_a[2] ;\n assign c1_and_c0 = operand_slice_a[1] & operand_slice_a[0] ;\n assign c1_nor_c0 = ~(operand_slice_a[1] | operand_slice_a[0]) ;\n assign nor_o2 = ~(c1_and_c0 | c1_nor_c0) ;\n \n assign flag_2x = ~nor_o2 ;\n assign flag_s1 = ~(not_c2 | c1_and_c0) ;\n assign flag_s2 = ~(operand_slice_a[2] | c1_nor_c0) ;\n \n wire flag_not_2x = nor_o2; \n assign pp_source = (({{operand_b[7]}, operand_b} & {9{flag_s2}}) | (operand_b_neg & {9{flag_s1}}));\n assign pp_out[0] = (!flag_2x & pp_source[0]);\n assign pp_out[8:1] = (({8{flag_2x}} & pp_source[7:0]) | ({8{flag_not_2x}} & pp_source[8:1]));\n assign pp_out[9] = pp_source[8];\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/pe.v", "module PE #\n(\n parameter WIDTH = 8,\n parameter ACC_WIDTH = 32\n)\n(\n input wire rst_n,\n input wire clk,\n input wire signed [WIDTH-1 :0] a,\n input wire signed [WIDTH-1 :0] b,\n input wire clc, // clean_result_cache\n\n output reg signed [WIDTH-1 :0] row,\n output reg signed [WIDTH-1 :0] col,\n output signed [2*ACC_WIDTH-1 :0] result\n);\n\n\nwire [ACC_WIDTH-1:0] acc_sum;\nwire [ACC_WIDTH-1:0] acc_carry;\nopt1_mac #(\n .ACC_WIDTH(ACC_WIDTH),\n .INPUT_PIP(0)\n) opt1_mac_test (\n .clk(clk),\n .rst_n(rst_n),\n .operand_a_in(a), \n .operand_b_in(b), \n .clc(clc), // input wire clean_result_cache\n .acc_sum(acc_sum),\n .acc_carry(acc_carry)\n);\nassign result = {acc_sum, acc_carry};\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n row <= 0;\n col <= 0;\n end\n else begin\n row <= a;\n col <= b;\n end\nend\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/booth_partial_product_generator_pp1.v", "module booth_partial_product_generator_pp1(\n input wire [1:0] operand_slice_a, \n input wire [7:0] operand_b, \n input wire [8:0] operand_b_neg, \n output wire [9:0] pp_out \n );\n \n wire [8:0] pp_source;\n wire not_code0;\n //----------------------------------------------------\n //| pp | flag_2x | flag_s1 | flag_s2 |\n //----------------------------------------------------\n //| operand_b | 0 | 0 | 1 |\n //| -operand_b | 0 | 1 | 0 |\n //| 2operand_b | 1 | 0 | 1 | \n //| -2operand_b | 1 | 1 | 0 |\n //| 0 | x | 0 | 0 | \n //----------------------------------------------------\n wire flag_2x;\n wire flag_s1;\n wire flag_s2; \n assign not_code0 = ~operand_slice_a[0]; \n assign flag_2x = not_code0; \n assign flag_s1 = operand_slice_a[1]; \n assign flag_s2 = ~(operand_slice_a[1] | not_code0); \n wire flag_not_2x = operand_slice_a[0];\n assign pp_source = (({{operand_b[7]}, operand_b} & {9{flag_s2}}) | (operand_b_neg & {9{flag_s1}}));\n assign pp_out[0] = (!flag_2x & pp_source[0]);\n assign pp_out[8:1] = (({8{flag_2x}} & pp_source[7:0]) | ({8{flag_not_2x}} & pp_source[8:1]));\n assign pp_out[9] = pp_source[8];\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_mac_based/get_pipline_mulwidth.v", "module get_pipeline_mulwidth #(\n parameter N = 4,\n parameter WIDTH = 8 \n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] signal,\n output wire [WIDTH-1:0] pipeline_signal\n);\n\n\n reg [WIDTH-1:0] pipeline_regs [N-1:0];\n\n\n genvar i;\n generate\n for (i = 0; i < N; i = i + 1) begin : pipeline_stage\n always @(posedge clk) begin\n if(~rst_n) \n pipeline_regs[i] <= 0;\n else begin\n if (i == 0) begin\n pipeline_regs[i] <= signal; \n end else begin\n pipeline_regs[i] <= pipeline_regs[i-1]; \n end\n end\n end\n end\n endgenerate\n\n\n assign pipeline_signal = pipeline_regs[N-1];\n\nendmodule\n\n\n// // 实例化 get_pipeline_mulwidth 模块\n// get_pipeline_mulwidth #(\n// .N(4), // 设置流水线深度为 4\n// .WIDTH(8) // 设置信号宽度为 8 位\n// ) pipeline_inst (\n// .clk(clk), // 连接时钟信号\n// .rst_n(rst_n), // 连接复位信号\n// .signal(input_signal), // 连接输入信号\n// .pipeline_signal(output_signal) // 连接输出信号\n// );\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_mac_based/get_pipline_mulwidth.v", "module get_pipeline_mulwidth #(\n parameter N = 4,\n parameter WIDTH = 8 \n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] signal,\n output wire [WIDTH-1:0] pipeline_signal\n);\n\n\n reg [WIDTH-1:0] pipeline_regs [N-1:0];\n\n\n genvar i;\n generate\n for (i = 0; i < N; i = i + 1) begin : pipeline_stage\n always @(posedge clk) begin\n if(~rst_n) \n pipeline_regs[i] <= 0;\n else begin\n if (i == 0) begin\n pipeline_regs[i] <= signal; \n end else begin\n pipeline_regs[i] <= pipeline_regs[i-1]; \n end\n end\n end\n end\n endgenerate\n\n\n assign pipeline_signal = pipeline_regs[N-1];\n\nendmodule\n\n\n// // 实例化 get_pipeline_mulwidth 模块\n// get_pipeline_mulwidth #(\n// .N(4), // 设置流水线深度为 4\n// .WIDTH(8) // 设置信号宽度为 8 位\n// ) pipeline_inst (\n// .clk(clk), // 连接时钟信号\n// .rst_n(rst_n), // 连接复位信号\n// .signal(input_signal), // 连接输入信号\n// .pipeline_signal(output_signal) // 连接输出信号\n// );\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/get_pipline_mulwidth.v", "module get_pipeline_mulwidth #(\n parameter N = 4,\n parameter WIDTH = 8 \n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] signal,\n output wire [WIDTH-1:0] pipeline_signal\n);\n\n\n reg [WIDTH-1:0] pipeline_regs [N-1:0];\n\n\n genvar i;\n generate\n for (i = 0; i < N; i = i + 1) begin : pipeline_stage\n always @(posedge clk) begin\n if(~rst_n) \n pipeline_regs[i] <= 0;\n else begin\n if (i == 0) begin\n pipeline_regs[i] <= signal; \n end else begin\n pipeline_regs[i] <= pipeline_regs[i-1]; \n end\n end\n end\n end\n endgenerate\n\n\n assign pipeline_signal = pipeline_regs[N-1];\n\nendmodule\n\n\n// // 实例化 get_pipeline_mulwidth 模块\n// get_pipeline_mulwidth #(\n// .N(4), // 设置流水线深度为 4\n// .WIDTH(8) // 设置信号宽度为 8 位\n// ) pipeline_inst (\n// .clk(clk), // 连接时钟信号\n// .rst_n(rst_n), // 连接复位信号\n// .signal(input_signal), // 连接输入信号\n// .pipeline_signal(output_signal) // 连接输出信号\n// );\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/get_pipline_mulwidth.v", "module get_pipeline_mulwidth #(\n parameter N = 4,\n parameter WIDTH = 8 \n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] signal,\n output wire [WIDTH-1:0] pipeline_signal\n);\n\n\n reg [WIDTH-1:0] pipeline_regs [N-1:0];\n\n\n genvar i;\n generate\n for (i = 0; i < N; i = i + 1) begin : pipeline_stage\n always @(posedge clk) begin\n if(~rst_n) \n pipeline_regs[i] <= 0;\n else begin\n if (i == 0) begin\n pipeline_regs[i] <= signal; \n end else begin\n pipeline_regs[i] <= pipeline_regs[i-1]; \n end\n end\n end\n end\n endgenerate\n\n\n assign pipeline_signal = pipeline_regs[N-1];\n\nendmodule\n\n\n// // 实例化 get_pipeline_mulwidth 模块\n// get_pipeline_mulwidth #(\n// .N(4), // 设置流水线深度为 4\n// .WIDTH(8) // 设置信号宽度为 8 位\n// ) pipeline_inst (\n// .clk(clk), // 连接时钟信号\n// .rst_n(rst_n), // 连接复位信号\n// .signal(input_signal), // 连接输入信号\n// .pipeline_signal(output_signal) // 连接输出信号\n// );\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_mac_based/get_pipline_mulwidth.v", "module get_pipeline_mulwidth #(\n parameter N = 4,\n parameter WIDTH = 8 \n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] signal,\n output wire [WIDTH-1:0] pipeline_signal\n);\n\n\n reg [WIDTH-1:0] pipeline_regs [N-1:0];\n\n\n genvar i;\n generate\n for (i = 0; i < N; i = i + 1) begin : pipeline_stage\n always @(posedge clk) begin\n if(~rst_n) \n pipeline_regs[i] <= 0;\n else begin\n if (i == 0) begin\n pipeline_regs[i] <= signal; \n end else begin\n pipeline_regs[i] <= pipeline_regs[i-1]; \n end\n end\n end\n end\n endgenerate\n\n\n assign pipeline_signal = pipeline_regs[N-1];\n\nendmodule\n\n\n// // 实例化 get_pipeline_mulwidth 模块\n// get_pipeline_mulwidth #(\n// .N(4), // 设置流水线深度为 4\n// .WIDTH(8) // 设置信号宽度为 8 位\n// ) pipeline_inst (\n// .clk(clk), // 连接时钟信号\n// .rst_n(rst_n), // 连接复位信号\n// .signal(input_signal), // 连接输入信号\n// .pipeline_signal(output_signal) // 连接输出信号\n// );\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/get_pipline_mulwidth.v", "module get_pipeline_mulwidth #(\n parameter N = 4,\n parameter WIDTH = 8 \n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] signal,\n output wire [WIDTH-1:0] pipeline_signal\n);\n\n\n reg [WIDTH-1:0] pipeline_regs [N-1:0];\n\n\n genvar i;\n generate\n for (i = 0; i < N; i = i + 1) begin : pipeline_stage\n always @(posedge clk) begin\n if(~rst_n) \n pipeline_regs[i] <= 0;\n else begin\n if (i == 0) begin\n pipeline_regs[i] <= signal; \n end else begin\n pipeline_regs[i] <= pipeline_regs[i-1]; \n end\n end\n end\n end\n endgenerate\n\n\n assign pipeline_signal = pipeline_regs[N-1];\n\nendmodule\n\n\n// // 实例化 get_pipeline_mulwidth 模块\n// get_pipeline_mulwidth #(\n// .N(4), // 设置流水线深度为 4\n// .WIDTH(8) // 设置信号宽度为 8 位\n// ) pipeline_inst (\n// .clk(clk), // 连接时钟信号\n// .rst_n(rst_n), // 连接复位信号\n// .signal(input_signal), // 连接输入信号\n// .pipeline_signal(output_signal) // 连接输出信号\n// );\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_mac_based/PE.v", "// b = w * a\nmodule PE #\n(\n parameter WIDTH = 8,\n parameter ACC_WIDTH = 24\n)\n(\n input wire rst_n ,\n input wire clk ,\n input wire weight_wen ,\n input [WIDTH-1 :0] weight_din ,\n input wire signed [WIDTH-1 :0] a ,\n input wire signed [ACC_WIDTH-1 :0] partial_result , \n\n output reg signed [WIDTH-1 :0] col ,\n output reg signed [ACC_WIDTH-1 :0] row \n);\n\n\nreg signed [WIDTH-1 :0] weight;\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n weight <= 0;\n end\n else begin\n if(weight_wen) begin\n weight <= weight_din; \n end\n else begin\n weight <= weight;\n end\n end\nend\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n col <= 0;\n end\n else begin\n if(weight_wen) begin\n col <= weight_din; \n end\n else begin\n col <= a;\n end\n end\nend\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n row <= 0;\n end\n else begin\n row <= partial_result + weight * a;\n end\nend\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_mac_based/pe.v", "module PE #\n(\n parameter WIDTH = 8,\n parameter ACC_WIDTH = 32\n)\n(\n input wire rst_n,\n input wire clk,\n input wire signed [WIDTH-1 :0] a,\n input wire signed [WIDTH-1 :0] b,\n input wire clc, // clean_result_cache,\n\n output reg signed [WIDTH-1 :0] row,\n output reg signed [WIDTH-1 :0] col,\n output reg signed [ACC_WIDTH-1 :0] result\n);\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n result <= 0;\n end\n else begin\n if(clc)\n result <= 0;\n else\n result <= result + a * b ;\n end\nend\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n row <= 0;\n col <= 0;\n end\n else begin\n row <= a;\n col <= b;\n end\nend\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/mac_pe/mac.v", "module mac #\n(\n parameter WIDTH = 8,\n parameter ACC_WIDTH = 32\n)\n(\n input wire rst_n,\n input wire clk,\n input wire signed [WIDTH-1 :0] a,\n input wire signed [WIDTH-1 :0] b,\n output reg signed [ACC_WIDTH-1 :0] result\n);\n\nwire signed [15:0] result_p;\nreg signed [7:0] operand_a;\nreg signed [7:0] operand_b;\n\nassign result_p = $signed(operand_a) * $signed(operand_b) ;\n\nalways @(posedge clk) begin\n operand_a <= a;\n operand_b <= b;\nend\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n result <= 0;\n end\n else begin\n result <= result + $signed(result_p);\n end\nend\n\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT2/weight_rf.sv", "module weight_rf (\n input clk,\n input wen,\n input [7:0] din,\n output [7:0] weight [0:15]\n);\n\nreg [7:0] buffer [0:15];\n\nassign weight = buffer;\n\ngenvar i;\ngenerate\n for (i = 0; i < 16; i = i + 1) begin\n always @(posedge clk) begin\n if(wen) begin\n if (i==15)\n buffer[i] <= din;\n else \n buffer[i] <= buffer[i+1];\n end\n else\n buffer[i] <= buffer[i];\n end\n end\nendgenerate\n\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_mac_based/pe.v", "`timescale 1ns / 1ps\n\n// b = w * a\nmodule PE #\n(\n parameter WIDTH = 8,\n parameter ACC_WIDTH = 24\n)\n(\n input wire rst_n,\n input wire clk,\n input wire signed [WIDTH-1 :0] i_z_a,\n input wire signed [WIDTH-1 :0] i_x_b,\n input wire signed [ACC_WIDTH-1 :0] i_y_p,\n\n output reg signed [WIDTH-1 :0] o_z_a,\n output reg signed [WIDTH-1 :0] o_x_b,\n output reg signed [ACC_WIDTH-1 :0] o_y_p\n);\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n o_y_p <= 0;\n end\n else begin\n o_y_p <= i_y_p + i_z_a*i_x_b; \n end\nend\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n o_z_a <= 0;\n o_x_b <= 0;\n end\n else begin\n o_z_a <= i_z_a; \n o_x_b <= i_x_b; \n end\nend\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/booth_pp_gen.v", "module booth_pp_gen(\n input wire [7:0] operand_a, \n input wire [7:0] operand_b, \n output wire [9:0] pp1,\n output wire [9:0] pp2,\n output wire [9:0] pp3,\n output wire [9:0] pp4 \n );\n\n wire [1:0] operand_slice_a1 ;\n wire [2:0] operand_slice_a2 ;\n wire [2:0] operand_slice_a3 ;\n wire [2:0] operand_slice_a4 ;\n wire [8:0] operand_b_neg ;\n \n inv_converter_8 inv_converter_8_inst(\n .data_i (operand_b),\n .inv_o (operand_b_neg) \n );\n \n assign operand_slice_a1 = operand_a[1:0] ;\n assign operand_slice_a2 = operand_a[3:1] ;\n assign operand_slice_a3 = operand_a[5:3] ;\n assign operand_slice_a4 = operand_a[7:5] ;\n\n booth_partial_product_generator_pp1 ppg_1 (\n .operand_slice_a (operand_slice_a1), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp1) \n );\n\n booth_partial_product_generator ppg_2 (\n .operand_slice_a (operand_slice_a2), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp2) \n );\n\n booth_partial_product_generator ppg_3 (\n .operand_slice_a (operand_slice_a3), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp3) \n );\n\n booth_partial_product_generator ppg_4 (\n .operand_slice_a (operand_slice_a4), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp4) \n );\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/booth_pp_gen.v", "module booth_pp_gen(\n input wire [7:0] operand_a, \n input wire [7:0] operand_b, \n output wire [9:0] pp1,\n output wire [9:0] pp2,\n output wire [9:0] pp3,\n output wire [9:0] pp4 \n );\n\n wire [1:0] operand_slice_a1 ;\n wire [2:0] operand_slice_a2 ;\n wire [2:0] operand_slice_a3 ;\n wire [2:0] operand_slice_a4 ;\n wire [8:0] operand_b_neg ;\n \n inv_converter_8 inv_converter_8_inst(\n .data_i (operand_b),\n .inv_o (operand_b_neg) \n );\n \n assign operand_slice_a1 = operand_a[1:0] ;\n assign operand_slice_a2 = operand_a[3:1] ;\n assign operand_slice_a3 = operand_a[5:3] ;\n assign operand_slice_a4 = operand_a[7:5] ;\n\n booth_partial_product_generator_pp1 ppg_1 (\n .operand_slice_a (operand_slice_a1), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp1) \n );\n\n booth_partial_product_generator ppg_2 (\n .operand_slice_a (operand_slice_a2), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp2) \n );\n\n booth_partial_product_generator ppg_3 (\n .operand_slice_a (operand_slice_a3), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp3) \n );\n\n booth_partial_product_generator ppg_4 (\n .operand_slice_a (operand_slice_a4), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp4) \n );\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/booth_pp_gen.v", "module booth_pp_gen(\n input wire [7:0] operand_a, \n input wire [7:0] operand_b, \n output wire [9:0] pp1,\n output wire [9:0] pp2,\n output wire [9:0] pp3,\n output wire [9:0] pp4 \n );\n\n wire [1:0] operand_slice_a1 ;\n wire [2:0] operand_slice_a2 ;\n wire [2:0] operand_slice_a3 ;\n wire [2:0] operand_slice_a4 ;\n wire [8:0] operand_b_neg ;\n \n inv_converter_8 inv_converter_8_inst(\n .data_i (operand_b),\n .inv_o (operand_b_neg) \n );\n \n assign operand_slice_a1 = operand_a[1:0] ;\n assign operand_slice_a2 = operand_a[3:1] ;\n assign operand_slice_a3 = operand_a[5:3] ;\n assign operand_slice_a4 = operand_a[7:5] ;\n\n booth_partial_product_generator_pp1 ppg_1 (\n .operand_slice_a (operand_slice_a1), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp1) \n );\n\n booth_partial_product_generator ppg_2 (\n .operand_slice_a (operand_slice_a2), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp2) \n );\n\n booth_partial_product_generator ppg_3 (\n .operand_slice_a (operand_slice_a3), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp3) \n );\n\n booth_partial_product_generator ppg_4 (\n .operand_slice_a (operand_slice_a4), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp4) \n );\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/booth_pp_gen.v", "module booth_pp_gen(\n input wire [7:0] operand_a, \n input wire [7:0] operand_b, \n output wire [9:0] pp1,\n output wire [9:0] pp2,\n output wire [9:0] pp3,\n output wire [9:0] pp4 \n );\n\n wire [1:0] operand_slice_a1 ;\n wire [2:0] operand_slice_a2 ;\n wire [2:0] operand_slice_a3 ;\n wire [2:0] operand_slice_a4 ;\n wire [8:0] operand_b_neg ;\n \n inv_converter_8 inv_converter_8_inst(\n .data_i (operand_b),\n .inv_o (operand_b_neg) \n );\n \n assign operand_slice_a1 = operand_a[1:0] ;\n assign operand_slice_a2 = operand_a[3:1] ;\n assign operand_slice_a3 = operand_a[5:3] ;\n assign operand_slice_a4 = operand_a[7:5] ;\n\n booth_partial_product_generator_pp1 ppg_1 (\n .operand_slice_a (operand_slice_a1), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp1) \n );\n\n booth_partial_product_generator ppg_2 (\n .operand_slice_a (operand_slice_a2), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp2) \n );\n\n booth_partial_product_generator ppg_3 (\n .operand_slice_a (operand_slice_a3), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp3) \n );\n\n booth_partial_product_generator ppg_4 (\n .operand_slice_a (operand_slice_a4), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp4) \n );\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT3_OPT4C/pe/get_pipline_mulwidth.v", "module get_pipeline_mulwidth #(\n parameter N = 4,\n parameter WIDTH = 8 \n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] signal,\n output wire [WIDTH-1:0] pipeline_signal\n);\n\n\nreg [WIDTH-1:0] pipeline_regs [N-1:0];\n\n\n genvar i;\n generate\n for (i = 0; i < N; i = i + 1) begin : pipeline_stage\n always @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n pipeline_regs[i] <= 0; \n end else begin\n if (i == 0) begin\n pipeline_regs[i] <= signal; \n end else begin\n pipeline_regs[i] <= pipeline_regs[i-1]; \n end\n end\n end\n end\n endgenerate\n\n\n assign pipeline_signal = pipeline_regs[N-1];\n\nendmodule\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT2/get_pipline_mulwidth.v", "module get_pipeline_mulwidth #(\n parameter N = 4,\n parameter WIDTH = 8 \n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] signal,\n output wire [WIDTH-1:0] pipeline_signal\n);\n\n\nreg [WIDTH-1:0] pipeline_regs [N-1:0];\n\n\n genvar i;\n generate\n for (i = 0; i < N; i = i + 1) begin : pipeline_stage\n always @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n pipeline_regs[i] <= 0; \n end else begin\n if (i == 0) begin\n pipeline_regs[i] <= signal; \n end else begin\n pipeline_regs[i] <= pipeline_regs[i-1]; \n end\n end\n end\n end\n endgenerate\n\n\n assign pipeline_signal = pipeline_regs[N-1];\n\nendmodule\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT3_OPT4C/pe/top_pe.v", "module top_pe(\n input clk,\n input rst_n,\n input clr,\n input [7:0] en_multiplicand, // operand a\n input [3:0] sign_en_multiplicand,\n input encode_valid,\n input [7:0] operand_b, \n output [1:0] position, // to prefetch operand b \n output [2:0] cal_cycle, // to prefetch operand a \n output [51:0] pe_result \n);\n\nwire [1:0] partial_product_index;\n\nsparse_encoder sp_encoder(\n .clk(clk),\n .rst_n(rst_n),\n .en_multiplicand(en_multiplicand),\n .sign_en_multiplicand(sign_en_multiplicand),\n .encode_valid(encode_valid),\n .partial_product_index(partial_product_index), // to sparse_pe generate partial product\n .position_0(position), // to prefetch operand b\n .cal_cycle(cal_cycle) // to prefetch operand a \n);\n\n\npe #(\n .ACC_WIDTH(26)\n) sparse_pe (\n .clk(clk),\n .rst_n(rst_n),\n .clr(clr),\n .encoder_position_ins(partial_product_index),\n .operand_b_ins(operand_b),\n .result(pe_result)\n);\n\n\n\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/dff_async.v", "module dff_async #(\n parameter WIDTH = 8\n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] d,\n output reg [WIDTH-1:0] q\n);\n\nalways @(posedge clk or negedge rst_n) begin\n if (!rst_n) begin\n q <= 0;\n end\n else begin\n q <= d;\n end\nend\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT3_OPT4C/pe/get_negedge.sv", "module get_negedge(\n input clk,\n input signal,\n output negedge_signal\n );\n\nreg save;\n\nalways @(posedge clk) begin\n save <= signal;\nend\n\nassign negedge_signal = ~signal & save;\n\nendmodule\n\n// get_negedge get_hit(\n// .clk(clk),\n// .signal(cache_hit),\n// .negedge_signal(negedge_cache_hit)\n// );"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/inv_unit.v", "module inv_unit(\n input wire a ,\n input wire b ,\n output wire xor_o , \n output wire or_o \n );\n \n wire aORb ; \n wire aNANDb ; \n \n assign aORb = a | b;\n assign aNANDb = ~(a & b);\n assign xor_o = (aORb & aNANDb);\n assign or_o = aORb;\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/inv_unit.v", "module inv_unit(\n input wire a ,\n input wire b ,\n output wire xor_o , \n output wire or_o \n );\n \n wire aORb ; \n wire aNANDb ; \n \n assign aORb = a | b;\n assign aNANDb = ~(a & b);\n assign xor_o = (aORb & aNANDb);\n assign or_o = aORb;\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/inv_unit.v", "module inv_unit(\n input wire a ,\n input wire b ,\n output wire xor_o , \n output wire or_o \n );\n \n wire aORb ; \n wire aNANDb ; \n \n assign aORb = a | b;\n assign aNANDb = ~(a & b);\n assign xor_o = (aORb & aNANDb);\n assign or_o = aORb;\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/inv_unit.v", "module inv_unit(\n input wire a ,\n input wire b ,\n output wire xor_o , \n output wire or_o \n );\n \n wire aORb ; \n wire aNANDb ; \n \n assign aORb = a | b;\n assign aNANDb = ~(a & b);\n assign xor_o = (aORb & aNANDb);\n assign or_o = aORb;\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/inv_unit_nor_out.v", "module inv_unit_nor_out(\n input wire a ,\n input wire b ,\n \n output wire xor_o , \n output wire nor_o \n );\n \n\n wire a_AND_b ; \n wire a_NOR_b ; \n \n \n assign a_AND_b = a & b;\n \n \n assign a_NOR_b = ~(a | b);\n \n\n assign xor_o = ~(a_AND_b | a_NOR_b);\n assign nor_o = a_NOR_b;\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/inv_unit_nor_out.v", "module inv_unit_nor_out(\n input wire a ,\n input wire b ,\n \n output wire xor_o , \n output wire nor_o \n );\n \n\n wire a_AND_b ; \n wire a_NOR_b ; \n \n \n assign a_AND_b = a & b;\n \n \n assign a_NOR_b = ~(a | b);\n \n\n assign xor_o = ~(a_AND_b | a_NOR_b);\n assign nor_o = a_NOR_b;\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/inv_unit_nor_out.v", "module inv_unit_nor_out(\n input wire a ,\n input wire b ,\n \n output wire xor_o , \n output wire nor_o \n );\n \n\n wire a_AND_b ; \n wire a_NOR_b ; \n \n \n assign a_AND_b = a & b;\n \n \n assign a_NOR_b = ~(a | b);\n \n\n assign xor_o = ~(a_AND_b | a_NOR_b);\n assign nor_o = a_NOR_b;\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/inv_unit_nor_out.v", "module inv_unit_nor_out(\n input wire a ,\n input wire b ,\n \n output wire xor_o , \n output wire nor_o \n );\n \n\n wire a_AND_b ; \n wire a_NOR_b ; \n \n \n assign a_AND_b = a & b;\n \n \n assign a_NOR_b = ~(a | b);\n \n\n assign xor_o = ~(a_AND_b | a_NOR_b);\n assign nor_o = a_NOR_b;\n \nendmodule"]], "task_instance_info": {"created_time": "2025-08-21 04:17:40", "created_task_model": "DeepSeek-R1", "class_skeleton": "module DW02_tree ( INPUT, OUT0, OUT1 ) ; // parameters endmodule", "code_description": "This code segment functions to: Reduce a collection of input values through hierarchical combination using bitwise operations and carry propagation, ultimately producing two output values representing the condensed result and accumulated carry information."}, "inference_content": {"inference_model": "DeepSeek-R1", "inference_result": "```verilog\n[TASK_BEGIN]\nmodule DW02_tree ( INPUT, OUT0, OUT1 );\n\nparameter num_inputs = 2;\nparameter input_width = 3;\n\ninput [num_inputs*input_width-1:0] INPUT;\noutput [input_width-1:0] OUT0, OUT1;\n\nreg [input_width-1:0] OUT0, OUT1;\nreg [input_width:0] sum;\n\ninteger i, j;\nreg [input_width-1:0] temp;\nreg x_flag;\n\nalways @(INPUT) begin\n sum = 0;\n x_flag = 0;\n \n for (i=0; i 2)\n begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I/3) ; O1OIIOII = O1OIIOII+1) begin\n l10III00[O1OIIOII*2] = I0lII01I[O1OIIOII*3] ^ I0lII01I[O1OIIOII*3+1] ^ I0lII01I[O1OIIOII*3+2];\n lI0OII0O = (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+1]) |\n (I0lII01I[O1OIIOII*3+1] & I0lII01I[O1OIIOII*3+2]) |\n (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+2]);\n l10III00[O1OIIOII*2+1] = lI0OII0O << 1;\n end\n if ((I1I1O00I % 3) > 0) begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I % 3) ; O1OIIOII = O1OIIOII + 1)\n l10III00[2 * (I1I1O00I/3) + O1OIIOII] = I0lII01I[3 * (I1I1O00I/3) + O1OIIOII];\n end\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII = O1OIIOII + 1)\n I0lII01I[O1OIIOII] = l10III00[O1OIIOII];\n I1I1O00I = I1I1O00I - (I1I1O00I/3);\n end\n OII0OOOI = I0lII01I[0];\n if (I1I1O00I > 1)\n O001l0I0 = I0lII01I[1];\n else\n O001l0I0 = {input_width{1'b0}};\nend \nassign OUT0 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : OII0OOOI;\nassign OUT1 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : O001l0I0;\nendmodule", "predict_code_clean": "module DW02_tree ( INPUT, OUT0, OUT1 );\nparameter num_inputs = 2;\nparameter input_width = 3;\ninput [num_inputs*input_width-1:0] INPUT;\noutput [input_width-1:0] OUT0, OUT1;\nreg [input_width-1:0] OUT0, OUT1;\nreg [input_width:0] sum;\ninteger i, j;\nreg [input_width-1:0] temp;\nreg x_flag;\nalways @(INPUT) begin\n sum = 0;\n x_flag = 0;\n for (i=0; i 1) ) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter verif_en (legal range: 0 to 1)\",\n// \tverif_en );\n// end\n \n// if ( param_err_flg == 1) begin\n// $display(\n// \"%m :\\n Simulation aborted due to invalid parameter value(s)\");\n// $finish;\n// end\n\n// end // parameter_check \n\n\n// `ifndef DW_SUPPRESS_WARN\n// initial begin : verif_en_warning\n// $display(\"The parameter verif_en is set to 0 for this simulator.\\nOther values for verif_en are enabled only for VCS.\");\n// end // verif_en_warning\n// `endif\n\n//-----------------------------------------------------------------------------\n\n\n\nalways @ (INPUT) begin : IIIIO1Ol\n reg [input_width-1 : 0] I0lII01I [0 : num_inputs-1];\n reg [input_width-1 : 0] l10III00 [0 : num_inputs-1];\n reg [input_width-1 : 0] IIIO00Ol, lI0OII0O;\n integer I1I1O00I, O1OIIOII, IlI01lIO;\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII=O1OIIOII+1) begin\n for (IlI01lIO=0 ; IlI01lIO < input_width ; IlI01lIO=IlI01lIO+1) begin\n IIIO00Ol[IlI01lIO] = INPUT[O1OIIOII*input_width+IlI01lIO];\n end // for IlI01lIO\n I0lII01I[O1OIIOII] = IIIO00Ol;\n end // for O1OIIOII\n\n I1I1O00I = num_inputs;\n\n while (I1I1O00I > 2)\n begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I/3) ; O1OIIOII = O1OIIOII+1) begin\n l10III00[O1OIIOII*2] = I0lII01I[O1OIIOII*3] ^ I0lII01I[O1OIIOII*3+1] ^ I0lII01I[O1OIIOII*3+2];\n\n lI0OII0O = (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+1]) |\n (I0lII01I[O1OIIOII*3+1] & I0lII01I[O1OIIOII*3+2]) |\n (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+2]);\n\n l10III00[O1OIIOII*2+1] = lI0OII0O << 1;\n end\n if ((I1I1O00I % 3) > 0) begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I % 3) ; O1OIIOII = O1OIIOII + 1)\n l10III00[2 * (I1I1O00I/3) + O1OIIOII] = I0lII01I[3 * (I1I1O00I/3) + O1OIIOII];\n end\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII = O1OIIOII + 1)\n I0lII01I[O1OIIOII] = l10III00[O1OIIOII];\n I1I1O00I = I1I1O00I - (I1I1O00I/3);\n end\n OII0OOOI = I0lII01I[0];\n if (I1I1O00I > 1)\n O001l0I0 = I0lII01I[1];\n else\n O001l0I0 = {input_width{1'b0}};\nend // IIIIO1Ol\n\n\nassign OUT0 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : OII0OOOI;\nassign OUT1 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : O001l0I0;\n\n// synopsys translate_on\n\nendmodule\n // synopsys translate_off\n// `endif\n // synopsys translate_on\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/DW02_tree.sv", "////////////////////////////////////////////////////////////////////////////////\n//\n// This confidential and proprietary software may be used only\n// as authorized by a licensing agreement from Synopsys Inc.\n// In the event of publication, the following notice is applicable:\n//\n// (C) COPYRIGHT 2000 - 2021 SYNOPSYS INC.\n// ALL RIGHTS RESERVED\n//\n// The entire notice above must be reproduced on all authorized\n// copies.\n//\n// AUTHOR: Rick Kelly 07/28/2000\n//\n// VERSION: Verilog Simulation Model for DW02_tree\n//\n// DesignWare_version: aacb4808\n// DesignWare_release: S-2021.06-DWBB_202106.4\n//\n////////////////////////////////////////////////////////////////////////////////\n\n//-----------------------------------------------------------------------------------\n//\n// ABSTRACT: Wallace Tree Summer with Carry Save output\n//\n// MODIFIED:\n// Aamir Farooqui 7/11/02\n// Corrected parameter checking, simplied sim model, and X_processing\n//\n//------------------------------------------------------------------------------\n//\n\n // synopsys translate_off\n// `ifdef VCS\n// `include \"DW02_tree.v\"\n// `else\n // synopsys translate_on\n\nmodule DW02_tree( INPUT, OUT0, OUT1 );\n\n// parameters\nparameter integer num_inputs = 8;\nparameter integer input_width = 8;\nparameter integer verif_en = 1;\n\n//-----------------------------------------------------------------------------\n// ports\ninput [num_inputs*input_width-1 : 0]\tINPUT;\noutput [input_width-1:0]\t\tOUT0, OUT1;\n\n//-----------------------------------------------------------------------------\n// synopsys translate_off\nreg [input_width-1:0]\t\tOII0OOOI, O001l0I0;\n\n//-----------------------------------------------------------------------------\n \n \n// initial begin : parameter_check\n// integer param_err_flg;\n\n// param_err_flg = 0;\n \n \n// if (num_inputs < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter num_inputs (lower bound: 1)\",\n// \tnum_inputs );\n// end\n \n// if (input_width < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter input_width (lower bound: 1)\",\n// \tinput_width );\n// end\n \n// if ( (verif_en < 0) || (verif_en > 1) ) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter verif_en (legal range: 0 to 1)\",\n// \tverif_en );\n// end\n \n// if ( param_err_flg == 1) begin\n// $display(\n// \"%m :\\n Simulation aborted due to invalid parameter value(s)\");\n// $finish;\n// end\n\n// end // parameter_check \n\n\n// `ifndef DW_SUPPRESS_WARN\n// initial begin : verif_en_warning\n// $display(\"The parameter verif_en is set to 0 for this simulator.\\nOther values for verif_en are enabled only for VCS.\");\n// end // verif_en_warning\n// `endif\n\n//-----------------------------------------------------------------------------\n\n\n\nalways @ (INPUT) begin : IIIIO1Ol\n reg [input_width-1 : 0] I0lII01I [0 : num_inputs-1];\n reg [input_width-1 : 0] l10III00 [0 : num_inputs-1];\n reg [input_width-1 : 0] IIIO00Ol, lI0OII0O;\n integer I1I1O00I, O1OIIOII, IlI01lIO;\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII=O1OIIOII+1) begin\n for (IlI01lIO=0 ; IlI01lIO < input_width ; IlI01lIO=IlI01lIO+1) begin\n IIIO00Ol[IlI01lIO] = INPUT[O1OIIOII*input_width+IlI01lIO];\n end // for IlI01lIO\n I0lII01I[O1OIIOII] = IIIO00Ol;\n end // for O1OIIOII\n\n I1I1O00I = num_inputs;\n\n while (I1I1O00I > 2)\n begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I/3) ; O1OIIOII = O1OIIOII+1) begin\n l10III00[O1OIIOII*2] = I0lII01I[O1OIIOII*3] ^ I0lII01I[O1OIIOII*3+1] ^ I0lII01I[O1OIIOII*3+2];\n\n lI0OII0O = (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+1]) |\n (I0lII01I[O1OIIOII*3+1] & I0lII01I[O1OIIOII*3+2]) |\n (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+2]);\n\n l10III00[O1OIIOII*2+1] = lI0OII0O << 1;\n end\n if ((I1I1O00I % 3) > 0) begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I % 3) ; O1OIIOII = O1OIIOII + 1)\n l10III00[2 * (I1I1O00I/3) + O1OIIOII] = I0lII01I[3 * (I1I1O00I/3) + O1OIIOII];\n end\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII = O1OIIOII + 1)\n I0lII01I[O1OIIOII] = l10III00[O1OIIOII];\n I1I1O00I = I1I1O00I - (I1I1O00I/3);\n end\n OII0OOOI = I0lII01I[0];\n if (I1I1O00I > 1)\n O001l0I0 = I0lII01I[1];\n else\n O001l0I0 = {input_width{1'b0}};\nend // IIIIO1Ol\n\n\nassign OUT0 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : OII0OOOI;\nassign OUT1 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : O001l0I0;\n\n// synopsys translate_on\n\nendmodule\n // synopsys translate_off\n// `endif\n // synopsys translate_on\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/DW02_tree.sv", "////////////////////////////////////////////////////////////////////////////////\n//\n// This confidential and proprietary software may be used only\n// as authorized by a licensing agreement from Synopsys Inc.\n// In the event of publication, the following notice is applicable:\n//\n// (C) COPYRIGHT 2000 - 2021 SYNOPSYS INC.\n// ALL RIGHTS RESERVED\n//\n// The entire notice above must be reproduced on all authorized\n// copies.\n//\n// AUTHOR: Rick Kelly 07/28/2000\n//\n// VERSION: Verilog Simulation Model for DW02_tree\n//\n// DesignWare_version: aacb4808\n// DesignWare_release: S-2021.06-DWBB_202106.4\n//\n////////////////////////////////////////////////////////////////////////////////\n\n//-----------------------------------------------------------------------------------\n//\n// ABSTRACT: Wallace Tree Summer with Carry Save output\n//\n// MODIFIED:\n// Aamir Farooqui 7/11/02\n// Corrected parameter checking, simplied sim model, and X_processing\n//\n//------------------------------------------------------------------------------\n//\n\n // synopsys translate_off\n// `ifdef VCS\n// `include \"DW02_tree.v\"\n// `else\n // synopsys translate_on\n\nmodule DW02_tree( INPUT, OUT0, OUT1 );\n\n// parameters\nparameter integer num_inputs = 8;\nparameter integer input_width = 8;\nparameter integer verif_en = 1;\n\n//-----------------------------------------------------------------------------\n// ports\ninput [num_inputs*input_width-1 : 0]\tINPUT;\noutput [input_width-1:0]\t\tOUT0, OUT1;\n\n//-----------------------------------------------------------------------------\n// synopsys translate_off\nreg [input_width-1:0]\t\tOII0OOOI, O001l0I0;\n\n//-----------------------------------------------------------------------------\n \n \n// initial begin : parameter_check\n// integer param_err_flg;\n\n// param_err_flg = 0;\n \n \n// if (num_inputs < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter num_inputs (lower bound: 1)\",\n// \tnum_inputs );\n// end\n \n// if (input_width < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter input_width (lower bound: 1)\",\n// \tinput_width );\n// end\n \n// if ( (verif_en < 0) || (verif_en > 1) ) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter verif_en (legal range: 0 to 1)\",\n// \tverif_en );\n// end\n \n// if ( param_err_flg == 1) begin\n// $display(\n// \"%m :\\n Simulation aborted due to invalid parameter value(s)\");\n// $finish;\n// end\n\n// end // parameter_check \n\n\n// `ifndef DW_SUPPRESS_WARN\n// initial begin : verif_en_warning\n// $display(\"The parameter verif_en is set to 0 for this simulator.\\nOther values for verif_en are enabled only for VCS.\");\n// end // verif_en_warning\n// `endif\n\n//-----------------------------------------------------------------------------\n\n\n\nalways @ (INPUT) begin : IIIIO1Ol\n reg [input_width-1 : 0] I0lII01I [0 : num_inputs-1];\n reg [input_width-1 : 0] l10III00 [0 : num_inputs-1];\n reg [input_width-1 : 0] IIIO00Ol, lI0OII0O;\n integer I1I1O00I, O1OIIOII, IlI01lIO;\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII=O1OIIOII+1) begin\n for (IlI01lIO=0 ; IlI01lIO < input_width ; IlI01lIO=IlI01lIO+1) begin\n IIIO00Ol[IlI01lIO] = INPUT[O1OIIOII*input_width+IlI01lIO];\n end // for IlI01lIO\n I0lII01I[O1OIIOII] = IIIO00Ol;\n end // for O1OIIOII\n\n I1I1O00I = num_inputs;\n\n while (I1I1O00I > 2)\n begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I/3) ; O1OIIOII = O1OIIOII+1) begin\n l10III00[O1OIIOII*2] = I0lII01I[O1OIIOII*3] ^ I0lII01I[O1OIIOII*3+1] ^ I0lII01I[O1OIIOII*3+2];\n\n lI0OII0O = (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+1]) |\n (I0lII01I[O1OIIOII*3+1] & I0lII01I[O1OIIOII*3+2]) |\n (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+2]);\n\n l10III00[O1OIIOII*2+1] = lI0OII0O << 1;\n end\n if ((I1I1O00I % 3) > 0) begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I % 3) ; O1OIIOII = O1OIIOII + 1)\n l10III00[2 * (I1I1O00I/3) + O1OIIOII] = I0lII01I[3 * (I1I1O00I/3) + O1OIIOII];\n end\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII = O1OIIOII + 1)\n I0lII01I[O1OIIOII] = l10III00[O1OIIOII];\n I1I1O00I = I1I1O00I - (I1I1O00I/3);\n end\n OII0OOOI = I0lII01I[0];\n if (I1I1O00I > 1)\n O001l0I0 = I0lII01I[1];\n else\n O001l0I0 = {input_width{1'b0}};\nend // IIIIO1Ol\n\n\nassign OUT0 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : OII0OOOI;\nassign OUT1 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : O001l0I0;\n\n// synopsys translate_on\n\nendmodule\n // synopsys translate_off\n// `endif\n // synopsys translate_on\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/booth_partial_product_generator_pp1.v", "module booth_partial_product_generator_pp1(\n input wire [1:0] operand_slice_a, \n input wire [7:0] operand_b, \n input wire [8:0] operand_b_neg, \n output wire [9:0] pp_out \n );\n \n wire [8:0] pp_source;\n wire not_code0;\n //----------------------------------------------------\n //| pp | flag_2x | flag_s1 | flag_s2 |\n //----------------------------------------------------\n //| operand_b | 0 | 0 | 1 |\n //| -operand_b | 0 | 1 | 0 |\n //| 2operand_b | 1 | 0 | 1 | \n //| -2operand_b | 1 | 1 | 0 |\n //| 0 | x | 0 | 0 | \n //----------------------------------------------------\n wire flag_2x;\n wire flag_s1;\n wire flag_s2; \n assign not_code0 = ~operand_slice_a[0]; \n assign flag_2x = not_code0; \n assign flag_s1 = operand_slice_a[1]; \n assign flag_s2 = ~(operand_slice_a[1] | not_code0); \n wire flag_not_2x = operand_slice_a[0];\n assign pp_source = (({{operand_b[7]}, operand_b} & {9{flag_s2}}) | (operand_b_neg & {9{flag_s1}}));\n assign pp_out[0] = (!flag_2x & pp_source[0]);\n assign pp_out[8:1] = (({8{flag_2x}} & pp_source[7:0]) | ({8{flag_not_2x}} & pp_source[8:1]));\n assign pp_out[9] = pp_source[8];\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/booth_pp_gen.v", "module booth_pp_gen(\n input wire [7:0] operand_a, \n input wire [7:0] operand_b, \n output wire [9:0] pp1,\n output wire [9:0] pp2,\n output wire [9:0] pp3,\n output wire [9:0] pp4 \n );\n\n wire [1:0] operand_slice_a1 ;\n wire [2:0] operand_slice_a2 ;\n wire [2:0] operand_slice_a3 ;\n wire [2:0] operand_slice_a4 ;\n wire [8:0] operand_b_neg ;\n \n inv_converter_8 inv_converter_8_inst(\n .data_i (operand_b),\n .inv_o (operand_b_neg) \n );\n \n assign operand_slice_a1 = operand_a[1:0] ;\n assign operand_slice_a2 = operand_a[3:1] ;\n assign operand_slice_a3 = operand_a[5:3] ;\n assign operand_slice_a4 = operand_a[7:5] ;\n\n booth_partial_product_generator_pp1 ppg_1 (\n .operand_slice_a (operand_slice_a1), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp1) \n );\n\n booth_partial_product_generator ppg_2 (\n .operand_slice_a (operand_slice_a2), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp2) \n );\n\n booth_partial_product_generator ppg_3 (\n .operand_slice_a (operand_slice_a3), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp3) \n );\n\n booth_partial_product_generator ppg_4 (\n .operand_slice_a (operand_slice_a4), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp4) \n );\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/booth_pp_gen.v", "module booth_pp_gen(\n input wire [7:0] operand_a, \n input wire [7:0] operand_b, \n output wire [9:0] pp1,\n output wire [9:0] pp2,\n output wire [9:0] pp3,\n output wire [9:0] pp4 \n );\n\n wire [1:0] operand_slice_a1 ;\n wire [2:0] operand_slice_a2 ;\n wire [2:0] operand_slice_a3 ;\n wire [2:0] operand_slice_a4 ;\n wire [8:0] operand_b_neg ;\n \n inv_converter_8 inv_converter_8_inst(\n .data_i (operand_b),\n .inv_o (operand_b_neg) \n );\n \n assign operand_slice_a1 = operand_a[1:0] ;\n assign operand_slice_a2 = operand_a[3:1] ;\n assign operand_slice_a3 = operand_a[5:3] ;\n assign operand_slice_a4 = operand_a[7:5] ;\n\n booth_partial_product_generator_pp1 ppg_1 (\n .operand_slice_a (operand_slice_a1), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp1) \n );\n\n booth_partial_product_generator ppg_2 (\n .operand_slice_a (operand_slice_a2), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp2) \n );\n\n booth_partial_product_generator ppg_3 (\n .operand_slice_a (operand_slice_a3), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp3) \n );\n\n booth_partial_product_generator ppg_4 (\n .operand_slice_a (operand_slice_a4), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp4) \n );\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/booth_pp_gen.v", "module booth_pp_gen(\n input wire [7:0] operand_a, \n input wire [7:0] operand_b, \n output wire [9:0] pp1,\n output wire [9:0] pp2,\n output wire [9:0] pp3,\n output wire [9:0] pp4 \n );\n\n wire [1:0] operand_slice_a1 ;\n wire [2:0] operand_slice_a2 ;\n wire [2:0] operand_slice_a3 ;\n wire [2:0] operand_slice_a4 ;\n wire [8:0] operand_b_neg ;\n \n inv_converter_8 inv_converter_8_inst(\n .data_i (operand_b),\n .inv_o (operand_b_neg) \n );\n \n assign operand_slice_a1 = operand_a[1:0] ;\n assign operand_slice_a2 = operand_a[3:1] ;\n assign operand_slice_a3 = operand_a[5:3] ;\n assign operand_slice_a4 = operand_a[7:5] ;\n\n booth_partial_product_generator_pp1 ppg_1 (\n .operand_slice_a (operand_slice_a1), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp1) \n );\n\n booth_partial_product_generator ppg_2 (\n .operand_slice_a (operand_slice_a2), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp2) \n );\n\n booth_partial_product_generator ppg_3 (\n .operand_slice_a (operand_slice_a3), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp3) \n );\n\n booth_partial_product_generator ppg_4 (\n .operand_slice_a (operand_slice_a4), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp4) \n );\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/booth_pp_gen.v", "module booth_pp_gen(\n input wire [7:0] operand_a, \n input wire [7:0] operand_b, \n output wire [9:0] pp1,\n output wire [9:0] pp2,\n output wire [9:0] pp3,\n output wire [9:0] pp4 \n );\n\n wire [1:0] operand_slice_a1 ;\n wire [2:0] operand_slice_a2 ;\n wire [2:0] operand_slice_a3 ;\n wire [2:0] operand_slice_a4 ;\n wire [8:0] operand_b_neg ;\n \n inv_converter_8 inv_converter_8_inst(\n .data_i (operand_b),\n .inv_o (operand_b_neg) \n );\n \n assign operand_slice_a1 = operand_a[1:0] ;\n assign operand_slice_a2 = operand_a[3:1] ;\n assign operand_slice_a3 = operand_a[5:3] ;\n assign operand_slice_a4 = operand_a[7:5] ;\n\n booth_partial_product_generator_pp1 ppg_1 (\n .operand_slice_a (operand_slice_a1), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp1) \n );\n\n booth_partial_product_generator ppg_2 (\n .operand_slice_a (operand_slice_a2), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp2) \n );\n\n booth_partial_product_generator ppg_3 (\n .operand_slice_a (operand_slice_a3), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp3) \n );\n\n booth_partial_product_generator ppg_4 (\n .operand_slice_a (operand_slice_a4), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp4) \n );\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_mac_based/get_pipline_mulwidth.v", "module get_pipeline_mulwidth #(\n parameter N = 4,\n parameter WIDTH = 8 \n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] signal,\n output wire [WIDTH-1:0] pipeline_signal\n);\n\n\n reg [WIDTH-1:0] pipeline_regs [N-1:0];\n\n\n genvar i;\n generate\n for (i = 0; i < N; i = i + 1) begin : pipeline_stage\n always @(posedge clk) begin\n if(~rst_n) \n pipeline_regs[i] <= 0;\n else begin\n if (i == 0) begin\n pipeline_regs[i] <= signal; \n end else begin\n pipeline_regs[i] <= pipeline_regs[i-1]; \n end\n end\n end\n end\n endgenerate\n\n\n assign pipeline_signal = pipeline_regs[N-1];\n\nendmodule\n\n\n// // 实例化 get_pipeline_mulwidth 模块\n// get_pipeline_mulwidth #(\n// .N(4), // 设置流水线深度为 4\n// .WIDTH(8) // 设置信号宽度为 8 位\n// ) pipeline_inst (\n// .clk(clk), // 连接时钟信号\n// .rst_n(rst_n), // 连接复位信号\n// .signal(input_signal), // 连接输入信号\n// .pipeline_signal(output_signal) // 连接输出信号\n// );\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/get_pipline_mulwidth.v", "module get_pipeline_mulwidth #(\n parameter N = 4,\n parameter WIDTH = 8 \n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] signal,\n output wire [WIDTH-1:0] pipeline_signal\n);\n\n\n reg [WIDTH-1:0] pipeline_regs [N-1:0];\n\n\n genvar i;\n generate\n for (i = 0; i < N; i = i + 1) begin : pipeline_stage\n always @(posedge clk) begin\n if(~rst_n) \n pipeline_regs[i] <= 0;\n else begin\n if (i == 0) begin\n pipeline_regs[i] <= signal; \n end else begin\n pipeline_regs[i] <= pipeline_regs[i-1]; \n end\n end\n end\n end\n endgenerate\n\n\n assign pipeline_signal = pipeline_regs[N-1];\n\nendmodule\n\n\n// // 实例化 get_pipeline_mulwidth 模块\n// get_pipeline_mulwidth #(\n// .N(4), // 设置流水线深度为 4\n// .WIDTH(8) // 设置信号宽度为 8 位\n// ) pipeline_inst (\n// .clk(clk), // 连接时钟信号\n// .rst_n(rst_n), // 连接复位信号\n// .signal(input_signal), // 连接输入信号\n// .pipeline_signal(output_signal) // 连接输出信号\n// );\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_mac_based/get_pipline_mulwidth.v", "module get_pipeline_mulwidth #(\n parameter N = 4,\n parameter WIDTH = 8 \n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] signal,\n output wire [WIDTH-1:0] pipeline_signal\n);\n\n\n reg [WIDTH-1:0] pipeline_regs [N-1:0];\n\n\n genvar i;\n generate\n for (i = 0; i < N; i = i + 1) begin : pipeline_stage\n always @(posedge clk) begin\n if(~rst_n) \n pipeline_regs[i] <= 0;\n else begin\n if (i == 0) begin\n pipeline_regs[i] <= signal; \n end else begin\n pipeline_regs[i] <= pipeline_regs[i-1]; \n end\n end\n end\n end\n endgenerate\n\n\n assign pipeline_signal = pipeline_regs[N-1];\n\nendmodule\n\n\n// // 实例化 get_pipeline_mulwidth 模块\n// get_pipeline_mulwidth #(\n// .N(4), // 设置流水线深度为 4\n// .WIDTH(8) // 设置信号宽度为 8 位\n// ) pipeline_inst (\n// .clk(clk), // 连接时钟信号\n// .rst_n(rst_n), // 连接复位信号\n// .signal(input_signal), // 连接输入信号\n// .pipeline_signal(output_signal) // 连接输出信号\n// );\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_mac_based/get_pipline_mulwidth.v", "module get_pipeline_mulwidth #(\n parameter N = 4,\n parameter WIDTH = 8 \n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] signal,\n output wire [WIDTH-1:0] pipeline_signal\n);\n\n\n reg [WIDTH-1:0] pipeline_regs [N-1:0];\n\n\n genvar i;\n generate\n for (i = 0; i < N; i = i + 1) begin : pipeline_stage\n always @(posedge clk) begin\n if(~rst_n) \n pipeline_regs[i] <= 0;\n else begin\n if (i == 0) begin\n pipeline_regs[i] <= signal; \n end else begin\n pipeline_regs[i] <= pipeline_regs[i-1]; \n end\n end\n end\n end\n endgenerate\n\n\n assign pipeline_signal = pipeline_regs[N-1];\n\nendmodule\n\n\n// // 实例化 get_pipeline_mulwidth 模块\n// get_pipeline_mulwidth #(\n// .N(4), // 设置流水线深度为 4\n// .WIDTH(8) // 设置信号宽度为 8 位\n// ) pipeline_inst (\n// .clk(clk), // 连接时钟信号\n// .rst_n(rst_n), // 连接复位信号\n// .signal(input_signal), // 连接输入信号\n// .pipeline_signal(output_signal) // 连接输出信号\n// );\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/get_pipline_mulwidth.v", "module get_pipeline_mulwidth #(\n parameter N = 4,\n parameter WIDTH = 8 \n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] signal,\n output wire [WIDTH-1:0] pipeline_signal\n);\n\n\n reg [WIDTH-1:0] pipeline_regs [N-1:0];\n\n\n genvar i;\n generate\n for (i = 0; i < N; i = i + 1) begin : pipeline_stage\n always @(posedge clk) begin\n if(~rst_n) \n pipeline_regs[i] <= 0;\n else begin\n if (i == 0) begin\n pipeline_regs[i] <= signal; \n end else begin\n pipeline_regs[i] <= pipeline_regs[i-1]; \n end\n end\n end\n end\n endgenerate\n\n\n assign pipeline_signal = pipeline_regs[N-1];\n\nendmodule\n\n\n// // 实例化 get_pipeline_mulwidth 模块\n// get_pipeline_mulwidth #(\n// .N(4), // 设置流水线深度为 4\n// .WIDTH(8) // 设置信号宽度为 8 位\n// ) pipeline_inst (\n// .clk(clk), // 连接时钟信号\n// .rst_n(rst_n), // 连接复位信号\n// .signal(input_signal), // 连接输入信号\n// .pipeline_signal(output_signal) // 连接输出信号\n// );\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/get_pipline_mulwidth.v", "module get_pipeline_mulwidth #(\n parameter N = 4,\n parameter WIDTH = 8 \n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] signal,\n output wire [WIDTH-1:0] pipeline_signal\n);\n\n\n reg [WIDTH-1:0] pipeline_regs [N-1:0];\n\n\n genvar i;\n generate\n for (i = 0; i < N; i = i + 1) begin : pipeline_stage\n always @(posedge clk) begin\n if(~rst_n) \n pipeline_regs[i] <= 0;\n else begin\n if (i == 0) begin\n pipeline_regs[i] <= signal; \n end else begin\n pipeline_regs[i] <= pipeline_regs[i-1]; \n end\n end\n end\n end\n endgenerate\n\n\n assign pipeline_signal = pipeline_regs[N-1];\n\nendmodule\n\n\n// // 实例化 get_pipeline_mulwidth 模块\n// get_pipeline_mulwidth #(\n// .N(4), // 设置流水线深度为 4\n// .WIDTH(8) // 设置信号宽度为 8 位\n// ) pipeline_inst (\n// .clk(clk), // 连接时钟信号\n// .rst_n(rst_n), // 连接复位信号\n// .signal(input_signal), // 连接输入信号\n// .pipeline_signal(output_signal) // 连接输出信号\n// );\n"], ["/High-Performance-Tensor-Processing-Engines/OPT3_OPT4C/pe/encoder_multi_bit.v", "module encoder_multi_bit #(\n localparam WIDTH = 8,\n localparam ENCODER_WIDTH = WIDTH + (WIDTH+1)%2,\n localparam TIMES = (WIDTH-1)/2 + (WIDTH-1)%2\n)(\n input clk,\n input rst_n,\n input [WIDTH-1:0] multiplicand,\n input multiplicand_valid, \n output reg [WIDTH:0] en_multiplicand, // native EN-T encoding is sent to tensorcore local memory or local rf.\n output en_multiplicand_valid\n );\n\nwire [WIDTH-1:0] encoder_input;\nwire [ENCODER_WIDTH-1:0] en_multiplicand_ins;\nwire [TIMES-1:0] en_t_c_out;\nreg [WIDTH-1:0] multiplicand_reg;\n\nassign encoder_input = (multiplicand_reg != 8'b10000000) ? {1'b0,multiplicand_reg[WIDTH-2:0]} : 8'b10000000;\nassign en_multiplicand_ins[ENCODER_WIDTH-1] = multiplicand_reg[WIDTH-1];\n\ngenvar i;\ngenerate for(i = 0; i < TIMES; i = i + 1) begin: gen_encoder \n if(i==0) begin\n assign en_multiplicand_ins[1:0] = multiplicand_reg[1:0];\n end\n else if (i==1)begin\n encoder ins_encoder\n (.A(encoder_input[2*i-1:2*i-2]),\n .C_IN(1'b0), \n .B(encoder_input[2*i+1:2*i]), \n .en_t_c_out(en_t_c_out[i]), \n .EN_B(en_multiplicand_ins[2*i+1:2*i]));\n end\n else begin\n encoder ins_encoder\n (.A(encoder_input[2*i-1:2*i-2]),\n .C_IN(en_t_c_out[i-1]), \n .B(encoder_input[2*i+1:2*i]), \n .en_t_c_out(en_t_c_out[i]), \n .EN_B(en_multiplicand_ins[2*i+1:2*i]));\n end \nend \nendgenerate \n\n\nalways @(posedge clk or negedge rst_n) begin\n\tif (!rst_n) begin\n en_multiplicand <= 0;\n multiplicand_reg <= 0;\n end\n\telse begin\n en_multiplicand <= en_multiplicand_ins; \n //multiplicand belongs to [-128,127] range and operand with complement representation use this logic:\n multiplicand_reg <= (multiplicand[WIDTH-1] & (multiplicand[WIDTH-2:0] != 0)) ? ({1'b1,~multiplicand[WIDTH-2:0] + 1'b1}) : multiplicand; \n //multiplicand belongs to [-127,127] range and operand with sign-magnitude representation use this logic:\n //multiplicand_reg <= multiplicand; \n end\nend\n\nget_pipeline_mulwidth #(\n .N(2), \n .WIDTH(1) \n) pipeline_en_multiplicand_valid (\n .clk(clk), \n .rst_n(rst_n), \n .signal(multiplicand_valid), \n .pipeline_signal(en_multiplicand_valid) \n);\n\nendmodule\n\n\nmodule encoder(A, C_IN, B, en_t_c_out, EN_B);\n\ninput wire [1:0] A;\ninput wire C_IN;\ninput wire [1:0] B;\n\noutput wire en_t_c_out;\noutput wire [1:0] EN_B;\n\nassign en_t_c_out = (A[0] & A[1]) | (A[1] & C_IN); \nassign EN_B = B + en_t_c_out;\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_mac_based/top.v", "`timescale 1ns / 1ps\nmodule top #\n(\n parameter N = 8, //CHANGE\n parameter WIDTH = 8, \n parameter ACC_WIDTH = 2*WIDTH + $clog2(N) \n)\n(\n input wire rst_n ,\n input wire clk ,\n input wire [N*N*WIDTH-1 :0] A ,\n input wire [N*N*WIDTH-1 :0] B ,\n output wire [N*N*ACC_WIDTH-1 :0] result \n);\n\nreg [N*N*WIDTH-1 :0] A_reg ;\nreg [N*N*WIDTH-1 :0] B_reg ;\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n A_reg<={(N*N*WIDTH){1'b0}};\n B_reg<={(N*N*WIDTH){1'b0}};\n end\n else begin\n A_reg<=A;\n B_reg<=B;\n end\nend\n\n\nwire signed [WIDTH-1:0] d_x [0:N-1][0:N-1][0:N-1];\nwire signed [ACC_WIDTH-1:0] d_y [0:N-1][0:N-1][0:N-1];\nwire signed [WIDTH-1:0] d_z [0:N-1][0:N-1][0:N-1];\n\n\n genvar x, y, z;\n generate\n for (z = 0; z < N; z = z + 1 ) begin\n for(x = 0; x < N; x = x + 1) begin\n for (y = 0; y < N; y = y + 1 ) begin\n if(z==0) begin\n if(x==0) begin\n if(y==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE //(1)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p ({ACC_WIDTH{1'b0}} ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n ); \n end\n else if(y==N-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(3)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (result[N*ACC_WIDTH*z+(x+1)*ACC_WIDTH-1 : ACC_WIDTH*N*z+x*ACC_WIDTH] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(2)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n );\n end\n end\n else begin\n if(y==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE //(6)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p ({ACC_WIDTH{1'b0}} ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n ); \n end\n else if(y==N-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(5)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (result[N*ACC_WIDTH*z+(x+1)*ACC_WIDTH-1 : ACC_WIDTH*N*z+x*ACC_WIDTH] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(4)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n );\n end \n end\n end\n else begin\n if(x==0) begin\n if(y==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE //(7)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p ({ACC_WIDTH{1'b0}} ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n ); \n end\n else if(y==N-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(9)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (result[N*ACC_WIDTH*z+(x+1)*ACC_WIDTH-1 : ACC_WIDTH*N*z+x*ACC_WIDTH] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(8)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n );\n end\n end\n else begin\n if(y==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE //(10)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p ({ACC_WIDTH{1'b0}} ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n ); \n end\n else if(y==N-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(12)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (result[N*ACC_WIDTH*z+(x+1)*ACC_WIDTH-1 : ACC_WIDTH*N*z+x*ACC_WIDTH] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(11)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n );\n end \n end\n end\n end\n end\n end\n endgenerate\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_mac_based/top.v", "// Calculate matrix (A*B)\n// Size of A is (M*K), size of B is (K*N), and A_H = K, B_W = N, B is weight\n// Size of output matirx A*B is (M*N)\n\nmodule top #\n(\n parameter A_H = 16, \n parameter B_W = 16, \n parameter WIDTH = 8,\n // parameter ACC_WIDTH = 32 \n parameter ACC_WIDTH = 2*WIDTH + $clog2(A_H)\n)\n(\n input wire clk ,\n input wire rst_n ,\n input weight_wen ,\n input [A_H*WIDTH-1 :0] weight_din ,\n input wire [A_H*WIDTH-1 :0] A ,\n output wire [B_W*ACC_WIDTH-1 :0] result \n);\n\nreg [A_H*WIDTH-1 :0] A_reg ;\nreg [A_H*WIDTH-1 :0] weight_din_reg;\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n A_reg<={(A_H*WIDTH){1'b0}};\n weight_din_reg <= {(B_W*WIDTH){1'b0}};\n end\n else begin\n A_reg<=A;\n weight_din_reg <= weight_din;\n end\nend\n\n\nwire signed [ACC_WIDTH-1:0] row [0:B_W-1][0:A_H-1];\nwire signed [WIDTH-1:0] col [0:B_W-1][0:A_H-1];\n\n\n genvar i, j;\n generate\n for (i = 0; i < B_W; i = i + 1 ) begin\n for(j = 0; j < A_H; j = j + 1) begin\n if(j==0) begin\n if(i==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .weight_wen (weight_wen ),\n .weight_din (weight_din_reg[(j+1)*WIDTH-1:j*WIDTH] ),\n .a (A_reg[(j+1)*WIDTH-1:j*WIDTH] ),\n .partial_result ({ACC_WIDTH{1'b0}} ), // or input\n .row (row[i][j] ),\n .col (col[i][j] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .weight_wen (weight_wen ),\n .weight_din (col[i-1][j] ),\n .a (col[i-1][j] ),\n .partial_result ({ACC_WIDTH{1'b0}} ), // or input\n .row (row[i][j] ),\n .col (col[i][j] )\n ); \n end\n end\n else if (i==0) begin\n if(j==A_H-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .weight_wen (weight_wen ),\n .weight_din (weight_din_reg[(j+1)*WIDTH-1:j*WIDTH] ),\n .a (A_reg[(j+1)*WIDTH-1:j*WIDTH] ),\n .partial_result (row[i][j-1] ),\n .row (result[(i+1)*ACC_WIDTH-1 :i*ACC_WIDTH] ),\n .col (col[i][j] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .weight_wen (weight_wen ),\n .weight_din (weight_din_reg[(j+1)*WIDTH-1:j*WIDTH] ),\n .a (A_reg[(j+1)*WIDTH-1:j*WIDTH] ),\n .partial_result (row[i][j-1] ),\n .row (row[i][j] ),\n .col (col[i][j] )\n ); \n end\n end\n else if (j==A_H-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .weight_wen (weight_wen ),\n .weight_din (col[i-1][j] ),\n .a (col[i-1][j] ),\n .partial_result (row[i][j-1] ),\n .row (result[(i+1)*ACC_WIDTH-1 :i*ACC_WIDTH] ),\n .col (col[i][j] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .weight_wen (weight_wen ),\n .weight_din (col[i-1][j] ),\n .a (col[i-1][j] ),\n .partial_result (row[i][j-1] ),\n .row (row[i][j] ),\n .col (col[i][j] )\n ); \n end\n end\n end\nendgenerate\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/top.v", "`timescale 1ns / 1ps\n\n// Calculate matrix (A*B)\n// Size of A is (A_H*A_W), size of B is (B_H*B_W), and A_W = B_H\n// Size of output matirx A*B is (A_H*B_W)\n\nmodule top #\n(\n parameter N = 8, //CHANGE\n parameter WIDTH = 8, \n parameter ACC_WIDTH = 2*WIDTH + $clog2(N) \n)\n(\n input wire rst_n ,\n input wire clk ,\n input wire [N*N*WIDTH-1 :0] A ,\n input wire [N*N*WIDTH-1 :0] B ,\n output wire [N*N*2*ACC_WIDTH-1 :0] result \n);\n\nreg [N*N*WIDTH-1 :0] A_reg ;\nreg [N*N*WIDTH-1 :0] B_reg ;\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n A_reg<={(N*N*WIDTH){1'b0}};\n B_reg<={(N*N*WIDTH){1'b0}};\n end\n else begin\n A_reg<=A;\n B_reg<=B;\n end\nend\n\n\nwire signed [WIDTH-1:0] d_x [0:N-1][0:N-1][0:N-1];\nwire signed [2*ACC_WIDTH-1:0] d_y [0:N-1][0:N-1][0:N-1];\nwire signed [WIDTH-1:0] d_z [0:N-1][0:N-1][0:N-1];\n\n\n genvar x, y, z;\n generate\n for (z = 0; z < N; z = z + 1 ) begin\n for(x = 0; x < N; x = x + 1) begin\n for (y = 0; y < N; y = y + 1 ) begin\n if(z==0) begin\n if(x==0) begin\n if(y==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE //(1)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p ({2*ACC_WIDTH{1'b0}} ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n ); \n end\n else if(y==N-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(3)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (result[N*2*ACC_WIDTH*z+(x+1)*2*ACC_WIDTH-1 : 2*ACC_WIDTH*N*z+x*2*ACC_WIDTH] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(2)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n );\n end\n end\n else begin\n if(y==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE //(6)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p ({2*ACC_WIDTH{1'b0}} ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n ); \n end\n else if(y==N-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(5)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (result[N*2*ACC_WIDTH*z+(x+1)*2*ACC_WIDTH-1 : 2*ACC_WIDTH*N*z+x*2*ACC_WIDTH] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(4)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n );\n end \n end\n end\n else begin\n if(x==0) begin\n if(y==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE //(7)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p ({2*ACC_WIDTH{1'b0}} ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n ); \n end\n else if(y==N-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(9)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (result[N*2*ACC_WIDTH*z+(x+1)*2*ACC_WIDTH-1 : 2*ACC_WIDTH*N*z+x*2*ACC_WIDTH] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(8)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n );\n end\n end\n else begin\n if(y==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE //(10)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p ({2*ACC_WIDTH{1'b0}} ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n ); \n end\n else if(y==N-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(12)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (result[N*2*ACC_WIDTH*z+(x+1)*2*ACC_WIDTH-1 : 2*ACC_WIDTH*N*z+x*2*ACC_WIDTH] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(11)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n );\n end \n end\n end\n end\n end\n end\n endgenerate\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT3_OPT4C/pe/get_pipline_mulwidth.v", "module get_pipeline_mulwidth #(\n parameter N = 4,\n parameter WIDTH = 8 \n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] signal,\n output wire [WIDTH-1:0] pipeline_signal\n);\n\n\nreg [WIDTH-1:0] pipeline_regs [N-1:0];\n\n\n genvar i;\n generate\n for (i = 0; i < N; i = i + 1) begin : pipeline_stage\n always @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n pipeline_regs[i] <= 0; \n end else begin\n if (i == 0) begin\n pipeline_regs[i] <= signal; \n end else begin\n pipeline_regs[i] <= pipeline_regs[i-1]; \n end\n end\n end\n end\n endgenerate\n\n\n assign pipeline_signal = pipeline_regs[N-1];\n\nendmodule\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT2/get_pipline_mulwidth.v", "module get_pipeline_mulwidth #(\n parameter N = 4,\n parameter WIDTH = 8 \n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] signal,\n output wire [WIDTH-1:0] pipeline_signal\n);\n\n\nreg [WIDTH-1:0] pipeline_regs [N-1:0];\n\n\n genvar i;\n generate\n for (i = 0; i < N; i = i + 1) begin : pipeline_stage\n always @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n pipeline_regs[i] <= 0; \n end else begin\n if (i == 0) begin\n pipeline_regs[i] <= signal; \n end else begin\n pipeline_regs[i] <= pipeline_regs[i-1]; \n end\n end\n end\n end\n endgenerate\n\n\n assign pipeline_signal = pipeline_regs[N-1];\n\nendmodule\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT2/vector_encoder.sv", "module vector_encoder(\n input clk,\n input [127:0] operand_a,\n output reg [3:0] bit_enable [0:15],\n output reg [7:0] partial_product_select [0:15]\n);\n\nwire [3:0] bit_valid [0:15];\nwire [7:0] encoder_nub [0:15];\nreg [127:0] sync_operand ;\n\ngenvar i;\ngenerate\n for(i = 0; i < 16; i = i + 1) begin\n en_t_encoder en_t_preencoder(\n .clk(clk),\n .multiplicand(sync_operand[8*(i+1)-1:8*i]),\n .cal_encode_nub(encoder_nub[i]),\n .bit_enable(bit_valid[i])\n );\n end \nendgenerate\n\nalways @(posedge clk) begin\n sync_operand <= operand_a;\n bit_enable <= bit_valid;\n partial_product_select <= encoder_nub;\nend\n\nendmodule\n\n\n\nmodule en_t_encoder(\n input clk,\n input [7:0] multiplicand, \n output reg [7:0] cal_encode_nub,\n output reg [3:0] bit_enable\n );\n\nwire [7:0] encode_input;\nwire [2:0] c_out;\nwire [7:0] encode_nub;\n\n// covert to bit_enable-Magnitude\nassign encode_input = multiplicand[7] ? ((multiplicand[6:0] == 0) ? 8'b10000000 : {1'b0,~multiplicand[6:0] + 1'b1}) : {1'b0,multiplicand[6:0]};\n\ngenvar i;\ngenerate for(i = 0; i < 4; i = i + 1) begin: gen_encode_nub \n if(i==0) begin\n assign encode_nub[1:0] = encode_input[1:0];\n end\n else if (i==1) begin\n encoder_1 en_t\n (.A(encode_input[2*i-1:2*i-2]),\n .B(encode_input[2*i+1:2*i]), \n .c_out(c_out[i]), \n .en_b(encode_nub[2*i+1:2*i])\n );\n end\n else if (i==3) begin\n encoder_3 en_t\n (.A(encode_input[2*i-1:2*i-2]),\n .c_in(c_out[i-1]), \n .B(encode_input[2*i+1:2*i]), \n .en_b(encode_nub[2*i+1:2*i])\n );\n end\n else begin\n encoder en_t\n (.A(encode_input[2*i-1:2*i-2]),\n .c_in(c_out[i-1]), \n .B(encode_input[2*i+1:2*i]), \n .c_out(c_out[i]), \n .en_b(encode_nub[2*i+1:2*i])\n );\n end \nend \nendgenerate \n\n\ngenerate \n for (i = 0 ; i < 4; i = i + 1) begin\n always @(posedge clk) begin\n if(encode_nub[2*i+1:2*i] == 2'b00) begin\n bit_enable[i] <= 0;\n cal_encode_nub[2*i+1:2*i] <= 0;\n end\n else begin\n bit_enable[i] <= 1;\n cal_encode_nub[2*i+1:2*i] <= {multiplicand[7]^encode_nub[2*i+1],encode_nub[2*i]};\n end\n end\n end\nendgenerate\n\nendmodule\n\n\nmodule encoder_1(A, B, c_out, en_b);\n\ninput wire [1:0] A;\ninput wire [1:0] B;\n \noutput wire c_out;\noutput wire [1:0] en_b;\n\nassign c_out = (A[0] & A[1]); \nassign en_b = B + c_out;\n\nendmodule\n\nmodule encoder(A, c_in, B, c_out, en_b);\n\ninput wire [1:0] A;\ninput wire c_in;\ninput wire [1:0] B;\n \noutput wire c_out;\noutput wire [1:0] en_b;\n\nassign c_out = (A[0] & A[1]) | (A[1] & c_in); \nassign en_b = B + c_out;\n\nendmodule\n\nmodule encoder_3(A, c_in, B, en_b);\n\ninput wire [1:0] A;\ninput wire c_in;\ninput wire [1:0] B;\noutput wire [1:0] en_b;\n\nwire c_out;\nassign c_out = (A[0] & A[1]) | (A[1] & c_in); \nassign en_b = B + c_out;\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT2/DW02_tree.sv", "//-----------------------------------------------------------------------------------\n//\n// ABSTRACT: Wallace Tree Summer with Carry Save output\n//\n//------------------------------------------------------------------------------\n//\n\n // synopsys translate_off\n// `ifdef VCS\n// `include \"DW02_tree.v\"\n// `else\n // synopsys translate_on\n\nmodule DW02_tree( INPUT, OUT0, OUT1 );\n\n// parameters\nparameter integer num_inputs = 8;\nparameter integer input_width = 8;\nparameter integer verif_en = 1;\n\n//-----------------------------------------------------------------------------\n// ports\ninput [num_inputs*input_width-1 : 0]\tINPUT;\noutput [input_width-1:0]\t\tOUT0, OUT1;\n\n//-----------------------------------------------------------------------------\n// synopsys translate_off\nreg [input_width-1:0]\t\tOII0OOOI, O001l0I0;\n\n//-----------------------------------------------------------------------------\n \n \n// initial begin : parameter_check\n// integer param_err_flg;\n\n// param_err_flg = 0;\n \n \n// if (num_inputs < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter num_inputs (lower bound: 1)\",\n// \tnum_inputs );\n// end\n \n// if (input_width < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter input_width (lower bound: 1)\",\n// \tinput_width );\n// end\n \n// if ( (verif_en < 0) || (verif_en > 1) ) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter verif_en (legal range: 0 to 1)\",\n// \tverif_en );\n// end\n \n// if ( param_err_flg == 1) begin\n// $display(\n// \"%m :\\n Simulation aborted due to invalid parameter value(s)\");\n// $finish;\n// end\n\n// end // parameter_check \n\n\n// `ifndef DW_SUPPRESS_WARN\n// initial begin : verif_en_warning\n// $display(\"The parameter verif_en is set to 0 for this simulator.\\nOther values for verif_en are enabled only for VCS.\");\n// end // verif_en_warning\n// `endif\n\n//-----------------------------------------------------------------------------\n\n\n\nalways @ (INPUT) begin : IIIIO1Ol\n reg [input_width-1 : 0] I0lII01I [0 : num_inputs-1];\n reg [input_width-1 : 0] l10III00 [0 : num_inputs-1];\n reg [input_width-1 : 0] IIIO00Ol, lI0OII0O;\n integer I1I1O00I, O1OIIOII, IlI01lIO;\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII=O1OIIOII+1) begin\n for (IlI01lIO=0 ; IlI01lIO < input_width ; IlI01lIO=IlI01lIO+1) begin\n IIIO00Ol[IlI01lIO] = INPUT[O1OIIOII*input_width+IlI01lIO];\n end // for IlI01lIO\n I0lII01I[O1OIIOII] = IIIO00Ol;\n end // for O1OIIOII\n\n I1I1O00I = num_inputs;\n\n while (I1I1O00I > 2)\n begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I/3) ; O1OIIOII = O1OIIOII+1) begin\n l10III00[O1OIIOII*2] = I0lII01I[O1OIIOII*3] ^ I0lII01I[O1OIIOII*3+1] ^ I0lII01I[O1OIIOII*3+2];\n\n lI0OII0O = (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+1]) |\n (I0lII01I[O1OIIOII*3+1] & I0lII01I[O1OIIOII*3+2]) |\n (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+2]);\n\n l10III00[O1OIIOII*2+1] = lI0OII0O << 1;\n end\n if ((I1I1O00I % 3) > 0) begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I % 3) ; O1OIIOII = O1OIIOII + 1)\n l10III00[2 * (I1I1O00I/3) + O1OIIOII] = I0lII01I[3 * (I1I1O00I/3) + O1OIIOII];\n end\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII = O1OIIOII + 1)\n I0lII01I[O1OIIOII] = l10III00[O1OIIOII];\n I1I1O00I = I1I1O00I - (I1I1O00I/3);\n end\n OII0OOOI = I0lII01I[0];\n if (I1I1O00I > 1)\n O001l0I0 = I0lII01I[1];\n else\n O001l0I0 = {input_width{1'b0}};\nend // IIIIO1Ol\n\n\nassign OUT0 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : OII0OOOI;\nassign OUT1 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : O001l0I0;\n\n// synopsys translate_on\n\nendmodule\n // synopsys translate_off\n// `endif\n // synopsys translate_on\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/DW02_tree.sv", "//-----------------------------------------------------------------------------------\n//\n// ABSTRACT: Wallace Tree Summer with Carry Save output\n//\n//------------------------------------------------------------------------------\n//\n\n // synopsys translate_off\n// `ifdef VCS\n// `include \"DW02_tree.v\"\n// `else\n // synopsys translate_on\n\nmodule DW02_tree( INPUT, OUT0, OUT1 );\n\n// parameters\nparameter integer num_inputs = 8;\nparameter integer input_width = 8;\nparameter integer verif_en = 1;\n\n//-----------------------------------------------------------------------------\n// ports\ninput [num_inputs*input_width-1 : 0]\tINPUT;\noutput [input_width-1:0]\t\tOUT0, OUT1;\n\n//-----------------------------------------------------------------------------\n// synopsys translate_off\nreg [input_width-1:0]\t\tOII0OOOI, O001l0I0;\n\n//-----------------------------------------------------------------------------\n \n \n// initial begin : parameter_check\n// integer param_err_flg;\n\n// param_err_flg = 0;\n \n \n// if (num_inputs < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter num_inputs (lower bound: 1)\",\n// \tnum_inputs );\n// end\n \n// if (input_width < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter input_width (lower bound: 1)\",\n// \tinput_width );\n// end\n \n// if ( (verif_en < 0) || (verif_en > 1) ) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter verif_en (legal range: 0 to 1)\",\n// \tverif_en );\n// end\n \n// if ( param_err_flg == 1) begin\n// $display(\n// \"%m :\\n Simulation aborted due to invalid parameter value(s)\");\n// $finish;\n// end\n\n// end // parameter_check \n\n\n// `ifndef DW_SUPPRESS_WARN\n// initial begin : verif_en_warning\n// $display(\"The parameter verif_en is set to 0 for this simulator.\\nOther values for verif_en are enabled only for VCS.\");\n// end // verif_en_warning\n// `endif\n\n//-----------------------------------------------------------------------------\n\n\n\nalways @ (INPUT) begin : IIIIO1Ol\n reg [input_width-1 : 0] I0lII01I [0 : num_inputs-1];\n reg [input_width-1 : 0] l10III00 [0 : num_inputs-1];\n reg [input_width-1 : 0] IIIO00Ol, lI0OII0O;\n integer I1I1O00I, O1OIIOII, IlI01lIO;\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII=O1OIIOII+1) begin\n for (IlI01lIO=0 ; IlI01lIO < input_width ; IlI01lIO=IlI01lIO+1) begin\n IIIO00Ol[IlI01lIO] = INPUT[O1OIIOII*input_width+IlI01lIO];\n end // for IlI01lIO\n I0lII01I[O1OIIOII] = IIIO00Ol;\n end // for O1OIIOII\n\n I1I1O00I = num_inputs;\n\n while (I1I1O00I > 2)\n begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I/3) ; O1OIIOII = O1OIIOII+1) begin\n l10III00[O1OIIOII*2] = I0lII01I[O1OIIOII*3] ^ I0lII01I[O1OIIOII*3+1] ^ I0lII01I[O1OIIOII*3+2];\n\n lI0OII0O = (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+1]) |\n (I0lII01I[O1OIIOII*3+1] & I0lII01I[O1OIIOII*3+2]) |\n (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+2]);\n\n l10III00[O1OIIOII*2+1] = lI0OII0O << 1;\n end\n if ((I1I1O00I % 3) > 0) begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I % 3) ; O1OIIOII = O1OIIOII + 1)\n l10III00[2 * (I1I1O00I/3) + O1OIIOII] = I0lII01I[3 * (I1I1O00I/3) + O1OIIOII];\n end\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII = O1OIIOII + 1)\n I0lII01I[O1OIIOII] = l10III00[O1OIIOII];\n I1I1O00I = I1I1O00I - (I1I1O00I/3);\n end\n OII0OOOI = I0lII01I[0];\n if (I1I1O00I > 1)\n O001l0I0 = I0lII01I[1];\n else\n O001l0I0 = {input_width{1'b0}};\nend // IIIIO1Ol\n\n\nassign OUT0 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : OII0OOOI;\nassign OUT1 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : O001l0I0;\n\n// synopsys translate_on\n\nendmodule\n // synopsys translate_off\n// `endif\n // synopsys translate_on\n"], ["/High-Performance-Tensor-Processing-Engines/OPT3_OPT4C/pe/DW02_tree.sv", "//-----------------------------------------------------------------------------------\n//\n// ABSTRACT: Wallace Tree Summer with Carry Save output\n//\n//------------------------------------------------------------------------------\n//\n\n // synopsys translate_off\n// `ifdef VCS\n// `include \"DW02_tree.v\"\n// `else\n // synopsys translate_on\n\nmodule DW02_tree( INPUT, OUT0, OUT1 );\n\n// parameters\nparameter integer num_inputs = 8;\nparameter integer input_width = 8;\nparameter integer verif_en = 1;\n\n//-----------------------------------------------------------------------------\n// ports\ninput [num_inputs*input_width-1 : 0]\tINPUT;\noutput [input_width-1:0]\t\tOUT0, OUT1;\n\n//-----------------------------------------------------------------------------\n// synopsys translate_off\nreg [input_width-1:0]\t\tOII0OOOI, O001l0I0;\n\n//-----------------------------------------------------------------------------\n \n \n// initial begin : parameter_check\n// integer param_err_flg;\n\n// param_err_flg = 0;\n \n \n// if (num_inputs < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter num_inputs (lower bound: 1)\",\n// \tnum_inputs );\n// end\n \n// if (input_width < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter input_width (lower bound: 1)\",\n// \tinput_width );\n// end\n \n// if ( (verif_en < 0) || (verif_en > 1) ) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter verif_en (legal range: 0 to 1)\",\n// \tverif_en );\n// end\n \n// if ( param_err_flg == 1) begin\n// $display(\n// \"%m :\\n Simulation aborted due to invalid parameter value(s)\");\n// $finish;\n// end\n\n// end // parameter_check \n\n\n// `ifndef DW_SUPPRESS_WARN\n// initial begin : verif_en_warning\n// $display(\"The parameter verif_en is set to 0 for this simulator.\\nOther values for verif_en are enabled only for VCS.\");\n// end // verif_en_warning\n// `endif\n\n//-----------------------------------------------------------------------------\n\n\n\nalways @ (INPUT) begin : IIIIO1Ol\n reg [input_width-1 : 0] I0lII01I [0 : num_inputs-1];\n reg [input_width-1 : 0] l10III00 [0 : num_inputs-1];\n reg [input_width-1 : 0] IIIO00Ol, lI0OII0O;\n integer I1I1O00I, O1OIIOII, IlI01lIO;\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII=O1OIIOII+1) begin\n for (IlI01lIO=0 ; IlI01lIO < input_width ; IlI01lIO=IlI01lIO+1) begin\n IIIO00Ol[IlI01lIO] = INPUT[O1OIIOII*input_width+IlI01lIO];\n end // for IlI01lIO\n I0lII01I[O1OIIOII] = IIIO00Ol;\n end // for O1OIIOII\n\n I1I1O00I = num_inputs;\n\n while (I1I1O00I > 2)\n begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I/3) ; O1OIIOII = O1OIIOII+1) begin\n l10III00[O1OIIOII*2] = I0lII01I[O1OIIOII*3] ^ I0lII01I[O1OIIOII*3+1] ^ I0lII01I[O1OIIOII*3+2];\n\n lI0OII0O = (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+1]) |\n (I0lII01I[O1OIIOII*3+1] & I0lII01I[O1OIIOII*3+2]) |\n (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+2]);\n\n l10III00[O1OIIOII*2+1] = lI0OII0O << 1;\n end\n if ((I1I1O00I % 3) > 0) begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I % 3) ; O1OIIOII = O1OIIOII + 1)\n l10III00[2 * (I1I1O00I/3) + O1OIIOII] = I0lII01I[3 * (I1I1O00I/3) + O1OIIOII];\n end\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII = O1OIIOII + 1)\n I0lII01I[O1OIIOII] = l10III00[O1OIIOII];\n I1I1O00I = I1I1O00I - (I1I1O00I/3);\n end\n OII0OOOI = I0lII01I[0];\n if (I1I1O00I > 1)\n O001l0I0 = I0lII01I[1];\n else\n O001l0I0 = {input_width{1'b0}};\nend // IIIIO1Ol\n\n\nassign OUT0 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : OII0OOOI;\nassign OUT1 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : O001l0I0;\n\n// synopsys translate_on\n\nendmodule\n // synopsys translate_off\n// `endif\n // synopsys translate_on\n"], ["/High-Performance-Tensor-Processing-Engines/OPT2/top_pe_tile.sv", "module top_pe_tile #(\n localparam RESULT_WIDTH = 20\n)(\n input clk,\n input weight_wen,\n input [7:0] weight_din,\n input [3:0] bit_enable [0:15],\n input [7:0] partial_product_select [0:15],\n output reg signed [RESULT_WIDTH-1:0] result,\n output reg [3:0] bit_enable_pip [0:15],\n output reg [7:0] partial_product_select_pip [0:15]\n);\n\nlocalparam REDUCE_WIDTH = 13;\n\n//*********range of partial_product in same bit-weight********/\n//** 9bit: -256 ≤ partial_product ≤ 254 /\n//** 13bit: -4096 ≤ 16 * partial_product ≤ 4064 /\n//************************************************************/\nwire [7:0] weight [0:15];\nwire signed [9:0] partial_product [0:15][0:3]; \nwire signed [REDUCE_WIDTH-1:0] csa_extend [0:15][0:3];\nwire [16*REDUCE_WIDTH-1:0] csa_input [0:3];\nwire [4*REDUCE_WIDTH-1:0] mid_result [0:3];\nwire signed [REDUCE_WIDTH-1:0] result_bw [0:3];\nwire signed [RESULT_WIDTH-1:0] bw_0;\nwire signed [RESULT_WIDTH-1:0] bw_1;\nwire signed [RESULT_WIDTH-1:0] bw_2;\nwire signed [RESULT_WIDTH-1:0] bw_3;\n\n\nweight_rf weight_buffer(\n .clk(clk),\n .wen(weight_wen),\n .din(weight_din),\n .weight(weight) \n);\n\ngenvar i,j;\ngenerate\n for (i=0;i<16;i=i+1) begin\n partial_product_select pps (\n .clk(clk),\n .weight(weight[i]),\n .bit_enable(bit_enable_pip[i]),\n .partial_product_select(partial_product_select_pip[i]),\n .partial_product(partial_product[i])\n );\n end\nendgenerate\n\ngenerate\n for (i=0;i<16;i=i+1) begin\n for (j=0;j<4;j=j+1) begin\n assign csa_extend[i][j] = $signed(partial_product[i][j]);\n end\n end\nendgenerate\n\ngenerate\n for (i=0;i<4;i=i+1) begin\n for (j=0;j<16;j=j+1) begin\n assign csa_input[i][(j+1)*REDUCE_WIDTH-1:j*REDUCE_WIDTH] = csa_extend[j][i];\n end\n end\nendgenerate\n\n\ngenerate\n for (i=0;i<4;i=i+1) begin\n\n tree_full_sum #(\n .K(4),\n .WIDTH(REDUCE_WIDTH)\n ) tree_stage_1_0 (\n .clk(clk),\n .csa_input({csa_input[i][1*REDUCE_WIDTH-1:0],\n csa_input[i][2*REDUCE_WIDTH-1:1*REDUCE_WIDTH],\n csa_input[i][3*REDUCE_WIDTH-1:2*REDUCE_WIDTH],\n csa_input[i][4*REDUCE_WIDTH-1:3*REDUCE_WIDTH]}),\n .full_sum(mid_result[i][1*REDUCE_WIDTH-1:0*REDUCE_WIDTH])\n );\n tree_full_sum #(\n .K(4),\n .WIDTH(REDUCE_WIDTH)\n ) tree_stage_1_1 (\n .clk(clk),\n .csa_input({csa_input[i][5*REDUCE_WIDTH-1:4*REDUCE_WIDTH],\n csa_input[i][6*REDUCE_WIDTH-1:5*REDUCE_WIDTH],\n csa_input[i][7*REDUCE_WIDTH-1:6*REDUCE_WIDTH],\n csa_input[i][8*REDUCE_WIDTH-1:7*REDUCE_WIDTH]}),\n .full_sum(mid_result[i][2*REDUCE_WIDTH-1:1*REDUCE_WIDTH])\n );\n tree_full_sum #(\n .K(4),\n .WIDTH(REDUCE_WIDTH)\n ) tree_stage_1_2 (\n .clk(clk),\n .csa_input({csa_input[i][9*REDUCE_WIDTH-1:8*REDUCE_WIDTH],\n csa_input[i][10*REDUCE_WIDTH-1:9*REDUCE_WIDTH],\n csa_input[i][11*REDUCE_WIDTH-1:10*REDUCE_WIDTH],\n csa_input[i][12*REDUCE_WIDTH-1:11*REDUCE_WIDTH]}),\n .full_sum(mid_result[i][3*REDUCE_WIDTH-1:2*REDUCE_WIDTH])\n );\n tree_full_sum #(\n .K(4),\n .WIDTH(REDUCE_WIDTH)\n ) tree_stage_1_3 (\n .clk(clk),\n .csa_input({csa_input[i][13*REDUCE_WIDTH-1:12*REDUCE_WIDTH],\n csa_input[i][14*REDUCE_WIDTH-1:13*REDUCE_WIDTH],\n csa_input[i][15*REDUCE_WIDTH-1:14*REDUCE_WIDTH],\n csa_input[i][16*REDUCE_WIDTH-1:15*REDUCE_WIDTH]}),\n .full_sum(mid_result[i][4*REDUCE_WIDTH-1:3*REDUCE_WIDTH])\n );\n end\nendgenerate\n\n\ngenerate\n for (i=0;i<4;i=i+1) begin\n tree_full_sum #(\n .K(4),\n .WIDTH(REDUCE_WIDTH)\n ) tree_stage_2 (\n .clk(clk),\n .csa_input({mid_result[i][1*REDUCE_WIDTH-1:0],\n mid_result[i][2*REDUCE_WIDTH-1:1*REDUCE_WIDTH],\n mid_result[i][3*REDUCE_WIDTH-1:2*REDUCE_WIDTH],\n mid_result[i][4*REDUCE_WIDTH-1:3*REDUCE_WIDTH]}),\n .full_sum(result_bw[i])\n );\n end\nendgenerate\n\n\nassign bw_0 = $signed(result_bw[0]);\nassign bw_1 = $signed({result_bw[1],2'b0});\nassign bw_2 = $signed({result_bw[2],4'b0});\nassign bw_3 = $signed({result_bw[3],6'b0});\n\ntree_full_sum #(\n .K(4),\n .WIDTH(RESULT_WIDTH)\n) tree_stage_3 (\n .clk(clk),\n .csa_input({bw_0,bw_1,bw_2,bw_3}),\n .full_sum(result)\n );\n\n// pipeline the bit_enable and partial_product_select\nalways @(posedge clk) begin\n bit_enable_pip <= bit_enable;\n partial_product_select_pip <= partial_product_select;\nend\n\nendmodule\n\n\n\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT2/tree_full_sum.sv", "module tree_full_sum #(\n parameter K = 16,\n parameter WIDTH = 13\n)(\n input clk,\n input [K*WIDTH-1:0] csa_input,\n output reg signed [WIDTH-1:0] full_sum\n);\n\nwire signed [WIDTH-1:0] acc_sum;\nwire signed [WIDTH-1:0] acc_carry;\n\ngenvar i;\ngenerate\n if(K == 4) begin\n always @(posedge clk) begin\n full_sum <= $signed(csa_input[1*WIDTH-1:0*WIDTH]) + $signed(csa_input[2*WIDTH-1:1*WIDTH]) + $signed(csa_input[3*WIDTH-1:2*WIDTH]) + $signed(csa_input[4*WIDTH-1:3*WIDTH]);\n end\n end\n else begin\n DW02_tree #(K, WIDTH, 1)\n ins_tree ( .INPUT(csa_input), .OUT0(acc_sum), .OUT1(acc_carry));\n always @(posedge clk) begin\n full_sum <= $signed(acc_sum) + $signed(acc_carry);\n end\n end\nendgenerate\n\n\n\n\nendmodule\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/dff_async.v", "module dff_async #(\n parameter WIDTH = 8\n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] d,\n output reg [WIDTH-1:0] q\n);\n\nalways @(posedge clk or negedge rst_n) begin\n if (!rst_n) begin\n q <= 0;\n end\n else begin\n q <= d;\n end\nend\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/opt1_mac.v", "module opt1_mac #(\n parameter ACC_WIDTH = 32,\n parameter INPUT_PIP = 1\n)(\n input wire clk,\n input wire rst_n,\n input wire [7:0] operand_a_in, \n input wire [7:0] operand_b_in, \n input wire signed [2*ACC_WIDTH-1:0] partial_result, \n output reg [ACC_WIDTH-1:0] acc_sum,\n output reg [ACC_WIDTH-1:0] acc_carry\n);\n\nreg [7:0] operand_a;\nreg [7:0] operand_b;\n\nwire signed [9:0] pp1;\nwire signed [9:0] pp2;\nwire signed [9:0] pp3;\nwire signed [9:0] pp4;\nwire [6*ACC_WIDTH-1 : 0] mul_reduce_csa_input;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp1;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp2;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp3;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp4;\nwire signed [ACC_WIDTH-1:0] reduce_acc_sum;\nwire signed [ACC_WIDTH-1:0] reduce_acc_carry;\n\nassign sign_extend_pp4 = $signed({pp4,6'b0});\nassign sign_extend_pp3 = $signed({pp3,4'b0});\nassign sign_extend_pp2 = $signed({pp2,2'b0});\nassign sign_extend_pp1 = $signed(pp1);\n\nassign mul_reduce_csa_input = {sign_extend_pp4,sign_extend_pp3,sign_extend_pp2,sign_extend_pp1,partial_result[0+:ACC_WIDTH],partial_result[ACC_WIDTH+:ACC_WIDTH]};\n\nbooth_pp_gen booth_pp_gen_inst(\n .operand_a(operand_a), \n .operand_b(operand_b), \n .pp1(pp1),\n .pp2(pp2),\n .pp3(pp3),\n .pp4(pp4)\n);\n\nDW02_tree #(6, ACC_WIDTH, 1)\n U2 ( .INPUT(mul_reduce_csa_input), .OUT0(reduce_acc_sum), .OUT1(reduce_acc_carry) );\n\nalways @(posedge clk) begin\n if (!rst_n) begin\n acc_sum <= 0;\n acc_carry <= 0;\n end\n else begin\n acc_sum <= reduce_acc_sum;\n acc_carry <= reduce_acc_carry;\n end\nend\n\ngenerate\n if(INPUT_PIP == 1) begin\n always @(posedge clk) begin\n operand_a <= operand_a_in;\n operand_b <= operand_b_in;\n end\n end\n else begin\n always @(*) begin\n operand_a = operand_a_in;\n operand_b = operand_b_in;\n end\n end\nendgenerate\n\n// dff_async #(\n// .WIDTH(ACC_WIDTH)) acc_sum_reg (\n// .clk(clk),\n// .rst_n(rst_n),\n// .d(reduce_acc_sum),\n// .q(acc_sum)\n// );\n\n// dff_async #(\n// .WIDTH(ACC_WIDTH)) acc_carry_reg (\n// .clk(clk),\n// .rst_n(rst_n),\n// .d(reduce_acc_carry),\n// .q(acc_carry)\n// );\n\n\n\n \nendmodule\n\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/opt1_mac.v", "module opt1_mac #(\n parameter ACC_WIDTH = 32,\n parameter INPUT_PIP = 1\n)(\n input wire clk,\n input wire rst_n,\n input wire [7:0] operand_a_in, \n input wire [7:0] operand_b_in, \n input wire signed [2*ACC_WIDTH-1:0] partial_result, \n output reg [ACC_WIDTH-1:0] acc_sum,\n output reg [ACC_WIDTH-1:0] acc_carry\n);\n\nreg [7:0] operand_a;\nreg [7:0] operand_b;\n\nwire signed [9:0] pp1;\nwire signed [9:0] pp2;\nwire signed [9:0] pp3;\nwire signed [9:0] pp4;\nwire [6*ACC_WIDTH-1 : 0] mul_reduce_csa_input;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp1;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp2;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp3;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp4;\nwire signed [ACC_WIDTH-1:0] reduce_acc_sum;\nwire signed [ACC_WIDTH-1:0] reduce_acc_carry;\n\nassign sign_extend_pp4 = $signed({pp4,6'b0});\nassign sign_extend_pp3 = $signed({pp3,4'b0});\nassign sign_extend_pp2 = $signed({pp2,2'b0});\nassign sign_extend_pp1 = $signed(pp1);\n\nassign mul_reduce_csa_input = {sign_extend_pp4,sign_extend_pp3,sign_extend_pp2,sign_extend_pp1,partial_result[0+:ACC_WIDTH],partial_result[ACC_WIDTH+:ACC_WIDTH]};\n\nbooth_pp_gen booth_pp_gen_inst(\n .operand_a(operand_a), \n .operand_b(operand_b), \n .pp1(pp1),\n .pp2(pp2),\n .pp3(pp3),\n .pp4(pp4)\n);\n\nDW02_tree #(6, ACC_WIDTH, 1)\n U2 ( .INPUT(mul_reduce_csa_input), .OUT0(reduce_acc_sum), .OUT1(reduce_acc_carry) );\n\nalways @(posedge clk) begin\n if (!rst_n) begin\n acc_sum <= 0;\n acc_carry <= 0;\n end\n else begin\n acc_sum <= reduce_acc_sum;\n acc_carry <= reduce_acc_carry;\n end\nend\n\ngenerate\n if(INPUT_PIP == 1) begin\n always @(posedge clk) begin\n operand_a <= operand_a_in;\n operand_b <= operand_b_in;\n end\n end\n else begin\n always @(*) begin\n operand_a = operand_a_in;\n operand_b = operand_b_in;\n end\n end\nendgenerate\n\n// dff_async #(\n// .WIDTH(ACC_WIDTH)) acc_sum_reg (\n// .clk(clk),\n// .rst_n(rst_n),\n// .d(reduce_acc_sum),\n// .q(acc_sum)\n// );\n\n// dff_async #(\n// .WIDTH(ACC_WIDTH)) acc_carry_reg (\n// .clk(clk),\n// .rst_n(rst_n),\n// .d(reduce_acc_carry),\n// .q(acc_carry)\n// );\n\n\n\n \nendmodule\n\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/opt1_mac.v", "module opt1_mac #(\n parameter ACC_WIDTH = 32,\n parameter INPUT_PIP = 1\n)(\n input wire clk,\n input wire rst_n,\n input wire [7:0] operand_a_in, \n input wire [7:0] operand_b_in, \n input wire clc, // clean_result_cache\n output reg [ACC_WIDTH-1:0] acc_sum,\n output reg [ACC_WIDTH-1:0] acc_carry\n);\n\nreg [7:0] operand_a;\nreg [7:0] operand_b;\n\nwire signed [9:0] pp1;\nwire signed [9:0] pp2;\nwire signed [9:0] pp3;\nwire signed [9:0] pp4;\nwire [6*ACC_WIDTH-1 : 0] mul_reduce_csa_input;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp1;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp2;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp3;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp4;\nwire signed [ACC_WIDTH-1:0] reduce_acc_sum;\nwire signed [ACC_WIDTH-1:0] reduce_acc_carry;\n\nassign sign_extend_pp4 = $signed({pp4,6'b0});\nassign sign_extend_pp3 = $signed({pp3,4'b0});\nassign sign_extend_pp2 = $signed({pp2,2'b0});\nassign sign_extend_pp1 = $signed(pp1);\n\nassign mul_reduce_csa_input = {sign_extend_pp4,sign_extend_pp3,sign_extend_pp2,sign_extend_pp1,acc_carry,acc_sum};\n\nbooth_pp_gen booth_pp_gen_inst(\n .operand_a(operand_a), \n .operand_b(operand_b), \n .pp1(pp1),\n .pp2(pp2),\n .pp3(pp3),\n .pp4(pp4)\n);\n\nDW02_tree #(6, ACC_WIDTH, 1)\n U2 ( .INPUT(mul_reduce_csa_input), .OUT0(reduce_acc_sum), .OUT1(reduce_acc_carry) );\n\nalways @(posedge clk) begin\n if (!rst_n) begin\n acc_sum <= 0;\n acc_carry <= 0;\n end\n else begin\n if(clc) begin\n acc_sum <= 0;\n acc_carry <= 0;\n end\n else begin\n acc_sum <= reduce_acc_sum;\n acc_carry <= reduce_acc_carry;\n end\n end\nend\n\ngenerate\n if(INPUT_PIP == 1) begin\n always @(posedge clk) begin\n operand_a <= operand_a_in;\n operand_b <= operand_b_in;\n end\n end\n else begin\n always @(*) begin\n operand_a = operand_a_in;\n operand_b = operand_b_in;\n end\n end\nendgenerate\n\n// dff_async #(\n// .WIDTH(ACC_WIDTH)) acc_sum_reg (\n// .clk(clk),\n// .rst_n(rst_n),\n// .d(reduce_acc_sum),\n// .q(acc_sum)\n// );\n\n// dff_async #(\n// .WIDTH(ACC_WIDTH)) acc_carry_reg (\n// .clk(clk),\n// .rst_n(rst_n),\n// .d(reduce_acc_carry),\n// .q(acc_carry)\n// );\n\n\n\n \nendmodule\n\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/opt1_mac.v", "module opt1_mac #(\n parameter ACC_WIDTH = 32,\n parameter INPUT_PIP = 1\n)(\n input wire clk,\n input wire rst_n,\n input wire [7:0] operand_a_in, \n input wire [7:0] operand_b_in, \n output reg [ACC_WIDTH-1:0] acc_sum,\n output reg [ACC_WIDTH-1:0] acc_carry\n);\n\nreg [7:0] operand_a;\nreg [7:0] operand_b;\n\nwire signed [9:0] pp1;\nwire signed [9:0] pp2;\nwire signed [9:0] pp3;\nwire signed [9:0] pp4;\nwire [6*ACC_WIDTH-1 : 0] mul_reduce_csa_input;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp1;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp2;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp3;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp4;\nwire signed [ACC_WIDTH-1:0] reduce_acc_sum;\nwire signed [ACC_WIDTH-1:0] reduce_acc_carry;\n\nassign sign_extend_pp4 = $signed({pp4,6'b0});\nassign sign_extend_pp3 = $signed({pp3,4'b0});\nassign sign_extend_pp2 = $signed({pp2,2'b0});\nassign sign_extend_pp1 = $signed(pp1);\n\nassign mul_reduce_csa_input = {sign_extend_pp4,sign_extend_pp3,sign_extend_pp2,sign_extend_pp1,acc_carry, acc_sum};\n\nbooth_pp_gen booth_pp_gen_inst(\n .operand_a(operand_a), \n .operand_b(operand_b), \n .pp1(pp1),\n .pp2(pp2),\n .pp3(pp3),\n .pp4(pp4)\n);\n\nDW02_tree #(6, ACC_WIDTH, 1)\n U2 ( .INPUT(mul_reduce_csa_input), .OUT0(reduce_acc_sum), .OUT1(reduce_acc_carry) );\n\nalways @(posedge clk) begin\n if (!rst_n) begin\n acc_sum <= 0;\n acc_carry <= 0;\n end\n else begin\n acc_sum <= reduce_acc_sum;\n acc_carry <= reduce_acc_carry;\n end\nend\n\ngenerate\n if(INPUT_PIP == 1) begin\n always @(posedge clk) begin\n operand_a <= operand_a_in;\n operand_b <= operand_b_in;\n end\n end\n else begin\n always @(*) begin\n operand_a = operand_a_in;\n operand_b = operand_b_in;\n end\n end\nendgenerate\n\n// dff_async #(\n// .WIDTH(ACC_WIDTH)) acc_sum_reg (\n// .clk(clk),\n// .rst_n(rst_n),\n// .d(reduce_acc_sum),\n// .q(acc_sum)\n// );\n\n// dff_async #(\n// .WIDTH(ACC_WIDTH)) acc_carry_reg (\n// .clk(clk),\n// .rst_n(rst_n),\n// .d(reduce_acc_carry),\n// .q(acc_carry)\n// );\n\n\n\n \nendmodule\n\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT2/top_tpe.sv", "module top_tpe #(\n parameter N = 32,\n localparam RESULT_WIDTH = 20\n)(\n \n input clk,\n input [127:0] operand_a,\n input weight_wen,\n input [8*N-1:0] weight_din,\n output [RESULT_WIDTH*N-1:0] result\n\n);\n\nwire [3:0] bit_enable [0:15];\nwire [7:0] partial_product_select [0:15];\nwire [3:0] bit_enable_pip [0:N-1][0:15];\nwire [7:0] partial_product_select_pip [0:N-1][0:15];\n\nvector_encoder encoder(\n .clk(clk),\n .operand_a(operand_a),\n .bit_enable(bit_enable),\n .partial_product_select(partial_product_select)\n);\n\ngenvar i;\ngenerate \n for (i = 0 ; i < N ; i = i + 1) begin\n if(i == 0) begin\n top_pe_tile pe_tile(\n .clk(clk),\n .weight_wen(weight_wen),\n .weight_din(weight_din[8*(i+1)-1:8*i]),\n .bit_enable(bit_enable),\n .partial_product_select(partial_product_select),\n .result(result[RESULT_WIDTH*(i+1)-1:RESULT_WIDTH*i]),\n .bit_enable_pip(bit_enable_pip[i]),\n .partial_product_select_pip(partial_product_select_pip[i])\n );\n end\n else begin\n top_pe_tile pe_tile(\n .clk(clk),\n .weight_wen(weight_wen),\n .weight_din(weight_din[8*(i+1)-1:8*i]),\n .bit_enable(bit_enable_pip[i-1]),\n .partial_product_select(partial_product_select_pip[i-1]),\n .result(result[RESULT_WIDTH*(i+1)-1:RESULT_WIDTH*i]),\n .bit_enable_pip(bit_enable_pip[i]),\n .partial_product_select_pip(partial_product_select_pip[i])\n );\n end\n end\nendgenerate\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT2/weight_rf.sv", "module weight_rf (\n input clk,\n input wen,\n input [7:0] din,\n output [7:0] weight [0:15]\n);\n\nreg [7:0] buffer [0:15];\n\nassign weight = buffer;\n\ngenvar i;\ngenerate\n for (i = 0; i < 16; i = i + 1) begin\n always @(posedge clk) begin\n if(wen) begin\n if (i==15)\n buffer[i] <= din;\n else \n buffer[i] <= buffer[i+1];\n end\n else\n buffer[i] <= buffer[i];\n end\n end\nendgenerate\n\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT3_OPT4C/pe/get_negedge.sv", "module get_negedge(\n input clk,\n input signal,\n output negedge_signal\n );\n\nreg save;\n\nalways @(posedge clk) begin\n save <= signal;\nend\n\nassign negedge_signal = ~signal & save;\n\nendmodule\n\n// get_negedge get_hit(\n// .clk(clk),\n// .signal(cache_hit),\n// .negedge_signal(negedge_cache_hit)\n// );"]], "task_instance_info": {"created_time": "2025-08-21 04:18:25", "created_task_model": "DeepSeek-R1", "class_skeleton": "module inv_unit (\n input wire a ,\n input wire b ,\n output wire xor_o , \n output wire or_o \n ) ; endmodule", "code_description": "This code segment functions to: Process two input signals by performing sequential logical operations to generate two distinct output signals representing exclusive and inclusive combinations of the inputs."}, "inference_content": {"inference_model": "DeepSeek-R1", "inference_result": "```verilog\n[TASK_BEGIN]\nmodule inv_unit (\n input wire a ,\n input wire b ,\n output wire xor_o , \n output wire or_o \n) ;\n assign xor_o = a ^ b;\n assign or_o = a | b;\nendmodule\n[TASK_END]\n```", "inference_time": "2025-08-21 04-18-41"}, "editdistance_info": {"edit_distance": 40.7767, "calculate_time": "2025-08-21 04:18:41", "true_code_clean": "module inv_unit(\n input wire a ,\n input wire b ,\n output wire xor_o , \n output wire or_o \n );\n wire aORb ; \n wire aNANDb ; \n assign aORb = a | b;\n assign aNANDb = ~(a & b);\n assign xor_o = (aORb & aNANDb);\n assign or_o = aORb;\nendmodule", "predict_code_clean": "module inv_unit (\n input wire a ,\n input wire b ,\n output wire xor_o , \n output wire or_o \n) ;\n assign xor_o = a ^ b;\n assign or_o = a | b;\nendmodule"}} +{"repo_name": "High-Performance-Tensor-Processing-Engines", "file_name": "/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/mac_pe/mac.v", "inference_info": {"prefix_code": "", "suffix_code": "\n", "middle_code": "module mac #\n(\n parameter WIDTH = 8,\n parameter ACC_WIDTH = 32\n)\n(\n input wire rst_n,\n input wire clk,\n input wire signed [WIDTH-1 :0] a,\n input wire signed [WIDTH-1 :0] b,\n output reg signed [ACC_WIDTH-1 :0] result\n);\nwire signed [15:0] result_p;\nreg signed [7:0] operand_a;\nreg signed [7:0] operand_b;\nassign result_p = $signed(operand_a) * $signed(operand_b) ;\nalways @(posedge clk) begin\n operand_a <= a;\n operand_b <= b;\nend\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n result <= 0;\n end\n else begin\n result <= result + $signed(result_p);\n end\nend\nendmodule", "code_description": null, "fill_type": "CLASS_TYPE", "language_type": "verilog", "sub_task_type": null}, "context_code": [["/High-Performance-Tensor-Processing-Engines/OPT3_OPT4C/pe/pe.v", "module pe #(\n parameter ACC_WIDTH = 26 //due to the same bit-weight reduction\n)(\n input clk,\n input rst_n,\n input clr,\n input wire [1:0] encoder_position_ins,\n input wire [7:0] operand_b_ins,\n output wire [51:0] result\n);\n\nwire signed [ACC_WIDTH-1:0] sum;\nwire signed [ACC_WIDTH-1:0] carry;\nwire signed [ACC_WIDTH-1:0] sum_input;\nwire signed [ACC_WIDTH-1:0] carry_input;\nreg signed [ACC_WIDTH-1:0] acc_sum;\nreg signed [ACC_WIDTH-1:0] acc_carry;\nreg [1:0] encoder_position;\nreg signed [7:0] operand_b;\n\n\nwire signed [8:0] b;\nwire signed [8:0] b_2;\nwire signed [8:0] neg_b;\nwire signed [9:0] neg_b_2;\nreg signed [9:0] mux_select_b;\nwire signed [ACC_WIDTH-1:0] mux_extend_b;\nwire [3*ACC_WIDTH-1:0] csa_input;\n\nassign b = $signed(operand_b);\nassign b_2 = {operand_b,1'b0};\nassign neg_b = ~b + 1'b1;\nassign neg_b_2 = {neg_b,1'b0};\nassign mux_extend_b = mux_select_b;\nassign sum_input = !clr ? 0 : acc_sum;\nassign carry_input = !clr ? 0 : acc_carry;\nassign csa_input = {mux_extend_b,sum_input,carry_input};\n\nalways @(*) begin\n case (encoder_position)\n 2'd0: mux_select_b = $signed(neg_b_2);\n 2'd1: mux_select_b = $signed(b);\n 2'd2: mux_select_b = $signed(b_2);\n 2'd3: mux_select_b = $signed(neg_b);\n endcase\nend\n\nDW02_tree #(3,ACC_WIDTH, 1)\n U1 ( .INPUT(csa_input), .OUT0(sum), .OUT1(carry) );\n\n always @(posedge clk or negedge rst_n) begin\n\tif (!rst_n) begin\n encoder_position <=0;\n operand_b <=0;\n\tend\n\telse begin\n encoder_position <= encoder_position_ins;\n operand_b <= operand_b_ins;\n\tend\nend\n\nalways @(posedge clk) begin\n acc_sum <= sum ;\n acc_carry <= carry;\nend\n\nassign result = {acc_sum,acc_carry};\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/pe.v", "module PE #\n(\n parameter WIDTH = 8,\n parameter ACC_WIDTH = 32\n)\n(\n input wire rst_n,\n input wire clk,\n input wire signed [WIDTH-1 :0] a,\n input wire signed [WIDTH-1 :0] b,\n input wire clc, // clean_result_cache\n\n output reg signed [WIDTH-1 :0] row,\n output reg signed [WIDTH-1 :0] col,\n output signed [2*ACC_WIDTH-1 :0] result\n);\n\n\nwire [ACC_WIDTH-1:0] acc_sum;\nwire [ACC_WIDTH-1:0] acc_carry;\nopt1_mac #(\n .ACC_WIDTH(ACC_WIDTH),\n .INPUT_PIP(0)\n) opt1_mac_test (\n .clk(clk),\n .rst_n(rst_n),\n .operand_a_in(a), \n .operand_b_in(b), \n .clc(clc), // input wire clean_result_cache\n .acc_sum(acc_sum),\n .acc_carry(acc_carry)\n);\nassign result = {acc_sum, acc_carry};\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n row <= 0;\n col <= 0;\n end\n else begin\n row <= a;\n col <= b;\n end\nend\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_mac_based/pe.v", "module PE #\n(\n parameter WIDTH = 8,\n parameter ACC_WIDTH = 32\n)\n(\n input wire rst_n,\n input wire clk,\n input wire signed [WIDTH-1 :0] a,\n input wire signed [WIDTH-1 :0] b,\n input wire clc, // clean_result_cache,\n\n output reg signed [WIDTH-1 :0] row,\n output reg signed [WIDTH-1 :0] col,\n output reg signed [ACC_WIDTH-1 :0] result\n);\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n result <= 0;\n end\n else begin\n if(clc)\n result <= 0;\n else\n result <= result + a * b ;\n end\nend\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n row <= 0;\n col <= 0;\n end\n else begin\n row <= a;\n col <= b;\n end\nend\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/PE.v", "`timescale 1ns / 1ps\n\n// b = w * a\nmodule PE #\n(\n parameter WIDTH = 8,\n parameter ACC_WIDTH = 24\n)\n(\n input wire rst_n,\n input wire clk,\n input wire signed [WIDTH-1 :0] i_z_a,\n input wire signed [WIDTH-1 :0] i_x_b,\n input wire signed [2*ACC_WIDTH-1 :0] i_y_p,\n\n output reg signed [WIDTH-1 :0] o_z_a,\n output reg signed [WIDTH-1 :0] o_x_b,\n output reg signed [2*ACC_WIDTH-1 :0] o_y_p\n);\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n o_z_a <= 0;\n o_x_b <= 0;\n end\n else begin\n o_z_a <= i_z_a; \n o_x_b <= i_x_b; \n end\nend\n\nwire [ACC_WIDTH-1:0] acc_sum;\nwire [ACC_WIDTH-1:0] acc_carry;\nalways @(*) begin\n if(!rst_n) begin\n o_y_p = 0;\n end\n else begin\n o_y_p = {acc_sum, acc_carry}; // partial_result + weight * a;\n end\nend\nopt1_mac #(\n .ACC_WIDTH(ACC_WIDTH),\n .INPUT_PIP(0)\n) opt1_mac_test (\n .clk(clk),\n .rst_n(rst_n),\n .operand_a_in(i_z_a), \n .operand_b_in(i_x_b), \n .partial_result(i_y_p),\n .acc_sum(acc_sum),\n .acc_carry(acc_carry)\n);\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_mac_based/pe.v", "`timescale 1ns / 1ps\n\n// b = w * a\nmodule PE #\n(\n parameter WIDTH = 8,\n parameter ACC_WIDTH = 24\n)\n(\n input wire rst_n,\n input wire clk,\n input wire signed [WIDTH-1 :0] i_z_a,\n input wire signed [WIDTH-1 :0] i_x_b,\n input wire signed [ACC_WIDTH-1 :0] i_y_p,\n\n output reg signed [WIDTH-1 :0] o_z_a,\n output reg signed [WIDTH-1 :0] o_x_b,\n output reg signed [ACC_WIDTH-1 :0] o_y_p\n);\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n o_y_p <= 0;\n end\n else begin\n o_y_p <= i_y_p + i_z_a*i_x_b; \n end\nend\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n o_z_a <= 0;\n o_x_b <= 0;\n end\n else begin\n o_z_a <= i_z_a; \n o_x_b <= i_x_b; \n end\nend\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/PE.v", "// b = w * a\nmodule PE #\n(\n parameter WIDTH = 8,\n parameter ACC_WIDTH = 24\n)\n(\n input wire rst_n ,\n input wire clk ,\n input wire weight_wen ,\n input [WIDTH-1 :0] weight_din ,\n input wire signed [WIDTH-1 :0] a ,\n input wire signed [2*ACC_WIDTH-1 :0] partial_result , \n\n output reg signed [WIDTH-1 :0] col ,\n output reg signed [2*ACC_WIDTH-1 :0] row \n);\n\n\nreg signed [WIDTH-1 :0] weight;\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n weight <= 0;\n end\n else begin\n if(weight_wen) begin\n weight <= weight_din; \n end\n else begin\n weight <= weight;\n end\n end\nend\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n col <= 0;\n end\n else begin\n if(weight_wen) begin\n col <= weight_din; \n end\n else begin\n col <= a;\n end\n end\nend\n\nwire [ACC_WIDTH-1:0] acc_sum;\nwire [ACC_WIDTH-1:0] acc_carry;\nalways @(*) begin\n if(!rst_n) begin\n row <= 0;\n end\n else begin\n row <= {acc_sum, acc_carry}; // partial_result + weight * a;\n end\nend\nopt1_mac #(\n .ACC_WIDTH(ACC_WIDTH),\n .INPUT_PIP(0)\n) opt1_mac_test (\n .clk(clk),\n .rst_n(rst_n),\n .operand_a_in(a), \n .operand_b_in(weight), \n .partial_result(partial_result),\n .acc_sum(acc_sum),\n .acc_carry(acc_carry)\n);\n\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/opt1_mac.v", "module opt1_mac #(\n parameter ACC_WIDTH = 32,\n parameter INPUT_PIP = 1\n)(\n input wire clk,\n input wire rst_n,\n input wire [7:0] operand_a_in, \n input wire [7:0] operand_b_in, \n output reg [ACC_WIDTH-1:0] acc_sum,\n output reg [ACC_WIDTH-1:0] acc_carry\n);\n\nreg [7:0] operand_a;\nreg [7:0] operand_b;\n\nwire signed [9:0] pp1;\nwire signed [9:0] pp2;\nwire signed [9:0] pp3;\nwire signed [9:0] pp4;\nwire [6*ACC_WIDTH-1 : 0] mul_reduce_csa_input;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp1;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp2;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp3;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp4;\nwire signed [ACC_WIDTH-1:0] reduce_acc_sum;\nwire signed [ACC_WIDTH-1:0] reduce_acc_carry;\n\nassign sign_extend_pp4 = $signed({pp4,6'b0});\nassign sign_extend_pp3 = $signed({pp3,4'b0});\nassign sign_extend_pp2 = $signed({pp2,2'b0});\nassign sign_extend_pp1 = $signed(pp1);\n\nassign mul_reduce_csa_input = {sign_extend_pp4,sign_extend_pp3,sign_extend_pp2,sign_extend_pp1,acc_carry, acc_sum};\n\nbooth_pp_gen booth_pp_gen_inst(\n .operand_a(operand_a), \n .operand_b(operand_b), \n .pp1(pp1),\n .pp2(pp2),\n .pp3(pp3),\n .pp4(pp4)\n);\n\nDW02_tree #(6, ACC_WIDTH, 1)\n U2 ( .INPUT(mul_reduce_csa_input), .OUT0(reduce_acc_sum), .OUT1(reduce_acc_carry) );\n\nalways @(posedge clk) begin\n if (!rst_n) begin\n acc_sum <= 0;\n acc_carry <= 0;\n end\n else begin\n acc_sum <= reduce_acc_sum;\n acc_carry <= reduce_acc_carry;\n end\nend\n\ngenerate\n if(INPUT_PIP == 1) begin\n always @(posedge clk) begin\n operand_a <= operand_a_in;\n operand_b <= operand_b_in;\n end\n end\n else begin\n always @(*) begin\n operand_a = operand_a_in;\n operand_b = operand_b_in;\n end\n end\nendgenerate\n\n// dff_async #(\n// .WIDTH(ACC_WIDTH)) acc_sum_reg (\n// .clk(clk),\n// .rst_n(rst_n),\n// .d(reduce_acc_sum),\n// .q(acc_sum)\n// );\n\n// dff_async #(\n// .WIDTH(ACC_WIDTH)) acc_carry_reg (\n// .clk(clk),\n// .rst_n(rst_n),\n// .d(reduce_acc_carry),\n// .q(acc_carry)\n// );\n\n\n\n \nendmodule\n\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/opt1_mac.v", "module opt1_mac #(\n parameter ACC_WIDTH = 32,\n parameter INPUT_PIP = 1\n)(\n input wire clk,\n input wire rst_n,\n input wire [7:0] operand_a_in, \n input wire [7:0] operand_b_in, \n input wire clc, // clean_result_cache\n output reg [ACC_WIDTH-1:0] acc_sum,\n output reg [ACC_WIDTH-1:0] acc_carry\n);\n\nreg [7:0] operand_a;\nreg [7:0] operand_b;\n\nwire signed [9:0] pp1;\nwire signed [9:0] pp2;\nwire signed [9:0] pp3;\nwire signed [9:0] pp4;\nwire [6*ACC_WIDTH-1 : 0] mul_reduce_csa_input;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp1;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp2;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp3;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp4;\nwire signed [ACC_WIDTH-1:0] reduce_acc_sum;\nwire signed [ACC_WIDTH-1:0] reduce_acc_carry;\n\nassign sign_extend_pp4 = $signed({pp4,6'b0});\nassign sign_extend_pp3 = $signed({pp3,4'b0});\nassign sign_extend_pp2 = $signed({pp2,2'b0});\nassign sign_extend_pp1 = $signed(pp1);\n\nassign mul_reduce_csa_input = {sign_extend_pp4,sign_extend_pp3,sign_extend_pp2,sign_extend_pp1,acc_carry,acc_sum};\n\nbooth_pp_gen booth_pp_gen_inst(\n .operand_a(operand_a), \n .operand_b(operand_b), \n .pp1(pp1),\n .pp2(pp2),\n .pp3(pp3),\n .pp4(pp4)\n);\n\nDW02_tree #(6, ACC_WIDTH, 1)\n U2 ( .INPUT(mul_reduce_csa_input), .OUT0(reduce_acc_sum), .OUT1(reduce_acc_carry) );\n\nalways @(posedge clk) begin\n if (!rst_n) begin\n acc_sum <= 0;\n acc_carry <= 0;\n end\n else begin\n if(clc) begin\n acc_sum <= 0;\n acc_carry <= 0;\n end\n else begin\n acc_sum <= reduce_acc_sum;\n acc_carry <= reduce_acc_carry;\n end\n end\nend\n\ngenerate\n if(INPUT_PIP == 1) begin\n always @(posedge clk) begin\n operand_a <= operand_a_in;\n operand_b <= operand_b_in;\n end\n end\n else begin\n always @(*) begin\n operand_a = operand_a_in;\n operand_b = operand_b_in;\n end\n end\nendgenerate\n\n// dff_async #(\n// .WIDTH(ACC_WIDTH)) acc_sum_reg (\n// .clk(clk),\n// .rst_n(rst_n),\n// .d(reduce_acc_sum),\n// .q(acc_sum)\n// );\n\n// dff_async #(\n// .WIDTH(ACC_WIDTH)) acc_carry_reg (\n// .clk(clk),\n// .rst_n(rst_n),\n// .d(reduce_acc_carry),\n// .q(acc_carry)\n// );\n\n\n\n \nendmodule\n\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/opt1_mac.v", "module opt1_mac #(\n parameter ACC_WIDTH = 32,\n parameter INPUT_PIP = 1\n)(\n input wire clk,\n input wire rst_n,\n input wire [7:0] operand_a_in, \n input wire [7:0] operand_b_in, \n input wire signed [2*ACC_WIDTH-1:0] partial_result, \n output reg [ACC_WIDTH-1:0] acc_sum,\n output reg [ACC_WIDTH-1:0] acc_carry\n);\n\nreg [7:0] operand_a;\nreg [7:0] operand_b;\n\nwire signed [9:0] pp1;\nwire signed [9:0] pp2;\nwire signed [9:0] pp3;\nwire signed [9:0] pp4;\nwire [6*ACC_WIDTH-1 : 0] mul_reduce_csa_input;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp1;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp2;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp3;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp4;\nwire signed [ACC_WIDTH-1:0] reduce_acc_sum;\nwire signed [ACC_WIDTH-1:0] reduce_acc_carry;\n\nassign sign_extend_pp4 = $signed({pp4,6'b0});\nassign sign_extend_pp3 = $signed({pp3,4'b0});\nassign sign_extend_pp2 = $signed({pp2,2'b0});\nassign sign_extend_pp1 = $signed(pp1);\n\nassign mul_reduce_csa_input = {sign_extend_pp4,sign_extend_pp3,sign_extend_pp2,sign_extend_pp1,partial_result[0+:ACC_WIDTH],partial_result[ACC_WIDTH+:ACC_WIDTH]};\n\nbooth_pp_gen booth_pp_gen_inst(\n .operand_a(operand_a), \n .operand_b(operand_b), \n .pp1(pp1),\n .pp2(pp2),\n .pp3(pp3),\n .pp4(pp4)\n);\n\nDW02_tree #(6, ACC_WIDTH, 1)\n U2 ( .INPUT(mul_reduce_csa_input), .OUT0(reduce_acc_sum), .OUT1(reduce_acc_carry) );\n\nalways @(posedge clk) begin\n if (!rst_n) begin\n acc_sum <= 0;\n acc_carry <= 0;\n end\n else begin\n acc_sum <= reduce_acc_sum;\n acc_carry <= reduce_acc_carry;\n end\nend\n\ngenerate\n if(INPUT_PIP == 1) begin\n always @(posedge clk) begin\n operand_a <= operand_a_in;\n operand_b <= operand_b_in;\n end\n end\n else begin\n always @(*) begin\n operand_a = operand_a_in;\n operand_b = operand_b_in;\n end\n end\nendgenerate\n\n// dff_async #(\n// .WIDTH(ACC_WIDTH)) acc_sum_reg (\n// .clk(clk),\n// .rst_n(rst_n),\n// .d(reduce_acc_sum),\n// .q(acc_sum)\n// );\n\n// dff_async #(\n// .WIDTH(ACC_WIDTH)) acc_carry_reg (\n// .clk(clk),\n// .rst_n(rst_n),\n// .d(reduce_acc_carry),\n// .q(acc_carry)\n// );\n\n\n\n \nendmodule\n\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/opt1_mac.v", "module opt1_mac #(\n parameter ACC_WIDTH = 32,\n parameter INPUT_PIP = 1\n)(\n input wire clk,\n input wire rst_n,\n input wire [7:0] operand_a_in, \n input wire [7:0] operand_b_in, \n input wire signed [2*ACC_WIDTH-1:0] partial_result, \n output reg [ACC_WIDTH-1:0] acc_sum,\n output reg [ACC_WIDTH-1:0] acc_carry\n);\n\nreg [7:0] operand_a;\nreg [7:0] operand_b;\n\nwire signed [9:0] pp1;\nwire signed [9:0] pp2;\nwire signed [9:0] pp3;\nwire signed [9:0] pp4;\nwire [6*ACC_WIDTH-1 : 0] mul_reduce_csa_input;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp1;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp2;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp3;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp4;\nwire signed [ACC_WIDTH-1:0] reduce_acc_sum;\nwire signed [ACC_WIDTH-1:0] reduce_acc_carry;\n\nassign sign_extend_pp4 = $signed({pp4,6'b0});\nassign sign_extend_pp3 = $signed({pp3,4'b0});\nassign sign_extend_pp2 = $signed({pp2,2'b0});\nassign sign_extend_pp1 = $signed(pp1);\n\nassign mul_reduce_csa_input = {sign_extend_pp4,sign_extend_pp3,sign_extend_pp2,sign_extend_pp1,partial_result[0+:ACC_WIDTH],partial_result[ACC_WIDTH+:ACC_WIDTH]};\n\nbooth_pp_gen booth_pp_gen_inst(\n .operand_a(operand_a), \n .operand_b(operand_b), \n .pp1(pp1),\n .pp2(pp2),\n .pp3(pp3),\n .pp4(pp4)\n);\n\nDW02_tree #(6, ACC_WIDTH, 1)\n U2 ( .INPUT(mul_reduce_csa_input), .OUT0(reduce_acc_sum), .OUT1(reduce_acc_carry) );\n\nalways @(posedge clk) begin\n if (!rst_n) begin\n acc_sum <= 0;\n acc_carry <= 0;\n end\n else begin\n acc_sum <= reduce_acc_sum;\n acc_carry <= reduce_acc_carry;\n end\nend\n\ngenerate\n if(INPUT_PIP == 1) begin\n always @(posedge clk) begin\n operand_a <= operand_a_in;\n operand_b <= operand_b_in;\n end\n end\n else begin\n always @(*) begin\n operand_a = operand_a_in;\n operand_b = operand_b_in;\n end\n end\nendgenerate\n\n// dff_async #(\n// .WIDTH(ACC_WIDTH)) acc_sum_reg (\n// .clk(clk),\n// .rst_n(rst_n),\n// .d(reduce_acc_sum),\n// .q(acc_sum)\n// );\n\n// dff_async #(\n// .WIDTH(ACC_WIDTH)) acc_carry_reg (\n// .clk(clk),\n// .rst_n(rst_n),\n// .d(reduce_acc_carry),\n// .q(acc_carry)\n// );\n\n\n\n \nendmodule\n\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_mac_based/PE.v", "// b = w * a\nmodule PE #\n(\n parameter WIDTH = 8,\n parameter ACC_WIDTH = 24\n)\n(\n input wire rst_n ,\n input wire clk ,\n input wire weight_wen ,\n input [WIDTH-1 :0] weight_din ,\n input wire signed [WIDTH-1 :0] a ,\n input wire signed [ACC_WIDTH-1 :0] partial_result , \n\n output reg signed [WIDTH-1 :0] col ,\n output reg signed [ACC_WIDTH-1 :0] row \n);\n\n\nreg signed [WIDTH-1 :0] weight;\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n weight <= 0;\n end\n else begin\n if(weight_wen) begin\n weight <= weight_din; \n end\n else begin\n weight <= weight;\n end\n end\nend\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n col <= 0;\n end\n else begin\n if(weight_wen) begin\n col <= weight_din; \n end\n else begin\n col <= a;\n end\n end\nend\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n row <= 0;\n end\n else begin\n row <= partial_result + weight * a;\n end\nend\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_mac_based/top.v", "`timescale 1ns / 1ps\nmodule top #\n(\n parameter N = 8, //CHANGE\n parameter WIDTH = 8, \n parameter ACC_WIDTH = 2*WIDTH + $clog2(N) \n)\n(\n input wire rst_n ,\n input wire clk ,\n input wire [N*N*WIDTH-1 :0] A ,\n input wire [N*N*WIDTH-1 :0] B ,\n output wire [N*N*ACC_WIDTH-1 :0] result \n);\n\nreg [N*N*WIDTH-1 :0] A_reg ;\nreg [N*N*WIDTH-1 :0] B_reg ;\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n A_reg<={(N*N*WIDTH){1'b0}};\n B_reg<={(N*N*WIDTH){1'b0}};\n end\n else begin\n A_reg<=A;\n B_reg<=B;\n end\nend\n\n\nwire signed [WIDTH-1:0] d_x [0:N-1][0:N-1][0:N-1];\nwire signed [ACC_WIDTH-1:0] d_y [0:N-1][0:N-1][0:N-1];\nwire signed [WIDTH-1:0] d_z [0:N-1][0:N-1][0:N-1];\n\n\n genvar x, y, z;\n generate\n for (z = 0; z < N; z = z + 1 ) begin\n for(x = 0; x < N; x = x + 1) begin\n for (y = 0; y < N; y = y + 1 ) begin\n if(z==0) begin\n if(x==0) begin\n if(y==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE //(1)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p ({ACC_WIDTH{1'b0}} ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n ); \n end\n else if(y==N-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(3)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (result[N*ACC_WIDTH*z+(x+1)*ACC_WIDTH-1 : ACC_WIDTH*N*z+x*ACC_WIDTH] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(2)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n );\n end\n end\n else begin\n if(y==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE //(6)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p ({ACC_WIDTH{1'b0}} ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n ); \n end\n else if(y==N-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(5)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (result[N*ACC_WIDTH*z+(x+1)*ACC_WIDTH-1 : ACC_WIDTH*N*z+x*ACC_WIDTH] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(4)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n );\n end \n end\n end\n else begin\n if(x==0) begin\n if(y==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE //(7)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p ({ACC_WIDTH{1'b0}} ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n ); \n end\n else if(y==N-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(9)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (result[N*ACC_WIDTH*z+(x+1)*ACC_WIDTH-1 : ACC_WIDTH*N*z+x*ACC_WIDTH] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(8)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n );\n end\n end\n else begin\n if(y==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE //(10)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p ({ACC_WIDTH{1'b0}} ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n ); \n end\n else if(y==N-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(12)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (result[N*ACC_WIDTH*z+(x+1)*ACC_WIDTH-1 : ACC_WIDTH*N*z+x*ACC_WIDTH] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(11)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n );\n end \n end\n end\n end\n end\n end\n endgenerate\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/top.v", "`timescale 1ns / 1ps\n\n// Calculate matrix (A*B)\n// Size of A is (A_H*A_W), size of B is (B_H*B_W), and A_W = B_H\n// Size of output matirx A*B is (A_H*B_W)\n\nmodule top #\n(\n parameter N = 8, //CHANGE\n parameter WIDTH = 8, \n parameter ACC_WIDTH = 2*WIDTH + $clog2(N) \n)\n(\n input wire rst_n ,\n input wire clk ,\n input wire [N*N*WIDTH-1 :0] A ,\n input wire [N*N*WIDTH-1 :0] B ,\n output wire [N*N*2*ACC_WIDTH-1 :0] result \n);\n\nreg [N*N*WIDTH-1 :0] A_reg ;\nreg [N*N*WIDTH-1 :0] B_reg ;\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n A_reg<={(N*N*WIDTH){1'b0}};\n B_reg<={(N*N*WIDTH){1'b0}};\n end\n else begin\n A_reg<=A;\n B_reg<=B;\n end\nend\n\n\nwire signed [WIDTH-1:0] d_x [0:N-1][0:N-1][0:N-1];\nwire signed [2*ACC_WIDTH-1:0] d_y [0:N-1][0:N-1][0:N-1];\nwire signed [WIDTH-1:0] d_z [0:N-1][0:N-1][0:N-1];\n\n\n genvar x, y, z;\n generate\n for (z = 0; z < N; z = z + 1 ) begin\n for(x = 0; x < N; x = x + 1) begin\n for (y = 0; y < N; y = y + 1 ) begin\n if(z==0) begin\n if(x==0) begin\n if(y==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE //(1)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p ({2*ACC_WIDTH{1'b0}} ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n ); \n end\n else if(y==N-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(3)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (result[N*2*ACC_WIDTH*z+(x+1)*2*ACC_WIDTH-1 : 2*ACC_WIDTH*N*z+x*2*ACC_WIDTH] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(2)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n );\n end\n end\n else begin\n if(y==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE //(6)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p ({2*ACC_WIDTH{1'b0}} ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n ); \n end\n else if(y==N-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(5)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (result[N*2*ACC_WIDTH*z+(x+1)*2*ACC_WIDTH-1 : 2*ACC_WIDTH*N*z+x*2*ACC_WIDTH] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(4)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n );\n end \n end\n end\n else begin\n if(x==0) begin\n if(y==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE //(7)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p ({2*ACC_WIDTH{1'b0}} ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n ); \n end\n else if(y==N-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(9)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (result[N*2*ACC_WIDTH*z+(x+1)*2*ACC_WIDTH-1 : 2*ACC_WIDTH*N*z+x*2*ACC_WIDTH] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(8)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n );\n end\n end\n else begin\n if(y==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE //(10)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p ({2*ACC_WIDTH{1'b0}} ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n ); \n end\n else if(y==N-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(12)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (result[N*2*ACC_WIDTH*z+(x+1)*2*ACC_WIDTH-1 : 2*ACC_WIDTH*N*z+x*2*ACC_WIDTH] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(11)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n );\n end \n end\n end\n end\n end\n end\n endgenerate\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT2/top_pe_tile.sv", "module top_pe_tile #(\n localparam RESULT_WIDTH = 20\n)(\n input clk,\n input weight_wen,\n input [7:0] weight_din,\n input [3:0] bit_enable [0:15],\n input [7:0] partial_product_select [0:15],\n output reg signed [RESULT_WIDTH-1:0] result,\n output reg [3:0] bit_enable_pip [0:15],\n output reg [7:0] partial_product_select_pip [0:15]\n);\n\nlocalparam REDUCE_WIDTH = 13;\n\n//*********range of partial_product in same bit-weight********/\n//** 9bit: -256 ≤ partial_product ≤ 254 /\n//** 13bit: -4096 ≤ 16 * partial_product ≤ 4064 /\n//************************************************************/\nwire [7:0] weight [0:15];\nwire signed [9:0] partial_product [0:15][0:3]; \nwire signed [REDUCE_WIDTH-1:0] csa_extend [0:15][0:3];\nwire [16*REDUCE_WIDTH-1:0] csa_input [0:3];\nwire [4*REDUCE_WIDTH-1:0] mid_result [0:3];\nwire signed [REDUCE_WIDTH-1:0] result_bw [0:3];\nwire signed [RESULT_WIDTH-1:0] bw_0;\nwire signed [RESULT_WIDTH-1:0] bw_1;\nwire signed [RESULT_WIDTH-1:0] bw_2;\nwire signed [RESULT_WIDTH-1:0] bw_3;\n\n\nweight_rf weight_buffer(\n .clk(clk),\n .wen(weight_wen),\n .din(weight_din),\n .weight(weight) \n);\n\ngenvar i,j;\ngenerate\n for (i=0;i<16;i=i+1) begin\n partial_product_select pps (\n .clk(clk),\n .weight(weight[i]),\n .bit_enable(bit_enable_pip[i]),\n .partial_product_select(partial_product_select_pip[i]),\n .partial_product(partial_product[i])\n );\n end\nendgenerate\n\ngenerate\n for (i=0;i<16;i=i+1) begin\n for (j=0;j<4;j=j+1) begin\n assign csa_extend[i][j] = $signed(partial_product[i][j]);\n end\n end\nendgenerate\n\ngenerate\n for (i=0;i<4;i=i+1) begin\n for (j=0;j<16;j=j+1) begin\n assign csa_input[i][(j+1)*REDUCE_WIDTH-1:j*REDUCE_WIDTH] = csa_extend[j][i];\n end\n end\nendgenerate\n\n\ngenerate\n for (i=0;i<4;i=i+1) begin\n\n tree_full_sum #(\n .K(4),\n .WIDTH(REDUCE_WIDTH)\n ) tree_stage_1_0 (\n .clk(clk),\n .csa_input({csa_input[i][1*REDUCE_WIDTH-1:0],\n csa_input[i][2*REDUCE_WIDTH-1:1*REDUCE_WIDTH],\n csa_input[i][3*REDUCE_WIDTH-1:2*REDUCE_WIDTH],\n csa_input[i][4*REDUCE_WIDTH-1:3*REDUCE_WIDTH]}),\n .full_sum(mid_result[i][1*REDUCE_WIDTH-1:0*REDUCE_WIDTH])\n );\n tree_full_sum #(\n .K(4),\n .WIDTH(REDUCE_WIDTH)\n ) tree_stage_1_1 (\n .clk(clk),\n .csa_input({csa_input[i][5*REDUCE_WIDTH-1:4*REDUCE_WIDTH],\n csa_input[i][6*REDUCE_WIDTH-1:5*REDUCE_WIDTH],\n csa_input[i][7*REDUCE_WIDTH-1:6*REDUCE_WIDTH],\n csa_input[i][8*REDUCE_WIDTH-1:7*REDUCE_WIDTH]}),\n .full_sum(mid_result[i][2*REDUCE_WIDTH-1:1*REDUCE_WIDTH])\n );\n tree_full_sum #(\n .K(4),\n .WIDTH(REDUCE_WIDTH)\n ) tree_stage_1_2 (\n .clk(clk),\n .csa_input({csa_input[i][9*REDUCE_WIDTH-1:8*REDUCE_WIDTH],\n csa_input[i][10*REDUCE_WIDTH-1:9*REDUCE_WIDTH],\n csa_input[i][11*REDUCE_WIDTH-1:10*REDUCE_WIDTH],\n csa_input[i][12*REDUCE_WIDTH-1:11*REDUCE_WIDTH]}),\n .full_sum(mid_result[i][3*REDUCE_WIDTH-1:2*REDUCE_WIDTH])\n );\n tree_full_sum #(\n .K(4),\n .WIDTH(REDUCE_WIDTH)\n ) tree_stage_1_3 (\n .clk(clk),\n .csa_input({csa_input[i][13*REDUCE_WIDTH-1:12*REDUCE_WIDTH],\n csa_input[i][14*REDUCE_WIDTH-1:13*REDUCE_WIDTH],\n csa_input[i][15*REDUCE_WIDTH-1:14*REDUCE_WIDTH],\n csa_input[i][16*REDUCE_WIDTH-1:15*REDUCE_WIDTH]}),\n .full_sum(mid_result[i][4*REDUCE_WIDTH-1:3*REDUCE_WIDTH])\n );\n end\nendgenerate\n\n\ngenerate\n for (i=0;i<4;i=i+1) begin\n tree_full_sum #(\n .K(4),\n .WIDTH(REDUCE_WIDTH)\n ) tree_stage_2 (\n .clk(clk),\n .csa_input({mid_result[i][1*REDUCE_WIDTH-1:0],\n mid_result[i][2*REDUCE_WIDTH-1:1*REDUCE_WIDTH],\n mid_result[i][3*REDUCE_WIDTH-1:2*REDUCE_WIDTH],\n mid_result[i][4*REDUCE_WIDTH-1:3*REDUCE_WIDTH]}),\n .full_sum(result_bw[i])\n );\n end\nendgenerate\n\n\nassign bw_0 = $signed(result_bw[0]);\nassign bw_1 = $signed({result_bw[1],2'b0});\nassign bw_2 = $signed({result_bw[2],4'b0});\nassign bw_3 = $signed({result_bw[3],6'b0});\n\ntree_full_sum #(\n .K(4),\n .WIDTH(RESULT_WIDTH)\n) tree_stage_3 (\n .clk(clk),\n .csa_input({bw_0,bw_1,bw_2,bw_3}),\n .full_sum(result)\n );\n\n// pipeline the bit_enable and partial_product_select\nalways @(posedge clk) begin\n bit_enable_pip <= bit_enable;\n partial_product_select_pip <= partial_product_select;\nend\n\nendmodule\n\n\n\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT2/partial_product_select.sv", "module partial_product_select(\n input clk,\n input [7:0] weight,\n input [3:0] bit_enable,\n input [7:0] partial_product_select,\n output signed [9:0] partial_product [0:3] \n);\n\nwire signed [8:0] inv_b;\nwire signed [7:0] b;\nwire signed [8:0] b_2;\nwire signed [8:0] b_neg;\nwire signed [9:0] b_2_neg;\nwire [1:0] cal_partial_product_select [0:3];\nreg signed [9:0] partial_product_bw [0:3]; \n\nassign cal_partial_product_select[0] = partial_product_select[1:0];\nassign cal_partial_product_select[1] = partial_product_select[3:2];\nassign cal_partial_product_select[2] = partial_product_select[5:4];\nassign cal_partial_product_select[3] = partial_product_select[7:6];\nassign partial_product = partial_product_bw;\nassign b = $signed(weight);\nassign inv_b = $signed(~b);\nassign b_2 = {b,1'b0};\nassign b_neg = inv_b + 1'b1;\nassign b_2_neg = {b_neg,1'b0};\n\ngenvar i;\ngenerate \n for (i = 0 ; i < 4; i = i + 1) begin\n always @(posedge clk) begin\n if(bit_enable[i]) begin\n case(cal_partial_product_select[i])\n 2'b00: partial_product_bw[i] <= $signed(b_2_neg);\n 2'b01: partial_product_bw[i] <= $signed(b);\n 2'b10: partial_product_bw[i] <= $signed(b_2);\n 2'b11: partial_product_bw[i] <= $signed(b_neg);\n endcase\n end\n else\n partial_product_bw[i] <= 0;\n end\n end \nendgenerate\n\nendmodule\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_mac_based/top.v", "module top #\n(\n parameter A_H = 16, \n parameter B_W = 16, \n parameter WIDTH = 8,\n parameter ACC_WIDTH = 32 \n)\n(\n input wire rst_n ,\n input wire clk ,\n input wire [A_H*WIDTH-1 :0] A ,\n input wire [B_W*WIDTH-1 :0] B ,\n input wire clc , // clean_result_cache,\n output wire [A_H*B_W*ACC_WIDTH-1 :0] result \n);\n\nreg [A_H*WIDTH-1 :0] A_reg ;\nreg [B_W*WIDTH-1 :0] B_reg ;\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n A_reg<={(A_H*WIDTH){1'b0}};\n B_reg<={(B_W*WIDTH){1'b0}};\n end\n else begin\n A_reg<=A;\n B_reg<=B;\n end\nend\n\nwire signed [WIDTH-1:0] row [0:A_H-1][0:B_W-1];\nwire signed [WIDTH-1:0] col [0:A_H-1][0:B_W-1];\n\n\n genvar i, j;\n generate\n for (i = 0; i < A_H; i = i + 1 ) begin\n for(j = 0; j < B_W; j = j + 1) begin\n if(i==0) begin\n if(j==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .a (A_reg[WIDTH-1 :0] ),\n .b (B_reg[WIDTH-1 :0] ),\n .clc (clc ),\n .row (row[i][j] ),\n .col (col[i][j] ),\n .result (result[(i*B_W+j+1)*ACC_WIDTH-1:(i*B_W+j)*ACC_WIDTH])\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .a (row[i][j-1] ),\n .b (B_reg[WIDTH*(j+1)-1 :WIDTH*j] ),\n .clc (clc ),\n .row (row[i][j] ),\n .col (col[i][j] ),\n .result (result[(i*B_W+j+1)*ACC_WIDTH-1:(i*B_W+j)*ACC_WIDTH])\n );\n end\n end\n else if (j==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .a (A_reg[WIDTH*(i+1)-1 :WIDTH*i] ),\n .b (col[i-1][j] ),\n .clc (clc ),\n .row (row[i][j] ),\n .col (col[i][j] ),\n .result (result[(i*B_W+j+1)*ACC_WIDTH-1:(i*B_W+j)*ACC_WIDTH])\n );\n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .a (row[i][j-1] ),\n .b (col[i-1][j] ),\n .clc (clc ),\n .row (row[i][j] ),\n .col (col[i][j] ),\n .result (result[(i*B_W+j+1)*ACC_WIDTH-1:(i*B_W+j)*ACC_WIDTH])\n ); \n \n end \n end\n end\n endgenerate\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/top.v", "module top #\n(\n parameter A_H = 16, //CHANGE\n parameter B_W = 16, //CHANGE\n parameter WIDTH = 8,\n parameter ACC_WIDTH = 32 //CHANGE\n)\n(\n input wire rst_n ,\n input wire clk ,\n input wire [A_H*WIDTH-1 :0] A ,\n input wire [B_W*WIDTH-1 :0] B ,\n input wire clc , // clean_result_cache\n// output wire [A_H*B_W*ACC_WIDTH-1 :0] result \n output wire [2*A_H*B_W*ACC_WIDTH-1 :0] result \n);\n\nreg [A_H*WIDTH-1 :0] A_reg ;\nreg [B_W*WIDTH-1 :0] B_reg ;\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n A_reg<={(A_H*WIDTH){1'b0}};\n B_reg<={(B_W*WIDTH){1'b0}};\n end\n else begin\n A_reg<=A;\n B_reg<=B;\n end\nend\n\nwire signed [WIDTH-1:0] row [0:A_H-1][0:B_W-1];\nwire signed [WIDTH-1:0] col [0:A_H-1][0:B_W-1];\n\n\n genvar i, j;\n generate\n for (i = 0; i < A_H; i = i + 1 ) begin\n for(j = 0; j < B_W; j = j + 1) begin\n if(i==0) begin\n if(j==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .a (A_reg[WIDTH-1 :0] ),\n .b (B_reg[WIDTH-1 :0] ),\n .clc (clc ), // input wire clean_result_cache\n .row (row[i][j] ),\n .col (col[i][j] ),\n// .result (result[(i*B_W+j+1)*ACC_WIDTH-1:(i*B_W+j)*ACC_WIDTH])\n .result (result[(i*B_W+j+1)*2*ACC_WIDTH-1:(i*B_W+j)*2*ACC_WIDTH])\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .a (row[i][j-1] ),\n .b (B_reg[WIDTH*(j+1)-1 :WIDTH*j] ),\n .clc (clc ), // input wire clean_result_cache\n .row (row[i][j] ),\n .col (col[i][j] ),\n// .result (result[(i*B_W+j+1)*ACC_WIDTH-1:(i*B_W+j)*ACC_WIDTH])\n .result (result[(i*B_W+j+1)*2*ACC_WIDTH-1:(i*B_W+j)*2*ACC_WIDTH])\n );\n end\n end\n else if (j==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .a (A_reg[WIDTH*(i+1)-1 :WIDTH*i] ),\n .b (col[i-1][j] ),\n .clc (clc ), // input wire clean_result_cache\n .row (row[i][j] ),\n .col (col[i][j] ),\n// .result (result[(i*B_W+j+1)*ACC_WIDTH-1:(i*B_W+j)*ACC_WIDTH])\n .result (result[(i*B_W+j+1)*2*ACC_WIDTH-1:(i*B_W+j)*2*ACC_WIDTH])\n );\n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .a (row[i][j-1] ),\n .b (col[i-1][j] ),\n .clc (clc ), // input wire clean_result_cache\n .row (row[i][j] ),\n .col (col[i][j] ),\n// .result (result[(i*B_W+j+1)*ACC_WIDTH-1:(i*B_W+j)*ACC_WIDTH])\n .result (result[(i*B_W+j+1)*2*ACC_WIDTH-1:(i*B_W+j)*2*ACC_WIDTH])\n ); \n \n end \n end\n end\n endgenerate\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT2/tree_full_sum.sv", "module tree_full_sum #(\n parameter K = 16,\n parameter WIDTH = 13\n)(\n input clk,\n input [K*WIDTH-1:0] csa_input,\n output reg signed [WIDTH-1:0] full_sum\n);\n\nwire signed [WIDTH-1:0] acc_sum;\nwire signed [WIDTH-1:0] acc_carry;\n\ngenvar i;\ngenerate\n if(K == 4) begin\n always @(posedge clk) begin\n full_sum <= $signed(csa_input[1*WIDTH-1:0*WIDTH]) + $signed(csa_input[2*WIDTH-1:1*WIDTH]) + $signed(csa_input[3*WIDTH-1:2*WIDTH]) + $signed(csa_input[4*WIDTH-1:3*WIDTH]);\n end\n end\n else begin\n DW02_tree #(K, WIDTH, 1)\n ins_tree ( .INPUT(csa_input), .OUT0(acc_sum), .OUT1(acc_carry));\n always @(posedge clk) begin\n full_sum <= $signed(acc_sum) + $signed(acc_carry);\n end\n end\nendgenerate\n\n\n\n\nendmodule\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_mac_based/top.v", "// Calculate matrix (A*B)\n// Size of A is (M*K), size of B is (K*N), and A_H = K, B_W = N, B is weight\n// Size of output matirx A*B is (M*N)\n\nmodule top #\n(\n parameter A_H = 16, \n parameter B_W = 16, \n parameter WIDTH = 8,\n // parameter ACC_WIDTH = 32 \n parameter ACC_WIDTH = 2*WIDTH + $clog2(A_H)\n)\n(\n input wire clk ,\n input wire rst_n ,\n input weight_wen ,\n input [A_H*WIDTH-1 :0] weight_din ,\n input wire [A_H*WIDTH-1 :0] A ,\n output wire [B_W*ACC_WIDTH-1 :0] result \n);\n\nreg [A_H*WIDTH-1 :0] A_reg ;\nreg [A_H*WIDTH-1 :0] weight_din_reg;\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n A_reg<={(A_H*WIDTH){1'b0}};\n weight_din_reg <= {(B_W*WIDTH){1'b0}};\n end\n else begin\n A_reg<=A;\n weight_din_reg <= weight_din;\n end\nend\n\n\nwire signed [ACC_WIDTH-1:0] row [0:B_W-1][0:A_H-1];\nwire signed [WIDTH-1:0] col [0:B_W-1][0:A_H-1];\n\n\n genvar i, j;\n generate\n for (i = 0; i < B_W; i = i + 1 ) begin\n for(j = 0; j < A_H; j = j + 1) begin\n if(j==0) begin\n if(i==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .weight_wen (weight_wen ),\n .weight_din (weight_din_reg[(j+1)*WIDTH-1:j*WIDTH] ),\n .a (A_reg[(j+1)*WIDTH-1:j*WIDTH] ),\n .partial_result ({ACC_WIDTH{1'b0}} ), // or input\n .row (row[i][j] ),\n .col (col[i][j] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .weight_wen (weight_wen ),\n .weight_din (col[i-1][j] ),\n .a (col[i-1][j] ),\n .partial_result ({ACC_WIDTH{1'b0}} ), // or input\n .row (row[i][j] ),\n .col (col[i][j] )\n ); \n end\n end\n else if (i==0) begin\n if(j==A_H-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .weight_wen (weight_wen ),\n .weight_din (weight_din_reg[(j+1)*WIDTH-1:j*WIDTH] ),\n .a (A_reg[(j+1)*WIDTH-1:j*WIDTH] ),\n .partial_result (row[i][j-1] ),\n .row (result[(i+1)*ACC_WIDTH-1 :i*ACC_WIDTH] ),\n .col (col[i][j] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .weight_wen (weight_wen ),\n .weight_din (weight_din_reg[(j+1)*WIDTH-1:j*WIDTH] ),\n .a (A_reg[(j+1)*WIDTH-1:j*WIDTH] ),\n .partial_result (row[i][j-1] ),\n .row (row[i][j] ),\n .col (col[i][j] )\n ); \n end\n end\n else if (j==A_H-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .weight_wen (weight_wen ),\n .weight_din (col[i-1][j] ),\n .a (col[i-1][j] ),\n .partial_result (row[i][j-1] ),\n .row (result[(i+1)*ACC_WIDTH-1 :i*ACC_WIDTH] ),\n .col (col[i][j] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .weight_wen (weight_wen ),\n .weight_din (col[i-1][j] ),\n .a (col[i-1][j] ),\n .partial_result (row[i][j-1] ),\n .row (row[i][j] ),\n .col (col[i][j] )\n ); \n end\n end\n end\nendgenerate\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT3_OPT4C/pe/sparse_encoder.v", "module sparse_encoder (\n input clk,\n input rst_n,\n input [7:0] en_multiplicand,\n input [3:0] sign_en_multiplicand,\n input encode_valid,\n output reg [1:0] partial_product_index, // to sparse_pe generate partial product\n output reg [1:0] position_0, // to prefetch operand b\n output [2:0] cal_cycle // to prefetch operand a \n);\n\nwire a ;\nwire b ;\nwire c ;\nwire d ;\n\nreg [7:0] cal_en_multiplicand;\nreg [1:0] position_1 ;\nreg [1:0] position_2 ;\nreg position_3 ;\n\nassign a = en_multiplicand[0] | en_multiplicand[1];\nassign b = en_multiplicand[2] | en_multiplicand[3];\nassign c = en_multiplicand[4] | en_multiplicand[5];\nassign d = en_multiplicand[6] | en_multiplicand[7];\n\n\nassign a_b_c_d = (a) & (b) & (c) & (d);\nassign cal_cycle = {a_b_c_d,(~a & ( (b & c) | (b & d) | (c & d) )) | (a & ( (b & ~c) | (~b & d) | (c & ~d) )),(a ^ b) ^ (c ^ d)};\n\n/**********************************************/\n/******** 00 | 01 | 10 | 11 | *********/\n/******** -2B | B | 2B | -B | *********/\n/**********************************************/\ngenvar i;\ngenerate\n for (i = 0 ; i < 4 ; i = i + 1) begin : gen_cal_encoder\n always @(posedge clk or negedge rst_n) begin\n\t if (!rst_n) begin\n cal_en_multiplicand[2*(i+1)-1:2*i] <= 0;\n\t end\n\t else begin\n if(encode_valid) begin\n if(sign_en_multiplicand[i]) begin\n cal_en_multiplicand[2*(i+1)-1:2*i] <= {~en_multiplicand[2*(i+1)-1],en_multiplicand[2*i]};\n end\n else\n cal_en_multiplicand[2*(i+1)-1:2*i] <= en_multiplicand[2*(i+1)-1:2*i];\n end else\n cal_en_multiplicand[2*(i+1)-1:2*i] <= cal_en_multiplicand[2*(i+1)-1:2*i] ;\n\t end\n end\n end\nendgenerate\n \n\n\nalways @(posedge clk or negedge rst_n) begin\n if (!rst_n) begin\n position_0 <= 2'b0 ; \n position_1 <= 2'b0 ; \n position_2 <= 2'b0 ; \n position_3 <= 1'b0 ;\n end\n else begin\n if(encode_valid) begin\n position_0 <= {(~a)&(~b), (~a & (b | ~c))};\n position_1 <= {( (a ^ b) & (c | d)) | ( (~a)&(c)&(d) ), (a & b) | ( d & ( ( (a ^ b) & ~c ) | ( ~a & ~b & c ) ))};\n position_2 <= {(c & d & (a | b)) | (a & b & (c | d)), d & ( (a&b | a&c | b&c) & ~(a&b&c) )};\n position_3 <= a_b_c_d;\n end\n else begin\n position_0 <= position_1;\n position_1 <= position_2;\n position_2 <= {position_3,position_3};\n position_3 <= 0;\n end\n end\nend\n\n\nalways @(posedge clk) begin\n case(position_0) \n 2'b00: partial_product_index <= cal_en_multiplicand[1:0];\n 2'b01: partial_product_index <= cal_en_multiplicand[3:2];\n 2'b10: partial_product_index <= cal_en_multiplicand[5:4];\n 2'b11: partial_product_index <= cal_en_multiplicand[7:6];\n endcase\nend\n\nendmodule\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT2/top_tpe.sv", "module top_tpe #(\n parameter N = 32,\n localparam RESULT_WIDTH = 20\n)(\n \n input clk,\n input [127:0] operand_a,\n input weight_wen,\n input [8*N-1:0] weight_din,\n output [RESULT_WIDTH*N-1:0] result\n\n);\n\nwire [3:0] bit_enable [0:15];\nwire [7:0] partial_product_select [0:15];\nwire [3:0] bit_enable_pip [0:N-1][0:15];\nwire [7:0] partial_product_select_pip [0:N-1][0:15];\n\nvector_encoder encoder(\n .clk(clk),\n .operand_a(operand_a),\n .bit_enable(bit_enable),\n .partial_product_select(partial_product_select)\n);\n\ngenvar i;\ngenerate \n for (i = 0 ; i < N ; i = i + 1) begin\n if(i == 0) begin\n top_pe_tile pe_tile(\n .clk(clk),\n .weight_wen(weight_wen),\n .weight_din(weight_din[8*(i+1)-1:8*i]),\n .bit_enable(bit_enable),\n .partial_product_select(partial_product_select),\n .result(result[RESULT_WIDTH*(i+1)-1:RESULT_WIDTH*i]),\n .bit_enable_pip(bit_enable_pip[i]),\n .partial_product_select_pip(partial_product_select_pip[i])\n );\n end\n else begin\n top_pe_tile pe_tile(\n .clk(clk),\n .weight_wen(weight_wen),\n .weight_din(weight_din[8*(i+1)-1:8*i]),\n .bit_enable(bit_enable_pip[i-1]),\n .partial_product_select(partial_product_select_pip[i-1]),\n .result(result[RESULT_WIDTH*(i+1)-1:RESULT_WIDTH*i]),\n .bit_enable_pip(bit_enable_pip[i]),\n .partial_product_select_pip(partial_product_select_pip[i])\n );\n end\n end\nendgenerate\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT2/vector_encoder.sv", "module vector_encoder(\n input clk,\n input [127:0] operand_a,\n output reg [3:0] bit_enable [0:15],\n output reg [7:0] partial_product_select [0:15]\n);\n\nwire [3:0] bit_valid [0:15];\nwire [7:0] encoder_nub [0:15];\nreg [127:0] sync_operand ;\n\ngenvar i;\ngenerate\n for(i = 0; i < 16; i = i + 1) begin\n en_t_encoder en_t_preencoder(\n .clk(clk),\n .multiplicand(sync_operand[8*(i+1)-1:8*i]),\n .cal_encode_nub(encoder_nub[i]),\n .bit_enable(bit_valid[i])\n );\n end \nendgenerate\n\nalways @(posedge clk) begin\n sync_operand <= operand_a;\n bit_enable <= bit_valid;\n partial_product_select <= encoder_nub;\nend\n\nendmodule\n\n\n\nmodule en_t_encoder(\n input clk,\n input [7:0] multiplicand, \n output reg [7:0] cal_encode_nub,\n output reg [3:0] bit_enable\n );\n\nwire [7:0] encode_input;\nwire [2:0] c_out;\nwire [7:0] encode_nub;\n\n// covert to bit_enable-Magnitude\nassign encode_input = multiplicand[7] ? ((multiplicand[6:0] == 0) ? 8'b10000000 : {1'b0,~multiplicand[6:0] + 1'b1}) : {1'b0,multiplicand[6:0]};\n\ngenvar i;\ngenerate for(i = 0; i < 4; i = i + 1) begin: gen_encode_nub \n if(i==0) begin\n assign encode_nub[1:0] = encode_input[1:0];\n end\n else if (i==1) begin\n encoder_1 en_t\n (.A(encode_input[2*i-1:2*i-2]),\n .B(encode_input[2*i+1:2*i]), \n .c_out(c_out[i]), \n .en_b(encode_nub[2*i+1:2*i])\n );\n end\n else if (i==3) begin\n encoder_3 en_t\n (.A(encode_input[2*i-1:2*i-2]),\n .c_in(c_out[i-1]), \n .B(encode_input[2*i+1:2*i]), \n .en_b(encode_nub[2*i+1:2*i])\n );\n end\n else begin\n encoder en_t\n (.A(encode_input[2*i-1:2*i-2]),\n .c_in(c_out[i-1]), \n .B(encode_input[2*i+1:2*i]), \n .c_out(c_out[i]), \n .en_b(encode_nub[2*i+1:2*i])\n );\n end \nend \nendgenerate \n\n\ngenerate \n for (i = 0 ; i < 4; i = i + 1) begin\n always @(posedge clk) begin\n if(encode_nub[2*i+1:2*i] == 2'b00) begin\n bit_enable[i] <= 0;\n cal_encode_nub[2*i+1:2*i] <= 0;\n end\n else begin\n bit_enable[i] <= 1;\n cal_encode_nub[2*i+1:2*i] <= {multiplicand[7]^encode_nub[2*i+1],encode_nub[2*i]};\n end\n end\n end\nendgenerate\n\nendmodule\n\n\nmodule encoder_1(A, B, c_out, en_b);\n\ninput wire [1:0] A;\ninput wire [1:0] B;\n \noutput wire c_out;\noutput wire [1:0] en_b;\n\nassign c_out = (A[0] & A[1]); \nassign en_b = B + c_out;\n\nendmodule\n\nmodule encoder(A, c_in, B, c_out, en_b);\n\ninput wire [1:0] A;\ninput wire c_in;\ninput wire [1:0] B;\n \noutput wire c_out;\noutput wire [1:0] en_b;\n\nassign c_out = (A[0] & A[1]) | (A[1] & c_in); \nassign en_b = B + c_out;\n\nendmodule\n\nmodule encoder_3(A, c_in, B, en_b);\n\ninput wire [1:0] A;\ninput wire c_in;\ninput wire [1:0] B;\noutput wire [1:0] en_b;\n\nwire c_out;\nassign c_out = (A[0] & A[1]) | (A[1] & c_in); \nassign en_b = B + c_out;\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT3_OPT4C/pe/encoder_multi_bit.v", "module encoder_multi_bit #(\n localparam WIDTH = 8,\n localparam ENCODER_WIDTH = WIDTH + (WIDTH+1)%2,\n localparam TIMES = (WIDTH-1)/2 + (WIDTH-1)%2\n)(\n input clk,\n input rst_n,\n input [WIDTH-1:0] multiplicand,\n input multiplicand_valid, \n output reg [WIDTH:0] en_multiplicand, // native EN-T encoding is sent to tensorcore local memory or local rf.\n output en_multiplicand_valid\n );\n\nwire [WIDTH-1:0] encoder_input;\nwire [ENCODER_WIDTH-1:0] en_multiplicand_ins;\nwire [TIMES-1:0] en_t_c_out;\nreg [WIDTH-1:0] multiplicand_reg;\n\nassign encoder_input = (multiplicand_reg != 8'b10000000) ? {1'b0,multiplicand_reg[WIDTH-2:0]} : 8'b10000000;\nassign en_multiplicand_ins[ENCODER_WIDTH-1] = multiplicand_reg[WIDTH-1];\n\ngenvar i;\ngenerate for(i = 0; i < TIMES; i = i + 1) begin: gen_encoder \n if(i==0) begin\n assign en_multiplicand_ins[1:0] = multiplicand_reg[1:0];\n end\n else if (i==1)begin\n encoder ins_encoder\n (.A(encoder_input[2*i-1:2*i-2]),\n .C_IN(1'b0), \n .B(encoder_input[2*i+1:2*i]), \n .en_t_c_out(en_t_c_out[i]), \n .EN_B(en_multiplicand_ins[2*i+1:2*i]));\n end\n else begin\n encoder ins_encoder\n (.A(encoder_input[2*i-1:2*i-2]),\n .C_IN(en_t_c_out[i-1]), \n .B(encoder_input[2*i+1:2*i]), \n .en_t_c_out(en_t_c_out[i]), \n .EN_B(en_multiplicand_ins[2*i+1:2*i]));\n end \nend \nendgenerate \n\n\nalways @(posedge clk or negedge rst_n) begin\n\tif (!rst_n) begin\n en_multiplicand <= 0;\n multiplicand_reg <= 0;\n end\n\telse begin\n en_multiplicand <= en_multiplicand_ins; \n //multiplicand belongs to [-128,127] range and operand with complement representation use this logic:\n multiplicand_reg <= (multiplicand[WIDTH-1] & (multiplicand[WIDTH-2:0] != 0)) ? ({1'b1,~multiplicand[WIDTH-2:0] + 1'b1}) : multiplicand; \n //multiplicand belongs to [-127,127] range and operand with sign-magnitude representation use this logic:\n //multiplicand_reg <= multiplicand; \n end\nend\n\nget_pipeline_mulwidth #(\n .N(2), \n .WIDTH(1) \n) pipeline_en_multiplicand_valid (\n .clk(clk), \n .rst_n(rst_n), \n .signal(multiplicand_valid), \n .pipeline_signal(en_multiplicand_valid) \n);\n\nendmodule\n\n\nmodule encoder(A, C_IN, B, en_t_c_out, EN_B);\n\ninput wire [1:0] A;\ninput wire C_IN;\ninput wire [1:0] B;\n\noutput wire en_t_c_out;\noutput wire [1:0] EN_B;\n\nassign en_t_c_out = (A[0] & A[1]) | (A[1] & C_IN); \nassign EN_B = B + en_t_c_out;\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT3_OPT4C/array/top_pe_column.v", "module top_pe_column #(\n parameter N = 32,\n parameter ACC_WIDTH = 26\n\n)(\n input clk,\n input rst_n,\n input clr,\n input [7:0] en_multiplicand, // operand a\n input [3:0] sign_en_multiplicand,\n input encode_valid,\n input [8*N-1:0] operand_b, \n output [1:0] position, // to prefetch operand b \n output [2:0] cal_cycle, // to prefetch operand a \n output [52*N-1:0] pe_result \n);\n\nwire [1:0] partial_product_index;\n\ngenvar i;\nsparse_encoder sp_encoder(\n .clk(clk),\n .rst_n(rst_n),\n .en_multiplicand(en_multiplicand),\n .sign_en_multiplicand(sign_en_multiplicand),\n .encode_valid(encode_valid),\n .partial_product_index(partial_product_index), // to sparse_pe generate partial product\n .position_0(position), // to prefetch operand b\n .cal_cycle(cal_cycle) // to prefetch operand a \n);\n\ngenerate\nfor (i = 0 ; i < N ; i = i + 1) begin\n pe #(\n .ACC_WIDTH(26)\n ) sparse_pe (\n .clk(clk),\n .rst_n(rst_n),\n .clr(clr),\n .encoder_position_ins(partial_product_index),\n .operand_b_ins(operand_b[8*(i+1)-1:8*i]),\n .result(pe_result[52*(i+1)-1:52*i])\n );\nend\nendgenerate\n\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT2/get_pipline_mulwidth.v", "module get_pipeline_mulwidth #(\n parameter N = 4,\n parameter WIDTH = 8 \n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] signal,\n output wire [WIDTH-1:0] pipeline_signal\n);\n\n\nreg [WIDTH-1:0] pipeline_regs [N-1:0];\n\n\n genvar i;\n generate\n for (i = 0; i < N; i = i + 1) begin : pipeline_stage\n always @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n pipeline_regs[i] <= 0; \n end else begin\n if (i == 0) begin\n pipeline_regs[i] <= signal; \n end else begin\n pipeline_regs[i] <= pipeline_regs[i-1]; \n end\n end\n end\n end\n endgenerate\n\n\n assign pipeline_signal = pipeline_regs[N-1];\n\nendmodule\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT3_OPT4C/pe/get_pipline_mulwidth.v", "module get_pipeline_mulwidth #(\n parameter N = 4,\n parameter WIDTH = 8 \n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] signal,\n output wire [WIDTH-1:0] pipeline_signal\n);\n\n\nreg [WIDTH-1:0] pipeline_regs [N-1:0];\n\n\n genvar i;\n generate\n for (i = 0; i < N; i = i + 1) begin : pipeline_stage\n always @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n pipeline_regs[i] <= 0; \n end else begin\n if (i == 0) begin\n pipeline_regs[i] <= signal; \n end else begin\n pipeline_regs[i] <= pipeline_regs[i-1]; \n end\n end\n end\n end\n endgenerate\n\n\n assign pipeline_signal = pipeline_regs[N-1];\n\nendmodule\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/dff_async.v", "module dff_async #(\n parameter WIDTH = 8\n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] d,\n output reg [WIDTH-1:0] q\n);\n\nalways @(posedge clk or negedge rst_n) begin\n if (!rst_n) begin\n q <= 0;\n end\n else begin\n q <= d;\n end\nend\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT3_OPT4C/pe/top_pe.v", "module top_pe(\n input clk,\n input rst_n,\n input clr,\n input [7:0] en_multiplicand, // operand a\n input [3:0] sign_en_multiplicand,\n input encode_valid,\n input [7:0] operand_b, \n output [1:0] position, // to prefetch operand b \n output [2:0] cal_cycle, // to prefetch operand a \n output [51:0] pe_result \n);\n\nwire [1:0] partial_product_index;\n\nsparse_encoder sp_encoder(\n .clk(clk),\n .rst_n(rst_n),\n .en_multiplicand(en_multiplicand),\n .sign_en_multiplicand(sign_en_multiplicand),\n .encode_valid(encode_valid),\n .partial_product_index(partial_product_index), // to sparse_pe generate partial product\n .position_0(position), // to prefetch operand b\n .cal_cycle(cal_cycle) // to prefetch operand a \n);\n\n\npe #(\n .ACC_WIDTH(26)\n) sparse_pe (\n .clk(clk),\n .rst_n(rst_n),\n .clr(clr),\n .encoder_position_ins(partial_product_index),\n .operand_b_ins(operand_b),\n .result(pe_result)\n);\n\n\n\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_mac_based/get_pipline_mulwidth.v", "module get_pipeline_mulwidth #(\n parameter N = 4,\n parameter WIDTH = 8 \n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] signal,\n output wire [WIDTH-1:0] pipeline_signal\n);\n\n\n reg [WIDTH-1:0] pipeline_regs [N-1:0];\n\n\n genvar i;\n generate\n for (i = 0; i < N; i = i + 1) begin : pipeline_stage\n always @(posedge clk) begin\n if(~rst_n) \n pipeline_regs[i] <= 0;\n else begin\n if (i == 0) begin\n pipeline_regs[i] <= signal; \n end else begin\n pipeline_regs[i] <= pipeline_regs[i-1]; \n end\n end\n end\n end\n endgenerate\n\n\n assign pipeline_signal = pipeline_regs[N-1];\n\nendmodule\n\n\n// // 实例化 get_pipeline_mulwidth 模块\n// get_pipeline_mulwidth #(\n// .N(4), // 设置流水线深度为 4\n// .WIDTH(8) // 设置信号宽度为 8 位\n// ) pipeline_inst (\n// .clk(clk), // 连接时钟信号\n// .rst_n(rst_n), // 连接复位信号\n// .signal(input_signal), // 连接输入信号\n// .pipeline_signal(output_signal) // 连接输出信号\n// );\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/get_pipline_mulwidth.v", "module get_pipeline_mulwidth #(\n parameter N = 4,\n parameter WIDTH = 8 \n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] signal,\n output wire [WIDTH-1:0] pipeline_signal\n);\n\n\n reg [WIDTH-1:0] pipeline_regs [N-1:0];\n\n\n genvar i;\n generate\n for (i = 0; i < N; i = i + 1) begin : pipeline_stage\n always @(posedge clk) begin\n if(~rst_n) \n pipeline_regs[i] <= 0;\n else begin\n if (i == 0) begin\n pipeline_regs[i] <= signal; \n end else begin\n pipeline_regs[i] <= pipeline_regs[i-1]; \n end\n end\n end\n end\n endgenerate\n\n\n assign pipeline_signal = pipeline_regs[N-1];\n\nendmodule\n\n\n// // 实例化 get_pipeline_mulwidth 模块\n// get_pipeline_mulwidth #(\n// .N(4), // 设置流水线深度为 4\n// .WIDTH(8) // 设置信号宽度为 8 位\n// ) pipeline_inst (\n// .clk(clk), // 连接时钟信号\n// .rst_n(rst_n), // 连接复位信号\n// .signal(input_signal), // 连接输入信号\n// .pipeline_signal(output_signal) // 连接输出信号\n// );\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_mac_based/get_pipline_mulwidth.v", "module get_pipeline_mulwidth #(\n parameter N = 4,\n parameter WIDTH = 8 \n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] signal,\n output wire [WIDTH-1:0] pipeline_signal\n);\n\n\n reg [WIDTH-1:0] pipeline_regs [N-1:0];\n\n\n genvar i;\n generate\n for (i = 0; i < N; i = i + 1) begin : pipeline_stage\n always @(posedge clk) begin\n if(~rst_n) \n pipeline_regs[i] <= 0;\n else begin\n if (i == 0) begin\n pipeline_regs[i] <= signal; \n end else begin\n pipeline_regs[i] <= pipeline_regs[i-1]; \n end\n end\n end\n end\n endgenerate\n\n\n assign pipeline_signal = pipeline_regs[N-1];\n\nendmodule\n\n\n// // 实例化 get_pipeline_mulwidth 模块\n// get_pipeline_mulwidth #(\n// .N(4), // 设置流水线深度为 4\n// .WIDTH(8) // 设置信号宽度为 8 位\n// ) pipeline_inst (\n// .clk(clk), // 连接时钟信号\n// .rst_n(rst_n), // 连接复位信号\n// .signal(input_signal), // 连接输入信号\n// .pipeline_signal(output_signal) // 连接输出信号\n// );\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_mac_based/get_pipline_mulwidth.v", "module get_pipeline_mulwidth #(\n parameter N = 4,\n parameter WIDTH = 8 \n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] signal,\n output wire [WIDTH-1:0] pipeline_signal\n);\n\n\n reg [WIDTH-1:0] pipeline_regs [N-1:0];\n\n\n genvar i;\n generate\n for (i = 0; i < N; i = i + 1) begin : pipeline_stage\n always @(posedge clk) begin\n if(~rst_n) \n pipeline_regs[i] <= 0;\n else begin\n if (i == 0) begin\n pipeline_regs[i] <= signal; \n end else begin\n pipeline_regs[i] <= pipeline_regs[i-1]; \n end\n end\n end\n end\n endgenerate\n\n\n assign pipeline_signal = pipeline_regs[N-1];\n\nendmodule\n\n\n// // 实例化 get_pipeline_mulwidth 模块\n// get_pipeline_mulwidth #(\n// .N(4), // 设置流水线深度为 4\n// .WIDTH(8) // 设置信号宽度为 8 位\n// ) pipeline_inst (\n// .clk(clk), // 连接时钟信号\n// .rst_n(rst_n), // 连接复位信号\n// .signal(input_signal), // 连接输入信号\n// .pipeline_signal(output_signal) // 连接输出信号\n// );\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/get_pipline_mulwidth.v", "module get_pipeline_mulwidth #(\n parameter N = 4,\n parameter WIDTH = 8 \n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] signal,\n output wire [WIDTH-1:0] pipeline_signal\n);\n\n\n reg [WIDTH-1:0] pipeline_regs [N-1:0];\n\n\n genvar i;\n generate\n for (i = 0; i < N; i = i + 1) begin : pipeline_stage\n always @(posedge clk) begin\n if(~rst_n) \n pipeline_regs[i] <= 0;\n else begin\n if (i == 0) begin\n pipeline_regs[i] <= signal; \n end else begin\n pipeline_regs[i] <= pipeline_regs[i-1]; \n end\n end\n end\n end\n endgenerate\n\n\n assign pipeline_signal = pipeline_regs[N-1];\n\nendmodule\n\n\n// // 实例化 get_pipeline_mulwidth 模块\n// get_pipeline_mulwidth #(\n// .N(4), // 设置流水线深度为 4\n// .WIDTH(8) // 设置信号宽度为 8 位\n// ) pipeline_inst (\n// .clk(clk), // 连接时钟信号\n// .rst_n(rst_n), // 连接复位信号\n// .signal(input_signal), // 连接输入信号\n// .pipeline_signal(output_signal) // 连接输出信号\n// );\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/get_pipline_mulwidth.v", "module get_pipeline_mulwidth #(\n parameter N = 4,\n parameter WIDTH = 8 \n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] signal,\n output wire [WIDTH-1:0] pipeline_signal\n);\n\n\n reg [WIDTH-1:0] pipeline_regs [N-1:0];\n\n\n genvar i;\n generate\n for (i = 0; i < N; i = i + 1) begin : pipeline_stage\n always @(posedge clk) begin\n if(~rst_n) \n pipeline_regs[i] <= 0;\n else begin\n if (i == 0) begin\n pipeline_regs[i] <= signal; \n end else begin\n pipeline_regs[i] <= pipeline_regs[i-1]; \n end\n end\n end\n end\n endgenerate\n\n\n assign pipeline_signal = pipeline_regs[N-1];\n\nendmodule\n\n\n// // 实例化 get_pipeline_mulwidth 模块\n// get_pipeline_mulwidth #(\n// .N(4), // 设置流水线深度为 4\n// .WIDTH(8) // 设置信号宽度为 8 位\n// ) pipeline_inst (\n// .clk(clk), // 连接时钟信号\n// .rst_n(rst_n), // 连接复位信号\n// .signal(input_signal), // 连接输入信号\n// .pipeline_signal(output_signal) // 连接输出信号\n// );\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/booth_pp_gen.v", "module booth_pp_gen(\n input wire [7:0] operand_a, \n input wire [7:0] operand_b, \n output wire [9:0] pp1,\n output wire [9:0] pp2,\n output wire [9:0] pp3,\n output wire [9:0] pp4 \n );\n\n wire [1:0] operand_slice_a1 ;\n wire [2:0] operand_slice_a2 ;\n wire [2:0] operand_slice_a3 ;\n wire [2:0] operand_slice_a4 ;\n wire [8:0] operand_b_neg ;\n \n inv_converter_8 inv_converter_8_inst(\n .data_i (operand_b),\n .inv_o (operand_b_neg) \n );\n \n assign operand_slice_a1 = operand_a[1:0] ;\n assign operand_slice_a2 = operand_a[3:1] ;\n assign operand_slice_a3 = operand_a[5:3] ;\n assign operand_slice_a4 = operand_a[7:5] ;\n\n booth_partial_product_generator_pp1 ppg_1 (\n .operand_slice_a (operand_slice_a1), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp1) \n );\n\n booth_partial_product_generator ppg_2 (\n .operand_slice_a (operand_slice_a2), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp2) \n );\n\n booth_partial_product_generator ppg_3 (\n .operand_slice_a (operand_slice_a3), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp3) \n );\n\n booth_partial_product_generator ppg_4 (\n .operand_slice_a (operand_slice_a4), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp4) \n );\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/booth_pp_gen.v", "module booth_pp_gen(\n input wire [7:0] operand_a, \n input wire [7:0] operand_b, \n output wire [9:0] pp1,\n output wire [9:0] pp2,\n output wire [9:0] pp3,\n output wire [9:0] pp4 \n );\n\n wire [1:0] operand_slice_a1 ;\n wire [2:0] operand_slice_a2 ;\n wire [2:0] operand_slice_a3 ;\n wire [2:0] operand_slice_a4 ;\n wire [8:0] operand_b_neg ;\n \n inv_converter_8 inv_converter_8_inst(\n .data_i (operand_b),\n .inv_o (operand_b_neg) \n );\n \n assign operand_slice_a1 = operand_a[1:0] ;\n assign operand_slice_a2 = operand_a[3:1] ;\n assign operand_slice_a3 = operand_a[5:3] ;\n assign operand_slice_a4 = operand_a[7:5] ;\n\n booth_partial_product_generator_pp1 ppg_1 (\n .operand_slice_a (operand_slice_a1), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp1) \n );\n\n booth_partial_product_generator ppg_2 (\n .operand_slice_a (operand_slice_a2), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp2) \n );\n\n booth_partial_product_generator ppg_3 (\n .operand_slice_a (operand_slice_a3), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp3) \n );\n\n booth_partial_product_generator ppg_4 (\n .operand_slice_a (operand_slice_a4), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp4) \n );\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/booth_pp_gen.v", "module booth_pp_gen(\n input wire [7:0] operand_a, \n input wire [7:0] operand_b, \n output wire [9:0] pp1,\n output wire [9:0] pp2,\n output wire [9:0] pp3,\n output wire [9:0] pp4 \n );\n\n wire [1:0] operand_slice_a1 ;\n wire [2:0] operand_slice_a2 ;\n wire [2:0] operand_slice_a3 ;\n wire [2:0] operand_slice_a4 ;\n wire [8:0] operand_b_neg ;\n \n inv_converter_8 inv_converter_8_inst(\n .data_i (operand_b),\n .inv_o (operand_b_neg) \n );\n \n assign operand_slice_a1 = operand_a[1:0] ;\n assign operand_slice_a2 = operand_a[3:1] ;\n assign operand_slice_a3 = operand_a[5:3] ;\n assign operand_slice_a4 = operand_a[7:5] ;\n\n booth_partial_product_generator_pp1 ppg_1 (\n .operand_slice_a (operand_slice_a1), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp1) \n );\n\n booth_partial_product_generator ppg_2 (\n .operand_slice_a (operand_slice_a2), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp2) \n );\n\n booth_partial_product_generator ppg_3 (\n .operand_slice_a (operand_slice_a3), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp3) \n );\n\n booth_partial_product_generator ppg_4 (\n .operand_slice_a (operand_slice_a4), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp4) \n );\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/booth_pp_gen.v", "module booth_pp_gen(\n input wire [7:0] operand_a, \n input wire [7:0] operand_b, \n output wire [9:0] pp1,\n output wire [9:0] pp2,\n output wire [9:0] pp3,\n output wire [9:0] pp4 \n );\n\n wire [1:0] operand_slice_a1 ;\n wire [2:0] operand_slice_a2 ;\n wire [2:0] operand_slice_a3 ;\n wire [2:0] operand_slice_a4 ;\n wire [8:0] operand_b_neg ;\n \n inv_converter_8 inv_converter_8_inst(\n .data_i (operand_b),\n .inv_o (operand_b_neg) \n );\n \n assign operand_slice_a1 = operand_a[1:0] ;\n assign operand_slice_a2 = operand_a[3:1] ;\n assign operand_slice_a3 = operand_a[5:3] ;\n assign operand_slice_a4 = operand_a[7:5] ;\n\n booth_partial_product_generator_pp1 ppg_1 (\n .operand_slice_a (operand_slice_a1), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp1) \n );\n\n booth_partial_product_generator ppg_2 (\n .operand_slice_a (operand_slice_a2), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp2) \n );\n\n booth_partial_product_generator ppg_3 (\n .operand_slice_a (operand_slice_a3), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp3) \n );\n\n booth_partial_product_generator ppg_4 (\n .operand_slice_a (operand_slice_a4), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp4) \n );\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT2/weight_rf.sv", "module weight_rf (\n input clk,\n input wen,\n input [7:0] din,\n output [7:0] weight [0:15]\n);\n\nreg [7:0] buffer [0:15];\n\nassign weight = buffer;\n\ngenvar i;\ngenerate\n for (i = 0; i < 16; i = i + 1) begin\n always @(posedge clk) begin\n if(wen) begin\n if (i==15)\n buffer[i] <= din;\n else \n buffer[i] <= buffer[i+1];\n end\n else\n buffer[i] <= buffer[i];\n end\n end\nendgenerate\n\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/DW02_tree.sv", "////////////////////////////////////////////////////////////////////////////////\n//\n// This confidential and proprietary software may be used only\n// as authorized by a licensing agreement from Synopsys Inc.\n// In the event of publication, the following notice is applicable:\n//\n// (C) COPYRIGHT 2000 - 2021 SYNOPSYS INC.\n// ALL RIGHTS RESERVED\n//\n// The entire notice above must be reproduced on all authorized\n// copies.\n//\n// AUTHOR: Rick Kelly 07/28/2000\n//\n// VERSION: Verilog Simulation Model for DW02_tree\n//\n// DesignWare_version: aacb4808\n// DesignWare_release: S-2021.06-DWBB_202106.4\n//\n////////////////////////////////////////////////////////////////////////////////\n\n//-----------------------------------------------------------------------------------\n//\n// ABSTRACT: Wallace Tree Summer with Carry Save output\n//\n// MODIFIED:\n// Aamir Farooqui 7/11/02\n// Corrected parameter checking, simplied sim model, and X_processing\n//\n//------------------------------------------------------------------------------\n//\n\n // synopsys translate_off\n// `ifdef VCS\n// `include \"DW02_tree.v\"\n// `else\n // synopsys translate_on\n\nmodule DW02_tree( INPUT, OUT0, OUT1 );\n\n// parameters\nparameter integer num_inputs = 8;\nparameter integer input_width = 8;\nparameter integer verif_en = 1;\n\n//-----------------------------------------------------------------------------\n// ports\ninput [num_inputs*input_width-1 : 0]\tINPUT;\noutput [input_width-1:0]\t\tOUT0, OUT1;\n\n//-----------------------------------------------------------------------------\n// synopsys translate_off\nreg [input_width-1:0]\t\tOII0OOOI, O001l0I0;\n\n//-----------------------------------------------------------------------------\n \n \n// initial begin : parameter_check\n// integer param_err_flg;\n\n// param_err_flg = 0;\n \n \n// if (num_inputs < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter num_inputs (lower bound: 1)\",\n// \tnum_inputs );\n// end\n \n// if (input_width < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter input_width (lower bound: 1)\",\n// \tinput_width );\n// end\n \n// if ( (verif_en < 0) || (verif_en > 1) ) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter verif_en (legal range: 0 to 1)\",\n// \tverif_en );\n// end\n \n// if ( param_err_flg == 1) begin\n// $display(\n// \"%m :\\n Simulation aborted due to invalid parameter value(s)\");\n// $finish;\n// end\n\n// end // parameter_check \n\n\n// `ifndef DW_SUPPRESS_WARN\n// initial begin : verif_en_warning\n// $display(\"The parameter verif_en is set to 0 for this simulator.\\nOther values for verif_en are enabled only for VCS.\");\n// end // verif_en_warning\n// `endif\n\n//-----------------------------------------------------------------------------\n\n\n\nalways @ (INPUT) begin : IIIIO1Ol\n reg [input_width-1 : 0] I0lII01I [0 : num_inputs-1];\n reg [input_width-1 : 0] l10III00 [0 : num_inputs-1];\n reg [input_width-1 : 0] IIIO00Ol, lI0OII0O;\n integer I1I1O00I, O1OIIOII, IlI01lIO;\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII=O1OIIOII+1) begin\n for (IlI01lIO=0 ; IlI01lIO < input_width ; IlI01lIO=IlI01lIO+1) begin\n IIIO00Ol[IlI01lIO] = INPUT[O1OIIOII*input_width+IlI01lIO];\n end // for IlI01lIO\n I0lII01I[O1OIIOII] = IIIO00Ol;\n end // for O1OIIOII\n\n I1I1O00I = num_inputs;\n\n while (I1I1O00I > 2)\n begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I/3) ; O1OIIOII = O1OIIOII+1) begin\n l10III00[O1OIIOII*2] = I0lII01I[O1OIIOII*3] ^ I0lII01I[O1OIIOII*3+1] ^ I0lII01I[O1OIIOII*3+2];\n\n lI0OII0O = (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+1]) |\n (I0lII01I[O1OIIOII*3+1] & I0lII01I[O1OIIOII*3+2]) |\n (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+2]);\n\n l10III00[O1OIIOII*2+1] = lI0OII0O << 1;\n end\n if ((I1I1O00I % 3) > 0) begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I % 3) ; O1OIIOII = O1OIIOII + 1)\n l10III00[2 * (I1I1O00I/3) + O1OIIOII] = I0lII01I[3 * (I1I1O00I/3) + O1OIIOII];\n end\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII = O1OIIOII + 1)\n I0lII01I[O1OIIOII] = l10III00[O1OIIOII];\n I1I1O00I = I1I1O00I - (I1I1O00I/3);\n end\n OII0OOOI = I0lII01I[0];\n if (I1I1O00I > 1)\n O001l0I0 = I0lII01I[1];\n else\n O001l0I0 = {input_width{1'b0}};\nend // IIIIO1Ol\n\n\nassign OUT0 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : OII0OOOI;\nassign OUT1 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : O001l0I0;\n\n// synopsys translate_on\n\nendmodule\n // synopsys translate_off\n// `endif\n // synopsys translate_on\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/DW02_tree.sv", "////////////////////////////////////////////////////////////////////////////////\n//\n// This confidential and proprietary software may be used only\n// as authorized by a licensing agreement from Synopsys Inc.\n// In the event of publication, the following notice is applicable:\n//\n// (C) COPYRIGHT 2000 - 2021 SYNOPSYS INC.\n// ALL RIGHTS RESERVED\n//\n// The entire notice above must be reproduced on all authorized\n// copies.\n//\n// AUTHOR: Rick Kelly 07/28/2000\n//\n// VERSION: Verilog Simulation Model for DW02_tree\n//\n// DesignWare_version: aacb4808\n// DesignWare_release: S-2021.06-DWBB_202106.4\n//\n////////////////////////////////////////////////////////////////////////////////\n\n//-----------------------------------------------------------------------------------\n//\n// ABSTRACT: Wallace Tree Summer with Carry Save output\n//\n// MODIFIED:\n// Aamir Farooqui 7/11/02\n// Corrected parameter checking, simplied sim model, and X_processing\n//\n//------------------------------------------------------------------------------\n//\n\n // synopsys translate_off\n// `ifdef VCS\n// `include \"DW02_tree.v\"\n// `else\n // synopsys translate_on\n\nmodule DW02_tree( INPUT, OUT0, OUT1 );\n\n// parameters\nparameter integer num_inputs = 8;\nparameter integer input_width = 8;\nparameter integer verif_en = 1;\n\n//-----------------------------------------------------------------------------\n// ports\ninput [num_inputs*input_width-1 : 0]\tINPUT;\noutput [input_width-1:0]\t\tOUT0, OUT1;\n\n//-----------------------------------------------------------------------------\n// synopsys translate_off\nreg [input_width-1:0]\t\tOII0OOOI, O001l0I0;\n\n//-----------------------------------------------------------------------------\n \n \n// initial begin : parameter_check\n// integer param_err_flg;\n\n// param_err_flg = 0;\n \n \n// if (num_inputs < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter num_inputs (lower bound: 1)\",\n// \tnum_inputs );\n// end\n \n// if (input_width < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter input_width (lower bound: 1)\",\n// \tinput_width );\n// end\n \n// if ( (verif_en < 0) || (verif_en > 1) ) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter verif_en (legal range: 0 to 1)\",\n// \tverif_en );\n// end\n \n// if ( param_err_flg == 1) begin\n// $display(\n// \"%m :\\n Simulation aborted due to invalid parameter value(s)\");\n// $finish;\n// end\n\n// end // parameter_check \n\n\n// `ifndef DW_SUPPRESS_WARN\n// initial begin : verif_en_warning\n// $display(\"The parameter verif_en is set to 0 for this simulator.\\nOther values for verif_en are enabled only for VCS.\");\n// end // verif_en_warning\n// `endif\n\n//-----------------------------------------------------------------------------\n\n\n\nalways @ (INPUT) begin : IIIIO1Ol\n reg [input_width-1 : 0] I0lII01I [0 : num_inputs-1];\n reg [input_width-1 : 0] l10III00 [0 : num_inputs-1];\n reg [input_width-1 : 0] IIIO00Ol, lI0OII0O;\n integer I1I1O00I, O1OIIOII, IlI01lIO;\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII=O1OIIOII+1) begin\n for (IlI01lIO=0 ; IlI01lIO < input_width ; IlI01lIO=IlI01lIO+1) begin\n IIIO00Ol[IlI01lIO] = INPUT[O1OIIOII*input_width+IlI01lIO];\n end // for IlI01lIO\n I0lII01I[O1OIIOII] = IIIO00Ol;\n end // for O1OIIOII\n\n I1I1O00I = num_inputs;\n\n while (I1I1O00I > 2)\n begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I/3) ; O1OIIOII = O1OIIOII+1) begin\n l10III00[O1OIIOII*2] = I0lII01I[O1OIIOII*3] ^ I0lII01I[O1OIIOII*3+1] ^ I0lII01I[O1OIIOII*3+2];\n\n lI0OII0O = (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+1]) |\n (I0lII01I[O1OIIOII*3+1] & I0lII01I[O1OIIOII*3+2]) |\n (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+2]);\n\n l10III00[O1OIIOII*2+1] = lI0OII0O << 1;\n end\n if ((I1I1O00I % 3) > 0) begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I % 3) ; O1OIIOII = O1OIIOII + 1)\n l10III00[2 * (I1I1O00I/3) + O1OIIOII] = I0lII01I[3 * (I1I1O00I/3) + O1OIIOII];\n end\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII = O1OIIOII + 1)\n I0lII01I[O1OIIOII] = l10III00[O1OIIOII];\n I1I1O00I = I1I1O00I - (I1I1O00I/3);\n end\n OII0OOOI = I0lII01I[0];\n if (I1I1O00I > 1)\n O001l0I0 = I0lII01I[1];\n else\n O001l0I0 = {input_width{1'b0}};\nend // IIIIO1Ol\n\n\nassign OUT0 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : OII0OOOI;\nassign OUT1 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : O001l0I0;\n\n// synopsys translate_on\n\nendmodule\n // synopsys translate_off\n// `endif\n // synopsys translate_on\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/DW02_tree.sv", "////////////////////////////////////////////////////////////////////////////////\n//\n// This confidential and proprietary software may be used only\n// as authorized by a licensing agreement from Synopsys Inc.\n// In the event of publication, the following notice is applicable:\n//\n// (C) COPYRIGHT 2000 - 2021 SYNOPSYS INC.\n// ALL RIGHTS RESERVED\n//\n// The entire notice above must be reproduced on all authorized\n// copies.\n//\n// AUTHOR: Rick Kelly 07/28/2000\n//\n// VERSION: Verilog Simulation Model for DW02_tree\n//\n// DesignWare_version: aacb4808\n// DesignWare_release: S-2021.06-DWBB_202106.4\n//\n////////////////////////////////////////////////////////////////////////////////\n\n//-----------------------------------------------------------------------------------\n//\n// ABSTRACT: Wallace Tree Summer with Carry Save output\n//\n// MODIFIED:\n// Aamir Farooqui 7/11/02\n// Corrected parameter checking, simplied sim model, and X_processing\n//\n//------------------------------------------------------------------------------\n//\n\n // synopsys translate_off\n// `ifdef VCS\n// `include \"DW02_tree.v\"\n// `else\n // synopsys translate_on\n\nmodule DW02_tree( INPUT, OUT0, OUT1 );\n\n// parameters\nparameter integer num_inputs = 8;\nparameter integer input_width = 8;\nparameter integer verif_en = 1;\n\n//-----------------------------------------------------------------------------\n// ports\ninput [num_inputs*input_width-1 : 0]\tINPUT;\noutput [input_width-1:0]\t\tOUT0, OUT1;\n\n//-----------------------------------------------------------------------------\n// synopsys translate_off\nreg [input_width-1:0]\t\tOII0OOOI, O001l0I0;\n\n//-----------------------------------------------------------------------------\n \n \n// initial begin : parameter_check\n// integer param_err_flg;\n\n// param_err_flg = 0;\n \n \n// if (num_inputs < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter num_inputs (lower bound: 1)\",\n// \tnum_inputs );\n// end\n \n// if (input_width < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter input_width (lower bound: 1)\",\n// \tinput_width );\n// end\n \n// if ( (verif_en < 0) || (verif_en > 1) ) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter verif_en (legal range: 0 to 1)\",\n// \tverif_en );\n// end\n \n// if ( param_err_flg == 1) begin\n// $display(\n// \"%m :\\n Simulation aborted due to invalid parameter value(s)\");\n// $finish;\n// end\n\n// end // parameter_check \n\n\n// `ifndef DW_SUPPRESS_WARN\n// initial begin : verif_en_warning\n// $display(\"The parameter verif_en is set to 0 for this simulator.\\nOther values for verif_en are enabled only for VCS.\");\n// end // verif_en_warning\n// `endif\n\n//-----------------------------------------------------------------------------\n\n\n\nalways @ (INPUT) begin : IIIIO1Ol\n reg [input_width-1 : 0] I0lII01I [0 : num_inputs-1];\n reg [input_width-1 : 0] l10III00 [0 : num_inputs-1];\n reg [input_width-1 : 0] IIIO00Ol, lI0OII0O;\n integer I1I1O00I, O1OIIOII, IlI01lIO;\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII=O1OIIOII+1) begin\n for (IlI01lIO=0 ; IlI01lIO < input_width ; IlI01lIO=IlI01lIO+1) begin\n IIIO00Ol[IlI01lIO] = INPUT[O1OIIOII*input_width+IlI01lIO];\n end // for IlI01lIO\n I0lII01I[O1OIIOII] = IIIO00Ol;\n end // for O1OIIOII\n\n I1I1O00I = num_inputs;\n\n while (I1I1O00I > 2)\n begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I/3) ; O1OIIOII = O1OIIOII+1) begin\n l10III00[O1OIIOII*2] = I0lII01I[O1OIIOII*3] ^ I0lII01I[O1OIIOII*3+1] ^ I0lII01I[O1OIIOII*3+2];\n\n lI0OII0O = (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+1]) |\n (I0lII01I[O1OIIOII*3+1] & I0lII01I[O1OIIOII*3+2]) |\n (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+2]);\n\n l10III00[O1OIIOII*2+1] = lI0OII0O << 1;\n end\n if ((I1I1O00I % 3) > 0) begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I % 3) ; O1OIIOII = O1OIIOII + 1)\n l10III00[2 * (I1I1O00I/3) + O1OIIOII] = I0lII01I[3 * (I1I1O00I/3) + O1OIIOII];\n end\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII = O1OIIOII + 1)\n I0lII01I[O1OIIOII] = l10III00[O1OIIOII];\n I1I1O00I = I1I1O00I - (I1I1O00I/3);\n end\n OII0OOOI = I0lII01I[0];\n if (I1I1O00I > 1)\n O001l0I0 = I0lII01I[1];\n else\n O001l0I0 = {input_width{1'b0}};\nend // IIIIO1Ol\n\n\nassign OUT0 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : OII0OOOI;\nassign OUT1 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : O001l0I0;\n\n// synopsys translate_on\n\nendmodule\n // synopsys translate_off\n// `endif\n // synopsys translate_on\n"], ["/High-Performance-Tensor-Processing-Engines/OPT2/DW02_tree.sv", "//-----------------------------------------------------------------------------------\n//\n// ABSTRACT: Wallace Tree Summer with Carry Save output\n//\n//------------------------------------------------------------------------------\n//\n\n // synopsys translate_off\n// `ifdef VCS\n// `include \"DW02_tree.v\"\n// `else\n // synopsys translate_on\n\nmodule DW02_tree( INPUT, OUT0, OUT1 );\n\n// parameters\nparameter integer num_inputs = 8;\nparameter integer input_width = 8;\nparameter integer verif_en = 1;\n\n//-----------------------------------------------------------------------------\n// ports\ninput [num_inputs*input_width-1 : 0]\tINPUT;\noutput [input_width-1:0]\t\tOUT0, OUT1;\n\n//-----------------------------------------------------------------------------\n// synopsys translate_off\nreg [input_width-1:0]\t\tOII0OOOI, O001l0I0;\n\n//-----------------------------------------------------------------------------\n \n \n// initial begin : parameter_check\n// integer param_err_flg;\n\n// param_err_flg = 0;\n \n \n// if (num_inputs < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter num_inputs (lower bound: 1)\",\n// \tnum_inputs );\n// end\n \n// if (input_width < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter input_width (lower bound: 1)\",\n// \tinput_width );\n// end\n \n// if ( (verif_en < 0) || (verif_en > 1) ) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter verif_en (legal range: 0 to 1)\",\n// \tverif_en );\n// end\n \n// if ( param_err_flg == 1) begin\n// $display(\n// \"%m :\\n Simulation aborted due to invalid parameter value(s)\");\n// $finish;\n// end\n\n// end // parameter_check \n\n\n// `ifndef DW_SUPPRESS_WARN\n// initial begin : verif_en_warning\n// $display(\"The parameter verif_en is set to 0 for this simulator.\\nOther values for verif_en are enabled only for VCS.\");\n// end // verif_en_warning\n// `endif\n\n//-----------------------------------------------------------------------------\n\n\n\nalways @ (INPUT) begin : IIIIO1Ol\n reg [input_width-1 : 0] I0lII01I [0 : num_inputs-1];\n reg [input_width-1 : 0] l10III00 [0 : num_inputs-1];\n reg [input_width-1 : 0] IIIO00Ol, lI0OII0O;\n integer I1I1O00I, O1OIIOII, IlI01lIO;\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII=O1OIIOII+1) begin\n for (IlI01lIO=0 ; IlI01lIO < input_width ; IlI01lIO=IlI01lIO+1) begin\n IIIO00Ol[IlI01lIO] = INPUT[O1OIIOII*input_width+IlI01lIO];\n end // for IlI01lIO\n I0lII01I[O1OIIOII] = IIIO00Ol;\n end // for O1OIIOII\n\n I1I1O00I = num_inputs;\n\n while (I1I1O00I > 2)\n begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I/3) ; O1OIIOII = O1OIIOII+1) begin\n l10III00[O1OIIOII*2] = I0lII01I[O1OIIOII*3] ^ I0lII01I[O1OIIOII*3+1] ^ I0lII01I[O1OIIOII*3+2];\n\n lI0OII0O = (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+1]) |\n (I0lII01I[O1OIIOII*3+1] & I0lII01I[O1OIIOII*3+2]) |\n (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+2]);\n\n l10III00[O1OIIOII*2+1] = lI0OII0O << 1;\n end\n if ((I1I1O00I % 3) > 0) begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I % 3) ; O1OIIOII = O1OIIOII + 1)\n l10III00[2 * (I1I1O00I/3) + O1OIIOII] = I0lII01I[3 * (I1I1O00I/3) + O1OIIOII];\n end\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII = O1OIIOII + 1)\n I0lII01I[O1OIIOII] = l10III00[O1OIIOII];\n I1I1O00I = I1I1O00I - (I1I1O00I/3);\n end\n OII0OOOI = I0lII01I[0];\n if (I1I1O00I > 1)\n O001l0I0 = I0lII01I[1];\n else\n O001l0I0 = {input_width{1'b0}};\nend // IIIIO1Ol\n\n\nassign OUT0 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : OII0OOOI;\nassign OUT1 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : O001l0I0;\n\n// synopsys translate_on\n\nendmodule\n // synopsys translate_off\n// `endif\n // synopsys translate_on\n"], ["/High-Performance-Tensor-Processing-Engines/OPT3_OPT4C/pe/DW02_tree.sv", "//-----------------------------------------------------------------------------------\n//\n// ABSTRACT: Wallace Tree Summer with Carry Save output\n//\n//------------------------------------------------------------------------------\n//\n\n // synopsys translate_off\n// `ifdef VCS\n// `include \"DW02_tree.v\"\n// `else\n // synopsys translate_on\n\nmodule DW02_tree( INPUT, OUT0, OUT1 );\n\n// parameters\nparameter integer num_inputs = 8;\nparameter integer input_width = 8;\nparameter integer verif_en = 1;\n\n//-----------------------------------------------------------------------------\n// ports\ninput [num_inputs*input_width-1 : 0]\tINPUT;\noutput [input_width-1:0]\t\tOUT0, OUT1;\n\n//-----------------------------------------------------------------------------\n// synopsys translate_off\nreg [input_width-1:0]\t\tOII0OOOI, O001l0I0;\n\n//-----------------------------------------------------------------------------\n \n \n// initial begin : parameter_check\n// integer param_err_flg;\n\n// param_err_flg = 0;\n \n \n// if (num_inputs < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter num_inputs (lower bound: 1)\",\n// \tnum_inputs );\n// end\n \n// if (input_width < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter input_width (lower bound: 1)\",\n// \tinput_width );\n// end\n \n// if ( (verif_en < 0) || (verif_en > 1) ) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter verif_en (legal range: 0 to 1)\",\n// \tverif_en );\n// end\n \n// if ( param_err_flg == 1) begin\n// $display(\n// \"%m :\\n Simulation aborted due to invalid parameter value(s)\");\n// $finish;\n// end\n\n// end // parameter_check \n\n\n// `ifndef DW_SUPPRESS_WARN\n// initial begin : verif_en_warning\n// $display(\"The parameter verif_en is set to 0 for this simulator.\\nOther values for verif_en are enabled only for VCS.\");\n// end // verif_en_warning\n// `endif\n\n//-----------------------------------------------------------------------------\n\n\n\nalways @ (INPUT) begin : IIIIO1Ol\n reg [input_width-1 : 0] I0lII01I [0 : num_inputs-1];\n reg [input_width-1 : 0] l10III00 [0 : num_inputs-1];\n reg [input_width-1 : 0] IIIO00Ol, lI0OII0O;\n integer I1I1O00I, O1OIIOII, IlI01lIO;\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII=O1OIIOII+1) begin\n for (IlI01lIO=0 ; IlI01lIO < input_width ; IlI01lIO=IlI01lIO+1) begin\n IIIO00Ol[IlI01lIO] = INPUT[O1OIIOII*input_width+IlI01lIO];\n end // for IlI01lIO\n I0lII01I[O1OIIOII] = IIIO00Ol;\n end // for O1OIIOII\n\n I1I1O00I = num_inputs;\n\n while (I1I1O00I > 2)\n begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I/3) ; O1OIIOII = O1OIIOII+1) begin\n l10III00[O1OIIOII*2] = I0lII01I[O1OIIOII*3] ^ I0lII01I[O1OIIOII*3+1] ^ I0lII01I[O1OIIOII*3+2];\n\n lI0OII0O = (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+1]) |\n (I0lII01I[O1OIIOII*3+1] & I0lII01I[O1OIIOII*3+2]) |\n (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+2]);\n\n l10III00[O1OIIOII*2+1] = lI0OII0O << 1;\n end\n if ((I1I1O00I % 3) > 0) begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I % 3) ; O1OIIOII = O1OIIOII + 1)\n l10III00[2 * (I1I1O00I/3) + O1OIIOII] = I0lII01I[3 * (I1I1O00I/3) + O1OIIOII];\n end\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII = O1OIIOII + 1)\n I0lII01I[O1OIIOII] = l10III00[O1OIIOII];\n I1I1O00I = I1I1O00I - (I1I1O00I/3);\n end\n OII0OOOI = I0lII01I[0];\n if (I1I1O00I > 1)\n O001l0I0 = I0lII01I[1];\n else\n O001l0I0 = {input_width{1'b0}};\nend // IIIIO1Ol\n\n\nassign OUT0 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : OII0OOOI;\nassign OUT1 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : O001l0I0;\n\n// synopsys translate_on\n\nendmodule\n // synopsys translate_off\n// `endif\n // synopsys translate_on\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/DW02_tree.sv", "//-----------------------------------------------------------------------------------\n//\n// ABSTRACT: Wallace Tree Summer with Carry Save output\n//\n//------------------------------------------------------------------------------\n//\n\n // synopsys translate_off\n// `ifdef VCS\n// `include \"DW02_tree.v\"\n// `else\n // synopsys translate_on\n\nmodule DW02_tree( INPUT, OUT0, OUT1 );\n\n// parameters\nparameter integer num_inputs = 8;\nparameter integer input_width = 8;\nparameter integer verif_en = 1;\n\n//-----------------------------------------------------------------------------\n// ports\ninput [num_inputs*input_width-1 : 0]\tINPUT;\noutput [input_width-1:0]\t\tOUT0, OUT1;\n\n//-----------------------------------------------------------------------------\n// synopsys translate_off\nreg [input_width-1:0]\t\tOII0OOOI, O001l0I0;\n\n//-----------------------------------------------------------------------------\n \n \n// initial begin : parameter_check\n// integer param_err_flg;\n\n// param_err_flg = 0;\n \n \n// if (num_inputs < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter num_inputs (lower bound: 1)\",\n// \tnum_inputs );\n// end\n \n// if (input_width < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter input_width (lower bound: 1)\",\n// \tinput_width );\n// end\n \n// if ( (verif_en < 0) || (verif_en > 1) ) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter verif_en (legal range: 0 to 1)\",\n// \tverif_en );\n// end\n \n// if ( param_err_flg == 1) begin\n// $display(\n// \"%m :\\n Simulation aborted due to invalid parameter value(s)\");\n// $finish;\n// end\n\n// end // parameter_check \n\n\n// `ifndef DW_SUPPRESS_WARN\n// initial begin : verif_en_warning\n// $display(\"The parameter verif_en is set to 0 for this simulator.\\nOther values for verif_en are enabled only for VCS.\");\n// end // verif_en_warning\n// `endif\n\n//-----------------------------------------------------------------------------\n\n\n\nalways @ (INPUT) begin : IIIIO1Ol\n reg [input_width-1 : 0] I0lII01I [0 : num_inputs-1];\n reg [input_width-1 : 0] l10III00 [0 : num_inputs-1];\n reg [input_width-1 : 0] IIIO00Ol, lI0OII0O;\n integer I1I1O00I, O1OIIOII, IlI01lIO;\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII=O1OIIOII+1) begin\n for (IlI01lIO=0 ; IlI01lIO < input_width ; IlI01lIO=IlI01lIO+1) begin\n IIIO00Ol[IlI01lIO] = INPUT[O1OIIOII*input_width+IlI01lIO];\n end // for IlI01lIO\n I0lII01I[O1OIIOII] = IIIO00Ol;\n end // for O1OIIOII\n\n I1I1O00I = num_inputs;\n\n while (I1I1O00I > 2)\n begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I/3) ; O1OIIOII = O1OIIOII+1) begin\n l10III00[O1OIIOII*2] = I0lII01I[O1OIIOII*3] ^ I0lII01I[O1OIIOII*3+1] ^ I0lII01I[O1OIIOII*3+2];\n\n lI0OII0O = (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+1]) |\n (I0lII01I[O1OIIOII*3+1] & I0lII01I[O1OIIOII*3+2]) |\n (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+2]);\n\n l10III00[O1OIIOII*2+1] = lI0OII0O << 1;\n end\n if ((I1I1O00I % 3) > 0) begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I % 3) ; O1OIIOII = O1OIIOII + 1)\n l10III00[2 * (I1I1O00I/3) + O1OIIOII] = I0lII01I[3 * (I1I1O00I/3) + O1OIIOII];\n end\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII = O1OIIOII + 1)\n I0lII01I[O1OIIOII] = l10III00[O1OIIOII];\n I1I1O00I = I1I1O00I - (I1I1O00I/3);\n end\n OII0OOOI = I0lII01I[0];\n if (I1I1O00I > 1)\n O001l0I0 = I0lII01I[1];\n else\n O001l0I0 = {input_width{1'b0}};\nend // IIIIO1Ol\n\n\nassign OUT0 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : OII0OOOI;\nassign OUT1 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : O001l0I0;\n\n// synopsys translate_on\n\nendmodule\n // synopsys translate_off\n// `endif\n // synopsys translate_on\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/booth_partial_product_generator_pp1.v", "module booth_partial_product_generator_pp1(\n input wire [1:0] operand_slice_a, \n input wire [7:0] operand_b, \n input wire [8:0] operand_b_neg, \n output wire [9:0] pp_out \n );\n \n wire [8:0] pp_source;\n wire not_code0;\n //----------------------------------------------------\n //| pp | flag_2x | flag_s1 | flag_s2 |\n //----------------------------------------------------\n //| operand_b | 0 | 0 | 1 |\n //| -operand_b | 0 | 1 | 0 |\n //| 2operand_b | 1 | 0 | 1 | \n //| -2operand_b | 1 | 1 | 0 |\n //| 0 | x | 0 | 0 | \n //----------------------------------------------------\n \n //----------------------------------------------------\n //operand_slice_a[1] operand_slice_a[0] operand_slice_a[-1] | pp \n //----------------------------------------------------\n // 0 0 0 | 0 \n // 0 1 0 | operand_b \n // 1 0 0 | 2operand_b \n // 1 1 0 | -operand_b \n //----------------------------------------------------\n \n wire flag_2x;\n wire flag_s1;\n wire flag_s2; \n assign not_code0 = ~operand_slice_a[0]; \n assign flag_2x = not_code0; \n assign flag_s1 = operand_slice_a[1]; // 取反\n assign flag_s2 = ~(operand_slice_a[1] | not_code0); // A\n wire flag_not_2x = operand_slice_a[0];\n assign pp_source = (({{operand_b[7]}, operand_b} & {9{flag_s2}}) | (operand_b_neg & {9{flag_s1}})); // A or ~A or 0\n assign pp_out[0] = (!flag_2x & pp_source[0]);// x2 (<<1) pp_out[0]=0\n assign pp_out[8:1] = (({8{flag_2x}} & pp_source[7:0]) | ({8{flag_not_2x}} & pp_source[8:1]));\n assign pp_out[9] = pp_source[8];\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/booth_partial_product_generator_pp1.v", "module booth_partial_product_generator_pp1(\n input wire [1:0] operand_slice_a, \n input wire [7:0] operand_b, \n input wire [8:0] operand_b_neg, \n output wire [9:0] pp_out \n );\n \n wire [8:0] pp_source;\n wire not_code0;\n //----------------------------------------------------\n //| pp | flag_2x | flag_s1 | flag_s2 |\n //----------------------------------------------------\n //| operand_b | 0 | 0 | 1 |\n //| -operand_b | 0 | 1 | 0 |\n //| 2operand_b | 1 | 0 | 1 | \n //| -2operand_b | 1 | 1 | 0 |\n //| 0 | x | 0 | 0 | \n //----------------------------------------------------\n \n //----------------------------------------------------\n //operand_slice_a[1] operand_slice_a[0] operand_slice_a[-1] | pp \n //----------------------------------------------------\n // 0 0 0 | 0 \n // 0 1 0 | operand_b \n // 1 0 0 | 2operand_b \n // 1 1 0 | -operand_b \n //----------------------------------------------------\n \n wire flag_2x;\n wire flag_s1;\n wire flag_s2; \n assign not_code0 = ~operand_slice_a[0]; \n assign flag_2x = not_code0; \n assign flag_s1 = operand_slice_a[1]; // 取反\n assign flag_s2 = ~(operand_slice_a[1] | not_code0); // A\n wire flag_not_2x = operand_slice_a[0];\n assign pp_source = (({{operand_b[7]}, operand_b} & {9{flag_s2}}) | (operand_b_neg & {9{flag_s1}})); // A or ~A or 0\n assign pp_out[0] = (!flag_2x & pp_source[0]);// x2 (<<1) pp_out[0]=0\n assign pp_out[8:1] = (({8{flag_2x}} & pp_source[7:0]) | ({8{flag_not_2x}} & pp_source[8:1]));\n assign pp_out[9] = pp_source[8];\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/booth_partial_product_generator_pp1.v", "module booth_partial_product_generator_pp1(\n input wire [1:0] operand_slice_a, \n input wire [7:0] operand_b, \n input wire [8:0] operand_b_neg, \n output wire [9:0] pp_out \n );\n \n wire [8:0] pp_source;\n wire not_code0;\n //----------------------------------------------------\n //| pp | flag_2x | flag_s1 | flag_s2 |\n //----------------------------------------------------\n //| operand_b | 0 | 0 | 1 |\n //| -operand_b | 0 | 1 | 0 |\n //| 2operand_b | 1 | 0 | 1 | \n //| -2operand_b | 1 | 1 | 0 |\n //| 0 | x | 0 | 0 | \n //----------------------------------------------------\n \n //----------------------------------------------------\n //operand_slice_a[1] operand_slice_a[0] operand_slice_a[-1] | pp \n //----------------------------------------------------\n // 0 0 0 | 0 \n // 0 1 0 | operand_b \n // 1 0 0 | 2operand_b \n // 1 1 0 | -operand_b \n //----------------------------------------------------\n \n wire flag_2x;\n wire flag_s1;\n wire flag_s2; \n assign not_code0 = ~operand_slice_a[0]; \n assign flag_2x = not_code0; \n assign flag_s1 = operand_slice_a[1]; // 取反\n assign flag_s2 = ~(operand_slice_a[1] | not_code0); // A\n wire flag_not_2x = operand_slice_a[0];\n assign pp_source = (({{operand_b[7]}, operand_b} & {9{flag_s2}}) | (operand_b_neg & {9{flag_s1}})); // A or ~A or 0\n assign pp_out[0] = (!flag_2x & pp_source[0]);// x2 (<<1) pp_out[0]=0\n assign pp_out[8:1] = (({8{flag_2x}} & pp_source[7:0]) | ({8{flag_not_2x}} & pp_source[8:1]));\n assign pp_out[9] = pp_source[8];\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/booth_partial_product_generator.v", "module booth_partial_product_generator(\n input wire [2:0] operand_slice_a, \n input wire [7:0] operand_b, \n input wire [8:0] operand_b_neg, \n output wire [9:0] pp_out \n );\n \n wire [8:0] pp_source ;\n //----------------------------------------------------\n //| pp | flag_2x | flag_s1 | flag_s2 |\n //----------------------------------------------------\n //| operand_b | 0 | 0 | 1 |\n //| -operand_b | 0 | 1 | 0 |\n //| 2operand_b | 1 | 0 | 1 | \n //| -2operand_b | 1 | 1 | 0 |\n //| 0 | x | 0 | 0 | \n //----------------------------------------------------\n \n //----------------------------------------------------\n //operand_slice_a[1] operand_slice_a[0] operand_slice_a[-1] | pp \n //----------------------------------------------------\n // 0 0 0 | 0 \n // 0 0 1 | operand_b \n // 0 1 0 | operand_b \n // 0 1 1 | 2operand_b \n // 1 0 0 | -2operand_b \n // 1 0 1 | -operand_b \n // 1 1 0 | -operand_b \n // 1 1 1 | 0 \n //----------------------------------------------------\n \n wire not_c2 ; \n wire c1_and_c0 ; \n wire c1_nor_c0 ; \n wire nor_o2 ; \n \n wire flag_2x ;\n wire flag_s1 ;\n wire flag_s2 ;\n \n assign not_c2 = ~operand_slice_a[2] ;\n assign c1_and_c0 = operand_slice_a[1] & operand_slice_a[0] ;\n assign c1_nor_c0 = ~(operand_slice_a[1] | operand_slice_a[0]) ;\n assign nor_o2 = ~(c1_and_c0 | c1_nor_c0) ;\n \n assign flag_2x = ~nor_o2 ;\n assign flag_s1 = ~(not_c2 | c1_and_c0) ;\n assign flag_s2 = ~(operand_slice_a[2] | c1_nor_c0) ;\n \n wire flag_not_2x = nor_o2; \n assign pp_source = (({{operand_b[7]}, operand_b} & {9{flag_s2}}) | (operand_b_neg & {9{flag_s1}}));\n assign pp_out[0] = (!flag_2x & pp_source[0]);\n assign pp_out[8:1] = (({8{flag_2x}} & pp_source[7:0]) | ({8{flag_not_2x}} & pp_source[8:1]));\n assign pp_out[9] = pp_source[8];\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/booth_partial_product_generator.v", "module booth_partial_product_generator(\n input wire [2:0] operand_slice_a, \n input wire [7:0] operand_b, \n input wire [8:0] operand_b_neg, \n output wire [9:0] pp_out \n );\n \n wire [8:0] pp_source ;\n //----------------------------------------------------\n //| pp | flag_2x | flag_s1 | flag_s2 |\n //----------------------------------------------------\n //| operand_b | 0 | 0 | 1 |\n //| -operand_b | 0 | 1 | 0 |\n //| 2operand_b | 1 | 0 | 1 | \n //| -2operand_b | 1 | 1 | 0 |\n //| 0 | x | 0 | 0 | \n //----------------------------------------------------\n \n //----------------------------------------------------\n //operand_slice_a[1] operand_slice_a[0] operand_slice_a[-1] | pp \n //----------------------------------------------------\n // 0 0 0 | 0 \n // 0 0 1 | operand_b \n // 0 1 0 | operand_b \n // 0 1 1 | 2operand_b \n // 1 0 0 | -2operand_b \n // 1 0 1 | -operand_b \n // 1 1 0 | -operand_b \n // 1 1 1 | 0 \n //----------------------------------------------------\n \n wire not_c2 ; \n wire c1_and_c0 ; \n wire c1_nor_c0 ; \n wire nor_o2 ; \n \n wire flag_2x ;\n wire flag_s1 ;\n wire flag_s2 ;\n \n assign not_c2 = ~operand_slice_a[2] ;\n assign c1_and_c0 = operand_slice_a[1] & operand_slice_a[0] ;\n assign c1_nor_c0 = ~(operand_slice_a[1] | operand_slice_a[0]) ;\n assign nor_o2 = ~(c1_and_c0 | c1_nor_c0) ;\n \n assign flag_2x = ~nor_o2 ;\n assign flag_s1 = ~(not_c2 | c1_and_c0) ;\n assign flag_s2 = ~(operand_slice_a[2] | c1_nor_c0) ;\n \n wire flag_not_2x = nor_o2; \n assign pp_source = (({{operand_b[7]}, operand_b} & {9{flag_s2}}) | (operand_b_neg & {9{flag_s1}}));\n assign pp_out[0] = (!flag_2x & pp_source[0]);\n assign pp_out[8:1] = (({8{flag_2x}} & pp_source[7:0]) | ({8{flag_not_2x}} & pp_source[8:1]));\n assign pp_out[9] = pp_source[8];\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/booth_partial_product_generator.v", "module booth_partial_product_generator(\n input wire [2:0] operand_slice_a, \n input wire [7:0] operand_b, \n input wire [8:0] operand_b_neg, \n output wire [9:0] pp_out \n );\n \n wire [8:0] pp_source ;\n //----------------------------------------------------\n //| pp | flag_2x | flag_s1 | flag_s2 |\n //----------------------------------------------------\n //| operand_b | 0 | 0 | 1 |\n //| -operand_b | 0 | 1 | 0 |\n //| 2operand_b | 1 | 0 | 1 | \n //| -2operand_b | 1 | 1 | 0 |\n //| 0 | x | 0 | 0 | \n //----------------------------------------------------\n \n //----------------------------------------------------\n //operand_slice_a[1] operand_slice_a[0] operand_slice_a[-1] | pp \n //----------------------------------------------------\n // 0 0 0 | 0 \n // 0 0 1 | operand_b \n // 0 1 0 | operand_b \n // 0 1 1 | 2operand_b \n // 1 0 0 | -2operand_b \n // 1 0 1 | -operand_b \n // 1 1 0 | -operand_b \n // 1 1 1 | 0 \n //----------------------------------------------------\n \n wire not_c2 ; \n wire c1_and_c0 ; \n wire c1_nor_c0 ; \n wire nor_o2 ; \n \n wire flag_2x ;\n wire flag_s1 ;\n wire flag_s2 ;\n \n assign not_c2 = ~operand_slice_a[2] ;\n assign c1_and_c0 = operand_slice_a[1] & operand_slice_a[0] ;\n assign c1_nor_c0 = ~(operand_slice_a[1] | operand_slice_a[0]) ;\n assign nor_o2 = ~(c1_and_c0 | c1_nor_c0) ;\n \n assign flag_2x = ~nor_o2 ;\n assign flag_s1 = ~(not_c2 | c1_and_c0) ;\n assign flag_s2 = ~(operand_slice_a[2] | c1_nor_c0) ;\n \n wire flag_not_2x = nor_o2; \n assign pp_source = (({{operand_b[7]}, operand_b} & {9{flag_s2}}) | (operand_b_neg & {9{flag_s1}}));\n assign pp_out[0] = (!flag_2x & pp_source[0]);\n assign pp_out[8:1] = (({8{flag_2x}} & pp_source[7:0]) | ({8{flag_not_2x}} & pp_source[8:1]));\n assign pp_out[9] = pp_source[8];\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/booth_partial_product_generator.v", "module booth_partial_product_generator(\n input wire [2:0] operand_slice_a, \n input wire [7:0] operand_b, \n input wire [8:0] operand_b_neg, \n output wire [9:0] pp_out \n );\n \n wire [8:0] pp_source ;\n //----------------------------------------------------\n //| pp | flag_2x | flag_s1 | flag_s2 |\n //----------------------------------------------------\n //| operand_b | 0 | 0 | 1 |\n //| -operand_b | 0 | 1 | 0 |\n //| 2operand_b | 1 | 0 | 1 | \n //| -2operand_b | 1 | 1 | 0 |\n //| 0 | x | 0 | 0 | \n //----------------------------------------------------\n wire not_c2 ; \n wire c1_and_c0 ; \n wire c1_nor_c0 ; \n wire nor_o2 ; \n \n wire flag_2x ;\n wire flag_s1 ;\n wire flag_s2 ;\n \n assign not_c2 = ~operand_slice_a[2] ;\n assign c1_and_c0 = operand_slice_a[1] & operand_slice_a[0] ;\n assign c1_nor_c0 = ~(operand_slice_a[1] | operand_slice_a[0]) ;\n assign nor_o2 = ~(c1_and_c0 | c1_nor_c0) ;\n \n assign flag_2x = ~nor_o2 ;\n assign flag_s1 = ~(not_c2 | c1_and_c0) ;\n assign flag_s2 = ~(operand_slice_a[2] | c1_nor_c0) ;\n \n wire flag_not_2x = nor_o2; \n \n assign pp_source = (({{operand_b[7]}, operand_b} & {9{flag_s2}}) | (operand_b_neg & {9{flag_s1}}));\n assign pp_out[0] = (!flag_2x & pp_source[0]);\n assign pp_out[8:1] = (({8{flag_2x}} & pp_source[7:0]) | ({8{flag_not_2x}} & pp_source[8:1]));\n assign pp_out[9] = pp_source[8];\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT3_OPT4C/pe/get_negedge.sv", "module get_negedge(\n input clk,\n input signal,\n output negedge_signal\n );\n\nreg save;\n\nalways @(posedge clk) begin\n save <= signal;\nend\n\nassign negedge_signal = ~signal & save;\n\nendmodule\n\n// get_negedge get_hit(\n// .clk(clk),\n// .signal(cache_hit),\n// .negedge_signal(negedge_cache_hit)\n// );"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/booth_partial_product_generator_pp1.v", "module booth_partial_product_generator_pp1(\n input wire [1:0] operand_slice_a, \n input wire [7:0] operand_b, \n input wire [8:0] operand_b_neg, \n output wire [9:0] pp_out \n );\n \n wire [8:0] pp_source;\n wire not_code0;\n //----------------------------------------------------\n //| pp | flag_2x | flag_s1 | flag_s2 |\n //----------------------------------------------------\n //| operand_b | 0 | 0 | 1 |\n //| -operand_b | 0 | 1 | 0 |\n //| 2operand_b | 1 | 0 | 1 | \n //| -2operand_b | 1 | 1 | 0 |\n //| 0 | x | 0 | 0 | \n //----------------------------------------------------\n wire flag_2x;\n wire flag_s1;\n wire flag_s2; \n assign not_code0 = ~operand_slice_a[0]; \n assign flag_2x = not_code0; \n assign flag_s1 = operand_slice_a[1]; \n assign flag_s2 = ~(operand_slice_a[1] | not_code0); \n wire flag_not_2x = operand_slice_a[0];\n assign pp_source = (({{operand_b[7]}, operand_b} & {9{flag_s2}}) | (operand_b_neg & {9{flag_s1}}));\n assign pp_out[0] = (!flag_2x & pp_source[0]);\n assign pp_out[8:1] = (({8{flag_2x}} & pp_source[7:0]) | ({8{flag_not_2x}} & pp_source[8:1]));\n assign pp_out[9] = pp_source[8];\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/inv_conveter_8.v", "// 取反 加1 （-1*A、-2*A 都要进行取反加1）\nmodule inv_converter_8(\n input wire [7:0] data_i ,\n output wire[8:0] inv_o \n );\n \n wire [5:0] wire_cout ; \n wire not_o ; \n\n assign inv_o[0] = data_i[0];\n \n inv_unit inv_unit_bit1(\n .a (data_i[1] ),\n .b (data_i[0] ),\n .xor_o (inv_o[1] ), \n .or_o (wire_cout[0] ) \n );\n \n genvar i;\n generate \n for(i=2;i<=5;i=i+1) begin\n inv_unit inv_unit_inst(\n .a (data_i[i] ),\n .b (wire_cout[i-2] ),\n .xor_o (inv_o[i] ), \n .or_o (wire_cout[i-1] ) \n );\n end\n endgenerate\n \n inv_unit_nor_out inv_unit_nor_out_inst_6(\n .a (data_i[6] ),\n .b (wire_cout[4] ),\n .xor_o (inv_o[6] ), \n .nor_o (wire_cout[5] ) \n );\n \n inv_unit_nor_out inv_unit_nor_out_inst_7(\n .a (data_i[7] ),\n .b (not_o ), \n .xor_o (inv_o[7] ), \n .nor_o ( ) \n );\n \n \n\n assign not_o = ~wire_cout[5] ;\n \n\n assign inv_o[8] = ~(wire_cout[5] | data_i[7]);\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/inv_conveter_8.v", "// 取反 加1 （-1*A、-2*A 都要进行取反加1）\nmodule inv_converter_8(\n input wire [7:0] data_i ,\n output wire[8:0] inv_o \n );\n \n wire [5:0] wire_cout ; \n wire not_o ; \n\n assign inv_o[0] = data_i[0];\n \n inv_unit inv_unit_bit1(\n .a (data_i[1] ),\n .b (data_i[0] ),\n .xor_o (inv_o[1] ), \n .or_o (wire_cout[0] ) \n );\n \n genvar i;\n generate \n for(i=2;i<=5;i=i+1) begin\n inv_unit inv_unit_inst(\n .a (data_i[i] ),\n .b (wire_cout[i-2] ),\n .xor_o (inv_o[i] ), \n .or_o (wire_cout[i-1] ) \n );\n end\n endgenerate\n \n inv_unit_nor_out inv_unit_nor_out_inst_6(\n .a (data_i[6] ),\n .b (wire_cout[4] ),\n .xor_o (inv_o[6] ), \n .nor_o (wire_cout[5] ) \n );\n \n inv_unit_nor_out inv_unit_nor_out_inst_7(\n .a (data_i[7] ),\n .b (not_o ), \n .xor_o (inv_o[7] ), \n .nor_o ( ) \n );\n \n \n\n assign not_o = ~wire_cout[5] ;\n \n\n assign inv_o[8] = ~(wire_cout[5] | data_i[7]);\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/inv_conveter_8.v", "// 取反 加1 （-1*A、-2*A 都要进行取反加1）\nmodule inv_converter_8(\n input wire [7:0] data_i ,\n output wire[8:0] inv_o \n );\n \n wire [5:0] wire_cout ; \n wire not_o ; \n\n assign inv_o[0] = data_i[0];\n \n inv_unit inv_unit_bit1(\n .a (data_i[1] ),\n .b (data_i[0] ),\n .xor_o (inv_o[1] ), \n .or_o (wire_cout[0] ) \n );\n \n genvar i;\n generate \n for(i=2;i<=5;i=i+1) begin\n inv_unit inv_unit_inst(\n .a (data_i[i] ),\n .b (wire_cout[i-2] ),\n .xor_o (inv_o[i] ), \n .or_o (wire_cout[i-1] ) \n );\n end\n endgenerate\n \n inv_unit_nor_out inv_unit_nor_out_inst_6(\n .a (data_i[6] ),\n .b (wire_cout[4] ),\n .xor_o (inv_o[6] ), \n .nor_o (wire_cout[5] ) \n );\n \n inv_unit_nor_out inv_unit_nor_out_inst_7(\n .a (data_i[7] ),\n .b (not_o ), \n .xor_o (inv_o[7] ), \n .nor_o ( ) \n );\n \n \n\n assign not_o = ~wire_cout[5] ;\n \n\n assign inv_o[8] = ~(wire_cout[5] | data_i[7]);\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/inv_conveter_8.v", "module inv_converter_8(\n input wire [7:0] data_i ,\n output wire[8:0] inv_o \n );\n \n wire [5:0] wire_cout ; \n wire not_o ; \n\n assign inv_o[0] = data_i[0];\n \n inv_unit inv_unit_bit1(\n .a (data_i[1] ),\n .b (data_i[0] ),\n .xor_o (inv_o[1] ), \n .or_o (wire_cout[0] ) \n );\n \n genvar i;\n generate \n for(i=2;i<=5;i=i+1) begin\n inv_unit inv_unit_inst(\n .a (data_i[i] ),\n .b (wire_cout[i-2] ),\n .xor_o (inv_o[i] ), \n .or_o (wire_cout[i-1] ) \n );\n end\n endgenerate\n \n inv_unit_nor_out inv_unit_nor_out_inst_6(\n .a (data_i[6] ),\n .b (wire_cout[4] ),\n .xor_o (inv_o[6] ), \n .nor_o (wire_cout[5] ) \n );\n \n inv_unit_nor_out inv_unit_nor_out_inst_7(\n .a (data_i[7] ),\n .b (not_o ), \n .xor_o (inv_o[7] ), \n .nor_o ( ) \n );\n \n \n\n assign not_o = ~wire_cout[5] ;\n \n\n assign inv_o[8] = ~(wire_cout[5] | data_i[7]);\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/inv_unit_nor_out.v", "module inv_unit_nor_out(\n input wire a ,\n input wire b ,\n \n output wire xor_o , \n output wire nor_o \n );\n \n\n wire a_AND_b ; \n wire a_NOR_b ; \n \n \n assign a_AND_b = a & b;\n \n \n assign a_NOR_b = ~(a | b);\n \n\n assign xor_o = ~(a_AND_b | a_NOR_b);\n assign nor_o = a_NOR_b;\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/inv_unit_nor_out.v", "module inv_unit_nor_out(\n input wire a ,\n input wire b ,\n \n output wire xor_o , \n output wire nor_o \n );\n \n\n wire a_AND_b ; \n wire a_NOR_b ; \n \n \n assign a_AND_b = a & b;\n \n \n assign a_NOR_b = ~(a | b);\n \n\n assign xor_o = ~(a_AND_b | a_NOR_b);\n assign nor_o = a_NOR_b;\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/inv_unit_nor_out.v", "module inv_unit_nor_out(\n input wire a ,\n input wire b ,\n \n output wire xor_o , \n output wire nor_o \n );\n \n\n wire a_AND_b ; \n wire a_NOR_b ; \n \n \n assign a_AND_b = a & b;\n \n \n assign a_NOR_b = ~(a | b);\n \n\n assign xor_o = ~(a_AND_b | a_NOR_b);\n assign nor_o = a_NOR_b;\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/inv_unit_nor_out.v", "module inv_unit_nor_out(\n input wire a ,\n input wire b ,\n \n output wire xor_o , \n output wire nor_o \n );\n \n\n wire a_AND_b ; \n wire a_NOR_b ; \n \n \n assign a_AND_b = a & b;\n \n \n assign a_NOR_b = ~(a | b);\n \n\n assign xor_o = ~(a_AND_b | a_NOR_b);\n assign nor_o = a_NOR_b;\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/inv_unit.v", "module inv_unit(\n input wire a ,\n input wire b ,\n output wire xor_o , \n output wire or_o \n );\n \n wire aORb ; \n wire aNANDb ; \n \n assign aORb = a | b;\n assign aNANDb = ~(a & b);\n assign xor_o = (aORb & aNANDb);\n assign or_o = aORb;\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/inv_unit.v", "module inv_unit(\n input wire a ,\n input wire b ,\n output wire xor_o , \n output wire or_o \n );\n \n wire aORb ; \n wire aNANDb ; \n \n assign aORb = a | b;\n assign aNANDb = ~(a & b);\n assign xor_o = (aORb & aNANDb);\n assign or_o = aORb;\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/inv_unit.v", "module inv_unit(\n input wire a ,\n input wire b ,\n output wire xor_o , \n output wire or_o \n );\n \n wire aORb ; \n wire aNANDb ; \n \n assign aORb = a | b;\n assign aNANDb = ~(a & b);\n assign xor_o = (aORb & aNANDb);\n assign or_o = aORb;\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/inv_unit.v", "module inv_unit(\n input wire a ,\n input wire b ,\n output wire xor_o , \n output wire or_o \n );\n \n wire aORb ; \n wire aNANDb ; \n \n assign aORb = a | b;\n assign aNANDb = ~(a & b);\n assign xor_o = (aORb & aNANDb);\n assign or_o = aORb;\n \nendmodule"]], "task_instance_info": {"created_time": "2025-08-21 04:17:40", "created_task_model": "DeepSeek-R1", "class_skeleton": "module mac #\n(\n parameter WIDTH = 8,\n parameter ACC_WIDTH = 32\n)\n(\n input wire rst_n,\n input wire clk,\n input wire signed [WIDTH-1 :0] a,\n input wire signed [WIDTH-1 :0] b,\n output reg signed [ACC_WIDTH-1 :0] result\n) ; endmodule", "code_description": "This code segment functions to: Implement a configurable multiply-accumulate operation with parameterized input precision and accumulator width, synchronously processing signed numerical inputs while maintaining state through reset management and sequential accumulation cycles."}, "inference_content": {"inference_model": "DeepSeek-R1", "inference_result": "```verilog\n[TASK_BEGIN]\n wire signed [2*WIDTH-1:0] product;\n assign product = a * b;\n\n always @(posedge clk or negedge rst_n) begin\n if (!rst_n) begin\n result <= 0;\n end else begin\n result <= result + product;\n end\n end\n[TASK_END]\n```", "inference_time": "2025-08-21 04-18-42"}, "editdistance_info": {"edit_distance": 20.9091, "calculate_time": "2025-08-21 04:18:42", "true_code_clean": "module mac #\n(\n parameter WIDTH = 8,\n parameter ACC_WIDTH = 32\n)\n(\n input wire rst_n,\n input wire clk,\n input wire signed [WIDTH-1 :0] a,\n input wire signed [WIDTH-1 :0] b,\n output reg signed [ACC_WIDTH-1 :0] result\n);\nwire signed [15:0] result_p;\nreg signed [7:0] operand_a;\nreg signed [7:0] operand_b;\nassign result_p = $signed(operand_a) * $signed(operand_b) ;\nalways @(posedge clk) begin\n operand_a <= a;\n operand_b <= b;\nend\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n result <= 0;\n end\n else begin\n result <= result + $signed(result_p);\n end\nend\nendmodule", "predict_code_clean": "wire signed [2*WIDTH-1:0] product;\n assign product = a * b;\n always @(posedge clk or negedge rst_n) begin\n if (!rst_n) begin\n result <= 0;\n end else begin\n result <= result + product;\n end\n end"}} +{"repo_name": "High-Performance-Tensor-Processing-Engines", "file_name": "/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/pe.v", "inference_info": {"prefix_code": "", "suffix_code": "\n", "middle_code": "module PE #\n(\n parameter WIDTH = 8,\n parameter ACC_WIDTH = 32\n)\n(\n input wire rst_n,\n input wire clk,\n input wire signed [WIDTH-1 :0] a,\n input wire signed [WIDTH-1 :0] b,\n input wire clc, \n output reg signed [WIDTH-1 :0] row,\n output reg signed [WIDTH-1 :0] col,\n output signed [2*ACC_WIDTH-1 :0] result\n);\nwire [ACC_WIDTH-1:0] acc_sum;\nwire [ACC_WIDTH-1:0] acc_carry;\nopt1_mac #(\n .ACC_WIDTH(ACC_WIDTH),\n .INPUT_PIP(0)\n) opt1_mac_test (\n .clk(clk),\n .rst_n(rst_n),\n .operand_a_in(a), \n .operand_b_in(b), \n .clc(clc), \n .acc_sum(acc_sum),\n .acc_carry(acc_carry)\n);\nassign result = {acc_sum, acc_carry};\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n row <= 0;\n col <= 0;\n end\n else begin\n row <= a;\n col <= b;\n end\nend\nendmodule", "code_description": null, "fill_type": "CLASS_TYPE", "language_type": "verilog", "sub_task_type": null}, "context_code": [["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/PE.v", "// b = w * a\nmodule PE #\n(\n parameter WIDTH = 8,\n parameter ACC_WIDTH = 24\n)\n(\n input wire rst_n ,\n input wire clk ,\n input wire weight_wen ,\n input [WIDTH-1 :0] weight_din ,\n input wire signed [WIDTH-1 :0] a ,\n input wire signed [2*ACC_WIDTH-1 :0] partial_result , \n\n output reg signed [WIDTH-1 :0] col ,\n output reg signed [2*ACC_WIDTH-1 :0] row \n);\n\n\nreg signed [WIDTH-1 :0] weight;\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n weight <= 0;\n end\n else begin\n if(weight_wen) begin\n weight <= weight_din; \n end\n else begin\n weight <= weight;\n end\n end\nend\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n col <= 0;\n end\n else begin\n if(weight_wen) begin\n col <= weight_din; \n end\n else begin\n col <= a;\n end\n end\nend\n\nwire [ACC_WIDTH-1:0] acc_sum;\nwire [ACC_WIDTH-1:0] acc_carry;\nalways @(*) begin\n if(!rst_n) begin\n row <= 0;\n end\n else begin\n row <= {acc_sum, acc_carry}; // partial_result + weight * a;\n end\nend\nopt1_mac #(\n .ACC_WIDTH(ACC_WIDTH),\n .INPUT_PIP(0)\n) opt1_mac_test (\n .clk(clk),\n .rst_n(rst_n),\n .operand_a_in(a), \n .operand_b_in(weight), \n .partial_result(partial_result),\n .acc_sum(acc_sum),\n .acc_carry(acc_carry)\n);\n\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/PE.v", "`timescale 1ns / 1ps\n\n// b = w * a\nmodule PE #\n(\n parameter WIDTH = 8,\n parameter ACC_WIDTH = 24\n)\n(\n input wire rst_n,\n input wire clk,\n input wire signed [WIDTH-1 :0] i_z_a,\n input wire signed [WIDTH-1 :0] i_x_b,\n input wire signed [2*ACC_WIDTH-1 :0] i_y_p,\n\n output reg signed [WIDTH-1 :0] o_z_a,\n output reg signed [WIDTH-1 :0] o_x_b,\n output reg signed [2*ACC_WIDTH-1 :0] o_y_p\n);\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n o_z_a <= 0;\n o_x_b <= 0;\n end\n else begin\n o_z_a <= i_z_a; \n o_x_b <= i_x_b; \n end\nend\n\nwire [ACC_WIDTH-1:0] acc_sum;\nwire [ACC_WIDTH-1:0] acc_carry;\nalways @(*) begin\n if(!rst_n) begin\n o_y_p = 0;\n end\n else begin\n o_y_p = {acc_sum, acc_carry}; // partial_result + weight * a;\n end\nend\nopt1_mac #(\n .ACC_WIDTH(ACC_WIDTH),\n .INPUT_PIP(0)\n) opt1_mac_test (\n .clk(clk),\n .rst_n(rst_n),\n .operand_a_in(i_z_a), \n .operand_b_in(i_x_b), \n .partial_result(i_y_p),\n .acc_sum(acc_sum),\n .acc_carry(acc_carry)\n);\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/opt1_mac.v", "module opt1_mac #(\n parameter ACC_WIDTH = 32,\n parameter INPUT_PIP = 1\n)(\n input wire clk,\n input wire rst_n,\n input wire [7:0] operand_a_in, \n input wire [7:0] operand_b_in, \n input wire clc, // clean_result_cache\n output reg [ACC_WIDTH-1:0] acc_sum,\n output reg [ACC_WIDTH-1:0] acc_carry\n);\n\nreg [7:0] operand_a;\nreg [7:0] operand_b;\n\nwire signed [9:0] pp1;\nwire signed [9:0] pp2;\nwire signed [9:0] pp3;\nwire signed [9:0] pp4;\nwire [6*ACC_WIDTH-1 : 0] mul_reduce_csa_input;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp1;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp2;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp3;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp4;\nwire signed [ACC_WIDTH-1:0] reduce_acc_sum;\nwire signed [ACC_WIDTH-1:0] reduce_acc_carry;\n\nassign sign_extend_pp4 = $signed({pp4,6'b0});\nassign sign_extend_pp3 = $signed({pp3,4'b0});\nassign sign_extend_pp2 = $signed({pp2,2'b0});\nassign sign_extend_pp1 = $signed(pp1);\n\nassign mul_reduce_csa_input = {sign_extend_pp4,sign_extend_pp3,sign_extend_pp2,sign_extend_pp1,acc_carry,acc_sum};\n\nbooth_pp_gen booth_pp_gen_inst(\n .operand_a(operand_a), \n .operand_b(operand_b), \n .pp1(pp1),\n .pp2(pp2),\n .pp3(pp3),\n .pp4(pp4)\n);\n\nDW02_tree #(6, ACC_WIDTH, 1)\n U2 ( .INPUT(mul_reduce_csa_input), .OUT0(reduce_acc_sum), .OUT1(reduce_acc_carry) );\n\nalways @(posedge clk) begin\n if (!rst_n) begin\n acc_sum <= 0;\n acc_carry <= 0;\n end\n else begin\n if(clc) begin\n acc_sum <= 0;\n acc_carry <= 0;\n end\n else begin\n acc_sum <= reduce_acc_sum;\n acc_carry <= reduce_acc_carry;\n end\n end\nend\n\ngenerate\n if(INPUT_PIP == 1) begin\n always @(posedge clk) begin\n operand_a <= operand_a_in;\n operand_b <= operand_b_in;\n end\n end\n else begin\n always @(*) begin\n operand_a = operand_a_in;\n operand_b = operand_b_in;\n end\n end\nendgenerate\n\n// dff_async #(\n// .WIDTH(ACC_WIDTH)) acc_sum_reg (\n// .clk(clk),\n// .rst_n(rst_n),\n// .d(reduce_acc_sum),\n// .q(acc_sum)\n// );\n\n// dff_async #(\n// .WIDTH(ACC_WIDTH)) acc_carry_reg (\n// .clk(clk),\n// .rst_n(rst_n),\n// .d(reduce_acc_carry),\n// .q(acc_carry)\n// );\n\n\n\n \nendmodule\n\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/opt1_mac.v", "module opt1_mac #(\n parameter ACC_WIDTH = 32,\n parameter INPUT_PIP = 1\n)(\n input wire clk,\n input wire rst_n,\n input wire [7:0] operand_a_in, \n input wire [7:0] operand_b_in, \n output reg [ACC_WIDTH-1:0] acc_sum,\n output reg [ACC_WIDTH-1:0] acc_carry\n);\n\nreg [7:0] operand_a;\nreg [7:0] operand_b;\n\nwire signed [9:0] pp1;\nwire signed [9:0] pp2;\nwire signed [9:0] pp3;\nwire signed [9:0] pp4;\nwire [6*ACC_WIDTH-1 : 0] mul_reduce_csa_input;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp1;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp2;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp3;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp4;\nwire signed [ACC_WIDTH-1:0] reduce_acc_sum;\nwire signed [ACC_WIDTH-1:0] reduce_acc_carry;\n\nassign sign_extend_pp4 = $signed({pp4,6'b0});\nassign sign_extend_pp3 = $signed({pp3,4'b0});\nassign sign_extend_pp2 = $signed({pp2,2'b0});\nassign sign_extend_pp1 = $signed(pp1);\n\nassign mul_reduce_csa_input = {sign_extend_pp4,sign_extend_pp3,sign_extend_pp2,sign_extend_pp1,acc_carry, acc_sum};\n\nbooth_pp_gen booth_pp_gen_inst(\n .operand_a(operand_a), \n .operand_b(operand_b), \n .pp1(pp1),\n .pp2(pp2),\n .pp3(pp3),\n .pp4(pp4)\n);\n\nDW02_tree #(6, ACC_WIDTH, 1)\n U2 ( .INPUT(mul_reduce_csa_input), .OUT0(reduce_acc_sum), .OUT1(reduce_acc_carry) );\n\nalways @(posedge clk) begin\n if (!rst_n) begin\n acc_sum <= 0;\n acc_carry <= 0;\n end\n else begin\n acc_sum <= reduce_acc_sum;\n acc_carry <= reduce_acc_carry;\n end\nend\n\ngenerate\n if(INPUT_PIP == 1) begin\n always @(posedge clk) begin\n operand_a <= operand_a_in;\n operand_b <= operand_b_in;\n end\n end\n else begin\n always @(*) begin\n operand_a = operand_a_in;\n operand_b = operand_b_in;\n end\n end\nendgenerate\n\n// dff_async #(\n// .WIDTH(ACC_WIDTH)) acc_sum_reg (\n// .clk(clk),\n// .rst_n(rst_n),\n// .d(reduce_acc_sum),\n// .q(acc_sum)\n// );\n\n// dff_async #(\n// .WIDTH(ACC_WIDTH)) acc_carry_reg (\n// .clk(clk),\n// .rst_n(rst_n),\n// .d(reduce_acc_carry),\n// .q(acc_carry)\n// );\n\n\n\n \nendmodule\n\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/opt1_mac.v", "module opt1_mac #(\n parameter ACC_WIDTH = 32,\n parameter INPUT_PIP = 1\n)(\n input wire clk,\n input wire rst_n,\n input wire [7:0] operand_a_in, \n input wire [7:0] operand_b_in, \n input wire signed [2*ACC_WIDTH-1:0] partial_result, \n output reg [ACC_WIDTH-1:0] acc_sum,\n output reg [ACC_WIDTH-1:0] acc_carry\n);\n\nreg [7:0] operand_a;\nreg [7:0] operand_b;\n\nwire signed [9:0] pp1;\nwire signed [9:0] pp2;\nwire signed [9:0] pp3;\nwire signed [9:0] pp4;\nwire [6*ACC_WIDTH-1 : 0] mul_reduce_csa_input;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp1;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp2;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp3;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp4;\nwire signed [ACC_WIDTH-1:0] reduce_acc_sum;\nwire signed [ACC_WIDTH-1:0] reduce_acc_carry;\n\nassign sign_extend_pp4 = $signed({pp4,6'b0});\nassign sign_extend_pp3 = $signed({pp3,4'b0});\nassign sign_extend_pp2 = $signed({pp2,2'b0});\nassign sign_extend_pp1 = $signed(pp1);\n\nassign mul_reduce_csa_input = {sign_extend_pp4,sign_extend_pp3,sign_extend_pp2,sign_extend_pp1,partial_result[0+:ACC_WIDTH],partial_result[ACC_WIDTH+:ACC_WIDTH]};\n\nbooth_pp_gen booth_pp_gen_inst(\n .operand_a(operand_a), \n .operand_b(operand_b), \n .pp1(pp1),\n .pp2(pp2),\n .pp3(pp3),\n .pp4(pp4)\n);\n\nDW02_tree #(6, ACC_WIDTH, 1)\n U2 ( .INPUT(mul_reduce_csa_input), .OUT0(reduce_acc_sum), .OUT1(reduce_acc_carry) );\n\nalways @(posedge clk) begin\n if (!rst_n) begin\n acc_sum <= 0;\n acc_carry <= 0;\n end\n else begin\n acc_sum <= reduce_acc_sum;\n acc_carry <= reduce_acc_carry;\n end\nend\n\ngenerate\n if(INPUT_PIP == 1) begin\n always @(posedge clk) begin\n operand_a <= operand_a_in;\n operand_b <= operand_b_in;\n end\n end\n else begin\n always @(*) begin\n operand_a = operand_a_in;\n operand_b = operand_b_in;\n end\n end\nendgenerate\n\n// dff_async #(\n// .WIDTH(ACC_WIDTH)) acc_sum_reg (\n// .clk(clk),\n// .rst_n(rst_n),\n// .d(reduce_acc_sum),\n// .q(acc_sum)\n// );\n\n// dff_async #(\n// .WIDTH(ACC_WIDTH)) acc_carry_reg (\n// .clk(clk),\n// .rst_n(rst_n),\n// .d(reduce_acc_carry),\n// .q(acc_carry)\n// );\n\n\n\n \nendmodule\n\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/opt1_mac.v", "module opt1_mac #(\n parameter ACC_WIDTH = 32,\n parameter INPUT_PIP = 1\n)(\n input wire clk,\n input wire rst_n,\n input wire [7:0] operand_a_in, \n input wire [7:0] operand_b_in, \n input wire signed [2*ACC_WIDTH-1:0] partial_result, \n output reg [ACC_WIDTH-1:0] acc_sum,\n output reg [ACC_WIDTH-1:0] acc_carry\n);\n\nreg [7:0] operand_a;\nreg [7:0] operand_b;\n\nwire signed [9:0] pp1;\nwire signed [9:0] pp2;\nwire signed [9:0] pp3;\nwire signed [9:0] pp4;\nwire [6*ACC_WIDTH-1 : 0] mul_reduce_csa_input;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp1;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp2;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp3;\nwire signed [ACC_WIDTH-1:0] sign_extend_pp4;\nwire signed [ACC_WIDTH-1:0] reduce_acc_sum;\nwire signed [ACC_WIDTH-1:0] reduce_acc_carry;\n\nassign sign_extend_pp4 = $signed({pp4,6'b0});\nassign sign_extend_pp3 = $signed({pp3,4'b0});\nassign sign_extend_pp2 = $signed({pp2,2'b0});\nassign sign_extend_pp1 = $signed(pp1);\n\nassign mul_reduce_csa_input = {sign_extend_pp4,sign_extend_pp3,sign_extend_pp2,sign_extend_pp1,partial_result[0+:ACC_WIDTH],partial_result[ACC_WIDTH+:ACC_WIDTH]};\n\nbooth_pp_gen booth_pp_gen_inst(\n .operand_a(operand_a), \n .operand_b(operand_b), \n .pp1(pp1),\n .pp2(pp2),\n .pp3(pp3),\n .pp4(pp4)\n);\n\nDW02_tree #(6, ACC_WIDTH, 1)\n U2 ( .INPUT(mul_reduce_csa_input), .OUT0(reduce_acc_sum), .OUT1(reduce_acc_carry) );\n\nalways @(posedge clk) begin\n if (!rst_n) begin\n acc_sum <= 0;\n acc_carry <= 0;\n end\n else begin\n acc_sum <= reduce_acc_sum;\n acc_carry <= reduce_acc_carry;\n end\nend\n\ngenerate\n if(INPUT_PIP == 1) begin\n always @(posedge clk) begin\n operand_a <= operand_a_in;\n operand_b <= operand_b_in;\n end\n end\n else begin\n always @(*) begin\n operand_a = operand_a_in;\n operand_b = operand_b_in;\n end\n end\nendgenerate\n\n// dff_async #(\n// .WIDTH(ACC_WIDTH)) acc_sum_reg (\n// .clk(clk),\n// .rst_n(rst_n),\n// .d(reduce_acc_sum),\n// .q(acc_sum)\n// );\n\n// dff_async #(\n// .WIDTH(ACC_WIDTH)) acc_carry_reg (\n// .clk(clk),\n// .rst_n(rst_n),\n// .d(reduce_acc_carry),\n// .q(acc_carry)\n// );\n\n\n\n \nendmodule\n\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT3_OPT4C/pe/pe.v", "module pe #(\n parameter ACC_WIDTH = 26 //due to the same bit-weight reduction\n)(\n input clk,\n input rst_n,\n input clr,\n input wire [1:0] encoder_position_ins,\n input wire [7:0] operand_b_ins,\n output wire [51:0] result\n);\n\nwire signed [ACC_WIDTH-1:0] sum;\nwire signed [ACC_WIDTH-1:0] carry;\nwire signed [ACC_WIDTH-1:0] sum_input;\nwire signed [ACC_WIDTH-1:0] carry_input;\nreg signed [ACC_WIDTH-1:0] acc_sum;\nreg signed [ACC_WIDTH-1:0] acc_carry;\nreg [1:0] encoder_position;\nreg signed [7:0] operand_b;\n\n\nwire signed [8:0] b;\nwire signed [8:0] b_2;\nwire signed [8:0] neg_b;\nwire signed [9:0] neg_b_2;\nreg signed [9:0] mux_select_b;\nwire signed [ACC_WIDTH-1:0] mux_extend_b;\nwire [3*ACC_WIDTH-1:0] csa_input;\n\nassign b = $signed(operand_b);\nassign b_2 = {operand_b,1'b0};\nassign neg_b = ~b + 1'b1;\nassign neg_b_2 = {neg_b,1'b0};\nassign mux_extend_b = mux_select_b;\nassign sum_input = !clr ? 0 : acc_sum;\nassign carry_input = !clr ? 0 : acc_carry;\nassign csa_input = {mux_extend_b,sum_input,carry_input};\n\nalways @(*) begin\n case (encoder_position)\n 2'd0: mux_select_b = $signed(neg_b_2);\n 2'd1: mux_select_b = $signed(b);\n 2'd2: mux_select_b = $signed(b_2);\n 2'd3: mux_select_b = $signed(neg_b);\n endcase\nend\n\nDW02_tree #(3,ACC_WIDTH, 1)\n U1 ( .INPUT(csa_input), .OUT0(sum), .OUT1(carry) );\n\n always @(posedge clk or negedge rst_n) begin\n\tif (!rst_n) begin\n encoder_position <=0;\n operand_b <=0;\n\tend\n\telse begin\n encoder_position <= encoder_position_ins;\n operand_b <= operand_b_ins;\n\tend\nend\n\nalways @(posedge clk) begin\n acc_sum <= sum ;\n acc_carry <= carry;\nend\n\nassign result = {acc_sum,acc_carry};\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_mac_based/pe.v", "module PE #\n(\n parameter WIDTH = 8,\n parameter ACC_WIDTH = 32\n)\n(\n input wire rst_n,\n input wire clk,\n input wire signed [WIDTH-1 :0] a,\n input wire signed [WIDTH-1 :0] b,\n input wire clc, // clean_result_cache,\n\n output reg signed [WIDTH-1 :0] row,\n output reg signed [WIDTH-1 :0] col,\n output reg signed [ACC_WIDTH-1 :0] result\n);\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n result <= 0;\n end\n else begin\n if(clc)\n result <= 0;\n else\n result <= result + a * b ;\n end\nend\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n row <= 0;\n col <= 0;\n end\n else begin\n row <= a;\n col <= b;\n end\nend\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_mac_based/top.v", "module top #\n(\n parameter A_H = 16, \n parameter B_W = 16, \n parameter WIDTH = 8,\n parameter ACC_WIDTH = 32 \n)\n(\n input wire rst_n ,\n input wire clk ,\n input wire [A_H*WIDTH-1 :0] A ,\n input wire [B_W*WIDTH-1 :0] B ,\n input wire clc , // clean_result_cache,\n output wire [A_H*B_W*ACC_WIDTH-1 :0] result \n);\n\nreg [A_H*WIDTH-1 :0] A_reg ;\nreg [B_W*WIDTH-1 :0] B_reg ;\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n A_reg<={(A_H*WIDTH){1'b0}};\n B_reg<={(B_W*WIDTH){1'b0}};\n end\n else begin\n A_reg<=A;\n B_reg<=B;\n end\nend\n\nwire signed [WIDTH-1:0] row [0:A_H-1][0:B_W-1];\nwire signed [WIDTH-1:0] col [0:A_H-1][0:B_W-1];\n\n\n genvar i, j;\n generate\n for (i = 0; i < A_H; i = i + 1 ) begin\n for(j = 0; j < B_W; j = j + 1) begin\n if(i==0) begin\n if(j==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .a (A_reg[WIDTH-1 :0] ),\n .b (B_reg[WIDTH-1 :0] ),\n .clc (clc ),\n .row (row[i][j] ),\n .col (col[i][j] ),\n .result (result[(i*B_W+j+1)*ACC_WIDTH-1:(i*B_W+j)*ACC_WIDTH])\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .a (row[i][j-1] ),\n .b (B_reg[WIDTH*(j+1)-1 :WIDTH*j] ),\n .clc (clc ),\n .row (row[i][j] ),\n .col (col[i][j] ),\n .result (result[(i*B_W+j+1)*ACC_WIDTH-1:(i*B_W+j)*ACC_WIDTH])\n );\n end\n end\n else if (j==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .a (A_reg[WIDTH*(i+1)-1 :WIDTH*i] ),\n .b (col[i-1][j] ),\n .clc (clc ),\n .row (row[i][j] ),\n .col (col[i][j] ),\n .result (result[(i*B_W+j+1)*ACC_WIDTH-1:(i*B_W+j)*ACC_WIDTH])\n );\n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .a (row[i][j-1] ),\n .b (col[i-1][j] ),\n .clc (clc ),\n .row (row[i][j] ),\n .col (col[i][j] ),\n .result (result[(i*B_W+j+1)*ACC_WIDTH-1:(i*B_W+j)*ACC_WIDTH])\n ); \n \n end \n end\n end\n endgenerate\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_mac_based/PE.v", "// b = w * a\nmodule PE #\n(\n parameter WIDTH = 8,\n parameter ACC_WIDTH = 24\n)\n(\n input wire rst_n ,\n input wire clk ,\n input wire weight_wen ,\n input [WIDTH-1 :0] weight_din ,\n input wire signed [WIDTH-1 :0] a ,\n input wire signed [ACC_WIDTH-1 :0] partial_result , \n\n output reg signed [WIDTH-1 :0] col ,\n output reg signed [ACC_WIDTH-1 :0] row \n);\n\n\nreg signed [WIDTH-1 :0] weight;\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n weight <= 0;\n end\n else begin\n if(weight_wen) begin\n weight <= weight_din; \n end\n else begin\n weight <= weight;\n end\n end\nend\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n col <= 0;\n end\n else begin\n if(weight_wen) begin\n col <= weight_din; \n end\n else begin\n col <= a;\n end\n end\nend\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n row <= 0;\n end\n else begin\n row <= partial_result + weight * a;\n end\nend\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/mac_pe/mac.v", "module mac #\n(\n parameter WIDTH = 8,\n parameter ACC_WIDTH = 32\n)\n(\n input wire rst_n,\n input wire clk,\n input wire signed [WIDTH-1 :0] a,\n input wire signed [WIDTH-1 :0] b,\n output reg signed [ACC_WIDTH-1 :0] result\n);\n\nwire signed [15:0] result_p;\nreg signed [7:0] operand_a;\nreg signed [7:0] operand_b;\n\nassign result_p = $signed(operand_a) * $signed(operand_b) ;\n\nalways @(posedge clk) begin\n operand_a <= a;\n operand_b <= b;\nend\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n result <= 0;\n end\n else begin\n result <= result + $signed(result_p);\n end\nend\n\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/top.v", "module top #\n(\n parameter A_H = 16, //CHANGE\n parameter B_W = 16, //CHANGE\n parameter WIDTH = 8,\n parameter ACC_WIDTH = 32 //CHANGE\n)\n(\n input wire rst_n ,\n input wire clk ,\n input wire [A_H*WIDTH-1 :0] A ,\n input wire [B_W*WIDTH-1 :0] B ,\n input wire clc , // clean_result_cache\n// output wire [A_H*B_W*ACC_WIDTH-1 :0] result \n output wire [2*A_H*B_W*ACC_WIDTH-1 :0] result \n);\n\nreg [A_H*WIDTH-1 :0] A_reg ;\nreg [B_W*WIDTH-1 :0] B_reg ;\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n A_reg<={(A_H*WIDTH){1'b0}};\n B_reg<={(B_W*WIDTH){1'b0}};\n end\n else begin\n A_reg<=A;\n B_reg<=B;\n end\nend\n\nwire signed [WIDTH-1:0] row [0:A_H-1][0:B_W-1];\nwire signed [WIDTH-1:0] col [0:A_H-1][0:B_W-1];\n\n\n genvar i, j;\n generate\n for (i = 0; i < A_H; i = i + 1 ) begin\n for(j = 0; j < B_W; j = j + 1) begin\n if(i==0) begin\n if(j==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .a (A_reg[WIDTH-1 :0] ),\n .b (B_reg[WIDTH-1 :0] ),\n .clc (clc ), // input wire clean_result_cache\n .row (row[i][j] ),\n .col (col[i][j] ),\n// .result (result[(i*B_W+j+1)*ACC_WIDTH-1:(i*B_W+j)*ACC_WIDTH])\n .result (result[(i*B_W+j+1)*2*ACC_WIDTH-1:(i*B_W+j)*2*ACC_WIDTH])\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .a (row[i][j-1] ),\n .b (B_reg[WIDTH*(j+1)-1 :WIDTH*j] ),\n .clc (clc ), // input wire clean_result_cache\n .row (row[i][j] ),\n .col (col[i][j] ),\n// .result (result[(i*B_W+j+1)*ACC_WIDTH-1:(i*B_W+j)*ACC_WIDTH])\n .result (result[(i*B_W+j+1)*2*ACC_WIDTH-1:(i*B_W+j)*2*ACC_WIDTH])\n );\n end\n end\n else if (j==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .a (A_reg[WIDTH*(i+1)-1 :WIDTH*i] ),\n .b (col[i-1][j] ),\n .clc (clc ), // input wire clean_result_cache\n .row (row[i][j] ),\n .col (col[i][j] ),\n// .result (result[(i*B_W+j+1)*ACC_WIDTH-1:(i*B_W+j)*ACC_WIDTH])\n .result (result[(i*B_W+j+1)*2*ACC_WIDTH-1:(i*B_W+j)*2*ACC_WIDTH])\n );\n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .a (row[i][j-1] ),\n .b (col[i-1][j] ),\n .clc (clc ), // input wire clean_result_cache\n .row (row[i][j] ),\n .col (col[i][j] ),\n// .result (result[(i*B_W+j+1)*ACC_WIDTH-1:(i*B_W+j)*ACC_WIDTH])\n .result (result[(i*B_W+j+1)*2*ACC_WIDTH-1:(i*B_W+j)*2*ACC_WIDTH])\n ); \n \n end \n end\n end\n endgenerate\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_mac_based/top.v", "// Calculate matrix (A*B)\n// Size of A is (M*K), size of B is (K*N), and A_H = K, B_W = N, B is weight\n// Size of output matirx A*B is (M*N)\n\nmodule top #\n(\n parameter A_H = 16, \n parameter B_W = 16, \n parameter WIDTH = 8,\n // parameter ACC_WIDTH = 32 \n parameter ACC_WIDTH = 2*WIDTH + $clog2(A_H)\n)\n(\n input wire clk ,\n input wire rst_n ,\n input weight_wen ,\n input [A_H*WIDTH-1 :0] weight_din ,\n input wire [A_H*WIDTH-1 :0] A ,\n output wire [B_W*ACC_WIDTH-1 :0] result \n);\n\nreg [A_H*WIDTH-1 :0] A_reg ;\nreg [A_H*WIDTH-1 :0] weight_din_reg;\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n A_reg<={(A_H*WIDTH){1'b0}};\n weight_din_reg <= {(B_W*WIDTH){1'b0}};\n end\n else begin\n A_reg<=A;\n weight_din_reg <= weight_din;\n end\nend\n\n\nwire signed [ACC_WIDTH-1:0] row [0:B_W-1][0:A_H-1];\nwire signed [WIDTH-1:0] col [0:B_W-1][0:A_H-1];\n\n\n genvar i, j;\n generate\n for (i = 0; i < B_W; i = i + 1 ) begin\n for(j = 0; j < A_H; j = j + 1) begin\n if(j==0) begin\n if(i==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .weight_wen (weight_wen ),\n .weight_din (weight_din_reg[(j+1)*WIDTH-1:j*WIDTH] ),\n .a (A_reg[(j+1)*WIDTH-1:j*WIDTH] ),\n .partial_result ({ACC_WIDTH{1'b0}} ), // or input\n .row (row[i][j] ),\n .col (col[i][j] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .weight_wen (weight_wen ),\n .weight_din (col[i-1][j] ),\n .a (col[i-1][j] ),\n .partial_result ({ACC_WIDTH{1'b0}} ), // or input\n .row (row[i][j] ),\n .col (col[i][j] )\n ); \n end\n end\n else if (i==0) begin\n if(j==A_H-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .weight_wen (weight_wen ),\n .weight_din (weight_din_reg[(j+1)*WIDTH-1:j*WIDTH] ),\n .a (A_reg[(j+1)*WIDTH-1:j*WIDTH] ),\n .partial_result (row[i][j-1] ),\n .row (result[(i+1)*ACC_WIDTH-1 :i*ACC_WIDTH] ),\n .col (col[i][j] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .weight_wen (weight_wen ),\n .weight_din (weight_din_reg[(j+1)*WIDTH-1:j*WIDTH] ),\n .a (A_reg[(j+1)*WIDTH-1:j*WIDTH] ),\n .partial_result (row[i][j-1] ),\n .row (row[i][j] ),\n .col (col[i][j] )\n ); \n end\n end\n else if (j==A_H-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .weight_wen (weight_wen ),\n .weight_din (col[i-1][j] ),\n .a (col[i-1][j] ),\n .partial_result (row[i][j-1] ),\n .row (result[(i+1)*ACC_WIDTH-1 :i*ACC_WIDTH] ),\n .col (col[i][j] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .weight_wen (weight_wen ),\n .weight_din (col[i-1][j] ),\n .a (col[i-1][j] ),\n .partial_result (row[i][j-1] ),\n .row (row[i][j] ),\n .col (col[i][j] )\n ); \n end\n end\n end\nendgenerate\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT2/tree_full_sum.sv", "module tree_full_sum #(\n parameter K = 16,\n parameter WIDTH = 13\n)(\n input clk,\n input [K*WIDTH-1:0] csa_input,\n output reg signed [WIDTH-1:0] full_sum\n);\n\nwire signed [WIDTH-1:0] acc_sum;\nwire signed [WIDTH-1:0] acc_carry;\n\ngenvar i;\ngenerate\n if(K == 4) begin\n always @(posedge clk) begin\n full_sum <= $signed(csa_input[1*WIDTH-1:0*WIDTH]) + $signed(csa_input[2*WIDTH-1:1*WIDTH]) + $signed(csa_input[3*WIDTH-1:2*WIDTH]) + $signed(csa_input[4*WIDTH-1:3*WIDTH]);\n end\n end\n else begin\n DW02_tree #(K, WIDTH, 1)\n ins_tree ( .INPUT(csa_input), .OUT0(acc_sum), .OUT1(acc_carry));\n always @(posedge clk) begin\n full_sum <= $signed(acc_sum) + $signed(acc_carry);\n end\n end\nendgenerate\n\n\n\n\nendmodule\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_mac_based/pe.v", "`timescale 1ns / 1ps\n\n// b = w * a\nmodule PE #\n(\n parameter WIDTH = 8,\n parameter ACC_WIDTH = 24\n)\n(\n input wire rst_n,\n input wire clk,\n input wire signed [WIDTH-1 :0] i_z_a,\n input wire signed [WIDTH-1 :0] i_x_b,\n input wire signed [ACC_WIDTH-1 :0] i_y_p,\n\n output reg signed [WIDTH-1 :0] o_z_a,\n output reg signed [WIDTH-1 :0] o_x_b,\n output reg signed [ACC_WIDTH-1 :0] o_y_p\n);\n\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n o_y_p <= 0;\n end\n else begin\n o_y_p <= i_y_p + i_z_a*i_x_b; \n end\nend\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n o_z_a <= 0;\n o_x_b <= 0;\n end\n else begin\n o_z_a <= i_z_a; \n o_x_b <= i_x_b; \n end\nend\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_mac_based/top.v", "`timescale 1ns / 1ps\nmodule top #\n(\n parameter N = 8, //CHANGE\n parameter WIDTH = 8, \n parameter ACC_WIDTH = 2*WIDTH + $clog2(N) \n)\n(\n input wire rst_n ,\n input wire clk ,\n input wire [N*N*WIDTH-1 :0] A ,\n input wire [N*N*WIDTH-1 :0] B ,\n output wire [N*N*ACC_WIDTH-1 :0] result \n);\n\nreg [N*N*WIDTH-1 :0] A_reg ;\nreg [N*N*WIDTH-1 :0] B_reg ;\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n A_reg<={(N*N*WIDTH){1'b0}};\n B_reg<={(N*N*WIDTH){1'b0}};\n end\n else begin\n A_reg<=A;\n B_reg<=B;\n end\nend\n\n\nwire signed [WIDTH-1:0] d_x [0:N-1][0:N-1][0:N-1];\nwire signed [ACC_WIDTH-1:0] d_y [0:N-1][0:N-1][0:N-1];\nwire signed [WIDTH-1:0] d_z [0:N-1][0:N-1][0:N-1];\n\n\n genvar x, y, z;\n generate\n for (z = 0; z < N; z = z + 1 ) begin\n for(x = 0; x < N; x = x + 1) begin\n for (y = 0; y < N; y = y + 1 ) begin\n if(z==0) begin\n if(x==0) begin\n if(y==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE //(1)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p ({ACC_WIDTH{1'b0}} ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n ); \n end\n else if(y==N-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(3)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (result[N*ACC_WIDTH*z+(x+1)*ACC_WIDTH-1 : ACC_WIDTH*N*z+x*ACC_WIDTH] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(2)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n );\n end\n end\n else begin\n if(y==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE //(6)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p ({ACC_WIDTH{1'b0}} ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n ); \n end\n else if(y==N-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(5)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (result[N*ACC_WIDTH*z+(x+1)*ACC_WIDTH-1 : ACC_WIDTH*N*z+x*ACC_WIDTH] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(4)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n );\n end \n end\n end\n else begin\n if(x==0) begin\n if(y==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE //(7)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p ({ACC_WIDTH{1'b0}} ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n ); \n end\n else if(y==N-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(9)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (result[N*ACC_WIDTH*z+(x+1)*ACC_WIDTH-1 : ACC_WIDTH*N*z+x*ACC_WIDTH] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(8)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n );\n end\n end\n else begin\n if(y==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE //(10)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p ({ACC_WIDTH{1'b0}} ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n ); \n end\n else if(y==N-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(12)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (result[N*ACC_WIDTH*z+(x+1)*ACC_WIDTH-1 : ACC_WIDTH*N*z+x*ACC_WIDTH] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(11)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n );\n end \n end\n end\n end\n end\n end\n endgenerate\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/top.v", "`timescale 1ns / 1ps\n\n// Calculate matrix (A*B)\n// Size of A is (A_H*A_W), size of B is (B_H*B_W), and A_W = B_H\n// Size of output matirx A*B is (A_H*B_W)\n\nmodule top #\n(\n parameter N = 8, //CHANGE\n parameter WIDTH = 8, \n parameter ACC_WIDTH = 2*WIDTH + $clog2(N) \n)\n(\n input wire rst_n ,\n input wire clk ,\n input wire [N*N*WIDTH-1 :0] A ,\n input wire [N*N*WIDTH-1 :0] B ,\n output wire [N*N*2*ACC_WIDTH-1 :0] result \n);\n\nreg [N*N*WIDTH-1 :0] A_reg ;\nreg [N*N*WIDTH-1 :0] B_reg ;\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n A_reg<={(N*N*WIDTH){1'b0}};\n B_reg<={(N*N*WIDTH){1'b0}};\n end\n else begin\n A_reg<=A;\n B_reg<=B;\n end\nend\n\n\nwire signed [WIDTH-1:0] d_x [0:N-1][0:N-1][0:N-1];\nwire signed [2*ACC_WIDTH-1:0] d_y [0:N-1][0:N-1][0:N-1];\nwire signed [WIDTH-1:0] d_z [0:N-1][0:N-1][0:N-1];\n\n\n genvar x, y, z;\n generate\n for (z = 0; z < N; z = z + 1 ) begin\n for(x = 0; x < N; x = x + 1) begin\n for (y = 0; y < N; y = y + 1 ) begin\n if(z==0) begin\n if(x==0) begin\n if(y==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE //(1)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p ({2*ACC_WIDTH{1'b0}} ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n ); \n end\n else if(y==N-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(3)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (result[N*2*ACC_WIDTH*z+(x+1)*2*ACC_WIDTH-1 : 2*ACC_WIDTH*N*z+x*2*ACC_WIDTH] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(2)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n );\n end\n end\n else begin\n if(y==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE //(6)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p ({2*ACC_WIDTH{1'b0}} ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n ); \n end\n else if(y==N-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(5)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (result[N*2*ACC_WIDTH*z+(x+1)*2*ACC_WIDTH-1 : 2*ACC_WIDTH*N*z+x*2*ACC_WIDTH] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(4)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (A_reg[N*WIDTH*x+(y+1)*WIDTH-1 : WIDTH*N*x+y*WIDTH] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n );\n end \n end\n end\n else begin\n if(x==0) begin\n if(y==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE //(7)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p ({2*ACC_WIDTH{1'b0}} ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n ); \n end\n else if(y==N-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(9)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (result[N*2*ACC_WIDTH*z+(x+1)*2*ACC_WIDTH-1 : 2*ACC_WIDTH*N*z+x*2*ACC_WIDTH] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(8)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (B_reg[N*WIDTH*z+(y+1)*WIDTH-1 : WIDTH*N*z+y*WIDTH] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n );\n end\n end\n else begin\n if(y==0) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE //(10)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p ({2*ACC_WIDTH{1'b0}} ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n ); \n end\n else if(y==N-1) begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(12)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (result[N*2*ACC_WIDTH*z+(x+1)*2*ACC_WIDTH-1 : 2*ACC_WIDTH*N*z+x*2*ACC_WIDTH] )\n ); \n end\n else begin\n PE #(.WIDTH(WIDTH),.ACC_WIDTH(ACC_WIDTH)) u_PE//(11)\n (\n .rst_n (rst_n ),\n .clk (clk ),\n .i_z_a (d_z[z-1][y][x] ),\n .i_x_b (d_x[z][y][x-1] ),\n .i_y_p (d_y[z][y-1][x] ),\n .o_z_a (d_z[z][y][x] ),\n .o_x_b (d_x[z][y][x] ),\n .o_y_p (d_y[z][y][x] )\n );\n end \n end\n end\n end\n end\n end\n endgenerate\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT2/top_pe_tile.sv", "module top_pe_tile #(\n localparam RESULT_WIDTH = 20\n)(\n input clk,\n input weight_wen,\n input [7:0] weight_din,\n input [3:0] bit_enable [0:15],\n input [7:0] partial_product_select [0:15],\n output reg signed [RESULT_WIDTH-1:0] result,\n output reg [3:0] bit_enable_pip [0:15],\n output reg [7:0] partial_product_select_pip [0:15]\n);\n\nlocalparam REDUCE_WIDTH = 13;\n\n//*********range of partial_product in same bit-weight********/\n//** 9bit: -256 ≤ partial_product ≤ 254 /\n//** 13bit: -4096 ≤ 16 * partial_product ≤ 4064 /\n//************************************************************/\nwire [7:0] weight [0:15];\nwire signed [9:0] partial_product [0:15][0:3]; \nwire signed [REDUCE_WIDTH-1:0] csa_extend [0:15][0:3];\nwire [16*REDUCE_WIDTH-1:0] csa_input [0:3];\nwire [4*REDUCE_WIDTH-1:0] mid_result [0:3];\nwire signed [REDUCE_WIDTH-1:0] result_bw [0:3];\nwire signed [RESULT_WIDTH-1:0] bw_0;\nwire signed [RESULT_WIDTH-1:0] bw_1;\nwire signed [RESULT_WIDTH-1:0] bw_2;\nwire signed [RESULT_WIDTH-1:0] bw_3;\n\n\nweight_rf weight_buffer(\n .clk(clk),\n .wen(weight_wen),\n .din(weight_din),\n .weight(weight) \n);\n\ngenvar i,j;\ngenerate\n for (i=0;i<16;i=i+1) begin\n partial_product_select pps (\n .clk(clk),\n .weight(weight[i]),\n .bit_enable(bit_enable_pip[i]),\n .partial_product_select(partial_product_select_pip[i]),\n .partial_product(partial_product[i])\n );\n end\nendgenerate\n\ngenerate\n for (i=0;i<16;i=i+1) begin\n for (j=0;j<4;j=j+1) begin\n assign csa_extend[i][j] = $signed(partial_product[i][j]);\n end\n end\nendgenerate\n\ngenerate\n for (i=0;i<4;i=i+1) begin\n for (j=0;j<16;j=j+1) begin\n assign csa_input[i][(j+1)*REDUCE_WIDTH-1:j*REDUCE_WIDTH] = csa_extend[j][i];\n end\n end\nendgenerate\n\n\ngenerate\n for (i=0;i<4;i=i+1) begin\n\n tree_full_sum #(\n .K(4),\n .WIDTH(REDUCE_WIDTH)\n ) tree_stage_1_0 (\n .clk(clk),\n .csa_input({csa_input[i][1*REDUCE_WIDTH-1:0],\n csa_input[i][2*REDUCE_WIDTH-1:1*REDUCE_WIDTH],\n csa_input[i][3*REDUCE_WIDTH-1:2*REDUCE_WIDTH],\n csa_input[i][4*REDUCE_WIDTH-1:3*REDUCE_WIDTH]}),\n .full_sum(mid_result[i][1*REDUCE_WIDTH-1:0*REDUCE_WIDTH])\n );\n tree_full_sum #(\n .K(4),\n .WIDTH(REDUCE_WIDTH)\n ) tree_stage_1_1 (\n .clk(clk),\n .csa_input({csa_input[i][5*REDUCE_WIDTH-1:4*REDUCE_WIDTH],\n csa_input[i][6*REDUCE_WIDTH-1:5*REDUCE_WIDTH],\n csa_input[i][7*REDUCE_WIDTH-1:6*REDUCE_WIDTH],\n csa_input[i][8*REDUCE_WIDTH-1:7*REDUCE_WIDTH]}),\n .full_sum(mid_result[i][2*REDUCE_WIDTH-1:1*REDUCE_WIDTH])\n );\n tree_full_sum #(\n .K(4),\n .WIDTH(REDUCE_WIDTH)\n ) tree_stage_1_2 (\n .clk(clk),\n .csa_input({csa_input[i][9*REDUCE_WIDTH-1:8*REDUCE_WIDTH],\n csa_input[i][10*REDUCE_WIDTH-1:9*REDUCE_WIDTH],\n csa_input[i][11*REDUCE_WIDTH-1:10*REDUCE_WIDTH],\n csa_input[i][12*REDUCE_WIDTH-1:11*REDUCE_WIDTH]}),\n .full_sum(mid_result[i][3*REDUCE_WIDTH-1:2*REDUCE_WIDTH])\n );\n tree_full_sum #(\n .K(4),\n .WIDTH(REDUCE_WIDTH)\n ) tree_stage_1_3 (\n .clk(clk),\n .csa_input({csa_input[i][13*REDUCE_WIDTH-1:12*REDUCE_WIDTH],\n csa_input[i][14*REDUCE_WIDTH-1:13*REDUCE_WIDTH],\n csa_input[i][15*REDUCE_WIDTH-1:14*REDUCE_WIDTH],\n csa_input[i][16*REDUCE_WIDTH-1:15*REDUCE_WIDTH]}),\n .full_sum(mid_result[i][4*REDUCE_WIDTH-1:3*REDUCE_WIDTH])\n );\n end\nendgenerate\n\n\ngenerate\n for (i=0;i<4;i=i+1) begin\n tree_full_sum #(\n .K(4),\n .WIDTH(REDUCE_WIDTH)\n ) tree_stage_2 (\n .clk(clk),\n .csa_input({mid_result[i][1*REDUCE_WIDTH-1:0],\n mid_result[i][2*REDUCE_WIDTH-1:1*REDUCE_WIDTH],\n mid_result[i][3*REDUCE_WIDTH-1:2*REDUCE_WIDTH],\n mid_result[i][4*REDUCE_WIDTH-1:3*REDUCE_WIDTH]}),\n .full_sum(result_bw[i])\n );\n end\nendgenerate\n\n\nassign bw_0 = $signed(result_bw[0]);\nassign bw_1 = $signed({result_bw[1],2'b0});\nassign bw_2 = $signed({result_bw[2],4'b0});\nassign bw_3 = $signed({result_bw[3],6'b0});\n\ntree_full_sum #(\n .K(4),\n .WIDTH(RESULT_WIDTH)\n) tree_stage_3 (\n .clk(clk),\n .csa_input({bw_0,bw_1,bw_2,bw_3}),\n .full_sum(result)\n );\n\n// pipeline the bit_enable and partial_product_select\nalways @(posedge clk) begin\n bit_enable_pip <= bit_enable;\n partial_product_select_pip <= partial_product_select;\nend\n\nendmodule\n\n\n\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT3_OPT4C/array/top_pe_column.v", "module top_pe_column #(\n parameter N = 32,\n parameter ACC_WIDTH = 26\n\n)(\n input clk,\n input rst_n,\n input clr,\n input [7:0] en_multiplicand, // operand a\n input [3:0] sign_en_multiplicand,\n input encode_valid,\n input [8*N-1:0] operand_b, \n output [1:0] position, // to prefetch operand b \n output [2:0] cal_cycle, // to prefetch operand a \n output [52*N-1:0] pe_result \n);\n\nwire [1:0] partial_product_index;\n\ngenvar i;\nsparse_encoder sp_encoder(\n .clk(clk),\n .rst_n(rst_n),\n .en_multiplicand(en_multiplicand),\n .sign_en_multiplicand(sign_en_multiplicand),\n .encode_valid(encode_valid),\n .partial_product_index(partial_product_index), // to sparse_pe generate partial product\n .position_0(position), // to prefetch operand b\n .cal_cycle(cal_cycle) // to prefetch operand a \n);\n\ngenerate\nfor (i = 0 ; i < N ; i = i + 1) begin\n pe #(\n .ACC_WIDTH(26)\n ) sparse_pe (\n .clk(clk),\n .rst_n(rst_n),\n .clr(clr),\n .encoder_position_ins(partial_product_index),\n .operand_b_ins(operand_b[8*(i+1)-1:8*i]),\n .result(pe_result[52*(i+1)-1:52*i])\n );\nend\nendgenerate\n\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT3_OPT4C/pe/encoder_multi_bit.v", "module encoder_multi_bit #(\n localparam WIDTH = 8,\n localparam ENCODER_WIDTH = WIDTH + (WIDTH+1)%2,\n localparam TIMES = (WIDTH-1)/2 + (WIDTH-1)%2\n)(\n input clk,\n input rst_n,\n input [WIDTH-1:0] multiplicand,\n input multiplicand_valid, \n output reg [WIDTH:0] en_multiplicand, // native EN-T encoding is sent to tensorcore local memory or local rf.\n output en_multiplicand_valid\n );\n\nwire [WIDTH-1:0] encoder_input;\nwire [ENCODER_WIDTH-1:0] en_multiplicand_ins;\nwire [TIMES-1:0] en_t_c_out;\nreg [WIDTH-1:0] multiplicand_reg;\n\nassign encoder_input = (multiplicand_reg != 8'b10000000) ? {1'b0,multiplicand_reg[WIDTH-2:0]} : 8'b10000000;\nassign en_multiplicand_ins[ENCODER_WIDTH-1] = multiplicand_reg[WIDTH-1];\n\ngenvar i;\ngenerate for(i = 0; i < TIMES; i = i + 1) begin: gen_encoder \n if(i==0) begin\n assign en_multiplicand_ins[1:0] = multiplicand_reg[1:0];\n end\n else if (i==1)begin\n encoder ins_encoder\n (.A(encoder_input[2*i-1:2*i-2]),\n .C_IN(1'b0), \n .B(encoder_input[2*i+1:2*i]), \n .en_t_c_out(en_t_c_out[i]), \n .EN_B(en_multiplicand_ins[2*i+1:2*i]));\n end\n else begin\n encoder ins_encoder\n (.A(encoder_input[2*i-1:2*i-2]),\n .C_IN(en_t_c_out[i-1]), \n .B(encoder_input[2*i+1:2*i]), \n .en_t_c_out(en_t_c_out[i]), \n .EN_B(en_multiplicand_ins[2*i+1:2*i]));\n end \nend \nendgenerate \n\n\nalways @(posedge clk or negedge rst_n) begin\n\tif (!rst_n) begin\n en_multiplicand <= 0;\n multiplicand_reg <= 0;\n end\n\telse begin\n en_multiplicand <= en_multiplicand_ins; \n //multiplicand belongs to [-128,127] range and operand with complement representation use this logic:\n multiplicand_reg <= (multiplicand[WIDTH-1] & (multiplicand[WIDTH-2:0] != 0)) ? ({1'b1,~multiplicand[WIDTH-2:0] + 1'b1}) : multiplicand; \n //multiplicand belongs to [-127,127] range and operand with sign-magnitude representation use this logic:\n //multiplicand_reg <= multiplicand; \n end\nend\n\nget_pipeline_mulwidth #(\n .N(2), \n .WIDTH(1) \n) pipeline_en_multiplicand_valid (\n .clk(clk), \n .rst_n(rst_n), \n .signal(multiplicand_valid), \n .pipeline_signal(en_multiplicand_valid) \n);\n\nendmodule\n\n\nmodule encoder(A, C_IN, B, en_t_c_out, EN_B);\n\ninput wire [1:0] A;\ninput wire C_IN;\ninput wire [1:0] B;\n\noutput wire en_t_c_out;\noutput wire [1:0] EN_B;\n\nassign en_t_c_out = (A[0] & A[1]) | (A[1] & C_IN); \nassign EN_B = B + en_t_c_out;\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT3_OPT4C/pe/top_pe.v", "module top_pe(\n input clk,\n input rst_n,\n input clr,\n input [7:0] en_multiplicand, // operand a\n input [3:0] sign_en_multiplicand,\n input encode_valid,\n input [7:0] operand_b, \n output [1:0] position, // to prefetch operand b \n output [2:0] cal_cycle, // to prefetch operand a \n output [51:0] pe_result \n);\n\nwire [1:0] partial_product_index;\n\nsparse_encoder sp_encoder(\n .clk(clk),\n .rst_n(rst_n),\n .en_multiplicand(en_multiplicand),\n .sign_en_multiplicand(sign_en_multiplicand),\n .encode_valid(encode_valid),\n .partial_product_index(partial_product_index), // to sparse_pe generate partial product\n .position_0(position), // to prefetch operand b\n .cal_cycle(cal_cycle) // to prefetch operand a \n);\n\n\npe #(\n .ACC_WIDTH(26)\n) sparse_pe (\n .clk(clk),\n .rst_n(rst_n),\n .clr(clr),\n .encoder_position_ins(partial_product_index),\n .operand_b_ins(operand_b),\n .result(pe_result)\n);\n\n\n\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT2/vector_encoder.sv", "module vector_encoder(\n input clk,\n input [127:0] operand_a,\n output reg [3:0] bit_enable [0:15],\n output reg [7:0] partial_product_select [0:15]\n);\n\nwire [3:0] bit_valid [0:15];\nwire [7:0] encoder_nub [0:15];\nreg [127:0] sync_operand ;\n\ngenvar i;\ngenerate\n for(i = 0; i < 16; i = i + 1) begin\n en_t_encoder en_t_preencoder(\n .clk(clk),\n .multiplicand(sync_operand[8*(i+1)-1:8*i]),\n .cal_encode_nub(encoder_nub[i]),\n .bit_enable(bit_valid[i])\n );\n end \nendgenerate\n\nalways @(posedge clk) begin\n sync_operand <= operand_a;\n bit_enable <= bit_valid;\n partial_product_select <= encoder_nub;\nend\n\nendmodule\n\n\n\nmodule en_t_encoder(\n input clk,\n input [7:0] multiplicand, \n output reg [7:0] cal_encode_nub,\n output reg [3:0] bit_enable\n );\n\nwire [7:0] encode_input;\nwire [2:0] c_out;\nwire [7:0] encode_nub;\n\n// covert to bit_enable-Magnitude\nassign encode_input = multiplicand[7] ? ((multiplicand[6:0] == 0) ? 8'b10000000 : {1'b0,~multiplicand[6:0] + 1'b1}) : {1'b0,multiplicand[6:0]};\n\ngenvar i;\ngenerate for(i = 0; i < 4; i = i + 1) begin: gen_encode_nub \n if(i==0) begin\n assign encode_nub[1:0] = encode_input[1:0];\n end\n else if (i==1) begin\n encoder_1 en_t\n (.A(encode_input[2*i-1:2*i-2]),\n .B(encode_input[2*i+1:2*i]), \n .c_out(c_out[i]), \n .en_b(encode_nub[2*i+1:2*i])\n );\n end\n else if (i==3) begin\n encoder_3 en_t\n (.A(encode_input[2*i-1:2*i-2]),\n .c_in(c_out[i-1]), \n .B(encode_input[2*i+1:2*i]), \n .en_b(encode_nub[2*i+1:2*i])\n );\n end\n else begin\n encoder en_t\n (.A(encode_input[2*i-1:2*i-2]),\n .c_in(c_out[i-1]), \n .B(encode_input[2*i+1:2*i]), \n .c_out(c_out[i]), \n .en_b(encode_nub[2*i+1:2*i])\n );\n end \nend \nendgenerate \n\n\ngenerate \n for (i = 0 ; i < 4; i = i + 1) begin\n always @(posedge clk) begin\n if(encode_nub[2*i+1:2*i] == 2'b00) begin\n bit_enable[i] <= 0;\n cal_encode_nub[2*i+1:2*i] <= 0;\n end\n else begin\n bit_enable[i] <= 1;\n cal_encode_nub[2*i+1:2*i] <= {multiplicand[7]^encode_nub[2*i+1],encode_nub[2*i]};\n end\n end\n end\nendgenerate\n\nendmodule\n\n\nmodule encoder_1(A, B, c_out, en_b);\n\ninput wire [1:0] A;\ninput wire [1:0] B;\n \noutput wire c_out;\noutput wire [1:0] en_b;\n\nassign c_out = (A[0] & A[1]); \nassign en_b = B + c_out;\n\nendmodule\n\nmodule encoder(A, c_in, B, c_out, en_b);\n\ninput wire [1:0] A;\ninput wire c_in;\ninput wire [1:0] B;\n \noutput wire c_out;\noutput wire [1:0] en_b;\n\nassign c_out = (A[0] & A[1]) | (A[1] & c_in); \nassign en_b = B + c_out;\n\nendmodule\n\nmodule encoder_3(A, c_in, B, en_b);\n\ninput wire [1:0] A;\ninput wire c_in;\ninput wire [1:0] B;\noutput wire [1:0] en_b;\n\nwire c_out;\nassign c_out = (A[0] & A[1]) | (A[1] & c_in); \nassign en_b = B + c_out;\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_mac_based/get_pipline_mulwidth.v", "module get_pipeline_mulwidth #(\n parameter N = 4,\n parameter WIDTH = 8 \n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] signal,\n output wire [WIDTH-1:0] pipeline_signal\n);\n\n\n reg [WIDTH-1:0] pipeline_regs [N-1:0];\n\n\n genvar i;\n generate\n for (i = 0; i < N; i = i + 1) begin : pipeline_stage\n always @(posedge clk) begin\n if(~rst_n) \n pipeline_regs[i] <= 0;\n else begin\n if (i == 0) begin\n pipeline_regs[i] <= signal; \n end else begin\n pipeline_regs[i] <= pipeline_regs[i-1]; \n end\n end\n end\n end\n endgenerate\n\n\n assign pipeline_signal = pipeline_regs[N-1];\n\nendmodule\n\n\n// // 实例化 get_pipeline_mulwidth 模块\n// get_pipeline_mulwidth #(\n// .N(4), // 设置流水线深度为 4\n// .WIDTH(8) // 设置信号宽度为 8 位\n// ) pipeline_inst (\n// .clk(clk), // 连接时钟信号\n// .rst_n(rst_n), // 连接复位信号\n// .signal(input_signal), // 连接输入信号\n// .pipeline_signal(output_signal) // 连接输出信号\n// );\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/get_pipline_mulwidth.v", "module get_pipeline_mulwidth #(\n parameter N = 4,\n parameter WIDTH = 8 \n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] signal,\n output wire [WIDTH-1:0] pipeline_signal\n);\n\n\n reg [WIDTH-1:0] pipeline_regs [N-1:0];\n\n\n genvar i;\n generate\n for (i = 0; i < N; i = i + 1) begin : pipeline_stage\n always @(posedge clk) begin\n if(~rst_n) \n pipeline_regs[i] <= 0;\n else begin\n if (i == 0) begin\n pipeline_regs[i] <= signal; \n end else begin\n pipeline_regs[i] <= pipeline_regs[i-1]; \n end\n end\n end\n end\n endgenerate\n\n\n assign pipeline_signal = pipeline_regs[N-1];\n\nendmodule\n\n\n// // 实例化 get_pipeline_mulwidth 模块\n// get_pipeline_mulwidth #(\n// .N(4), // 设置流水线深度为 4\n// .WIDTH(8) // 设置信号宽度为 8 位\n// ) pipeline_inst (\n// .clk(clk), // 连接时钟信号\n// .rst_n(rst_n), // 连接复位信号\n// .signal(input_signal), // 连接输入信号\n// .pipeline_signal(output_signal) // 连接输出信号\n// );\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/get_pipline_mulwidth.v", "module get_pipeline_mulwidth #(\n parameter N = 4,\n parameter WIDTH = 8 \n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] signal,\n output wire [WIDTH-1:0] pipeline_signal\n);\n\n\n reg [WIDTH-1:0] pipeline_regs [N-1:0];\n\n\n genvar i;\n generate\n for (i = 0; i < N; i = i + 1) begin : pipeline_stage\n always @(posedge clk) begin\n if(~rst_n) \n pipeline_regs[i] <= 0;\n else begin\n if (i == 0) begin\n pipeline_regs[i] <= signal; \n end else begin\n pipeline_regs[i] <= pipeline_regs[i-1]; \n end\n end\n end\n end\n endgenerate\n\n\n assign pipeline_signal = pipeline_regs[N-1];\n\nendmodule\n\n\n// // 实例化 get_pipeline_mulwidth 模块\n// get_pipeline_mulwidth #(\n// .N(4), // 设置流水线深度为 4\n// .WIDTH(8) // 设置信号宽度为 8 位\n// ) pipeline_inst (\n// .clk(clk), // 连接时钟信号\n// .rst_n(rst_n), // 连接复位信号\n// .signal(input_signal), // 连接输入信号\n// .pipeline_signal(output_signal) // 连接输出信号\n// );\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/get_pipline_mulwidth.v", "module get_pipeline_mulwidth #(\n parameter N = 4,\n parameter WIDTH = 8 \n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] signal,\n output wire [WIDTH-1:0] pipeline_signal\n);\n\n\n reg [WIDTH-1:0] pipeline_regs [N-1:0];\n\n\n genvar i;\n generate\n for (i = 0; i < N; i = i + 1) begin : pipeline_stage\n always @(posedge clk) begin\n if(~rst_n) \n pipeline_regs[i] <= 0;\n else begin\n if (i == 0) begin\n pipeline_regs[i] <= signal; \n end else begin\n pipeline_regs[i] <= pipeline_regs[i-1]; \n end\n end\n end\n end\n endgenerate\n\n\n assign pipeline_signal = pipeline_regs[N-1];\n\nendmodule\n\n\n// // 实例化 get_pipeline_mulwidth 模块\n// get_pipeline_mulwidth #(\n// .N(4), // 设置流水线深度为 4\n// .WIDTH(8) // 设置信号宽度为 8 位\n// ) pipeline_inst (\n// .clk(clk), // 连接时钟信号\n// .rst_n(rst_n), // 连接复位信号\n// .signal(input_signal), // 连接输入信号\n// .pipeline_signal(output_signal) // 连接输出信号\n// );\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_mac_based/get_pipline_mulwidth.v", "module get_pipeline_mulwidth #(\n parameter N = 4,\n parameter WIDTH = 8 \n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] signal,\n output wire [WIDTH-1:0] pipeline_signal\n);\n\n\n reg [WIDTH-1:0] pipeline_regs [N-1:0];\n\n\n genvar i;\n generate\n for (i = 0; i < N; i = i + 1) begin : pipeline_stage\n always @(posedge clk) begin\n if(~rst_n) \n pipeline_regs[i] <= 0;\n else begin\n if (i == 0) begin\n pipeline_regs[i] <= signal; \n end else begin\n pipeline_regs[i] <= pipeline_regs[i-1]; \n end\n end\n end\n end\n endgenerate\n\n\n assign pipeline_signal = pipeline_regs[N-1];\n\nendmodule\n\n\n// // 实例化 get_pipeline_mulwidth 模块\n// get_pipeline_mulwidth #(\n// .N(4), // 设置流水线深度为 4\n// .WIDTH(8) // 设置信号宽度为 8 位\n// ) pipeline_inst (\n// .clk(clk), // 连接时钟信号\n// .rst_n(rst_n), // 连接复位信号\n// .signal(input_signal), // 连接输入信号\n// .pipeline_signal(output_signal) // 连接输出信号\n// );\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_mac_based/get_pipline_mulwidth.v", "module get_pipeline_mulwidth #(\n parameter N = 4,\n parameter WIDTH = 8 \n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] signal,\n output wire [WIDTH-1:0] pipeline_signal\n);\n\n\n reg [WIDTH-1:0] pipeline_regs [N-1:0];\n\n\n genvar i;\n generate\n for (i = 0; i < N; i = i + 1) begin : pipeline_stage\n always @(posedge clk) begin\n if(~rst_n) \n pipeline_regs[i] <= 0;\n else begin\n if (i == 0) begin\n pipeline_regs[i] <= signal; \n end else begin\n pipeline_regs[i] <= pipeline_regs[i-1]; \n end\n end\n end\n end\n endgenerate\n\n\n assign pipeline_signal = pipeline_regs[N-1];\n\nendmodule\n\n\n// // 实例化 get_pipeline_mulwidth 模块\n// get_pipeline_mulwidth #(\n// .N(4), // 设置流水线深度为 4\n// .WIDTH(8) // 设置信号宽度为 8 位\n// ) pipeline_inst (\n// .clk(clk), // 连接时钟信号\n// .rst_n(rst_n), // 连接复位信号\n// .signal(input_signal), // 连接输入信号\n// .pipeline_signal(output_signal) // 连接输出信号\n// );\n"], ["/High-Performance-Tensor-Processing-Engines/OPT3_OPT4C/pe/sparse_encoder.v", "module sparse_encoder (\n input clk,\n input rst_n,\n input [7:0] en_multiplicand,\n input [3:0] sign_en_multiplicand,\n input encode_valid,\n output reg [1:0] partial_product_index, // to sparse_pe generate partial product\n output reg [1:0] position_0, // to prefetch operand b\n output [2:0] cal_cycle // to prefetch operand a \n);\n\nwire a ;\nwire b ;\nwire c ;\nwire d ;\n\nreg [7:0] cal_en_multiplicand;\nreg [1:0] position_1 ;\nreg [1:0] position_2 ;\nreg position_3 ;\n\nassign a = en_multiplicand[0] | en_multiplicand[1];\nassign b = en_multiplicand[2] | en_multiplicand[3];\nassign c = en_multiplicand[4] | en_multiplicand[5];\nassign d = en_multiplicand[6] | en_multiplicand[7];\n\n\nassign a_b_c_d = (a) & (b) & (c) & (d);\nassign cal_cycle = {a_b_c_d,(~a & ( (b & c) | (b & d) | (c & d) )) | (a & ( (b & ~c) | (~b & d) | (c & ~d) )),(a ^ b) ^ (c ^ d)};\n\n/**********************************************/\n/******** 00 | 01 | 10 | 11 | *********/\n/******** -2B | B | 2B | -B | *********/\n/**********************************************/\ngenvar i;\ngenerate\n for (i = 0 ; i < 4 ; i = i + 1) begin : gen_cal_encoder\n always @(posedge clk or negedge rst_n) begin\n\t if (!rst_n) begin\n cal_en_multiplicand[2*(i+1)-1:2*i] <= 0;\n\t end\n\t else begin\n if(encode_valid) begin\n if(sign_en_multiplicand[i]) begin\n cal_en_multiplicand[2*(i+1)-1:2*i] <= {~en_multiplicand[2*(i+1)-1],en_multiplicand[2*i]};\n end\n else\n cal_en_multiplicand[2*(i+1)-1:2*i] <= en_multiplicand[2*(i+1)-1:2*i];\n end else\n cal_en_multiplicand[2*(i+1)-1:2*i] <= cal_en_multiplicand[2*(i+1)-1:2*i] ;\n\t end\n end\n end\nendgenerate\n \n\n\nalways @(posedge clk or negedge rst_n) begin\n if (!rst_n) begin\n position_0 <= 2'b0 ; \n position_1 <= 2'b0 ; \n position_2 <= 2'b0 ; \n position_3 <= 1'b0 ;\n end\n else begin\n if(encode_valid) begin\n position_0 <= {(~a)&(~b), (~a & (b | ~c))};\n position_1 <= {( (a ^ b) & (c | d)) | ( (~a)&(c)&(d) ), (a & b) | ( d & ( ( (a ^ b) & ~c ) | ( ~a & ~b & c ) ))};\n position_2 <= {(c & d & (a | b)) | (a & b & (c | d)), d & ( (a&b | a&c | b&c) & ~(a&b&c) )};\n position_3 <= a_b_c_d;\n end\n else begin\n position_0 <= position_1;\n position_1 <= position_2;\n position_2 <= {position_3,position_3};\n position_3 <= 0;\n end\n end\nend\n\n\nalways @(posedge clk) begin\n case(position_0) \n 2'b00: partial_product_index <= cal_en_multiplicand[1:0];\n 2'b01: partial_product_index <= cal_en_multiplicand[3:2];\n 2'b10: partial_product_index <= cal_en_multiplicand[5:4];\n 2'b11: partial_product_index <= cal_en_multiplicand[7:6];\n endcase\nend\n\nendmodule\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT2/top_tpe.sv", "module top_tpe #(\n parameter N = 32,\n localparam RESULT_WIDTH = 20\n)(\n \n input clk,\n input [127:0] operand_a,\n input weight_wen,\n input [8*N-1:0] weight_din,\n output [RESULT_WIDTH*N-1:0] result\n\n);\n\nwire [3:0] bit_enable [0:15];\nwire [7:0] partial_product_select [0:15];\nwire [3:0] bit_enable_pip [0:N-1][0:15];\nwire [7:0] partial_product_select_pip [0:N-1][0:15];\n\nvector_encoder encoder(\n .clk(clk),\n .operand_a(operand_a),\n .bit_enable(bit_enable),\n .partial_product_select(partial_product_select)\n);\n\ngenvar i;\ngenerate \n for (i = 0 ; i < N ; i = i + 1) begin\n if(i == 0) begin\n top_pe_tile pe_tile(\n .clk(clk),\n .weight_wen(weight_wen),\n .weight_din(weight_din[8*(i+1)-1:8*i]),\n .bit_enable(bit_enable),\n .partial_product_select(partial_product_select),\n .result(result[RESULT_WIDTH*(i+1)-1:RESULT_WIDTH*i]),\n .bit_enable_pip(bit_enable_pip[i]),\n .partial_product_select_pip(partial_product_select_pip[i])\n );\n end\n else begin\n top_pe_tile pe_tile(\n .clk(clk),\n .weight_wen(weight_wen),\n .weight_din(weight_din[8*(i+1)-1:8*i]),\n .bit_enable(bit_enable_pip[i-1]),\n .partial_product_select(partial_product_select_pip[i-1]),\n .result(result[RESULT_WIDTH*(i+1)-1:RESULT_WIDTH*i]),\n .bit_enable_pip(bit_enable_pip[i]),\n .partial_product_select_pip(partial_product_select_pip[i])\n );\n end\n end\nendgenerate\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT2/get_pipline_mulwidth.v", "module get_pipeline_mulwidth #(\n parameter N = 4,\n parameter WIDTH = 8 \n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] signal,\n output wire [WIDTH-1:0] pipeline_signal\n);\n\n\nreg [WIDTH-1:0] pipeline_regs [N-1:0];\n\n\n genvar i;\n generate\n for (i = 0; i < N; i = i + 1) begin : pipeline_stage\n always @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n pipeline_regs[i] <= 0; \n end else begin\n if (i == 0) begin\n pipeline_regs[i] <= signal; \n end else begin\n pipeline_regs[i] <= pipeline_regs[i-1]; \n end\n end\n end\n end\n endgenerate\n\n\n assign pipeline_signal = pipeline_regs[N-1];\n\nendmodule\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT3_OPT4C/pe/get_pipline_mulwidth.v", "module get_pipeline_mulwidth #(\n parameter N = 4,\n parameter WIDTH = 8 \n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] signal,\n output wire [WIDTH-1:0] pipeline_signal\n);\n\n\nreg [WIDTH-1:0] pipeline_regs [N-1:0];\n\n\n genvar i;\n generate\n for (i = 0; i < N; i = i + 1) begin : pipeline_stage\n always @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n pipeline_regs[i] <= 0; \n end else begin\n if (i == 0) begin\n pipeline_regs[i] <= signal; \n end else begin\n pipeline_regs[i] <= pipeline_regs[i-1]; \n end\n end\n end\n end\n endgenerate\n\n\n assign pipeline_signal = pipeline_regs[N-1];\n\nendmodule\n\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT2/partial_product_select.sv", "module partial_product_select(\n input clk,\n input [7:0] weight,\n input [3:0] bit_enable,\n input [7:0] partial_product_select,\n output signed [9:0] partial_product [0:3] \n);\n\nwire signed [8:0] inv_b;\nwire signed [7:0] b;\nwire signed [8:0] b_2;\nwire signed [8:0] b_neg;\nwire signed [9:0] b_2_neg;\nwire [1:0] cal_partial_product_select [0:3];\nreg signed [9:0] partial_product_bw [0:3]; \n\nassign cal_partial_product_select[0] = partial_product_select[1:0];\nassign cal_partial_product_select[1] = partial_product_select[3:2];\nassign cal_partial_product_select[2] = partial_product_select[5:4];\nassign cal_partial_product_select[3] = partial_product_select[7:6];\nassign partial_product = partial_product_bw;\nassign b = $signed(weight);\nassign inv_b = $signed(~b);\nassign b_2 = {b,1'b0};\nassign b_neg = inv_b + 1'b1;\nassign b_2_neg = {b_neg,1'b0};\n\ngenvar i;\ngenerate \n for (i = 0 ; i < 4; i = i + 1) begin\n always @(posedge clk) begin\n if(bit_enable[i]) begin\n case(cal_partial_product_select[i])\n 2'b00: partial_product_bw[i] <= $signed(b_2_neg);\n 2'b01: partial_product_bw[i] <= $signed(b);\n 2'b10: partial_product_bw[i] <= $signed(b_2);\n 2'b11: partial_product_bw[i] <= $signed(b_neg);\n endcase\n end\n else\n partial_product_bw[i] <= 0;\n end\n end \nendgenerate\n\nendmodule\n\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/dff_async.v", "module dff_async #(\n parameter WIDTH = 8\n)(\n input wire clk,\n input wire rst_n,\n input wire [WIDTH-1:0] d,\n output reg [WIDTH-1:0] q\n);\n\nalways @(posedge clk or negedge rst_n) begin\n if (!rst_n) begin\n q <= 0;\n end\n else begin\n q <= d;\n end\nend\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/booth_pp_gen.v", "module booth_pp_gen(\n input wire [7:0] operand_a, \n input wire [7:0] operand_b, \n output wire [9:0] pp1,\n output wire [9:0] pp2,\n output wire [9:0] pp3,\n output wire [9:0] pp4 \n );\n\n wire [1:0] operand_slice_a1 ;\n wire [2:0] operand_slice_a2 ;\n wire [2:0] operand_slice_a3 ;\n wire [2:0] operand_slice_a4 ;\n wire [8:0] operand_b_neg ;\n \n inv_converter_8 inv_converter_8_inst(\n .data_i (operand_b),\n .inv_o (operand_b_neg) \n );\n \n assign operand_slice_a1 = operand_a[1:0] ;\n assign operand_slice_a2 = operand_a[3:1] ;\n assign operand_slice_a3 = operand_a[5:3] ;\n assign operand_slice_a4 = operand_a[7:5] ;\n\n booth_partial_product_generator_pp1 ppg_1 (\n .operand_slice_a (operand_slice_a1), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp1) \n );\n\n booth_partial_product_generator ppg_2 (\n .operand_slice_a (operand_slice_a2), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp2) \n );\n\n booth_partial_product_generator ppg_3 (\n .operand_slice_a (operand_slice_a3), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp3) \n );\n\n booth_partial_product_generator ppg_4 (\n .operand_slice_a (operand_slice_a4), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp4) \n );\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/booth_pp_gen.v", "module booth_pp_gen(\n input wire [7:0] operand_a, \n input wire [7:0] operand_b, \n output wire [9:0] pp1,\n output wire [9:0] pp2,\n output wire [9:0] pp3,\n output wire [9:0] pp4 \n );\n\n wire [1:0] operand_slice_a1 ;\n wire [2:0] operand_slice_a2 ;\n wire [2:0] operand_slice_a3 ;\n wire [2:0] operand_slice_a4 ;\n wire [8:0] operand_b_neg ;\n \n inv_converter_8 inv_converter_8_inst(\n .data_i (operand_b),\n .inv_o (operand_b_neg) \n );\n \n assign operand_slice_a1 = operand_a[1:0] ;\n assign operand_slice_a2 = operand_a[3:1] ;\n assign operand_slice_a3 = operand_a[5:3] ;\n assign operand_slice_a4 = operand_a[7:5] ;\n\n booth_partial_product_generator_pp1 ppg_1 (\n .operand_slice_a (operand_slice_a1), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp1) \n );\n\n booth_partial_product_generator ppg_2 (\n .operand_slice_a (operand_slice_a2), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp2) \n );\n\n booth_partial_product_generator ppg_3 (\n .operand_slice_a (operand_slice_a3), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp3) \n );\n\n booth_partial_product_generator ppg_4 (\n .operand_slice_a (operand_slice_a4), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp4) \n );\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/booth_pp_gen.v", "module booth_pp_gen(\n input wire [7:0] operand_a, \n input wire [7:0] operand_b, \n output wire [9:0] pp1,\n output wire [9:0] pp2,\n output wire [9:0] pp3,\n output wire [9:0] pp4 \n );\n\n wire [1:0] operand_slice_a1 ;\n wire [2:0] operand_slice_a2 ;\n wire [2:0] operand_slice_a3 ;\n wire [2:0] operand_slice_a4 ;\n wire [8:0] operand_b_neg ;\n \n inv_converter_8 inv_converter_8_inst(\n .data_i (operand_b),\n .inv_o (operand_b_neg) \n );\n \n assign operand_slice_a1 = operand_a[1:0] ;\n assign operand_slice_a2 = operand_a[3:1] ;\n assign operand_slice_a3 = operand_a[5:3] ;\n assign operand_slice_a4 = operand_a[7:5] ;\n\n booth_partial_product_generator_pp1 ppg_1 (\n .operand_slice_a (operand_slice_a1), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp1) \n );\n\n booth_partial_product_generator ppg_2 (\n .operand_slice_a (operand_slice_a2), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp2) \n );\n\n booth_partial_product_generator ppg_3 (\n .operand_slice_a (operand_slice_a3), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp3) \n );\n\n booth_partial_product_generator ppg_4 (\n .operand_slice_a (operand_slice_a4), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp4) \n );\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/booth_pp_gen.v", "module booth_pp_gen(\n input wire [7:0] operand_a, \n input wire [7:0] operand_b, \n output wire [9:0] pp1,\n output wire [9:0] pp2,\n output wire [9:0] pp3,\n output wire [9:0] pp4 \n );\n\n wire [1:0] operand_slice_a1 ;\n wire [2:0] operand_slice_a2 ;\n wire [2:0] operand_slice_a3 ;\n wire [2:0] operand_slice_a4 ;\n wire [8:0] operand_b_neg ;\n \n inv_converter_8 inv_converter_8_inst(\n .data_i (operand_b),\n .inv_o (operand_b_neg) \n );\n \n assign operand_slice_a1 = operand_a[1:0] ;\n assign operand_slice_a2 = operand_a[3:1] ;\n assign operand_slice_a3 = operand_a[5:3] ;\n assign operand_slice_a4 = operand_a[7:5] ;\n\n booth_partial_product_generator_pp1 ppg_1 (\n .operand_slice_a (operand_slice_a1), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp1) \n );\n\n booth_partial_product_generator ppg_2 (\n .operand_slice_a (operand_slice_a2), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp2) \n );\n\n booth_partial_product_generator ppg_3 (\n .operand_slice_a (operand_slice_a3), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp3) \n );\n\n booth_partial_product_generator ppg_4 (\n .operand_slice_a (operand_slice_a4), \n .operand_b (operand_b), \n .operand_b_neg (operand_b_neg), \n .pp_out (pp4) \n );\n\nendmodule\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/inv_conveter_8.v", "// 取反 加1 （-1*A、-2*A 都要进行取反加1）\nmodule inv_converter_8(\n input wire [7:0] data_i ,\n output wire[8:0] inv_o \n );\n \n wire [5:0] wire_cout ; \n wire not_o ; \n\n assign inv_o[0] = data_i[0];\n \n inv_unit inv_unit_bit1(\n .a (data_i[1] ),\n .b (data_i[0] ),\n .xor_o (inv_o[1] ), \n .or_o (wire_cout[0] ) \n );\n \n genvar i;\n generate \n for(i=2;i<=5;i=i+1) begin\n inv_unit inv_unit_inst(\n .a (data_i[i] ),\n .b (wire_cout[i-2] ),\n .xor_o (inv_o[i] ), \n .or_o (wire_cout[i-1] ) \n );\n end\n endgenerate\n \n inv_unit_nor_out inv_unit_nor_out_inst_6(\n .a (data_i[6] ),\n .b (wire_cout[4] ),\n .xor_o (inv_o[6] ), \n .nor_o (wire_cout[5] ) \n );\n \n inv_unit_nor_out inv_unit_nor_out_inst_7(\n .a (data_i[7] ),\n .b (not_o ), \n .xor_o (inv_o[7] ), \n .nor_o ( ) \n );\n \n \n\n assign not_o = ~wire_cout[5] ;\n \n\n assign inv_o[8] = ~(wire_cout[5] | data_i[7]);\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/inv_conveter_8.v", "// 取反 加1 （-1*A、-2*A 都要进行取反加1）\nmodule inv_converter_8(\n input wire [7:0] data_i ,\n output wire[8:0] inv_o \n );\n \n wire [5:0] wire_cout ; \n wire not_o ; \n\n assign inv_o[0] = data_i[0];\n \n inv_unit inv_unit_bit1(\n .a (data_i[1] ),\n .b (data_i[0] ),\n .xor_o (inv_o[1] ), \n .or_o (wire_cout[0] ) \n );\n \n genvar i;\n generate \n for(i=2;i<=5;i=i+1) begin\n inv_unit inv_unit_inst(\n .a (data_i[i] ),\n .b (wire_cout[i-2] ),\n .xor_o (inv_o[i] ), \n .or_o (wire_cout[i-1] ) \n );\n end\n endgenerate\n \n inv_unit_nor_out inv_unit_nor_out_inst_6(\n .a (data_i[6] ),\n .b (wire_cout[4] ),\n .xor_o (inv_o[6] ), \n .nor_o (wire_cout[5] ) \n );\n \n inv_unit_nor_out inv_unit_nor_out_inst_7(\n .a (data_i[7] ),\n .b (not_o ), \n .xor_o (inv_o[7] ), \n .nor_o ( ) \n );\n \n \n\n assign not_o = ~wire_cout[5] ;\n \n\n assign inv_o[8] = ~(wire_cout[5] | data_i[7]);\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/inv_conveter_8.v", "// 取反 加1 （-1*A、-2*A 都要进行取反加1）\nmodule inv_converter_8(\n input wire [7:0] data_i ,\n output wire[8:0] inv_o \n );\n \n wire [5:0] wire_cout ; \n wire not_o ; \n\n assign inv_o[0] = data_i[0];\n \n inv_unit inv_unit_bit1(\n .a (data_i[1] ),\n .b (data_i[0] ),\n .xor_o (inv_o[1] ), \n .or_o (wire_cout[0] ) \n );\n \n genvar i;\n generate \n for(i=2;i<=5;i=i+1) begin\n inv_unit inv_unit_inst(\n .a (data_i[i] ),\n .b (wire_cout[i-2] ),\n .xor_o (inv_o[i] ), \n .or_o (wire_cout[i-1] ) \n );\n end\n endgenerate\n \n inv_unit_nor_out inv_unit_nor_out_inst_6(\n .a (data_i[6] ),\n .b (wire_cout[4] ),\n .xor_o (inv_o[6] ), \n .nor_o (wire_cout[5] ) \n );\n \n inv_unit_nor_out inv_unit_nor_out_inst_7(\n .a (data_i[7] ),\n .b (not_o ), \n .xor_o (inv_o[7] ), \n .nor_o ( ) \n );\n \n \n\n assign not_o = ~wire_cout[5] ;\n \n\n assign inv_o[8] = ~(wire_cout[5] | data_i[7]);\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/inv_conveter_8.v", "module inv_converter_8(\n input wire [7:0] data_i ,\n output wire[8:0] inv_o \n );\n \n wire [5:0] wire_cout ; \n wire not_o ; \n\n assign inv_o[0] = data_i[0];\n \n inv_unit inv_unit_bit1(\n .a (data_i[1] ),\n .b (data_i[0] ),\n .xor_o (inv_o[1] ), \n .or_o (wire_cout[0] ) \n );\n \n genvar i;\n generate \n for(i=2;i<=5;i=i+1) begin\n inv_unit inv_unit_inst(\n .a (data_i[i] ),\n .b (wire_cout[i-2] ),\n .xor_o (inv_o[i] ), \n .or_o (wire_cout[i-1] ) \n );\n end\n endgenerate\n \n inv_unit_nor_out inv_unit_nor_out_inst_6(\n .a (data_i[6] ),\n .b (wire_cout[4] ),\n .xor_o (inv_o[6] ), \n .nor_o (wire_cout[5] ) \n );\n \n inv_unit_nor_out inv_unit_nor_out_inst_7(\n .a (data_i[7] ),\n .b (not_o ), \n .xor_o (inv_o[7] ), \n .nor_o ( ) \n );\n \n \n\n assign not_o = ~wire_cout[5] ;\n \n\n assign inv_o[8] = ~(wire_cout[5] | data_i[7]);\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT3_OPT4C/pe/get_negedge.sv", "module get_negedge(\n input clk,\n input signal,\n output negedge_signal\n );\n\nreg save;\n\nalways @(posedge clk) begin\n save <= signal;\nend\n\nassign negedge_signal = ~signal & save;\n\nendmodule\n\n// get_negedge get_hit(\n// .clk(clk),\n// .signal(cache_hit),\n// .negedge_signal(negedge_cache_hit)\n// );"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/DW02_tree.sv", "////////////////////////////////////////////////////////////////////////////////\n//\n// This confidential and proprietary software may be used only\n// as authorized by a licensing agreement from Synopsys Inc.\n// In the event of publication, the following notice is applicable:\n//\n// (C) COPYRIGHT 2000 - 2021 SYNOPSYS INC.\n// ALL RIGHTS RESERVED\n//\n// The entire notice above must be reproduced on all authorized\n// copies.\n//\n// AUTHOR: Rick Kelly 07/28/2000\n//\n// VERSION: Verilog Simulation Model for DW02_tree\n//\n// DesignWare_version: aacb4808\n// DesignWare_release: S-2021.06-DWBB_202106.4\n//\n////////////////////////////////////////////////////////////////////////////////\n\n//-----------------------------------------------------------------------------------\n//\n// ABSTRACT: Wallace Tree Summer with Carry Save output\n//\n// MODIFIED:\n// Aamir Farooqui 7/11/02\n// Corrected parameter checking, simplied sim model, and X_processing\n//\n//------------------------------------------------------------------------------\n//\n\n // synopsys translate_off\n// `ifdef VCS\n// `include \"DW02_tree.v\"\n// `else\n // synopsys translate_on\n\nmodule DW02_tree( INPUT, OUT0, OUT1 );\n\n// parameters\nparameter integer num_inputs = 8;\nparameter integer input_width = 8;\nparameter integer verif_en = 1;\n\n//-----------------------------------------------------------------------------\n// ports\ninput [num_inputs*input_width-1 : 0]\tINPUT;\noutput [input_width-1:0]\t\tOUT0, OUT1;\n\n//-----------------------------------------------------------------------------\n// synopsys translate_off\nreg [input_width-1:0]\t\tOII0OOOI, O001l0I0;\n\n//-----------------------------------------------------------------------------\n \n \n// initial begin : parameter_check\n// integer param_err_flg;\n\n// param_err_flg = 0;\n \n \n// if (num_inputs < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter num_inputs (lower bound: 1)\",\n// \tnum_inputs );\n// end\n \n// if (input_width < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter input_width (lower bound: 1)\",\n// \tinput_width );\n// end\n \n// if ( (verif_en < 0) || (verif_en > 1) ) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter verif_en (legal range: 0 to 1)\",\n// \tverif_en );\n// end\n \n// if ( param_err_flg == 1) begin\n// $display(\n// \"%m :\\n Simulation aborted due to invalid parameter value(s)\");\n// $finish;\n// end\n\n// end // parameter_check \n\n\n// `ifndef DW_SUPPRESS_WARN\n// initial begin : verif_en_warning\n// $display(\"The parameter verif_en is set to 0 for this simulator.\\nOther values for verif_en are enabled only for VCS.\");\n// end // verif_en_warning\n// `endif\n\n//-----------------------------------------------------------------------------\n\n\n\nalways @ (INPUT) begin : IIIIO1Ol\n reg [input_width-1 : 0] I0lII01I [0 : num_inputs-1];\n reg [input_width-1 : 0] l10III00 [0 : num_inputs-1];\n reg [input_width-1 : 0] IIIO00Ol, lI0OII0O;\n integer I1I1O00I, O1OIIOII, IlI01lIO;\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII=O1OIIOII+1) begin\n for (IlI01lIO=0 ; IlI01lIO < input_width ; IlI01lIO=IlI01lIO+1) begin\n IIIO00Ol[IlI01lIO] = INPUT[O1OIIOII*input_width+IlI01lIO];\n end // for IlI01lIO\n I0lII01I[O1OIIOII] = IIIO00Ol;\n end // for O1OIIOII\n\n I1I1O00I = num_inputs;\n\n while (I1I1O00I > 2)\n begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I/3) ; O1OIIOII = O1OIIOII+1) begin\n l10III00[O1OIIOII*2] = I0lII01I[O1OIIOII*3] ^ I0lII01I[O1OIIOII*3+1] ^ I0lII01I[O1OIIOII*3+2];\n\n lI0OII0O = (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+1]) |\n (I0lII01I[O1OIIOII*3+1] & I0lII01I[O1OIIOII*3+2]) |\n (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+2]);\n\n l10III00[O1OIIOII*2+1] = lI0OII0O << 1;\n end\n if ((I1I1O00I % 3) > 0) begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I % 3) ; O1OIIOII = O1OIIOII + 1)\n l10III00[2 * (I1I1O00I/3) + O1OIIOII] = I0lII01I[3 * (I1I1O00I/3) + O1OIIOII];\n end\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII = O1OIIOII + 1)\n I0lII01I[O1OIIOII] = l10III00[O1OIIOII];\n I1I1O00I = I1I1O00I - (I1I1O00I/3);\n end\n OII0OOOI = I0lII01I[0];\n if (I1I1O00I > 1)\n O001l0I0 = I0lII01I[1];\n else\n O001l0I0 = {input_width{1'b0}};\nend // IIIIO1Ol\n\n\nassign OUT0 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : OII0OOOI;\nassign OUT1 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : O001l0I0;\n\n// synopsys translate_on\n\nendmodule\n // synopsys translate_off\n// `endif\n // synopsys translate_on\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/DW02_tree.sv", "////////////////////////////////////////////////////////////////////////////////\n//\n// This confidential and proprietary software may be used only\n// as authorized by a licensing agreement from Synopsys Inc.\n// In the event of publication, the following notice is applicable:\n//\n// (C) COPYRIGHT 2000 - 2021 SYNOPSYS INC.\n// ALL RIGHTS RESERVED\n//\n// The entire notice above must be reproduced on all authorized\n// copies.\n//\n// AUTHOR: Rick Kelly 07/28/2000\n//\n// VERSION: Verilog Simulation Model for DW02_tree\n//\n// DesignWare_version: aacb4808\n// DesignWare_release: S-2021.06-DWBB_202106.4\n//\n////////////////////////////////////////////////////////////////////////////////\n\n//-----------------------------------------------------------------------------------\n//\n// ABSTRACT: Wallace Tree Summer with Carry Save output\n//\n// MODIFIED:\n// Aamir Farooqui 7/11/02\n// Corrected parameter checking, simplied sim model, and X_processing\n//\n//------------------------------------------------------------------------------\n//\n\n // synopsys translate_off\n// `ifdef VCS\n// `include \"DW02_tree.v\"\n// `else\n // synopsys translate_on\n\nmodule DW02_tree( INPUT, OUT0, OUT1 );\n\n// parameters\nparameter integer num_inputs = 8;\nparameter integer input_width = 8;\nparameter integer verif_en = 1;\n\n//-----------------------------------------------------------------------------\n// ports\ninput [num_inputs*input_width-1 : 0]\tINPUT;\noutput [input_width-1:0]\t\tOUT0, OUT1;\n\n//-----------------------------------------------------------------------------\n// synopsys translate_off\nreg [input_width-1:0]\t\tOII0OOOI, O001l0I0;\n\n//-----------------------------------------------------------------------------\n \n \n// initial begin : parameter_check\n// integer param_err_flg;\n\n// param_err_flg = 0;\n \n \n// if (num_inputs < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter num_inputs (lower bound: 1)\",\n// \tnum_inputs );\n// end\n \n// if (input_width < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter input_width (lower bound: 1)\",\n// \tinput_width );\n// end\n \n// if ( (verif_en < 0) || (verif_en > 1) ) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter verif_en (legal range: 0 to 1)\",\n// \tverif_en );\n// end\n \n// if ( param_err_flg == 1) begin\n// $display(\n// \"%m :\\n Simulation aborted due to invalid parameter value(s)\");\n// $finish;\n// end\n\n// end // parameter_check \n\n\n// `ifndef DW_SUPPRESS_WARN\n// initial begin : verif_en_warning\n// $display(\"The parameter verif_en is set to 0 for this simulator.\\nOther values for verif_en are enabled only for VCS.\");\n// end // verif_en_warning\n// `endif\n\n//-----------------------------------------------------------------------------\n\n\n\nalways @ (INPUT) begin : IIIIO1Ol\n reg [input_width-1 : 0] I0lII01I [0 : num_inputs-1];\n reg [input_width-1 : 0] l10III00 [0 : num_inputs-1];\n reg [input_width-1 : 0] IIIO00Ol, lI0OII0O;\n integer I1I1O00I, O1OIIOII, IlI01lIO;\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII=O1OIIOII+1) begin\n for (IlI01lIO=0 ; IlI01lIO < input_width ; IlI01lIO=IlI01lIO+1) begin\n IIIO00Ol[IlI01lIO] = INPUT[O1OIIOII*input_width+IlI01lIO];\n end // for IlI01lIO\n I0lII01I[O1OIIOII] = IIIO00Ol;\n end // for O1OIIOII\n\n I1I1O00I = num_inputs;\n\n while (I1I1O00I > 2)\n begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I/3) ; O1OIIOII = O1OIIOII+1) begin\n l10III00[O1OIIOII*2] = I0lII01I[O1OIIOII*3] ^ I0lII01I[O1OIIOII*3+1] ^ I0lII01I[O1OIIOII*3+2];\n\n lI0OII0O = (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+1]) |\n (I0lII01I[O1OIIOII*3+1] & I0lII01I[O1OIIOII*3+2]) |\n (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+2]);\n\n l10III00[O1OIIOII*2+1] = lI0OII0O << 1;\n end\n if ((I1I1O00I % 3) > 0) begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I % 3) ; O1OIIOII = O1OIIOII + 1)\n l10III00[2 * (I1I1O00I/3) + O1OIIOII] = I0lII01I[3 * (I1I1O00I/3) + O1OIIOII];\n end\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII = O1OIIOII + 1)\n I0lII01I[O1OIIOII] = l10III00[O1OIIOII];\n I1I1O00I = I1I1O00I - (I1I1O00I/3);\n end\n OII0OOOI = I0lII01I[0];\n if (I1I1O00I > 1)\n O001l0I0 = I0lII01I[1];\n else\n O001l0I0 = {input_width{1'b0}};\nend // IIIIO1Ol\n\n\nassign OUT0 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : OII0OOOI;\nassign OUT1 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : O001l0I0;\n\n// synopsys translate_on\n\nendmodule\n // synopsys translate_off\n// `endif\n // synopsys translate_on\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/DW02_tree.sv", "////////////////////////////////////////////////////////////////////////////////\n//\n// This confidential and proprietary software may be used only\n// as authorized by a licensing agreement from Synopsys Inc.\n// In the event of publication, the following notice is applicable:\n//\n// (C) COPYRIGHT 2000 - 2021 SYNOPSYS INC.\n// ALL RIGHTS RESERVED\n//\n// The entire notice above must be reproduced on all authorized\n// copies.\n//\n// AUTHOR: Rick Kelly 07/28/2000\n//\n// VERSION: Verilog Simulation Model for DW02_tree\n//\n// DesignWare_version: aacb4808\n// DesignWare_release: S-2021.06-DWBB_202106.4\n//\n////////////////////////////////////////////////////////////////////////////////\n\n//-----------------------------------------------------------------------------------\n//\n// ABSTRACT: Wallace Tree Summer with Carry Save output\n//\n// MODIFIED:\n// Aamir Farooqui 7/11/02\n// Corrected parameter checking, simplied sim model, and X_processing\n//\n//------------------------------------------------------------------------------\n//\n\n // synopsys translate_off\n// `ifdef VCS\n// `include \"DW02_tree.v\"\n// `else\n // synopsys translate_on\n\nmodule DW02_tree( INPUT, OUT0, OUT1 );\n\n// parameters\nparameter integer num_inputs = 8;\nparameter integer input_width = 8;\nparameter integer verif_en = 1;\n\n//-----------------------------------------------------------------------------\n// ports\ninput [num_inputs*input_width-1 : 0]\tINPUT;\noutput [input_width-1:0]\t\tOUT0, OUT1;\n\n//-----------------------------------------------------------------------------\n// synopsys translate_off\nreg [input_width-1:0]\t\tOII0OOOI, O001l0I0;\n\n//-----------------------------------------------------------------------------\n \n \n// initial begin : parameter_check\n// integer param_err_flg;\n\n// param_err_flg = 0;\n \n \n// if (num_inputs < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter num_inputs (lower bound: 1)\",\n// \tnum_inputs );\n// end\n \n// if (input_width < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter input_width (lower bound: 1)\",\n// \tinput_width );\n// end\n \n// if ( (verif_en < 0) || (verif_en > 1) ) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter verif_en (legal range: 0 to 1)\",\n// \tverif_en );\n// end\n \n// if ( param_err_flg == 1) begin\n// $display(\n// \"%m :\\n Simulation aborted due to invalid parameter value(s)\");\n// $finish;\n// end\n\n// end // parameter_check \n\n\n// `ifndef DW_SUPPRESS_WARN\n// initial begin : verif_en_warning\n// $display(\"The parameter verif_en is set to 0 for this simulator.\\nOther values for verif_en are enabled only for VCS.\");\n// end // verif_en_warning\n// `endif\n\n//-----------------------------------------------------------------------------\n\n\n\nalways @ (INPUT) begin : IIIIO1Ol\n reg [input_width-1 : 0] I0lII01I [0 : num_inputs-1];\n reg [input_width-1 : 0] l10III00 [0 : num_inputs-1];\n reg [input_width-1 : 0] IIIO00Ol, lI0OII0O;\n integer I1I1O00I, O1OIIOII, IlI01lIO;\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII=O1OIIOII+1) begin\n for (IlI01lIO=0 ; IlI01lIO < input_width ; IlI01lIO=IlI01lIO+1) begin\n IIIO00Ol[IlI01lIO] = INPUT[O1OIIOII*input_width+IlI01lIO];\n end // for IlI01lIO\n I0lII01I[O1OIIOII] = IIIO00Ol;\n end // for O1OIIOII\n\n I1I1O00I = num_inputs;\n\n while (I1I1O00I > 2)\n begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I/3) ; O1OIIOII = O1OIIOII+1) begin\n l10III00[O1OIIOII*2] = I0lII01I[O1OIIOII*3] ^ I0lII01I[O1OIIOII*3+1] ^ I0lII01I[O1OIIOII*3+2];\n\n lI0OII0O = (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+1]) |\n (I0lII01I[O1OIIOII*3+1] & I0lII01I[O1OIIOII*3+2]) |\n (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+2]);\n\n l10III00[O1OIIOII*2+1] = lI0OII0O << 1;\n end\n if ((I1I1O00I % 3) > 0) begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I % 3) ; O1OIIOII = O1OIIOII + 1)\n l10III00[2 * (I1I1O00I/3) + O1OIIOII] = I0lII01I[3 * (I1I1O00I/3) + O1OIIOII];\n end\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII = O1OIIOII + 1)\n I0lII01I[O1OIIOII] = l10III00[O1OIIOII];\n I1I1O00I = I1I1O00I - (I1I1O00I/3);\n end\n OII0OOOI = I0lII01I[0];\n if (I1I1O00I > 1)\n O001l0I0 = I0lII01I[1];\n else\n O001l0I0 = {input_width{1'b0}};\nend // IIIIO1Ol\n\n\nassign OUT0 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : OII0OOOI;\nassign OUT1 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : O001l0I0;\n\n// synopsys translate_on\n\nendmodule\n // synopsys translate_off\n// `endif\n // synopsys translate_on\n"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/DW02_tree.sv", "//-----------------------------------------------------------------------------------\n//\n// ABSTRACT: Wallace Tree Summer with Carry Save output\n//\n//------------------------------------------------------------------------------\n//\n\n // synopsys translate_off\n// `ifdef VCS\n// `include \"DW02_tree.v\"\n// `else\n // synopsys translate_on\n\nmodule DW02_tree( INPUT, OUT0, OUT1 );\n\n// parameters\nparameter integer num_inputs = 8;\nparameter integer input_width = 8;\nparameter integer verif_en = 1;\n\n//-----------------------------------------------------------------------------\n// ports\ninput [num_inputs*input_width-1 : 0]\tINPUT;\noutput [input_width-1:0]\t\tOUT0, OUT1;\n\n//-----------------------------------------------------------------------------\n// synopsys translate_off\nreg [input_width-1:0]\t\tOII0OOOI, O001l0I0;\n\n//-----------------------------------------------------------------------------\n \n \n// initial begin : parameter_check\n// integer param_err_flg;\n\n// param_err_flg = 0;\n \n \n// if (num_inputs < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter num_inputs (lower bound: 1)\",\n// \tnum_inputs );\n// end\n \n// if (input_width < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter input_width (lower bound: 1)\",\n// \tinput_width );\n// end\n \n// if ( (verif_en < 0) || (verif_en > 1) ) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter verif_en (legal range: 0 to 1)\",\n// \tverif_en );\n// end\n \n// if ( param_err_flg == 1) begin\n// $display(\n// \"%m :\\n Simulation aborted due to invalid parameter value(s)\");\n// $finish;\n// end\n\n// end // parameter_check \n\n\n// `ifndef DW_SUPPRESS_WARN\n// initial begin : verif_en_warning\n// $display(\"The parameter verif_en is set to 0 for this simulator.\\nOther values for verif_en are enabled only for VCS.\");\n// end // verif_en_warning\n// `endif\n\n//-----------------------------------------------------------------------------\n\n\n\nalways @ (INPUT) begin : IIIIO1Ol\n reg [input_width-1 : 0] I0lII01I [0 : num_inputs-1];\n reg [input_width-1 : 0] l10III00 [0 : num_inputs-1];\n reg [input_width-1 : 0] IIIO00Ol, lI0OII0O;\n integer I1I1O00I, O1OIIOII, IlI01lIO;\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII=O1OIIOII+1) begin\n for (IlI01lIO=0 ; IlI01lIO < input_width ; IlI01lIO=IlI01lIO+1) begin\n IIIO00Ol[IlI01lIO] = INPUT[O1OIIOII*input_width+IlI01lIO];\n end // for IlI01lIO\n I0lII01I[O1OIIOII] = IIIO00Ol;\n end // for O1OIIOII\n\n I1I1O00I = num_inputs;\n\n while (I1I1O00I > 2)\n begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I/3) ; O1OIIOII = O1OIIOII+1) begin\n l10III00[O1OIIOII*2] = I0lII01I[O1OIIOII*3] ^ I0lII01I[O1OIIOII*3+1] ^ I0lII01I[O1OIIOII*3+2];\n\n lI0OII0O = (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+1]) |\n (I0lII01I[O1OIIOII*3+1] & I0lII01I[O1OIIOII*3+2]) |\n (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+2]);\n\n l10III00[O1OIIOII*2+1] = lI0OII0O << 1;\n end\n if ((I1I1O00I % 3) > 0) begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I % 3) ; O1OIIOII = O1OIIOII + 1)\n l10III00[2 * (I1I1O00I/3) + O1OIIOII] = I0lII01I[3 * (I1I1O00I/3) + O1OIIOII];\n end\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII = O1OIIOII + 1)\n I0lII01I[O1OIIOII] = l10III00[O1OIIOII];\n I1I1O00I = I1I1O00I - (I1I1O00I/3);\n end\n OII0OOOI = I0lII01I[0];\n if (I1I1O00I > 1)\n O001l0I0 = I0lII01I[1];\n else\n O001l0I0 = {input_width{1'b0}};\nend // IIIIO1Ol\n\n\nassign OUT0 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : OII0OOOI;\nassign OUT1 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : O001l0I0;\n\n// synopsys translate_on\n\nendmodule\n // synopsys translate_off\n// `endif\n // synopsys translate_on\n"], ["/High-Performance-Tensor-Processing-Engines/OPT3_OPT4C/pe/DW02_tree.sv", "//-----------------------------------------------------------------------------------\n//\n// ABSTRACT: Wallace Tree Summer with Carry Save output\n//\n//------------------------------------------------------------------------------\n//\n\n // synopsys translate_off\n// `ifdef VCS\n// `include \"DW02_tree.v\"\n// `else\n // synopsys translate_on\n\nmodule DW02_tree( INPUT, OUT0, OUT1 );\n\n// parameters\nparameter integer num_inputs = 8;\nparameter integer input_width = 8;\nparameter integer verif_en = 1;\n\n//-----------------------------------------------------------------------------\n// ports\ninput [num_inputs*input_width-1 : 0]\tINPUT;\noutput [input_width-1:0]\t\tOUT0, OUT1;\n\n//-----------------------------------------------------------------------------\n// synopsys translate_off\nreg [input_width-1:0]\t\tOII0OOOI, O001l0I0;\n\n//-----------------------------------------------------------------------------\n \n \n// initial begin : parameter_check\n// integer param_err_flg;\n\n// param_err_flg = 0;\n \n \n// if (num_inputs < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter num_inputs (lower bound: 1)\",\n// \tnum_inputs );\n// end\n \n// if (input_width < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter input_width (lower bound: 1)\",\n// \tinput_width );\n// end\n \n// if ( (verif_en < 0) || (verif_en > 1) ) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter verif_en (legal range: 0 to 1)\",\n// \tverif_en );\n// end\n \n// if ( param_err_flg == 1) begin\n// $display(\n// \"%m :\\n Simulation aborted due to invalid parameter value(s)\");\n// $finish;\n// end\n\n// end // parameter_check \n\n\n// `ifndef DW_SUPPRESS_WARN\n// initial begin : verif_en_warning\n// $display(\"The parameter verif_en is set to 0 for this simulator.\\nOther values for verif_en are enabled only for VCS.\");\n// end // verif_en_warning\n// `endif\n\n//-----------------------------------------------------------------------------\n\n\n\nalways @ (INPUT) begin : IIIIO1Ol\n reg [input_width-1 : 0] I0lII01I [0 : num_inputs-1];\n reg [input_width-1 : 0] l10III00 [0 : num_inputs-1];\n reg [input_width-1 : 0] IIIO00Ol, lI0OII0O;\n integer I1I1O00I, O1OIIOII, IlI01lIO;\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII=O1OIIOII+1) begin\n for (IlI01lIO=0 ; IlI01lIO < input_width ; IlI01lIO=IlI01lIO+1) begin\n IIIO00Ol[IlI01lIO] = INPUT[O1OIIOII*input_width+IlI01lIO];\n end // for IlI01lIO\n I0lII01I[O1OIIOII] = IIIO00Ol;\n end // for O1OIIOII\n\n I1I1O00I = num_inputs;\n\n while (I1I1O00I > 2)\n begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I/3) ; O1OIIOII = O1OIIOII+1) begin\n l10III00[O1OIIOII*2] = I0lII01I[O1OIIOII*3] ^ I0lII01I[O1OIIOII*3+1] ^ I0lII01I[O1OIIOII*3+2];\n\n lI0OII0O = (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+1]) |\n (I0lII01I[O1OIIOII*3+1] & I0lII01I[O1OIIOII*3+2]) |\n (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+2]);\n\n l10III00[O1OIIOII*2+1] = lI0OII0O << 1;\n end\n if ((I1I1O00I % 3) > 0) begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I % 3) ; O1OIIOII = O1OIIOII + 1)\n l10III00[2 * (I1I1O00I/3) + O1OIIOII] = I0lII01I[3 * (I1I1O00I/3) + O1OIIOII];\n end\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII = O1OIIOII + 1)\n I0lII01I[O1OIIOII] = l10III00[O1OIIOII];\n I1I1O00I = I1I1O00I - (I1I1O00I/3);\n end\n OII0OOOI = I0lII01I[0];\n if (I1I1O00I > 1)\n O001l0I0 = I0lII01I[1];\n else\n O001l0I0 = {input_width{1'b0}};\nend // IIIIO1Ol\n\n\nassign OUT0 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : OII0OOOI;\nassign OUT1 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : O001l0I0;\n\n// synopsys translate_on\n\nendmodule\n // synopsys translate_off\n// `endif\n // synopsys translate_on\n"], ["/High-Performance-Tensor-Processing-Engines/OPT2/DW02_tree.sv", "//-----------------------------------------------------------------------------------\n//\n// ABSTRACT: Wallace Tree Summer with Carry Save output\n//\n//------------------------------------------------------------------------------\n//\n\n // synopsys translate_off\n// `ifdef VCS\n// `include \"DW02_tree.v\"\n// `else\n // synopsys translate_on\n\nmodule DW02_tree( INPUT, OUT0, OUT1 );\n\n// parameters\nparameter integer num_inputs = 8;\nparameter integer input_width = 8;\nparameter integer verif_en = 1;\n\n//-----------------------------------------------------------------------------\n// ports\ninput [num_inputs*input_width-1 : 0]\tINPUT;\noutput [input_width-1:0]\t\tOUT0, OUT1;\n\n//-----------------------------------------------------------------------------\n// synopsys translate_off\nreg [input_width-1:0]\t\tOII0OOOI, O001l0I0;\n\n//-----------------------------------------------------------------------------\n \n \n// initial begin : parameter_check\n// integer param_err_flg;\n\n// param_err_flg = 0;\n \n \n// if (num_inputs < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter num_inputs (lower bound: 1)\",\n// \tnum_inputs );\n// end\n \n// if (input_width < 1) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter input_width (lower bound: 1)\",\n// \tinput_width );\n// end\n \n// if ( (verif_en < 0) || (verif_en > 1) ) begin\n// param_err_flg = 1;\n// $display(\n// \t\"ERROR: %m :\\n Invalid value (%d) for parameter verif_en (legal range: 0 to 1)\",\n// \tverif_en );\n// end\n \n// if ( param_err_flg == 1) begin\n// $display(\n// \"%m :\\n Simulation aborted due to invalid parameter value(s)\");\n// $finish;\n// end\n\n// end // parameter_check \n\n\n// `ifndef DW_SUPPRESS_WARN\n// initial begin : verif_en_warning\n// $display(\"The parameter verif_en is set to 0 for this simulator.\\nOther values for verif_en are enabled only for VCS.\");\n// end // verif_en_warning\n// `endif\n\n//-----------------------------------------------------------------------------\n\n\n\nalways @ (INPUT) begin : IIIIO1Ol\n reg [input_width-1 : 0] I0lII01I [0 : num_inputs-1];\n reg [input_width-1 : 0] l10III00 [0 : num_inputs-1];\n reg [input_width-1 : 0] IIIO00Ol, lI0OII0O;\n integer I1I1O00I, O1OIIOII, IlI01lIO;\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII=O1OIIOII+1) begin\n for (IlI01lIO=0 ; IlI01lIO < input_width ; IlI01lIO=IlI01lIO+1) begin\n IIIO00Ol[IlI01lIO] = INPUT[O1OIIOII*input_width+IlI01lIO];\n end // for IlI01lIO\n I0lII01I[O1OIIOII] = IIIO00Ol;\n end // for O1OIIOII\n\n I1I1O00I = num_inputs;\n\n while (I1I1O00I > 2)\n begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I/3) ; O1OIIOII = O1OIIOII+1) begin\n l10III00[O1OIIOII*2] = I0lII01I[O1OIIOII*3] ^ I0lII01I[O1OIIOII*3+1] ^ I0lII01I[O1OIIOII*3+2];\n\n lI0OII0O = (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+1]) |\n (I0lII01I[O1OIIOII*3+1] & I0lII01I[O1OIIOII*3+2]) |\n (I0lII01I[O1OIIOII*3] & I0lII01I[O1OIIOII*3+2]);\n\n l10III00[O1OIIOII*2+1] = lI0OII0O << 1;\n end\n if ((I1I1O00I % 3) > 0) begin\n for (O1OIIOII=0 ; O1OIIOII < (I1I1O00I % 3) ; O1OIIOII = O1OIIOII + 1)\n l10III00[2 * (I1I1O00I/3) + O1OIIOII] = I0lII01I[3 * (I1I1O00I/3) + O1OIIOII];\n end\n\n for (O1OIIOII=0 ; O1OIIOII < num_inputs ; O1OIIOII = O1OIIOII + 1)\n I0lII01I[O1OIIOII] = l10III00[O1OIIOII];\n I1I1O00I = I1I1O00I - (I1I1O00I/3);\n end\n OII0OOOI = I0lII01I[0];\n if (I1I1O00I > 1)\n O001l0I0 = I0lII01I[1];\n else\n O001l0I0 = {input_width{1'b0}};\nend // IIIIO1Ol\n\n\nassign OUT0 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : OII0OOOI;\nassign OUT1 = (^(INPUT ^ INPUT) !== 1'b0) ? {input_width{1'bx}} : O001l0I0;\n\n// synopsys translate_on\n\nendmodule\n // synopsys translate_off\n// `endif\n // synopsys translate_on\n"], ["/High-Performance-Tensor-Processing-Engines/OPT2/weight_rf.sv", "module weight_rf (\n input clk,\n input wen,\n input [7:0] din,\n output [7:0] weight [0:15]\n);\n\nreg [7:0] buffer [0:15];\n\nassign weight = buffer;\n\ngenvar i;\ngenerate\n for (i = 0; i < 16; i = i + 1) begin\n always @(posedge clk) begin\n if(wen) begin\n if (i==15)\n buffer[i] <= din;\n else \n buffer[i] <= buffer[i+1];\n end\n else\n buffer[i] <= buffer[i];\n end\n end\nendgenerate\n\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/booth_partial_product_generator.v", "module booth_partial_product_generator(\n input wire [2:0] operand_slice_a, \n input wire [7:0] operand_b, \n input wire [8:0] operand_b_neg, \n output wire [9:0] pp_out \n );\n \n wire [8:0] pp_source ;\n //----------------------------------------------------\n //| pp | flag_2x | flag_s1 | flag_s2 |\n //----------------------------------------------------\n //| operand_b | 0 | 0 | 1 |\n //| -operand_b | 0 | 1 | 0 |\n //| 2operand_b | 1 | 0 | 1 | \n //| -2operand_b | 1 | 1 | 0 |\n //| 0 | x | 0 | 0 | \n //----------------------------------------------------\n wire not_c2 ; \n wire c1_and_c0 ; \n wire c1_nor_c0 ; \n wire nor_o2 ; \n \n wire flag_2x ;\n wire flag_s1 ;\n wire flag_s2 ;\n \n assign not_c2 = ~operand_slice_a[2] ;\n assign c1_and_c0 = operand_slice_a[1] & operand_slice_a[0] ;\n assign c1_nor_c0 = ~(operand_slice_a[1] | operand_slice_a[0]) ;\n assign nor_o2 = ~(c1_and_c0 | c1_nor_c0) ;\n \n assign flag_2x = ~nor_o2 ;\n assign flag_s1 = ~(not_c2 | c1_and_c0) ;\n assign flag_s2 = ~(operand_slice_a[2] | c1_nor_c0) ;\n \n wire flag_not_2x = nor_o2; \n \n assign pp_source = (({{operand_b[7]}, operand_b} & {9{flag_s2}}) | (operand_b_neg & {9{flag_s1}}));\n assign pp_out[0] = (!flag_2x & pp_source[0]);\n assign pp_out[8:1] = (({8{flag_2x}} & pp_source[7:0]) | ({8{flag_not_2x}} & pp_source[8:1]));\n assign pp_out[9] = pp_source[8];\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/booth_partial_product_generator.v", "module booth_partial_product_generator(\n input wire [2:0] operand_slice_a, \n input wire [7:0] operand_b, \n input wire [8:0] operand_b_neg, \n output wire [9:0] pp_out \n );\n \n wire [8:0] pp_source ;\n //----------------------------------------------------\n //| pp | flag_2x | flag_s1 | flag_s2 |\n //----------------------------------------------------\n //| operand_b | 0 | 0 | 1 |\n //| -operand_b | 0 | 1 | 0 |\n //| 2operand_b | 1 | 0 | 1 | \n //| -2operand_b | 1 | 1 | 0 |\n //| 0 | x | 0 | 0 | \n //----------------------------------------------------\n \n //----------------------------------------------------\n //operand_slice_a[1] operand_slice_a[0] operand_slice_a[-1] | pp \n //----------------------------------------------------\n // 0 0 0 | 0 \n // 0 0 1 | operand_b \n // 0 1 0 | operand_b \n // 0 1 1 | 2operand_b \n // 1 0 0 | -2operand_b \n // 1 0 1 | -operand_b \n // 1 1 0 | -operand_b \n // 1 1 1 | 0 \n //----------------------------------------------------\n \n wire not_c2 ; \n wire c1_and_c0 ; \n wire c1_nor_c0 ; \n wire nor_o2 ; \n \n wire flag_2x ;\n wire flag_s1 ;\n wire flag_s2 ;\n \n assign not_c2 = ~operand_slice_a[2] ;\n assign c1_and_c0 = operand_slice_a[1] & operand_slice_a[0] ;\n assign c1_nor_c0 = ~(operand_slice_a[1] | operand_slice_a[0]) ;\n assign nor_o2 = ~(c1_and_c0 | c1_nor_c0) ;\n \n assign flag_2x = ~nor_o2 ;\n assign flag_s1 = ~(not_c2 | c1_and_c0) ;\n assign flag_s2 = ~(operand_slice_a[2] | c1_nor_c0) ;\n \n wire flag_not_2x = nor_o2; \n assign pp_source = (({{operand_b[7]}, operand_b} & {9{flag_s2}}) | (operand_b_neg & {9{flag_s1}}));\n assign pp_out[0] = (!flag_2x & pp_source[0]);\n assign pp_out[8:1] = (({8{flag_2x}} & pp_source[7:0]) | ({8{flag_not_2x}} & pp_source[8:1]));\n assign pp_out[9] = pp_source[8];\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/booth_partial_product_generator.v", "module booth_partial_product_generator(\n input wire [2:0] operand_slice_a, \n input wire [7:0] operand_b, \n input wire [8:0] operand_b_neg, \n output wire [9:0] pp_out \n );\n \n wire [8:0] pp_source ;\n //----------------------------------------------------\n //| pp | flag_2x | flag_s1 | flag_s2 |\n //----------------------------------------------------\n //| operand_b | 0 | 0 | 1 |\n //| -operand_b | 0 | 1 | 0 |\n //| 2operand_b | 1 | 0 | 1 | \n //| -2operand_b | 1 | 1 | 0 |\n //| 0 | x | 0 | 0 | \n //----------------------------------------------------\n \n //----------------------------------------------------\n //operand_slice_a[1] operand_slice_a[0] operand_slice_a[-1] | pp \n //----------------------------------------------------\n // 0 0 0 | 0 \n // 0 0 1 | operand_b \n // 0 1 0 | operand_b \n // 0 1 1 | 2operand_b \n // 1 0 0 | -2operand_b \n // 1 0 1 | -operand_b \n // 1 1 0 | -operand_b \n // 1 1 1 | 0 \n //----------------------------------------------------\n \n wire not_c2 ; \n wire c1_and_c0 ; \n wire c1_nor_c0 ; \n wire nor_o2 ; \n \n wire flag_2x ;\n wire flag_s1 ;\n wire flag_s2 ;\n \n assign not_c2 = ~operand_slice_a[2] ;\n assign c1_and_c0 = operand_slice_a[1] & operand_slice_a[0] ;\n assign c1_nor_c0 = ~(operand_slice_a[1] | operand_slice_a[0]) ;\n assign nor_o2 = ~(c1_and_c0 | c1_nor_c0) ;\n \n assign flag_2x = ~nor_o2 ;\n assign flag_s1 = ~(not_c2 | c1_and_c0) ;\n assign flag_s2 = ~(operand_slice_a[2] | c1_nor_c0) ;\n \n wire flag_not_2x = nor_o2; \n assign pp_source = (({{operand_b[7]}, operand_b} & {9{flag_s2}}) | (operand_b_neg & {9{flag_s1}}));\n assign pp_out[0] = (!flag_2x & pp_source[0]);\n assign pp_out[8:1] = (({8{flag_2x}} & pp_source[7:0]) | ({8{flag_not_2x}} & pp_source[8:1]));\n assign pp_out[9] = pp_source[8];\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/booth_partial_product_generator.v", "module booth_partial_product_generator(\n input wire [2:0] operand_slice_a, \n input wire [7:0] operand_b, \n input wire [8:0] operand_b_neg, \n output wire [9:0] pp_out \n );\n \n wire [8:0] pp_source ;\n //----------------------------------------------------\n //| pp | flag_2x | flag_s1 | flag_s2 |\n //----------------------------------------------------\n //| operand_b | 0 | 0 | 1 |\n //| -operand_b | 0 | 1 | 0 |\n //| 2operand_b | 1 | 0 | 1 | \n //| -2operand_b | 1 | 1 | 0 |\n //| 0 | x | 0 | 0 | \n //----------------------------------------------------\n \n //----------------------------------------------------\n //operand_slice_a[1] operand_slice_a[0] operand_slice_a[-1] | pp \n //----------------------------------------------------\n // 0 0 0 | 0 \n // 0 0 1 | operand_b \n // 0 1 0 | operand_b \n // 0 1 1 | 2operand_b \n // 1 0 0 | -2operand_b \n // 1 0 1 | -operand_b \n // 1 1 0 | -operand_b \n // 1 1 1 | 0 \n //----------------------------------------------------\n \n wire not_c2 ; \n wire c1_and_c0 ; \n wire c1_nor_c0 ; \n wire nor_o2 ; \n \n wire flag_2x ;\n wire flag_s1 ;\n wire flag_s2 ;\n \n assign not_c2 = ~operand_slice_a[2] ;\n assign c1_and_c0 = operand_slice_a[1] & operand_slice_a[0] ;\n assign c1_nor_c0 = ~(operand_slice_a[1] | operand_slice_a[0]) ;\n assign nor_o2 = ~(c1_and_c0 | c1_nor_c0) ;\n \n assign flag_2x = ~nor_o2 ;\n assign flag_s1 = ~(not_c2 | c1_and_c0) ;\n assign flag_s2 = ~(operand_slice_a[2] | c1_nor_c0) ;\n \n wire flag_not_2x = nor_o2; \n assign pp_source = (({{operand_b[7]}, operand_b} & {9{flag_s2}}) | (operand_b_neg & {9{flag_s1}}));\n assign pp_out[0] = (!flag_2x & pp_source[0]);\n assign pp_out[8:1] = (({8{flag_2x}} & pp_source[7:0]) | ({8{flag_not_2x}} & pp_source[8:1]));\n assign pp_out[9] = pp_source[8];\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/booth_partial_product_generator_pp1.v", "module booth_partial_product_generator_pp1(\n input wire [1:0] operand_slice_a, \n input wire [7:0] operand_b, \n input wire [8:0] operand_b_neg, \n output wire [9:0] pp_out \n );\n \n wire [8:0] pp_source;\n wire not_code0;\n //----------------------------------------------------\n //| pp | flag_2x | flag_s1 | flag_s2 |\n //----------------------------------------------------\n //| operand_b | 0 | 0 | 1 |\n //| -operand_b | 0 | 1 | 0 |\n //| 2operand_b | 1 | 0 | 1 | \n //| -2operand_b | 1 | 1 | 0 |\n //| 0 | x | 0 | 0 | \n //----------------------------------------------------\n \n //----------------------------------------------------\n //operand_slice_a[1] operand_slice_a[0] operand_slice_a[-1] | pp \n //----------------------------------------------------\n // 0 0 0 | 0 \n // 0 1 0 | operand_b \n // 1 0 0 | 2operand_b \n // 1 1 0 | -operand_b \n //----------------------------------------------------\n \n wire flag_2x;\n wire flag_s1;\n wire flag_s2; \n assign not_code0 = ~operand_slice_a[0]; \n assign flag_2x = not_code0; \n assign flag_s1 = operand_slice_a[1]; // 取反\n assign flag_s2 = ~(operand_slice_a[1] | not_code0); // A\n wire flag_not_2x = operand_slice_a[0];\n assign pp_source = (({{operand_b[7]}, operand_b} & {9{flag_s2}}) | (operand_b_neg & {9{flag_s1}})); // A or ~A or 0\n assign pp_out[0] = (!flag_2x & pp_source[0]);// x2 (<<1) pp_out[0]=0\n assign pp_out[8:1] = (({8{flag_2x}} & pp_source[7:0]) | ({8{flag_not_2x}} & pp_source[8:1]));\n assign pp_out[9] = pp_source[8];\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/booth_partial_product_generator_pp1.v", "module booth_partial_product_generator_pp1(\n input wire [1:0] operand_slice_a, \n input wire [7:0] operand_b, \n input wire [8:0] operand_b_neg, \n output wire [9:0] pp_out \n );\n \n wire [8:0] pp_source;\n wire not_code0;\n //----------------------------------------------------\n //| pp | flag_2x | flag_s1 | flag_s2 |\n //----------------------------------------------------\n //| operand_b | 0 | 0 | 1 |\n //| -operand_b | 0 | 1 | 0 |\n //| 2operand_b | 1 | 0 | 1 | \n //| -2operand_b | 1 | 1 | 0 |\n //| 0 | x | 0 | 0 | \n //----------------------------------------------------\n \n //----------------------------------------------------\n //operand_slice_a[1] operand_slice_a[0] operand_slice_a[-1] | pp \n //----------------------------------------------------\n // 0 0 0 | 0 \n // 0 1 0 | operand_b \n // 1 0 0 | 2operand_b \n // 1 1 0 | -operand_b \n //----------------------------------------------------\n \n wire flag_2x;\n wire flag_s1;\n wire flag_s2; \n assign not_code0 = ~operand_slice_a[0]; \n assign flag_2x = not_code0; \n assign flag_s1 = operand_slice_a[1]; // 取反\n assign flag_s2 = ~(operand_slice_a[1] | not_code0); // A\n wire flag_not_2x = operand_slice_a[0];\n assign pp_source = (({{operand_b[7]}, operand_b} & {9{flag_s2}}) | (operand_b_neg & {9{flag_s1}})); // A or ~A or 0\n assign pp_out[0] = (!flag_2x & pp_source[0]);// x2 (<<1) pp_out[0]=0\n assign pp_out[8:1] = (({8{flag_2x}} & pp_source[7:0]) | ({8{flag_not_2x}} & pp_source[8:1]));\n assign pp_out[9] = pp_source[8];\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/booth_partial_product_generator_pp1.v", "module booth_partial_product_generator_pp1(\n input wire [1:0] operand_slice_a, \n input wire [7:0] operand_b, \n input wire [8:0] operand_b_neg, \n output wire [9:0] pp_out \n );\n \n wire [8:0] pp_source;\n wire not_code0;\n //----------------------------------------------------\n //| pp | flag_2x | flag_s1 | flag_s2 |\n //----------------------------------------------------\n //| operand_b | 0 | 0 | 1 |\n //| -operand_b | 0 | 1 | 0 |\n //| 2operand_b | 1 | 0 | 1 | \n //| -2operand_b | 1 | 1 | 0 |\n //| 0 | x | 0 | 0 | \n //----------------------------------------------------\n \n //----------------------------------------------------\n //operand_slice_a[1] operand_slice_a[0] operand_slice_a[-1] | pp \n //----------------------------------------------------\n // 0 0 0 | 0 \n // 0 1 0 | operand_b \n // 1 0 0 | 2operand_b \n // 1 1 0 | -operand_b \n //----------------------------------------------------\n \n wire flag_2x;\n wire flag_s1;\n wire flag_s2; \n assign not_code0 = ~operand_slice_a[0]; \n assign flag_2x = not_code0; \n assign flag_s1 = operand_slice_a[1]; // 取反\n assign flag_s2 = ~(operand_slice_a[1] | not_code0); // A\n wire flag_not_2x = operand_slice_a[0];\n assign pp_source = (({{operand_b[7]}, operand_b} & {9{flag_s2}}) | (operand_b_neg & {9{flag_s1}})); // A or ~A or 0\n assign pp_out[0] = (!flag_2x & pp_source[0]);// x2 (<<1) pp_out[0]=0\n assign pp_out[8:1] = (({8{flag_2x}} & pp_source[7:0]) | ({8{flag_not_2x}} & pp_source[8:1]));\n assign pp_out[9] = pp_source[8];\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/booth_partial_product_generator_pp1.v", "module booth_partial_product_generator_pp1(\n input wire [1:0] operand_slice_a, \n input wire [7:0] operand_b, \n input wire [8:0] operand_b_neg, \n output wire [9:0] pp_out \n );\n \n wire [8:0] pp_source;\n wire not_code0;\n //----------------------------------------------------\n //| pp | flag_2x | flag_s1 | flag_s2 |\n //----------------------------------------------------\n //| operand_b | 0 | 0 | 1 |\n //| -operand_b | 0 | 1 | 0 |\n //| 2operand_b | 1 | 0 | 1 | \n //| -2operand_b | 1 | 1 | 0 |\n //| 0 | x | 0 | 0 | \n //----------------------------------------------------\n wire flag_2x;\n wire flag_s1;\n wire flag_s2; \n assign not_code0 = ~operand_slice_a[0]; \n assign flag_2x = not_code0; \n assign flag_s1 = operand_slice_a[1]; \n assign flag_s2 = ~(operand_slice_a[1] | not_code0); \n wire flag_not_2x = operand_slice_a[0];\n assign pp_source = (({{operand_b[7]}, operand_b} & {9{flag_s2}}) | (operand_b_neg & {9{flag_s1}}));\n assign pp_out[0] = (!flag_2x & pp_source[0]);\n assign pp_out[8:1] = (({8{flag_2x}} & pp_source[7:0]) | ({8{flag_not_2x}} & pp_source[8:1]));\n assign pp_out[9] = pp_source[8];\n\nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/inv_unit_nor_out.v", "module inv_unit_nor_out(\n input wire a ,\n input wire b ,\n \n output wire xor_o , \n output wire nor_o \n );\n \n\n wire a_AND_b ; \n wire a_NOR_b ; \n \n \n assign a_AND_b = a & b;\n \n \n assign a_NOR_b = ~(a | b);\n \n\n assign xor_o = ~(a_AND_b | a_NOR_b);\n assign nor_o = a_NOR_b;\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/inv_unit_nor_out.v", "module inv_unit_nor_out(\n input wire a ,\n input wire b ,\n \n output wire xor_o , \n output wire nor_o \n );\n \n\n wire a_AND_b ; \n wire a_NOR_b ; \n \n \n assign a_AND_b = a & b;\n \n \n assign a_NOR_b = ~(a | b);\n \n\n assign xor_o = ~(a_AND_b | a_NOR_b);\n assign nor_o = a_NOR_b;\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/inv_unit_nor_out.v", "module inv_unit_nor_out(\n input wire a ,\n input wire b ,\n \n output wire xor_o , \n output wire nor_o \n );\n \n\n wire a_AND_b ; \n wire a_NOR_b ; \n \n \n assign a_AND_b = a & b;\n \n \n assign a_NOR_b = ~(a | b);\n \n\n assign xor_o = ~(a_AND_b | a_NOR_b);\n assign nor_o = a_NOR_b;\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/inv_unit_nor_out.v", "module inv_unit_nor_out(\n input wire a ,\n input wire b ,\n \n output wire xor_o , \n output wire nor_o \n );\n \n\n wire a_AND_b ; \n wire a_NOR_b ; \n \n \n assign a_AND_b = a & b;\n \n \n assign a_NOR_b = ~(a | b);\n \n\n assign xor_o = ~(a_AND_b | a_NOR_b);\n assign nor_o = a_NOR_b;\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/array_opt1_based/inv_unit.v", "module inv_unit(\n input wire a ,\n input wire b ,\n output wire xor_o , \n output wire or_o \n );\n \n wire aORb ; \n wire aNANDb ; \n \n assign aORb = a | b;\n assign aNANDb = ~(a & b);\n assign xor_o = (aORb & aNANDb);\n assign or_o = aORb;\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_os/opt1_pe/inv_unit.v", "module inv_unit(\n input wire a ,\n input wire b ,\n output wire xor_o , \n output wire or_o \n );\n \n wire aORb ; \n wire aNANDb ; \n \n assign aORb = a | b;\n assign aNANDb = ~(a & b);\n assign xor_o = (aORb & aNANDb);\n assign or_o = aORb;\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/cube/array_opt1_based/inv_unit.v", "module inv_unit(\n input wire a ,\n input wire b ,\n output wire xor_o , \n output wire or_o \n );\n \n wire aORb ; \n wire aNANDb ; \n \n assign aORb = a | b;\n assign aNANDb = ~(a & b);\n assign xor_o = (aORb & aNANDb);\n assign or_o = aORb;\n \nendmodule"], ["/High-Performance-Tensor-Processing-Engines/OPT1/systolic_array_ws/array_opt1_based/inv_unit.v", "module inv_unit(\n input wire a ,\n input wire b ,\n output wire xor_o , \n output wire or_o \n );\n \n wire aORb ; \n wire aNANDb ; \n \n assign aORb = a | b;\n assign aNANDb = ~(a & b);\n assign xor_o = (aORb & aNANDb);\n assign or_o = aORb;\n \nendmodule"]], "task_instance_info": {"created_time": "2025-08-21 04:17:40", "created_task_model": "DeepSeek-R1", "class_skeleton": "module PE #\n(\n parameter WIDTH = 8,\n parameter ACC_WIDTH = 32\n)\n(\n input wire rst_n,\n input wire clk,\n input wire signed [WIDTH-1 :0] a,\n input wire signed [WIDTH-1 :0] b,\n input wire clc, // clean_result_cache\n\n output reg signed [WIDTH-1 :0] row,\n output reg signed [WIDTH-1 :0] col,\n output signed [2*ACC_WIDTH-1 :0] result\n) ; endmodule", "code_description": "This code segment functions to: Perform signed multiplication and accumulation operations on input data streams while maintaining synchronized state registers for operand tracking and outputting combined accumulator results."}, "inference_content": {"inference_model": "DeepSeek-R1", "inference_result": "```verilog\n[TASK_BEGIN]\nreg signed [2*ACC_WIDTH-1:0] acc;\n\nalways @(posedge clk or negedge rst_n) begin\n if (!rst_n) begin\n row <= 0;\n col <= 0;\n acc <= 0;\n end else begin\n row <= a;\n col <= b;\n \n if (clc) begin\n acc <= 0;\n end else begin\n acc <= acc + (row * col);\n end\n end\nend\n\nassign result = acc;\n[TASK_END]\n```", "inference_time": "2025-08-21 04-18-52"}, "editdistance_info": {"edit_distance": 11.1465, "calculate_time": "2025-08-21 04:18:52", "true_code_clean": "module PE #\n(\n parameter WIDTH = 8,\n parameter ACC_WIDTH = 32\n)\n(\n input wire rst_n,\n input wire clk,\n input wire signed [WIDTH-1 :0] a,\n input wire signed [WIDTH-1 :0] b,\n input wire clc, \n output reg signed [WIDTH-1 :0] row,\n output reg signed [WIDTH-1 :0] col,\n output signed [2*ACC_WIDTH-1 :0] result\n);\nwire [ACC_WIDTH-1:0] acc_sum;\nwire [ACC_WIDTH-1:0] acc_carry;\nopt1_mac #(\n .ACC_WIDTH(ACC_WIDTH),\n .INPUT_PIP(0)\n) opt1_mac_test (\n .clk(clk),\n .rst_n(rst_n),\n .operand_a_in(a), \n .operand_b_in(b), \n .clc(clc), \n .acc_sum(acc_sum),\n .acc_carry(acc_carry)\n);\nassign result = {acc_sum, acc_carry};\nalways @(posedge clk or negedge rst_n) begin\n if(!rst_n) begin\n row <= 0;\n col <= 0;\n end\n else begin\n row <= a;\n col <= b;\n end\nend\nendmodule", "predict_code_clean": "reg signed [2*ACC_WIDTH-1:0] acc;\nalways @(posedge clk or negedge rst_n) begin\n if (!rst_n) begin\n row <= 0;\n col <= 0;\n acc <= 0;\n end else begin\n row <= a;\n col <= b;\n if (clc) begin\n acc <= 0;\n end else begin\n acc <= acc + (row * col);\n end\n end\nend\nassign result = acc;"}}