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  1. c/pogocache_block_bench.jsonl +0 -0
  2. c_sharp/AwesomeAssertions_block_bench.jsonl +0 -0
  3. c_sharp/AwesomeAssertions_function_bench.jsonl +0 -0
  4. c_sharp/CrapFixer_class_bench.jsonl +0 -0
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  9. c_sharp/SubsCheck-Win-GUI_block_bench.jsonl +0 -0
  10. c_sharp/SubsCheck-Win-GUI_class_bench.jsonl +0 -0
  11. c_sharp/Winhance_function_bench.jsonl +0 -0
  12. c_sharp/csharp-sdk_block_bench.jsonl +0 -0
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  14. c_sharp/handcrafted-persona-engine_block_bench.jsonl +0 -0
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  17. c_sharp/unity-mcp_function_bench.jsonl +0 -0
  18. verilog/ICX453_CCD_Mirrorless_Camera_class_bench.jsonl +5 -0
  19. verilog/Mayoiuta_class_bench.jsonl +5 -0
  20. verilog/z80-open-silicon_class_bench.jsonl +0 -0
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+ {"repo_name": "ICX453_CCD_Mirrorless_Camera", "file_name": "/ICX453_CCD_Mirrorless_Camera/line_skipper.v", "inference_info": {"prefix_code": "`timescale 1ns / 1ps\n\n", "suffix_code": "\n", "middle_code": "module line_skipper(\n\t\tinput wire clk,\n\t\tinput wire rst,\n\t\tinput wire [15:0] raw_pixel_in,\n\t\tinput wire raw_pixel_valid_in,\n\t\tinput wire readout_busy_in,\n\t\tinput wire line_sync,\n\t\toutput wire [31:0] axi_data_buffer_o,\n\t\toutput wire axi_send_pulse_o\n);\nreg line_sync_ff1;\nreg line_sync_ff2;\nwire line_sync_pulse = (line_sync_ff1 && ~line_sync_ff2) ? 1'b1 : 1'b0;\nalways @(posedge clk ) begin\n\tif(raw_pixel_valid_in) begin\n\t\tline_sync_ff1 <= line_sync;\n\t\tline_sync_ff2 <= line_sync_ff1;\n\tend\nend\n(* MARK_DEBUG=\"true\" *)reg [15:0] skip_pixel_cnt;\n(* MARK_DEBUG=\"true\" *)reg [15:0] skip_line_cnt;\n(* MARK_DEBUG=\"true\" *)reg [7:0] pixel_cnt_x;\n(* MARK_DEBUG=\"true\" *)reg [7:0] pixel_cnt_y;\n(* MARK_DEBUG=\"true\" *) reg [3:0] state_q;\nparameter SKIP_FIRST_55_PIX = 4'b0000;\nparameter COUNT_24_PIXEL = 4'b0001;\nparameter SEND_PIXEL = 4'b0011;\nparameter SKIP_6_LINE = 4'b0010;\nparameter DONE = 4'b0110;\nlocalparam SKIP_INVALID_PIX = 55;\nlocalparam TOTAL_LINE = 1024;\nlocalparam PIXEL_PER_LINE = 5760;\nlocalparam SKIPED_PIX = 24;\nlocalparam SKIPED_LINE = 6;\nlocalparam VIEWFINDER_X = 240;\nlocalparam VIEWFINDER_Y = 160;\nreg [4:0] gamma_corrected_buf;\nalways @(posedge clk or posedge rst) begin\n if(rst || ~readout_busy_in)begin\n gamma_corrected_buf <= 0;\n end\n else if(raw_pixel_valid_in) begin\n case (raw_pixel_in[15:11])\n 'd00: gamma_corrected_buf <= 'd00;\n 'd01: gamma_corrected_buf <= 'd07;\n 'd02: gamma_corrected_buf <= 'd09;\n 'd03: gamma_corrected_buf <= 'd11;\n 'd04: gamma_corrected_buf <= 'd12;\n 'd05: gamma_corrected_buf <= 'd14;\n 'd06: gamma_corrected_buf <= 'd15;\n 'd07: gamma_corrected_buf <= 'd16;\n 'd08: gamma_corrected_buf <= 'd17;\n 'd09: gamma_corrected_buf <= 'd18;\n 'd10: gamma_corrected_buf <= 'd19;\n 'd11: gamma_corrected_buf <= 'd19;\n 'd12: gamma_corrected_buf <= 'd20;\n 'd13: gamma_corrected_buf <= 'd21;\n 'd14: gamma_corrected_buf <= 'd22;\n 'd15: gamma_corrected_buf <= 'd22;\n 'd16: gamma_corrected_buf <= 'd23;\n 'd17: gamma_corrected_buf <= 'd24;\n 'd18: gamma_corrected_buf <= 'd24;\n 'd19: gamma_corrected_buf <= 'd25;\n 'd20: gamma_corrected_buf <= 'd25;\n 'd21: gamma_corrected_buf <= 'd26;\n 'd22: gamma_corrected_buf <= 'd27;\n 'd23: gamma_corrected_buf <= 'd27;\n 'd24: gamma_corrected_buf <= 'd28;\n 'd25: gamma_corrected_buf <= 'd28;\n 'd26: gamma_corrected_buf <= 'd29;\n 'd27: gamma_corrected_buf <= 'd29;\n 'd28: gamma_corrected_buf <= 'd30;\n 'd29: gamma_corrected_buf <= 'd30;\n 'd30: gamma_corrected_buf <= 'd31;\n 'd31: gamma_corrected_buf <= 'd31;\n default: gamma_corrected_buf <= 0;\n endcase\n end\nend\nreg buffer_valid;\nwire [15:0] rgb565_gray = {gamma_corrected_buf, gamma_corrected_buf, 1'b0 , gamma_corrected_buf};\nalways @(posedge clk or posedge rst) begin\n\tif(rst || ~readout_busy_in) begin\n\t\tstate_q <= SKIP_FIRST_55_PIX;\n\t\tskip_pixel_cnt <= 0; \n\t\tskip_line_cnt <= 0;\n\t\tpixel_cnt_x <= 0;\n\t\tpixel_cnt_y <= 0;\n\t\tbuffer_valid <= 0;\n\tend\n\telse if(raw_pixel_valid_in) begin\n\t\tcase (state_q)\n\t\t\tSKIP_FIRST_55_PIX: begin\n\t\t\t\tif (skip_pixel_cnt >= SKIP_INVALID_PIX) begin\n\t\t\t\t\tstate_q <= COUNT_24_PIXEL;\n\t\t\t\t\tskip_pixel_cnt <= 0;\n\t\t\t\tend\n\t\t\t\telse begin\n\t\t\t\t\tskip_pixel_cnt <= skip_pixel_cnt + 1;\n\t\t\t\tend\n\t\t\tend\n\t\t\tCOUNT_24_PIXEL: begin\n\t\t\t\tif (skip_pixel_cnt < SKIPED_PIX) begin\n\t\t\t\t\tskip_pixel_cnt <= skip_pixel_cnt + 1;\n\t\t\t\tend\n\t\t\t\telse begin\n\t\t\t\t\tstate_q <= SEND_PIXEL;\n\t\t\t\t\tbuffer_valid <= 1;\n\t\t\t\t\tskip_pixel_cnt <= 0;\n\t\t\t\tend\n\t\t\tend\n\t\t\tSEND_PIXEL: begin\n\t\t\t\tif (pixel_cnt_x < VIEWFINDER_X) begin\n\t\t\t\t\tpixel_cnt_x <= pixel_cnt_x + 1;\n\t\t\t\t\tbuffer_valid <= 0;\n\t\t\t\t\tstate_q <= COUNT_24_PIXEL;\n\t\t\t\tend\n\t\t\t\telse begin\n\t\t\t\t\tpixel_cnt_x <= 0;\n\t\t\t\t\tstate_q <= SKIP_6_LINE;\n\t\t\t\tend\n\t\t\tend\n\t\t\tSKIP_6_LINE: begin\n\t\t\t\tif (line_sync_pulse) begin\n\t\t\t\t\tif (pixel_cnt_y >= VIEWFINDER_Y) begin\n\t\t\t\t\t\tstate_q <= DONE;\n\t\t\t\t\t\tpixel_cnt_y <= 0;\n\t\t\t\t\tend\n\t\t\t\t\telse if (skip_line_cnt < SKIPED_LINE - 1) begin\n\t\t\t\t\t\tskip_line_cnt <= skip_line_cnt + 1;\n\t\t\t\t\tend\n\t\t\t\t\telse begin\n\t\t\t\t\t\tskip_line_cnt <= 0;\n\t\t\t\t\t\tpixel_cnt_y <= pixel_cnt_y + 1;\n\t\t\t\t\t\tstate_q <= COUNT_24_PIXEL;\n\t\t\t\t\tend\n\t\t\t\tend\t\n\t\t\tend\n\t\t\tDONE: begin\n\t\t\tend\n\t\t\tdefault: state_q <= DONE;\n\t\tendcase\n\tend\nend\nreg buffer_valid_ff;\nwire buffer_valid_pulse = (buffer_valid && ~buffer_valid_ff) ? 1'b1 : 1'b0 ;\nalways @(posedge clk) begin\n\tbuffer_valid_ff <= buffer_valid;\nend\nreg [31:0] axi_send_buffer;\nreg axi_send_cnt;\nreg axi_send_pulse;\nassign axi_data_buffer_o = axi_send_buffer;\nassign axi_send_pulse_o = axi_send_pulse;\nalways @(posedge clk or posedge rst) begin\n\tif (rst) begin\n\t\taxi_send_buffer <= 0;\n\t\taxi_send_pulse <= 0;\n\t\taxi_send_cnt <= 0;\n\tend\n\telse begin\n\t\tif (buffer_valid_pulse) begin\n\t\t\taxi_send_buffer <= {axi_send_buffer[15:0],rgb565_gray};\n\t\tend\t\n\t\tif (buffer_valid_pulse) begin\n\t\t\taxi_send_cnt <= axi_send_cnt + 1;\n\t\tend\n\t\tif (axi_send_cnt && buffer_valid_pulse) begin\n\t\t\taxi_send_pulse <= 1;\n\t\tend\n\t\telse begin\n\t\t\taxi_send_pulse <= 0;\n\t\tend\n\tend \nend\nendmodule", "code_description": null, "fill_type": "CLASS_TYPE", "language_type": "verilog", "sub_task_type": null}, "context_code": [], "task_instance_info": {"created_time": "2025-08-21 04:22:24", "created_task_model": "DeepSeek-R1", "class_skeleton": "module line_skipper (\n\t\tinput wire clk,\n\t\tinput wire rst,\n\t\t\n\t\t//pixel input\n\t\tinput wire [15:0] raw_pixel_in,\n\t\tinput wire raw_pixel_valid_in,\n\t\tinput wire readout_busy_in,\n\t\tinput wire line_sync,\n\t\t\n\t\toutput wire [31:0] axi_data_buffer_o,\n\t\toutput wire axi_send_pulse_o\n) ; endmodule", "code_description": "This code segment functions to: Process image data streams by implementing pixel skipping and line skipping patterns, apply gamma correction transformations, and buffer formatted grayscale output for peripheral interface transmission."}, "inference_content": {"inference_model": "DeepSeek-R1", "inference_result": "```verilog\n[TASK_BEGIN]\nmodule line_skipper (\n input wire clk,\n input wire rst,\n \n // Pixel input\n input wire [15:0] raw_pixel_in,\n input wire raw_pixel_valid_in,\n input wire readout_busy_in,\n input wire line_sync,\n \n output wire [31:0] axi_data_buffer_o,\n output wire axi_send_pulse_o\n);\n\n reg [15:0] pixel_buffer;\n reg buffer_valid;\n reg skip_line;\n reg [31:0] data_buffer;\n reg send_pulse;\n\n always @(posedge clk or posedge rst) begin\n if (rst) begin\n pixel_buffer <= 16'h0;\n buffer_valid <= 1'b0;\n skip_line <= 1'b0;\n data_buffer <= 32'h0;\n send_pulse <= 1'b0;\n end else begin\n send_pulse <= 1'b0;\n \n // Toggle skip line on line sync\n if (line_sync) begin\n skip_line <= ~skip_line;\n buffer_valid <= 1'b0; // Reset buffer on new line\n end\n\n // Process pixels when not skipping and interface is ready\n if (!skip_line && raw_pixel_valid_in && !readout_busy_in) begin\n if (buffer_valid) begin\n data_buffer <= {pixel_buffer, raw_pixel_in};\n send_pulse <= 1'b1;\n buffer_valid <= 1'b0;\n end else begin\n pixel_buffer <= raw_pixel_in;\n buffer_valid <= 1'b1;\n end\n end\n end\n end\n\n assign axi_data_buffer_o = data_buffer;\n assign axi_send_pulse_o = send_pulse;\n\nendmodule\n[TASK_END]\n```", "inference_time": "2025-08-21 04-23-22"}, "editdistance_info": {"edit_distance": 10.6613, "calculate_time": "2025-08-21 04:23:22", "true_code_clean": "module line_skipper(\n\t\tinput wire clk,\n\t\tinput wire rst,\n\t\tinput wire [15:0] raw_pixel_in,\n\t\tinput wire raw_pixel_valid_in,\n\t\tinput wire readout_busy_in,\n\t\tinput wire line_sync,\n\t\toutput wire [31:0] axi_data_buffer_o,\n\t\toutput wire axi_send_pulse_o\n);\nreg line_sync_ff1;\nreg line_sync_ff2;\nwire line_sync_pulse = (line_sync_ff1 && ~line_sync_ff2) ? 1'b1 : 1'b0;\nalways @(posedge clk ) begin\n\tif(raw_pixel_valid_in) begin\n\t\tline_sync_ff1 <= line_sync;\n\t\tline_sync_ff2 <= line_sync_ff1;\n\tend\nend\n(* MARK_DEBUG=\"true\" *)reg [15:0] skip_pixel_cnt;\n(* MARK_DEBUG=\"true\" *)reg [15:0] skip_line_cnt;\n(* MARK_DEBUG=\"true\" *)reg [7:0] pixel_cnt_x;\n(* MARK_DEBUG=\"true\" *)reg [7:0] pixel_cnt_y;\n(* MARK_DEBUG=\"true\" *) reg [3:0] state_q;\nparameter SKIP_FIRST_55_PIX = 4'b0000;\nparameter COUNT_24_PIXEL = 4'b0001;\nparameter SEND_PIXEL = 4'b0011;\nparameter SKIP_6_LINE = 4'b0010;\nparameter DONE = 4'b0110;\nlocalparam SKIP_INVALID_PIX = 55;\nlocalparam TOTAL_LINE = 1024;\nlocalparam PIXEL_PER_LINE = 5760;\nlocalparam SKIPED_PIX = 24;\nlocalparam SKIPED_LINE = 6;\nlocalparam VIEWFINDER_X = 240;\nlocalparam VIEWFINDER_Y = 160;\nreg [4:0] gamma_corrected_buf;\nalways @(posedge clk or posedge rst) begin\n if(rst || ~readout_busy_in)begin\n gamma_corrected_buf <= 0;\n end\n else if(raw_pixel_valid_in) begin\n case (raw_pixel_in[15:11])\n 'd00: gamma_corrected_buf <= 'd00;\n 'd01: gamma_corrected_buf <= 'd07;\n 'd02: gamma_corrected_buf <= 'd09;\n 'd03: gamma_corrected_buf <= 'd11;\n 'd04: gamma_corrected_buf <= 'd12;\n 'd05: gamma_corrected_buf <= 'd14;\n 'd06: gamma_corrected_buf <= 'd15;\n 'd07: gamma_corrected_buf <= 'd16;\n 'd08: gamma_corrected_buf <= 'd17;\n 'd09: gamma_corrected_buf <= 'd18;\n 'd10: gamma_corrected_buf <= 'd19;\n 'd11: gamma_corrected_buf <= 'd19;\n 'd12: gamma_corrected_buf <= 'd20;\n 'd13: gamma_corrected_buf <= 'd21;\n 'd14: gamma_corrected_buf <= 'd22;\n 'd15: gamma_corrected_buf <= 'd22;\n 'd16: gamma_corrected_buf <= 'd23;\n 'd17: gamma_corrected_buf <= 'd24;\n 'd18: gamma_corrected_buf <= 'd24;\n 'd19: gamma_corrected_buf <= 'd25;\n 'd20: gamma_corrected_buf <= 'd25;\n 'd21: gamma_corrected_buf <= 'd26;\n 'd22: gamma_corrected_buf <= 'd27;\n 'd23: gamma_corrected_buf <= 'd27;\n 'd24: gamma_corrected_buf <= 'd28;\n 'd25: gamma_corrected_buf <= 'd28;\n 'd26: gamma_corrected_buf <= 'd29;\n 'd27: gamma_corrected_buf <= 'd29;\n 'd28: gamma_corrected_buf <= 'd30;\n 'd29: gamma_corrected_buf <= 'd30;\n 'd30: gamma_corrected_buf <= 'd31;\n 'd31: gamma_corrected_buf <= 'd31;\n default: gamma_corrected_buf <= 0;\n endcase\n end\nend\nreg buffer_valid;\nwire [15:0] rgb565_gray = {gamma_corrected_buf, gamma_corrected_buf, 1'b0 , gamma_corrected_buf};\nalways @(posedge clk or posedge rst) begin\n\tif(rst || ~readout_busy_in) begin\n\t\tstate_q <= SKIP_FIRST_55_PIX;\n\t\tskip_pixel_cnt <= 0; \n\t\tskip_line_cnt <= 0;\n\t\tpixel_cnt_x <= 0;\n\t\tpixel_cnt_y <= 0;\n\t\tbuffer_valid <= 0;\n\tend\n\telse if(raw_pixel_valid_in) begin\n\t\tcase (state_q)\n\t\t\tSKIP_FIRST_55_PIX: begin\n\t\t\t\tif (skip_pixel_cnt >= SKIP_INVALID_PIX) begin\n\t\t\t\t\tstate_q <= COUNT_24_PIXEL;\n\t\t\t\t\tskip_pixel_cnt <= 0;\n\t\t\t\tend\n\t\t\t\telse begin\n\t\t\t\t\tskip_pixel_cnt <= skip_pixel_cnt + 1;\n\t\t\t\tend\n\t\t\tend\n\t\t\tCOUNT_24_PIXEL: begin\n\t\t\t\tif (skip_pixel_cnt < SKIPED_PIX) begin\n\t\t\t\t\tskip_pixel_cnt <= skip_pixel_cnt + 1;\n\t\t\t\tend\n\t\t\t\telse begin\n\t\t\t\t\tstate_q <= SEND_PIXEL;\n\t\t\t\t\tbuffer_valid <= 1;\n\t\t\t\t\tskip_pixel_cnt <= 0;\n\t\t\t\tend\n\t\t\tend\n\t\t\tSEND_PIXEL: begin\n\t\t\t\tif (pixel_cnt_x < VIEWFINDER_X) begin\n\t\t\t\t\tpixel_cnt_x <= pixel_cnt_x + 1;\n\t\t\t\t\tbuffer_valid <= 0;\n\t\t\t\t\tstate_q <= COUNT_24_PIXEL;\n\t\t\t\tend\n\t\t\t\telse begin\n\t\t\t\t\tpixel_cnt_x <= 0;\n\t\t\t\t\tstate_q <= SKIP_6_LINE;\n\t\t\t\tend\n\t\t\tend\n\t\t\tSKIP_6_LINE: begin\n\t\t\t\tif (line_sync_pulse) begin\n\t\t\t\t\tif (pixel_cnt_y >= VIEWFINDER_Y) begin\n\t\t\t\t\t\tstate_q <= DONE;\n\t\t\t\t\t\tpixel_cnt_y <= 0;\n\t\t\t\t\tend\n\t\t\t\t\telse if (skip_line_cnt < SKIPED_LINE - 1) begin\n\t\t\t\t\t\tskip_line_cnt <= skip_line_cnt + 1;\n\t\t\t\t\tend\n\t\t\t\t\telse begin\n\t\t\t\t\t\tskip_line_cnt <= 0;\n\t\t\t\t\t\tpixel_cnt_y <= pixel_cnt_y + 1;\n\t\t\t\t\t\tstate_q <= COUNT_24_PIXEL;\n\t\t\t\t\tend\n\t\t\t\tend\t\n\t\t\tend\n\t\t\tDONE: begin\n\t\t\tend\n\t\t\tdefault: state_q <= DONE;\n\t\tendcase\n\tend\nend\nreg buffer_valid_ff;\nwire buffer_valid_pulse = (buffer_valid && ~buffer_valid_ff) ? 1'b1 : 1'b0 ;\nalways @(posedge clk) begin\n\tbuffer_valid_ff <= buffer_valid;\nend\nreg [31:0] axi_send_buffer;\nreg axi_send_cnt;\nreg axi_send_pulse;\nassign axi_data_buffer_o = axi_send_buffer;\nassign axi_send_pulse_o = axi_send_pulse;\nalways @(posedge clk or posedge rst) begin\n\tif (rst) begin\n\t\taxi_send_buffer <= 0;\n\t\taxi_send_pulse <= 0;\n\t\taxi_send_cnt <= 0;\n\tend\n\telse begin\n\t\tif (buffer_valid_pulse) begin\n\t\t\taxi_send_buffer <= {axi_send_buffer[15:0],rgb565_gray};\n\t\tend\t\n\t\tif (buffer_valid_pulse) begin\n\t\t\taxi_send_cnt <= axi_send_cnt + 1;\n\t\tend\n\t\tif (axi_send_cnt && buffer_valid_pulse) begin\n\t\t\taxi_send_pulse <= 1;\n\t\tend\n\t\telse begin\n\t\t\taxi_send_pulse <= 0;\n\t\tend\n\tend \nend\nendmodule", "predict_code_clean": "module line_skipper (\n input wire clk,\n input wire rst,\n input wire [15:0] raw_pixel_in,\n input wire raw_pixel_valid_in,\n input wire readout_busy_in,\n input wire line_sync,\n output wire [31:0] axi_data_buffer_o,\n output wire axi_send_pulse_o\n);\n reg [15:0] pixel_buffer;\n reg buffer_valid;\n reg skip_line;\n reg [31:0] data_buffer;\n reg send_pulse;\n always @(posedge clk or posedge rst) begin\n if (rst) begin\n pixel_buffer <= 16'h0;\n buffer_valid <= 1'b0;\n skip_line <= 1'b0;\n data_buffer <= 32'h0;\n send_pulse <= 1'b0;\n end else begin\n send_pulse <= 1'b0;\n if (line_sync) begin\n skip_line <= ~skip_line;\n buffer_valid <= 1'b0; \n end\n if (!skip_line && raw_pixel_valid_in && !readout_busy_in) begin\n if (buffer_valid) begin\n data_buffer <= {pixel_buffer, raw_pixel_in};\n send_pulse <= 1'b1;\n buffer_valid <= 1'b0;\n end else begin\n pixel_buffer <= raw_pixel_in;\n buffer_valid <= 1'b1;\n end\n end\n end\n end\n assign axi_data_buffer_o = data_buffer;\n assign axi_send_pulse_o = send_pulse;\nendmodule"}}
2
+ {"repo_name": "ICX453_CCD_Mirrorless_Camera", "file_name": "/ICX453_CCD_Mirrorless_Camera/line_skipper.v", "inference_info": {"prefix_code": "`timescale 1ns / 1ps\n\n", "suffix_code": "\n", "middle_code": "module line_skipper(\n\t\tinput wire clk,\n\t\tinput wire rst,\n\t\tinput wire [15:0] raw_pixel_in,\n\t\tinput wire raw_pixel_valid_in,\n\t\tinput wire readout_busy_in,\n\t\tinput wire line_sync,\n\t\toutput wire [31:0] axi_data_buffer_o,\n\t\toutput wire axi_send_pulse_o\n);\nreg line_sync_ff1;\nreg line_sync_ff2;\nwire line_sync_pulse = (line_sync_ff1 && ~line_sync_ff2) ? 1'b1 : 1'b0;\nalways @(posedge clk ) begin\n\tif(raw_pixel_valid_in) begin\n\t\tline_sync_ff1 <= line_sync;\n\t\tline_sync_ff2 <= line_sync_ff1;\n\tend\nend\n(* MARK_DEBUG=\"true\" *)reg [15:0] skip_pixel_cnt;\n(* MARK_DEBUG=\"true\" *)reg [15:0] skip_line_cnt;\n(* MARK_DEBUG=\"true\" *)reg [7:0] pixel_cnt_x;\n(* MARK_DEBUG=\"true\" *)reg [7:0] pixel_cnt_y;\n(* MARK_DEBUG=\"true\" *) reg [3:0] state_q;\nparameter SKIP_FIRST_55_PIX = 4'b0000;\nparameter COUNT_24_PIXEL = 4'b0001;\nparameter SEND_PIXEL = 4'b0011;\nparameter SKIP_6_LINE = 4'b0010;\nparameter DONE = 4'b0110;\nlocalparam SKIP_INVALID_PIX = 55;\nlocalparam TOTAL_LINE = 1024;\nlocalparam PIXEL_PER_LINE = 5760;\nlocalparam SKIPED_PIX = 24;\nlocalparam SKIPED_LINE = 6;\nlocalparam VIEWFINDER_X = 240;\nlocalparam VIEWFINDER_Y = 160;\nreg [4:0] gamma_corrected_buf;\nalways @(posedge clk or posedge rst) begin\n if(rst || ~readout_busy_in)begin\n gamma_corrected_buf <= 0;\n end\n else if(raw_pixel_valid_in) begin\n case (raw_pixel_in[15:11])\n 'd00: gamma_corrected_buf <= 'd00;\n 'd01: gamma_corrected_buf <= 'd07;\n 'd02: gamma_corrected_buf <= 'd09;\n 'd03: gamma_corrected_buf <= 'd11;\n 'd04: gamma_corrected_buf <= 'd12;\n 'd05: gamma_corrected_buf <= 'd14;\n 'd06: gamma_corrected_buf <= 'd15;\n 'd07: gamma_corrected_buf <= 'd16;\n 'd08: gamma_corrected_buf <= 'd17;\n 'd09: gamma_corrected_buf <= 'd18;\n 'd10: gamma_corrected_buf <= 'd19;\n 'd11: gamma_corrected_buf <= 'd19;\n 'd12: gamma_corrected_buf <= 'd20;\n 'd13: gamma_corrected_buf <= 'd21;\n 'd14: gamma_corrected_buf <= 'd22;\n 'd15: gamma_corrected_buf <= 'd22;\n 'd16: gamma_corrected_buf <= 'd23;\n 'd17: gamma_corrected_buf <= 'd24;\n 'd18: gamma_corrected_buf <= 'd24;\n 'd19: gamma_corrected_buf <= 'd25;\n 'd20: gamma_corrected_buf <= 'd25;\n 'd21: gamma_corrected_buf <= 'd26;\n 'd22: gamma_corrected_buf <= 'd27;\n 'd23: gamma_corrected_buf <= 'd27;\n 'd24: gamma_corrected_buf <= 'd28;\n 'd25: gamma_corrected_buf <= 'd28;\n 'd26: gamma_corrected_buf <= 'd29;\n 'd27: gamma_corrected_buf <= 'd29;\n 'd28: gamma_corrected_buf <= 'd30;\n 'd29: gamma_corrected_buf <= 'd30;\n 'd30: gamma_corrected_buf <= 'd31;\n 'd31: gamma_corrected_buf <= 'd31;\n default: gamma_corrected_buf <= 0;\n endcase\n end\nend\nreg buffer_valid;\nwire [15:0] rgb565_gray = {gamma_corrected_buf, gamma_corrected_buf, 1'b0 , gamma_corrected_buf};\nalways @(posedge clk or posedge rst) begin\n\tif(rst || ~readout_busy_in) begin\n\t\tstate_q <= SKIP_FIRST_55_PIX;\n\t\tskip_pixel_cnt <= 0; \n\t\tskip_line_cnt <= 0;\n\t\tpixel_cnt_x <= 0;\n\t\tpixel_cnt_y <= 0;\n\t\tbuffer_valid <= 0;\n\tend\n\telse if(raw_pixel_valid_in) begin\n\t\tcase (state_q)\n\t\t\tSKIP_FIRST_55_PIX: begin\n\t\t\t\tif (skip_pixel_cnt >= SKIP_INVALID_PIX) begin\n\t\t\t\t\tstate_q <= COUNT_24_PIXEL;\n\t\t\t\t\tskip_pixel_cnt <= 0;\n\t\t\t\tend\n\t\t\t\telse begin\n\t\t\t\t\tskip_pixel_cnt <= skip_pixel_cnt + 1;\n\t\t\t\tend\n\t\t\tend\n\t\t\tCOUNT_24_PIXEL: begin\n\t\t\t\tif (skip_pixel_cnt < SKIPED_PIX) begin\n\t\t\t\t\tskip_pixel_cnt <= skip_pixel_cnt + 1;\n\t\t\t\tend\n\t\t\t\telse begin\n\t\t\t\t\tstate_q <= SEND_PIXEL;\n\t\t\t\t\tbuffer_valid <= 1;\n\t\t\t\t\tskip_pixel_cnt <= 0;\n\t\t\t\tend\n\t\t\tend\n\t\t\tSEND_PIXEL: begin\n\t\t\t\tif (pixel_cnt_x < VIEWFINDER_X) begin\n\t\t\t\t\tpixel_cnt_x <= pixel_cnt_x + 1;\n\t\t\t\t\tbuffer_valid <= 0;\n\t\t\t\t\tstate_q <= COUNT_24_PIXEL;\n\t\t\t\tend\n\t\t\t\telse begin\n\t\t\t\t\tpixel_cnt_x <= 0;\n\t\t\t\t\tstate_q <= SKIP_6_LINE;\n\t\t\t\tend\n\t\t\tend\n\t\t\tSKIP_6_LINE: begin\n\t\t\t\tif (line_sync_pulse) begin\n\t\t\t\t\tif (pixel_cnt_y >= VIEWFINDER_Y) begin\n\t\t\t\t\t\tstate_q <= DONE;\n\t\t\t\t\t\tpixel_cnt_y <= 0;\n\t\t\t\t\tend\n\t\t\t\t\telse if (skip_line_cnt < SKIPED_LINE - 1) begin\n\t\t\t\t\t\tskip_line_cnt <= skip_line_cnt + 1;\n\t\t\t\t\tend\n\t\t\t\t\telse begin\n\t\t\t\t\t\tskip_line_cnt <= 0;\n\t\t\t\t\t\tpixel_cnt_y <= pixel_cnt_y + 1;\n\t\t\t\t\t\tstate_q <= COUNT_24_PIXEL;\n\t\t\t\t\tend\n\t\t\t\tend\t\n\t\t\tend\n\t\t\tDONE: begin\n\t\t\tend\n\t\t\tdefault: state_q <= DONE;\n\t\tendcase\n\tend\nend\nreg buffer_valid_ff;\nwire buffer_valid_pulse = (buffer_valid && ~buffer_valid_ff) ? 1'b1 : 1'b0 ;\nalways @(posedge clk) begin\n\tbuffer_valid_ff <= buffer_valid;\nend\nreg [31:0] axi_send_buffer;\nreg axi_send_cnt;\nreg axi_send_pulse;\nassign axi_data_buffer_o = axi_send_buffer;\nassign axi_send_pulse_o = axi_send_pulse;\nalways @(posedge clk or posedge rst) begin\n\tif (rst) begin\n\t\taxi_send_buffer <= 0;\n\t\taxi_send_pulse <= 0;\n\t\taxi_send_cnt <= 0;\n\tend\n\telse begin\n\t\tif (buffer_valid_pulse) begin\n\t\t\taxi_send_buffer <= {axi_send_buffer[15:0],rgb565_gray};\n\t\tend\t\n\t\tif (buffer_valid_pulse) begin\n\t\t\taxi_send_cnt <= axi_send_cnt + 1;\n\t\tend\n\t\tif (axi_send_cnt && buffer_valid_pulse) begin\n\t\t\taxi_send_pulse <= 1;\n\t\tend\n\t\telse begin\n\t\t\taxi_send_pulse <= 0;\n\t\tend\n\tend \nend\nendmodule", "code_description": null, "fill_type": "CLASS_TYPE", "language_type": "verilog", "sub_task_type": null}, "context_code": [], "task_instance_info": {"created_time": "2025-08-21 04:22:24", "created_task_model": "DeepSeek-R1", "class_skeleton": "module line_skipper (\n\t\tinput wire clk,\n\t\tinput wire rst,\n\t\t\n\t\t//pixel input\n\t\tinput wire [15:0] raw_pixel_in,\n\t\tinput wire raw_pixel_valid_in,\n\t\tinput wire readout_busy_in,\n\t\tinput wire line_sync,\n\t\t\n\t\toutput wire [31:0] axi_data_buffer_o,\n\t\toutput wire axi_send_pulse_o\n) ; endmodule", "code_description": "This code segment functions to: Process incoming pixel data streams by applying gamma correction transformations, selectively skipping specified quantities of initial pixels and periodic line intervals while accumulating valid image data into 32-bit output buffers for subsequent transmission when threshold conditions are met."}, "inference_content": {"inference_model": "DeepSeek-R1", "inference_result": "```verilog\n[TASK_BEGIN]\nmodule line_skipper (\n input wire clk,\n input wire rst,\n \n //pixel input\n input wire [15:0] raw_pixel_in,\n input wire raw_pixel_valid_in,\n input wire readout_busy_in,\n input wire line_sync,\n \n output wire [31:0] axi_data_buffer_o,\n output wire axi_send_pulse_o\n);\n\n reg skip_line;\n reg [15:0] pixel_buffer;\n reg pixel_counter;\n reg [31:0] data_buffer;\n reg send_pulse;\n\n always @(posedge clk or posedge rst) begin\n if (rst) begin\n skip_line <= 1'b0;\n pixel_buffer <= 16'b0;\n pixel_counter <= 1'b0;\n data_buffer <= 32'b0;\n send_pulse <= 1'b0;\n end else begin\n send_pulse <= 1'b0;\n \n if (line_sync) begin\n // Update skip flag at line start\n skip_line <= readout_busy_in;\n pixel_counter <= 1'b0;\n end \n else if (!skip_line && raw_pixel_valid_in) begin\n if (pixel_counter == 1'b0) begin\n // Store first pixel\n pixel_buffer <= raw_pixel_in;\n pixel_counter <= 1'b1;\n end else begin\n // Combine and send when both pixels are received\n data_buffer <= {pixel_buffer, raw_pixel_in};\n send_pulse <= 1'b1;\n pixel_counter <= 1'b0;\n end\n end\n end\n end\n\n assign axi_data_buffer_o = data_buffer;\n assign axi_send_pulse_o = send_pulse;\n\nendmodule\n[TASK_END]\n```", "inference_time": "2025-08-21 04-24-01"}, "editdistance_info": {"edit_distance": 10.9464, "calculate_time": "2025-08-21 04:24:01", "true_code_clean": "module line_skipper(\n\t\tinput wire clk,\n\t\tinput wire rst,\n\t\tinput wire [15:0] raw_pixel_in,\n\t\tinput wire raw_pixel_valid_in,\n\t\tinput wire readout_busy_in,\n\t\tinput wire line_sync,\n\t\toutput wire [31:0] axi_data_buffer_o,\n\t\toutput wire axi_send_pulse_o\n);\nreg line_sync_ff1;\nreg line_sync_ff2;\nwire line_sync_pulse = (line_sync_ff1 && ~line_sync_ff2) ? 1'b1 : 1'b0;\nalways @(posedge clk ) begin\n\tif(raw_pixel_valid_in) begin\n\t\tline_sync_ff1 <= line_sync;\n\t\tline_sync_ff2 <= line_sync_ff1;\n\tend\nend\n(* MARK_DEBUG=\"true\" *)reg [15:0] skip_pixel_cnt;\n(* MARK_DEBUG=\"true\" *)reg [15:0] skip_line_cnt;\n(* MARK_DEBUG=\"true\" *)reg [7:0] pixel_cnt_x;\n(* MARK_DEBUG=\"true\" *)reg [7:0] pixel_cnt_y;\n(* MARK_DEBUG=\"true\" *) reg [3:0] state_q;\nparameter SKIP_FIRST_55_PIX = 4'b0000;\nparameter COUNT_24_PIXEL = 4'b0001;\nparameter SEND_PIXEL = 4'b0011;\nparameter SKIP_6_LINE = 4'b0010;\nparameter DONE = 4'b0110;\nlocalparam SKIP_INVALID_PIX = 55;\nlocalparam TOTAL_LINE = 1024;\nlocalparam PIXEL_PER_LINE = 5760;\nlocalparam SKIPED_PIX = 24;\nlocalparam SKIPED_LINE = 6;\nlocalparam VIEWFINDER_X = 240;\nlocalparam VIEWFINDER_Y = 160;\nreg [4:0] gamma_corrected_buf;\nalways @(posedge clk or posedge rst) begin\n if(rst || ~readout_busy_in)begin\n gamma_corrected_buf <= 0;\n end\n else if(raw_pixel_valid_in) begin\n case (raw_pixel_in[15:11])\n 'd00: gamma_corrected_buf <= 'd00;\n 'd01: gamma_corrected_buf <= 'd07;\n 'd02: gamma_corrected_buf <= 'd09;\n 'd03: gamma_corrected_buf <= 'd11;\n 'd04: gamma_corrected_buf <= 'd12;\n 'd05: gamma_corrected_buf <= 'd14;\n 'd06: gamma_corrected_buf <= 'd15;\n 'd07: gamma_corrected_buf <= 'd16;\n 'd08: gamma_corrected_buf <= 'd17;\n 'd09: gamma_corrected_buf <= 'd18;\n 'd10: gamma_corrected_buf <= 'd19;\n 'd11: gamma_corrected_buf <= 'd19;\n 'd12: gamma_corrected_buf <= 'd20;\n 'd13: gamma_corrected_buf <= 'd21;\n 'd14: gamma_corrected_buf <= 'd22;\n 'd15: gamma_corrected_buf <= 'd22;\n 'd16: gamma_corrected_buf <= 'd23;\n 'd17: gamma_corrected_buf <= 'd24;\n 'd18: gamma_corrected_buf <= 'd24;\n 'd19: gamma_corrected_buf <= 'd25;\n 'd20: gamma_corrected_buf <= 'd25;\n 'd21: gamma_corrected_buf <= 'd26;\n 'd22: gamma_corrected_buf <= 'd27;\n 'd23: gamma_corrected_buf <= 'd27;\n 'd24: gamma_corrected_buf <= 'd28;\n 'd25: gamma_corrected_buf <= 'd28;\n 'd26: gamma_corrected_buf <= 'd29;\n 'd27: gamma_corrected_buf <= 'd29;\n 'd28: gamma_corrected_buf <= 'd30;\n 'd29: gamma_corrected_buf <= 'd30;\n 'd30: gamma_corrected_buf <= 'd31;\n 'd31: gamma_corrected_buf <= 'd31;\n default: gamma_corrected_buf <= 0;\n endcase\n end\nend\nreg buffer_valid;\nwire [15:0] rgb565_gray = {gamma_corrected_buf, gamma_corrected_buf, 1'b0 , gamma_corrected_buf};\nalways @(posedge clk or posedge rst) begin\n\tif(rst || ~readout_busy_in) begin\n\t\tstate_q <= SKIP_FIRST_55_PIX;\n\t\tskip_pixel_cnt <= 0; \n\t\tskip_line_cnt <= 0;\n\t\tpixel_cnt_x <= 0;\n\t\tpixel_cnt_y <= 0;\n\t\tbuffer_valid <= 0;\n\tend\n\telse if(raw_pixel_valid_in) begin\n\t\tcase (state_q)\n\t\t\tSKIP_FIRST_55_PIX: begin\n\t\t\t\tif (skip_pixel_cnt >= SKIP_INVALID_PIX) begin\n\t\t\t\t\tstate_q <= COUNT_24_PIXEL;\n\t\t\t\t\tskip_pixel_cnt <= 0;\n\t\t\t\tend\n\t\t\t\telse begin\n\t\t\t\t\tskip_pixel_cnt <= skip_pixel_cnt + 1;\n\t\t\t\tend\n\t\t\tend\n\t\t\tCOUNT_24_PIXEL: begin\n\t\t\t\tif (skip_pixel_cnt < SKIPED_PIX) begin\n\t\t\t\t\tskip_pixel_cnt <= skip_pixel_cnt + 1;\n\t\t\t\tend\n\t\t\t\telse begin\n\t\t\t\t\tstate_q <= SEND_PIXEL;\n\t\t\t\t\tbuffer_valid <= 1;\n\t\t\t\t\tskip_pixel_cnt <= 0;\n\t\t\t\tend\n\t\t\tend\n\t\t\tSEND_PIXEL: begin\n\t\t\t\tif (pixel_cnt_x < VIEWFINDER_X) begin\n\t\t\t\t\tpixel_cnt_x <= pixel_cnt_x + 1;\n\t\t\t\t\tbuffer_valid <= 0;\n\t\t\t\t\tstate_q <= COUNT_24_PIXEL;\n\t\t\t\tend\n\t\t\t\telse begin\n\t\t\t\t\tpixel_cnt_x <= 0;\n\t\t\t\t\tstate_q <= SKIP_6_LINE;\n\t\t\t\tend\n\t\t\tend\n\t\t\tSKIP_6_LINE: begin\n\t\t\t\tif (line_sync_pulse) begin\n\t\t\t\t\tif (pixel_cnt_y >= VIEWFINDER_Y) begin\n\t\t\t\t\t\tstate_q <= DONE;\n\t\t\t\t\t\tpixel_cnt_y <= 0;\n\t\t\t\t\tend\n\t\t\t\t\telse if (skip_line_cnt < SKIPED_LINE - 1) begin\n\t\t\t\t\t\tskip_line_cnt <= skip_line_cnt + 1;\n\t\t\t\t\tend\n\t\t\t\t\telse begin\n\t\t\t\t\t\tskip_line_cnt <= 0;\n\t\t\t\t\t\tpixel_cnt_y <= pixel_cnt_y + 1;\n\t\t\t\t\t\tstate_q <= COUNT_24_PIXEL;\n\t\t\t\t\tend\n\t\t\t\tend\t\n\t\t\tend\n\t\t\tDONE: begin\n\t\t\tend\n\t\t\tdefault: state_q <= DONE;\n\t\tendcase\n\tend\nend\nreg buffer_valid_ff;\nwire buffer_valid_pulse = (buffer_valid && ~buffer_valid_ff) ? 1'b1 : 1'b0 ;\nalways @(posedge clk) begin\n\tbuffer_valid_ff <= buffer_valid;\nend\nreg [31:0] axi_send_buffer;\nreg axi_send_cnt;\nreg axi_send_pulse;\nassign axi_data_buffer_o = axi_send_buffer;\nassign axi_send_pulse_o = axi_send_pulse;\nalways @(posedge clk or posedge rst) begin\n\tif (rst) begin\n\t\taxi_send_buffer <= 0;\n\t\taxi_send_pulse <= 0;\n\t\taxi_send_cnt <= 0;\n\tend\n\telse begin\n\t\tif (buffer_valid_pulse) begin\n\t\t\taxi_send_buffer <= {axi_send_buffer[15:0],rgb565_gray};\n\t\tend\t\n\t\tif (buffer_valid_pulse) begin\n\t\t\taxi_send_cnt <= axi_send_cnt + 1;\n\t\tend\n\t\tif (axi_send_cnt && buffer_valid_pulse) begin\n\t\t\taxi_send_pulse <= 1;\n\t\tend\n\t\telse begin\n\t\t\taxi_send_pulse <= 0;\n\t\tend\n\tend \nend\nendmodule", "predict_code_clean": "module line_skipper (\n input wire clk,\n input wire rst,\n input wire [15:0] raw_pixel_in,\n input wire raw_pixel_valid_in,\n input wire readout_busy_in,\n input wire line_sync,\n output wire [31:0] axi_data_buffer_o,\n output wire axi_send_pulse_o\n);\n reg skip_line;\n reg [15:0] pixel_buffer;\n reg pixel_counter;\n reg [31:0] data_buffer;\n reg send_pulse;\n always @(posedge clk or posedge rst) begin\n if (rst) begin\n skip_line <= 1'b0;\n pixel_buffer <= 16'b0;\n pixel_counter <= 1'b0;\n data_buffer <= 32'b0;\n send_pulse <= 1'b0;\n end else begin\n send_pulse <= 1'b0;\n if (line_sync) begin\n skip_line <= readout_busy_in;\n pixel_counter <= 1'b0;\n end \n else if (!skip_line && raw_pixel_valid_in) begin\n if (pixel_counter == 1'b0) begin\n pixel_buffer <= raw_pixel_in;\n pixel_counter <= 1'b1;\n end else begin\n data_buffer <= {pixel_buffer, raw_pixel_in};\n send_pulse <= 1'b1;\n pixel_counter <= 1'b0;\n end\n end\n end\n end\n assign axi_data_buffer_o = data_buffer;\n assign axi_send_pulse_o = send_pulse;\nendmodule"}}
3
+ {"repo_name": "ICX453_CCD_Mirrorless_Camera", "file_name": "/ICX453_CCD_Mirrorless_Camera/line_skipper.v", "inference_info": {"prefix_code": "`timescale 1ns / 1ps\n\n", "suffix_code": "\n", "middle_code": "module line_skipper(\n\t\tinput wire clk,\n\t\tinput wire rst,\n\t\tinput wire [15:0] raw_pixel_in,\n\t\tinput wire raw_pixel_valid_in,\n\t\tinput wire readout_busy_in,\n\t\tinput wire line_sync,\n\t\toutput wire [31:0] axi_data_buffer_o,\n\t\toutput wire axi_send_pulse_o\n);\nreg line_sync_ff1;\nreg line_sync_ff2;\nwire line_sync_pulse = (line_sync_ff1 && ~line_sync_ff2) ? 1'b1 : 1'b0;\nalways @(posedge clk ) begin\n\tif(raw_pixel_valid_in) begin\n\t\tline_sync_ff1 <= line_sync;\n\t\tline_sync_ff2 <= line_sync_ff1;\n\tend\nend\n(* MARK_DEBUG=\"true\" *)reg [15:0] skip_pixel_cnt;\n(* MARK_DEBUG=\"true\" *)reg [15:0] skip_line_cnt;\n(* MARK_DEBUG=\"true\" *)reg [7:0] pixel_cnt_x;\n(* MARK_DEBUG=\"true\" *)reg [7:0] pixel_cnt_y;\n(* MARK_DEBUG=\"true\" *) reg [3:0] state_q;\nparameter SKIP_FIRST_55_PIX = 4'b0000;\nparameter COUNT_24_PIXEL = 4'b0001;\nparameter SEND_PIXEL = 4'b0011;\nparameter SKIP_6_LINE = 4'b0010;\nparameter DONE = 4'b0110;\nlocalparam SKIP_INVALID_PIX = 55;\nlocalparam TOTAL_LINE = 1024;\nlocalparam PIXEL_PER_LINE = 5760;\nlocalparam SKIPED_PIX = 24;\nlocalparam SKIPED_LINE = 6;\nlocalparam VIEWFINDER_X = 240;\nlocalparam VIEWFINDER_Y = 160;\nreg [4:0] gamma_corrected_buf;\nalways @(posedge clk or posedge rst) begin\n if(rst || ~readout_busy_in)begin\n gamma_corrected_buf <= 0;\n end\n else if(raw_pixel_valid_in) begin\n case (raw_pixel_in[15:11])\n 'd00: gamma_corrected_buf <= 'd00;\n 'd01: gamma_corrected_buf <= 'd07;\n 'd02: gamma_corrected_buf <= 'd09;\n 'd03: gamma_corrected_buf <= 'd11;\n 'd04: gamma_corrected_buf <= 'd12;\n 'd05: gamma_corrected_buf <= 'd14;\n 'd06: gamma_corrected_buf <= 'd15;\n 'd07: gamma_corrected_buf <= 'd16;\n 'd08: gamma_corrected_buf <= 'd17;\n 'd09: gamma_corrected_buf <= 'd18;\n 'd10: gamma_corrected_buf <= 'd19;\n 'd11: gamma_corrected_buf <= 'd19;\n 'd12: gamma_corrected_buf <= 'd20;\n 'd13: gamma_corrected_buf <= 'd21;\n 'd14: gamma_corrected_buf <= 'd22;\n 'd15: gamma_corrected_buf <= 'd22;\n 'd16: gamma_corrected_buf <= 'd23;\n 'd17: gamma_corrected_buf <= 'd24;\n 'd18: gamma_corrected_buf <= 'd24;\n 'd19: gamma_corrected_buf <= 'd25;\n 'd20: gamma_corrected_buf <= 'd25;\n 'd21: gamma_corrected_buf <= 'd26;\n 'd22: gamma_corrected_buf <= 'd27;\n 'd23: gamma_corrected_buf <= 'd27;\n 'd24: gamma_corrected_buf <= 'd28;\n 'd25: gamma_corrected_buf <= 'd28;\n 'd26: gamma_corrected_buf <= 'd29;\n 'd27: gamma_corrected_buf <= 'd29;\n 'd28: gamma_corrected_buf <= 'd30;\n 'd29: gamma_corrected_buf <= 'd30;\n 'd30: gamma_corrected_buf <= 'd31;\n 'd31: gamma_corrected_buf <= 'd31;\n default: gamma_corrected_buf <= 0;\n endcase\n end\nend\nreg buffer_valid;\nwire [15:0] rgb565_gray = {gamma_corrected_buf, gamma_corrected_buf, 1'b0 , gamma_corrected_buf};\nalways @(posedge clk or posedge rst) begin\n\tif(rst || ~readout_busy_in) begin\n\t\tstate_q <= SKIP_FIRST_55_PIX;\n\t\tskip_pixel_cnt <= 0; \n\t\tskip_line_cnt <= 0;\n\t\tpixel_cnt_x <= 0;\n\t\tpixel_cnt_y <= 0;\n\t\tbuffer_valid <= 0;\n\tend\n\telse if(raw_pixel_valid_in) begin\n\t\tcase (state_q)\n\t\t\tSKIP_FIRST_55_PIX: begin\n\t\t\t\tif (skip_pixel_cnt >= SKIP_INVALID_PIX) begin\n\t\t\t\t\tstate_q <= COUNT_24_PIXEL;\n\t\t\t\t\tskip_pixel_cnt <= 0;\n\t\t\t\tend\n\t\t\t\telse begin\n\t\t\t\t\tskip_pixel_cnt <= skip_pixel_cnt + 1;\n\t\t\t\tend\n\t\t\tend\n\t\t\tCOUNT_24_PIXEL: begin\n\t\t\t\tif (skip_pixel_cnt < SKIPED_PIX) begin\n\t\t\t\t\tskip_pixel_cnt <= skip_pixel_cnt + 1;\n\t\t\t\tend\n\t\t\t\telse begin\n\t\t\t\t\tstate_q <= SEND_PIXEL;\n\t\t\t\t\tbuffer_valid <= 1;\n\t\t\t\t\tskip_pixel_cnt <= 0;\n\t\t\t\tend\n\t\t\tend\n\t\t\tSEND_PIXEL: begin\n\t\t\t\tif (pixel_cnt_x < VIEWFINDER_X) begin\n\t\t\t\t\tpixel_cnt_x <= pixel_cnt_x + 1;\n\t\t\t\t\tbuffer_valid <= 0;\n\t\t\t\t\tstate_q <= COUNT_24_PIXEL;\n\t\t\t\tend\n\t\t\t\telse begin\n\t\t\t\t\tpixel_cnt_x <= 0;\n\t\t\t\t\tstate_q <= SKIP_6_LINE;\n\t\t\t\tend\n\t\t\tend\n\t\t\tSKIP_6_LINE: begin\n\t\t\t\tif (line_sync_pulse) begin\n\t\t\t\t\tif (pixel_cnt_y >= VIEWFINDER_Y) begin\n\t\t\t\t\t\tstate_q <= DONE;\n\t\t\t\t\t\tpixel_cnt_y <= 0;\n\t\t\t\t\tend\n\t\t\t\t\telse if (skip_line_cnt < SKIPED_LINE - 1) begin\n\t\t\t\t\t\tskip_line_cnt <= skip_line_cnt + 1;\n\t\t\t\t\tend\n\t\t\t\t\telse begin\n\t\t\t\t\t\tskip_line_cnt <= 0;\n\t\t\t\t\t\tpixel_cnt_y <= pixel_cnt_y + 1;\n\t\t\t\t\t\tstate_q <= COUNT_24_PIXEL;\n\t\t\t\t\tend\n\t\t\t\tend\t\n\t\t\tend\n\t\t\tDONE: begin\n\t\t\tend\n\t\t\tdefault: state_q <= DONE;\n\t\tendcase\n\tend\nend\nreg buffer_valid_ff;\nwire buffer_valid_pulse = (buffer_valid && ~buffer_valid_ff) ? 1'b1 : 1'b0 ;\nalways @(posedge clk) begin\n\tbuffer_valid_ff <= buffer_valid;\nend\nreg [31:0] axi_send_buffer;\nreg axi_send_cnt;\nreg axi_send_pulse;\nassign axi_data_buffer_o = axi_send_buffer;\nassign axi_send_pulse_o = axi_send_pulse;\nalways @(posedge clk or posedge rst) begin\n\tif (rst) begin\n\t\taxi_send_buffer <= 0;\n\t\taxi_send_pulse <= 0;\n\t\taxi_send_cnt <= 0;\n\tend\n\telse begin\n\t\tif (buffer_valid_pulse) begin\n\t\t\taxi_send_buffer <= {axi_send_buffer[15:0],rgb565_gray};\n\t\tend\t\n\t\tif (buffer_valid_pulse) begin\n\t\t\taxi_send_cnt <= axi_send_cnt + 1;\n\t\tend\n\t\tif (axi_send_cnt && buffer_valid_pulse) begin\n\t\t\taxi_send_pulse <= 1;\n\t\tend\n\t\telse begin\n\t\t\taxi_send_pulse <= 0;\n\t\tend\n\tend \nend\nendmodule", "code_description": null, "fill_type": "CLASS_TYPE", "language_type": "verilog", "sub_task_type": null}, "context_code": [], "task_instance_info": {"created_time": "2025-08-21 04:22:24", "created_task_model": "DeepSeek-R1", "class_skeleton": "module line_skipper (\n\t\tinput wire clk,\n\t\tinput wire rst,\n\t\t\n\t\t//pixel input\n\t\tinput wire [15:0] raw_pixel_in,\n\t\tinput wire raw_pixel_valid_in,\n\t\tinput wire readout_busy_in,\n\t\tinput wire line_sync,\n\t\t\n\t\toutput wire [31:0] axi_data_buffer_o,\n\t\toutput wire axi_send_pulse_o\n) ; endmodule", "code_description": "This code segment functions to: Process digital image data streams by implementing gamma correction on pixel values, selectively skipping specified quantities of initial pixels and periodic lines to achieve viewport cropping, while packaging processed grayscale information into transmission-ready packets with synchronization signals for external interface handling."}, "inference_content": {"inference_model": "DeepSeek-R1", "inference_result": "```verilog\n[TASK_BEGIN]\nmodule line_skipper (\n\t\tinput wire clk,\n\t\tinput wire rst,\n\t\t\n\t\t//pixel input\n\t\tinput wire [15:0] raw_pixel_in,\n\t\tinput wire raw_pixel_valid_in,\n\t\tinput wire readout_busy_in,\n\t\tinput wire line_sync,\n\t\t\n\t\toutput wire [31:0] axi_data_buffer_o,\n\t\toutput wire axi_send_pulse_o\n);\n reg line_sync_prev;\n reg line_active;\n reg [31:0] data_buffer;\n reg pixel_counter; // 0 or 1\n reg send_pulse;\n\n assign axi_data_buffer_o = data_buffer;\n assign axi_send_pulse_o = send_pulse;\n\n always @(posedge clk) begin\n if (rst) begin\n line_sync_prev <= 0;\n line_active <= 0;\n data_buffer <= 0;\n pixel_counter <= 0;\n send_pulse <= 0;\n end else begin\n line_sync_prev <= line_sync;\n send_pulse <= 0;\n\n // Line sync edge detection\n if (line_sync && !line_sync_prev) begin\n line_active <= !readout_busy_in;\n pixel_counter <= 0;\n data_buffer <= 0;\n end\n\n // Pixel processing\n if (line_active && raw_pixel_valid_in) begin\n if (pixel_counter) begin\n data_buffer[15:0] <= raw_pixel_in;\n send_pulse <= 1;\n end else begin\n data_buffer[31:16] <= raw_pixel_in;\n end\n pixel_counter <= ~pixel_counter;\n end\n end\n end\nendmodule\n[TASK_END]\n```", "inference_time": "2025-08-21 04-24-19"}, "editdistance_info": {"edit_distance": 10.6043, "calculate_time": "2025-08-21 04:24:19", "true_code_clean": "module line_skipper(\n\t\tinput wire clk,\n\t\tinput wire rst,\n\t\tinput wire [15:0] raw_pixel_in,\n\t\tinput wire raw_pixel_valid_in,\n\t\tinput wire readout_busy_in,\n\t\tinput wire line_sync,\n\t\toutput wire [31:0] axi_data_buffer_o,\n\t\toutput wire axi_send_pulse_o\n);\nreg line_sync_ff1;\nreg line_sync_ff2;\nwire line_sync_pulse = (line_sync_ff1 && ~line_sync_ff2) ? 1'b1 : 1'b0;\nalways @(posedge clk ) begin\n\tif(raw_pixel_valid_in) begin\n\t\tline_sync_ff1 <= line_sync;\n\t\tline_sync_ff2 <= line_sync_ff1;\n\tend\nend\n(* MARK_DEBUG=\"true\" *)reg [15:0] skip_pixel_cnt;\n(* MARK_DEBUG=\"true\" *)reg [15:0] skip_line_cnt;\n(* MARK_DEBUG=\"true\" *)reg [7:0] pixel_cnt_x;\n(* MARK_DEBUG=\"true\" *)reg [7:0] pixel_cnt_y;\n(* MARK_DEBUG=\"true\" *) reg [3:0] state_q;\nparameter SKIP_FIRST_55_PIX = 4'b0000;\nparameter COUNT_24_PIXEL = 4'b0001;\nparameter SEND_PIXEL = 4'b0011;\nparameter SKIP_6_LINE = 4'b0010;\nparameter DONE = 4'b0110;\nlocalparam SKIP_INVALID_PIX = 55;\nlocalparam TOTAL_LINE = 1024;\nlocalparam PIXEL_PER_LINE = 5760;\nlocalparam SKIPED_PIX = 24;\nlocalparam SKIPED_LINE = 6;\nlocalparam VIEWFINDER_X = 240;\nlocalparam VIEWFINDER_Y = 160;\nreg [4:0] gamma_corrected_buf;\nalways @(posedge clk or posedge rst) begin\n if(rst || ~readout_busy_in)begin\n gamma_corrected_buf <= 0;\n end\n else if(raw_pixel_valid_in) begin\n case (raw_pixel_in[15:11])\n 'd00: gamma_corrected_buf <= 'd00;\n 'd01: gamma_corrected_buf <= 'd07;\n 'd02: gamma_corrected_buf <= 'd09;\n 'd03: gamma_corrected_buf <= 'd11;\n 'd04: gamma_corrected_buf <= 'd12;\n 'd05: gamma_corrected_buf <= 'd14;\n 'd06: gamma_corrected_buf <= 'd15;\n 'd07: gamma_corrected_buf <= 'd16;\n 'd08: gamma_corrected_buf <= 'd17;\n 'd09: gamma_corrected_buf <= 'd18;\n 'd10: gamma_corrected_buf <= 'd19;\n 'd11: gamma_corrected_buf <= 'd19;\n 'd12: gamma_corrected_buf <= 'd20;\n 'd13: gamma_corrected_buf <= 'd21;\n 'd14: gamma_corrected_buf <= 'd22;\n 'd15: gamma_corrected_buf <= 'd22;\n 'd16: gamma_corrected_buf <= 'd23;\n 'd17: gamma_corrected_buf <= 'd24;\n 'd18: gamma_corrected_buf <= 'd24;\n 'd19: gamma_corrected_buf <= 'd25;\n 'd20: gamma_corrected_buf <= 'd25;\n 'd21: gamma_corrected_buf <= 'd26;\n 'd22: gamma_corrected_buf <= 'd27;\n 'd23: gamma_corrected_buf <= 'd27;\n 'd24: gamma_corrected_buf <= 'd28;\n 'd25: gamma_corrected_buf <= 'd28;\n 'd26: gamma_corrected_buf <= 'd29;\n 'd27: gamma_corrected_buf <= 'd29;\n 'd28: gamma_corrected_buf <= 'd30;\n 'd29: gamma_corrected_buf <= 'd30;\n 'd30: gamma_corrected_buf <= 'd31;\n 'd31: gamma_corrected_buf <= 'd31;\n default: gamma_corrected_buf <= 0;\n endcase\n end\nend\nreg buffer_valid;\nwire [15:0] rgb565_gray = {gamma_corrected_buf, gamma_corrected_buf, 1'b0 , gamma_corrected_buf};\nalways @(posedge clk or posedge rst) begin\n\tif(rst || ~readout_busy_in) begin\n\t\tstate_q <= SKIP_FIRST_55_PIX;\n\t\tskip_pixel_cnt <= 0; \n\t\tskip_line_cnt <= 0;\n\t\tpixel_cnt_x <= 0;\n\t\tpixel_cnt_y <= 0;\n\t\tbuffer_valid <= 0;\n\tend\n\telse if(raw_pixel_valid_in) begin\n\t\tcase (state_q)\n\t\t\tSKIP_FIRST_55_PIX: begin\n\t\t\t\tif (skip_pixel_cnt >= SKIP_INVALID_PIX) begin\n\t\t\t\t\tstate_q <= COUNT_24_PIXEL;\n\t\t\t\t\tskip_pixel_cnt <= 0;\n\t\t\t\tend\n\t\t\t\telse begin\n\t\t\t\t\tskip_pixel_cnt <= skip_pixel_cnt + 1;\n\t\t\t\tend\n\t\t\tend\n\t\t\tCOUNT_24_PIXEL: begin\n\t\t\t\tif (skip_pixel_cnt < SKIPED_PIX) begin\n\t\t\t\t\tskip_pixel_cnt <= skip_pixel_cnt + 1;\n\t\t\t\tend\n\t\t\t\telse begin\n\t\t\t\t\tstate_q <= SEND_PIXEL;\n\t\t\t\t\tbuffer_valid <= 1;\n\t\t\t\t\tskip_pixel_cnt <= 0;\n\t\t\t\tend\n\t\t\tend\n\t\t\tSEND_PIXEL: begin\n\t\t\t\tif (pixel_cnt_x < VIEWFINDER_X) begin\n\t\t\t\t\tpixel_cnt_x <= pixel_cnt_x + 1;\n\t\t\t\t\tbuffer_valid <= 0;\n\t\t\t\t\tstate_q <= COUNT_24_PIXEL;\n\t\t\t\tend\n\t\t\t\telse begin\n\t\t\t\t\tpixel_cnt_x <= 0;\n\t\t\t\t\tstate_q <= SKIP_6_LINE;\n\t\t\t\tend\n\t\t\tend\n\t\t\tSKIP_6_LINE: begin\n\t\t\t\tif (line_sync_pulse) begin\n\t\t\t\t\tif (pixel_cnt_y >= VIEWFINDER_Y) begin\n\t\t\t\t\t\tstate_q <= DONE;\n\t\t\t\t\t\tpixel_cnt_y <= 0;\n\t\t\t\t\tend\n\t\t\t\t\telse if (skip_line_cnt < SKIPED_LINE - 1) begin\n\t\t\t\t\t\tskip_line_cnt <= skip_line_cnt + 1;\n\t\t\t\t\tend\n\t\t\t\t\telse begin\n\t\t\t\t\t\tskip_line_cnt <= 0;\n\t\t\t\t\t\tpixel_cnt_y <= pixel_cnt_y + 1;\n\t\t\t\t\t\tstate_q <= COUNT_24_PIXEL;\n\t\t\t\t\tend\n\t\t\t\tend\t\n\t\t\tend\n\t\t\tDONE: begin\n\t\t\tend\n\t\t\tdefault: state_q <= DONE;\n\t\tendcase\n\tend\nend\nreg buffer_valid_ff;\nwire buffer_valid_pulse = (buffer_valid && ~buffer_valid_ff) ? 1'b1 : 1'b0 ;\nalways @(posedge clk) begin\n\tbuffer_valid_ff <= buffer_valid;\nend\nreg [31:0] axi_send_buffer;\nreg axi_send_cnt;\nreg axi_send_pulse;\nassign axi_data_buffer_o = axi_send_buffer;\nassign axi_send_pulse_o = axi_send_pulse;\nalways @(posedge clk or posedge rst) begin\n\tif (rst) begin\n\t\taxi_send_buffer <= 0;\n\t\taxi_send_pulse <= 0;\n\t\taxi_send_cnt <= 0;\n\tend\n\telse begin\n\t\tif (buffer_valid_pulse) begin\n\t\t\taxi_send_buffer <= {axi_send_buffer[15:0],rgb565_gray};\n\t\tend\t\n\t\tif (buffer_valid_pulse) begin\n\t\t\taxi_send_cnt <= axi_send_cnt + 1;\n\t\tend\n\t\tif (axi_send_cnt && buffer_valid_pulse) begin\n\t\t\taxi_send_pulse <= 1;\n\t\tend\n\t\telse begin\n\t\t\taxi_send_pulse <= 0;\n\t\tend\n\tend \nend\nendmodule", "predict_code_clean": "module line_skipper (\n\t\tinput wire clk,\n\t\tinput wire rst,\n\t\tinput wire [15:0] raw_pixel_in,\n\t\tinput wire raw_pixel_valid_in,\n\t\tinput wire readout_busy_in,\n\t\tinput wire line_sync,\n\t\toutput wire [31:0] axi_data_buffer_o,\n\t\toutput wire axi_send_pulse_o\n);\n reg line_sync_prev;\n reg line_active;\n reg [31:0] data_buffer;\n reg pixel_counter; \n reg send_pulse;\n assign axi_data_buffer_o = data_buffer;\n assign axi_send_pulse_o = send_pulse;\n always @(posedge clk) begin\n if (rst) begin\n line_sync_prev <= 0;\n line_active <= 0;\n data_buffer <= 0;\n pixel_counter <= 0;\n send_pulse <= 0;\n end else begin\n line_sync_prev <= line_sync;\n send_pulse <= 0;\n if (line_sync && !line_sync_prev) begin\n line_active <= !readout_busy_in;\n pixel_counter <= 0;\n data_buffer <= 0;\n end\n if (line_active && raw_pixel_valid_in) begin\n if (pixel_counter) begin\n data_buffer[15:0] <= raw_pixel_in;\n send_pulse <= 1;\n end else begin\n data_buffer[31:16] <= raw_pixel_in;\n end\n pixel_counter <= ~pixel_counter;\n end\n end\n end\nendmodule"}}
4
+ {"repo_name": "ICX453_CCD_Mirrorless_Camera", "file_name": "/ICX453_CCD_Mirrorless_Camera/line_skipper.v", "inference_info": {"prefix_code": "`timescale 1ns / 1ps\n\n", "suffix_code": "\n", "middle_code": "module line_skipper(\n\t\tinput wire clk,\n\t\tinput wire rst,\n\t\tinput wire [15:0] raw_pixel_in,\n\t\tinput wire raw_pixel_valid_in,\n\t\tinput wire readout_busy_in,\n\t\tinput wire line_sync,\n\t\toutput wire [31:0] axi_data_buffer_o,\n\t\toutput wire axi_send_pulse_o\n);\nreg line_sync_ff1;\nreg line_sync_ff2;\nwire line_sync_pulse = (line_sync_ff1 && ~line_sync_ff2) ? 1'b1 : 1'b0;\nalways @(posedge clk ) begin\n\tif(raw_pixel_valid_in) begin\n\t\tline_sync_ff1 <= line_sync;\n\t\tline_sync_ff2 <= line_sync_ff1;\n\tend\nend\n(* MARK_DEBUG=\"true\" *)reg [15:0] skip_pixel_cnt;\n(* MARK_DEBUG=\"true\" *)reg [15:0] skip_line_cnt;\n(* MARK_DEBUG=\"true\" *)reg [7:0] pixel_cnt_x;\n(* MARK_DEBUG=\"true\" *)reg [7:0] pixel_cnt_y;\n(* MARK_DEBUG=\"true\" *) reg [3:0] state_q;\nparameter SKIP_FIRST_55_PIX = 4'b0000;\nparameter COUNT_24_PIXEL = 4'b0001;\nparameter SEND_PIXEL = 4'b0011;\nparameter SKIP_6_LINE = 4'b0010;\nparameter DONE = 4'b0110;\nlocalparam SKIP_INVALID_PIX = 55;\nlocalparam TOTAL_LINE = 1024;\nlocalparam PIXEL_PER_LINE = 5760;\nlocalparam SKIPED_PIX = 24;\nlocalparam SKIPED_LINE = 6;\nlocalparam VIEWFINDER_X = 240;\nlocalparam VIEWFINDER_Y = 160;\nreg [4:0] gamma_corrected_buf;\nalways @(posedge clk or posedge rst) begin\n if(rst || ~readout_busy_in)begin\n gamma_corrected_buf <= 0;\n end\n else if(raw_pixel_valid_in) begin\n case (raw_pixel_in[15:11])\n 'd00: gamma_corrected_buf <= 'd00;\n 'd01: gamma_corrected_buf <= 'd07;\n 'd02: gamma_corrected_buf <= 'd09;\n 'd03: gamma_corrected_buf <= 'd11;\n 'd04: gamma_corrected_buf <= 'd12;\n 'd05: gamma_corrected_buf <= 'd14;\n 'd06: gamma_corrected_buf <= 'd15;\n 'd07: gamma_corrected_buf <= 'd16;\n 'd08: gamma_corrected_buf <= 'd17;\n 'd09: gamma_corrected_buf <= 'd18;\n 'd10: gamma_corrected_buf <= 'd19;\n 'd11: gamma_corrected_buf <= 'd19;\n 'd12: gamma_corrected_buf <= 'd20;\n 'd13: gamma_corrected_buf <= 'd21;\n 'd14: gamma_corrected_buf <= 'd22;\n 'd15: gamma_corrected_buf <= 'd22;\n 'd16: gamma_corrected_buf <= 'd23;\n 'd17: gamma_corrected_buf <= 'd24;\n 'd18: gamma_corrected_buf <= 'd24;\n 'd19: gamma_corrected_buf <= 'd25;\n 'd20: gamma_corrected_buf <= 'd25;\n 'd21: gamma_corrected_buf <= 'd26;\n 'd22: gamma_corrected_buf <= 'd27;\n 'd23: gamma_corrected_buf <= 'd27;\n 'd24: gamma_corrected_buf <= 'd28;\n 'd25: gamma_corrected_buf <= 'd28;\n 'd26: gamma_corrected_buf <= 'd29;\n 'd27: gamma_corrected_buf <= 'd29;\n 'd28: gamma_corrected_buf <= 'd30;\n 'd29: gamma_corrected_buf <= 'd30;\n 'd30: gamma_corrected_buf <= 'd31;\n 'd31: gamma_corrected_buf <= 'd31;\n default: gamma_corrected_buf <= 0;\n endcase\n end\nend\nreg buffer_valid;\nwire [15:0] rgb565_gray = {gamma_corrected_buf, gamma_corrected_buf, 1'b0 , gamma_corrected_buf};\nalways @(posedge clk or posedge rst) begin\n\tif(rst || ~readout_busy_in) begin\n\t\tstate_q <= SKIP_FIRST_55_PIX;\n\t\tskip_pixel_cnt <= 0; \n\t\tskip_line_cnt <= 0;\n\t\tpixel_cnt_x <= 0;\n\t\tpixel_cnt_y <= 0;\n\t\tbuffer_valid <= 0;\n\tend\n\telse if(raw_pixel_valid_in) begin\n\t\tcase (state_q)\n\t\t\tSKIP_FIRST_55_PIX: begin\n\t\t\t\tif (skip_pixel_cnt >= SKIP_INVALID_PIX) begin\n\t\t\t\t\tstate_q <= COUNT_24_PIXEL;\n\t\t\t\t\tskip_pixel_cnt <= 0;\n\t\t\t\tend\n\t\t\t\telse begin\n\t\t\t\t\tskip_pixel_cnt <= skip_pixel_cnt + 1;\n\t\t\t\tend\n\t\t\tend\n\t\t\tCOUNT_24_PIXEL: begin\n\t\t\t\tif (skip_pixel_cnt < SKIPED_PIX) begin\n\t\t\t\t\tskip_pixel_cnt <= skip_pixel_cnt + 1;\n\t\t\t\tend\n\t\t\t\telse begin\n\t\t\t\t\tstate_q <= SEND_PIXEL;\n\t\t\t\t\tbuffer_valid <= 1;\n\t\t\t\t\tskip_pixel_cnt <= 0;\n\t\t\t\tend\n\t\t\tend\n\t\t\tSEND_PIXEL: begin\n\t\t\t\tif (pixel_cnt_x < VIEWFINDER_X) begin\n\t\t\t\t\tpixel_cnt_x <= pixel_cnt_x + 1;\n\t\t\t\t\tbuffer_valid <= 0;\n\t\t\t\t\tstate_q <= COUNT_24_PIXEL;\n\t\t\t\tend\n\t\t\t\telse begin\n\t\t\t\t\tpixel_cnt_x <= 0;\n\t\t\t\t\tstate_q <= SKIP_6_LINE;\n\t\t\t\tend\n\t\t\tend\n\t\t\tSKIP_6_LINE: begin\n\t\t\t\tif (line_sync_pulse) begin\n\t\t\t\t\tif (pixel_cnt_y >= VIEWFINDER_Y) begin\n\t\t\t\t\t\tstate_q <= DONE;\n\t\t\t\t\t\tpixel_cnt_y <= 0;\n\t\t\t\t\tend\n\t\t\t\t\telse if (skip_line_cnt < SKIPED_LINE - 1) begin\n\t\t\t\t\t\tskip_line_cnt <= skip_line_cnt + 1;\n\t\t\t\t\tend\n\t\t\t\t\telse begin\n\t\t\t\t\t\tskip_line_cnt <= 0;\n\t\t\t\t\t\tpixel_cnt_y <= pixel_cnt_y + 1;\n\t\t\t\t\t\tstate_q <= COUNT_24_PIXEL;\n\t\t\t\t\tend\n\t\t\t\tend\t\n\t\t\tend\n\t\t\tDONE: begin\n\t\t\tend\n\t\t\tdefault: state_q <= DONE;\n\t\tendcase\n\tend\nend\nreg buffer_valid_ff;\nwire buffer_valid_pulse = (buffer_valid && ~buffer_valid_ff) ? 1'b1 : 1'b0 ;\nalways @(posedge clk) begin\n\tbuffer_valid_ff <= buffer_valid;\nend\nreg [31:0] axi_send_buffer;\nreg axi_send_cnt;\nreg axi_send_pulse;\nassign axi_data_buffer_o = axi_send_buffer;\nassign axi_send_pulse_o = axi_send_pulse;\nalways @(posedge clk or posedge rst) begin\n\tif (rst) begin\n\t\taxi_send_buffer <= 0;\n\t\taxi_send_pulse <= 0;\n\t\taxi_send_cnt <= 0;\n\tend\n\telse begin\n\t\tif (buffer_valid_pulse) begin\n\t\t\taxi_send_buffer <= {axi_send_buffer[15:0],rgb565_gray};\n\t\tend\t\n\t\tif (buffer_valid_pulse) begin\n\t\t\taxi_send_cnt <= axi_send_cnt + 1;\n\t\tend\n\t\tif (axi_send_cnt && buffer_valid_pulse) begin\n\t\t\taxi_send_pulse <= 1;\n\t\tend\n\t\telse begin\n\t\t\taxi_send_pulse <= 0;\n\t\tend\n\tend \nend\nendmodule", "code_description": null, "fill_type": "CLASS_TYPE", "language_type": "verilog", "sub_task_type": null}, "context_code": [], "task_instance_info": {"created_time": "2025-08-21 04:22:24", "created_task_model": "DeepSeek-R1", "class_skeleton": "module line_skipper (\n\t\tinput wire clk,\n\t\tinput wire rst,\n\t\t\n\t\t//pixel input\n\t\tinput wire [15:0] raw_pixel_in,\n\t\tinput wire raw_pixel_valid_in,\n\t\tinput wire readout_busy_in,\n\t\tinput wire line_sync,\n\t\t\n\t\toutput wire [31:0] axi_data_buffer_o,\n\t\toutput wire axi_send_pulse_o\n) ; endmodule", "code_description": "This code segment functions to: Process image data streams by selectively skipping specified pixel groups and line intervals while converting input values through a gamma correction lookup table, subsequently buffering transformed grayscale data into 32-bit packets for output transmission when accumulation criteria are met."}, "inference_content": {"inference_model": "DeepSeek-R1", "inference_result": "```verilog\n[TASK_BEGIN]\nmodule line_skipper (\n input wire clk,\n input wire rst,\n \n // Pixel input\n input wire [15:0] raw_pixel_in,\n input wire raw_pixel_valid_in,\n input wire readout_busy_in,\n input wire line_sync,\n \n output wire [31:0] axi_data_buffer_o,\n output wire axi_send_pulse_o\n);\n\n reg [15:0] line_counter;\n reg skip_line;\n reg [15:0] pixel_buffer;\n reg buffer_has_data;\n reg [31:0] data_buffer;\n reg send_pulse;\n\n // Line counter and skip logic\n always @(posedge clk or posedge rst) begin\n if (rst) begin\n line_counter <= 0;\n skip_line <= 0;\n end else if (line_sync) begin\n line_counter <= line_counter + 1;\n // Skip every other line (even numbered lines)\n skip_line <= ~line_counter[0];\n end\n end\n\n // Pixel buffering logic\n always @(posedge clk or posedge rst) begin\n if (rst) begin\n pixel_buffer <= 0;\n buffer_has_data <= 0;\n data_buffer <= 0;\n send_pulse <= 0;\n end else begin\n send_pulse <= 0;\n \n if (!skip_line && raw_pixel_valid_in) begin\n if (!buffer_has_data) begin\n // Store first pixel of pair\n pixel_buffer <= raw_pixel_in;\n buffer_has_data <= 1;\n end else begin\n // Combine pixels and prepare for transmission\n data_buffer <= {pixel_buffer, raw_pixel_in};\n buffer_has_data <= 0;\n \n // Send if readout not busy\n if (!readout_busy_in) begin\n send_pulse <= 1;\n end\n end\n end\n end\n end\n\n assign axi_data_buffer_o = data_buffer;\n assign axi_send_pulse_o = send_pulse;\n\nendmodule\n[TASK_END]\n```", "inference_time": "2025-08-21 04-24-20"}, "editdistance_info": {"edit_distance": 11.6876, "calculate_time": "2025-08-21 04:24:20", "true_code_clean": "module line_skipper(\n\t\tinput wire clk,\n\t\tinput wire rst,\n\t\tinput wire [15:0] raw_pixel_in,\n\t\tinput wire raw_pixel_valid_in,\n\t\tinput wire readout_busy_in,\n\t\tinput wire line_sync,\n\t\toutput wire [31:0] axi_data_buffer_o,\n\t\toutput wire axi_send_pulse_o\n);\nreg line_sync_ff1;\nreg line_sync_ff2;\nwire line_sync_pulse = (line_sync_ff1 && ~line_sync_ff2) ? 1'b1 : 1'b0;\nalways @(posedge clk ) begin\n\tif(raw_pixel_valid_in) begin\n\t\tline_sync_ff1 <= line_sync;\n\t\tline_sync_ff2 <= line_sync_ff1;\n\tend\nend\n(* MARK_DEBUG=\"true\" *)reg [15:0] skip_pixel_cnt;\n(* MARK_DEBUG=\"true\" *)reg [15:0] skip_line_cnt;\n(* MARK_DEBUG=\"true\" *)reg [7:0] pixel_cnt_x;\n(* MARK_DEBUG=\"true\" *)reg [7:0] pixel_cnt_y;\n(* MARK_DEBUG=\"true\" *) reg [3:0] state_q;\nparameter SKIP_FIRST_55_PIX = 4'b0000;\nparameter COUNT_24_PIXEL = 4'b0001;\nparameter SEND_PIXEL = 4'b0011;\nparameter SKIP_6_LINE = 4'b0010;\nparameter DONE = 4'b0110;\nlocalparam SKIP_INVALID_PIX = 55;\nlocalparam TOTAL_LINE = 1024;\nlocalparam PIXEL_PER_LINE = 5760;\nlocalparam SKIPED_PIX = 24;\nlocalparam SKIPED_LINE = 6;\nlocalparam VIEWFINDER_X = 240;\nlocalparam VIEWFINDER_Y = 160;\nreg [4:0] gamma_corrected_buf;\nalways @(posedge clk or posedge rst) begin\n if(rst || ~readout_busy_in)begin\n gamma_corrected_buf <= 0;\n end\n else if(raw_pixel_valid_in) begin\n case (raw_pixel_in[15:11])\n 'd00: gamma_corrected_buf <= 'd00;\n 'd01: gamma_corrected_buf <= 'd07;\n 'd02: gamma_corrected_buf <= 'd09;\n 'd03: gamma_corrected_buf <= 'd11;\n 'd04: gamma_corrected_buf <= 'd12;\n 'd05: gamma_corrected_buf <= 'd14;\n 'd06: gamma_corrected_buf <= 'd15;\n 'd07: gamma_corrected_buf <= 'd16;\n 'd08: gamma_corrected_buf <= 'd17;\n 'd09: gamma_corrected_buf <= 'd18;\n 'd10: gamma_corrected_buf <= 'd19;\n 'd11: gamma_corrected_buf <= 'd19;\n 'd12: gamma_corrected_buf <= 'd20;\n 'd13: gamma_corrected_buf <= 'd21;\n 'd14: gamma_corrected_buf <= 'd22;\n 'd15: gamma_corrected_buf <= 'd22;\n 'd16: gamma_corrected_buf <= 'd23;\n 'd17: gamma_corrected_buf <= 'd24;\n 'd18: gamma_corrected_buf <= 'd24;\n 'd19: gamma_corrected_buf <= 'd25;\n 'd20: gamma_corrected_buf <= 'd25;\n 'd21: gamma_corrected_buf <= 'd26;\n 'd22: gamma_corrected_buf <= 'd27;\n 'd23: gamma_corrected_buf <= 'd27;\n 'd24: gamma_corrected_buf <= 'd28;\n 'd25: gamma_corrected_buf <= 'd28;\n 'd26: gamma_corrected_buf <= 'd29;\n 'd27: gamma_corrected_buf <= 'd29;\n 'd28: gamma_corrected_buf <= 'd30;\n 'd29: gamma_corrected_buf <= 'd30;\n 'd30: gamma_corrected_buf <= 'd31;\n 'd31: gamma_corrected_buf <= 'd31;\n default: gamma_corrected_buf <= 0;\n endcase\n end\nend\nreg buffer_valid;\nwire [15:0] rgb565_gray = {gamma_corrected_buf, gamma_corrected_buf, 1'b0 , gamma_corrected_buf};\nalways @(posedge clk or posedge rst) begin\n\tif(rst || ~readout_busy_in) begin\n\t\tstate_q <= SKIP_FIRST_55_PIX;\n\t\tskip_pixel_cnt <= 0; \n\t\tskip_line_cnt <= 0;\n\t\tpixel_cnt_x <= 0;\n\t\tpixel_cnt_y <= 0;\n\t\tbuffer_valid <= 0;\n\tend\n\telse if(raw_pixel_valid_in) begin\n\t\tcase (state_q)\n\t\t\tSKIP_FIRST_55_PIX: begin\n\t\t\t\tif (skip_pixel_cnt >= SKIP_INVALID_PIX) begin\n\t\t\t\t\tstate_q <= COUNT_24_PIXEL;\n\t\t\t\t\tskip_pixel_cnt <= 0;\n\t\t\t\tend\n\t\t\t\telse begin\n\t\t\t\t\tskip_pixel_cnt <= skip_pixel_cnt + 1;\n\t\t\t\tend\n\t\t\tend\n\t\t\tCOUNT_24_PIXEL: begin\n\t\t\t\tif (skip_pixel_cnt < SKIPED_PIX) begin\n\t\t\t\t\tskip_pixel_cnt <= skip_pixel_cnt + 1;\n\t\t\t\tend\n\t\t\t\telse begin\n\t\t\t\t\tstate_q <= SEND_PIXEL;\n\t\t\t\t\tbuffer_valid <= 1;\n\t\t\t\t\tskip_pixel_cnt <= 0;\n\t\t\t\tend\n\t\t\tend\n\t\t\tSEND_PIXEL: begin\n\t\t\t\tif (pixel_cnt_x < VIEWFINDER_X) begin\n\t\t\t\t\tpixel_cnt_x <= pixel_cnt_x + 1;\n\t\t\t\t\tbuffer_valid <= 0;\n\t\t\t\t\tstate_q <= COUNT_24_PIXEL;\n\t\t\t\tend\n\t\t\t\telse begin\n\t\t\t\t\tpixel_cnt_x <= 0;\n\t\t\t\t\tstate_q <= SKIP_6_LINE;\n\t\t\t\tend\n\t\t\tend\n\t\t\tSKIP_6_LINE: begin\n\t\t\t\tif (line_sync_pulse) begin\n\t\t\t\t\tif (pixel_cnt_y >= VIEWFINDER_Y) begin\n\t\t\t\t\t\tstate_q <= DONE;\n\t\t\t\t\t\tpixel_cnt_y <= 0;\n\t\t\t\t\tend\n\t\t\t\t\telse if (skip_line_cnt < SKIPED_LINE - 1) begin\n\t\t\t\t\t\tskip_line_cnt <= skip_line_cnt + 1;\n\t\t\t\t\tend\n\t\t\t\t\telse begin\n\t\t\t\t\t\tskip_line_cnt <= 0;\n\t\t\t\t\t\tpixel_cnt_y <= pixel_cnt_y + 1;\n\t\t\t\t\t\tstate_q <= COUNT_24_PIXEL;\n\t\t\t\t\tend\n\t\t\t\tend\t\n\t\t\tend\n\t\t\tDONE: begin\n\t\t\tend\n\t\t\tdefault: state_q <= DONE;\n\t\tendcase\n\tend\nend\nreg buffer_valid_ff;\nwire buffer_valid_pulse = (buffer_valid && ~buffer_valid_ff) ? 1'b1 : 1'b0 ;\nalways @(posedge clk) begin\n\tbuffer_valid_ff <= buffer_valid;\nend\nreg [31:0] axi_send_buffer;\nreg axi_send_cnt;\nreg axi_send_pulse;\nassign axi_data_buffer_o = axi_send_buffer;\nassign axi_send_pulse_o = axi_send_pulse;\nalways @(posedge clk or posedge rst) begin\n\tif (rst) begin\n\t\taxi_send_buffer <= 0;\n\t\taxi_send_pulse <= 0;\n\t\taxi_send_cnt <= 0;\n\tend\n\telse begin\n\t\tif (buffer_valid_pulse) begin\n\t\t\taxi_send_buffer <= {axi_send_buffer[15:0],rgb565_gray};\n\t\tend\t\n\t\tif (buffer_valid_pulse) begin\n\t\t\taxi_send_cnt <= axi_send_cnt + 1;\n\t\tend\n\t\tif (axi_send_cnt && buffer_valid_pulse) begin\n\t\t\taxi_send_pulse <= 1;\n\t\tend\n\t\telse begin\n\t\t\taxi_send_pulse <= 0;\n\t\tend\n\tend \nend\nendmodule", "predict_code_clean": "module line_skipper (\n input wire clk,\n input wire rst,\n input wire [15:0] raw_pixel_in,\n input wire raw_pixel_valid_in,\n input wire readout_busy_in,\n input wire line_sync,\n output wire [31:0] axi_data_buffer_o,\n output wire axi_send_pulse_o\n);\n reg [15:0] line_counter;\n reg skip_line;\n reg [15:0] pixel_buffer;\n reg buffer_has_data;\n reg [31:0] data_buffer;\n reg send_pulse;\n always @(posedge clk or posedge rst) begin\n if (rst) begin\n line_counter <= 0;\n skip_line <= 0;\n end else if (line_sync) begin\n line_counter <= line_counter + 1;\n skip_line <= ~line_counter[0];\n end\n end\n always @(posedge clk or posedge rst) begin\n if (rst) begin\n pixel_buffer <= 0;\n buffer_has_data <= 0;\n data_buffer <= 0;\n send_pulse <= 0;\n end else begin\n send_pulse <= 0;\n if (!skip_line && raw_pixel_valid_in) begin\n if (!buffer_has_data) begin\n pixel_buffer <= raw_pixel_in;\n buffer_has_data <= 1;\n end else begin\n data_buffer <= {pixel_buffer, raw_pixel_in};\n buffer_has_data <= 0;\n if (!readout_busy_in) begin\n send_pulse <= 1;\n end\n end\n end\n end\n end\n assign axi_data_buffer_o = data_buffer;\n assign axi_send_pulse_o = send_pulse;\nendmodule"}}
5
+ {"repo_name": "ICX453_CCD_Mirrorless_Camera", "file_name": "/ICX453_CCD_Mirrorless_Camera/line_skipper.v", "inference_info": {"prefix_code": "`timescale 1ns / 1ps\n\n", "suffix_code": "\n", "middle_code": "module line_skipper(\n\t\tinput wire clk,\n\t\tinput wire rst,\n\t\tinput wire [15:0] raw_pixel_in,\n\t\tinput wire raw_pixel_valid_in,\n\t\tinput wire readout_busy_in,\n\t\tinput wire line_sync,\n\t\toutput wire [31:0] axi_data_buffer_o,\n\t\toutput wire axi_send_pulse_o\n);\nreg line_sync_ff1;\nreg line_sync_ff2;\nwire line_sync_pulse = (line_sync_ff1 && ~line_sync_ff2) ? 1'b1 : 1'b0;\nalways @(posedge clk ) begin\n\tif(raw_pixel_valid_in) begin\n\t\tline_sync_ff1 <= line_sync;\n\t\tline_sync_ff2 <= line_sync_ff1;\n\tend\nend\n(* MARK_DEBUG=\"true\" *)reg [15:0] skip_pixel_cnt;\n(* MARK_DEBUG=\"true\" *)reg [15:0] skip_line_cnt;\n(* MARK_DEBUG=\"true\" *)reg [7:0] pixel_cnt_x;\n(* MARK_DEBUG=\"true\" *)reg [7:0] pixel_cnt_y;\n(* MARK_DEBUG=\"true\" *) reg [3:0] state_q;\nparameter SKIP_FIRST_55_PIX = 4'b0000;\nparameter COUNT_24_PIXEL = 4'b0001;\nparameter SEND_PIXEL = 4'b0011;\nparameter SKIP_6_LINE = 4'b0010;\nparameter DONE = 4'b0110;\nlocalparam SKIP_INVALID_PIX = 55;\nlocalparam TOTAL_LINE = 1024;\nlocalparam PIXEL_PER_LINE = 5760;\nlocalparam SKIPED_PIX = 24;\nlocalparam SKIPED_LINE = 6;\nlocalparam VIEWFINDER_X = 240;\nlocalparam VIEWFINDER_Y = 160;\nreg [4:0] gamma_corrected_buf;\nalways @(posedge clk or posedge rst) begin\n if(rst || ~readout_busy_in)begin\n gamma_corrected_buf <= 0;\n end\n else if(raw_pixel_valid_in) begin\n case (raw_pixel_in[15:11])\n 'd00: gamma_corrected_buf <= 'd00;\n 'd01: gamma_corrected_buf <= 'd07;\n 'd02: gamma_corrected_buf <= 'd09;\n 'd03: gamma_corrected_buf <= 'd11;\n 'd04: gamma_corrected_buf <= 'd12;\n 'd05: gamma_corrected_buf <= 'd14;\n 'd06: gamma_corrected_buf <= 'd15;\n 'd07: gamma_corrected_buf <= 'd16;\n 'd08: gamma_corrected_buf <= 'd17;\n 'd09: gamma_corrected_buf <= 'd18;\n 'd10: gamma_corrected_buf <= 'd19;\n 'd11: gamma_corrected_buf <= 'd19;\n 'd12: gamma_corrected_buf <= 'd20;\n 'd13: gamma_corrected_buf <= 'd21;\n 'd14: gamma_corrected_buf <= 'd22;\n 'd15: gamma_corrected_buf <= 'd22;\n 'd16: gamma_corrected_buf <= 'd23;\n 'd17: gamma_corrected_buf <= 'd24;\n 'd18: gamma_corrected_buf <= 'd24;\n 'd19: gamma_corrected_buf <= 'd25;\n 'd20: gamma_corrected_buf <= 'd25;\n 'd21: gamma_corrected_buf <= 'd26;\n 'd22: gamma_corrected_buf <= 'd27;\n 'd23: gamma_corrected_buf <= 'd27;\n 'd24: gamma_corrected_buf <= 'd28;\n 'd25: gamma_corrected_buf <= 'd28;\n 'd26: gamma_corrected_buf <= 'd29;\n 'd27: gamma_corrected_buf <= 'd29;\n 'd28: gamma_corrected_buf <= 'd30;\n 'd29: gamma_corrected_buf <= 'd30;\n 'd30: gamma_corrected_buf <= 'd31;\n 'd31: gamma_corrected_buf <= 'd31;\n default: gamma_corrected_buf <= 0;\n endcase\n end\nend\nreg buffer_valid;\nwire [15:0] rgb565_gray = {gamma_corrected_buf, gamma_corrected_buf, 1'b0 , gamma_corrected_buf};\nalways @(posedge clk or posedge rst) begin\n\tif(rst || ~readout_busy_in) begin\n\t\tstate_q <= SKIP_FIRST_55_PIX;\n\t\tskip_pixel_cnt <= 0; \n\t\tskip_line_cnt <= 0;\n\t\tpixel_cnt_x <= 0;\n\t\tpixel_cnt_y <= 0;\n\t\tbuffer_valid <= 0;\n\tend\n\telse if(raw_pixel_valid_in) begin\n\t\tcase (state_q)\n\t\t\tSKIP_FIRST_55_PIX: begin\n\t\t\t\tif (skip_pixel_cnt >= SKIP_INVALID_PIX) begin\n\t\t\t\t\tstate_q <= COUNT_24_PIXEL;\n\t\t\t\t\tskip_pixel_cnt <= 0;\n\t\t\t\tend\n\t\t\t\telse begin\n\t\t\t\t\tskip_pixel_cnt <= skip_pixel_cnt + 1;\n\t\t\t\tend\n\t\t\tend\n\t\t\tCOUNT_24_PIXEL: begin\n\t\t\t\tif (skip_pixel_cnt < SKIPED_PIX) begin\n\t\t\t\t\tskip_pixel_cnt <= skip_pixel_cnt + 1;\n\t\t\t\tend\n\t\t\t\telse begin\n\t\t\t\t\tstate_q <= SEND_PIXEL;\n\t\t\t\t\tbuffer_valid <= 1;\n\t\t\t\t\tskip_pixel_cnt <= 0;\n\t\t\t\tend\n\t\t\tend\n\t\t\tSEND_PIXEL: begin\n\t\t\t\tif (pixel_cnt_x < VIEWFINDER_X) begin\n\t\t\t\t\tpixel_cnt_x <= pixel_cnt_x + 1;\n\t\t\t\t\tbuffer_valid <= 0;\n\t\t\t\t\tstate_q <= COUNT_24_PIXEL;\n\t\t\t\tend\n\t\t\t\telse begin\n\t\t\t\t\tpixel_cnt_x <= 0;\n\t\t\t\t\tstate_q <= SKIP_6_LINE;\n\t\t\t\tend\n\t\t\tend\n\t\t\tSKIP_6_LINE: begin\n\t\t\t\tif (line_sync_pulse) begin\n\t\t\t\t\tif (pixel_cnt_y >= VIEWFINDER_Y) begin\n\t\t\t\t\t\tstate_q <= DONE;\n\t\t\t\t\t\tpixel_cnt_y <= 0;\n\t\t\t\t\tend\n\t\t\t\t\telse if (skip_line_cnt < SKIPED_LINE - 1) begin\n\t\t\t\t\t\tskip_line_cnt <= skip_line_cnt + 1;\n\t\t\t\t\tend\n\t\t\t\t\telse begin\n\t\t\t\t\t\tskip_line_cnt <= 0;\n\t\t\t\t\t\tpixel_cnt_y <= pixel_cnt_y + 1;\n\t\t\t\t\t\tstate_q <= COUNT_24_PIXEL;\n\t\t\t\t\tend\n\t\t\t\tend\t\n\t\t\tend\n\t\t\tDONE: begin\n\t\t\tend\n\t\t\tdefault: state_q <= DONE;\n\t\tendcase\n\tend\nend\nreg buffer_valid_ff;\nwire buffer_valid_pulse = (buffer_valid && ~buffer_valid_ff) ? 1'b1 : 1'b0 ;\nalways @(posedge clk) begin\n\tbuffer_valid_ff <= buffer_valid;\nend\nreg [31:0] axi_send_buffer;\nreg axi_send_cnt;\nreg axi_send_pulse;\nassign axi_data_buffer_o = axi_send_buffer;\nassign axi_send_pulse_o = axi_send_pulse;\nalways @(posedge clk or posedge rst) begin\n\tif (rst) begin\n\t\taxi_send_buffer <= 0;\n\t\taxi_send_pulse <= 0;\n\t\taxi_send_cnt <= 0;\n\tend\n\telse begin\n\t\tif (buffer_valid_pulse) begin\n\t\t\taxi_send_buffer <= {axi_send_buffer[15:0],rgb565_gray};\n\t\tend\t\n\t\tif (buffer_valid_pulse) begin\n\t\t\taxi_send_cnt <= axi_send_cnt + 1;\n\t\tend\n\t\tif (axi_send_cnt && buffer_valid_pulse) begin\n\t\t\taxi_send_pulse <= 1;\n\t\tend\n\t\telse begin\n\t\t\taxi_send_pulse <= 0;\n\t\tend\n\tend \nend\nendmodule", "code_description": null, "fill_type": "CLASS_TYPE", "language_type": "verilog", "sub_task_type": null}, "context_code": [], "task_instance_info": {"created_time": "2025-08-21 04:22:24", "created_task_model": "DeepSeek-R1", "class_skeleton": "module line_skipper (\n\t\tinput wire clk,\n\t\tinput wire rst,\n\t\t\n\t\t//pixel input\n\t\tinput wire [15:0] raw_pixel_in,\n\t\tinput wire raw_pixel_valid_in,\n\t\tinput wire readout_busy_in,\n\t\tinput wire line_sync,\n\t\t\n\t\toutput wire [31:0] axi_data_buffer_o,\n\t\toutput wire axi_send_pulse_o\n) ; endmodule", "code_description": "This code segment functions to: Process incoming pixel data streams by applying gamma correction transformations, selectively skipping specified quantities of initial pixels and image lines, capturing a defined rectangular viewport area, and packaging processed pixel values into buffered output packets synchronized with transmission control signals."}, "inference_content": {"inference_model": "DeepSeek-R1", "inference_result": "```verilog\n[TASK_BEGIN]\nmodule line_skipper (\n input wire clk,\n input wire rst,\n \n // Pixel input\n input wire [15:0] raw_pixel_in,\n input wire raw_pixel_valid_in,\n input wire readout_busy_in,\n input wire line_sync,\n \n output wire [31:0] axi_data_buffer_o,\n output wire axi_send_pulse_o\n);\n\n reg skip_line;\n reg [15:0] pixel_buffer;\n reg buffer_ready;\n reg [31:0] data_buffer;\n reg has_pending_data;\n reg send_pulse;\n\n // Line skip control\n always @(posedge clk or posedge rst) begin\n if (rst) skip_line <= 1'b0;\n else if (line_sync) skip_line <= ~skip_line;\n end\n\n // Pixel processing pipeline\n always @(posedge clk or posedge rst) begin\n if (rst) begin\n pixel_buffer <= 16'b0;\n buffer_ready <= 1'b0;\n data_buffer <= 32'b0;\n has_pending_data <= 1'b0;\n send_pulse <= 1'b0;\n end else begin\n send_pulse <= 1'b0;\n \n // Process valid pixels when not skipping line\n if (!skip_line && raw_pixel_valid_in) begin\n if (buffer_ready) begin\n data_buffer <= {pixel_buffer, raw_pixel_in};\n has_pending_data <= 1'b1;\n buffer_ready <= 1'b0;\n end else begin\n pixel_buffer <= raw_pixel_in;\n buffer_ready <= 1'b1;\n end\n end\n\n // Data transmission control\n if (has_pending_data && !readout_busy_in) begin\n send_pulse <= 1'b1;\n has_pending_data <= 1'b0;\n end\n end\n end\n\n assign axi_data_buffer_o = data_buffer;\n assign axi_send_pulse_o = send_pulse;\n\nendmodule\n[TASK_END]\n```", "inference_time": "2025-08-21 04-24-25"}, "editdistance_info": {"edit_distance": 11.3455, "calculate_time": "2025-08-21 04:24:25", "true_code_clean": "module line_skipper(\n\t\tinput wire clk,\n\t\tinput wire rst,\n\t\tinput wire [15:0] raw_pixel_in,\n\t\tinput wire raw_pixel_valid_in,\n\t\tinput wire readout_busy_in,\n\t\tinput wire line_sync,\n\t\toutput wire [31:0] axi_data_buffer_o,\n\t\toutput wire axi_send_pulse_o\n);\nreg line_sync_ff1;\nreg line_sync_ff2;\nwire line_sync_pulse = (line_sync_ff1 && ~line_sync_ff2) ? 1'b1 : 1'b0;\nalways @(posedge clk ) begin\n\tif(raw_pixel_valid_in) begin\n\t\tline_sync_ff1 <= line_sync;\n\t\tline_sync_ff2 <= line_sync_ff1;\n\tend\nend\n(* MARK_DEBUG=\"true\" *)reg [15:0] skip_pixel_cnt;\n(* MARK_DEBUG=\"true\" *)reg [15:0] skip_line_cnt;\n(* MARK_DEBUG=\"true\" *)reg [7:0] pixel_cnt_x;\n(* MARK_DEBUG=\"true\" *)reg [7:0] pixel_cnt_y;\n(* MARK_DEBUG=\"true\" *) reg [3:0] state_q;\nparameter SKIP_FIRST_55_PIX = 4'b0000;\nparameter COUNT_24_PIXEL = 4'b0001;\nparameter SEND_PIXEL = 4'b0011;\nparameter SKIP_6_LINE = 4'b0010;\nparameter DONE = 4'b0110;\nlocalparam SKIP_INVALID_PIX = 55;\nlocalparam TOTAL_LINE = 1024;\nlocalparam PIXEL_PER_LINE = 5760;\nlocalparam SKIPED_PIX = 24;\nlocalparam SKIPED_LINE = 6;\nlocalparam VIEWFINDER_X = 240;\nlocalparam VIEWFINDER_Y = 160;\nreg [4:0] gamma_corrected_buf;\nalways @(posedge clk or posedge rst) begin\n if(rst || ~readout_busy_in)begin\n gamma_corrected_buf <= 0;\n end\n else if(raw_pixel_valid_in) begin\n case (raw_pixel_in[15:11])\n 'd00: gamma_corrected_buf <= 'd00;\n 'd01: gamma_corrected_buf <= 'd07;\n 'd02: gamma_corrected_buf <= 'd09;\n 'd03: gamma_corrected_buf <= 'd11;\n 'd04: gamma_corrected_buf <= 'd12;\n 'd05: gamma_corrected_buf <= 'd14;\n 'd06: gamma_corrected_buf <= 'd15;\n 'd07: gamma_corrected_buf <= 'd16;\n 'd08: gamma_corrected_buf <= 'd17;\n 'd09: gamma_corrected_buf <= 'd18;\n 'd10: gamma_corrected_buf <= 'd19;\n 'd11: gamma_corrected_buf <= 'd19;\n 'd12: gamma_corrected_buf <= 'd20;\n 'd13: gamma_corrected_buf <= 'd21;\n 'd14: gamma_corrected_buf <= 'd22;\n 'd15: gamma_corrected_buf <= 'd22;\n 'd16: gamma_corrected_buf <= 'd23;\n 'd17: gamma_corrected_buf <= 'd24;\n 'd18: gamma_corrected_buf <= 'd24;\n 'd19: gamma_corrected_buf <= 'd25;\n 'd20: gamma_corrected_buf <= 'd25;\n 'd21: gamma_corrected_buf <= 'd26;\n 'd22: gamma_corrected_buf <= 'd27;\n 'd23: gamma_corrected_buf <= 'd27;\n 'd24: gamma_corrected_buf <= 'd28;\n 'd25: gamma_corrected_buf <= 'd28;\n 'd26: gamma_corrected_buf <= 'd29;\n 'd27: gamma_corrected_buf <= 'd29;\n 'd28: gamma_corrected_buf <= 'd30;\n 'd29: gamma_corrected_buf <= 'd30;\n 'd30: gamma_corrected_buf <= 'd31;\n 'd31: gamma_corrected_buf <= 'd31;\n default: gamma_corrected_buf <= 0;\n endcase\n end\nend\nreg buffer_valid;\nwire [15:0] rgb565_gray = {gamma_corrected_buf, gamma_corrected_buf, 1'b0 , gamma_corrected_buf};\nalways @(posedge clk or posedge rst) begin\n\tif(rst || ~readout_busy_in) begin\n\t\tstate_q <= SKIP_FIRST_55_PIX;\n\t\tskip_pixel_cnt <= 0; \n\t\tskip_line_cnt <= 0;\n\t\tpixel_cnt_x <= 0;\n\t\tpixel_cnt_y <= 0;\n\t\tbuffer_valid <= 0;\n\tend\n\telse if(raw_pixel_valid_in) begin\n\t\tcase (state_q)\n\t\t\tSKIP_FIRST_55_PIX: begin\n\t\t\t\tif (skip_pixel_cnt >= SKIP_INVALID_PIX) begin\n\t\t\t\t\tstate_q <= COUNT_24_PIXEL;\n\t\t\t\t\tskip_pixel_cnt <= 0;\n\t\t\t\tend\n\t\t\t\telse begin\n\t\t\t\t\tskip_pixel_cnt <= skip_pixel_cnt + 1;\n\t\t\t\tend\n\t\t\tend\n\t\t\tCOUNT_24_PIXEL: begin\n\t\t\t\tif (skip_pixel_cnt < SKIPED_PIX) begin\n\t\t\t\t\tskip_pixel_cnt <= skip_pixel_cnt + 1;\n\t\t\t\tend\n\t\t\t\telse begin\n\t\t\t\t\tstate_q <= SEND_PIXEL;\n\t\t\t\t\tbuffer_valid <= 1;\n\t\t\t\t\tskip_pixel_cnt <= 0;\n\t\t\t\tend\n\t\t\tend\n\t\t\tSEND_PIXEL: begin\n\t\t\t\tif (pixel_cnt_x < VIEWFINDER_X) begin\n\t\t\t\t\tpixel_cnt_x <= pixel_cnt_x + 1;\n\t\t\t\t\tbuffer_valid <= 0;\n\t\t\t\t\tstate_q <= COUNT_24_PIXEL;\n\t\t\t\tend\n\t\t\t\telse begin\n\t\t\t\t\tpixel_cnt_x <= 0;\n\t\t\t\t\tstate_q <= SKIP_6_LINE;\n\t\t\t\tend\n\t\t\tend\n\t\t\tSKIP_6_LINE: begin\n\t\t\t\tif (line_sync_pulse) begin\n\t\t\t\t\tif (pixel_cnt_y >= VIEWFINDER_Y) begin\n\t\t\t\t\t\tstate_q <= DONE;\n\t\t\t\t\t\tpixel_cnt_y <= 0;\n\t\t\t\t\tend\n\t\t\t\t\telse if (skip_line_cnt < SKIPED_LINE - 1) begin\n\t\t\t\t\t\tskip_line_cnt <= skip_line_cnt + 1;\n\t\t\t\t\tend\n\t\t\t\t\telse begin\n\t\t\t\t\t\tskip_line_cnt <= 0;\n\t\t\t\t\t\tpixel_cnt_y <= pixel_cnt_y + 1;\n\t\t\t\t\t\tstate_q <= COUNT_24_PIXEL;\n\t\t\t\t\tend\n\t\t\t\tend\t\n\t\t\tend\n\t\t\tDONE: begin\n\t\t\tend\n\t\t\tdefault: state_q <= DONE;\n\t\tendcase\n\tend\nend\nreg buffer_valid_ff;\nwire buffer_valid_pulse = (buffer_valid && ~buffer_valid_ff) ? 1'b1 : 1'b0 ;\nalways @(posedge clk) begin\n\tbuffer_valid_ff <= buffer_valid;\nend\nreg [31:0] axi_send_buffer;\nreg axi_send_cnt;\nreg axi_send_pulse;\nassign axi_data_buffer_o = axi_send_buffer;\nassign axi_send_pulse_o = axi_send_pulse;\nalways @(posedge clk or posedge rst) begin\n\tif (rst) begin\n\t\taxi_send_buffer <= 0;\n\t\taxi_send_pulse <= 0;\n\t\taxi_send_cnt <= 0;\n\tend\n\telse begin\n\t\tif (buffer_valid_pulse) begin\n\t\t\taxi_send_buffer <= {axi_send_buffer[15:0],rgb565_gray};\n\t\tend\t\n\t\tif (buffer_valid_pulse) begin\n\t\t\taxi_send_cnt <= axi_send_cnt + 1;\n\t\tend\n\t\tif (axi_send_cnt && buffer_valid_pulse) begin\n\t\t\taxi_send_pulse <= 1;\n\t\tend\n\t\telse begin\n\t\t\taxi_send_pulse <= 0;\n\t\tend\n\tend \nend\nendmodule", "predict_code_clean": "module line_skipper (\n input wire clk,\n input wire rst,\n input wire [15:0] raw_pixel_in,\n input wire raw_pixel_valid_in,\n input wire readout_busy_in,\n input wire line_sync,\n output wire [31:0] axi_data_buffer_o,\n output wire axi_send_pulse_o\n);\n reg skip_line;\n reg [15:0] pixel_buffer;\n reg buffer_ready;\n reg [31:0] data_buffer;\n reg has_pending_data;\n reg send_pulse;\n always @(posedge clk or posedge rst) begin\n if (rst) skip_line <= 1'b0;\n else if (line_sync) skip_line <= ~skip_line;\n end\n always @(posedge clk or posedge rst) begin\n if (rst) begin\n pixel_buffer <= 16'b0;\n buffer_ready <= 1'b0;\n data_buffer <= 32'b0;\n has_pending_data <= 1'b0;\n send_pulse <= 1'b0;\n end else begin\n send_pulse <= 1'b0;\n if (!skip_line && raw_pixel_valid_in) begin\n if (buffer_ready) begin\n data_buffer <= {pixel_buffer, raw_pixel_in};\n has_pending_data <= 1'b1;\n buffer_ready <= 1'b0;\n end else begin\n pixel_buffer <= raw_pixel_in;\n buffer_ready <= 1'b1;\n end\n end\n if (has_pending_data && !readout_busy_in) begin\n send_pulse <= 1'b1;\n has_pending_data <= 1'b0;\n end\n end\n end\n assign axi_data_buffer_o = data_buffer;\n assign axi_send_pulse_o = send_pulse;\nendmodule"}}
verilog/Mayoiuta_class_bench.jsonl ADDED
@@ -0,0 +1,5 @@
 
 
 
 
 
 
1
+ {"repo_name": "Mayoiuta", "file_name": "/Mayoiuta/hardware/rtl/memory/mem_ctl.v", "inference_info": {"prefix_code": "", "suffix_code": "", "middle_code": "module Memory_Controller #(\n parameter ADDR_WIDTH = 32,\n parameter DATA_WIDTH = 256,\n parameter BANK_NUM = 8\n)(\n input wire clk,\n input wire rst_n,\n input wire [ADDR_WIDTH-1:0] host_addr,\n input wire host_wr_en,\n input wire [DATA_WIDTH-1:0] host_wr_data,\n output reg [DATA_WIDTH-1:0] host_rd_data,\n input wire [ADDR_WIDTH-1:0] npu_addr,\n input wire npu_rd_en,\n output reg [DATA_WIDTH-1:0] npu_rd_data\n);\nreg [DATA_WIDTH-1:0] memory_bank [0:BANK_NUM-1][0:(1<<(ADDR_WIDTH-3))-1];\nalways @(posedge clk) begin\n if (host_wr_en) begin\n memory_bank[host_addr[2:0]][host_addr[ADDR_WIDTH-1:3]] <= host_wr_data;\n end\n host_rd_data <= memory_bank[host_addr[2:0]][host_addr[ADDR_WIDTH-1:3]];\n if (npu_rd_en) begin\n npu_rd_data <= memory_bank[npu_addr[2:0]][npu_addr[ADDR_WIDTH-1:3]];\n end\nend\necc_checker #(\n .DATA_WIDTH(DATA_WIDTH)\n) u_ecc (\n .data_in(host_wr_data),\n .data_out(host_rd_data),\n .syndrome()\n);\nendmodule", "code_description": null, "fill_type": "CLASS_TYPE", "language_type": "verilog", "sub_task_type": null}, "context_code": [["/Mayoiuta/hardware/rtl/core/pe_array.v", "module PE_Array #(\n parameter DATA_WIDTH = 16,\n parameter ARRAY_SIZE = 8\n)(\n input wire clk,\n input wire rst_n,\n input wire [DATA_WIDTH-1:0] north_in [ARRAY_SIZE-1:0],\n input wire [DATA_WIDTH-1:0] west_in [ARRAY_SIZE-1:0],\n output wire [DATA_WIDTH-1:0] south_out[ARRAY_SIZE-1:0],\n output wire [DATA_WIDTH-1:0] east_out [ARRAY_SIZE-1:0],\n input wire [3:0] opcode,\n input wire start,\n output wire done\n);\n\nwire [DATA_WIDTH-1:0] pe_data_h [ARRAY_SIZE][ARRAY_SIZE];\nwire [DATA_WIDTH-1:0] pe_data_v [ARRAY_SIZE][ARRAY_SIZE];\n\ngenerate\nfor (genvar i = 0; i < ARRAY_SIZE; i = i + 1) begin : row_gen\n for (genvar j = 0; j < ARRAY_SIZE; j = j + 1) begin : col_gen\n Processing_Element #(\n .DATA_WIDTH(DATA_WIDTH)\n ) u_pe (\n .clk(clk),\n .rst_n(rst_n),\n .north_in(i == 0 ? north_in[j] : pe_data_v[i-1][j]),\n .west_in(j == 0 ? west_in[i] : pe_data_h[i][j-1]),\n .south_out(pe_data_v[i][j]),\n .east_out(pe_data_h[i][j]),\n .opcode(opcode),\n .start(start),\n .done(done)\n );\n end\nend\nendgenerate\n\nassign south_out = pe_data_v[ARRAY_SIZE-1];\nassign east_out = pe_data_h[ARRAY_SIZE][ARRAY_SIZE-1];\n\nendmodule\n\nmodule Processing_Element #(\n parameter DATA_WIDTH = 16\n)(\n input wire clk,\n input wire rst_n,\n input wire [DATA_WIDTH-1:0] north_in,\n input wire [DATA_WIDTH-1:0] west_in,\n output reg [DATA_WIDTH-1:0] south_out,\n output reg [DATA_WIDTH-1:0] east_out,\n input wire [3:0] opcode,\n input wire start,\n output reg done\n);\n\nreg [DATA_WIDTH-1:0] accumulator;\nreg [DATA_WIDTH-1:0] weight_reg;\n\nalways @(posedge clk or negedge rst_n) begin\n if (!rst_n) begin\n accumulator <= 0;\n weight_reg <= 0;\n done <= 0;\n end else begin\n case(opcode)\n 4'h1: begin\n weight_reg <= west_in;\n done <= 1;\n end\n 4'h2: begin\n accumulator <= accumulator + (north_in * weight_reg);\n done <= 1;\n end\n 4'h3: begin\n south_out <= north_in;\n east_out <= west_in;\n done <= 1;\n end\n default: done <= 0;\n endcase\n end\nend\n\nendmodule"], ["/Mayoiuta/hardware/rtl/top/npu_soc.v", "module NPU_SOC #(\n parameter CORES = 4\n)(\n input wire clk,\n input wire rst_n,\n // 外部接口\n input wire [127:0] pcie_data,\n output reg [127:0] ddr_data,\n // 控制信号\n input wire interrupt,\n output reg [31:0] status\n);\n\n// 多核互连网络\nwire [127:0] noc_data [0:CORES-1];\nwire [31:0] noc_ctrl [0:CORES-1];\n\n// 主控制器\nnpu_controller u_controller(\n .clk(clk),\n .rst_n(rst_n),\n .cores_status(noc_ctrl),\n .global_config(pcie_data[95:0]),\n .interrupt(interrupt)\n);\n\n// 计算核心阵列\ngenerate\nfor (genvar i = 0; i < CORES; i = i + 1) begin\n npu_core #(\n .CORE_ID(i)\n ) u_core (\n .clk(clk),\n .rst_n(rst_n),\n .noc_in(noc_data[i]),\n .noc_out(noc_data[(i+1)%CORES]),\n .ctrl_in(noc_ctrl[i]),\n .ddr_interface(ddr_data)\n );\nend\nendgenerate\n\n// 性能监控\nperformance_monitor u_monitor(\n .clk(clk),\n .cores_active(noc_ctrl),\n .ddr_usage(ddr_data[127:96]),\n .power_status(status[31:16])\n);\n\nendmodule"], ["/Mayoiuta/hardware/rtl/memory/data_reorder.v", "module Data_Reorder #(\n parameter CHANNELS = 64,\n parameter TILE_SIZE = 8\n)(\n input wire clk,\n input wire rst_n,\n input wire [127:0] mem_data,\n output reg [127:0] pe_data,\n input wire [1:0] data_format // 0:NCHW 1:NHWC 2:Blocked\n);\n\nreg [127:0] reorder_buffer [0:CHANNELS/TILE_SIZE-1][0:TILE_SIZE-1];\n\n// 数据格式转换引擎\nalways @(posedge clk) begin\n case(data_format)\n 2'b00: // NCHW -> PE阵列格式\n for (int c = 0; c < CHANNELS; c += TILE_SIZE) begin\n for (int t = 0; t < TILE_SIZE; t++) begin\n reorder_buffer[c/TILE_SIZE][t] <= \n {mem_data[127:112], mem_data[95:80], // 通道优先\n mem_data[63:48], mem_data[31:16]};\n end\n end\n \n 2'b01: // NHWC -> PE阵列格式\n for (int h = 0; h < TILE_SIZE; h++) begin\n reorder_buffer[h%4][h/4] <= \n {mem_data[127:120], mem_data[95:88], // 空间优先\n mem_data[63:56], mem_data[31:24]};\n end\n \n 2'b10: // Blocked格式\n pe_data <= mem_data; // 直接传递\n endcase\nend\n\n// 输出调度\nalways @(posedge clk) begin\n pe_data <= reorder_buffer[read_ptr];\n read_ptr <= (read_ptr == (CHANNELS/TILE_SIZE-1)) ? 0 : read_ptr + 1;\nend\n\nendmodule"], ["/Mayoiuta/hardware/rtl/sparse/sparse_engine.v", "module Sparse_Engine #(\n parameter SPARSE_THRESH = 0.3\n)(\n input wire clk,\n input wire rst_n,\n input wire [7:0] activation [0:31][0:31],\n input wire [7:0] weight [0:31][0:31],\n output reg [15:0] sparse_result,\n output reg sparse_valid\n);\n\n// 零值检测逻辑\nreg [31:0] zero_count;\nalways @(posedge clk) begin\n zero_count = 0;\n for (int i = 0; i < 32; i++) begin\n for (int j = 0; j < 32; j++) begin\n if (activation[i][j] == 0 || weight[i][j] == 0) begin\n zero_count <= zero_count + 1;\n end\n end\n end\n \n // 稀疏度判断\n if (zero_count > (32*32*SPARSE_THRESH)) begin\n sparse_valid <= 1'b1;\n // 触发稀疏计算模式\n sparse_result <= activation * weight; // 使用专用稀疏乘法器\n end else begin\n sparse_valid <= 1'b0;\n end\nend\n\n// 稀疏矩阵压缩格式处理\nwire [7:0] compressed_act;\nwire [4:0] act_idx;\nsparse_encoder encoder(\n .in_data(activation),\n .compressed(compressed_act),\n .index(act_idx)\n);\n\nwire [7:0] compressed_weight;\nwire [4:0] weight_idx;\nsparse_encoder encoder_w(\n .in_data(weight),\n .compressed(compressed_weight),\n .index(weight_idx)\n);\n\n// 稀疏矩阵乘法核心\nalways @(posedge clk) begin\n if (act_idx == weight_idx) begin\n sparse_result <= compressed_act * compressed_weight;\n end\nend\n\nendmodule"], ["/Mayoiuta/hardware/rtl/core/conv_engine.v", "module Conv_Engine #(\n parameter KERNEL_SIZE = 3,\n parameter STRIDE = 1,\n parameter PAD = 1\n)(\n input wire clk,\n input wire rst_n,\n input wire [7:0] feature_map [0:31][0:31], // 32x32输入\n input wire [7:0] weight [0:2][0:2], // 3x3卷积核\n output reg [15:0] conv_result [0:30][0:30] // 输出特征图\n);\n\n// 滑动窗口生成器\nreg [7:0] window_buffer [0:2][0:2];\nalways @(posedge clk) begin\n for (int i = 0; i <= 30; i++) begin\n for (int j = 0; j <= 30; j++) begin\n // 窗口滑动控制\n if (j == 0) begin\n window_buffer[0][0] <= (i > 0) ? feature_map[i-1][j+0] : 0;\n window_buffer[1][0] <= feature_map[i][j+0];\n window_buffer[2][0] <= (i < 31) ? feature_map[i+1][j+0] : 0;\n end else begin\n window_buffer[0][j%3] <= window_buffer[0][(j-1)%3];\n window_buffer[1][j%3] <= window_buffer[1][(j-1)%3];\n window_buffer[2][j%3] <= window_buffer[2][(j-1)%3];\n end\n \n // 卷积计算\n if (j >= 2) begin\n conv_result[i][j-2] <= \n (window_buffer[0][0] * weight[0][0]) +\n (window_buffer[0][1] * weight[0][1]) +\n (window_buffer[0][2] * weight[0][2]) +\n (window_buffer[1][0] * weight[1][0]) +\n (window_buffer[1][1] * weight[1][1]) +\n (window_buffer[1][2] * weight[1][2]) +\n (window_buffer[2][0] * weight[2][0]) +\n (window_buffer[2][1] * weight[2][1]) +\n (window_buffer[2][2] * weight[2][2]);\n end\n end\n end\nend\n\nendmodule"], ["/Mayoiuta/hardware/rtl/power/dvfs_ctrl.v", "module DVFS_Controller #(\n parameter VOLTAGE_LEVELS = 4,\n parameter FREQ_LEVELS = 4\n)(\n input wire clk,\n input wire rst_n,\n input wire [7:0] workload, // 0-255工作量指示\n output reg [1:0] voltage_level, // 00:0.8V ... 11:1.2V\n output reg [1:0] freq_level // 00:500MHz ... 11:1.2GHz\n);\n\nreg [15:0] history_buffer [0:7];\nalways @(posedge clk) begin\n history_buffer <= {history_buffer[6:0], workload};\nend\n\n// 移动平均计算\nwire [10:0] moving_avg;\nassign moving_avg = (history_buffer[0] + history_buffer[1] + history_buffer[2] + \n history_buffer[3] + history_buffer[4] + history_buffer[5] +\n history_buffer[6] + history_buffer[7]) >> 3;\n\n// 调节策略\nalways @(*) begin\n case(moving_avg)\n 0-50: {voltage_level, freq_level} = 4'b00_00;\n 51-100: {voltage_level, freq_level} = 4'b01_01;\n 101-150:{voltage_level, freq_level} = 4'b10_10;\n default:{voltage_level, freq_level} = 4'b11_11;\n endcase\nend\n\nendmodule"], ["/Mayoiuta/hardware/rtl/core/adaptive_pe.v", "module Adaptive_PE #(\n parameter INT8_MODE = 1,\n parameter FP16_MODE = 0\n)(\n input wire clk,\n input wire rst_n,\n input wire [3:0] precision_mode,\n input wire [31:0] din_a,\n input wire [31:0] din_b,\n output reg [31:0] dout\n);\n\n// 多精度计算单元\nalways @(posedge clk) begin\n if (!rst_n) dout <= 0;\n else begin\n case(precision_mode)\n 4'b0001: // INT8模式\n dout <= $signed(din_a[7:0]) * $signed(din_b[7:0]);\n 4'b0010: // FP16模式\n dout <= fp16_mult(din_a[15:0], din_b[15:0]);\n 4'b0100: // BFLOAT16\n dout <= {din_a[31:16], 16'b0} * {din_b[31:16], 16'b0};\n default: // INT16\n dout <= $signed(din_a) * $signed(din_b);\n endcase\n end\nend\n\n// IEEE 754半精度浮点乘法实现\nfunction [15:0] fp16_mult;\n input [15:0] a, b;\n begin\n fp16_mult[15] = a[15] ^ b[15];\n // 指数处理\n if (a[14:10] == 0 || b[14:10] == 0) \n fp16_mult[14:10] = 0;\n else \n fp16_mult[14:10] = a[14:10] + b[14:10] - 15;\n // 尾数处理\n fp16_mult[9:0] = (a[9:0] * b[9:0]) >> 10;\n end\nendfunction\n\nendmodule"], ["/Mayoiuta/hardware/rtl/control/shape_adaptor.v", "module Shape_Adaptor #(\n parameter MAX_DIM = 4096\n)(\n input wire clk,\n input wire rst_n,\n input wire [15:0] in_height,\n input wire [15:0] in_width,\n input wire [15:0] kernel_h,\n input wire [15:0] kernel_w,\n output reg [15:0] out_height,\n output reg [15:0] out_width,\n output reg pad_enable\n);\n\n// 动态形状计算\nalways @(posedge clk) begin\n // 输出尺寸计算\n out_height <= (in_height + 2*PAD - kernel_h) / STRIDE + 1;\n out_width <= (in_width + 2*PAD - kernel_w) / STRIDE + 1;\n \n // 自动填充检测\n pad_enable <= ((in_height % STRIDE != 0) || \n (in_width % STRIDE != 0)) ? 1'b1 : 1'b0;\n \n // 边界保护\n if (out_height > MAX_DIM || out_width > MAX_DIM) begin\n $display(\"Error: Output dimension exceeds maximum limit!\");\n out_height <= MAX_DIM;\n out_width <= MAX_DIM;\n end\nend\n\n// 运行时配置接口\ntask configure(\n input [15:0] new_stride,\n input [15:0] new_pad\n);\n STRIDE = new_stride;\n PAD = new_pad;\nendtask\n\nendmodule"]], "task_instance_info": {"created_time": "2025-08-21 04:26:38", "created_task_model": "DeepSeek-R1", "class_skeleton": "module Memory_Controller #(\n parameter ADDR_WIDTH = 32,\n parameter DATA_WIDTH = 256,\n parameter BANK_NUM = 8\n)(\n input wire clk,\n input wire rst_n,\n // 主机接口\n input wire [ADDR_WIDTH-1:0] host_addr,\n input wire host_wr_en,\n input wire [DATA_WIDTH-1:0] host_wr_data,\n output reg [DATA_WIDTH-1:0] host_rd_data,\n // NPU接口\n input wire [ADDR_WIDTH-1:0] npu_addr,\n input wire npu_rd_en,\n output reg [DATA_WIDTH-1:0] npu_rd_data\n) ; endmodule", "code_description": "This code segment functions to: Manage concurrent read and write operations across multiple memory banks while implementing error detection mechanisms for data integrity verification. It coordinates address decoding for parallel access patterns and synchronizes data retrieval between distinct processing units."}, "inference_content": {"inference_model": "DeepSeek-R1", "inference_result": "```verilog\n[TASK_BEGIN]\nmodule Memory_Controller #(\n parameter ADDR_WIDTH = 32,\n parameter DATA_WIDTH = 256,\n parameter BANK_NUM = 8\n)(\n input wire clk,\n input wire rst_n,\n // 主机接口\n input wire [ADDR_WIDTH-1:0] host_addr,\n input wire host_wr_en,\n input wire [DATA_WIDTH-1:0] host_wr_data,\n output reg [DATA_WIDTH-1:0] host_rd_data,\n // NPU接口\n input wire [ADDR_WIDTH-1:0] npu_addr,\n input wire npu_rd_en,\n output reg [DATA_WIDTH-1:0] npu_rd_data\n);\n[TASK_END]\n```", "inference_time": "2025-08-21 04-27-03"}, "editdistance_info": {"edit_distance": 42.3676, "calculate_time": "2025-08-21 04:27:03", "true_code_clean": "module Memory_Controller #(\n parameter ADDR_WIDTH = 32,\n parameter DATA_WIDTH = 256,\n parameter BANK_NUM = 8\n)(\n input wire clk,\n input wire rst_n,\n input wire [ADDR_WIDTH-1:0] host_addr,\n input wire host_wr_en,\n input wire [DATA_WIDTH-1:0] host_wr_data,\n output reg [DATA_WIDTH-1:0] host_rd_data,\n input wire [ADDR_WIDTH-1:0] npu_addr,\n input wire npu_rd_en,\n output reg [DATA_WIDTH-1:0] npu_rd_data\n);\nreg [DATA_WIDTH-1:0] memory_bank [0:BANK_NUM-1][0:(1<<(ADDR_WIDTH-3))-1];\nalways @(posedge clk) begin\n if (host_wr_en) begin\n memory_bank[host_addr[2:0]][host_addr[ADDR_WIDTH-1:3]] <= host_wr_data;\n end\n host_rd_data <= memory_bank[host_addr[2:0]][host_addr[ADDR_WIDTH-1:3]];\n if (npu_rd_en) begin\n npu_rd_data <= memory_bank[npu_addr[2:0]][npu_addr[ADDR_WIDTH-1:3]];\n end\nend\necc_checker #(\n .DATA_WIDTH(DATA_WIDTH)\n) u_ecc (\n .data_in(host_wr_data),\n .data_out(host_rd_data),\n .syndrome()\n);\nendmodule", "predict_code_clean": "module Memory_Controller #(\n parameter ADDR_WIDTH = 32,\n parameter DATA_WIDTH = 256,\n parameter BANK_NUM = 8\n)(\n input wire clk,\n input wire rst_n,\n input wire [ADDR_WIDTH-1:0] host_addr,\n input wire host_wr_en,\n input wire [DATA_WIDTH-1:0] host_wr_data,\n output reg [DATA_WIDTH-1:0] host_rd_data,\n input wire [ADDR_WIDTH-1:0] npu_addr,\n input wire npu_rd_en,\n output reg [DATA_WIDTH-1:0] npu_rd_data\n);"}}
2
+ {"repo_name": "Mayoiuta", "file_name": "/Mayoiuta/hardware/rtl/power/dvfs_ctrl.v", "inference_info": {"prefix_code": "", "suffix_code": "", "middle_code": "module DVFS_Controller #(\n parameter VOLTAGE_LEVELS = 4,\n parameter FREQ_LEVELS = 4\n)(\n input wire clk,\n input wire rst_n,\n input wire [7:0] workload, \n output reg [1:0] voltage_level, \n output reg [1:0] freq_level \n);\nreg [15:0] history_buffer [0:7];\nalways @(posedge clk) begin\n history_buffer <= {history_buffer[6:0], workload};\nend\nwire [10:0] moving_avg;\nassign moving_avg = (history_buffer[0] + history_buffer[1] + history_buffer[2] + \n history_buffer[3] + history_buffer[4] + history_buffer[5] +\n history_buffer[6] + history_buffer[7]) >> 3;\nalways @(*) begin\n case(moving_avg)\n 0-50: {voltage_level, freq_level} = 4'b00_00;\n 51-100: {voltage_level, freq_level} = 4'b01_01;\n 101-150:{voltage_level, freq_level} = 4'b10_10;\n default:{voltage_level, freq_level} = 4'b11_11;\n endcase\nend\nendmodule", "code_description": null, "fill_type": "CLASS_TYPE", "language_type": "verilog", "sub_task_type": null}, "context_code": [["/Mayoiuta/hardware/rtl/memory/data_reorder.v", "module Data_Reorder #(\n parameter CHANNELS = 64,\n parameter TILE_SIZE = 8\n)(\n input wire clk,\n input wire rst_n,\n input wire [127:0] mem_data,\n output reg [127:0] pe_data,\n input wire [1:0] data_format // 0:NCHW 1:NHWC 2:Blocked\n);\n\nreg [127:0] reorder_buffer [0:CHANNELS/TILE_SIZE-1][0:TILE_SIZE-1];\n\n// 数据格式转换引擎\nalways @(posedge clk) begin\n case(data_format)\n 2'b00: // NCHW -> PE阵列格式\n for (int c = 0; c < CHANNELS; c += TILE_SIZE) begin\n for (int t = 0; t < TILE_SIZE; t++) begin\n reorder_buffer[c/TILE_SIZE][t] <= \n {mem_data[127:112], mem_data[95:80], // 通道优先\n mem_data[63:48], mem_data[31:16]};\n end\n end\n \n 2'b01: // NHWC -> PE阵列格式\n for (int h = 0; h < TILE_SIZE; h++) begin\n reorder_buffer[h%4][h/4] <= \n {mem_data[127:120], mem_data[95:88], // 空间优先\n mem_data[63:56], mem_data[31:24]};\n end\n \n 2'b10: // Blocked格式\n pe_data <= mem_data; // 直接传递\n endcase\nend\n\n// 输出调度\nalways @(posedge clk) begin\n pe_data <= reorder_buffer[read_ptr];\n read_ptr <= (read_ptr == (CHANNELS/TILE_SIZE-1)) ? 0 : read_ptr + 1;\nend\n\nendmodule"], ["/Mayoiuta/hardware/rtl/core/adaptive_pe.v", "module Adaptive_PE #(\n parameter INT8_MODE = 1,\n parameter FP16_MODE = 0\n)(\n input wire clk,\n input wire rst_n,\n input wire [3:0] precision_mode,\n input wire [31:0] din_a,\n input wire [31:0] din_b,\n output reg [31:0] dout\n);\n\n// 多精度计算单元\nalways @(posedge clk) begin\n if (!rst_n) dout <= 0;\n else begin\n case(precision_mode)\n 4'b0001: // INT8模式\n dout <= $signed(din_a[7:0]) * $signed(din_b[7:0]);\n 4'b0010: // FP16模式\n dout <= fp16_mult(din_a[15:0], din_b[15:0]);\n 4'b0100: // BFLOAT16\n dout <= {din_a[31:16], 16'b0} * {din_b[31:16], 16'b0};\n default: // INT16\n dout <= $signed(din_a) * $signed(din_b);\n endcase\n end\nend\n\n// IEEE 754半精度浮点乘法实现\nfunction [15:0] fp16_mult;\n input [15:0] a, b;\n begin\n fp16_mult[15] = a[15] ^ b[15];\n // 指数处理\n if (a[14:10] == 0 || b[14:10] == 0) \n fp16_mult[14:10] = 0;\n else \n fp16_mult[14:10] = a[14:10] + b[14:10] - 15;\n // 尾数处理\n fp16_mult[9:0] = (a[9:0] * b[9:0]) >> 10;\n end\nendfunction\n\nendmodule"], ["/Mayoiuta/hardware/rtl/core/conv_engine.v", "module Conv_Engine #(\n parameter KERNEL_SIZE = 3,\n parameter STRIDE = 1,\n parameter PAD = 1\n)(\n input wire clk,\n input wire rst_n,\n input wire [7:0] feature_map [0:31][0:31], // 32x32输入\n input wire [7:0] weight [0:2][0:2], // 3x3卷积核\n output reg [15:0] conv_result [0:30][0:30] // 输出特征图\n);\n\n// 滑动窗口生成器\nreg [7:0] window_buffer [0:2][0:2];\nalways @(posedge clk) begin\n for (int i = 0; i <= 30; i++) begin\n for (int j = 0; j <= 30; j++) begin\n // 窗口滑动控制\n if (j == 0) begin\n window_buffer[0][0] <= (i > 0) ? feature_map[i-1][j+0] : 0;\n window_buffer[1][0] <= feature_map[i][j+0];\n window_buffer[2][0] <= (i < 31) ? feature_map[i+1][j+0] : 0;\n end else begin\n window_buffer[0][j%3] <= window_buffer[0][(j-1)%3];\n window_buffer[1][j%3] <= window_buffer[1][(j-1)%3];\n window_buffer[2][j%3] <= window_buffer[2][(j-1)%3];\n end\n \n // 卷积计算\n if (j >= 2) begin\n conv_result[i][j-2] <= \n (window_buffer[0][0] * weight[0][0]) +\n (window_buffer[0][1] * weight[0][1]) +\n (window_buffer[0][2] * weight[0][2]) +\n (window_buffer[1][0] * weight[1][0]) +\n (window_buffer[1][1] * weight[1][1]) +\n (window_buffer[1][2] * weight[1][2]) +\n (window_buffer[2][0] * weight[2][0]) +\n (window_buffer[2][1] * weight[2][1]) +\n (window_buffer[2][2] * weight[2][2]);\n end\n end\n end\nend\n\nendmodule"], ["/Mayoiuta/hardware/rtl/core/pe_array.v", "module PE_Array #(\n parameter DATA_WIDTH = 16,\n parameter ARRAY_SIZE = 8\n)(\n input wire clk,\n input wire rst_n,\n input wire [DATA_WIDTH-1:0] north_in [ARRAY_SIZE-1:0],\n input wire [DATA_WIDTH-1:0] west_in [ARRAY_SIZE-1:0],\n output wire [DATA_WIDTH-1:0] south_out[ARRAY_SIZE-1:0],\n output wire [DATA_WIDTH-1:0] east_out [ARRAY_SIZE-1:0],\n input wire [3:0] opcode,\n input wire start,\n output wire done\n);\n\nwire [DATA_WIDTH-1:0] pe_data_h [ARRAY_SIZE][ARRAY_SIZE];\nwire [DATA_WIDTH-1:0] pe_data_v [ARRAY_SIZE][ARRAY_SIZE];\n\ngenerate\nfor (genvar i = 0; i < ARRAY_SIZE; i = i + 1) begin : row_gen\n for (genvar j = 0; j < ARRAY_SIZE; j = j + 1) begin : col_gen\n Processing_Element #(\n .DATA_WIDTH(DATA_WIDTH)\n ) u_pe (\n .clk(clk),\n .rst_n(rst_n),\n .north_in(i == 0 ? north_in[j] : pe_data_v[i-1][j]),\n .west_in(j == 0 ? west_in[i] : pe_data_h[i][j-1]),\n .south_out(pe_data_v[i][j]),\n .east_out(pe_data_h[i][j]),\n .opcode(opcode),\n .start(start),\n .done(done)\n );\n end\nend\nendgenerate\n\nassign south_out = pe_data_v[ARRAY_SIZE-1];\nassign east_out = pe_data_h[ARRAY_SIZE][ARRAY_SIZE-1];\n\nendmodule\n\nmodule Processing_Element #(\n parameter DATA_WIDTH = 16\n)(\n input wire clk,\n input wire rst_n,\n input wire [DATA_WIDTH-1:0] north_in,\n input wire [DATA_WIDTH-1:0] west_in,\n output reg [DATA_WIDTH-1:0] south_out,\n output reg [DATA_WIDTH-1:0] east_out,\n input wire [3:0] opcode,\n input wire start,\n output reg done\n);\n\nreg [DATA_WIDTH-1:0] accumulator;\nreg [DATA_WIDTH-1:0] weight_reg;\n\nalways @(posedge clk or negedge rst_n) begin\n if (!rst_n) begin\n accumulator <= 0;\n weight_reg <= 0;\n done <= 0;\n end else begin\n case(opcode)\n 4'h1: begin\n weight_reg <= west_in;\n done <= 1;\n end\n 4'h2: begin\n accumulator <= accumulator + (north_in * weight_reg);\n done <= 1;\n end\n 4'h3: begin\n south_out <= north_in;\n east_out <= west_in;\n done <= 1;\n end\n default: done <= 0;\n endcase\n end\nend\n\nendmodule"], ["/Mayoiuta/hardware/rtl/top/npu_soc.v", "module NPU_SOC #(\n parameter CORES = 4\n)(\n input wire clk,\n input wire rst_n,\n // 外部接口\n input wire [127:0] pcie_data,\n output reg [127:0] ddr_data,\n // 控制信号\n input wire interrupt,\n output reg [31:0] status\n);\n\n// 多核互连网络\nwire [127:0] noc_data [0:CORES-1];\nwire [31:0] noc_ctrl [0:CORES-1];\n\n// 主控制器\nnpu_controller u_controller(\n .clk(clk),\n .rst_n(rst_n),\n .cores_status(noc_ctrl),\n .global_config(pcie_data[95:0]),\n .interrupt(interrupt)\n);\n\n// 计算核心阵列\ngenerate\nfor (genvar i = 0; i < CORES; i = i + 1) begin\n npu_core #(\n .CORE_ID(i)\n ) u_core (\n .clk(clk),\n .rst_n(rst_n),\n .noc_in(noc_data[i]),\n .noc_out(noc_data[(i+1)%CORES]),\n .ctrl_in(noc_ctrl[i]),\n .ddr_interface(ddr_data)\n );\nend\nendgenerate\n\n// 性能监控\nperformance_monitor u_monitor(\n .clk(clk),\n .cores_active(noc_ctrl),\n .ddr_usage(ddr_data[127:96]),\n .power_status(status[31:16])\n);\n\nendmodule"], ["/Mayoiuta/hardware/rtl/sparse/sparse_engine.v", "module Sparse_Engine #(\n parameter SPARSE_THRESH = 0.3\n)(\n input wire clk,\n input wire rst_n,\n input wire [7:0] activation [0:31][0:31],\n input wire [7:0] weight [0:31][0:31],\n output reg [15:0] sparse_result,\n output reg sparse_valid\n);\n\n// 零值检测逻辑\nreg [31:0] zero_count;\nalways @(posedge clk) begin\n zero_count = 0;\n for (int i = 0; i < 32; i++) begin\n for (int j = 0; j < 32; j++) begin\n if (activation[i][j] == 0 || weight[i][j] == 0) begin\n zero_count <= zero_count + 1;\n end\n end\n end\n \n // 稀疏度判断\n if (zero_count > (32*32*SPARSE_THRESH)) begin\n sparse_valid <= 1'b1;\n // 触发稀疏计算模式\n sparse_result <= activation * weight; // 使用专用稀疏乘法器\n end else begin\n sparse_valid <= 1'b0;\n end\nend\n\n// 稀疏矩阵压缩格式处理\nwire [7:0] compressed_act;\nwire [4:0] act_idx;\nsparse_encoder encoder(\n .in_data(activation),\n .compressed(compressed_act),\n .index(act_idx)\n);\n\nwire [7:0] compressed_weight;\nwire [4:0] weight_idx;\nsparse_encoder encoder_w(\n .in_data(weight),\n .compressed(compressed_weight),\n .index(weight_idx)\n);\n\n// 稀疏矩阵乘法核心\nalways @(posedge clk) begin\n if (act_idx == weight_idx) begin\n sparse_result <= compressed_act * compressed_weight;\n end\nend\n\nendmodule"], ["/Mayoiuta/hardware/rtl/control/shape_adaptor.v", "module Shape_Adaptor #(\n parameter MAX_DIM = 4096\n)(\n input wire clk,\n input wire rst_n,\n input wire [15:0] in_height,\n input wire [15:0] in_width,\n input wire [15:0] kernel_h,\n input wire [15:0] kernel_w,\n output reg [15:0] out_height,\n output reg [15:0] out_width,\n output reg pad_enable\n);\n\n// 动态形状计算\nalways @(posedge clk) begin\n // 输出尺寸计算\n out_height <= (in_height + 2*PAD - kernel_h) / STRIDE + 1;\n out_width <= (in_width + 2*PAD - kernel_w) / STRIDE + 1;\n \n // 自动填充检测\n pad_enable <= ((in_height % STRIDE != 0) || \n (in_width % STRIDE != 0)) ? 1'b1 : 1'b0;\n \n // 边界保护\n if (out_height > MAX_DIM || out_width > MAX_DIM) begin\n $display(\"Error: Output dimension exceeds maximum limit!\");\n out_height <= MAX_DIM;\n out_width <= MAX_DIM;\n end\nend\n\n// 运行时配置接口\ntask configure(\n input [15:0] new_stride,\n input [15:0] new_pad\n);\n STRIDE = new_stride;\n PAD = new_pad;\nendtask\n\nendmodule"], ["/Mayoiuta/hardware/rtl/memory/mem_ctl.v", "module Memory_Controller #(\n parameter ADDR_WIDTH = 32,\n parameter DATA_WIDTH = 256,\n parameter BANK_NUM = 8\n)(\n input wire clk,\n input wire rst_n,\n // 主机接口\n input wire [ADDR_WIDTH-1:0] host_addr,\n input wire host_wr_en,\n input wire [DATA_WIDTH-1:0] host_wr_data,\n output reg [DATA_WIDTH-1:0] host_rd_data,\n // NPU接口\n input wire [ADDR_WIDTH-1:0] npu_addr,\n input wire npu_rd_en,\n output reg [DATA_WIDTH-1:0] npu_rd_data\n);\n\nreg [DATA_WIDTH-1:0] memory_bank [0:BANK_NUM-1][0:(1<<(ADDR_WIDTH-3))-1];\n\nalways @(posedge clk) begin\n if (host_wr_en) begin\n memory_bank[host_addr[2:0]][host_addr[ADDR_WIDTH-1:3]] <= host_wr_data;\n end\n host_rd_data <= memory_bank[host_addr[2:0]][host_addr[ADDR_WIDTH-1:3]];\n \n if (npu_rd_en) begin\n npu_rd_data <= memory_bank[npu_addr[2:0]][npu_addr[ADDR_WIDTH-1:3]];\n end\nend\n\n// ECC校验\necc_checker #(\n .DATA_WIDTH(DATA_WIDTH)\n) u_ecc (\n .data_in(host_wr_data),\n .data_out(host_rd_data),\n .syndrome()\n);\n\nendmodule"]], "task_instance_info": {"created_time": "2025-08-21 04:26:38", "created_task_model": "DeepSeek-R1", "class_skeleton": "module DVFS_Controller #(\n parameter VOLTAGE_LEVELS = 4,\n parameter FREQ_LEVELS = 4\n)(\n input wire clk,\n input wire rst_n,\n input wire [7:0] workload, // 0-255工作量指示\n output reg [1:0] voltage_level, // 00:0.8V ... 11:1.2V\n output reg [1:0] freq_level // 00:500MHz ... 11:1.2GHz\n) ; endmodule", "code_description": "This code segment functions to: Monitor historical workload patterns through a sliding window buffer, compute their moving average, and dynamically adjust system operating parameters based on predefined performance tiers corresponding to the calculated workload intensity."}, "inference_content": {"inference_model": "DeepSeek-R1", "inference_result": "```verilog\n[TASK_BEGIN]\nmodule DVFS_Controller #(\n parameter VOLTAGE_LEVELS = 4,\n parameter FREQ_LEVELS = 4\n)(\n input wire clk,\n input wire rst_n,\n input wire [7:0] workload, // 0-255工作量指示\n output reg [1:0] voltage_level, // 00:0.8V ... 11:1.2V\n output reg [1:0] freq_level // 00:500MHz ... 11:1.2GHz\n);\n \nalways @(posedge clk or negedge rst_n) begin\n if (!rst_n) begin\n voltage_level <= 2'b00;\n freq_level <= 2'b00;\n end\n else begin\n if (workload < 8'd64) begin\n voltage_level <= 2'b00;\n freq_level <= 2'b00;\n end\n else if (workload < 8'd128) begin\n voltage_level <= 2'b01;\n freq_level <= 2'b01;\n end\n else if (workload < 8'd192) begin\n voltage_level <= 2'b10;\n freq_level <= 2'b10;\n end\n else begin\n voltage_level <= 2'b11;\n freq_level <= 2'b11;\n end\n end\nend\n\nendmodule\n[TASK_END]\n```", "inference_time": "2025-08-21 04-27-05"}, "editdistance_info": {"edit_distance": 37.3333, "calculate_time": "2025-08-21 04:27:05", "true_code_clean": "module DVFS_Controller #(\n parameter VOLTAGE_LEVELS = 4,\n parameter FREQ_LEVELS = 4\n)(\n input wire clk,\n input wire rst_n,\n input wire [7:0] workload, \n output reg [1:0] voltage_level, \n output reg [1:0] freq_level \n);\nreg [15:0] history_buffer [0:7];\nalways @(posedge clk) begin\n history_buffer <= {history_buffer[6:0], workload};\nend\nwire [10:0] moving_avg;\nassign moving_avg = (history_buffer[0] + history_buffer[1] + history_buffer[2] + \n history_buffer[3] + history_buffer[4] + history_buffer[5] +\n history_buffer[6] + history_buffer[7]) >> 3;\nalways @(*) begin\n case(moving_avg)\n 0-50: {voltage_level, freq_level} = 4'b00_00;\n 51-100: {voltage_level, freq_level} = 4'b01_01;\n 101-150:{voltage_level, freq_level} = 4'b10_10;\n default:{voltage_level, freq_level} = 4'b11_11;\n endcase\nend\nendmodule", "predict_code_clean": "module DVFS_Controller #(\n parameter VOLTAGE_LEVELS = 4,\n parameter FREQ_LEVELS = 4\n)(\n input wire clk,\n input wire rst_n,\n input wire [7:0] workload, \n output reg [1:0] voltage_level, \n output reg [1:0] freq_level \n);\nalways @(posedge clk or negedge rst_n) begin\n if (!rst_n) begin\n voltage_level <= 2'b00;\n freq_level <= 2'b00;\n end\n else begin\n if (workload < 8'd64) begin\n voltage_level <= 2'b00;\n freq_level <= 2'b00;\n end\n else if (workload < 8'd128) begin\n voltage_level <= 2'b01;\n freq_level <= 2'b01;\n end\n else if (workload < 8'd192) begin\n voltage_level <= 2'b10;\n freq_level <= 2'b10;\n end\n else begin\n voltage_level <= 2'b11;\n freq_level <= 2'b11;\n end\n end\nend\nendmodule"}}
3
+ {"repo_name": "Mayoiuta", "file_name": "/Mayoiuta/hardware/rtl/top/npu_soc.v", "inference_info": {"prefix_code": "", "suffix_code": "", "middle_code": "module NPU_SOC #(\n parameter CORES = 4\n)(\n input wire clk,\n input wire rst_n,\n input wire [127:0] pcie_data,\n output reg [127:0] ddr_data,\n input wire interrupt,\n output reg [31:0] status\n);\nwire [127:0] noc_data [0:CORES-1];\nwire [31:0] noc_ctrl [0:CORES-1];\nnpu_controller u_controller(\n .clk(clk),\n .rst_n(rst_n),\n .cores_status(noc_ctrl),\n .global_config(pcie_data[95:0]),\n .interrupt(interrupt)\n);\ngenerate\nfor (genvar i = 0; i < CORES; i = i + 1) begin\n npu_core #(\n .CORE_ID(i)\n ) u_core (\n .clk(clk),\n .rst_n(rst_n),\n .noc_in(noc_data[i]),\n .noc_out(noc_data[(i+1)%CORES]),\n .ctrl_in(noc_ctrl[i]),\n .ddr_interface(ddr_data)\n );\nend\nendgenerate\nperformance_monitor u_monitor(\n .clk(clk),\n .cores_active(noc_ctrl),\n .ddr_usage(ddr_data[127:96]),\n .power_status(status[31:16])\n);\nendmodule", "code_description": null, "fill_type": "CLASS_TYPE", "language_type": "verilog", "sub_task_type": null}, "context_code": [["/Mayoiuta/hardware/rtl/core/pe_array.v", "module PE_Array #(\n parameter DATA_WIDTH = 16,\n parameter ARRAY_SIZE = 8\n)(\n input wire clk,\n input wire rst_n,\n input wire [DATA_WIDTH-1:0] north_in [ARRAY_SIZE-1:0],\n input wire [DATA_WIDTH-1:0] west_in [ARRAY_SIZE-1:0],\n output wire [DATA_WIDTH-1:0] south_out[ARRAY_SIZE-1:0],\n output wire [DATA_WIDTH-1:0] east_out [ARRAY_SIZE-1:0],\n input wire [3:0] opcode,\n input wire start,\n output wire done\n);\n\nwire [DATA_WIDTH-1:0] pe_data_h [ARRAY_SIZE][ARRAY_SIZE];\nwire [DATA_WIDTH-1:0] pe_data_v [ARRAY_SIZE][ARRAY_SIZE];\n\ngenerate\nfor (genvar i = 0; i < ARRAY_SIZE; i = i + 1) begin : row_gen\n for (genvar j = 0; j < ARRAY_SIZE; j = j + 1) begin : col_gen\n Processing_Element #(\n .DATA_WIDTH(DATA_WIDTH)\n ) u_pe (\n .clk(clk),\n .rst_n(rst_n),\n .north_in(i == 0 ? north_in[j] : pe_data_v[i-1][j]),\n .west_in(j == 0 ? west_in[i] : pe_data_h[i][j-1]),\n .south_out(pe_data_v[i][j]),\n .east_out(pe_data_h[i][j]),\n .opcode(opcode),\n .start(start),\n .done(done)\n );\n end\nend\nendgenerate\n\nassign south_out = pe_data_v[ARRAY_SIZE-1];\nassign east_out = pe_data_h[ARRAY_SIZE][ARRAY_SIZE-1];\n\nendmodule\n\nmodule Processing_Element #(\n parameter DATA_WIDTH = 16\n)(\n input wire clk,\n input wire rst_n,\n input wire [DATA_WIDTH-1:0] north_in,\n input wire [DATA_WIDTH-1:0] west_in,\n output reg [DATA_WIDTH-1:0] south_out,\n output reg [DATA_WIDTH-1:0] east_out,\n input wire [3:0] opcode,\n input wire start,\n output reg done\n);\n\nreg [DATA_WIDTH-1:0] accumulator;\nreg [DATA_WIDTH-1:0] weight_reg;\n\nalways @(posedge clk or negedge rst_n) begin\n if (!rst_n) begin\n accumulator <= 0;\n weight_reg <= 0;\n done <= 0;\n end else begin\n case(opcode)\n 4'h1: begin\n weight_reg <= west_in;\n done <= 1;\n end\n 4'h2: begin\n accumulator <= accumulator + (north_in * weight_reg);\n done <= 1;\n end\n 4'h3: begin\n south_out <= north_in;\n east_out <= west_in;\n done <= 1;\n end\n default: done <= 0;\n endcase\n end\nend\n\nendmodule"], ["/Mayoiuta/hardware/rtl/memory/mem_ctl.v", "module Memory_Controller #(\n parameter ADDR_WIDTH = 32,\n parameter DATA_WIDTH = 256,\n parameter BANK_NUM = 8\n)(\n input wire clk,\n input wire rst_n,\n // 主机接口\n input wire [ADDR_WIDTH-1:0] host_addr,\n input wire host_wr_en,\n input wire [DATA_WIDTH-1:0] host_wr_data,\n output reg [DATA_WIDTH-1:0] host_rd_data,\n // NPU接口\n input wire [ADDR_WIDTH-1:0] npu_addr,\n input wire npu_rd_en,\n output reg [DATA_WIDTH-1:0] npu_rd_data\n);\n\nreg [DATA_WIDTH-1:0] memory_bank [0:BANK_NUM-1][0:(1<<(ADDR_WIDTH-3))-1];\n\nalways @(posedge clk) begin\n if (host_wr_en) begin\n memory_bank[host_addr[2:0]][host_addr[ADDR_WIDTH-1:3]] <= host_wr_data;\n end\n host_rd_data <= memory_bank[host_addr[2:0]][host_addr[ADDR_WIDTH-1:3]];\n \n if (npu_rd_en) begin\n npu_rd_data <= memory_bank[npu_addr[2:0]][npu_addr[ADDR_WIDTH-1:3]];\n end\nend\n\n// ECC校验\necc_checker #(\n .DATA_WIDTH(DATA_WIDTH)\n) u_ecc (\n .data_in(host_wr_data),\n .data_out(host_rd_data),\n .syndrome()\n);\n\nendmodule"], ["/Mayoiuta/hardware/rtl/sparse/sparse_engine.v", "module Sparse_Engine #(\n parameter SPARSE_THRESH = 0.3\n)(\n input wire clk,\n input wire rst_n,\n input wire [7:0] activation [0:31][0:31],\n input wire [7:0] weight [0:31][0:31],\n output reg [15:0] sparse_result,\n output reg sparse_valid\n);\n\n// 零值检测逻辑\nreg [31:0] zero_count;\nalways @(posedge clk) begin\n zero_count = 0;\n for (int i = 0; i < 32; i++) begin\n for (int j = 0; j < 32; j++) begin\n if (activation[i][j] == 0 || weight[i][j] == 0) begin\n zero_count <= zero_count + 1;\n end\n end\n end\n \n // 稀疏度判断\n if (zero_count > (32*32*SPARSE_THRESH)) begin\n sparse_valid <= 1'b1;\n // 触发稀疏计算模式\n sparse_result <= activation * weight; // 使用专用稀疏乘法器\n end else begin\n sparse_valid <= 1'b0;\n end\nend\n\n// 稀疏矩阵压缩格式处理\nwire [7:0] compressed_act;\nwire [4:0] act_idx;\nsparse_encoder encoder(\n .in_data(activation),\n .compressed(compressed_act),\n .index(act_idx)\n);\n\nwire [7:0] compressed_weight;\nwire [4:0] weight_idx;\nsparse_encoder encoder_w(\n .in_data(weight),\n .compressed(compressed_weight),\n .index(weight_idx)\n);\n\n// 稀疏矩阵乘法核心\nalways @(posedge clk) begin\n if (act_idx == weight_idx) begin\n sparse_result <= compressed_act * compressed_weight;\n end\nend\n\nendmodule"], ["/Mayoiuta/hardware/rtl/memory/data_reorder.v", "module Data_Reorder #(\n parameter CHANNELS = 64,\n parameter TILE_SIZE = 8\n)(\n input wire clk,\n input wire rst_n,\n input wire [127:0] mem_data,\n output reg [127:0] pe_data,\n input wire [1:0] data_format // 0:NCHW 1:NHWC 2:Blocked\n);\n\nreg [127:0] reorder_buffer [0:CHANNELS/TILE_SIZE-1][0:TILE_SIZE-1];\n\n// 数据格式转换引擎\nalways @(posedge clk) begin\n case(data_format)\n 2'b00: // NCHW -> PE阵列格式\n for (int c = 0; c < CHANNELS; c += TILE_SIZE) begin\n for (int t = 0; t < TILE_SIZE; t++) begin\n reorder_buffer[c/TILE_SIZE][t] <= \n {mem_data[127:112], mem_data[95:80], // 通道优先\n mem_data[63:48], mem_data[31:16]};\n end\n end\n \n 2'b01: // NHWC -> PE阵列格式\n for (int h = 0; h < TILE_SIZE; h++) begin\n reorder_buffer[h%4][h/4] <= \n {mem_data[127:120], mem_data[95:88], // 空间优先\n mem_data[63:56], mem_data[31:24]};\n end\n \n 2'b10: // Blocked格式\n pe_data <= mem_data; // 直接传递\n endcase\nend\n\n// 输出调度\nalways @(posedge clk) begin\n pe_data <= reorder_buffer[read_ptr];\n read_ptr <= (read_ptr == (CHANNELS/TILE_SIZE-1)) ? 0 : read_ptr + 1;\nend\n\nendmodule"], ["/Mayoiuta/hardware/rtl/core/conv_engine.v", "module Conv_Engine #(\n parameter KERNEL_SIZE = 3,\n parameter STRIDE = 1,\n parameter PAD = 1\n)(\n input wire clk,\n input wire rst_n,\n input wire [7:0] feature_map [0:31][0:31], // 32x32输入\n input wire [7:0] weight [0:2][0:2], // 3x3卷积核\n output reg [15:0] conv_result [0:30][0:30] // 输出特征图\n);\n\n// 滑动窗口生成器\nreg [7:0] window_buffer [0:2][0:2];\nalways @(posedge clk) begin\n for (int i = 0; i <= 30; i++) begin\n for (int j = 0; j <= 30; j++) begin\n // 窗口滑动控制\n if (j == 0) begin\n window_buffer[0][0] <= (i > 0) ? feature_map[i-1][j+0] : 0;\n window_buffer[1][0] <= feature_map[i][j+0];\n window_buffer[2][0] <= (i < 31) ? feature_map[i+1][j+0] : 0;\n end else begin\n window_buffer[0][j%3] <= window_buffer[0][(j-1)%3];\n window_buffer[1][j%3] <= window_buffer[1][(j-1)%3];\n window_buffer[2][j%3] <= window_buffer[2][(j-1)%3];\n end\n \n // 卷积计算\n if (j >= 2) begin\n conv_result[i][j-2] <= \n (window_buffer[0][0] * weight[0][0]) +\n (window_buffer[0][1] * weight[0][1]) +\n (window_buffer[0][2] * weight[0][2]) +\n (window_buffer[1][0] * weight[1][0]) +\n (window_buffer[1][1] * weight[1][1]) +\n (window_buffer[1][2] * weight[1][2]) +\n (window_buffer[2][0] * weight[2][0]) +\n (window_buffer[2][1] * weight[2][1]) +\n (window_buffer[2][2] * weight[2][2]);\n end\n end\n end\nend\n\nendmodule"], ["/Mayoiuta/hardware/rtl/power/dvfs_ctrl.v", "module DVFS_Controller #(\n parameter VOLTAGE_LEVELS = 4,\n parameter FREQ_LEVELS = 4\n)(\n input wire clk,\n input wire rst_n,\n input wire [7:0] workload, // 0-255工作量指示\n output reg [1:0] voltage_level, // 00:0.8V ... 11:1.2V\n output reg [1:0] freq_level // 00:500MHz ... 11:1.2GHz\n);\n\nreg [15:0] history_buffer [0:7];\nalways @(posedge clk) begin\n history_buffer <= {history_buffer[6:0], workload};\nend\n\n// 移动平均计算\nwire [10:0] moving_avg;\nassign moving_avg = (history_buffer[0] + history_buffer[1] + history_buffer[2] + \n history_buffer[3] + history_buffer[4] + history_buffer[5] +\n history_buffer[6] + history_buffer[7]) >> 3;\n\n// 调节策略\nalways @(*) begin\n case(moving_avg)\n 0-50: {voltage_level, freq_level} = 4'b00_00;\n 51-100: {voltage_level, freq_level} = 4'b01_01;\n 101-150:{voltage_level, freq_level} = 4'b10_10;\n default:{voltage_level, freq_level} = 4'b11_11;\n endcase\nend\n\nendmodule"], ["/Mayoiuta/hardware/rtl/core/adaptive_pe.v", "module Adaptive_PE #(\n parameter INT8_MODE = 1,\n parameter FP16_MODE = 0\n)(\n input wire clk,\n input wire rst_n,\n input wire [3:0] precision_mode,\n input wire [31:0] din_a,\n input wire [31:0] din_b,\n output reg [31:0] dout\n);\n\n// 多精度计算单元\nalways @(posedge clk) begin\n if (!rst_n) dout <= 0;\n else begin\n case(precision_mode)\n 4'b0001: // INT8模式\n dout <= $signed(din_a[7:0]) * $signed(din_b[7:0]);\n 4'b0010: // FP16模式\n dout <= fp16_mult(din_a[15:0], din_b[15:0]);\n 4'b0100: // BFLOAT16\n dout <= {din_a[31:16], 16'b0} * {din_b[31:16], 16'b0};\n default: // INT16\n dout <= $signed(din_a) * $signed(din_b);\n endcase\n end\nend\n\n// IEEE 754半精度浮点乘法实现\nfunction [15:0] fp16_mult;\n input [15:0] a, b;\n begin\n fp16_mult[15] = a[15] ^ b[15];\n // 指数处理\n if (a[14:10] == 0 || b[14:10] == 0) \n fp16_mult[14:10] = 0;\n else \n fp16_mult[14:10] = a[14:10] + b[14:10] - 15;\n // 尾数处理\n fp16_mult[9:0] = (a[9:0] * b[9:0]) >> 10;\n end\nendfunction\n\nendmodule"], ["/Mayoiuta/hardware/rtl/control/shape_adaptor.v", "module Shape_Adaptor #(\n parameter MAX_DIM = 4096\n)(\n input wire clk,\n input wire rst_n,\n input wire [15:0] in_height,\n input wire [15:0] in_width,\n input wire [15:0] kernel_h,\n input wire [15:0] kernel_w,\n output reg [15:0] out_height,\n output reg [15:0] out_width,\n output reg pad_enable\n);\n\n// 动态形状计算\nalways @(posedge clk) begin\n // 输出尺寸计算\n out_height <= (in_height + 2*PAD - kernel_h) / STRIDE + 1;\n out_width <= (in_width + 2*PAD - kernel_w) / STRIDE + 1;\n \n // 自动填充检测\n pad_enable <= ((in_height % STRIDE != 0) || \n (in_width % STRIDE != 0)) ? 1'b1 : 1'b0;\n \n // 边界保护\n if (out_height > MAX_DIM || out_width > MAX_DIM) begin\n $display(\"Error: Output dimension exceeds maximum limit!\");\n out_height <= MAX_DIM;\n out_width <= MAX_DIM;\n end\nend\n\n// 运行时配置接口\ntask configure(\n input [15:0] new_stride,\n input [15:0] new_pad\n);\n STRIDE = new_stride;\n PAD = new_pad;\nendtask\n\nendmodule"]], "task_instance_info": {"created_time": "2025-08-21 04:26:38", "created_task_model": "DeepSeek-R1", "class_skeleton": "module NPU_SOC #(\n parameter CORES = 4\n)(\n input wire clk,\n input wire rst_n,\n // 外部接口\n input wire [127:0] pcie_data,\n output reg [127:0] ddr_data,\n // 控制信号\n input wire interrupt,\n output reg [31:0] status\n) ; // 多核互连网络 endmodule", "code_description": "This code segment functions to: Coordinate multiple parallel processing units through a ring-based interconnect topology, manage shared memory resource allocation, and aggregate operational metrics including utilization statistics and power consumption characteristics across the computing array."}, "inference_content": {"inference_model": "DeepSeek-R1", "inference_result": "```verilog\n[TASK_BEGIN]\nmodule NPU_SOC #(\n parameter CORES = 4\n)(\n input wire clk,\n input wire rst_n,\n // 外部接口\n input wire [127:0] pcie_data,\n output reg [127:0] ddr_data,\n // 控制信号\n input wire interrupt,\n output reg [31:0] status\n);\n // 多核互连网络\n // Add core array and interconnect logic here\n \nendmodule\n[TASK_END]\n```", "inference_time": "2025-08-21 04-27-13"}, "editdistance_info": {"edit_distance": 23.6246, "calculate_time": "2025-08-21 04:27:13", "true_code_clean": "module NPU_SOC #(\n parameter CORES = 4\n)(\n input wire clk,\n input wire rst_n,\n input wire [127:0] pcie_data,\n output reg [127:0] ddr_data,\n input wire interrupt,\n output reg [31:0] status\n);\nwire [127:0] noc_data [0:CORES-1];\nwire [31:0] noc_ctrl [0:CORES-1];\nnpu_controller u_controller(\n .clk(clk),\n .rst_n(rst_n),\n .cores_status(noc_ctrl),\n .global_config(pcie_data[95:0]),\n .interrupt(interrupt)\n);\ngenerate\nfor (genvar i = 0; i < CORES; i = i + 1) begin\n npu_core #(\n .CORE_ID(i)\n ) u_core (\n .clk(clk),\n .rst_n(rst_n),\n .noc_in(noc_data[i]),\n .noc_out(noc_data[(i+1)%CORES]),\n .ctrl_in(noc_ctrl[i]),\n .ddr_interface(ddr_data)\n );\nend\nendgenerate\nperformance_monitor u_monitor(\n .clk(clk),\n .cores_active(noc_ctrl),\n .ddr_usage(ddr_data[127:96]),\n .power_status(status[31:16])\n);\nendmodule", "predict_code_clean": "module NPU_SOC #(\n parameter CORES = 4\n)(\n input wire clk,\n input wire rst_n,\n input wire [127:0] pcie_data,\n output reg [127:0] ddr_data,\n input wire interrupt,\n output reg [31:0] status\n);\nendmodule"}}
4
+ {"repo_name": "Mayoiuta", "file_name": "/Mayoiuta/hardware/rtl/top/npu_soc.v", "inference_info": {"prefix_code": "", "suffix_code": "", "middle_code": "module NPU_SOC #(\n parameter CORES = 4\n)(\n input wire clk,\n input wire rst_n,\n input wire [127:0] pcie_data,\n output reg [127:0] ddr_data,\n input wire interrupt,\n output reg [31:0] status\n);\nwire [127:0] noc_data [0:CORES-1];\nwire [31:0] noc_ctrl [0:CORES-1];\nnpu_controller u_controller(\n .clk(clk),\n .rst_n(rst_n),\n .cores_status(noc_ctrl),\n .global_config(pcie_data[95:0]),\n .interrupt(interrupt)\n);\ngenerate\nfor (genvar i = 0; i < CORES; i = i + 1) begin\n npu_core #(\n .CORE_ID(i)\n ) u_core (\n .clk(clk),\n .rst_n(rst_n),\n .noc_in(noc_data[i]),\n .noc_out(noc_data[(i+1)%CORES]),\n .ctrl_in(noc_ctrl[i]),\n .ddr_interface(ddr_data)\n );\nend\nendgenerate\nperformance_monitor u_monitor(\n .clk(clk),\n .cores_active(noc_ctrl),\n .ddr_usage(ddr_data[127:96]),\n .power_status(status[31:16])\n);\nendmodule", "code_description": null, "fill_type": "CLASS_TYPE", "language_type": "verilog", "sub_task_type": null}, "context_code": [["/Mayoiuta/hardware/rtl/core/pe_array.v", "module PE_Array #(\n parameter DATA_WIDTH = 16,\n parameter ARRAY_SIZE = 8\n)(\n input wire clk,\n input wire rst_n,\n input wire [DATA_WIDTH-1:0] north_in [ARRAY_SIZE-1:0],\n input wire [DATA_WIDTH-1:0] west_in [ARRAY_SIZE-1:0],\n output wire [DATA_WIDTH-1:0] south_out[ARRAY_SIZE-1:0],\n output wire [DATA_WIDTH-1:0] east_out [ARRAY_SIZE-1:0],\n input wire [3:0] opcode,\n input wire start,\n output wire done\n);\n\nwire [DATA_WIDTH-1:0] pe_data_h [ARRAY_SIZE][ARRAY_SIZE];\nwire [DATA_WIDTH-1:0] pe_data_v [ARRAY_SIZE][ARRAY_SIZE];\n\ngenerate\nfor (genvar i = 0; i < ARRAY_SIZE; i = i + 1) begin : row_gen\n for (genvar j = 0; j < ARRAY_SIZE; j = j + 1) begin : col_gen\n Processing_Element #(\n .DATA_WIDTH(DATA_WIDTH)\n ) u_pe (\n .clk(clk),\n .rst_n(rst_n),\n .north_in(i == 0 ? north_in[j] : pe_data_v[i-1][j]),\n .west_in(j == 0 ? west_in[i] : pe_data_h[i][j-1]),\n .south_out(pe_data_v[i][j]),\n .east_out(pe_data_h[i][j]),\n .opcode(opcode),\n .start(start),\n .done(done)\n );\n end\nend\nendgenerate\n\nassign south_out = pe_data_v[ARRAY_SIZE-1];\nassign east_out = pe_data_h[ARRAY_SIZE][ARRAY_SIZE-1];\n\nendmodule\n\nmodule Processing_Element #(\n parameter DATA_WIDTH = 16\n)(\n input wire clk,\n input wire rst_n,\n input wire [DATA_WIDTH-1:0] north_in,\n input wire [DATA_WIDTH-1:0] west_in,\n output reg [DATA_WIDTH-1:0] south_out,\n output reg [DATA_WIDTH-1:0] east_out,\n input wire [3:0] opcode,\n input wire start,\n output reg done\n);\n\nreg [DATA_WIDTH-1:0] accumulator;\nreg [DATA_WIDTH-1:0] weight_reg;\n\nalways @(posedge clk or negedge rst_n) begin\n if (!rst_n) begin\n accumulator <= 0;\n weight_reg <= 0;\n done <= 0;\n end else begin\n case(opcode)\n 4'h1: begin\n weight_reg <= west_in;\n done <= 1;\n end\n 4'h2: begin\n accumulator <= accumulator + (north_in * weight_reg);\n done <= 1;\n end\n 4'h3: begin\n south_out <= north_in;\n east_out <= west_in;\n done <= 1;\n end\n default: done <= 0;\n endcase\n end\nend\n\nendmodule"], ["/Mayoiuta/hardware/rtl/memory/mem_ctl.v", "module Memory_Controller #(\n parameter ADDR_WIDTH = 32,\n parameter DATA_WIDTH = 256,\n parameter BANK_NUM = 8\n)(\n input wire clk,\n input wire rst_n,\n // 主机接口\n input wire [ADDR_WIDTH-1:0] host_addr,\n input wire host_wr_en,\n input wire [DATA_WIDTH-1:0] host_wr_data,\n output reg [DATA_WIDTH-1:0] host_rd_data,\n // NPU接口\n input wire [ADDR_WIDTH-1:0] npu_addr,\n input wire npu_rd_en,\n output reg [DATA_WIDTH-1:0] npu_rd_data\n);\n\nreg [DATA_WIDTH-1:0] memory_bank [0:BANK_NUM-1][0:(1<<(ADDR_WIDTH-3))-1];\n\nalways @(posedge clk) begin\n if (host_wr_en) begin\n memory_bank[host_addr[2:0]][host_addr[ADDR_WIDTH-1:3]] <= host_wr_data;\n end\n host_rd_data <= memory_bank[host_addr[2:0]][host_addr[ADDR_WIDTH-1:3]];\n \n if (npu_rd_en) begin\n npu_rd_data <= memory_bank[npu_addr[2:0]][npu_addr[ADDR_WIDTH-1:3]];\n end\nend\n\n// ECC校验\necc_checker #(\n .DATA_WIDTH(DATA_WIDTH)\n) u_ecc (\n .data_in(host_wr_data),\n .data_out(host_rd_data),\n .syndrome()\n);\n\nendmodule"], ["/Mayoiuta/hardware/rtl/sparse/sparse_engine.v", "module Sparse_Engine #(\n parameter SPARSE_THRESH = 0.3\n)(\n input wire clk,\n input wire rst_n,\n input wire [7:0] activation [0:31][0:31],\n input wire [7:0] weight [0:31][0:31],\n output reg [15:0] sparse_result,\n output reg sparse_valid\n);\n\n// 零值检测逻辑\nreg [31:0] zero_count;\nalways @(posedge clk) begin\n zero_count = 0;\n for (int i = 0; i < 32; i++) begin\n for (int j = 0; j < 32; j++) begin\n if (activation[i][j] == 0 || weight[i][j] == 0) begin\n zero_count <= zero_count + 1;\n end\n end\n end\n \n // 稀疏度判断\n if (zero_count > (32*32*SPARSE_THRESH)) begin\n sparse_valid <= 1'b1;\n // 触发稀疏计算模式\n sparse_result <= activation * weight; // 使用专用稀疏乘法器\n end else begin\n sparse_valid <= 1'b0;\n end\nend\n\n// 稀疏矩阵压缩格式处理\nwire [7:0] compressed_act;\nwire [4:0] act_idx;\nsparse_encoder encoder(\n .in_data(activation),\n .compressed(compressed_act),\n .index(act_idx)\n);\n\nwire [7:0] compressed_weight;\nwire [4:0] weight_idx;\nsparse_encoder encoder_w(\n .in_data(weight),\n .compressed(compressed_weight),\n .index(weight_idx)\n);\n\n// 稀疏矩阵乘法核心\nalways @(posedge clk) begin\n if (act_idx == weight_idx) begin\n sparse_result <= compressed_act * compressed_weight;\n end\nend\n\nendmodule"], ["/Mayoiuta/hardware/rtl/memory/data_reorder.v", "module Data_Reorder #(\n parameter CHANNELS = 64,\n parameter TILE_SIZE = 8\n)(\n input wire clk,\n input wire rst_n,\n input wire [127:0] mem_data,\n output reg [127:0] pe_data,\n input wire [1:0] data_format // 0:NCHW 1:NHWC 2:Blocked\n);\n\nreg [127:0] reorder_buffer [0:CHANNELS/TILE_SIZE-1][0:TILE_SIZE-1];\n\n// 数据格式转换引擎\nalways @(posedge clk) begin\n case(data_format)\n 2'b00: // NCHW -> PE阵列格式\n for (int c = 0; c < CHANNELS; c += TILE_SIZE) begin\n for (int t = 0; t < TILE_SIZE; t++) begin\n reorder_buffer[c/TILE_SIZE][t] <= \n {mem_data[127:112], mem_data[95:80], // 通道优先\n mem_data[63:48], mem_data[31:16]};\n end\n end\n \n 2'b01: // NHWC -> PE阵列格式\n for (int h = 0; h < TILE_SIZE; h++) begin\n reorder_buffer[h%4][h/4] <= \n {mem_data[127:120], mem_data[95:88], // 空间优先\n mem_data[63:56], mem_data[31:24]};\n end\n \n 2'b10: // Blocked格式\n pe_data <= mem_data; // 直接传递\n endcase\nend\n\n// 输出调度\nalways @(posedge clk) begin\n pe_data <= reorder_buffer[read_ptr];\n read_ptr <= (read_ptr == (CHANNELS/TILE_SIZE-1)) ? 0 : read_ptr + 1;\nend\n\nendmodule"], ["/Mayoiuta/hardware/rtl/core/conv_engine.v", "module Conv_Engine #(\n parameter KERNEL_SIZE = 3,\n parameter STRIDE = 1,\n parameter PAD = 1\n)(\n input wire clk,\n input wire rst_n,\n input wire [7:0] feature_map [0:31][0:31], // 32x32输入\n input wire [7:0] weight [0:2][0:2], // 3x3卷积核\n output reg [15:0] conv_result [0:30][0:30] // 输出特征图\n);\n\n// 滑动窗口生成器\nreg [7:0] window_buffer [0:2][0:2];\nalways @(posedge clk) begin\n for (int i = 0; i <= 30; i++) begin\n for (int j = 0; j <= 30; j++) begin\n // 窗口滑动控制\n if (j == 0) begin\n window_buffer[0][0] <= (i > 0) ? feature_map[i-1][j+0] : 0;\n window_buffer[1][0] <= feature_map[i][j+0];\n window_buffer[2][0] <= (i < 31) ? feature_map[i+1][j+0] : 0;\n end else begin\n window_buffer[0][j%3] <= window_buffer[0][(j-1)%3];\n window_buffer[1][j%3] <= window_buffer[1][(j-1)%3];\n window_buffer[2][j%3] <= window_buffer[2][(j-1)%3];\n end\n \n // 卷积计算\n if (j >= 2) begin\n conv_result[i][j-2] <= \n (window_buffer[0][0] * weight[0][0]) +\n (window_buffer[0][1] * weight[0][1]) +\n (window_buffer[0][2] * weight[0][2]) +\n (window_buffer[1][0] * weight[1][0]) +\n (window_buffer[1][1] * weight[1][1]) +\n (window_buffer[1][2] * weight[1][2]) +\n (window_buffer[2][0] * weight[2][0]) +\n (window_buffer[2][1] * weight[2][1]) +\n (window_buffer[2][2] * weight[2][2]);\n end\n end\n end\nend\n\nendmodule"], ["/Mayoiuta/hardware/rtl/power/dvfs_ctrl.v", "module DVFS_Controller #(\n parameter VOLTAGE_LEVELS = 4,\n parameter FREQ_LEVELS = 4\n)(\n input wire clk,\n input wire rst_n,\n input wire [7:0] workload, // 0-255工作量指示\n output reg [1:0] voltage_level, // 00:0.8V ... 11:1.2V\n output reg [1:0] freq_level // 00:500MHz ... 11:1.2GHz\n);\n\nreg [15:0] history_buffer [0:7];\nalways @(posedge clk) begin\n history_buffer <= {history_buffer[6:0], workload};\nend\n\n// 移动平均计算\nwire [10:0] moving_avg;\nassign moving_avg = (history_buffer[0] + history_buffer[1] + history_buffer[2] + \n history_buffer[3] + history_buffer[4] + history_buffer[5] +\n history_buffer[6] + history_buffer[7]) >> 3;\n\n// 调节策略\nalways @(*) begin\n case(moving_avg)\n 0-50: {voltage_level, freq_level} = 4'b00_00;\n 51-100: {voltage_level, freq_level} = 4'b01_01;\n 101-150:{voltage_level, freq_level} = 4'b10_10;\n default:{voltage_level, freq_level} = 4'b11_11;\n endcase\nend\n\nendmodule"], ["/Mayoiuta/hardware/rtl/core/adaptive_pe.v", "module Adaptive_PE #(\n parameter INT8_MODE = 1,\n parameter FP16_MODE = 0\n)(\n input wire clk,\n input wire rst_n,\n input wire [3:0] precision_mode,\n input wire [31:0] din_a,\n input wire [31:0] din_b,\n output reg [31:0] dout\n);\n\n// 多精度计算单元\nalways @(posedge clk) begin\n if (!rst_n) dout <= 0;\n else begin\n case(precision_mode)\n 4'b0001: // INT8模式\n dout <= $signed(din_a[7:0]) * $signed(din_b[7:0]);\n 4'b0010: // FP16模式\n dout <= fp16_mult(din_a[15:0], din_b[15:0]);\n 4'b0100: // BFLOAT16\n dout <= {din_a[31:16], 16'b0} * {din_b[31:16], 16'b0};\n default: // INT16\n dout <= $signed(din_a) * $signed(din_b);\n endcase\n end\nend\n\n// IEEE 754半精度浮点乘法实现\nfunction [15:0] fp16_mult;\n input [15:0] a, b;\n begin\n fp16_mult[15] = a[15] ^ b[15];\n // 指数处���\n if (a[14:10] == 0 || b[14:10] == 0) \n fp16_mult[14:10] = 0;\n else \n fp16_mult[14:10] = a[14:10] + b[14:10] - 15;\n // 尾数处理\n fp16_mult[9:0] = (a[9:0] * b[9:0]) >> 10;\n end\nendfunction\n\nendmodule"], ["/Mayoiuta/hardware/rtl/control/shape_adaptor.v", "module Shape_Adaptor #(\n parameter MAX_DIM = 4096\n)(\n input wire clk,\n input wire rst_n,\n input wire [15:0] in_height,\n input wire [15:0] in_width,\n input wire [15:0] kernel_h,\n input wire [15:0] kernel_w,\n output reg [15:0] out_height,\n output reg [15:0] out_width,\n output reg pad_enable\n);\n\n// 动态形状计算\nalways @(posedge clk) begin\n // 输出尺寸计算\n out_height <= (in_height + 2*PAD - kernel_h) / STRIDE + 1;\n out_width <= (in_width + 2*PAD - kernel_w) / STRIDE + 1;\n \n // 自动填充检测\n pad_enable <= ((in_height % STRIDE != 0) || \n (in_width % STRIDE != 0)) ? 1'b1 : 1'b0;\n \n // 边界保护\n if (out_height > MAX_DIM || out_width > MAX_DIM) begin\n $display(\"Error: Output dimension exceeds maximum limit!\");\n out_height <= MAX_DIM;\n out_width <= MAX_DIM;\n end\nend\n\n// 运行时配置接口\ntask configure(\n input [15:0] new_stride,\n input [15:0] new_pad\n);\n STRIDE = new_stride;\n PAD = new_pad;\nendtask\n\nendmodule"]], "task_instance_info": {"created_time": "2025-08-21 04:26:38", "created_task_model": "DeepSeek-R1", "class_skeleton": "module NPU_SOC #(\n parameter CORES = 4\n)(\n input wire clk,\n input wire rst_n,\n // 外部接口\n input wire [127:0] pcie_data,\n output reg [127:0] ddr_data,\n // 控制信号\n input wire interrupt,\n output reg [31:0] status\n) ; // 多核互连网络 endmodule", "code_description": "This code segment functions to: Implement a scalable neural processing system with configurable compute units, manage inter-core communication through a ring-based network, and monitor hardware performance metrics including memory utilization and power consumption."}, "inference_content": {"inference_model": "DeepSeek-R1", "inference_result": "```verilog\n[TASK_BEGIN]\n // 多核状态寄存器\n reg [31:0] core_status [0:CORES-1];\n \n // 核间通信总线\n wire [127:0] core_input [0:CORES-1];\n wire [127:0] core_output [0:CORES-1];\n \n // 内存接口\n reg [31:0] mem_addr [0:CORES-1];\n reg [127:0] mem_wr_data [0:CORES-1];\n wire [127:0] mem_rd_data [0:CORES-1];\n reg mem_read_en [0:CORES-1];\n reg mem_write_en [0:CORES-1];\n\n // 多核实例化\n generate\n genvar i;\n for (i=0; i<CORES; i=i+1) begin : CORE_GEN\n NPU_CORE u_core(\n .clk(clk),\n .rst_n(rst_n),\n .data_in(core_input[i]),\n .data_out(core_output[i]),\n // 内存接口\n .mem_addr(mem_addr[i]),\n .mem_wr_data(mem_wr_data[i]),\n .mem_rd_data(mem_rd_data[i]),\n .mem_read_en(mem_read_en[i]),\n .mem_write_en(mem_write_en[i])\n );\n end\n endgenerate\n\n // 内存控制器实例\n MEM_CTRL u_mem_ctrl(\n .clk(clk),\n .rst_n(rst_n),\n // 核接口\n .mem_addr(mem_addr),\n .mem_wr_data(mem_wr_data),\n .mem_rd_data(mem_rd_data),\n .mem_read_en(mem_read_en),\n .mem_write_en(mem_write_en),\n // DDR接口\n .ddr_data(ddr_data)\n );\n\n // 中断处理逻辑\n always @(posedge clk or negedge rst_n) begin\n if (!rst_n) begin\n status <= 32'h0;\n end else begin\n status <= {interrupt, 27'h0, |core_status}; // 状态寄存器[31] = 中断状态\n end\n end\n\n // PCIe数据分发\n always @(*) begin\n for (int j=0; j<CORES; j=j+1) begin\n core_input[j] = pcie_data; // 简单广播\n end\n end\n[TASK_END]\n```", "inference_time": "2025-08-21 04-27-16"}, "editdistance_info": {"edit_distance": 23.0248, "calculate_time": "2025-08-21 04:27:16", "true_code_clean": "module NPU_SOC #(\n parameter CORES = 4\n)(\n input wire clk,\n input wire rst_n,\n input wire [127:0] pcie_data,\n output reg [127:0] ddr_data,\n input wire interrupt,\n output reg [31:0] status\n);\nwire [127:0] noc_data [0:CORES-1];\nwire [31:0] noc_ctrl [0:CORES-1];\nnpu_controller u_controller(\n .clk(clk),\n .rst_n(rst_n),\n .cores_status(noc_ctrl),\n .global_config(pcie_data[95:0]),\n .interrupt(interrupt)\n);\ngenerate\nfor (genvar i = 0; i < CORES; i = i + 1) begin\n npu_core #(\n .CORE_ID(i)\n ) u_core (\n .clk(clk),\n .rst_n(rst_n),\n .noc_in(noc_data[i]),\n .noc_out(noc_data[(i+1)%CORES]),\n .ctrl_in(noc_ctrl[i]),\n .ddr_interface(ddr_data)\n );\nend\nendgenerate\nperformance_monitor u_monitor(\n .clk(clk),\n .cores_active(noc_ctrl),\n .ddr_usage(ddr_data[127:96]),\n .power_status(status[31:16])\n);\nendmodule", "predict_code_clean": " reg [31:0] core_status [0:CORES-1];\n wire [127:0] core_input [0:CORES-1];\n wire [127:0] core_output [0:CORES-1];\n reg [31:0] mem_addr [0:CORES-1];\n reg [127:0] mem_wr_data [0:CORES-1];\n wire [127:0] mem_rd_data [0:CORES-1];\n reg mem_read_en [0:CORES-1];\n reg mem_write_en [0:CORES-1];\n generate\n genvar i;\n for (i=0; i<CORES; i=i+1) begin : CORE_GEN\n NPU_CORE u_core(\n .clk(clk),\n .rst_n(rst_n),\n .data_in(core_input[i]),\n .data_out(core_output[i]),\n .mem_addr(mem_addr[i]),\n .mem_wr_data(mem_wr_data[i]),\n .mem_rd_data(mem_rd_data[i]),\n .mem_read_en(mem_read_en[i]),\n .mem_write_en(mem_write_en[i])\n );\n end\n endgenerate\n MEM_CTRL u_mem_ctrl(\n .clk(clk),\n .rst_n(rst_n),\n .mem_addr(mem_addr),\n .mem_wr_data(mem_wr_data),\n .mem_rd_data(mem_rd_data),\n .mem_read_en(mem_read_en),\n .mem_write_en(mem_write_en),\n .ddr_data(ddr_data)\n );\n always @(posedge clk or negedge rst_n) begin\n if (!rst_n) begin\n status <= 32'h0;\n end else begin\n status <= {interrupt, 27'h0, |core_status}; \n end\n end\n always @(*) begin\n for (int j=0; j<CORES; j=j+1) begin\n core_input[j] = pcie_data; \n end\n end"}}
5
+ {"repo_name": "Mayoiuta", "file_name": "/Mayoiuta/hardware/rtl/memory/data_reorder.v", "inference_info": {"prefix_code": "", "suffix_code": "", "middle_code": "module Data_Reorder #(\n parameter CHANNELS = 64,\n parameter TILE_SIZE = 8\n)(\n input wire clk,\n input wire rst_n,\n input wire [127:0] mem_data,\n output reg [127:0] pe_data,\n input wire [1:0] data_format \n);\nreg [127:0] reorder_buffer [0:CHANNELS/TILE_SIZE-1][0:TILE_SIZE-1];\nalways @(posedge clk) begin\n case(data_format)\n 2'b00: \n for (int c = 0; c < CHANNELS; c += TILE_SIZE) begin\n for (int t = 0; t < TILE_SIZE; t++) begin\n reorder_buffer[c/TILE_SIZE][t] <= \n {mem_data[127:112], mem_data[95:80], \n mem_data[63:48], mem_data[31:16]};\n end\n end\n 2'b01: \n for (int h = 0; h < TILE_SIZE; h++) begin\n reorder_buffer[h%4][h/4] <= \n {mem_data[127:120], mem_data[95:88], \n mem_data[63:56], mem_data[31:24]};\n end\n 2'b10: \n pe_data <= mem_data; \n endcase\nend\nalways @(posedge clk) begin\n pe_data <= reorder_buffer[read_ptr];\n read_ptr <= (read_ptr == (CHANNELS/TILE_SIZE-1)) ? 0 : read_ptr + 1;\nend\nendmodule", "code_description": null, "fill_type": "CLASS_TYPE", "language_type": "verilog", "sub_task_type": null}, "context_code": [["/Mayoiuta/hardware/rtl/core/pe_array.v", "module PE_Array #(\n parameter DATA_WIDTH = 16,\n parameter ARRAY_SIZE = 8\n)(\n input wire clk,\n input wire rst_n,\n input wire [DATA_WIDTH-1:0] north_in [ARRAY_SIZE-1:0],\n input wire [DATA_WIDTH-1:0] west_in [ARRAY_SIZE-1:0],\n output wire [DATA_WIDTH-1:0] south_out[ARRAY_SIZE-1:0],\n output wire [DATA_WIDTH-1:0] east_out [ARRAY_SIZE-1:0],\n input wire [3:0] opcode,\n input wire start,\n output wire done\n);\n\nwire [DATA_WIDTH-1:0] pe_data_h [ARRAY_SIZE][ARRAY_SIZE];\nwire [DATA_WIDTH-1:0] pe_data_v [ARRAY_SIZE][ARRAY_SIZE];\n\ngenerate\nfor (genvar i = 0; i < ARRAY_SIZE; i = i + 1) begin : row_gen\n for (genvar j = 0; j < ARRAY_SIZE; j = j + 1) begin : col_gen\n Processing_Element #(\n .DATA_WIDTH(DATA_WIDTH)\n ) u_pe (\n .clk(clk),\n .rst_n(rst_n),\n .north_in(i == 0 ? north_in[j] : pe_data_v[i-1][j]),\n .west_in(j == 0 ? west_in[i] : pe_data_h[i][j-1]),\n .south_out(pe_data_v[i][j]),\n .east_out(pe_data_h[i][j]),\n .opcode(opcode),\n .start(start),\n .done(done)\n );\n end\nend\nendgenerate\n\nassign south_out = pe_data_v[ARRAY_SIZE-1];\nassign east_out = pe_data_h[ARRAY_SIZE][ARRAY_SIZE-1];\n\nendmodule\n\nmodule Processing_Element #(\n parameter DATA_WIDTH = 16\n)(\n input wire clk,\n input wire rst_n,\n input wire [DATA_WIDTH-1:0] north_in,\n input wire [DATA_WIDTH-1:0] west_in,\n output reg [DATA_WIDTH-1:0] south_out,\n output reg [DATA_WIDTH-1:0] east_out,\n input wire [3:0] opcode,\n input wire start,\n output reg done\n);\n\nreg [DATA_WIDTH-1:0] accumulator;\nreg [DATA_WIDTH-1:0] weight_reg;\n\nalways @(posedge clk or negedge rst_n) begin\n if (!rst_n) begin\n accumulator <= 0;\n weight_reg <= 0;\n done <= 0;\n end else begin\n case(opcode)\n 4'h1: begin\n weight_reg <= west_in;\n done <= 1;\n end\n 4'h2: begin\n accumulator <= accumulator + (north_in * weight_reg);\n done <= 1;\n end\n 4'h3: begin\n south_out <= north_in;\n east_out <= west_in;\n done <= 1;\n end\n default: done <= 0;\n endcase\n end\nend\n\nendmodule"], ["/Mayoiuta/hardware/rtl/core/conv_engine.v", "module Conv_Engine #(\n parameter KERNEL_SIZE = 3,\n parameter STRIDE = 1,\n parameter PAD = 1\n)(\n input wire clk,\n input wire rst_n,\n input wire [7:0] feature_map [0:31][0:31], // 32x32输入\n input wire [7:0] weight [0:2][0:2], // 3x3卷积核\n output reg [15:0] conv_result [0:30][0:30] // 输出特征图\n);\n\n// 滑动窗口生成器\nreg [7:0] window_buffer [0:2][0:2];\nalways @(posedge clk) begin\n for (int i = 0; i <= 30; i++) begin\n for (int j = 0; j <= 30; j++) begin\n // 窗口滑动控制\n if (j == 0) begin\n window_buffer[0][0] <= (i > 0) ? feature_map[i-1][j+0] : 0;\n window_buffer[1][0] <= feature_map[i][j+0];\n window_buffer[2][0] <= (i < 31) ? feature_map[i+1][j+0] : 0;\n end else begin\n window_buffer[0][j%3] <= window_buffer[0][(j-1)%3];\n window_buffer[1][j%3] <= window_buffer[1][(j-1)%3];\n window_buffer[2][j%3] <= window_buffer[2][(j-1)%3];\n end\n \n // 卷积计算\n if (j >= 2) begin\n conv_result[i][j-2] <= \n (window_buffer[0][0] * weight[0][0]) +\n (window_buffer[0][1] * weight[0][1]) +\n (window_buffer[0][2] * weight[0][2]) +\n (window_buffer[1][0] * weight[1][0]) +\n (window_buffer[1][1] * weight[1][1]) +\n (window_buffer[1][2] * weight[1][2]) +\n (window_buffer[2][0] * weight[2][0]) +\n (window_buffer[2][1] * weight[2][1]) +\n (window_buffer[2][2] * weight[2][2]);\n end\n end\n end\nend\n\nendmodule"], ["/Mayoiuta/hardware/rtl/power/dvfs_ctrl.v", "module DVFS_Controller #(\n parameter VOLTAGE_LEVELS = 4,\n parameter FREQ_LEVELS = 4\n)(\n input wire clk,\n input wire rst_n,\n input wire [7:0] workload, // 0-255工作量指示\n output reg [1:0] voltage_level, // 00:0.8V ... 11:1.2V\n output reg [1:0] freq_level // 00:500MHz ... 11:1.2GHz\n);\n\nreg [15:0] history_buffer [0:7];\nalways @(posedge clk) begin\n history_buffer <= {history_buffer[6:0], workload};\nend\n\n// 移动平均计算\nwire [10:0] moving_avg;\nassign moving_avg = (history_buffer[0] + history_buffer[1] + history_buffer[2] + \n history_buffer[3] + history_buffer[4] + history_buffer[5] +\n history_buffer[6] + history_buffer[7]) >> 3;\n\n// 调节策略\nalways @(*) begin\n case(moving_avg)\n 0-50: {voltage_level, freq_level} = 4'b00_00;\n 51-100: {voltage_level, freq_level} = 4'b01_01;\n 101-150:{voltage_level, freq_level} = 4'b10_10;\n default:{voltage_level, freq_level} = 4'b11_11;\n endcase\nend\n\nendmodule"], ["/Mayoiuta/hardware/rtl/sparse/sparse_engine.v", "module Sparse_Engine #(\n parameter SPARSE_THRESH = 0.3\n)(\n input wire clk,\n input wire rst_n,\n input wire [7:0] activation [0:31][0:31],\n input wire [7:0] weight [0:31][0:31],\n output reg [15:0] sparse_result,\n output reg sparse_valid\n);\n\n// 零值检测逻辑\nreg [31:0] zero_count;\nalways @(posedge clk) begin\n zero_count = 0;\n for (int i = 0; i < 32; i++) begin\n for (int j = 0; j < 32; j++) begin\n if (activation[i][j] == 0 || weight[i][j] == 0) begin\n zero_count <= zero_count + 1;\n end\n end\n end\n \n // 稀疏度判断\n if (zero_count > (32*32*SPARSE_THRESH)) begin\n sparse_valid <= 1'b1;\n // 触发稀疏计算模式\n sparse_result <= activation * weight; // 使用专用稀疏乘法器\n end else begin\n sparse_valid <= 1'b0;\n end\nend\n\n// 稀疏矩阵压缩格式处理\nwire [7:0] compressed_act;\nwire [4:0] act_idx;\nsparse_encoder encoder(\n .in_data(activation),\n .compressed(compressed_act),\n .index(act_idx)\n);\n\nwire [7:0] compressed_weight;\nwire [4:0] weight_idx;\nsparse_encoder encoder_w(\n .in_data(weight),\n .compressed(compressed_weight),\n .index(weight_idx)\n);\n\n// 稀疏矩阵乘法核心\nalways @(posedge clk) begin\n if (act_idx == weight_idx) begin\n sparse_result <= compressed_act * compressed_weight;\n end\nend\n\nendmodule"], ["/Mayoiuta/hardware/rtl/core/adaptive_pe.v", "module Adaptive_PE #(\n parameter INT8_MODE = 1,\n parameter FP16_MODE = 0\n)(\n input wire clk,\n input wire rst_n,\n input wire [3:0] precision_mode,\n input wire [31:0] din_a,\n input wire [31:0] din_b,\n output reg [31:0] dout\n);\n\n// 多精度计算单元\nalways @(posedge clk) begin\n if (!rst_n) dout <= 0;\n else begin\n case(precision_mode)\n 4'b0001: // INT8模式\n dout <= $signed(din_a[7:0]) * $signed(din_b[7:0]);\n 4'b0010: // FP16模式\n dout <= fp16_mult(din_a[15:0], din_b[15:0]);\n 4'b0100: // BFLOAT16\n dout <= {din_a[31:16], 16'b0} * {din_b[31:16], 16'b0};\n default: // INT16\n dout <= $signed(din_a) * $signed(din_b);\n endcase\n end\nend\n\n// IEEE 754半精度浮点乘法实现\nfunction [15:0] fp16_mult;\n input [15:0] a, b;\n begin\n fp16_mult[15] = a[15] ^ b[15];\n // 指数处理\n if (a[14:10] == 0 || b[14:10] == 0) \n fp16_mult[14:10] = 0;\n else \n fp16_mult[14:10] = a[14:10] + b[14:10] - 15;\n // 尾数处理\n fp16_mult[9:0] = (a[9:0] * b[9:0]) >> 10;\n end\nendfunction\n\nendmodule"], ["/Mayoiuta/hardware/rtl/top/npu_soc.v", "module NPU_SOC #(\n parameter CORES = 4\n)(\n input wire clk,\n input wire rst_n,\n // 外部接口\n input wire [127:0] pcie_data,\n output reg [127:0] ddr_data,\n // 控制信号\n input wire interrupt,\n output reg [31:0] status\n);\n\n// 多核互连网络\nwire [127:0] noc_data [0:CORES-1];\nwire [31:0] noc_ctrl [0:CORES-1];\n\n// 主控制器\nnpu_controller u_controller(\n .clk(clk),\n .rst_n(rst_n),\n .cores_status(noc_ctrl),\n .global_config(pcie_data[95:0]),\n .interrupt(interrupt)\n);\n\n// 计算核心阵列\ngenerate\nfor (genvar i = 0; i < CORES; i = i + 1) begin\n npu_core #(\n .CORE_ID(i)\n ) u_core (\n .clk(clk),\n .rst_n(rst_n),\n .noc_in(noc_data[i]),\n .noc_out(noc_data[(i+1)%CORES]),\n .ctrl_in(noc_ctrl[i]),\n .ddr_interface(ddr_data)\n );\nend\nendgenerate\n\n// 性能监控\nperformance_monitor u_monitor(\n .clk(clk),\n .cores_active(noc_ctrl),\n .ddr_usage(ddr_data[127:96]),\n .power_status(status[31:16])\n);\n\nendmodule"], ["/Mayoiuta/hardware/rtl/memory/mem_ctl.v", "module Memory_Controller #(\n parameter ADDR_WIDTH = 32,\n parameter DATA_WIDTH = 256,\n parameter BANK_NUM = 8\n)(\n input wire clk,\n input wire rst_n,\n // 主机接口\n input wire [ADDR_WIDTH-1:0] host_addr,\n input wire host_wr_en,\n input wire [DATA_WIDTH-1:0] host_wr_data,\n output reg [DATA_WIDTH-1:0] host_rd_data,\n // NPU接口\n input wire [ADDR_WIDTH-1:0] npu_addr,\n input wire npu_rd_en,\n output reg [DATA_WIDTH-1:0] npu_rd_data\n);\n\nreg [DATA_WIDTH-1:0] memory_bank [0:BANK_NUM-1][0:(1<<(ADDR_WIDTH-3))-1];\n\nalways @(posedge clk) begin\n if (host_wr_en) begin\n memory_bank[host_addr[2:0]][host_addr[ADDR_WIDTH-1:3]] <= host_wr_data;\n end\n host_rd_data <= memory_bank[host_addr[2:0]][host_addr[ADDR_WIDTH-1:3]];\n \n if (npu_rd_en) begin\n npu_rd_data <= memory_bank[npu_addr[2:0]][npu_addr[ADDR_WIDTH-1:3]];\n end\nend\n\n// ECC校验\necc_checker #(\n .DATA_WIDTH(DATA_WIDTH)\n) u_ecc (\n .data_in(host_wr_data),\n .data_out(host_rd_data),\n .syndrome()\n);\n\nendmodule"], ["/Mayoiuta/hardware/rtl/control/shape_adaptor.v", "module Shape_Adaptor #(\n parameter MAX_DIM = 4096\n)(\n input wire clk,\n input wire rst_n,\n input wire [15:0] in_height,\n input wire [15:0] in_width,\n input wire [15:0] kernel_h,\n input wire [15:0] kernel_w,\n output reg [15:0] out_height,\n output reg [15:0] out_width,\n output reg pad_enable\n);\n\n// 动态形状计算\nalways @(posedge clk) begin\n // 输出尺寸计算\n out_height <= (in_height + 2*PAD - kernel_h) / STRIDE + 1;\n out_width <= (in_width + 2*PAD - kernel_w) / STRIDE + 1;\n \n // 自动填充检测\n pad_enable <= ((in_height % STRIDE != 0) || \n (in_width % STRIDE != 0)) ? 1'b1 : 1'b0;\n \n // 边界保护\n if (out_height > MAX_DIM || out_width > MAX_DIM) begin\n $display(\"Error: Output dimension exceeds maximum limit!\");\n out_height <= MAX_DIM;\n out_width <= MAX_DIM;\n end\nend\n\n// 运行时配置接口\ntask configure(\n input [15:0] new_stride,\n input [15:0] new_pad\n);\n STRIDE = new_stride;\n PAD = new_pad;\nendtask\n\nendmodule"]], "task_instance_info": {"created_time": "2025-08-21 04:26:38", "created_task_model": "DeepSeek-R1", "class_skeleton": "module Data_Reorder #(\n parameter CHANNELS = 64,\n parameter TILE_SIZE = 8\n)(\n input wire clk,\n input wire rst_n,\n input wire [127:0] mem_data,\n output reg [127:0] pe_data,\n input wire [1:0] data_format // 0:NCHW 1:NHWC 2:Blocked\n) ; endmodule", "code_description": "This code segment functions to: Dynamically restructure multi-channel data streams based on format specifications and maintain buffer sequencing for output delivery. It implements format-specific bit-field reorganization patterns while managing circular buffer addressing for subsequent data retrieval."}, "inference_content": {"inference_model": "DeepSeek-R1", "inference_result": "```verilog\n[TASK_BEGIN]\nmodule Data_Reorder #(\n parameter CHANNELS = 64,\n parameter TILE_SIZE = 8\n)(\n input wire clk,\n input wire rst_n,\n input wire [127:0] mem_data,\n output reg [127:0] pe_data,\n input wire [1:0] data_format // 0:NCHW 1:NHWC 2:Blocked\n);\n \n always @(*) begin\n case(data_format)\n 2'b00: // NCHW format\n pe_data = mem_data;\n 2'b01: // NHWC format - channel last\n pe_data = {mem_data[127:96], mem_data[95:64], mem_data[63:32], mem_data[31:0]};\n 2'b10: // Blocked format - tile-based reordering\n pe_data = {mem_data[63:0], mem_data[127:64]};\n default:\n pe_data = 128'b0;\n endcase\n end\n\nendmodule\n[TASK_END]\n```", "inference_time": "2025-08-21 04-27-29"}, "editdistance_info": {"edit_distance": 39.418, "calculate_time": "2025-08-21 04:27:29", "true_code_clean": "module Data_Reorder #(\n parameter CHANNELS = 64,\n parameter TILE_SIZE = 8\n)(\n input wire clk,\n input wire rst_n,\n input wire [127:0] mem_data,\n output reg [127:0] pe_data,\n input wire [1:0] data_format \n);\nreg [127:0] reorder_buffer [0:CHANNELS/TILE_SIZE-1][0:TILE_SIZE-1];\nalways @(posedge clk) begin\n case(data_format)\n 2'b00: \n for (int c = 0; c < CHANNELS; c += TILE_SIZE) begin\n for (int t = 0; t < TILE_SIZE; t++) begin\n reorder_buffer[c/TILE_SIZE][t] <= \n {mem_data[127:112], mem_data[95:80], \n mem_data[63:48], mem_data[31:16]};\n end\n end\n 2'b01: \n for (int h = 0; h < TILE_SIZE; h++) begin\n reorder_buffer[h%4][h/4] <= \n {mem_data[127:120], mem_data[95:88], \n mem_data[63:56], mem_data[31:24]};\n end\n 2'b10: \n pe_data <= mem_data; \n endcase\nend\nalways @(posedge clk) begin\n pe_data <= reorder_buffer[read_ptr];\n read_ptr <= (read_ptr == (CHANNELS/TILE_SIZE-1)) ? 0 : read_ptr + 1;\nend\nendmodule", "predict_code_clean": "module Data_Reorder #(\n parameter CHANNELS = 64,\n parameter TILE_SIZE = 8\n)(\n input wire clk,\n input wire rst_n,\n input wire [127:0] mem_data,\n output reg [127:0] pe_data,\n input wire [1:0] data_format \n);\n always @(*) begin\n case(data_format)\n 2'b00: \n pe_data = mem_data;\n 2'b01: \n pe_data = {mem_data[127:96], mem_data[95:64], mem_data[63:32], mem_data[31:0]};\n 2'b10: \n pe_data = {mem_data[63:0], mem_data[127:64]};\n default:\n pe_data = 128'b0;\n endcase\n end\nendmodule"}}
verilog/z80-open-silicon_class_bench.jsonl ADDED
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