Datasets:
Formats:
csv
Size:
1K - 10K
ArXiv:
Tags:
electronic-design-automation
chip-placement
physical-design
ppa-prediction
timing-analysis
graph-neural-networks
License:
Add ICCAD 2026 acceptance and DOI
Browse files
README.md
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- graph-neural-networks
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- dreamplace
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- openroad
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configs:
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- config_name: default
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data_files:
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# PPAPlace-5000
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**The official training dataset for _PPAPlace: Differentiable Cross-Stage
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Objectives for Chip Placement Optimization_
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[
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| [Download files](https://huggingface.co/datasets/ValleyC/PPAPlace-5000/tree/main)
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| [Citation](#citation)
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| Placements per circuit | **500** |
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| Placement representation | Complete mixed-size DEF |
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| Post-GRT targets | WNS, TNS, total power, core area |
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| Compressed download | 9,096,824,559 bytes (**8.47 GiB**) |
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| Certified source payload | 198,591,827,060 bytes (**184.95 GiB**) |
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## Citation
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Please cite both the
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```bibtex
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@
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title
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author
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}
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@dataset{chen2026ppaplace5000,
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url = {https://huggingface.co/datasets/ValleyC/PPAPlace-5000}
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}
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```
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When a public proceedings, DOI, or preprint record becomes available, use that
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bibliographic record for the manuscript citation.
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- graph-neural-networks
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- dreamplace
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- openroad
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- iccad-2026
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configs:
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- config_name: default
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data_files:
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# PPAPlace-5000
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**The official training dataset for _PPAPlace: Differentiable Cross-Stage
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Objectives for Chip Placement Optimization_, accepted at the 2026 IEEE/ACM
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International Conference on Computer-Aided Design (ICCAD 2026), by Ruogu Chen
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and Jie Han of the University of Alberta.**
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[Accepted ICCAD 2026 paper](https://doi.org/10.1145/3831252.3834172)
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| [PPAPlace code and reproduction workflow](https://github.com/ValleyC/PPAPlace)
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| [Download files](https://huggingface.co/datasets/ValleyC/PPAPlace-5000/tree/main)
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| [Citation](#citation)
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| Placements per circuit | **500** |
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| Placement representation | Complete mixed-size DEF |
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| Post-GRT targets | WNS, TNS, total power, core area |
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| Paper | Accepted at **ICCAD 2026** |
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| Paper DOI | [`10.1145/3831252.3834172`](https://doi.org/10.1145/3831252.3834172) |
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| Compressed download | 9,096,824,559 bytes (**8.47 GiB**) |
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| Certified source payload | 198,591,827,060 bytes (**184.95 GiB**) |
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## Citation
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Please cite both the accepted ICCAD 2026 paper and this dataset:
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```bibtex
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@inproceedings{chen2026ppaplace,
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title = {{PPAPlace}: Differentiable Cross-Stage Objectives for Chip Placement Optimization},
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author = {Chen, Ruogu and Han, Jie},
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booktitle = {2026 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)},
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address = {San Jose, CA, USA},
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year = {2026},
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doi = {10.1145/3831252.3834172},
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url = {https://doi.org/10.1145/3831252.3834172}
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}
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@dataset{chen2026ppaplace5000,
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url = {https://huggingface.co/datasets/ValleyC/PPAPlace-5000}
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}
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```
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