Upload 42 files

README.md

@@ -1,3 +1,77 @@
 ---
-license: cc-by-4.0
+pretty_name: PPAPlace Exact-5000 Training Dataset
+license: other
+size_categories:
+- 1K<n<10K
+tags:
+- electronic-design-automation
+- chip-placement
+- physical-design
+- dreamplace
+- openroad
 ---
+
+# PPAPlace Exact-5000 Training Dataset
+
+This release contains the frozen training corpus used by PPAPlace: exactly
+5,000 distinct mixed-size DREAMPlace placements across ten ChiPBench circuits,
+with one post-global-routing OpenROAD label JSON for every DEF.
+
+## Contents
+
+| Circuit | DEFs | Labels | Compressed size | SHA-256 |
+| --- | ---: | ---: | ---: | --- |
+| `bp_be12` | 500 | 500 | 0.20 GiB | `2f102b2128bbf8dfc846d2b2e087c48f21f07bebc471b62ab716d11a8ff4d27b` |
+| `bp_fe` | 500 | 500 | 0.17 GiB | `b9ca630ff311cc2925247e27a80e46fbebf786f7364cc5840e177548b757e933` |
+| `bp_multi` | 500 | 500 | 0.90 GiB | `23071960c668e6d2b0f91f77bcfa5ce8bb335650c46589baf19e3c87c09927b6` |
+| `dft68` | 500 | 500 | 0.22 GiB | `fac0d1c1486100ef81b8ccf986b20a44948192e73a62821af7885fcc9becf102` |
+| `ethernet` | 500 | 500 | 0.18 GiB | `343b8d2a8ea0284aa7ebca570d1043a300614499d9a3420f5bbe704db8e1786b` |
+| `isa_npu` | 500 | 500 | 4.97 GiB | `f9e2ee8b04818c3a3f00a97d6239106494a97d76b742769f6559c43c0bc8152e` |
+| `mor1kx` | 500 | 500 | 0.44 GiB | `cef3034871f596386fa5a1e003a2e51d3e2b5a150cabf6f585bcf1a3046a407a` |
+| `or1200` | 500 | 500 | 0.14 GiB | `b7c7d025b41b4029f568a498455e46c5464f993fb92bfe6ac14404198ba40009` |
+| `swerv_wrapper43` | 500 | 500 | 0.54 GiB | `c1b0cf03640b2297bddf698bc82888cbeec6703c05983f2518bae4e02598f938` |
+| `vga_lcd` | 500 | 500 | 0.70 GiB | `234ee1dd04529b3c25c9fc41846ae3cec6c202820eb87b77ada877d17ebaeb53` |
+
+The uncompressed certified payload is
+198,591,827,060 bytes. `samples.csv` and
+`samples.jsonl` provide one row per pair, including archive member paths,
+cryptographic hashes, PPA labels, and the DREAMPlace hyperparameters.
+
+Each circuit archive contains only its 500 certified `*_final.def` files and
+500 matching `grt_jsons/*_final_grt.json` files. Generation candidates, failed
+runs, flow scratch, and machine-specific paths are intentionally excluded.
+
+## Labels
+
+- `wns`: `globalroute__timing__setup__ws`
+- `tns`: `globalroute__timing__setup__tns`
+- `power`: `globalroute__power__total`
+- `area`: `globalroute__design__core__area`
+
+## Verification
+
+```bash
+sha256sum -c SHA256SUMS
+tar --use-compress-program=unzstd -xf data/bp_fe.tar.zst
+```
+
+`metadata/certificate.json` is the immutable exact-5,000 certificate.
+`metadata/snapshot_artifacts.json` records the SHA-256 and byte count of every
+DEF and label. Every archive was decompressed after creation and every member
+was compared byte-for-byte with that inventory.
+
+Source aggregate SHA-256:
+`f51ba91e7da337518c4f0c00738157a1d51bb22ce094ff15ce7e6de8b4a1eea4`.
+
+## Required benchmark files
+
+The archives contain generated placements and labels. Obtain the corresponding
+ChiPBench LEF/design files separately from the upstream ChiPBench project and
+follow the PPAPlace repository documentation to train or regenerate features.
+
+## License and provenance
+
+This upload uses `license: other` conservatively. Review
+`THIRD_PARTY_NOTICES.md` and select an appropriate release license before
+making the dataset public. Generated files derive from ChiPBench benchmark
+designs and were produced with DREAMPlace and the ChiPBench/OpenROAD flow.

READY_TO_UPLOAD.json

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+}

SHA256SUMS

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THIRD_PARTY_NOTICES.md

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+# Third-party notices
+
+The PPAPlace training corpus contains generated placement DEFs and metrics
+derived from ChiPBench benchmark inputs. ChiPBench's top-level license is
+reproduced below. Individual benchmark designs may carry additional upstream
+notices in the ChiPBench source repository. This package does not replace or
+supersede those notices.
+
+Before a public upload, the publisher should confirm the intended PPAPlace
+dataset license and the redistribution terms of all constituent benchmark
+designs. For that reason, the prepared Hugging Face card uses `license: other`
+instead of asserting a new license grant.
+
+## ChiPBench top-level license
+
+```text
+BSD 3-Clause License
+
+Copyright (c) 2024, ZhaojieTu
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+   list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice,
+   this list of conditions and the following disclaimer in the documentation
+   and/or other materials provided with the distribution.
+
+3. Neither the name of the copyright holder nor the names of its
+   contributors may be used to endorse or promote products derived from
+   this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+```

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metadata/dreamplace_commit.txt

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+      "circuit": "swerv_wrapper43",
+      "content_audit_sha256": "d723462bcd0c7a5eea86121d9ab6015f690f1d3d6f50f69b27a7f9d5914516dd",
+      "count": 500,
+      "filename_sha256": "e653bd786c735d779b7b4aa34e85da5aa0b7ada5ec138fa230b4925e3ea5f98d",
+      "label_unique_counts": {
+        "Area": 1,
+        "Power": 495,
+        "TNS": 500,
+        "WNS": 500
+      },
+      "live_source_count_at_seal": 500,
+      "live_source_filename_sha256_at_seal": "e653bd786c735d779b7b4aa34e85da5aa0b7ada5ec138fa230b4925e3ea5f98d",
+      "report_pair_source": "live_current",
+      "tensor_audit_sha256": "fb7c78234b32f02c12de9cc38abda8055915f52638a92f9683023097f4b25950",
+      "unique_tensor_hash_count": 500
+    },
+    {
+      "assertions": {
+        "audited_inventory_still_present_in_append_only_source": true,
+        "content_all_checks": true,
+        "content_errors_empty": true,
+        "content_pair_inventory": true,
+        "content_passed": true,
+        "content_snapshot_stable": true,
+        "content_tensor_count_signature_match": true,
+        "content_tensor_labels_match": true,
+        "macro_mobility_direct": true,
+        "macro_mobility_tolerance_aware": true,
+        "tensor_all_checks": true,
+        "tensor_errors_empty": true,
+        "tensor_passed": true,
+        "tensor_sample_inventory": true,
+        "tensor_snapshot_stable": true,
+        "tensor_unique_count": true
+      },
+      "audited_inventory_still_present": true,
+      "circuit": "vga_lcd",
+      "content_audit_sha256": "622358ed7d1566ec99bad45a11161f49ceb17ddbaadf1252df6b0a601b94fa83",
+      "count": 500,
+      "filename_sha256": "5cc79daf95cc9eff65612f7c39d6243e35cb44d2367d6370683c47b7b35935ad",
+      "label_unique_counts": {
+        "Area": 1,
+        "Power": 493,
+        "TNS": 500,
+        "WNS": 500
+      },
+      "live_source_count_at_seal": 500,
+      "live_source_filename_sha256_at_seal": "5cc79daf95cc9eff65612f7c39d6243e35cb44d2367d6370683c47b7b35935ad",
+      "report_pair_source": "live_current",
+      "tensor_audit_sha256": "341993b19a8e0cc1d4a61152cf318cb0d2e3951d158e9bc5c8b44a9e18fc8c7f",
+      "unique_tensor_hash_count": 500
+    },
+    {
+      "assertions": {
+        "audited_inventory_still_present_in_append_only_source": true,
+        "content_all_checks": true,
+        "content_errors_empty": true,
+        "content_pair_inventory": true,
+        "content_passed": true,
+        "content_snapshot_stable": true,
+        "content_tensor_count_signature_match": true,
+        "content_tensor_labels_match": true,
+        "macro_mobility_direct": true,
+        "macro_mobility_tolerance_aware": true,
+        "tensor_all_checks": true,
+        "tensor_errors_empty": true,
+        "tensor_passed": true,
+        "tensor_sample_inventory": true,
+        "tensor_snapshot_stable": true,
+        "tensor_unique_count": true
+      },
+      "audited_inventory_still_present": true,
+      "circuit": "ethernet",
+      "content_audit_sha256": "cf368ce8e473b54e6479e15398f7b971be493e64fc98d3cc178a87f7b11cedc9",
+      "count": 500,
+      "filename_sha256": "7494b83b5b89a01792ec2b6c1aa9c54237d46a346a8f849ee4461c755037fa22",
+      "label_unique_counts": {
+        "Area": 1,
+        "Power": 481,
+        "TNS": 500,
+        "WNS": 498
+      },
+      "live_source_count_at_seal": 500,
+      "live_source_filename_sha256_at_seal": "7494b83b5b89a01792ec2b6c1aa9c54237d46a346a8f849ee4461c755037fa22",
+      "report_pair_source": "live_current",
+      "tensor_audit_sha256": "589b36e7c23cf28c43579bd8cb19e306ada9f5d99826796f644fd8cbeb452606",
+      "unique_tensor_hash_count": 500
+    },
+    {
+      "assertions": {
+        "audited_inventory_still_present_in_append_only_source": true,
+        "content_all_checks": true,
+        "content_errors_empty": true,
+        "content_pair_inventory": true,
+        "content_passed": true,
+        "content_snapshot_stable": true,
+        "content_tensor_count_signature_match": true,
+        "content_tensor_labels_match": true,
+        "macro_mobility_direct": true,
+        "macro_mobility_tolerance_aware": true,
+        "tensor_all_checks": true,
+        "tensor_errors_empty": true,
+        "tensor_passed": true,
+        "tensor_sample_inventory": true,
+        "tensor_snapshot_stable": true,
+        "tensor_unique_count": true
+      },
+      "audited_inventory_still_present": true,
+      "circuit": "dft68",
+      "content_audit_sha256": "693f51178a0e5498f101ca35dc02de2f5be7f488ef81a53f7b3f4b4f52df46fc",
+      "count": 500,
+      "filename_sha256": "05282d25ad89d704257001bd8cf1dd4bf844e72b0ecfb0194f33cc3a00af9914",
+      "label_unique_counts": {
+        "Area": 1,
+        "Power": 492,
+        "TNS": 499,
+        "WNS": 500
+      },
+      "live_source_count_at_seal": 500,
+      "live_source_filename_sha256_at_seal": "05282d25ad89d704257001bd8cf1dd4bf844e72b0ecfb0194f33cc3a00af9914",
+      "report_pair_source": "live_current",
+      "tensor_audit_sha256": "baf74cefc820c857f49c745e41c48cd88a5601fe9218b4b83b2da2415594330c",
+      "unique_tensor_hash_count": 500
+    },
+    {
+      "assertions": {
+        "audited_inventory_still_present_in_append_only_source": true,
+        "content_all_checks": true,
+        "content_errors_empty": true,
+        "content_pair_inventory": true,
+        "content_passed": true,
+        "content_snapshot_stable": true,
+        "content_tensor_count_signature_match": true,
+        "content_tensor_labels_match": true,
+        "macro_mobility_direct": true,
+        "macro_mobility_tolerance_aware": true,
+        "tensor_all_checks": true,
+        "tensor_errors_empty": true,
+        "tensor_passed": true,
+        "tensor_sample_inventory": true,
+        "tensor_snapshot_stable": true,
+        "tensor_unique_count": true
+      },
+      "audited_inventory_still_present": true,
+      "circuit": "mor1kx",
+      "content_audit_sha256": "8ce4006a061e1616f0ea83b40dfd8094a639b2085b9bd14d6e4cfa2632c22a91",
+      "count": 500,
+      "filename_sha256": "9fa0f34b725f318b1d3ac163a7a2bcf80de170a1ae9ccf2a9cc718ca38aa380f",
+      "label_unique_counts": {
+        "Area": 1,
+        "Power": 489,
+        "TNS": 496,
+        "WNS": 497
+      },
+      "live_source_count_at_seal": 500,
+      "live_source_filename_sha256_at_seal": "9fa0f34b725f318b1d3ac163a7a2bcf80de170a1ae9ccf2a9cc718ca38aa380f",
+      "report_pair_source": "live_current",
+      "tensor_audit_sha256": "294bb838b33a1d5779d3d94aabf4003db0b8fe1e61a02aac0e3380ba3a95cc31",
+      "unique_tensor_hash_count": 500
+    }
+  ],
+  "expected_total": 5000,
+  "generated_at_utc": "2026-08-18T14:31:30.448647+00:00",
+  "observed_total": 5000,
+  "passed": true,
+  "requirements": {
+    "all_content_audits_pass": true,
+    "all_macros_move_across_samples": true,
+    "all_macros_move_tolerance_aware_across_samples": true,
+    "all_model_input_tensors_unique_within_circuit": true,
+    "all_tensor_audits_pass": true,
+    "audited_inventories_still_present_in_append_only_sources": true,
+    "content_tensor_labels_identical": true,
+    "ppa_vectors_not_collapsed": true,
+    "source_filename_snapshots_stable_during_each_audit": true,
+    "ten_manuscript_training_circuits": true
+  },
+  "schema_version": 1,
+  "scope": "immutable common content+production-tensor audit frontier; live sources are append-only and may already be ahead"
+}

metadata/exact5000_independent_audit.json

@@ -0,0 +1,146 @@
+{
+  "assertion_count": 19,
+  "assertions": {
+    "all_macros_move_across_samples": true,
+    "all_model_input_tensors_unique": true,
+    "all_source_labels_reparsed": true,
+    "content_reports_pass": true,
+    "content_tensor_labels_identical": true,
+    "content_tensor_signatures_identical": true,
+    "expected_per_circuit_counts_exact": true,
+    "manifest_member_count_exact21": true,
+    "manifest_member_modes_0444": true,
+    "manifest_member_sha256_exact": true,
+    "manifest_member_sizes_exact": true,
+    "manifest_mode_0444": true,
+    "openroad_label_handoff_macros_fixed": true,
+    "seal_directory_mode_0555": true,
+    "source_content_tensor_labels_identical": true,
+    "summary_exact_total": true,
+    "summary_sha256_manifest_bound": true,
+    "ten_circuits_exact": true,
+    "tensor_reports_pass": true
+  },
+  "circuits": [
+    {
+      "all_macros_move": true,
+      "all_macros_move_tolerance_aware": true,
+      "circuit": "bp_fe",
+      "content_tensor_source_labels_identical": true,
+      "count": 500,
+      "fixed_openroad_handoff_verified": true,
+      "macro_count": 11,
+      "source_labels_reparsed": 500,
+      "unique_tensor_hash_count": 500
+    },
+    {
+      "all_macros_move": true,
+      "all_macros_move_tolerance_aware": true,
+      "circuit": "bp_be12",
+      "content_tensor_source_labels_identical": true,
+      "count": 500,
+      "fixed_openroad_handoff_verified": true,
+      "macro_count": 12,
+      "source_labels_reparsed": 500,
+      "unique_tensor_hash_count": 500
+    },
+    {
+      "all_macros_move": true,
+      "all_macros_move_tolerance_aware": true,
+      "circuit": "isa_npu",
+      "content_tensor_source_labels_identical": true,
+      "count": 500,
+      "fixed_openroad_handoff_verified": true,
+      "macro_count": 15,
+      "source_labels_reparsed": 500,
+      "unique_tensor_hash_count": 500
+    },
+    {
+      "all_macros_move": true,
+      "all_macros_move_tolerance_aware": true,
+      "circuit": "bp_multi",
+      "content_tensor_source_labels_identical": true,
+      "count": 500,
+      "fixed_openroad_handoff_verified": true,
+      "macro_count": 26,
+      "source_labels_reparsed": 500,
+      "unique_tensor_hash_count": 500
+    },
+    {
+      "all_macros_move": true,
+      "all_macros_move_tolerance_aware": true,
+      "circuit": "or1200",
+      "content_tensor_source_labels_identical": true,
+      "count": 500,
+      "fixed_openroad_handoff_verified": true,
+      "macro_count": 36,
+      "source_labels_reparsed": 500,
+      "unique_tensor_hash_count": 500
+    },
+    {
+      "all_macros_move": true,
+      "all_macros_move_tolerance_aware": true,
+      "circuit": "swerv_wrapper43",
+      "content_tensor_source_labels_identical": true,
+      "count": 500,
+      "fixed_openroad_handoff_verified": true,
+      "macro_count": 43,
+      "source_labels_reparsed": 500,
+      "unique_tensor_hash_count": 500
+    },
+    {
+      "all_macros_move": true,
+      "all_macros_move_tolerance_aware": true,
+      "circuit": "vga_lcd",
+      "content_tensor_source_labels_identical": true,
+      "count": 500,
+      "fixed_openroad_handoff_verified": true,
+      "macro_count": 62,
+      "source_labels_reparsed": 500,
+      "unique_tensor_hash_count": 500
+    },
+    {
+      "all_macros_move": true,
+      "all_macros_move_tolerance_aware": true,
+      "circuit": "ethernet",
+      "content_tensor_source_labels_identical": true,
+      "count": 500,
+      "fixed_openroad_handoff_verified": true,
+      "macro_count": 64,
+      "source_labels_reparsed": 500,
+      "unique_tensor_hash_count": 500
+    },
+    {
+      "all_macros_move": true,
+      "all_macros_move_tolerance_aware": true,
+      "circuit": "dft68",
+      "content_tensor_source_labels_identical": true,
+      "count": 500,
+      "fixed_openroad_handoff_verified": true,
+      "macro_count": 68,
+      "source_labels_reparsed": 500,
+      "unique_tensor_hash_count": 500
+    },
+    {
+      "all_macros_move": true,
+      "all_macros_move_tolerance_aware": true,
+      "circuit": "mor1kx",
+      "content_tensor_source_labels_identical": true,
+      "count": 500,
+      "fixed_openroad_handoff_verified": true,
+      "macro_count": 78,
+      "source_labels_reparsed": 500,
+      "unique_tensor_hash_count": 500
+    }
+  ],
+  "expected_total": 5000,
+  "generated_at_utc": "2026-08-18T14:31:45.596669+00:00",
+  "observed_total": 5000,
+  "passed": true,
+  "schema_version": 1,
+  "scope": "independent immutable exact5000 training frontier audit",
+  "seal": "/home/ruogu/experiments/ppaplace/reproduction/training_data/audit_snapshots/operator_training_common_frontier_exact5000_20260818T1431Z",
+  "seal_manifest_sha256": "5e0f1f2a429653bcae3c8adb0cfd6fbb30915a8b0b95eac51953e49a31de82f5",
+  "seal_summary_sha256": "e96541a266ecdcbd6ea0d4e689ebc2db50aca978f1b1aa6eb25b12a364a1b624",
+  "source_label_files_reparsed": 5000
+}

metadata/exact5000_second_replay.json

@@ -0,0 +1,146 @@
+{
+  "assertion_count": 19,
+  "assertions": {
+    "all_macros_move_across_samples": true,
+    "all_model_input_tensors_unique": true,
+    "all_source_labels_reparsed": true,
+    "content_reports_pass": true,
+    "content_tensor_labels_identical": true,
+    "content_tensor_signatures_identical": true,
+    "expected_per_circuit_counts_exact": true,
+    "manifest_member_count_exact21": true,
+    "manifest_member_modes_0444": true,
+    "manifest_member_sha256_exact": true,
+    "manifest_member_sizes_exact": true,
+    "manifest_mode_0444": true,
+    "openroad_label_handoff_macros_fixed": true,
+    "seal_directory_mode_0555": true,
+    "source_content_tensor_labels_identical": true,
+    "summary_exact_total": true,
+    "summary_sha256_manifest_bound": true,
+    "ten_circuits_exact": true,
+    "tensor_reports_pass": true
+  },
+  "circuits": [
+    {
+      "all_macros_move": true,
+      "all_macros_move_tolerance_aware": true,
+      "circuit": "bp_fe",
+      "content_tensor_source_labels_identical": true,
+      "count": 500,
+      "fixed_openroad_handoff_verified": true,
+      "macro_count": 11,
+      "source_labels_reparsed": 500,
+      "unique_tensor_hash_count": 500
+    },
+    {
+      "all_macros_move": true,
+      "all_macros_move_tolerance_aware": true,
+      "circuit": "bp_be12",
+      "content_tensor_source_labels_identical": true,
+      "count": 500,
+      "fixed_openroad_handoff_verified": true,
+      "macro_count": 12,
+      "source_labels_reparsed": 500,
+      "unique_tensor_hash_count": 500
+    },
+    {
+      "all_macros_move": true,
+      "all_macros_move_tolerance_aware": true,
+      "circuit": "isa_npu",
+      "content_tensor_source_labels_identical": true,
+      "count": 500,
+      "fixed_openroad_handoff_verified": true,
+      "macro_count": 15,
+      "source_labels_reparsed": 500,
+      "unique_tensor_hash_count": 500
+    },
+    {
+      "all_macros_move": true,
+      "all_macros_move_tolerance_aware": true,
+      "circuit": "bp_multi",
+      "content_tensor_source_labels_identical": true,
+      "count": 500,
+      "fixed_openroad_handoff_verified": true,
+      "macro_count": 26,
+      "source_labels_reparsed": 500,
+      "unique_tensor_hash_count": 500
+    },
+    {
+      "all_macros_move": true,
+      "all_macros_move_tolerance_aware": true,
+      "circuit": "or1200",
+      "content_tensor_source_labels_identical": true,
+      "count": 500,
+      "fixed_openroad_handoff_verified": true,
+      "macro_count": 36,
+      "source_labels_reparsed": 500,
+      "unique_tensor_hash_count": 500
+    },
+    {
+      "all_macros_move": true,
+      "all_macros_move_tolerance_aware": true,
+      "circuit": "swerv_wrapper43",
+      "content_tensor_source_labels_identical": true,
+      "count": 500,
+      "fixed_openroad_handoff_verified": true,
+      "macro_count": 43,
+      "source_labels_reparsed": 500,
+      "unique_tensor_hash_count": 500
+    },
+    {
+      "all_macros_move": true,
+      "all_macros_move_tolerance_aware": true,
+      "circuit": "vga_lcd",
+      "content_tensor_source_labels_identical": true,
+      "count": 500,
+      "fixed_openroad_handoff_verified": true,
+      "macro_count": 62,
+      "source_labels_reparsed": 500,
+      "unique_tensor_hash_count": 500
+    },
+    {
+      "all_macros_move": true,
+      "all_macros_move_tolerance_aware": true,
+      "circuit": "ethernet",
+      "content_tensor_source_labels_identical": true,
+      "count": 500,
+      "fixed_openroad_handoff_verified": true,
+      "macro_count": 64,
+      "source_labels_reparsed": 500,
+      "unique_tensor_hash_count": 500
+    },
+    {
+      "all_macros_move": true,
+      "all_macros_move_tolerance_aware": true,
+      "circuit": "dft68",
+      "content_tensor_source_labels_identical": true,
+      "count": 500,
+      "fixed_openroad_handoff_verified": true,
+      "macro_count": 68,
+      "source_labels_reparsed": 500,
+      "unique_tensor_hash_count": 500
+    },
+    {
+      "all_macros_move": true,
+      "all_macros_move_tolerance_aware": true,
+      "circuit": "mor1kx",
+      "content_tensor_source_labels_identical": true,
+      "count": 500,
+      "fixed_openroad_handoff_verified": true,
+      "macro_count": 78,
+      "source_labels_reparsed": 500,
+      "unique_tensor_hash_count": 500
+    }
+  ],
+  "expected_total": 5000,
+  "generated_at_utc": "2026-08-18T14:31:57.052117+00:00",
+  "observed_total": 5000,
+  "passed": true,
+  "schema_version": 1,
+  "scope": "independent immutable exact5000 training frontier audit",
+  "seal": "/home/ruogu/experiments/ppaplace/reproduction/training_data/audit_snapshots/operator_training_common_frontier_exact5000_20260818T1431Z",
+  "seal_manifest_sha256": "5e0f1f2a429653bcae3c8adb0cfd6fbb30915a8b0b95eac51953e49a31de82f5",
+  "seal_summary_sha256": "e96541a266ecdcbd6ea0d4e689ebc2db50aca978f1b1aa6eb25b12a364a1b624",
+  "source_label_files_reparsed": 5000
+}

metadata/ppaplace_commit.txt

@@ -0,0 +1 @@
+b2b013e60080722c86eff2e392b36866c66062dc

metadata/toolchain_and_hardware.txt

@@ -0,0 +1,48 @@
+CHIPBENCH_ROOT=/home/ruogu/NewDirection/baselines/ChiPBench
+v2.0-17198-g8396d0866 
+Yosys 0.47+116 (git sha1 4b3c03dab, clang++ 18.1.8 -fPIC -O3)
+KLayout 0.28.8
+2.0.1 NVIDIA RTX A6000
+
+Native DREAMPlace/ChiPBench/OpenROAD toolchain: PASS
+Architecture:                    x86_64
+CPU op-mode(s):                  32-bit, 64-bit
+Address sizes:                   46 bits physical, 48 bits virtual
+Byte Order:                      Little Endian
+CPU(s):                          80
+On-line CPU(s) list:             0-79
+Vendor ID:                       GenuineIntel
+Model name:                      Intel(R) Xeon(R) Gold 5218R CPU @ 2.10GHz
+CPU family:                      6
+Model:                           85
+Thread(s) per core:              2
+Core(s) per socket:              20
+Socket(s):                       2
+Stepping:                        7
+CPU max MHz:                     4000.0000
+CPU min MHz:                     800.0000
+BogoMIPS:                        4200.00
+Flags:                           fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cdp_l3 invpcid_single intel_ppin ssbd mba ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid cqm mpx rdt_a avx512f avx512dq rdseed adx smap clflushopt clwb intel_pt avx512cd avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local dtherm ida arat pln pts hwp hwp_act_window hwp_epp hwp_pkg_req pku ospke avx512_vnni md_clear flush_l1d arch_capabilities
+Virtualization:                  VT-x
+L1d cache:                       1.3 MiB (40 instances)
+L1i cache:                       1.3 MiB (40 instances)
+L2 cache:                        40 MiB (40 instances)
+L3 cache:                        55 MiB (2 instances)
+NUMA node(s):                    2
+NUMA node0 CPU(s):               0-19,40-59
+NUMA node1 CPU(s):               20-39,60-79
+Vulnerability Itlb multihit:     KVM: Mitigation: VMX disabled
+Vulnerability L1tf:              Not affected
+Vulnerability Mds:               Not affected
+Vulnerability Meltdown:          Not affected
+Vulnerability Mmio stale data:   Mitigation; Clear CPU buffers; SMT vulnerable
+Vulnerability Retbleed:          Mitigation; Enhanced IBRS
+Vulnerability Spec store bypass: Mitigation; Speculative Store Bypass disabled via prctl and seccomp
+Vulnerability Spectre v1:        Mitigation; usercopy/swapgs barriers and __user pointer sanitization
+Vulnerability Spectre v2:        Mitigation; Enhanced IBRS, IBPB conditional, RSB filling, PBRSB-eIBRS SW sequence
+Vulnerability Srbds:             Not affected
+Vulnerability Tsx async abort:   Mitigation; TSX disabled
+               total        used        free      shared  buff/cache   available
+Mem:            62Gi        16Gi        33Gi        40Mi        12Gi        45Gi
+Swap:          2.0Gi       1.0Gi       1.0Gi
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